ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 4 Channel, 200 ksps to 500 ksps, 12-Bit A/D Converter Check for Samples: ADC124S051 FEATURES DESCRIPTION • • • • The ADC124S051 is a low-power, four-channel CMOS 12-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC124S051 is fully specified over a sample rate range of 200 ksps to 500 ksps. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to four input signals at inputs IN1 through IN4. 1 2 Specified Over a Range of Sample Rates Four Input Channels Variable Power Management Single Power Supply with 2.7V - 5.25V Range KEY SPECIFICATIONS • • • • DNL: +0.7 / −0.4 LSB (typ) INL: ± 0.5 LSB (typ) SNR: 72.5 dB (typ) Power Consumption: – 3V Supply: 3.0 mW (typ) – 5V Supply: 10.0 mW (typ) The output serial data is straight binary, and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE and many common DSP serial interfaces. The ADC124S051 operates with a single supply that can range from +2.7V to +5.25V. Normal power consumption using a +3V or +5V supply is 3.0 mW and 10.0 mW, respectively. The power-down feature reduces the power consumption to just 0.14 µW using a +3V supply, or 0.32 µW using a +5V supply. APPLICATIONS • • • Portable Systems Remote Data Acquisition Instrumentation and Control Systems The ADC124S051 is packaged in a 10-lead VSSOP package. Operation over the industrial temperature range of −40°C to +85°C is ensured. Table 1. Pin-Compatible Alternatives by Resolution and Speed (1) Resolution (1) Specified for a Sample Rate Range of: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC124S021 ADC124S051 ADC122S101 10-bit ADC104S021 ADC104S051 ADC102S101 8-bit ADC084S021 ADC084S051 ADC082S101 All devices are fully pin and function compatible. Connection Diagram CS 1 VA 2 ADC124S051 10 SCLK 9 DOUT 8 DIN GND 3 IN4 4 7 IN1 IN3 5 6 IN2 10 Pin VSSOP Package See Package Number DGS 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com Block Diagram IN1 . . . MUX IN4 T/H 12-Bit SUCCESSIVE APPROXIMATION ADC VA CONTROL LOGIC CS GND GND SCLK DIN DOUT PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 4-7 IN1 to IN4 Analog inputs. These signals can range from 0V to VA. DIGITAL I/O 10 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 9 DOUT Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 8 DIN Digital data input. The ADC124S051's Control Register is loaded through this pin on rising edges of the SCLK pin. 1 CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. 2 VA Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with a 1 µF tantalum capacitor and a 0.1 µF ceramic monolithic capacitor located within 1 cm of the power pin. 3 GND POWER SUPPLY 2 The ground return for the supply and signals. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Supply Voltage VA −0.3V to VA +0.3V Voltage on Any Pin to GND Input Current at Any Pin (4) Package Input Current ±10 mA (4) ±20 mA Power Consumption at TA = 25°C See ESD Susceptibility (6) Human Body Model (5) 2500V Machine Model 250V Junction Temperature +150°C Storage Temperature −65°C to +150°C (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms. Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Range VA Supply Voltage +2.7V to +5.25V −0.3V to VA Digital Input Pins Voltage Range Clock Frequency 50 kHz to 16 MHz Analog Input Voltage (1) (2) 0V to VA Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = 0V, unless otherwise specified. Package Thermal Resistance (1) (1) Package θJA 10-lead VSSOP 190°C / W Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow temperature profiles are different for lead-free and non-lead-free packages. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 3 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ADC124S051 Converter Electrical Characteristics (1) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes 12 Bits ±0.5 ±1.1 LSB (max) +0.7 +1.3 LSB (max) −0.4 −1.0 LSB (min) +0.3 ±1.3 LSB (max) Channel to Channel Offset Error Match ±0.1 ±1.0 LSB (max) FSE Full Scale Error −0.5 ±1.5 LSB (max) FSEM Channel to Channel Full-Scale Error Match +0.1 ±1.0 LSB (max) INL Integral Non-Linearity DNL Differential Non-Linearity VOFF Offset Error OEM DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-Noise Plus Distortion Ratio VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS 72 69.2 dB (min) SNR Signal-to-Noise Ratio VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS 72.5 70.6 dB (min) THD Total Harmonic Distortion VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS −84 −75 dB (max) SFDR Spurious-Free Dynamic Range VA = +2.7 to 5.25V fIN = 40.2 kHz, −0.02 dBFS 86 76 dB (min) ENOB Effective Number of Bits VA = +2.7 to 5.25V 11.7 11.2 Bits (min) Channel-to-Channel Crosstalk VA = +5.25V fIN = 40.2 kHz −86 dB Intermodulation Distortion, Second Order Terms VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz −87 dB Intermodulation Distortion, Third Order Terms VA = +5.25V fa = 40.161 kHz, fb = 41.015 kHz −88 dB VA = +5V 11 MHz VA = +3V 8 MHz IMD FPBW -3 dB Full Power Bandwidth ANALOG INPUT CHARACTERISTICS VIN Input Range IDCL DC Leakage Current CINA Input Capacitance 0 to VA ±0.02 V ±1 µA (max) Track Mode 33 pF Hold Mode 3 pF DIGITAL INPUT CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage IIN Input Current CIND Digital Input Capacitance (1) (2) 4 VA = +5.25V 2.4 VA = +3.6V 2.1 V (min) 0.8 V (max) ±0.02 ±10 µA (max) 2 4 pF (max) VIN = 0V or VA V (min) Min/max specification limits are ensured by design, test, or statistical analysis. Tested limits are ensured to AOQL (Average Outgoing Quality Level). Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 Converter Electrical Characteristics(1) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Limits Typical (2) Units VA − 0.5 V (min) 0.4 V (max) 0.005 ±1 µA (max) 2 4 pF (max) DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage ISOURCE = 200 µA VA − 0.03 ISOURCE = 1 mA VA − 0.10 ISINK = 200 µA 0.02 ISINK = 1 mA IOZH, IOZL TRI-STATE Leakage Current COUT TRI-STATE Output Capacitance V 0.1 Output Coding V Straight (Natural) Binary POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA Supply Voltage Supply Current, Normal Mode (Operational, CS low) IA Supply Current, Shutdown (CS high) 2.7 V (min) 5.25 V (max) VA = +5.25V, fSAMPLE = 500 ksps, fIN = 40 kHz 1.9 2.4 mA (max) VA = +3.6V, fSAMPLE = 500 ksps, fIN = 40 kHz 0.84 1.2 mA (max) VA = +5.25V, fSAMPLE = 0 ksps 60 nA VA = +3.6V, fSAMPLE = 0 ksps 38 nA Power Consumption, Normal Mode (Operational, CS low) VA = +5.25V 10 12.6 mW (max) VA = +3.6V 3.0 4.3 mW (max) Power Consumption, Shutdown (CS high) VA = +5.25V 0.32 µW VA = +3.6V 0.14 µW PD AC ELECTRICAL CHARACTERISTICS fSCLK Maximum Clock Frequency See (3) fS Sample Rate See (3) tCONV Conversion Time MHz (min) 8 MHz (max) 200 ksps (min) 500 ksps (max) 13 SCLK cycles 30 % (min) 70 % (max) DC SCLK Duty Cycle fSCLK = 8 MHz tACQ Track/Hold Acquisition Time Full-Scale Step Input 3 SCLK cycles Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles (3) 50 3.2 This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 5 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ADC124S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 to 500 ksps, CL = 35 pF, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical VA = +3.0V −3.5 VA = +5.0V −0.5 VA = +3.0V +4.5 VA = +5.0V +1.5 VA = +3.0V +4 VA = +5.0V +2 VA = +3.0V +14.5 VA = +5.0V +13 Limits (1) Units 10 ns (min) 10 ns (min) 30 ns (max) 30 ns (max) tCSU Setup Time SCLK High to CS Falling Edge See (2) tCLH Hold time SCLK Low to CS Falling Edge See (2) tEN Delay from CS Until DOUT active tACC Data Access Time after SCLK Falling Edge tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min) tH Data Valid SCLK Hold Time +3 10 ns (min) ns (min) tCH SCLK High Pulse Width 0.5 x tSCLK 0.3 x tSCLK tCL SCLK Low Pulse Width 0.5 x tSCLK 0.3 x tSCLK ns (min) 20 ns (max) Output Falling tDIS CS Rising Edge to DOUT High-Impedance Output Rising (1) (2) VA = +3.0V 1.8 VA = +5.0V 1.3 VA = +3.0V 1.0 VA = +5.0V 1.0 Tested limits are ensured to AOQL (Average Outgoing Quality Level). Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.. Timing Diagrams Power Down Power Up Track Power Up Hold Track Hold CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 9 8 10 SCLK Control register Control register DIN DOUT b7 b6 b5 b4 b3 b2 b1 DB11 DB10 DB9 b0 DB8 b7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 b6 b5 DB0 b4 b3 b2 b1 DB11 DB10 DB9 b0 DB8 DB7 Figure 1. ADC124S051 Operational Timing Diagram 6 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 IOL 200 PA To Output Pin 1.6V CL 35 pF IOH 200 PA Figure 2. Timing Test Circuit CS tACQ tCONVERT tCH SCLK 1 2 3 4 6 DOUT Z3 tSU Z2 Z1 7 8 16 tACC tCL tEN DIN 5 Z0 DB11 DB10 tDIS DB9 DB1 DB8 DB0 tH DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Figure 3. ADC124S051 Serial Timing Diagram CS tCSU SCLK tCLH SCLK Figure 4. SCLK and CS Timing Parameters Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 7 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below VREF+ and is defined as: VFSE = Vmax + 1.5 LSB – VREF+ where • Vmax is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts, LSB or percent of full scale range. (1) GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1.5 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be reached with any input value. The ADC124S051 is ensured not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including d.c. or the harmonics included in THD. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c. SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. 8 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as: THD = 20 ‡ log10 A f 22 + + A f 62 A f12 where • • Af1 is the RMS power of the input frequency at the output and A Af2 through f6 are the RMS power in the first 5 harmonic frequencies. (2) THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion and read out times. In the case of the ADC124S051, this is 16 SCLK periods. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 9 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 10 DNL - VA = 3.0V INL - VA = 3.0V Figure 5. Figure 6. DNL - VA = 5.0V INL - VA = 5.0V Figure 7. Figure 8. DNL vs. Supply INL vs. Supply Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 11. Figure 12. DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle Figure 13. Figure 14. DNL vs. Temperature INL vs. Temperature Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 11 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 12 SNR vs. Supply THD vs. Supply Figure 17. Figure 18. SNR vs. Clock Frequency THD vs. Clock Frequency Figure 19. Figure 20. SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SNR vs. Input Frequency THD vs. Input Frequency Figure 23. Figure 24. SNR vs. Temperature THD vs. Temperature Figure 25. Figure 26. SFDR vs. Supply SINAD vs. Supply Figure 27. Figure 28. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 13 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 14 SFDR vs. Clock Frequency SINAD vs. Clock Frequency Figure 29. Figure 30. SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle Figure 31. Figure 32. SFDR vs. Input Frequency SINAD vs. Input Frequency Figure 33. Figure 34. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. SFDR vs. Temperature SINAD vs. Temperature Figure 35. Figure 36. ENOB vs. Supply ENOB vs. Clock Frequency Figure 37. Figure 38. ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency Figure 39. Figure 40. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 15 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 to 8 MHz, fIN = 40.2 kHz unless otherwise stated. 16 ENOB vs. Temperature Spectral Response - 3V, 200 ksps Figure 41. Figure 42. Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps Figure 43. Figure 44. Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput Figure 45. Figure 46. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 APPLICATIONS INFORMATION ADC124S051 OPERATION The ADC124S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter. Simplified schematics of the ADC124S051 in both track and hold modes are shown in Figure 47 Figure 48, respectively. In Figure 47, the ADC124S051 is in track mode: switch SW1 connects the sampling capacitor to one of four analog input channels through the multiplexer, and SW2 balances the comparator inputs. The ADC124S051 is in this state for the first three SCLK cycles after CS is brought low. Figure 48 shows the ADC124S051 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC124S051 is in this state for the fourth through sixteenth SCLK cycles after CS is brought low. The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of 16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is clocked into the DIN pin to indicate the multiplexer address for the next conversion. CHARGE REDISTRIBUTION DAC IN1 MUX SAMPLING CAPACITOR IN4 SW1 SW2 AGND + - CONTROL LOGIC VA 2 Figure 47. ADC124S051 in Track Mode CHARGE REDISTRIBUTION DAC IN1 MUX SAMPLING CAPACITOR IN4 SW1 SW2 AGND + - CONTROL LOGIC VA 2 Figure 48. ADC124S051 in Hold Mode Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 17 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com USING THE ADC124S051 An ADC124S051 timing diagram and a serial interface timing diagram for the ADC124S051 are shown in the Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC124S051's Control Register is placed at DIN, the serial data input pin. New data is written to the ADC at DIN with each conversion. A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a power down state when CS is high, and also between continuous conversion cycles. During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13 SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting with the 5th clock. If there is more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK, where "N" is an integer. When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC enters the track mode on the first falling edge of SCLK after the falling edge of CS. During each conversion, data is clocked into the ADC at DIN on the first 8 rising edges of SCLK after the fall of CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. See Table 2, Table 3, and Table 4. If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking in data at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum tCSU and tCLH times given in the Timing Specifications. There are no power-up delays or dummy conversions required with the ADC124S051. The ADC is able to sample and convert an input to full conversion immediately following power up. The first conversion result after power-up will be that of IN1. Table 2. Control Register Bits Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC Table 3. Control Register Bit Descriptions Bit #: Symbol: Description 7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect device operation. 5 ADD2 4 ADD1 3 ADD0 These three bits determine which input channel will be sampled and converted in the next track/hold cycle. The mapping between codes and channels is shown in Table 4. Table 4. Input Channel Selection 18 ADD2 ADD1 ADD0 Input Channel x 0 0 IN1 (Default) x 0 1 IN2 x 1 0 IN3 x 1 1 IN4 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 ADC124S051 TRANSFER FUNCTION The output format of the ADC124S051 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC124S051 is VA/4096. The ideal transfer characteristic is shown in Figure 49. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of VA/8192. Other code transitions occur at steps of one LSB. 111...111 111...000 | | ADC CODE 111...110 1LSB = VA/4096 011...111 000...010 | 000...001 000...000 0.5LSB 0V ANALOG INPUT +VA - 1.5LSB Figure 49. Ideal Transfer Characteristic TYPICAL APPLICATION CIRCUIT A typical application of the ADC124S051 is shown in Figure 50. Power is provided, in this example, by the LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC124S051. Because the reference for the ADC124S051 is the supply voltage, any noise on the supply will degrade device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC124S051 supply pin. Because of the ADC124S051's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The four-wire interface is shown connected to a microprocessor or DSP. LP2950 1 PF TANT VA IN1 IN2 IN3 1 PF 0.1 PF SCLK ADC124S051 IN4 0.1 PF 5V CS DIN MICROPROCESSOR DSP DOUT GND Figure 50. Typical Application Circuit Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 19 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com ANALOG INPUTS An equivalent circuit for one of the ADC124S051's input channels is shown in Figure 51. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should any input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason, these ESD diodes should NOT be used to clamp the input signal. The capacitor C1 in Figure 51 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the ADC124S051 sampling capacitor, and is typically 30 pF. The ADC124S051 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC124S051 to sample AC signals. Also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance. VA D1 R1 C2 30 pF VIN C1 3 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Figure 51. Equivalent Input Circuit DIGITAL INPUTS AND OUTPUTS The ADC124S051's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted before VA without any latch-up risk. POWER SUPPLY CONSIDERATIONS The ADC124S051 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with one exception: the ADC124S051 automatically enters power-down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams). The ADC124S051 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles. The ADC124S051 will perform conversions continuously as long as CS is held low. The user may trade off throughput for power consumption by simply performing fewer conversions per unit time. The Power Consumption vs. Sample Rate curve in the Typical Performance Characteristics section shows the typical power consumption of the ADC124S051 versus throughput. To calculate the power consumption, simply multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation. 20 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 ADC124S051 www.ti.com SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 Power Management When the ADC124S051 is operated continuously in normal mode, the maximum throughput is fSCLK/16. Throughput may be traded for power consumption by running fSCLK at its maximum 8 MHz and performing fewer conversions per unit time, putting the ADC124S051 into shutdown mode between conversions. A plot of typical Power Consumption vs. Throughput is shown in the Typical Performance Characteristics section. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part back into shutdown mode. Note that the curve of Power Consumption vs. Throughput is nearly linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. Power Supply Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger is the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 35 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and maintain noise performance. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 21 ADC124S051 SNAS260E – NOVEMBER 2004 – REVISED NOVEMBER 2004 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 22 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 21 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: ADC124S051 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADC124S051CIMM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X12C ADC124S051CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X12C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADC124S051CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADC124S051CIMMX/NOP VSSOP B DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC124S051CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 VSSOP DGS 10 3500 367.0 367.0 35.0 ADC124S051CIMMX/NOP B Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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