Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350 BS66F360/BS66F370 Revision: V1.40 Date: ����������������� December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Table of Contents Features................................................................................................................. 7 CPU Features...............................................................................................................................7 Peripheral Features.......................................................................................................................7 General Description.............................................................................................. 8 Selection Table...................................................................................................... 9 Block Diagram....................................................................................................... 9 Pin Assignment................................................................................................... 10 Pin Descriptions................................................................................................. 15 Absolute Maximum Ratings............................................................................... 30 D.C. Characteristics............................................................................................ 30 A.C. Characteristics............................................................................................ 32 A/D Converter Characteristics........................................................................... 33 Temperature Sensor Electrical Characteristics............................................... 33 LVD/LVR Electrical Characteristics................................................................... 34 Touch Key Electrical Characteristics................................................................ 35 Power-on Reset Characteristics........................................................................ 37 System Architecture........................................................................................... 38 Clocking and Pipelining...............................................................................................................38 Program Counter.........................................................................................................................39 Stack...........................................................................................................................................40 Arithmetic and Logic Unit – ALU.................................................................................................40 Flash Program Memory...................................................................................... 41 Structure......................................................................................................................................41 Special Vectors...........................................................................................................................41 Look-up Table..............................................................................................................................42 Table Program Example..............................................................................................................42 In Circuit Programming – ICP.....................................................................................................43 On-Chip Debug Support – OCDS...............................................................................................44 In Application Programming – IAP..............................................................................................45 Data Memory....................................................................................................... 55 Structure......................................................................................................................................55 Data Memory Addressing............................................................................................................56 General Purpose Data Memory..................................................................................................56 Special Purpose Data Memory...................................................................................................56 Special Function Register Description............................................................. 61 Indirect Addressing Registers – IAR0, IAR1, IAR2.....................................................................61 Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L.................................................................61 Rev. 1.40 2 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Program Memory Bank Pointer – PBP........................................................................................63 Accumulator – ACC.....................................................................................................................63 Program Counter Low Register – PCL........................................................................................63 Look-up Table Registers – TBLP, TBHP, TBLH...........................................................................64 Status Register – STATUS..........................................................................................................64 EEPROM Data Memory....................................................................................... 66 EEPROM Data Memory Structure..............................................................................................66 EEPROM Registers....................................................................................................................66 Reading Data from the EEPROM...............................................................................................67 Writing Data to the EEPROM......................................................................................................68 Write Protection...........................................................................................................................68 EEPROM Interrupt......................................................................................................................68 Programming Considerations......................................................................................................68 Oscillators........................................................................................................... 70 Oscillator Overview.....................................................................................................................70 System Clock Configurations......................................................................................................70 External Crystal/Ceramic Oscillator – HXT.................................................................................71 Internal High Speed RC Oscillator – HIRC.................................................................................72 External 32.768 kHz Crystal Oscillator – LXT.............................................................................72 Internal 32kHz Oscillator – LIRC.................................................................................................73 Operating Modes and System Clocks.............................................................. 74 System Clocks............................................................................................................................74 System Operation Modes............................................................................................................76 Control Registers........................................................................................................................77 Operating Mode Switching..........................................................................................................80 Standby Current Considerations.................................................................................................84 Wake-up......................................................................................................................................84 Watchdog Timer.................................................................................................. 85 Watchdog Timer Clock Source....................................................................................................85 Watchdog Timer Control Register...............................................................................................85 Watchdog Timer Operation.........................................................................................................86 Reset and Initialisation....................................................................................... 87 Reset Functions..........................................................................................................................87 Reset Initial Conditions...............................................................................................................90 Input/Output Ports.............................................................................................. 97 Pull-high Resistors....................................................................................................................100 Port A Wake-up.........................................................................................................................100 I/O Port Control Registers.........................................................................................................100 I/O Port Source Current Control................................................................................................100 Pin-shared Functions................................................................................................................102 I/O Pin Structures...................................................................................................................... 111 Programming Considerations.................................................................................................... 112 Rev. 1.40 3 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer Modules – TM......................................................................................... 113 Introduction............................................................................................................................... 113 TM Operation............................................................................................................................ 113 TM Clock Source....................................................................................................................... 113 TM Interrupts............................................................................................................................. 114 TM External Pins....................................................................................................................... 114 TM Input/Output Pin Selection.................................................................................................. 115 Programming Considerations.................................................................................................... 116 Compact Type TM – CTM................................................................................. 117 Compact TM Operation............................................................................................................. 117 Compact Type TM Register Description................................................................................... 118 Compact Type TM Operation Modes........................................................................................122 Standard Type TM – STM................................................................................. 128 Standard TM Operation.............................................................................................................128 Standard Type TM Register Description...................................................................................129 Standard Type TM Operation Modes........................................................................................133 Periodic Type TM – PTM................................................................................... 143 Periodic TM Operation..............................................................................................................143 Periodic Type TM Register Description.....................................................................................144 Periodic Type TM Operation Modes..........................................................................................148 Analog to Digital Converter............................................................................. 157 A/D Converter Overview...........................................................................................................157 Registers Descriptions..............................................................................................................158 A/D Converter Operation...........................................................................................................163 A/D Converter Reference Voltage.............................................................................................164 A/D Converter Input Pins..........................................................................................................164 Conversion Rate and Timing Diagram......................................................................................164 Summary of A/D Conversion Steps...........................................................................................165 Programming Considerations....................................................................................................166 A/D Converter Transfer Function..............................................................................................166 A/D Programming Examples.....................................................................................................167 Serial Interface Module – SIM.......................................................................... 169 SPI Interface.............................................................................................................................169 I2C Interface..............................................................................................................................175 UART Interface.................................................................................................. 184 UART External Pin....................................................................................................................185 UART Data Transfer Scheme...................................................................................................185 UART Status and Control Registers.........................................................................................185 Baud Rate Generator................................................................................................................191 UART Setup and Control..........................................................................................................192 UART Transmitter.....................................................................................................................193 UART Receiver.........................................................................................................................194 Managing Receiver Errors........................................................................................................196 Rev. 1.40 4 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UART Interrupt Structure..........................................................................................................197 UART Power Down and Wake-up.............................................................................................198 Touch Key Function......................................................................................... 199 Touch Key Structure..................................................................................................................199 Touch Key Register Definition...................................................................................................200 Touch Key Operation.................................................................................................................206 Touch Key Interrupt...................................................................................................................212 Progrsmming Considerations....................................................................................................212 Low Voltage Detector – LVD............................................................................ 213 LVD Register.............................................................................................................................213 LVD Operation...........................................................................................................................214 Interrupts........................................................................................................... 215 Interrupt Registers.....................................................................................................................215 Interrupt Operation....................................................................................................................220 External Interrupt.......................................................................................................................221 Touch Key Interrupt...................................................................................................................222 UART Transfer Interrupt............................................................................................................222 A/D Converter Interrupt.............................................................................................................222 Multi-function Interrupt..............................................................................................................222 Time Base Interrupt...................................................................................................................223 Serial Interface Module Interrupt...............................................................................................224 LVD Interrupt.............................................................................................................................225 EEPROM Interrupt....................................................................................................................225 TM Interrupt...............................................................................................................................225 Programming Considerations....................................................................................................226 Application Circuits.......................................................................................... 227 Instruction Set................................................................................................... 228 Introduction...............................................................................................................................228 Instruction Timing......................................................................................................................228 Moving and Transferring Data...................................................................................................228 Arithmetic Operations................................................................................................................228 Logical and Rotate Operation...................................................................................................229 Branches and Control Transfer.................................................................................................229 Bit Operations...........................................................................................................................229 Table Read Operations.............................................................................................................229 Other Operations.......................................................................................................................229 Instruction Set Summary................................................................................. 230 Table Conventions.....................................................................................................................230 Extended Instruction Set...........................................................................................................232 Instruction Definition........................................................................................ 234 Extended Instruction Definition.................................................................................................243 Rev. 1.40 5 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Package Information........................................................................................ 250 28-pin SOP (300mil) Outline Dimensions.................................................................................251 28-pin SSOP (150mil) Outline Dimensions...............................................................................252 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions.................................................253 48-pin LQFP (7mm×7mm) Outline Dimensions........................................................................254 64-pin LQFP (7mm×7mm) Outline Dimensions........................................................................255 Rev. 1.40 6 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Features CPU Features • Operating voltage ♦♦ fSYS= 8MHz: 2.2V~5.5V ♦♦ fSYS=12MHz: 2.7V~5.5V ♦♦ fSYS=16MHz: 3.3V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator type ♦♦ External High Speed Crystal – HXT ♦♦ Internal High Speed RC – HIRC ♦♦ External 32.768kHz Crystal – LXT ♦♦ Internal 32kHz RC – LIRC • Fully integrated internal 8/12/16MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions • 115 powerful instructions • Up to 16-level subroutine nesting • Bit manipulation instruction Peripheral Features • Program Memory: Up to 32K×16 • Data Memory: Up to 1536×8 • True EEPROM Memory: 128×8 • Fully integrated touch key functions – require no external components • Watchdog Timer function • Up to 60 bidirectional I/O lines • Two external interrupt lines shared with I/O pins • Multiple Timer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function • Serial Interfaces Module – SIM for SPI or I2C • Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART • Programming I/O source current • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • Temperature Sensor • In Application Programming function – IAP • Low voltage reset function • Low voltage detect function Rev. 1.40 7 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • True EEPROM data memory can be re-programmed up to 1,000,000 times • True EEPROM data memory data retention > 10 years • Wide range of available package types General Description The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontroller with fully integrated touch key functions. With all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, each device has all the features to offer designers a reliable and easy means of implementing Touch Keyes within their products applications. The touch key functions are fully integrated completely eliminating the need for external components. In addition to the flash program memory, other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data, etc. Analog features include a multi-channel 12-bit A/D converter with temperature sensor. Protective features such as an internal Watchdog Timer and Low Voltage Reset functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. These devices also include fully integrated low and high speed oscillators which are flexibly used for different applications. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the internal UART, I2C and SPI interfaces, while the inclusion of flexible I/O programming features, Timer modules and many other features further enhance device functionality and flexibility. The touch key devices will find excellent use in a huge range of modern Touch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. Rev. 1.40 8 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Selection Table Most features are common to all devices. The main features distinguishing them are Memory capacity, I/O count, Touch Module and key mumber, stack capacity and package types. The following table summarises the main features of each device. Part No. Program Memory Data Memory Data EEPROM I/O A/D Temp. Sensor Time Base BS66F340 4k×16 512×8 128×8 26 12-bit×8 √ 2 BS66F350 8k×16 768×8 128×8 40 12-bit×8 √ 2 BS66F360 16k×16 1024×8 128×8 46 12-bit×8 √ 2 BS66F370 32K×16 1536×8 128×8 60 12-bit×8 √ 2 Part No. Timer Module Touch Module Touch Key SIM UART Stacks Package BS66F340 10-bit CTM×2 10-bit PTM×1 16-bit STM×1 3 12 √ √ 8 28SSOP BS66F350 10-bit CTM×2 10-bit PTM×1 16-bit STM×1 5 20 √ √ 8 44/48LQFP BS66F360 10-bit CTM×2 10-bit PTM×1 16-bit STM×1 7 28 √ √ 12 28SOP 44/48LQFP BS66F370 10-bit CTM×2 10-bit PTM×1 16-bit STM×1 9 36 √ √ 16 44/48/64LQFP Note: As devices exist in more than one package format, the table reflects the situation for the package with the most pins. Block Diagram Wat�hdog Ti�e� Flash/EEPROM P�og�a��ing Ci��uit�y EEPROM Data Me�o�y Flash P�og�a� Me�o�y Low Voltage Dete�t IAP Reset Ci��uit Inte�nal HIRC/LIRC Os�illato�s Low Voltage Reset RAM Data Me�o�y Ti�e Base 8-�it RISC MCU Co�e Inte��upt Cont�olle� Exte�nal HXT Os�illato� Exte�nal LXT Os�illato� 1�-�it A/D Conve�te� I/O Rev. 1.40 Ti�e� Modules SIM (SPI/I�C) UART Te�pe�atu�e Senso� Tou�h Key Modules 9 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pin Assignment PB3/RX/AN3 1 28 PA7/CTP1 PB2/PTPI/TX/PTP/AN2 2 27 PB7/INT1/KEY4/AN7 PB6/PTCK/KEY3/AN6 3 26 PA6/CTCK0/INT0 PC0/KEY5 4 25 PB5/STCK/KEY2/AN5 5 24 PC1/KEY6 PC2/KEY7 PB4/PTPI/PTPB/KEY1/AN4 PB1/SCK/SCL/AN1 6 23 PC3/KEY8 7 22 PB0/SDI/SDA/VREF/AN0 8 21 PE0/KEY9 PE1/KEY10 VDD PA4/SDO/XT2 PA3/SCS/XT1 9 20 PE2/STPI/STP/KEY11 10 19 11 18 PE3/STPI/STPB/KEY12 PA5/CTP0B VSS PE4/OSC1 12 17 PA1/CTP0 13 16 PA2/CTCK1/SCS/ICPCK/OCDSCK PE5/CTP1B/OSC2 14 15 PA0/SDO/ICPDA/OCDSDA BS66F340/BS66V340 28 SSOP-A PA5/CTP0B 1 28 PA1/CTP0 PA6/CTCK0/INT0 2 27 PA2/SCSB/OCDSCK PA7 3 26 PA0/SDO/OCDSDA PE3/STP0B/STP0I_1/KEY24 4 25 PE2/STP0/STP0I_0/KEY23 5 24 PE5/CTCK1/OSC2 PE4/OSC1 PD7/KEY20 6 23 PD6/KEY19 PD5/KEY18 7 22 VSS PA3/SCSB/XT1 PD4/KEY17 8 9 21 20 PD3/KEY16 10 19 VDD PD2/KEY15 11 18 PD1/KEY14 PB0/VREF/SDI/SDA/RESB/AN0 12 17 PB1/SCK/SCL/AN1 PB2/PTP0/PTP0I_0/TX/AN2 PB3/RX/AN3 13 16 PB4/PTP0B/PTP0I_1/AN4/KEY1 PB6/PTCK0/AN6/KEY3 14 15 PB5/STCK0/AN5/KEY2 PA4/SDO/XT2 BS66F360/BS66V360 28 SOP-A Rev. 1.40 10 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PA�/SCS/ICPCK/OCDSCK NC NC NC PE7/CTP1B PE�/CTP1 PB�/PTPI/TX/PTP/AN� PB1/SCK/SCL/AN1 PB0/SDI/SDA/VREF/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 NC NC 44 43 4� 41 40 39 38 37 3� 3� 34 1 33 � 3� 3 31 4 30 � �9 BS66F350/BS66V350 � �8 44 LQFP-A 7 �7 8 �� 9 �� 10 �4 11 �3 1� 13 14 1� 1� 17 18 19 �0 �1 �� PB3/RX/AN3 PB4/PTPI/PTPB/KEY1/AN4 PB�/STCK/KEY�/AN� PB�/PTCK/KEY3/AN� PB7/INT1/KEY4/AN7 PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0 PE1 PE�/STPI/STP PE3/STPI/STPB PA�/SCS/ICPCK/OCDSCK PB3/RX/AN3 PB�/PTPI/TX/PTP/AN� PB1/SCK/SCL/AN1 PB0/SDI/SDA/VREF/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 NC NC NC NC NC NC PE7/CTP1B PE�/CTP1 48 47 4� 4� 44 43 4� 41 40 39 38 37 3� 1 3� � 34 3 33 4 � 3� 31 BS66F350/BS66V350 � 7 30 48 LQFP-A �9 8 �8 9 �7 10 �� 11 �� 1� 13 14 1� 1� 17 18 19 �0 �1 �� �3 �4 PD0/KEY13 PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0 PE1 PE�/STPI/STP PE3/STPI/STPB Rev. 1.40 PB4/PTPI/PTPB/KEY1/AN4 PB�/STCK/KEY�/AN� PB�/PTCK/KEY3/AN� PB7/INT1/KEY4/AN7 PC0/KEY� PC1/KEY� PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� 11 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PA�/SCS/ICPCK/OCDSCK PF� PF1/KEY�8 PF0/KEY�7 PE7/CTP1B/KEY�� PE�/CTP1/KEY�� PB�/PTPI/TX/PTP/AN� PB1/SCK/SCL/AN1 PB0/SDI/SDA/VREF/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 PF� PF3 44 43 4� 41 40 39 38 37 3� 3� 34 1 33 � 3� 3 31 4 30 � �9 BS66F360/BS66V360 � �8 44 LQFP-A 7 �7 8 �� 9 �� 10 �4 11 �3 1� 13 14 1� 1� 17 18 19 �0 �1 �� PB3/RX/AN3 PB4/PTPI/PTPB/KEY1/AN4 PB�/STCK/KEY�/AN� PB�/PTCK/KEY3/AN� PB7/INT1/KEY4/AN7 PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0 PE1 PE�/STPI/STP/KEY�3 PE3/STPI/STPB/KEY�4 PA�/SCS/ICPCK/OCDSCK PB3/RX/AN3 PB�/PTPI/TX/PTP/AN� PB1/SCK/SCL/AN1 PB0/SDI/SDA/VREF/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 PF� PF4 PF3 PF� PF1/KEY�8 PF0/KEY�7 PE7/CTP1B/KEY�� PE�/CTP1/KEY�� 48 47 4� 4� 44 43 4� 41 40 39 38 37 3� 1 3� � 34 3 4 33 � 3� 31 BS66F360/BS66V360 � 7 30 48 LQFP-A �9 8 �8 9 �7 10 �� 11 �� 1� 13 14 1� 1� 17 18 19 �0 �1 �� �3 �4 PD0/KEY13 PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0/KEY�1 PE1/KEY�� PE�/STPI/STP/KEY�3 PE3/STPI/STPB/KEY�4 Rev. 1.40 PB4/PTPI/PTPB/KEY1/AN4 PB�/STCK/KEY�/AN� PB�/PTCK/KEY3/AN� PB7/INT1/KEY4/AN7 PC0/KEY� PC1/KEY� PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� 12 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PB�/PTP/PTPI/TX/AN� PB1/SCK/SCL/AN1 PB0/VREF/SDI/SDA/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA�/SCS/ICPCK/OCDSCK PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 PF� PF3 PF� PF1/KEY�8 PF0/KEY�7 PE7/CTP1B/KEY�� PE�/CTP1/KEY�� 44 43 4� 41 40 39 38 37 3� 3� 34 1 33 � 3� 3 31 4 30 � �9 BS66F370/BS66V370 � �8 44 LQFP-A 7 �7 8 �� 9 �� 10 �4 11 �3 1� 13 14 1� 1� 17 18 19 �0 �1 �� PB3/RX/AN3 PB4/PTPB/PTPI/AN4/KEY1 PB�/STCK/AN�/KEY� PB�/PTCK/AN�/KEY3 PB7/INT1/AN7/KEY4 PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0/KEY�1 PE1/KEY�� PE�/STP/STPI/KEY�3 PE3/STPB/STPI/KEY�4 PB3/RX/AN3 PB�/PTP/PTPI/TX/AN� PB1/SCK/SCL/AN1 PB0/VREF/SDI/SDA/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA�/SCS/ICPCK/OCDSCK PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 PF� PF4 PF3 PF� PF1/KEY�8 PF0/KEY�7 PE7/CTP1B/KEY�� PE�/CTP1/KEY�� 48 47 4� 4� 44 43 4� 41 40 39 38 37 3� 1 3� � 34 3 33 4 � 3� 31 BS66F370/BS66V370 � 7 30 48 LQFP-A �9 8 �8 9 �7 10 �� 11 �� 1� 13 14 1� 1� 17 18 19 �0 �1 �� �3 �4 PB4/PTPB/PTPI/AN4/KEY1 PB�/STCK/AN�/KEY� PB�/PTCK/AN�/KEY3 PB7/INT1/AN7/KEY4 PC0/KEY� PC1/KEY� PC�/KEY7 PC3/KEY8 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� PD0/KEY13 PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0/KEY�1 PE1/KEY�� PE�/STP/STPI/KEY�3 PE3/STPB/STPI/KEY�4 Rev. 1.40 13 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PG0/KEY�9 PG1/KEY30 PG�/KEY31 PG3/KEY3� PB3/RX/AN3 PB�/PTP/PTPI/TX/AN� PB1/SCK/SCL/AN1 PB0/VREF/SDI/SDA/AN0 VDD PA4/SDO/XT� PA3/SCS/XT1 VSS PE4/OSC1 PE�/CTCK1/OSC� PA0/SDO/ICPDA/OCDSDA PA�/SCS/ICPCK/OCDSCK PA1/CTP0 PA�/CTP0B PA�/CTCK0/INT0 PA7 PF� PF4 PF3 PF� PH� PH4 PH3 PH� PF1/KEY�8 PF0/KEY�7 PE7/CTP1B/KEY�� PE�/CTP1/KEY�� �4 �3 �� �1 �0 �9 �8 �7 �� �� �4 �3 �� �1 �0 49 1 48 � 47 3 4� 4 4� � 44 � 43 4� 7 BS66F370/BS66V370 8 41 40 9 64 LQFP-A 10 39 38 11 1� 37 3� 13 3� 14 34 1� 33 1� 17 18 19 �0 �1 �� �3 �4 �� �� �7 �8 �9 30 31 3� PB4/PTPB/PTPI/AN4/KEY1 PB�/STCK/AN�/KEY� PB�/PTCK/AN�/KEY3 PB7/INT1/AN7/KEY4 PC0/KEY� PC1/KEY� PC�/KEY7 PC3/KEY8 PH0 PH1 VDD1 VSS1 PC4/KEY9 PC�/KEY10 PC�/KEY11 PC7/KEY1� PG4/KEY33 PG�/KEY34 PG�/KEY3� PG7/KEY3� PD0/KEY13 PD1/KEY14 PD�/KEY1� PD3/KEY1� PD4/KEY17 PD�/KEY18 PD�/KEY19 PD7/KEY�0 PE0/KEY�1 PE1/KEY�� PE�/STP/STPI/KEY�3 PE3/STPB/STPI/KEY�4 Note: The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the BS66V3x0 device which is the OCDS EV chip for the BS66F3x0 device. Rev. 1.40 14 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on these devices can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. BS66F340 Pad Name PA0/SDO/ ICPDA/ OCDSDA PA1/CTP0 PA2/CTCK1/ SCS/ ICPCK/ OCDSCK PA3/SCS/ XT1 PA4/SDO/ XT2 PA5/CTP0B PA6/CTCK0/ INT0 Rev. 1.40 Function OPT I/T PA0 PAWU PAPU PAS0 O/T Description ST SDO PAS0 — CMOS SPI data output ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA2 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTCK1 PAS0 ST SCS PAS0 IFS ST CMOS SPI slave select CMOS ICP Clock pin CMOS General purpose I/O. Register enabled pull-up and wake-up. — CTM1 clock input ICPCK — ST OCDSCK — ST PA3 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT PA4 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output — — OCDS Clock pin, for EV chip only. LXT oscillator pin SDO PAS1 — XT2 PAS1 — PA5 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inverted output PA6 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 clock input INT0 PAS1 INTEG INTC0 ST — External Interrupt 0 LXT LXT oscillator pin 15 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PA7/CTP1 PB0/SDI/ SDA/VREF/ AN0 PB1/SCK/ SCL/AN1 PB2/PTPI/ TX/PTP/AN2 PB3/RX/AN3 PB4/PTPI/ PTPB/KEY1/ AN4 PB5/STCK/ KEY2/AN5 PB6/PTCK/ KEY3/AN6 PB7/INT1/ KEY4/AN7 Rev. 1.40 Function OPT I/T PA7 PAWU PAPU PAS1 O/T ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP1 PAS1 — CMOS CTM1 output PB0 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. SDI PBS0 ST SDA PBS0 ST — Description SPI data input NMOS I2C data line VREF PBS0 — AN A/D Converter reference voltage output AN0 PBS0 AN — A/D Converter analog input PB1 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. SCK PBS0 ST CMOS SPI serial clock SCL PBS0 ST NMOS I2C clock line AN1 PBS0 AN PB2 PBPU PBS0 ST PTPI PBS0 IFS ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. — PTM capture input TX PBS0 — CMOS UART TX serial data output PTP PBS0 — CMOS PTM output AN2 PBS0 AN PB3 PBPU PBS0 ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. RX PBS0 ST — UART RX serial data input AN3 PBS0 AN — A/D Converter analog input PB4 PBPU PBS1 ST PTPI PBS1 IFS ST PTPB PBS1 — KEY1 PBS1 AN — Touch key input AN4 PBS1 AN — A/D Converter analog input PB5 PBPU PBS1 ST CMOS General purpose I/O. Register enabled pull-up. — PTM capture input CMOS PTM inverted output CMOS General purpose I/O. Register enabled pull-up. STCK PBS1 ST — STM clock input KEY2 PBS1 AN — Touch key input AN5 PBS1 AN — A/D Converter analog input PB6 PBPU PBS1 ST CMOS General purpose I/O. Register enabled pull-up. PTCK PBS1 ST — PTM clock input KEY3 PBS1 AN — Touch key input AN6 PBS1 AN — A/D Converter analog input PB7 PBPU PBS1 ST INT1 PBS1 INTEG INTC0 ST CMOS General purpose I/O. Register enabled pull-up. — External Interrupt 1 KEY4 PBS1 AN — Touch key input AN7 PBS1 AN — A/D Converter analog input 16 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PC0/KEY5 PC1/KEY6 PC2/KEY7 PC3/KEY8 PE0/KEY9 PE1/KEY10 PE2/STPI/ STP/KEY11 PE3/STPI/ STPB/ KEY12 PE4/OSC1 PE5/CTP1B/ OSC2 Function OPT I/T PC0 PCPU PCS0 ST KEY5 PCS0 AN PC1 PCPU PCS0 ST KEY6 PCS0 AN PC2 PCPU PCS0 ST KEY7 PCS0 AN PC3 PCPU PCS0 ST KEY8 PCS0 AN PE0 PEPU PES0 ST KEY9 PES0 AN PE1 PEPU PES0 ST KEY10 PES0 AN PE2 PEPU PES0 ST STPI PES0 IFS ST STP PES0 — KEY11 PES0 AN PE3 PEPU PES0 ST STPI PES0 IFS ST O/T Description CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — STM capture input CMOS STM output — Touch key input CMOS General purpose I/O. Register enabled pull-up. — STM capture input STPB PES0 — KEY12 PES0 AN CMOS STM inverted output PE4 PEPU PES1 ST OSC1 PES1 HXT PE5 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS CTM0 inverted output — Touch key input CMOS General purpose I/O. Register enabled pull-up. — HXT oscillator pin CTP1B PES1 — OSC2 PES1 — HXT VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground. HXT oscillator pin Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt Trigger input; AN: Analog signal; CMOS: CMOS output; NMOS: NMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator Rev. 1.40 17 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F350 Pad Name PA0/SDO/ ICPDA/ OCDSDA PA1/CTP0 PA2/SCS/ ICPCK/ OCDSCK PA3/SCS/XT1 PA4/SDO/XT2 PA5/CTP0B PA6/CTCK0/ INT0 PA7 PB0/SDI/ SDA/VREF/ AN0 Rev. 1.40 Function OPT I/T PA0 PAWU PAPU PAS0 O/T Description ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output SDO PAS0 — ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA2 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select CMOS ICP Clock pin ICPCK — ST OCDSCK — ST PA3 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT PA4 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT2 PAS1 — PA5 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inverted output PA6 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 clock input INT0 PAS1 INTEG INTC0 ST — External Interrupt 0 PA7 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PB0 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. — — LXT — OCDS Clock pin, for EV chip only. LXT oscillator pin LXT oscillator pin SDI PBS0 ST SDA PBS0 ST SPI data input VREF PBS0 — AN A/D Converter reference voltage output AN0 PBS0 AN — A/D Converter analog input NMOS I2C data line 18 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PB1/SCK/ SCL/AN1 PB2/PTPI/TX/ PTP/AN2 PB3/RX/AN3 PB4/PTPI/ PTPB/KEY1/ AN4 PB5/STCK/ KEY2/AN5 PB6/PTCK/ KEY3/AN6 PB7/INT1/ KEY4/AN7 PC0/KEY5 PC1/KEY6 PC2/KEY7 Rev. 1.40 Function OPT I/T PB1 PBPU PBS0 ST O/T Description CMOS General purpose I/O. Register enabled pull-up. SCK PBS0 ST CMOS SPI serial clock SCL PBS0 ST NMOS I2C clock line AN1 PBS0 AN PB2 PBPU PBS0 ST PTPI PBS0 IFS ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. — PTM capture input TX PBS0 — CMOS UART TX serial data output PTP PBS0 — CMOS PTM output AN2 PBS0 AN PB3 PBPU PBS0 ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. RX PBS0 ST — UART RX serial data input AN3 PBS0 AN — A/D Converter analog input PB4 PBPU PBS1 ST PTPI PBS1 IFS ST CMOS General purpose I/O. Register enabled pull-up. — PTM capture input PTPB PBS1 — KEY1 PBS1 AN CMOS PTM inverted output — Touch key input AN4 PBS1 AN — A/D Converter analog input PB5 PBPU PBS1 ST STCK PBS1 ST — STM clock input KEY2 PBS1 AN — Touch key input AN5 PBS1 AN — A/D Converter analog input PB6 PBPU PBS1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. PTCK PBS1 ST — PTM clock input KEY3 PBS1 AN — Touch key input AN6 PBS1 AN — A/D Converter analog input PB7 PBPU PBS1 ST INT1 PBS1 INTEG INTC0 ST CMOS General purpose I/O. Register enabled pull-up. — External Interrupt 1 KEY4 PBS1 AN — Touch key input AN7 PBS1 AN — A/D Converter analog input PC0 PCPU PCS0 ST KEY5 PCS0 AN PC1 PCPU PCS0 ST KEY6 PCS0 AN PC2 PCPU PCS0 ST KEY7 PCS0 AN CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input 19 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T PC3 PCPU PCS0 ST KEY8 PCS0 AN PC4 PCPU PCS1 ST KEY9 PCS1 AN PC5 PCPU PCS1 ST KEY10 PCS1 AN PC6 PCPU PCS1 ST KEY11 PCS1 AN PC7 PCPU PCS1 ST KEY12 PCS1 AN PD0 PDPU PDS0 ST KEY13 PDS0 AN PD1 PDPU PDS0 ST KEY14 PDS0 AN PD2 PDPU PDS0 ST KEY15 PDS0 AN PD3 PDPU PDS0 ST KEY16 PDS0 AN PD4 PDPU PDS1 ST KEY17 PDS1 AN PD5 PDPU PDS1 ST KEY18 PDS1 AN PD6 PDPU PDS1 ST KEY19 PDS1 AN PD7 PDPU PDS1 ST KEY20 PDS1 AN PE0 PE0 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. PE1 PE1 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. PE2 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. STPI PES0 IFS ST STP PES0 — CMOS STM output PE3 PEPU PES0 ST CMOS General purpose I/O. Register enabled pull-up. STPI PES0 IFS ST STPB PES0 — PC3/KEY8 PC4/KEY9 PC5/KEY10 PC6/KEY11 PC7/KEY12 PD0/KEY13 PD1/KEY14 PD2/KEY15 PD3/KEY16 PD4/KEY17 PD5/KEY18 PD6/KEY19 PD7/KEY20 PE2/STPI/ STP PE3/STPI/ STPB Rev. 1.40 O/T Description CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — — — Touch key input STM capture input STM capture input CMOS STM inverted output 20 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T PE4 PEPU PES1 ST OSC1 PES1 HXT PE5 PEPU PES1 ST CTCK1 PES1 ST — CTM1 clock input OSC2 PES1 — HXT HXT oscillator pin PE6 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CTP1 PES1 — CMOS CTM1 output PE7 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CTP1B PES1 — CMOS CTM1 inverted output VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground. PE4/OSC1 PE5/CTCK1/ OSC2 PE6/CTP1 PE7/CTP1B O/T CMOS General purpose I/O. Register enabled pull-up. — HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. Legend: I/T: Input type; OPT: Optional by register option; ST: Schmitt Trigger input; CMOS: CMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator Rev. 1.40 Description O/T: Output type; PWR: Power; AN: Analog signal; NMOS: NMOS output; 21 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F360 Pad Name PA0/SDO/ ICPDA/ OCDSDA PA1/CTP0 PA2/SCS/ ICPCK/ OCDSCK PA3/SCS/XT1 PA4/SDO/ XT2 PA5/CTP0B PA6/CTCK0/ INT0 PA7 PB0/SDI/ SDA/VREF/ AN0 Rev. 1.40 Function OPT I/T PA0 PAWU PAPU PAS0 O/T Description ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output SDO PAS0 — ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA2 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select CMOS ICP Clock pin ICPCK — ST OCDSCK — ST PA3 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT PA4 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT2 PAS1 — PA5 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inverted output PA6 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 clock input INT0 PAS1 INTEG INTC0 ST — External Interrupt 0 PA7 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PB0 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. — — LXT — OCDS Clock pin, for EV chip only. LXT oscillator pin LXT oscillator pin SDI PBS0 ST SDA PBS0 ST SPI data input VREF PBS0 — AN A/D Converter reference voltage output AN0 PBS0 AN — A/D Converter analog input NMOS I2C data line 22 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PB1/SCK/ SCL/AN1 PB2/PTPI/TX/ PTP/AN2 PB3/RX/AN3 PB4/PTPI/ PTPB/KEY1/ AN4 PB5/STCK/ KEY2/AN5 PB6/PTCK/ KEY3/AN6 PB7/INT1/ KEY4/AN7 PC0/KEY5 PC1/KEY6 PC2/KEY7 PC3/KEY8 Rev. 1.40 Function OPT I/T PB1 PBPU PBS0 ST O/T Description CMOS General purpose I/O. Register enabled pull-up. SCK PBS0 ST CMOS SPI serial clock SCL PBS0 ST NMOS I2C clock line AN1 PBS0 AN PB2 PBPU PBS0 ST PTPI PBS0 IFS ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. — PTM capture input TX PBS0 — CMOS UART TX serial data output PTP PBS0 — CMOS PTM output AN2 PBS0 AN PB3 PBPU PBS0 ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. RX PBS0 ST — UART RX serial data input AN3 PBS0 AN — A/D Converter analog input PB4 PBPU PBS1 ST PTPI PBS1 IFS ST CMOS General purpose I/O. Register enabled pull-up. — PTM capture input PTPB PBS1 — KEY1 PBS1 AN CMOS PTM inverted output — Touch key input AN4 PBS1 AN — A/D Converter analog input PB5 PBPU PBS1 ST STCK PBS1 ST — STM clock input KEY2 PBS1 AN — Touch key input AN5 PBS1 AN — A/D Converter analog input PB6 PBPU PBS1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. PTCK PBS1 ST — PTM clock input KEY3 PBS1 AN — Touch key input AN6 PBS1 AN — A/D Converter analog input PB7 PBPU PBS1 ST INT1 PBS1 INTEG INTC0 ST CMOS General purpose I/O. Register enabled pull-up. — External Interrupt 1 KEY4 PBS1 AN — Touch key input AN7 PBS1 AN — A/D Converter analog input PC0 PCPU PCS0 ST KEY5 PCS0 AN PC1 PCPU PCS0 ST KEY6 PCS0 AN PC2 PCPU PCS0 ST KEY7 PCS0 AN PC3 PCPU PCS0 ST KEY8 PCS0 AN CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input 23 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PC4/KEY9 PC5/KEY10 PC6/KEY11 PC7/KEY12 PD0/KEY13 PD1/KEY14 PD2/KEY15 PD3/KEY16 PD4/KEY17 PD5/KEY18 PD6/KEY19 PD7/KEY20 PE0/KEY21 PE1/KEY22 PE2/STPI/ STP/KEY23 Rev. 1.40 Function OPT I/T PC4 PCPU PCS1 ST KEY9 PCS1 AN PC5 PCPU PCS1 ST KEY10 PCS1 AN PC6 PCPU PCS1 ST KEY11 PCS1 AN PC7 PCPU PCS1 ST KEY12 PCS1 AN PD0 PDPU PDS0 ST KEY13 PDS0 AN PD1 PDPU PDS0 ST KEY14 PDS0 AN PD2 PDPU PDS0 ST KEY15 PDS0 AN PD3 PDPU PDS0 ST KEY16 PDS0 AN PD4 PDPU PDS1 ST KEY17 PDS1 AN PD5 PDPU PDS1 ST KEY18 PDS1 AN PD6 PDPU PDS1 ST KEY19 PDS1 AN PD7 PDPU PDS1 ST KEY20 PDS1 AN PE0 PEPU PES0 ST KEY21 PES0 AN PE1 PEPU PES0 ST KEY22 PES0 AN PE2 PEPU PES0 ST STPI PES0 IFS ST STP PES0 — KEY23 PES0 AN O/T Description CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — STM capture input CMOS STM output — Touch key input 24 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PE3/STPI/ STPB/KEY24 PE4/OSC1 PE5/CTCK1/ OSC2 PE6/CTP1/ KEY25 Function OPT I/T PE3 PEPU PES0 ST STPI PES0 IFS ST O/T Description CMOS General purpose I/O. Register enabled pull-up. — STM capture input STPB PES0 — KEY24 PES0 AN CMOS STM inverted output PE4 PEPU PES1 ST OSC1 PES1 HXT PE5 PEPU PES1 ST CTCK1 PES1 ST — CTM1 clock input OSC2 PES1 — HXT HXT oscillator pin PE6 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS CTM1 output — Touch key input CMOS General purpose I/O. Register enabled pull-up. — HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. CTP1 PES1 — KEY25 PES1 AN PE7 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CTP1B PES1 — CMOS CTM1 inverted output KEY26 PES1 AN PF0 PFPU PFS0 ST KEY27 PFS0 AN PF1 PFPU PFS0 ST KEY28 PFS0 AN PF2~PF5 PFn PFPU ST VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply, ground. PE7/CTP1B/ KEY26 PF0/KEY27 PF1/KEY28 — — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. Legend: I/T: Input type; OPT: Optional by register option; ST: Schmitt Trigger input; CMOS: CMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator Rev. 1.40 Touch key input O/T: Output type; PWR: Power; AN: Analog signal; NMOS: NMOS output; 25 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F370 Pad Name PA0/SDO/ ICPDA/ OCDSDA PA1/CTP0 PA2/SCS/ ICPCK/ OCDSCK PA3/SCS/XT1 PA4/SDO/ XT2 PA5/CTP0B PA6/CTCK0/ INT0 PA7 PB0/VREF/ SDI/SDA/ AN0 PB1/SCK/ SCL/AN1 Rev. 1.40 Function OPT I/T PA0 PAWU PAPU PAS0 O/T Description ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output SDO PAS0 — ICPDA — ST CMOS ICP Data/Address pin OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only. PA1 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA2 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select CMOS ICP Clock pin ICPCK — ST OCDSCK — ST PA3 PAWU PAPU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT PA4 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT2 PAS1 — PA5 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inverted output PA6 PAWU PAPU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 clock input INT0 PAS1 INTEG INTC0 ST — External Interrupt 0 PA7 PAWU PAPU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PB0 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. — — LXT — OCDS Clock pin, for EV chip only. LXT oscillator pin LXT oscillator pin SDI PBS0 ST SDA PBS0 ST SPI data input VREF PBS0 — AN A/D Converter reference voltage output AN0 PBS0 AN — A/D Converter analog input PB1 PBPU PBS0 ST NMOS I2C data line CMOS General purpose I/O. Register enabled pull-up. SCK PBS0 ST CMOS SPI serial clock SCL PBS0 ST NMOS I2C clock line AN1 PBS0 AN — A/D Converter analog input 26 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PB2/PTPI/ TX/PTP/AN2 PB3/RX/AN3 PB4/PTPI/ PTPB/KEY1/ AN4 PB5/STCK/ KEY2/AN5 PB6/PTCK/ KEY3/AN6 PB7/INT1/ KEY4/AN7 PC0/KEY5 PC1/KEY6 PC2/KEY7 PC3/KEY8 PC4/KEY9 Rev. 1.40 Function OPT I/T PB2 PBPU PBS0 ST PTPI PBS0 IFS ST O/T Description CMOS General purpose I/O. Register enabled pull-up. — PTM capture input TX PBS0 — CMOS UART TX serial data output PTP PBS0 — CMOS PTM output AN2 PBS0 AN PB3 PBPU PBS0 ST — A/D Converter analog input CMOS General purpose I/O. Register enabled pull-up. RX PBS0 ST — UART RX serial data input AN3 PBS0 AN — A/D Converter analog input PB4 PBPU PBS1 ST PTPI PBS1 IFS ST CMOS General purpose I/O. Register enabled pull-up. — PTM capture input PTPB PBS1 — KEY1 PBS1 AN CMOS PTM inverted output — Touch key input AN4 PBS1 AN — A/D Converter analog input PB5 PBPU PBS1 ST STCK PBS1 ST — STM clock input KEY2 PBS1 AN — Touch key input AN5 PBS1 AN — A/D Converter analog input PB6 PBPU PBS1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS General purpose I/O. Register enabled pull-up. PTCK PBS1 ST — PTM clock input KEY3 PBS1 AN — Touch key input AN6 PBS1 AN — A/D Converter analog input PB7 PBPU PBS1 ST INT1 PBS1 INTEG INTC0 ST CMOS General purpose I/O. Register enabled pull-up. — External Interrupt 1 KEY4 PBS1 AN — Touch key input AN7 PBS1 AN — A/D Converter analog input PC0 PCPU PCS0 ST KEY5 PCS0 AN PC1 PCPU PCS0 ST KEY6 PCS0 AN PC2 PCPU PCS0 ST KEY7 PCS0 AN PC3 PCPU PCS0 ST KEY8 PCS0 AN PC4 PCPU PCS1 ST KEY9 PCS1 AN CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input 27 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PC5/KEY10 PC6/KEY11 PC7/KEY12 PD0/KEY13 PD1/KEY14 PD2/KEY15 PD3/KEY16 PD4/KEY17 PD5/KEY18 PD6/KEY19 PD7/KEY20 PE0/KEY21 PE1/KEY22 PE2/STPI/ STP/KEY23 PE3/STPI/ STPB/KEY24 Rev. 1.40 Function OPT I/T PC5 PCPU PCS1 ST KEY10 PCS1 AN PC6 PCPU PCS1 ST KEY11 PCS1 AN PC7 PCPU PCS1 ST KEY12 PCS1 AN PD0 PDPU PDS0 ST KEY13 PDS0 AN PD1 PDPU PDS0 ST KEY14 PDS0 AN PD2 PDPU PDS0 ST KEY15 PDS0 AN PD3 PDPU PDS0 ST KEY16 PDS0 AN PD4 PDPU PDS1 ST KEY17 PDS1 AN PD5 PDPU PDS1 ST KEY18 PDS1 AN PD6 PDPU PDS1 ST KEY19 PDS1 AN PD7 PDPU PDS1 ST KEY20 PDS1 AN PE0 PEPU PES0 ST KEY21 PES0 AN PE1 PEPU PES0 ST KEY22 PES0 AN PE2 PEPU PES0 ST STPI PES0 IFS ST STP PES0 — KEY23 PES0 AN PE3 PEPU PES0 ST STPI PES0 IFS ST STPB PES0 — KEY24 PES0 AN O/T Description CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — STM capture input CMOS STM output — Touch key input CMOS General purpose I/O. Register enabled pull-up. — STM capture input CMOS STM inverted output — Touch key input 28 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name PE4/OSC1 PE5/CTCK1/ OSC2 PE6/CTP1/ KEY25 PE7/CTP1B/ KEY26 PF0/KEY27 PF1/KEY28 Function OPT I/T PE4 PEPU PES1 O/T Description ST OSC1 PES1 HXT PE5 PEPU PES1 ST CTCK1 PES1 ST — CTM1 clock input OSC2 PES1 — HXT HXT oscillator pin PE6 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CMOS CTM1 output CMOS General purpose I/O. Register enabled pull-up. — HXT oscillator pin CMOS General purpose I/O. Register enabled pull-up. CTP1 PES1 — KEY25 PES1 AN PE7 PEPU PES1 ST CMOS General purpose I/O. Register enabled pull-up. CTP1B PES1 — CMOS CTM1 inverted output KEY26 PES1 AN PF0 PFPU PFS0 ST KEY27 PFS0 AN PF1 PFPU PFS0 ST — — Touch key input Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. KEY28 PFS0 AN PF2 PF2 PFPU ST CMOS General purpose I/O. Register enabled pull-up. PF3 PF3 PFPU ST CMOS General purpose I/O. Register enabled pull-up. PF4 PF4 PFPU ST CMOS General purpose I/O. Register enabled pull-up. PF5 PF5 PFPU ST CMOS General purpose I/O. Register enabled pull-up. PG0 PGPU PGS0 ST CMOS General purpose I/O. Register enabled pull-up. KEY29 PGS0 AN PG1 PGPU PGS0 ST KEY30 PGS0 AN PG2 PGPU PGS0 ST KEY31 PGS0 AN PG3 PGPU PGS0 ST KEY32 PGS0 AN PG4 PGPU PGS1 ST KEY33 PGS1 AN PG5 PGPU PGS1 ST KEY34 PGS1 AN PG6 PGPU PGS1 ST KEY35 PGS1 AN PG7 PGPU PGS1 ST PG0/KEY29 PG1/KEY30 PG2/KEY31 PG3/KEY32 PG4/KEY33 PG5/KEY34 PG6/KEY35 PG7/KEY36 — — Touch key input Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. — Touch key input CMOS General purpose I/O. Register enabled pull-up. KEY36 PGS1 AN PH0 PH0 PHPU ST CMOS General purpose I/O. Register enabled pull-up. PH1 PH1 PHPU ST CMOS General purpose I/O. Register enabled pull-up. Rev. 1.40 — Touch key input 29 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Function OPT I/T PH2 Pad Name PH2 PHPU ST CMOS General purpose I/O. Register enabled pull-up. O/T PH3 PH3 PHPU ST CMOS General purpose I/O. Register enabled pull-up. PH4 PH4 PHPU ST CMOS General purpose I/O. Register enabled pull-up. PH5 PH5 PHPU ST CMOS General purpose I/O. Register enabled pull-up. VDD, VDD1 VDD — PWR — Positive power supply VSS, VSS1 VSS — PWR — Negative power supply, ground. Legend: I/T: Input type; OPT: Optional by register option; ST: Schmitt Trigger input; CMOS: CMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator Description O/T: Output type; PWR: Power; AN: Analog signal; NMOS: NMOS output; Absolute Maximum Ratings Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V Storage Temperature .................................................................................................. -50°C to 125°C Operating Temperature . ............................................................................................... -40°C to 85°C IOH Total.....................................................................................................................................-80mA IOL Total . .................................................................................................................................... 80mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol Parameter Operating Voltage (HXT) Test Conditions ─ VDD Operating Voltage (HIRC) Rev. 1.40 Min. Typ. Max. Unit fSYS=8MHz 2.2 ─ 5.5 V fSYS=12MHz 2.7 ─ 5.5 V fSYS=16MHz 3.3 ─ 5.5 V fSYS=8MHz 2.2 ─ 5.5 V fSYS=12MHz 2.7 ─ 5.5 V fSYS=16MHz 3.3 ─ 5.5 V VDD ─ Conditions 30 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Symbol Parameter Test Conditions 3V 5V 3V Operating Current (HXT) 5V 3V 5V 5V 3V IDD 5V Operating Current (HIRC) 3V 5V 5V Operating Current (LXT) Operating Current (LIRC) Standby Current (IDLE0 Mode) ISTB Standby Current (IDLE1 Mode) Min. Typ. Max. fSYS=fH=4MHz No load, all peripherals off ─ 500 750 μA ─ 1.0 1.5 mA fSYS=fH=8MHz No load, all peripherals off ─ 1.0 1.5 mA ─ 2.0 3.0 mA fSYS=fH=12MHz No load, all peripherals off ─ 1.5 2.75 mA ─ 3.0 4.5 mA ─ 3.6 5.4 mA fSYS=fH=8MHz No load, all peripherals off ─ 0.8 1.2 mA ─ 1.6 2.4 mA fSYS=fH=12MHz No load, all peripherals off ─ 1.2 1.8 mA ─ 2.4 3.6 mA ─ 3.2 4.8 mA fSYS=fSUB=fLXT=32.768kHz No load, all peripherals off ─ 10 20 μA ─ 30 50 μA fSYS=fSUB=fLIRC=32kHz No load, all peripherals off ─ 10 20 μA ─ 30 50 μA fSYS off, fSUB on, No load, all peripherals off, WDT enabled ─ 1.3 3.0 μA ─ 2.4 5.0 μA fSYS=12MHz on, fSUB on, No load, all peripherals off, WDT enabled ─ 0.9 1.4 mA ─ 1.4 2.1 mA ─ 1.2 1.8 μA VDD 3V 5V 3V 5V 3V 5V 3V 5V 3V Conditions fSYS=fH=16MHz, no load, all peripherals off fSYS=fH=16MHz, no load, all peripherals off Unit 5V fSYS off, fSUB off, No load, all peripherals off, WDT enabled ─ 1.8 2.7 μA VIL Input Low Voltage for I/O Ports or Input Pins 5V ─ 0 ─ 1.5 V ─ ─ 0 ─ 0.2VDD V VIH Input High Voltage for I/O Ports or Input Pins 5V ─ 3.5 ─ 5.0 V ─ ─ 0.8VDD ─ VDD V 17 34 ─ mA 34 68 ─ mA Standby Current (SLEEP Mode) IOL Sink Current for I/O Pins Source Current for I/O Pins 3V 5V 3V 5V 3V 5V IOH 3V Programming Source Current for I/O Pins * 5V 3V 5V 3V 5V RPH Pull-high Resistance for I/O Ports VOL=0.1VDD -5.5 -11.0 ─ mA -11.0 -22.0 ─ mA VOH=0.9VDD, PxPS[n+1:n]=00, x=A, B, C, G or H, n=0 or 2 -1.0 -2.0 ─ mA -2.0 -4.0 ─ mA VOH=0.9VDD, PxPS[n+1:n]=01, x=A, B, C, G or H, n=0 or 2 -1.75 -3.5 ─ mA -3.5 -7.0 ─ mA VOH=0.9VDD, PxPS[n+1:n]=10, x=A, B, C, G or H, n=0 or 2 -2.5 -5.0 ─ mA -5.0 -10.0 ─ mA VOH=0.9VDD VOH=0.9VDD, PxPS[n+1:n]=11, x=A, B, C, G or H, n=0 or 2 -5.5 -11.0 ─ mA -11.0 -22.0 ─ mA 3V ─ 20 60 100 kΩ 5V ─ 10 30 50 kΩ *Note: 1. The I/O pins with programming source current are PA1, PA5~PA7, PB4~PB7, PC0~PC3 for BS66F340. 2. The I/O pins with programming source current are PA1, PA5~PA7, PB4~PB7, PC0~PC7 for BS66F350/ BS66F360/BS66F370, PG0~PG3, PH0~PH3 for BS66F370. Rev. 1.40 31 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A.C. Characteristics Ta=25°C Symbol Parameter System Clock (HXT) fSYS System Clock (HIRC) Test Condition VDD Condition Min. Typ. Max. Unit 2.2~5.5V fSYS=fHXT=8MHz ─ 8 ─ MHz 2.7~5.5V fSYS=fHXT=12MHz ─ 12 ─ MHz 3.3~5.5V fSYS=fHXT=16MHz ─ 16 ─ MHz 2.2~5.5V fSYS=fHIRC=8MHz ─ 8 ─ MHz 2.7~5.5V fSYS=fHIRC=12MHz ─ 12 ─ MHz 3.3~5.5V fSYS=fHIRC=16MHz ─ 16 ─ MHz System Clock (LXT) 2.2~5.5V fSYS=fLXT=32.768kHz ─ 32.768 ─ kHz System Clock (LIRC) 2.2~5.5V fSYS=fLIRC=32kHz ─ 32 ─ kHz -2% 12 +2% MHz Ta=25°C 3V High Speed Internal RC Oscillator (HIRC) (12MHz trim at VDD=3V) fHIRC High Speed Internal RC Oscillator (HIRC) (12MHz Trim at VDD=5V) 3V ± 0.1V Ta=0°C~70°C -5% 12 +5% MHz 2.7V~5.5V Ta=0°C~70°C -7% 12 +7% MHz 2.7V~5.5V Ta=-40°C~85°C -10% 12 +10% MHz 3V Ta=25°C -20% 8 +20% MHz 3V Ta=25°C -20% 16 +20% MHz 5V Ta=25°C -2% 12 +2% 5V ± 0.1V Ta=0°C~70°C -5% 12 +5% MHz 2.7V~5.5V Ta=0°C~70°C -7% 12 +7% MHz 2.7V~5.5V Ta=-40°C~85°C MHz -10% 12 +10% MHz 5V Ta=25°C -20% 8 +20% MHz 5V Ta=25°C -20% 16 +20% MHz 5V Ta=25°C -10% 32 +10% kHz -40% 32 +40% kHz fLIRC Low Speed Internal RC Oscillator (LIRC) tTPI STPI, PTPI pin Minimum Input Pulse Width ─ ─ 0.3 ─ ─ μs tTCK CTCKn, STCK, PTCK pin Minimum Input Pulse Width ─ ─ 0.3 ─ ─ μs tINT Interrupt Pin Minimum Input Pulse Width ─ ─ 10 ─ ─ μs 128 ─ ─ tHXT tHIRC tSST System Start-up Timer Period (Wake-up from Power Down Mode and fSYS off) ─ fSYS=fH=fHXT~fHXT/64 ─ fSYS=fH=fHIRC~fHIRC/64 16 ─ ─ ─ fSYS=fSUB=fLXT 1024 ─ ─ tLXT ─ fSYS=fSUB=fLIRC 2 ─ ─ tLIRC System Start-up Timer Period (Wake-up from Power Down Mode and fSYS on) ─ fSYS=fH~fH/64, fH=fHXT or fHIRC 2 ─ ─ tH ─ fSYS=fSUB=fLXT or fLIRC 2 ─ ─ tSUB ─ fHXT off → on (HXTF=1) 1024 ─ ─ tHXT ─ fHIRC off → on (HIRCF=1) 16 ─ ─ tHIRC ─ fLXT off → on (LXTF=1) 1024 ─ ─ tLXT 0 ─ ─ tSYS System Start-up Timer Period (SLOW Mode → NORMAL Mode) (NORMAL Mode → SLOW Mode) System Start-up Timer period (WDT Hardware Reset) Rev. 1.40 2.2V~5.5V Ta=-40°C~85°C ─ ─ 32 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Symbol Test Condition Parameter Min. Typ. Max. Unit ─ 25 50 100 ms ─ ─ 8.3 16.7 33.3 ms EEPROM Read Time ─ ─ ─ ─ 4 tSYS EEPROM Write Time ─ ─ ─ 4 6 ms VDD Condition System Reset Delay Time (Power-on Reset, LVR Hardware reset, LVRC/WDTC/RSTC Software Reset) ─ System Reset Delay Time (WDT Hardware Reset) tEERD tEEWR tRSTD Note: tSYS= 1/fSYS A/D Converter Characteristics Operating Temperature: -40°C~85°C, unless otherwise specified. Symbol Test Conditions Parameter Conditions VDD Min. Typ. Max. Unit VDD Operating Voltage ─ ─ 2.7 ─ 5.5 V VADI Input Voltage ─ ─ 0 ─ VREF V VREF Reference Voltage ─ ─ 2 ─ VDD V VREF=VDD, tADCK=0.5μs or 10μs ─ ─ ±3 LSB VREF=VDD, tADCK=0.5μs or 10μs ─ ─ ±4 LSB ─ 1.0 2.0 mA ─ 1.5 3.0 mA 3V DNL Differential Non-linearity INL Integral Non-linearity IADC Additional Current Consumption for A/D Converter Enable 5V 3V 5V 3V 5V No load, tADCK=0.5μs ─ AN≠Temperature sensor output 0.5 ─ 10 μs ─ AN=Temperature sensor output 1 ─ 2 μs ─ tADCK tADCK Clock Period tADC Conversion Time (Including A/D Sample and Hold Time) ─ AN≠Temperature sensor output ─ 16 ─ AN=Temperature sensor output ─ 56 ─ tADCK tON2ST A/D Converter On-to-Start Time ─ ─ 4 ─ ─ μs Temperature Sensor Electrical Characteristics Ta=25°C, Operating Temperature: -40°C~85°C, unless otherwise specified. Symbol VDD VTSVREF Parameter Test Conditions Unit 2.7 ─ 5.5 V Ta=25°C, Trim @VDD=3V, K_VPTAT=0, K_REFO=0 -5% 2.01 +5% V Ta=25°C, VREF=VTSVREF, G5XEN=1, AN=Temperature sensor output 1990 2250 2600 LSB Ta=90°C, VREF=VTSVREF, G5XEN=1, AN=Temperature sensor output 3400 3850 4250 LSB Ta=-40°C, VREF=VTSVREF, G5XEN=1, AN=Temperature sensor output 550 720 995 LSB ─ ─ ─ 5 μs ─ ─ Temperature Sensor Reference Voltage 3V 5V A/D Conversion Code Range 3V 5V 3V 5V Rev. 1.40 Max. Operating Voltage 5V tTSS Typ. Conditions 3V CodeTS Min. VDD Temperature Sensor Turn on Stable Time 3V 5V 33 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD/LVR Electrical Characteristics Ta=25°C Symbol VLVR VLVD Parameter Low Voltage Reset Voltage Low Voltage Detector Voltage Test Conditions VDD ─ ─ Conditions Min. LVR Enable, voltage select 2.1V 2.1 LVR Enable, voltage select 2.55V 2.55 LVR Enable, voltage select 3.15V - 5% Bandgap Reference Voltage IOP LVD/LVR Operating Current tBGS VBG Turn on Stable Time tLVDS 3.15 LVR Enable, voltage select 3.8V 3.8 LVD Enable, voltage select 2.0V 2.0 LVD Enable, voltage select 2.2V 2.2 LVD Enable, voltage select 2.4V 2.4 LVD Enable, voltage select 2.7V LVD Enable, voltage select 3.0V - 5% 2.7 3.0 LVD Enable, voltage select 3.3V 3.3 LVD Enable, voltage select 3.6V 3.6 LVD Enable, voltage select 4.0V VBG Typ. ─ ─ Max. Unit + 5% V + 5% V V 4.0 - 5% 1.04 + 5% 5V LVD/LVR Enable, VBGEN=0 ─ 20 25 μA 5V LVD/LVR Enable, VBGEN=1 ─ 25 30 μA ─ No load ─ ─ 150 μs ─ For LVR enable, VBGEN=0, LVD off→on ─ ─ 15 μs ─ For LVR disable, VBGEN=0, LVD off→on ─ ─ 150 μs LVDO Stable Time tLVR Minimum Low Voltage Width to Reset ─ ─ 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt ─ ─ 60 120 240 μs Rev. 1.40 34 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Electrical Characteristics Ta=25°C Touch Key RC Oscillator 500kHz Mode Selected Symbol Parameter IKEYOSC Only Sensor (KEY) Oscillator Operating Current IREFOSC Only Reference Oscillator Operating Current Test Conditions VDD 3V 5V 3V 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitor 3V CREFOSC Reference Oscillator Internal Capacitor 3V fKEYOSC Sensor (KEY) Oscillator Operating Frequency 3V Reference Oscillator Operating Frequency 3V fREFOSC 5V 5V 5V 5V Conditions *fSENOSC = 500kHz *fREFOSC = 500kHz, MnTSS = 0 *fREFOSC = 500kHz, MnTSS = 1 *fSENOSC=500kHz *fSENOSC=500kHz Min. Typ. Max. — 30 60 — 60 120 — 30 60 — 60 120 Unit µA µA — 30 60 — 60 120 3 10 30 5 10 20 pF 3 10 30 pF µA pF 5 10 20 pF * CEXT=7, 8, 9, 10, 11, 12, 13, 14, 15, … 50pF 100 500 1000 kHz 100 500 1000 kHz * CINT=7, 8, 9, 10, 11, 12, 13, 14, 15, … 50pF 100 500 1000 kHz 100 500 1000 kHz Note: 1. fSENOSC = 500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 500kHz. 2. fREFOSC = 500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 500kHz. Touch Key RC Oscillator 1000kHz Mode Selected Symbol Parameter IKEYOSC Only Sensor (KEY) Oscillator Operating Current IREFOSC Only Reference Oscillator Operating Current Test Conditions VDD 3V 5V 3V 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitor 3V CREFOSC Reference Oscillator internal Capacitor 3V fKEYOSC Sensor (KEY) Oscillator Operating Frequency 3V Reference Oscillator Operating Frequency 3V fREFOSC 5V 5V 5V 5V Conditions *fSENOSC = 1000kHz *fREFOSC = 1000kHz, MnTSS = 0 *fREFOSC = 1000kHz, MnTSS = 1 *fSENOSC=1000kHz *fSENOSC=1000kHz * CEXT=3, 4, 5, 6, 7, 8, 9, … 50pF * CINT=3, 4, 5, 6, 7, 8, 9, … 50pF Min. Typ. Max. Unit — 40 80 — 80 160 — 40 80 — 80 160 — 40 80 — 80 160 3 10 25 pF 5 10 20 pF 3 10 25 pF 5 10 20 pF 150 1000 2000 kHz 150 1000 2000 kHz 150 1000 2000 kHz 150 1000 2000 kHz µA µA µA Note: 1. fSENOSC = 1000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 1000kHz. 2. fREFOSC = 1000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1000kHz. Rev. 1.40 35 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key RC Oscillator 1500kHz Mode Selected Symbol Parameter Only Sensor (KEY) Oscillator Operating Current IKEYOSC Test Conditions VDD 3V 5V 3V Only Reference Oscillator Operating Current IREFOSC 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitor 3V CREFOSC Reference Oscillator internal Capacitor 3V Sensor (KEY) Oscillator Operating Frequency 3V Reference Oscillator Operating Frequency 3V fKEYOSC fREFOSC 5V 5V 5V 5V Conditions *fSENOSC=1500kHz *fREFOSC=1500kHz, MnTSS=0 *fREFOSC=1500kHz, MnTSS=1 *fSENOSC=1500kHz *fSENOSC=1500kHz * CEXT=3, 4, 5, 6, 7, 8, 9, … 50pF * CEXT=3, 4, 5, 6, 7, 8, 9, … 50pF Min. Typ. Max. — 60 120 — 120 240 — 60 120 — 120 240 — 60 120 — 120 240 Unit µA µA µA 4 8 20 pF 5 10 20 pF 4 8 20 pF 5 10 20 pF 150 1500 3000 kHz 150 1500 3000 kHz 150 1500 3000 kHz 150 1500 3000 kHz Note: 1. fSENOSC=1500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 1500kHz. 2. fREFOSC=1500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1500kHz. Touch Key RC Oscillator 2000kHz Mode Selected Symbol IKEYOSC Parameter Only Sensor (KEY) Oscillator Operating Current Test Conditions VDD 3V 5V 3V IREFOSC Only Reference Oscillator Operating Current 5V 3V 5V CKEYOSC Sensor (KEY) Oscillator External Capacitor 3V CREFOSC Reference Oscillator Internal Capacitor 3V fKEYOSC Sensor (KEY) Oscillator Operating Frequency 3V Reference Oscillator Operating Frequency 3V fREFOSC 5V 5V 5V 5V Conditions *fSENOSC=2000kHz *fREFOSC=2000kHz, MnTSS=0 *fREFOSC=2000kHz, MnTSS=1 *fSENOSC=2000kHz *fSENOSC=2000kHz * CEXT=3, 4, 5, 6, 7, 8, 9, … 50pF * CEXT=3, 4, 5, 6, 7, 8, 9, … 50pF Min. Typ. Max. Unit — 80 160 — 160 320 — 80 160 — 160 320 — 80 160 — 160 320 4 8 20 pF 5 10 20 pF 4 8 20 pF 5 10 20 µA µA µA pF 150 2000 4000 kHz 150 2000 4000 kHz 150 2000 4000 kHz 150 2000 4000 kHz Note: 1. fSENOSC=2000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 2000kHz. 2. fREFOSC=2000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 2000kHz. Rev. 1.40 36 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset ─ ─ ─ ─ 100 mV RRPOR VDD Raising Rate to Ensure Power-on Reset ─ ─ 0.035 ─ ─ V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset ─ ─ 1 ─ ─ ms Rev. 1.40 37 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.40 38 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. For the device whose memory capacity is greater than 8K words the Program Memory address may be located in a certain program memory bank which is selected by the program memory bank pointer bit, PBP0 or PBP1. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Device High Byte Low Byte (PCL) BS66F340 PC11~PC8 PC7~PC0 BS66F350 PC12~PC8 PC7~PC0 BS66F360 PBP0, PC12~PC8 PC7~PC0 BS66F370 PBP0, PBP1, PC12~PC8 PC7~PC0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.40 39 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�a� Counte� Top of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Pointe� Sta�k Level 3 Botto� of Sta�k Sta�k Level N : : : P�og�a� Me�o�y Note: N=8 for BS66F340/BS66F350, N=12 for BS66F360 while N=16 for BS66F370 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC • Increment and Decrement: INCA, INC, DECA, DEC LINCA, LINC, LDECA, LDEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA Rev. 1.40 40 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity Banks BS66F340 4K × 16 — BS66F350 8K × 16 — BS66F360 16K × 16 0~1 BS66F370 32K × 16 0~3 Structure The Program Memory has a capacity of 4K×16 to 32K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer registers. 000H BS66F340 BS66F350 BS66F360 BS66F370 Initialisation Ve�to� Initialisation Ve�to� Initialisation Ve�to� Initialisation Ve�to� Inte��upt Ve�to�s Inte��upt Ve�to�s Inte��upt Ve�to�s Inte��upt Ve�to�s Look-up Ta�le Look-up Ta�le Look-up Ta�le Look-up Ta�le Bank 1 Bank 1 004H 0�CH n00H nFFH FFFH 1� �its 1FFFH 1� �its �000H 3FFFH 1� �its 4000H Bank � �FFFH �000H Bank 3 7FFFH 1� �its Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Rev. 1.40 41 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors except sector 0, the data can be retrieved from the program memory using the corresponding extended table read instruction such as "LTABRD [m]" or "LTABRDL [m]" respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is "0F00H" which refers to the start address of the last page within the 4K Program Memory of the BS66F340 device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page pointed by the TBHP register if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m] instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.40 42 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,0fh ; initialise high table pointer mov tbhp,a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0F06H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "0F05H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 : org 0F00h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller incircuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and reinsertion of the device. Holtek Writer Pins MCU Programming Pins ICPDA PA0 Programming Serial Data/Address Pin Description ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins. Rev. 1.40 43 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver W r ite r C o n n e c to r S ig n a ls M C U W r ite r _ V D D V D D IC P D A P A 0 IC P C K P A 2 W r ite r _ V S S V S S * P r o g r a m m in g P in s * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named BS66V3x0 which is used to emulate the real MCU device named BS66F3x0. The EV chip device also provides the "On-Chip Debug" function to debug the real MCU device during development process. The EV chip and real MCU devices, BS66V3x0 and BS66F3x0, are almost functional compatible except the "On-Chip Debug" function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins Rev. 1.40 EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground 44 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In Application Programming – IAP These devices offer IAP function to update data or application program to flash ROM. Users can define any ROM location for IAP, but there are some features which user must notice in using IAP function. Note that the BS66F340 device supports the "Block Erase" function instead of the "Page Erase" function. BS66F340 Configurations BS66F350 Configurations BS66F360/370 Configurations Erase Block 256 words / block Erase Page 32 words / page Erase Page 64 words / page Writing Word 4 words / time Writing Word 32 words / time Writing Word 64 words / time Reading Word 1 word / time Reading Word 1 word / time Reading Word 1 word / time In Application Programming Control Registers The Address register, FARL and FARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access registers located in Data Memory sector 0 for IAP. If using the indirect addressing method to access the FC0, FC1 and FC2 registers, all read and write operations to the registers must be performed using the Indirect Addressing Register, IAR1 or IAR2, and the Memory Pointer pair, MP1L/MP1H or MP2L/MP2H. Because the FC0, FC1 and FC2 control registers are located at the address of 50H~52H in Data Memory sector 0, the desired value ranged from 50H to 52H must first be written into the MP1L or MP2L Memory Pointer low byte and the value "00H" must also be written into the MP1H or MP2H Memory Pointer high byte. Register Name FC0 Bit 7 6 5 4 3 CFWEN FMOD2 FMOD1 FMOD0 FWPEN 2 1 0 FWT FRDEN FRD FC1 D7 D6 D5 D4 D3 D2 D1 D0 FC2 (BS66F350/360/370) — — — — — — — CLWB FARL A7 A6 A5 A4 A3 A2 A1 A0 FARH (BS66F340) — — — — A11 A10 A9 A8 FARH (BS66F350) — — — A12 A11 A10 A9 A8 FARH (BS66F360) — — A13 A12 A11 A10 A9 A8 FARH (BS66F370) — A14 A13 A12 A11 A10 A9 A8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 D8 FD1H D15 D14 D13 D12 D11 D10 D9 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 IAP Registers List Rev. 1.40 45 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • FC0 Register Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 FWPEN FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 0 0 0 0 Bit 7 CFWEN: Flash Memory Write enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a "1" into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the Flash memory write function is enabled successfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. Bit 6~4 FMOD2~FMOD0: Mode selection 000: Write program memory 001: Block/Page erase program memory 010: Reserved 011: Read program memory 10x: Reserved 110: FWEN mode – Flash memory Write function Enabled mode 111: Reserved When these bits are set to "001", the "Block erase" mode is selected for BS66F340 while the "Page erase" mode is selected for BS66F350/BS66F360/BS66F370. Bit 3 FWPEN: Flash memory Write Procedure Enable control 0: Disable 1: Enable When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will execute the "Flash memory write function enable" procedure. Once the Flash memory write function is successfully enabled, it is not necessary to set the FWPEN bit any more. Bit 2 FWT: Flash memory Write Initiate control 0: Do not initiate Flash memory write or Flash memory write process is completed 1: Initiate Flash memory write process This bit is set by software and cleared by hardware when the Flash memory write process is completed. Bit 1 FRDEN: Flash memory Read Enable control 0: Flash memory read disable 1: Flash memory read enable Bit 0 FRD: Flash memory Read Initiate control 0: Do not initiate Flash memory read or Flash memory read process is completed 1: Initiate Flash memory read process This bit is set by software and cleared by hardware when the Flash memory read process is completed. • FC1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 D7~D0: Whole chip reset pattern When user writes a specific value of "55H" to this register, it will generate a reset signal to reset whole chip. 46 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • FC2 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Name — — — — — — — CLWB R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as 0. Bit 0 CLWB: Flash memory Write Buffer Clear control 0: Do not initiate Write Buffer Clear process or Write Buffer Clear process is completed 1: Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process is completed. • FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Flash Memory Address bit 7 ~ bit 0 • FARH Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Name — — — — A11 A10 A9 A8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~0 Flash Memory Address bit 11 ~ bit 8 • FARH Register – BS66F350 Bit 7 6 5 4 3 2 1 0 Name — — — A12 A11 A10 A9 A8 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as 0. Bit 4~0 Flash Memory Address bit 12 ~ bit 8 • FARH Register – BS66F360 Bit 7 6 5 4 3 2 1 0 Name — — A13 A12 A11 A10 A9 A8 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 3 2 1 0 Bit 7~6 Unimplemented, read as 0. Bit 5~0 Flash Memory Address bit 13 ~ bit 8 • FARH Register – BS66F370 Bit 6 5 4 Name — A14 A13 A12 A11 A10 A9 A8 R/W — R/W R/W R/W R/W R/W R/W R/W — 0 0 0 0 0 0 0 POR Rev. 1.40 7 Bit 7 Unimplemented, read as 0. Bit 6~0 Flash Memory Address bit 14 ~ bit 8 47 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 7 ~ bit 0 • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 15 ~ bit 8 • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 7 ~ bit 0 • FD1H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 15 ~ bit 8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 7 ~ bit 0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 15 ~ bit 8 • FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 The fourth Flash Memory data bit 7 ~ bit 0 48 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 15 ~ bit 8 Flash Memory Write Function Enable Procedure In order to allow users to change the Flash memory data through the IAP control registers, users must first enable the Flash memory write operation by the following procedure: 1. Write "110" into the FMOD2~FMOD0 bits to select the FWEN mode. 2. Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously. 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H~FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. Then the FWPEN bit will automatically be cleared to 0 by hardware. 6. If the pattern data is correct before the counter overflows, the Flash memory write operation will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully enabled. 7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data through the Flash control register. 8. To disable the Flash memory write operation, the user can clear the CFWEN bit to 0. Is �ounte� ove�flow ? Flash Me�o�y W�ite Fun�tion Ena�le P�o�edu�e No Yes FWPEN=0 Set FMOD [�:0] =110 & FWPEN=1 Sele�t FWEN �ode & Sta�t Flash w�ite Ha�dwa�e a�tivate a �ounte� Is patte�n �o��e�t ? W�tie the following patte�n to Flash Data �egiste�s FD1L= 00h � FD1H = 04h FD�L= 0Dh � FD�H = 09h FD3L= C3h � FD3H = 40h No Yes CFWEN = 1 CFWEN=0 Su��ess Failed END Flash Memory Write Function Enable Procedure Rev. 1.40 49 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Flash Memory Read/Write Procedure After the Flash memory write function is successfully enabled through the preceding IAP procedure, users must first erase the corresponding Flash memory block or page and then initiate the Flash memory write operation. For the BS66F340 device the number of the block erase operation is 256 words per block, the available block erase address is only specified by FARH register and the content in the FARL register is not used to specify the block address. For the BS66F350, BS66F360 and BS66F370 devices the number of the page erase operation is 32, 64 and 64 words per page respectively, the available page erase address is specified by FARH register and the content of FARL [7:5] and FARL [7:6] bit field respectively. Erase Block FARH [3:0] FARL [7:0] 0 0000 xxxx xxxx 1 0001 xxxx xxxx 2 0010 xxxx xxxx 3 0011 xxxx xxxx 4 0100 xxxx xxxx 5 0101 xxxx xxxx 6 0110 xxxx xxxx 7 0111 xxxx xxxx 8 1000 xxxx xxxx 9 1001 xxxx xxxx 10 1010 xxxx xxxx 11 1011 xxxx xxxx 12 1100 xxxx xxxx 13 1101 xxxx xxxx 14 1110 xxxx xxxx 15 1111 xxxx xxxx "x": don’t care BS66F340 Erase Block Number and Selection Erase Page FARH FARL [7:5] 0 0000 0000 000 FARL [4:0] x xxxx 1 0000 0000 001 x xxxx 2 0000 0000 010 x xxxx 3 0000 0000 011 x xxxx 4 0000 0000 100 x xxxx 5 0000 0000 101 x xxxx 6 0000 0000 110 x xxxx 7 0000 0000 111 x xxxx 8 0000 0001 000 x xxxx 9 0000 0001 001 x xxxx : : : : 126 0000 1111 110 x xxxx 127 0000 1111 111 x xxxx 128 0001 0000 000 x xxxx 129 0001 0000 001 x xxxx : : : : 254 0001 1111 110 x xxxx 255 0001 1111 111 x xxxx "x": don’t care BS66F350 Erase Page Number and Selection Rev. 1.40 50 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Erase Page FARH FARL [7:6] 0 0000 0000 00 FARL [5:0] xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 5 0000 0001 01 xx xxxx : : : : 126 0001 1111 10 xx xxxx 127 0001 1111 11 xx xxxx 128 0010 0000 00 xx xxxx 129 0010 0000 01 xx xxxx : : : : 254 0011 1111 10 xx xxxx 255 0011 1111 11 xx xxxx "x": don’t care BS66F360 Erase Page Number and Selection Erase Page FARH FARL [7:6] FARL [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 5 0000 0001 01 xx xxxx : : : : : : : : 126 0001 1111 10 xx xxxx 127 0001 1111 11 xx xxxx 128 0010 0000 00 xx xxxx 129 0010 0000 01 xx xxxx : : : : : : : : 254 0011 1111 10 xx xxxx 255 0011 1111 11 xx xxxx 256 0100 0000 00 xx xxxx 257 0100 0000 01 xx xxxx : : : : : : : : 510 0111 1111 10 xx xxxx 511 0111 1111 11 xx xxxx "x": don’t care BS66F370 Erase Page Number and Selection Rev. 1.40 51 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Read Flash Me�o�y Set FMOD [�:0]=011 & FRDEN=1 Set Flash Add�ess �egiste�s FARH=xxh� FARL=xxh Set FRD=1 No FRD=0 ? Yes Read data value: FD0L=xxh� FD0H=xxh Read Finish ? No Yes Clea� FRDEN �it END Read Flash Memory Procedure Rev. 1.40 52 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Write Flash Memory Flash Memory Write Function Enable Procedure Set Block Erase address: FARH/FARL Set FMOD [2:0]=001 & FWT=1 à Select “Block Erase mode” & Initiate write operation No FWT=0 ? Yes Set FMOD [2:0]=000 à Select “Write Flash Mode” Set Write starting address: FARH/FARL Write data to data register: FD0L/FD0H, FD1L/FD1H, FD2L/FD2H, FD3L/FD3H, Set FWT=1 No FWT=0 ? Yes Write Finish ? No Yes Clear CFWEN=0 END Write Flash Memory Procedure – BS66F340 Rev. 1.40 53 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Write Flash Memory Flash Memory Write Function Enable Procedure Set Page Erase address: FARH/FARL Set FMOD [2:0]=001 & FWT=1 à Select “Page Erase mode” & Initiate write operation No FWT=0 ? Yes Set FMOD [2:0]=000 à Select “Write Flash Mode” Set Write starting address: FARH/FARL Write data to data register: FD0L/FD0H No Page data Write finish Yes Set FWT=1 No FWT=0 ? Yes Write Finish ? No Yes Clear CFWEN=0 END Write Flash Memory Procedure – BS66F350/BS66F360/BS66F370 Note: When the FWT or FRD bit is set to 1, the MCU is stopped. Rev. 1.40 54 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Switching between the different Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH. The General Purpose Data Memory address range is from 80H to FFH except the Touch Key Module Data Memory. The Touch Key Modul Data Memory is located in sector 5 and sector 6 respectively with a start address of 00H. Device Special Purpose Data Memory General Purpose Data Memory Touch Key Module Data Memory Located Sectors Capacity Sector : Address Sector : Address BS66F340 0, 1 512 x 8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 3: 80H~FFH 5: 00H~17H 6: 00H~17H BS66F350 0, 1 768 x 8 0: 80H~FFH 1: 80H~FFH : 5: 80H~FFH 5: 00H~27H 6: 00H~27H BS66F360 0, 1 1024 x 8 0: 80H~FFH 1: 80H~FFH : 7: 80H~FFH 5: 00H~37H 6: 00H~37H 1536 x 8 0: 80H~FFH 1: 80H~FFH : 11: 80H~FFH 5: 00H~47H 6: 00H~47H BS66F370 0, 1 Data Memory Summary Rev. 1.40 55 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H Spe�ial Pu�pose Data Me�o�y (Se�to� 0 ~ Se�to� 1) Tou�h Key Module Data Me�o�y 7FH 80H (Se�to� �~Se�to� �) Gene�al Pu�pose Data Me�o�y (Se�to� 0 ~ Se�to� N) FFH Se�to� 0 Se�to� 1 Se�to� N Note: N=3 fo� BS��F340; N=� fo� BS��F3�0; N=7 fo� BS��F3�0; N=11 fo� BS��F370 Data Memory Structure Data Memory Addressing For these devices that support the extended instructions, there is no Bank Pointer for Data Memory. The Bank Pointer, PBP, is only available for Program Memory. For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. For the accessed data memory which is located in any data memory sectors except sector 0, the extended instructions can be used to access the data memory instead of using the indirect addressing access. The main difference between standard instructions and extended instructions is that the data memory address "m" in the extended instructions can be from 10 bits to 11 bits depending upon which device is selected, the high byte indicates a sector and the low byte indicates a specific address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.40 56 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS IAR2 MP2L MP2H RSTFC INTC0 INTC1 INTC2 PA PAC PAPU PAWU PB PBC PBPU INTEG SCC HIRCC HXTC LXTC LVDC LVRC WDTC RSTC PC PCC PCPU Sector 1 TKTMR TKC0 TK16DL TK16DH TKC1 TKM016DL TKM016DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C2 TKM116DL TKM116DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C2 TKM216DL TKM216DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 TKM2C2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH MFI0 MFI1 MFI2 MFI3 ADRL ADRH ADCR0 ADCR1 PSCR0 TB0C TB1C SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH Sector 0 EEA Sector 1 EEC EED PSCR1 SLEDC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH FC0 FC1 IFS PAS0 PAS1 PBS0 PBS1 PCS0 PES0 PES1 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC2 TSC3 PE PEC PEPU USR UCR1 UCR2 TXR_RXR BRG 7FH : Unused, read as 00H Special Purpose Data Memory Structure – BS66F340 Rev. 1.40 57 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS IAR2 MP2L MP2H RSTFC INTC0 INTC1 INTC2 PA PAC PAPU PAWU PB PBC PBPU INTEG SCC HIRCC HXTC LXTC LVDC LVRC WDTC RSTC PC PCC PCPU PD PDC PDPU MFI0 MFI1 MFI2 MFI3 ADRL ADRH ADCR0 ADCR1 PSCR0 TB0C TB1C SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH Sector 1 TKTMR TKC0 TK16DL TK16DH TKC1 TKM016DL TKM016DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C2 TKM116DL TKM116DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C2 TKM216DL TKM216DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 TKM2C2 TKM316DL TKM316DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C2 TKM416DL TKM416DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH Sector 0 EEA Sector 1 EEC EED PSCR1 SLDEC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC2 TSC3 IFS PAS0 PAS1 PBS0 PBS1 PCS0 PCS1 PDS0 PDS1 PES0 PES1 PE PEC PEPU USR UCR1 UCR2 TXR_RXR BRG 7FH : Unused, read as 00H Special Purpose Data Memory Structure – BS66F350 Rev. 1.40 58 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS PBP IAR2 MP2L MP2H RSTFC INTC0 INTC1 INTC2 PA PAC PAPU PAWU PB PBC PBPU INTEG SCC HIRCC HXTC LXTC LVDC LVRC WDTC RSTC PC PCC PCPU PD PDC PDPU MFI0 MFI1 MFI2 MFI3 ADRL ADRH ADCR0 ADCR1 PSCR0 TB0C TB1C SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH Sector 1 TKTMR TKC0 TK16DL TK16DH TKC1 TKM016DL TKM016DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C2 TKM116DL TKM116DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C2 TKM216DL TKM216DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 TKM2C2 TKM316DL TKM316DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C2 TKM416DL TKM416DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C2 TKM516DL TKM516DH TKM5ROL TKM5ROH TKM5C0 TKM5C1 TKM5C2 TKM616DL TKM616DH TKM6ROL TKM6ROH TKM6C0 TKM6C1 TKM6C2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH Sector 0 EEA Sector 1 EEC EED PSCR1 SLEDC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC2 TSC3 IFS PAS0 PAS1 PBS0 PBS1 PCS0 PCS1 PDS0 PDS1 PES0 PES1 PFS0 PE PEC PEPU PF PFC PFPU USR UCR1 UCR2 TXR_RXR BRG 7FH : Unused, read as 00H Special Purpose Data Memory Structure – BS66F360 Rev. 1.40 59 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Sector 0 IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP STATUS PBP IAR2 MP2L MP2H RSTFC INTC0 INTC1 INTC2 PA PAC PAPU PAWU PB PBC PBPU INTEG SCC HIRCC HXTC LXTC LVDC LVRC WDTC RSTC PC PCC PCPU PD PDC PDPU MFI0 MFI1 MFI2 MFI3 ADRL ADRH ADCR0 ADCR1 PSCR0 TB0C TB1C SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH Sector 1 TKTMR TKC0 TK16DL TK16DH TKC1 TKM016DL TKM016DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C2 TKM116DL TKM116DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C2 TKM216DL TKM216DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 TKM2C2 TKM316DL TKM316DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C2 TKM416DL TKM416DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C2 TKM516DL TKM516DH TKM5ROL TKM5ROH TKM5C0 TKM5C1 TKM5C2 TKM616DL TKM616DH TKM6ROL TKM6ROH TKM6C0 TKM6C1 TKM6C2 TKM716DL TKM716DH TKM7ROL TKM7ROH TKM7C0 TKM7C1 TKM7C2 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Sector 0 EEA EED PSCR1 SLEDC SLEDC1 PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH FC0 FC1 FC2 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC2 TSC3 Sector 1 EEC IFS PAS0 PAS1 PBS0 PBS1 PCS0 PCS1 PDS0 PDS1 PES0 PES1 PFS0 PGS0 PGS1 PH PHC PHPU TKM816DL TKM816DH TKM8ROL TKM8ROH TKM8C0 TKM8C1 TKM8C2 PE PEC PEPU PF PFC PFPU USR UCR1 UCR2 TXR_RXR BRG PG PGC PGPU : Unused, read as 00H Special Purpose Data Memory Structure – BS66F370 Rev. 1.40 60 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/ MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. Indirect Addressing Program Example • Example 1 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; mov block,a mov a,offset adres1 ; mov mp0,a ; loop: clr IAR0 ; inc mp0; sdz block ; jmp loop continue: : Rev. 1.40 setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared 61 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block mov block,a mov a,01h ; setup the memory sector mov mp1h,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1 inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: : The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Direct Addressing Program Example using extended instructions data .section ‘data’ temp db ? code .section at 0 code org 00h start: lmov a,[m]; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c; [m]>[m+1]? jmp continue; no lmov a,[m] ; yes, exchange [m] and [m+1] data mov temp,a lmov a,[m+1] lmov [m],a mov a,temp lmov [m+1],a continue: : Note: Here "m" is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1. Rev. 1.40 62 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Program Memory Bank Pointer – PBP For the BS66F360 and BS66F370 device the Program Memory is divided into several banks. Selecting the required Program Memory area is achieved using the Program Memory Bank Pointer, PBP. The PBP register should be properly configured before the device executes the "Branch" operation using the "JMP" or "CALL" instruction. After that a jump to a non-consecutive Program Memory address which is located in a certain bank selected by the program memory bank pointer bits will occur. PBP Register – BS66F360 Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 PBP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1 D7~D1: General data bits and can be read or written. Bit 0 PBP0: Program Memory Bank Point bit 0 0: Bank 0 1: Bank 1 PBP Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Name D6 D5 D4 D3 D2 D1 PBP1 PBP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~2 D6~D1: General data bits and can be read or written. Bit 1~0 PBP1~PBP0: Program Memory Bank Point bit1~bit 0 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Rev. 1.40 63 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. • SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result. • CZ is the operational result of different flags for different instuctions. Refer to register definitions for more details. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.40 64 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x "x": unknown Rev. 1.40 Bit 7 SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the "AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5 TO: Watchdog Time-out flag 0: After power up ow executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up ow executing the "CLR WDT" instruction 1: By executing the "HALT" instructin Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction. 65 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. Device Capacity Address 128 x 8 00H ~ 7FH BS66F340 BS66F350 BS66F360 BS66F370 EEPROM Data Memory Structure The EEPROM Data Memory capacity is 128×8 bits for the series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register, however, being located in sector 1, can be read from or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H in sector 1, the Memory Pointer low byte register, MP1L or MP2L, must first be set to the value 40H and the Memory Pointer high byte register, MP1H or MP2H, set to the value, 01H, before any operations on the EEC register are executed. Bit Register Name 7 6 5 4 3 2 1 0 EEA — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Registers List EEA Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — EEA6 EEA5 EEA4 EEA3 EEA2 EEA1 EEA0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0 EEA6~EEA0: Data EEPROM address bit 6 ~ bit0 66 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: Data EEPROM data bit 7~bit0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3 WREN: Data EEPROM write enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM write control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM read enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0 RD: EEPROM read control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Rev. 1.40 67 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. Then the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register is located in sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However, as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Rev. 1.40 68 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Programming Example • Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM write ; move read data to register • Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.40 ; user defined address ; user defined data ; setup memory pointer low byte MP1L ; MP1L points to EEC register ; setup Memory Pointer high byte MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit ; check for write cycle end ; disable EEPROM write 69 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Oscillators Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of application program and relevant control registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Frequency Pins External High Speed Crystal HXT 400 kHz~20 MHz OSC1/OSC2 Internal High Speed RC HIRC 8/12/16 MHz — External Low Speed Crystal LXT 32.768 kHz XT1/XT2 Internal Low Speed RC LIRC 32 kHz — Oscillator Types System Clock Configurations There are four methods of generating the system clock, two high speed oscillators for all devices and two low speed oscillators. The high speed oscillator is the external crystal/ceramic oscillator, HXT, and the internal 8/12/16 MHz RC oscillator, HIRC. The two low speed oscillators are the internal 32 kHz RC oscillator, LIRC, and the external 32.768 kHz crystal oscillator, LXT. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC register. The frequency of the slow speed or high speed system clock is determined using the CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 1.40 70 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver fH High Speed Os�illato�s FHS fH/� fH/4 HIRC HIRCEN HXTEN fH/8 P�es�ale� fH HXT fSYS fH/1� fH/3� fH/�4 Low Speed Os�illato�s FSS CKS�~CKS0 LXTEN LXT fSUB LIRC fSUB fLIRC fLIRC System Clock Configurations External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is the high frequency oscillator, which is the default oscillator clock source after power on. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Crystal/Resonator Oscillator HXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0 pF 0 pF 8MHz 0 pF 0 pF 4MHz 0 pF 0 pF 1MHz 100 pF 100 pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Rev. 1.40 71 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/ O pins are free for use as normal I/O pins. External 32.768 kHz Crystal Oscillator – LXT The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, Rp, is required. The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functional pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functional pins. • If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. External LXT Oscillator Rev. 1.40 72 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Speed-Up Mode and the Low-Power Mode. The mode selection is executed using the LXTSP bit in the LXTC register. LXTSP LXT Operating Mode 0 Low-Power 1 Speed-Up When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-Up Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up, it can be placed into the Low-Power Mode by clearing the LXTSP bit to zero and the oscillator will continue to run but with reduced current consumption. It is important to note that the LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register, the LXT oscillator operating mode can not be changed. It should be note that no matter what condition the LXTSP is set to the LXT oscillator will always function normally. The only difference is that it will take more time to start up if in the Low Power Mode. Internal 32kHz Oscillator – LIRC The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency of 32 kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%. Rev. 1.40 73 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks Each device has different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced from an HXT or HIRC oscillator, selected via configuring the FHS bit in the SCC register. The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.40 74 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver fH High Speed Os�illato�s HIRCEN HXTEN FHS fH/� fH/4 HIRC fH/8 P�es�ale� fH HXT fSYS fH/1� fH/3� fH/�4 FSS LXTEN CKS�~CKS0 LXT fSUB LIRC fSUB fLIRC fSYS fPSC0 fSYS/4 Low Speed Os�illato�s fSUB P�es�ale� 0 Ti�e Base 0 TB0[�:0] CLKSEL0[1:0] fSYS fPSC1 fSYS/4 fSUB CLKSEL1[1:0] fLIRC fLIRC P�es�ale� 1 Ti�e Base 1 TB1[�:0] WDT LVR Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. Rev. 1.40 75 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL On SLOW On Register Setting FHIDEN FSIDEN x x CKS2~CKS0 x 000~110 x IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 fSYS fH fH~fH/64 On 111 fSUB 000~110 Off 111 On xxx On 000~110 On 111 Off xxx Off fSUB fLIRC On On On On Off On On On On On On Off On Off Off On/Off (1) (2) On Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock will be switched on since the WDT function is always enabled. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register.Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock still continues to operate since the WDT function is always enabled. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. Rev. 1.40 76 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the corresponding oscillator configurations. Bit Register Name 7 6 5 4 3 2 1 0 SCC CKS2 CKS1 CKS0 — FHS FSS FHIDEN FSIDEN HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN HXTC — — — — — HXTM HXTF HXTEN LXTC — — — — — LXTSP LXTF LXTEN System Operating Mode Control Registers List SCC Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — FHS FSS FHIDEN FSIDEN R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7~5 Rev. 1.40 CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. Bit 3 FHS: High Frequency clock selection 0: HIRC 1: HXT Bit 2 FSS: Low Frequency clock selection 0: LIRC 1: LXT 77 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0 FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. HIRCC Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — HIRC1 HIRC0 HIRCF HIRCEN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 1 Bit 7~4 Unimplemented, read as 0. Bit 3~2 HIRC1~HIRC0: HIRC frequency selection 00: 8 MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the HIRCF flag is set to 1. Bit 1 HIRCF: HIRC oscillator stable flag 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection is changed by application program, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0 HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable 78 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver HXTC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — HXTM HXTF HXTEN R/W — — — — — R/W R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2 HXTM: HXT mode selection 0: HXT frequency ≤ 10 MHz 1: HXT frequency >10 MHz This bit is used to select the HXT oscillator operating mode. Note that this bit must be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to change the value of this bit. Bit 1 HXTF: HXT oscillator stable flag 0: HXT unstable 1: HXT stable This bit is used to indicate whether the HXT oscillator is stable or not. When the HXTEN bit is set to 1 to enable the HXT oscillator, the HXTF bit will first be cleared to 0 and then set to 1 after the HXT oscillator is stable. Bit 0 HXTEN: HXT oscillator enable control 0: Disable 1: Enable LXTC Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — — LXTSP LXTF LXTEN R/W — — — — — RW R R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as 0. Bit 2 LXTSP: LXT oscillator speed-up control 0: Disable – Low power 1: Enable – Speed up This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bit can not be changed after the LXT oscillator is selected as the system clock source using the CKS2~CKS0 and FSS bits in the SCC register. Bit 1 LXTF: LXT oscillator stable flag 0: LXT unstable 1: LXT stable This bit is used to indicate whether the LXT oscillator is stable or not. When the LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will first be cleared to 0 and then set to 1 after the LXT oscillator is stable. Bit 0 LXTEN: LXT oscillator enable control 0: Disable 1: Enable 79 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Operating Mode Switching These devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL fSYS=fH~fH/64 fH on CPU run fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU run fSYS on fH on/off SLEEP HALT instruction executed CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT instruction executed CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.40 80 IDLE1 HALT instruction executed CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to "111" in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS2~CKS0 = 111 SLOW Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Rev. 1.40 81 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"110" and then the system clock will respectively be switched to fH~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. SLOW Mode CKS2~CKS0 = 000~110 NORMAL Mode FHIDEN=0, FSIDEN=0 HALT instruction is executed SLEEP Mode FHIDEN=0, FSIDEN=1 HALT instruction is executed IDLE0 Mode FHIDEN=1, FSIDEN=1 HALT instruction is executed IDLE1 Mode FHIDEN=1, FSIDEN=0 HALT instruction is executed IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Rev. 1.40 82 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HALT" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting as the WDT function is always enabled. Rev. 1.40 83 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the "HALT" instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but wukk rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.40 84 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal RC oscillator, fLIRC. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function enable control 10101 or 01010: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the RSTFC register will be set to 1. Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 210/fLIRC 010: 212/fLIRC 011: 214/fLIRC 100: 215/fLIRC 101: 216/fLIRC 110: 217/fLIRC 111: 218/fLIRC These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Rev. 1.40 Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag Described elsewhere. 85 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR control register software reset flag Described elsewhere. Bit 0 WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the WDT control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instruction will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be enabled when the WE4~WE0 bits are set to a value of 01010B or 10101B. If the WE4~WE0 bits are set to any other values other than 01010B and 10101B, it will reset the device after 2~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B or 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT contents. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8s for the 218 division ratio and a minimum timeout of 7.8ms for the 28 division ration. WDTC WE4~WE0 �its Registe� Reset MCU CLR “HALT”Inst�u�tion “CLR WDT”Inst�u�tion LIRC fLIRC 8-stage Divide� fLIRC/�8 WS�~WS0 (fLIRC/�8 ~ fLIRC/�18) WDT P�es�ale� 8-to-1 MUX WDT Ti�e-out (�8/fLIRC ~ �18/fLIRC ) Watchdog timer Rev. 1.40 86 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Powe�-on Reset tRSTD SST Ti�e-out Note: tRSTD is power-on delay with typical time=50 ms Power-On Reset Timing Chart Internal Reset Control There is an internal reset control register, RSTC, which is used to provide a reset when the device operates abnormally due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock cycles. After power on the register will have a value of 01010101B. RSTC7 ~ RSTC0 Bits Reset Function 01010101B No operation 10101010B No operation Any other value Reset MCU Internal Reset Function Control Rev. 1.40 87 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • RSTC Register Bit 7 6 5 4 3 2 1 0 Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 RSTC7~RSTC0: Reset function control 01010101: No operation 10101010: No operation Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the RSTF bit in the RSTFC register will be set to 1. • RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the RSTC control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR control register software reset flag Described elsewhere. Bit 0 WRF: WDT control register software reset flag Described elsewhere. Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the LVR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Rev. 1.40 88 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Note: tRSTD is power-on delay with typical time=50ms Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. • RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Rev. 1.40 Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag Described elsewhere. Bit 2 LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the LVRC control register contains any undefined LVR voltage register values. This in effect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT control register software reset flag Described elsewhere. 89 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as the hardware Low Voltage Reset except that the Watchdog time-out flag TO will be set to "1". Note: tRSTD is power-on delay with typical time=16.7ms WDT Time-out Reset during NORMAL Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Function 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.40 Reset Function Program Counter Reset to zero Interrupts All interrupts will be disabled WDT, Time Base Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack pointer Stack pointer will point to the top of the stack 90 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) IAR0 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR1 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ● ---- xxxx ---- uuuu ---- uuuu ---- uuuu ---x xxxx ---u uuuu ---u uuuu ---u uuuu --xx xxxx --uu uuuu --uu uuuu --uu uuuu ● -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu ● ● xx00 xxxx uuuu uuuu xx1u uuuu u u 11 u u u u ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu Register TBHP ● TBHP ● TBHP STATUS ● ● PBP LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* IAR2 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP2H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu RSTFC ● ● ● ● ---- 0x00 ---- u1uu ---- uuuu ---- uuuu INTC0 ● ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PA ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PAPU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PB ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTEG ● ● ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu SCC ● ● ● ● 000- 0000 000- 0000 000- 0000 uuu- uuuu HIRCC ● ● ● ● ---- 0001 ---- 0001 ---- 0001 ---- uuuu HXTC ● ● ● ● ---- -000 ---- -000 ---- -000 ---- -uuu LXTC ● ● ● ● ---- -000 ---- -000 ---- -000 ---- -uuu LVDC ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu LVRC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu WDTC ● ● ● ● 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu RSTC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu PC ● - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu - - - - 1111 - - - - 1111 - - - - 1111 ---- uuuu PC PCC Rev. 1.40 ● ● ● ● 91 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F370 PCPU BS66F360 PCC BS66F350 BS66F340 Register Reset (Power On) ● ● ● 1111 1111 ● LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* 1111 1111 1111 1111 uuuu uuuu ---- 0000 ---- 0000 ---- 0000 ---- uuuu PCPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PD ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU ● ● ● 0000 0000 0000 0000 0000 0000 0uuuu uuuu MFI0 ● ● ● ● --00 --00 --00 --00 --00 --00 --uu --uu MFI1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI2 ● ● ● ● -000 -000 -000 -000 -000 -000 -uuu -uuu MFI3 ● ● ● ● --00 --00 --00 --00 --00 --00 --uu --uu ADRL (ADRFS=0) ● ● ● ● xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRL (ADRFS=1) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=0) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=1) ● ● ● ● ---- xxxx ---- uuuu ---- uuuu ---- uuuu ADCR0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ADCR1 ● ● ● ● 0-00 -000 0-00 -000 0-00 -000 u-uu -uuu PSCR0 ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TB0C ● ● ● ● 0--- -000 0--- -000 0--- -000 u--- -uuu TB1C ● ● ● ● 0--- -000 0--- -000 0--- -000 u--- -uuu SIMTOC ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 ● ● ● ● 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu- uuuu SIMC1 ● ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/ SIMC2 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu CTM0AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0AH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu EEA ● ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu EED ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PSCR1 ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu SLEDC ● --00 0000 --00 0000 --00 0000 --uu uuuu ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu uuuu u--- SLEDC ● ● SLEDC1 PTMC0 ● ● ● ● 0000 0--- 0000 0--- 0000 0--- PTMC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu PTMAL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMAH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu Rev. 1.40 92 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) PTMRPL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMRPH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu FC0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ● ---- ---0 ---- ---0 ---- ---0 ---- ---u ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---0 0000 ---0 0000 ---0 0000 ---u uuuu --00 0000 --00 0000 --00 0000 --uu uuuu ● -000 0000 -000 0000 -000 0000 -uuu uuuu Register FC2 FARL ● FARH ● FARH ● FARH ● FARH LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* FD0L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD0H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD2H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMC0 ● ● ● ● 0000 0--- 0000 0--- 0000 0--- uuuu u--- STMC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMRP ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1DH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu CTM1AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1AH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TSC0 ● ● ● ● 010- ---- 010- ---- 010- ---- uuu- ---- TSC1 ● ● ● ● 000- ---- 000- ---- 000- ---- uuu- ---- ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● ● --0- ---- --0- ---- --0- ---- --u- ---- - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu --00 0000 --00 0000 --00 0000 --uu uuuu TSC2 TSC3 ● PE ● PE PEC ● ● ● PEC PEPU ● ● ● ● ● PEPU ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PF ● ● - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PFC ● ● - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PFPU ● ● --00 0000 --00 0000 --00 0000 --uu uuuu ● ● 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu USR Rev. 1.40 ● ● ● 93 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) UCR1 ● ● ● ● 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TXR_RXR ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BRG ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PG ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PGC ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PGPU ● 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu Register LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* TKTMR ● ● ● ● 0000 0000 0000 0000 0000 0000 TKC0 ● ● ● ● 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu TK16DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TK16DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC1 ● ● ● ● 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu TKM016DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM016DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM0C0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM0C1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM0C2 ● ● ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM116DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM116DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM1C0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM1C1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM1C2 ● ● ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM216DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM216DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2ROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2ROH ● ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM2C0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM2C1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM2C2 ● ● ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM316DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM316DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM3C0 ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM3C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM3C2 ● ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM416DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM416DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROH ● ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM4C0 ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu Rev. 1.40 94 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F350 BS66F360 BS66F370 BS66F340 Reset (Power On) TKM4C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 TKM4C2 ● ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM516DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM516DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM5ROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM5ROH ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM5C0 ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM5C1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM5C2 ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM616DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM616DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM6ROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM6ROH ● ● ---- --00 ---- --00 ---- --00 ---- --uu TKM6C0 ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM6C1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM6C2 ● ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu TKM716DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM716DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM7ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM7ROH ● ---- --00 ---- --00 ---- --00 ---- --uu TKM7C0 ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM7C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM7C2 ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu Register LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* u-uu uuuu EEC ● ● ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu IFS ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu PAS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PAS1 ● 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu PAS1 ● ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu PBS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PBS1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 ---- 0000 ---- 0000 ---- uuuu ---- ---- 0000 ---- 0000 ---- 0000 ---- uuuu uuuu uuuu PES0 ● PES0 PES1 PES1 ● ● ● ● 0000 0000 0000 0000 0000 0000 ● ● ---- 0000 ---- 0000 ---- 0000 ---- uuuu PGS0 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PGS1 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PH ● - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PHC ● - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PHPU ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM816DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PFS0 Rev. 1.40 ● 95 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F370 BS66F360 BS66F350 BS66F340 Reset (Power On) TKM816DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM8ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM8ROH ● ---- --00 ---- --00 ---- --00 ---- --uu TKM8C0 ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM8C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM8C2 ● 111 0 0 1 0 0 111 0 0 1 0 0 111 0 0 1 0 0 uuuu uuuu Register LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* Note: "u" stands for unchanged "x" stands for "unknown" "-" stands for unimplemented Rev. 1.40 96 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. These devices provide bidirectional input/output lines labeled with port names PA~PH. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC — — — — PC3 PC2 PC1 PC0 PCC — — — — PCC3 PCC2 PCC1 PCC0 PCPU — — — — PCPU3 PCPU2 PCPU1 PCPU0 PE — — PE5 PE4 PE3 PE2 PE1 PE0 PEC — — PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU — — PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 I/O Registers List – BS66F340 Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 I/O Registers List – BS66F350 Rev. 1.40 97 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PF — — PF5 PF4 PF3 PF2 PF1 PF0 PFC — — PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PFPU — — PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0 I/O Registers List – BS66F360 Rev. 1.40 98 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PF — — PF5 PF4 PF3 PF2 PF1 PF0 PFC — — PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PFPU — — PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0 PG PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PGC PGC7 PGC6 PGC5 PGC4 PGC3 PGC2 PGC1 PGC0 PGPU PGPU7 PGPU6 PGPU5 PGPU4 PGPU3 PGPU2 PGPU1 PGPU0 PH — — PH5 PH4 PH3 PH2 PH1 PH0 PHC — — PHC5 PHC4 PHC3 PHC2 PHC1 PHC0 PHPU — — PHPU5 PHPU4 PHPU3 PHPU2 PHPU1 PHPU0 I/O Registers List – BS66F370 Unimplemented, read as "0". PAWUn: Port A Pin wake-up function control 0: Disable 1: Enable PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn: I/O Pin pull-high function control 0: Disable 1: Enable PAn/PBn/PCn/PDn/PEn/PFn/PGn/PHn: I/O Port Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn: I/O Pin type selection 0: Output 1: Input Rev. 1.40 99 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or NMOS output. Otherwise, the pull-high resistors can not be enabled. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. I/O Port Control Registers Each Port has its own control register, known as PAC~PHC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Port Source Current Control These devices support different source current driving capability for each I/O port. With the selection register, SLEDC or SLEDC1, specific I/O port can support four levels of the source current driving capability. Users should refer to the D.C. characteristics section to select the desired source current for different applications. Register Name SLEDC (BS66F340) SLEDC (BS66F350/BS66F360/ BS66F370) SLEDC1 (BS66F370) Bit 7 6 — — 5 4 3 2 1 0 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 PCPS3 PCPS2 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 — — — — PHPS1 PHPS0 PGPS1 PGPS0 I/O Port Source Current Control Registers List Rev. 1.40 100 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLEDC Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Name — — PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0 Bit 5~4 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PBPS1~PBPS0: PB7~PB4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PAPS1~PAPS0: PA7~PA5 and PA1 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) SLEDC Register – BS66F350/BS66F360/BS66F370 Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PCPS3 PCPS2 PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCPS3~PCPS2: PC7~PC4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 5~4 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PBPS1~PBPS0: PB7~PB4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PAPS1~PAPS0: PA7~PA5 and PA1 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) 101 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLEDC1 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Name — — — — PHPS1 PHPS0 PGPS1 PGPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~2 PHPS1~PHPS0: PH3~PH0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0 PGPS1~PGPS0: PG3~PG0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. Each device includes Port "x" output function Selection register "n", labeled as PxSn, and Input Function Selection register, labeled as IFS, which can select the desired functions of the multi-function pin-shared pins. When the pin-shared input function is selected to be used, the corresponding input and output functions selection should be properly managed. For example, if the I2C SDA line is used, the corresponding output pin-shared function should be configured as the SDI/SDA function by configuring the PxSn register and the SDA signal intput should be properly selected using the IFS register. However, if the external interrupt function is selected to be used, the relevant output pin-shared function should be selected as an I/O function and the interrupt input signal should be selected. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Rev. 1.40 102 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 — — PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 PES1 — — — — PES13 PES12 PES11 PES10 IFS — — IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 0 Pin-shared Function Selection Registers List – BS66F340 Bit Register Name 7 6 5 4 3 2 1 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 — — — — PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 — — — — PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 IFS — — IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F350 Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 — — — — PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS10 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 PFS0 — — — — PFS03 PFS02 PFS01 PFS00 IFS — — IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F360 Rev. 1.40 103 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 — — — — PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 PCS10 PCS1 PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 PFS0 — — — — PFS03 PFS02 PFS01 PFS00 PGS0 PGS07 PGS06 PGS05 PGS04 PGS03 PGS02 PGS01 PGS00 PGS1 PGS17 PGS16 PGS15 PGS14 PGS13 PGS12 PGS11 PGS10 IFS — — IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F370 • PAS0 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS07~PAS06: PA3 pin function selection 00/11: PA3 01: SCS 10: XT1 Bit 5~4 PAS05~PAS04: PA2 pin function selection PAS0[5:4] BS66F340 BS66F350 BS66F360 00 PA2/CTCK1 PA2 PA2 PA2 01 SCS SCS SCS SCS 10 PA2/CTCK1 PA2 PA2 PA2 11 PA2/CTCK1 PA2 PA2 PA2 Bit 3~2 PAS03~PAS02: PA1 pin function selection 00/10/11: PA1 01: CTP0 Bit 1~0 PAS01~PAS00: PA0 pin function selection 00/10/11: PA0 01: SDO 104 BS66F370 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • PAS1 Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 — — PAS13 PAS12 PAS11 PAS10 R/W R/W R/W — — R/W R/W R/W R/W POR 0 0 — — 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 PAS17~PAS16: PA7 pin function selection 00/10/11: PA7 01: CTP1 Unimplemented, read as 0 PAS13~PAS12: PA5 pin function selection 00/10/11: PA5 01: CTP0B PAS11~PAS10: PA4 pin function selection 00/11: PA4 01: SDO 10: XT2 • PAS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Name — — — — PAS13 PAS12 PAS11 PAS10 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Bit 3~2 Bit 1~0 Unimplemented, read as 0 PAS13~PAS12: PA5 pin function selection 00/10/11: PA5 01: CTP0B PAS11~PAS10: PA4 pin function selection 00/11: PA4 01: SDO 10: XT2 • PBS0 Register Bit 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 Rev. 1.40 PBS07~PBS06: PB3 pin function selection 00/10: PB3 01: RX 11: AN3 PBS05~PBS04: PB2 pin function selection 00: PB2/PTPI 01: TX 10: PTP 11: AN2 PBS03~PBS02: PB1 pin function selection 00/10: PB1 01: SCK/SCL 11: AN1 PBS01~PBS00: PB0 pin function selection 00: PB0 01: SDI/SDA 10: VREF 11: AN0 105 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PBS17~PBS16: PB7 pin function selection 00/01: PB7/INT1 10: KEY4 11: AN7 Bit 5~4 PBS15~PBS14: PB6 pin function selection 00/01: PB6/PTCK 10: KEY3 11: AN6 Bit 3~2 PBS13~PBS12: PB5 pin function selection 00/01: PB5/STCK 10: KEY2 11: AN5 Bit 1~0 PBS11~PBS10: PB4 pin function selection 00: PB4/PTPI 01: PTPB 10: KEY1 11: AN4 • PCS0 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS07~PCS06: PC3 pin function selection 00: PC3 01: PC3 10: KEY8 11: PC3 Bit 5~4 PCS05~PCS04: PC2 pin function selection 00: PC2 01: PC2 10: KEY7 11: PC2 Bit 3~2 PCS03~PCS02: PC1 pin function selection 00: PC1 01: PC1 10: KEY6 11: PC1 Bit 1~0 PCS01~PCS00: PC0 pin function selection 00: PC0 01: PC0 10: KEY5 11: PC0 106 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • PCS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Name PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS17~PCS16: PC7 pin function selection 00: PC7 01: PC7 10: KEY12 11: PC7 Bit 5~4 PCS15~PCS14: PC6 pin function selection 00: PC6 01: PC6 10: KEY11 11: PC6 Bit 3~2 PCS13~PCS12: PC5 pin function selection 00: PC5 01: PC5 10: KEY10 11: PC5 Bit 1~0 PCS11~PCS10: PC4 pin function selection 00: PC4 01: PC4 10: KEY9 11: PC4 • PDS0 Register – BS66F350/BS66F360/BS66F370 Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PDS07~PDS06: PD3 pin function selection 00: PD3 01: PD3 10: KEY16 11: PD3 Bit 5~4 PDS05~PDS04: PD2 pin function selection 00: PD2 01: PD2 10: KEY15 11: PD2 Bit 3~2 PDS03~PDS02: PD1 pin function selection 00: PD1 01: PD1 10: KEY14 11: PD1 Bit 1~0 PDS01~PDS00: PD0 pin function selection 00: PD0 01: PD0 10: KEY13 11: PD0 107 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • PDS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Name PDS17 PDS16 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 PDS17~PDS16: PD7 pin function selection 00: PD7 01: PD7 10: KEY20 11: PD7 PDS15~PDS14: PD6 pin function selection 00: PD6 01: PD6 10: KEY19 11: PD6 Bit 3~2 PDS13~PDS12: PD5 pin function selection 00: PD5 01: PD5 10: KEY18 11: PD5 Bit 1~0 PDS11~PDS10: PD4 pin function selection 00: PD4 01: PD4 10: KEY17 11: PD4 • PES0 Register Bit 7 6 5 4 3 2 1 0 Name PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 PES07~PES06: PE3 pin function selection PES0[7:6] BS66F340 BS66F350 BS66F360 BS66F370 00 PE3/STPI PE3/STPI PE3/STPI PE3/STPI 01 STPB STPB STPB STPB 10 KEY12 PE3/STPI KEY24 KEY24 11 PE3/STPI PE3/STPI PE3/STPI PE3/STPI PES05~PES04: PE2 pin function selection PES0[5:4] BS66F340 BS66F350 BS66F360 BS66F370 00 PE2/STPI PE2/STPI PE2/STPI PE2/STPI 01 STP STP STP STP 10 KEY11 PE2/STPI KEY23 KEY23 11 PE2/STPI PE2/STPI PE2/STPI PE2/STPI BS66F370 PES03~PES02: PE1 pin function selection PES0[3:2] BS66F340 BS66F350 BS66F360 00 PE1 — PE1 PE1 01 PE1 — PE1 PE1 10 KEY10 — KEY22 KEY22 11 PE1 — PE1 PE1 "—": Unimplemented, read as 0 – BS66F350 Rev. 1.40 108 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1~0 PES01~PES00: PE0 pin function selection PES0[1:0] BS66F340 BS66F350 BS66F360 00 PE0 — PE0 BS66F370 PE0 01 PE0 — PE0 PE0 10 KEY9 — KEY21 KEY21 11 PE0 — PE0 PE0 Unimplemented, read as 0 – BS66F350 • PES1 Register Bit 7 6 5 4 3 2 1 0 Name PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PES17~PES16: PE7 pin function selection PES1[7:6] BS66F340 BS66F350 BS66F360 BS66F370 00 — PE7 PE7 PE7 01 — CTP1B CTP1B CTP1B 10 — PE7 KEY26 KEY26 11 — PE7 PE7 PE7 Unimplemented, read as 0 – BS66F340 Bit 5~4 PES15~PES14: PE6 pin function selection PES1[5:4] BS66F340 BS66F350 BS66F360 BS66F370 00 — PE6 PE6 PE6 01 — CTP1 CTP1 CTP1 10 — PE6 KEY25 KEY25 11 — PE6 PE6 PE6 Unimplemented, read as 0 – BS66F340 Bit 3~2 Bit 1~0 PES13~PES12: PE5 pin function selection PES1[3:2] BS66F340 BS66F350 BS66F360 BS66F370 00 PE5 PE5/CTCK1 PE5/CTCK1 PE5/CTCK1 01 CTP1B PE5/CTCK1 PE5/CTCK1 PE5/CTCK1 10 OSC2 OSC2 OSC2 OSC2 11 PE5 PE5/CTCK1 PE5/CTCK1 PE5/CTCK1 PES11~PES10: PE4 pin function selection 00: PE4 01: PE4 10: OSC1 11: PE4 • PFS0 Register – BS66F360/BS66F370 Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — — — PFS03 PFS02 PFS01 PFS00 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0 Bit 3~2 PFS03~PFS02: PF1 pin function selection 00/01/11: PF1 10: KEY28 109 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1~0 PFS01~PFS00: PF0 pin function selection 00/01/11: PF1 10: KEY27 • PGS0 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Name PGS07 PGS06 PGS05 PGS04 PGS03 PGS02 PGS01 PGS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 PGS07~PGS06: PG3 pin function selection 00: PG3 01: PG3 10: KEY32 11: PG3 PGS05~PGS04: PG2 pin function selection 00: PG2 01: PG2 10: KEY31 11: PG2 PGS03~PGS02: PG1 pin function selection 00: PG1 01: PG1 10: KEY30 11: PG1 PGS01~PGS00: PG0 pin function selection 00: PG0 01: PG0 10: KEY29 11: PG0 • PGS1 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Name PGS17 PGS16 PGS15 PGS14 PGS13 PGS12 PGS11 PGS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Bit 5~4 Bit 3~2 Bit 1~0 Rev. 1.40 PGS17~PGS16: PG7 pin function selection 00: PG7 01: PG7 10: KEY36 11: PG7 PGS15~PGS14: PG6 pin function selection 00: PG6 01: PG6 10: KEY35 11: PG6 PGS13~PGS12: PG5 pin function selection 00: PG5 01: PG5 10: KEY34 11: PG5 PGS11~PGS10: PG4 pin function selection 00: PG4 01: PG4 10: KEY33 11: PG4 110 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • IFS Register Bit 7 6 5 4 3 2 1 0 Name — — IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0 Bit 5~4 IFS5~IFS4: SCS input source pin selection 00/10: PA2 01/11: PA3 Bit 3~2 IFS3~IFS2: PTPI input source pin selection 00/10: PB2 01/11: PB4 Bit 1~0 IFS1~IFS0: STPI input source pin selection 00/01: PE2 01/11: PE3 I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure Rev. 1.40 111 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Input/Output Structure Programming Considerations Within the user program, one of the things first to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.40 112 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction These devices contain four TMs and each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Periodic Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Periodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM PTM Timer/Counter TM Function √ √ √ Input Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 1 Single Pulse Output — 1 1 Edge Edge Edge Duty or Period Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary TM Operation The different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. When the free running count-up counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" stands for C, S or P type TM and "n" stands for the specific TM serial number. For STM and PTM there is no serial number "n" in the relevant pin or control bits since there is only one STM and PTM respectively in the series of devices, The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. Rev. 1.40 113 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and xTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling active edge. The STCK and PTCK pins are also used as the external trigger input pin in single pulse output mode for the STM and PTM respectively. The other xTM input pin, STPI or PTPI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the STIO1~STIO0 or PTIO1~PTIO0 bits in the STMC1 or PTMC1 register respectively. There is another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger input source except the PTPI pin. The TMs each have two output pins, xTPn and xTPnB. The xTPnB is the inverted signal of the xTPn output. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn or xTPnB output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. Device BS66F340 BS66F350 BS66F360 BS66F370 CTM Input CTCK0 CTCK1 STM Output Input CTP0, CTP0B STCK, STPI CTP1, CTP1B PTM Output STP, STPB Input Output PTCK, PTPI PTP, PTPB TM External Pins Rev. 1.40 114 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TM Input/Output Pin Selection Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. CTCKn CTMn CCR output CTPn CTPnB CTM Function Pin Control Block Diagram – n = 0 or 1 STCK CCR �aptu�e input STPI STM CCR output STP STPB STM Function Pin Control Block Diagram PTCK CCR �aptu�e input PTPI PTM CCR output PTP PTPB PTM Function Pin Control Block Diagram Rev. 1.40 115 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMRPL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. xTMn Counte� Registe� (Read only) xTMnDL xTMnDH 8-�it Buffe� xTMnAL xTMnAH xTMn CCRA Registe� (Read/W�ite) PTMRPL PTMRPH PTM CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.40 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMRPL ––this step reads data from the 8-bit buffer. 116 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pin. Device CTM Core CTM Input Pin CTM Output Pin Note BS66F340 BS66F350 BS66F360 BS66F370 10-bit CTM (CTM0, CTM1) CTCK0, CTCK1 CTP0, CTP0B CTP1, CTP1B n=0~1 CCRP fSYS/4 fSYS fH/1� fH/�4 fSUB fSUB 3-�it Co�pa�ato� P 000 001 011 10-�it Count-up Counte� 100 101 111 CTnON CTnPAU �0~�9 10-�it Co�pa�ato� A CTMnPF Inte��upt CTnOC �7~�9 010 110 CTCKn Co�pa�ato� P Mat�h Counte� Clea� 0 1 CTnCCLR Co�pa�ato� A Mat�h Output Cont�ol Pola�ity Cont�ol Pin Cont�ol CTnM1� CTnM0 CTnIO1� CTnIO0 CTnPOL PxSn CTPn CTPnB CTMnAF Inte��upt CTnCK�~CTnCK0 CCRA Compact Type TM Block Diagram – n = 0 or 1 Compact TM Operation The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three-bit wide whose value is compared with the highest three bits in the counter while the CCRA is ten-bit wide and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.40 117 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes and as well as the three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 CTMnC0 CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D7 D6 D5 D4 D3 D2 D1 D0 CTMnDH — — — — — — D9 D8 CTMnAL D7 D6 D5 D4 D3 D2 D1 D0 CTMnAH — — — — — — D9 D8 10-bit Compact TM Registers List – n = 0 or 1 CTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn Counter Low Byte Register bit 7 ~ bit 0 CTMn 10-bit Counter bit 7 ~ bit 0 CTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn Counter High Byte Register bit 1 ~ bit 0 CTMn 10-bit Counter bit 9 ~ bit 8 CTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 1 0 Bit 7~0 CTMn CCRA Low Byte Register bit 7 ~ bit 0 CTMn 10-bit CCRA bit 7 ~ bit 0 CTMnAH Register Rev. 1.40 Bit 7 6 5 4 3 2 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn CCRA High Byte Register bit 1 ~ bit 0 CTMn 10-bit CCRA bit 9 ~ bit 8 118 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver CTMnC0 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CTnPAU: CTMn Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 CTnCK2~CTnCK0: Select CTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCKn rising edge clock 111: CTCKn falling edge clock These three bits are used to select the clock source for the CTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 CTnON: CTMn Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the CTMn. Setting the bit high enables the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero will stop the counter from counting and turn off the CTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the CTMn is in the Compare Match Output Mode then the CTMn output pin will be reset to its initial condition, as specified by the CTnOC bit, when the CTnON bit changes from low to high. Bit 2~0 CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter bit 9 ~ bit 7 000: 1024 CTMn clocks 001: 128 CTMn clocks 010: 256 CTMn clocks 011: 384 CTMn clocks 100: 512 CTMn clocks 101: 640 CTMn clocks 110: 768 CTMn clocks 111: 896 CTMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 119 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver CTMnC1 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CTnM1~CTnM0: Select CTMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTMn. To ensure reliable operation the CTMn should be switched off before any changes are made to the CTnM1 and CTnM0 bits. In the Timer/Counter Mode, the CTMn output pin control will be disabled. Bit 5~4 CTnIO1~CTnIO0: Select CTMn external pin (CTPn) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the CTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTMn is running. In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a compare match occurs from the Comparator A. The CTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pin should be setup using the CTnOC bit in the CTMnC1 register. Note that the output level requested by the CTnIO1 and CTnIO0 bits must be different from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pin when a compare match occurs. After the CTMn output pin changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high. In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running. 120 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Rev. 1.40 Bit 3 CTnOC: CTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTMn output pin. Its operation depends upon whether CTMn is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 CTnPOL: CTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the CTPn output pin. When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 CTnDPX: CTMn PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0 CTnCCLR: CTMn Counter Clear condition selection 0: CTMn Comparator P match 1: CTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not used in the PWM Mode. 121 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM Operation Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0 bits in the CTMnC1 register. Compare Match Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMnAF and CTMnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTnCCLR is high no CTMnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTMn output pin will change state. The CTMn output pin condition however only changes state when a CTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the CTMn output pin. The way in which the CTMn output pin changes state are determined by the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTMn output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place. Rev. 1.40 122 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value Counte� ove�flow CCRP=0 0x3FF CTnCCLR = 0; CTnM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin Output pin set to initial Level Low if CTnOC=0 Output not affe�ted �y CTMnAF flag. Re�ains High until �eset �y CTnON �it Output Toggle with CTMnAF flag He�e CTnIO [1:0] = 11 Toggle Output sele�t Note CTnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when CTnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – CTnCCLR = 0 Note: 1. With CTnCCLR=0, a Comparator P match will clear the counter 2. The CTMn output pin controlled only by CTMnAF flag 3. The output pin is reset to its initial state by CTnON bit rising edge 4. n = 0 or 1 Rev. 1.40 123 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value CTnCCLR = 1; CTnM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF Resu�e CCRA Pause CCRA=0 Stop Counte� Resta�t CCRP Ti�e CTnON CTnPAU CTnPOL No CTMnAF flag gene�ated on CCRA ove�flow CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF CTMn O/P Pin CTMnPF not gene�ated Output pin set to initial Level Low if CTnOC=0 Output does not �hange Output not affe�ted �y CTMnAF flag. Re�ains High until �eset �y CTnON �it Output Toggle with CTMnAF flag He�e CTnIO [1:0] = 11 Toggle Output sele�t Note CTnIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when CTnPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – CTnCCLR = 1 Note: 1. With CTnCCLR=1, a Comparator A match will clear the counter 2. The CTMn output pin is controlled only by CTMnAF flag 3. The CTMn output pin is reset to initial state by CTnON rising edge 4. The CTMnPF flags is not generated when CTnCCLR=1 5. n = 0 or 1 Rev. 1.40 124 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTMn output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10 respectively. The PWM function within the CTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTnOC bit in the CTMnC1 register is used to select the required polarity of the PWM waveform while the two CTnIO1 and CTnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The CTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=16MHz, CTMn clock source is fSYS/4, CCRP=2 and CCRA=128, The CTMn PWM output frequency=(fSYS/4)/256=fSYS/1024=15.625kHz, duty=128/256=50%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the CTMn clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.40 125 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value CTnDPX = 0; CTnM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when CTnON �etu�ns high CCRP Pause Resu�e CCRA Counte� Stop if CTnON �it low Ti�e CTnON CTnPAU CTnPOL CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF CTMn O/P Pin (CTnOC=1) CTMn O/P Pin (CTnOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when CTnPOL = 1 PWM Output Mode – CTnDPX = 0 Note: 1. Here CTnDPX=0 – Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO [1:0]=00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1 Rev. 1.40 126 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value CTnDPX = 1; CTnM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when CTnON �etu�ns high CCRA Pause Resu�e CCRP Counte� Stop if CTnON �it low Ti�e CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin (CTnOC=1) CTMn O/P Pin (CTnOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when CTnPOL = 1 PWM Output Mode – CTnDPX = 1 Note: 1. Here CTnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO [1:0] = 00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1 Rev. 1.40 127 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive two external output pin. Device STM Core STM Input Pin STM Output Pin BS66F340 BS66F350 BS66F360 BS66F370 16-bit STM STCK, STPI STP, STPB CCRP fSYS/4 fSYS fH/1� fH/�4 fSUB fSUB 8-�it Co�pa�ato� P 001 STMPF Inte��upt STOC �8~�1� 010 011 1�-�it Count-up Counte� 100 101 110 STCK Co�pa�ato� P Mat�h 000 STON STPAU 1�-�it Co�pa�ato� A 0 1 STCCLR �0~�1� 111 STCK�~STCK0 Counte� Clea� Output Cont�ol Pola�ity Cont�ol Pin Cont�ol STM1� STM0 STIO1� STIO0 STPOL PxSn Co�pa�ato� A Mat�h STP STPB STMAF Inte��upt STIO1� STIO0 Edge Dete�to� CCRA STPI Standard Type TM Block Diagram Standard TM Operation The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.40 128 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH D15 D14 D13 D12 D11 D10 D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH D15 D14 D13 D12 D11 D10 D9 D8 STMRP STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 16-bit Standard TM Registers List STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter Low Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter High Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8 129 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver STMC0 Register Bit 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 STPAU: STM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 STON: STM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run while clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" STMC1 Register Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Rev. 1.40 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin control will be disabled. 130 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Rev. 1.40 Bit 5~4 STIO1~STIO0: Select STM external pin (STP or STPI) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPI 01: Input capture at falling edge of STPI 10: Input capture at rising/falling edge of STPI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. In the Compare Match Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STM output pin should be setup using the STOC bit in the STMC1 register. Note that the output level requested by the STIO1 and STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the STIO1 and STIO0 bits only after the STM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the STM is running. Bit 3 STOC: STM STP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the STM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. 131 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 STPOL: STM STP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the STP output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. Bit 1 STDPX: STM PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STCCLR: STM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. STMRP Register Bit 7 6 5 4 3 2 1 0 Name STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8 Comparator P match period = 0: 65536 STM clocks 1~255: (1~255) × 256 STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter’s highest eight bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. 132 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM Operation Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.40 133 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value Counte� ove�flow CCRP=0 0xFFFF STCCLR = 0; STM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Output pin set to initial Level Low if STOC=0 Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR = 0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to itsinitial state by a STON bit rising edge Rev. 1.40 134 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0xFFFF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e STON STPAU STPOL No STMAF flag gene�ated on CCRA ove�flow CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin STMPF not gene�ated Output pin set to initial Level Low if STOC=0 Output does not �hange Output not affe�ted �y STMAF flag. Re�ains High until �eset �y STON �it Output Toggle with STMAF flag He�e STIO [1:0] = 11 Toggle Output sele�t Note STIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when STPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – STCCLR = 1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4. A STMPF flag is not generated when STCCLR=1 Rev. 1.40 135 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~255 Period CCRPx256 Duty 0 65536 CCRA If fSYS=16MHz, STM clock source is fSYS/4, CCRP=2 and CCRA=128, The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~255 Period 0 CCRA CCRPx256 Duty 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value except when the CCRP value is equal to 0. Rev. 1.40 136 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value STDPX = 0; STM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when STON �etu�ns high CCRP Pause Resu�e CCRA Counte� Stop if STON �it low Ti�e STON STPAU STPOL CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when STPOL = 1 PWM Output Mode – STDPX = 0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.40 137 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value STDPX = 1; STM [1:0] = 10 Counte� �lea�ed �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Resu�e CCRP Counte� Stop if STON �it low Ti�e STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cy�le set �y CCRP PWM Pe�iod set �y CCRA PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion when STPOL = 1 PWM Output Mode – STDPX = 1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.40 138 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. S/W Co��and SET“STON” o� STCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge STON �it 0à1 STON �it 1à0 S/W Co��and CLR“STON” o� CCRA Co�pa�e Mat�h STP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.40 139 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value STM [1:0] = 10 ; STIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when STON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Ti�e STON Softwa�e T�igge� Auto. set �y STCK pin Clea�ed �y CCRA �at�h STCK pin Softwa�e T�igge� Softwa�e T�igge� Softwa�e Softwa�e T�igge� Clea� STCK pin T�igge� STPAU STPOL CCRP Int. Flag STMPF No CCRP Inte��upts gene�ated CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inve�ts when STPOL = 1 Pulse Width set �y CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCK pin or by setting the STON bit high 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Mode, STIO [1:0] must be set to "11" and can not be changed. Rev. 1.40 140 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STPI pin, whose active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.40 141 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value STM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP YY Pause Resu�e XX Ti�e STON STPAU A�tive edge A�tive edge STM �aptu�e pin STPI A�tive edge CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disa�le Captu�e Capture Input Mode Note: 1. STM [1:0] = 01 and active edge set by the STIO [1:0] bits 2. A STM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function -- STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.40 142 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pin. Device PTM Core PTM Input Pin PTM Output Pin BS66F340 BS66F350 BS66F360 BS66F370 10-bit PTM PTCK, PTPI PTP, PTPB CCRP fSYS/4 fSYS fH/1� fH/�4 fSUB fSUB 10-�it Co�pa�ato� P 001 PTMPF Inte��upt PTOC �0~�9 010 011 10-�it Count-up Counte� 100 101 110 PTCK Co�pa�ato� P Mat�h 000 PTON PTPAU 10-�it Co�pa�ato� A CCRA Output Cont�ol Pola�ity Cont�ol Pin Cont�ol PTM1� PTM0 PTIO1� PTIO0 PTPOL PxSn 0 1 PTCCLR �0~�9 111 PTCK�~PTCK0 Counte� Clea� Co�pa�ato� A Mat�h PTIO1� PTIO0 PTCAPTS Edge Dete�to� 0 1 PTP PTPB PTMAF Inte��upt IFS Pin Cont�ol PTPI Periodic Type TM Block Diagram Periodic TM Operation The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is respectively compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program is to clear the counter by changing the PTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers. Rev. 1.40 143 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D7 D6 D5 D4 D3 D2 D1 D0 PTMDH — — — — — — D9 D8 PTMAL D7 D6 D5 D4 D3 D2 D1 D0 PTMAH — — — — — — D9 D8 PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 PTMRPH — — — — — — PTRP9 PTRP8 Periodic TM Registers List PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 10-bit Counter bit 7 ~ bit 0 PTMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 PTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Rev. 1.40 PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0 144 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTMRPL Register Bit 7 6 5 4 3 2 1 0 Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 PTMRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PTRP9 PTRP8 R/W — — — — — — R/W R/W — — — — — — 0 0 POR Bit 7~2 Bit 1~0 Unimplemented, read as "0" PTRP9~PTRP8: PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 PTMC0 Register Bit 7 6 5 4 3 2 1 0 Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — — R/W R/W R/W R/W R/W R/W — — — 0 0 0 0 0 — — — POR Bit 7 Bit 6~4 Rev. 1.40 PTPAU: PTM Counter Pause control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. 145 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 3 PTON: PTM Counter On/Off control 0: Off 1: On This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run while clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMC1 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0 bits. In the Timer/Counter Mode, the PTM output pin control will be disabled. Bit 5~4 PTIO1~PTIO0: Select PTM external pin PTP or PTPI function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at rising/falling edge of PTPI or PTCK 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running. 146 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be setup using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running. Rev. 1.40 Bit 3 PTOC: PTM PTP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 PTPOL: PTM PTP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM is in the Timer/Counter Mode. Bit 1 PTCAPTS: PTM Capture Triiger Source selection 0: From PTPI pin 1: From PTCK pin Bit 0 PTCCLR: PTM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. 147 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM Operation Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the PTM output pin will change state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PTON bit changes from low to high, is setup using the PTOC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place. Rev. 1.40 148 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value Counte� ove�flow CCRP=0 0x3FF PTCCLR = 0; PTM [1:0] = 00 CCRP > 0 Counte� �lea�ed �y CCRP value CCRP > 0 Counte� Resta�t Resu�e CCRP Pause CCRA Stop Ti�e PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output not affe�ted �y PTMAF flag. Re�ains High until �eset �y PTON �it Output Toggle with PTMAF flag He�e PTIO [1:0] = 11 Toggle Output sele�t Note PTIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 0 Note: 1. With PTCCLR=0, a Comparator P match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge Rev. 1.40 149 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value PTCCLR = 1; PTM [1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed �y CCRA value 0x3FF CCRA=0 Resu�e CCRA Pause Stop Counte� Resta�t CCRP Ti�e PTON PTPAU PTPOL No PTMAF flag gene�ated on CCRA ove�flow CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTMPF not gene�ated Output does not �hange PTM O/P Pin Output pin set to initial Level Low if PTOC=0 Output Toggle with PTMAF flag He�e PTIO [1:0] = 11 Toggle Output sele�t Output not affe�ted �y PTMAF flag. Re�ains High until �eset �y PTON �it Note PTIO [1:0] = 10 A�tive High Output sele�t Output Inve�ts when PTPOL is high Output Pin Reset to Initial value Output �ont�olled �y othe� pin-sha�ed fun�tion Compare Match Output Mode – PTCCLR = 1 Note: 1. With PTCCLR=1, a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge 4. A PTMPF flag is not generated when PTCCLR =1 Rev. 1.40 150 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 10 respectively. The PWM function within the PTM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTCCLR bit has no effect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTM, PWM Mode, CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.40 151 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value PTM [1:0] = 10 Counte� �lea�ed �y CCRP Counte� Reset when PTON �etu�ns high CCRP Pause Resu�e CCRA Counte� Stop if PTON �it low Ti�e PTON PTPAU PTPOL CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) PWM Duty Cy�le set �y CCRA PWM Pe�iod set �y CCRP PWM �esu�es ope�ation Output �ont�olled �y Output Inve�ts othe� pin-sha�ed fun�tion When PTPOL = 1 PWM Mode Note: 1. The counter is cleared by CCRP. 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO [1:0] = 00 or 01 4. The PTCCLR bit has no influence on PWM operation Rev. 1.40 152 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTON bit can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PTON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode. S/W Co��and SET“PTON” o� PTCK Pin T�ansition CCRA Leading Edge CCRA T�ailing Edge PTON �it 0à1 PTON �it 1à0 S/W Co��and CLR“PTON” o� CCRA Co�pa�e Mat�h PTP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.40 153 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value PTM [1:0] = 10 ; PTIO [1:0] = 11 Counte� stopped �y CCRA Counte� Reset when PTON �etu�ns high CCRA Pause Counte� Stops �y softwa�e Resu�e CCRP Ti�e PTON Softwa�e T�igge� Auto. set �y PTCK pin Clea�ed �y CCRA �at�h PTCK pin Softwa�e T�igge� Softwa�e T�igge� Softwa�e Softwa�e T�igge� Clea� PTCK pin T�igge� PTPAU PTPOL CCRP Int. Flag PTMPF No CCRP Inte��upts gene�ated CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) PTM O/P Pin (PTOC=0) Pulse Width set �y CCRA Output Inve�ts when PTPOL = 1 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high. 5. In the Single Pulse Mode, PTIO [1:0] must be set to "11" and can not be changed. Rev. 1.40 154 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register. The counter is started when the PTON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, falling edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PTOC and PTPOL bits are not used in this Mode. Rev. 1.40 155 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte� Value PTM [1:0] = 01 Counte� �lea�ed �y CCRP Counte� Counte� Stop Reset CCRP YY Pause Resu�e XX Ti�e PTON PTPAU A�tive edge A�tive edge PTM �aptu�e pin PTPI o� PTCK A�tive edge CCRA Int. Flag PTMAF CCRP Int. Flag PTMPF CCRA Value PTIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disa�le Captu�e Capture Input Mode Note: 1. PTM [1:0] = 01 and active edge set by the PTIO [1:0] bits 2. A PTM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.40 156 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the Temperature semsor output or Temperature sensor reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the ACS3~ACS0 bits together with the TSE and BGMEN bits. When the external analog signal is to be converted, the corresponding pin-shared control bits should first be properly configured and then desired external channel input should be selected using the ACS3~ACS0 bits. This A/D converter also includes a temperature sensor circuitry which contains a temperature sensor, operational amplifiers and an internal reference voltage. The temperature sensor will detect the temperature and output a voltage proportional to the temperature. The output voltage can be amplified by the OPA and then converted to an 12-bit digital data using the A/D converter. The accompanying block diagram shows the internal structure of the A/D converter with temperature sensor together with its associated registers and control bits. Device External Input Channels Internal Signal A/D Channel Select Bits BS66F340 BS66F350 BS66F360 BS66F370 8: AN0~AN7 2: VTSO, VTSVREF ACS3~ACS0 TSE, BGMEN VDD fSYS Pin-sha�ed Sele�tion ÷� ADCK�~ADCK0 N (N=0~7) ACS3~ACS0 ADCEN TSCLK_S1~TSCLK_S0 A/D Clo�k AN0 AN1 AN7 VTSVREF 1xxxB ATM START IDLE_CONV ADBZ BGMEN VPTAT BGMEN Te�p. Senso� A/D Conve�te� Refe�en�e Voltage VTSO OPA� Gain=4 o� � Pin-sha�ed Sele�tion VREFP_EXT G�XEN BIAS VBGTS ADRFS OP�EN VTSVREF VDD VPTAT A/D Data Registe�s ADRH VSS TSE VTSO TSE ADRL A/D Conve�te� VREF OP1EN VTSVRI VTSVREF OPA1 Gain=1.�7� o� 1 VDD VREFS K_REFO K_VPTAT A/D Converter with Temperature Sensor Diagram Rev. 1.40 157 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Registers Descriptions Overall operation of the A/D converter with Temperature sensor is controlled using eight registers. A read only register pair exists to store the A/D Converter data 12-bit value. Two registers, ADCR0 and ADCR1, are the control registers which setup the operating and control function of the A/D converter. The remaining four registers are the temperature sensor control registers which select the temperature sensor signal to be converted and the reference voltage source together with the temperature sensor conversion clock cycles. Bit Register Name 7 6 5 4 3 2 1 0 ADRL (ADRFS=0) D3 D2 D1 D0 — — — — ADRL (ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH (ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRH (ADRFS=1) — — — — D11 D10 D9 D8 START ADBZ ADCEN ADRFS ACS3 ACS2 ACS1 ACS0 ATM — IDLE_ CONV VREFS — ADCK2 ADCK1 ADCK0 TSC0 BGMEN G5XEN K_REFO — — — — — TSC1 TSE OP2EN OP1EN — — — — — TSC2 VREFP_EXT BIAS D5 D4 D3 D2 TSC3 — — K_VPTAT — — — ADCR0 ADCR1 TSCLK_S1 TSCLK_S0 — — A/D Converter with Temperature Sensor Registers List A/D Converter Data Registers – ADRL, ADRH As these devices contain an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that the A/D data register contents can only be read in the A/ D conversion completion interrupt service subroutine when the Auto-conversion mode is enabled by setting the ATM bit in the ADCR1 register to 1. The A/D data registers contents will be cleared to zero if the A/D converter is disabled. ADRFS 0 1 ADRH 7 6 D11 D10 0 0 ADRL 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Converter Data Registers Rev. 1.40 158 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Control Registers – ADCR0, ADCR1 To control the function and operation of the A/D converter, two control registers known as ADCR0 and ADCR1 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As these devices contain only one actual analog to digital converter hardware circuit, each of the external and internal analog signals must be routed to the converter. The ACS3~ACS0 bits in the ADCR0 register and the TSE and BGMEN bits in the TSC1 and TSC0 registers are used to determine that the specific external channel input or relevant internal temperature sensor signal is selected to be converted. If the internal temperature sensor analog signal is selected to be converted, the ACS3~ACS0 bits should be set as "1xxx" together with proper configurations of TSE and BGMEN bits. TSE BGMEN ACS3~ACS0 Input Signals 0 x x000~x111 AN0~AN7 1 0 1xxx VTSO 1 1 1xxx VTSVREF Description External channel analog input Temperature Sensor output voltage Temperature Sensor reference voltage A/D Converter Input Signal Selection The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input. • ADCR0 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name START ADBZ ADCEN ADRFS ACS3 ACS2 ACS1 ACS0 R/W R/W R R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6 ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5 ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair known as ADRH and ADRL will be cleared to zero. 159 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 4 ADRFS: A/D conversion data format select 0: A/D converter data format → ADRH = D [11:4]; ADRL = D [3:0] 1: A/D converter data format → ADRH = D [11:8]; ADRL = D [7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D converter data register section. Bit 3~0 ACS3~ACS0: A/D converter analog input signal select 0000: External AN0 input 0001: External AN1 input 0010: External AN2 input 0011: External AN3 input 0100: External AN4 input 0101: External AN5 input 0110: External AN6 input 0111: External AN7 input 1xxx: Internal signal from temperature sensor – temperature output voltage or reference voltage The "1xxx" selection is only available when the TSE bit is set to 1. To select the internal temperature sensor signal to be converted, these bits must be set as "1xxx" when the TSE bit is set to 1. Otherwise, these bits are used to select the external ANn channel input without the regard of the ACS3 value if the TSE bit is cleared to 0. • ADCR1 Register Bit 7 6 5 4 3 2 1 0 Name ATM — IDLE_CONV VREFS — ADCK2 ADCK1 ADCK0 R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — 0 0 0 Bit 7 Rev. 1.40 ATM: A/D auto-conversion mode enable control 0: Disable 1: Enable When this bit is set to 1, the A/D converter will continuously perform the data conversion after the current conversion is complete without configuring the "START" bit by application program. Note that the A/D conversion data can only be read in the A/D conversion completion interrupt service subroutine when the A/D auto-conversion mode is enabled. Bit 6 Unimplemented, read as "0" Bit 5 IDLE_CONV: CPU idle conversion mode enable control 0: Disable 1: Enable When this bit is set to 1, the A/D conversion with CPU idle mode will be enabled. The CPU will not operate when the A/D converter is operating with the IDLE_CONV bit being set to 1 until the conversion is completed. Bit 4 VREFS: A/D converter reference voltage select 0: Internal A/D converter power 1: VREF pin This bit is used to select the A/D converter reference voltage and only available when the VREFP_EXT bit in the TSC2 register is set to 1. It is recommended to keep the VREFP_EXT bit low when the internal temperature sensor signal is selected to be converted. Bit 3 Unimplemented, read as "0" 160 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2~0 ADCK2~ADCK0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These bits are used to select the clock source for the A/D converter. It is recommended that the A/D conversion clock frequency should be in the range from 500 kHz to 1MHz by properly configuring the ADCK2~ADCK0 bits when the internal temperature sensor signal is selected to be converted as temperature sensor enabled, • TSC0 Register Bit 7 6 5 4 3 2 1 0 Name BGMEN G5XEN K_REFO — — — — — R/W R/W R/W R/W — — — — — POR 0 1 0 — — — — — Bit 7 BGMEN: Temperature sensor reference voltage output function enable control 0: Disable 1: Enable This bit controls the internal temperature sensor reference voltage output function and is only available when the TSE bit is set to 1. The internal temperature sensor reference voltage can be converted when the TSE and BGMEN bits are set to 1 and the ACS bit field is set to "1xxx". However, the internal temperature sensor output voltage will be converted if the TSE bit is set to 1 and the BGMEN bit is cleared to 0 together with ACS bit field equal to "1xxx". Bit 6 G5XEN: OPA2 gain select 0: Gain=4 1: Gain=5 This bit controls the OPA2 gain selection. This bit should be properly selected for different temperature range applications to avoid the saturated code. Bit 5 K_REFO: OPA1 gain select 0: Gain=1.675 1: Gain=1 This bit is used to select the OPA1 gain to determine the temperature sensor reference voltage output value. Bit 4~0 Unimplemented, read as "0" • TSC1 Register Bit 7 6 5 4 3 2 1 0 Name TSE OP2EN OP1EN — — — — — R/W R/W R/W R/W — — — — — POR 0 0 0 — — — — — Bit 7 Rev. 1.40 TSE: Temperature sensor circuitry enable control 0: Disable 1: Enable This bit controls the internal temperature sensor circuitry. When the temperature sensor is enabled by setting the TSE bit to 1, a time named as tTSS should be allowed for the temperature sensor circuit to stabilise before implementing relevant temperature sensor operation. 161 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 6 OP2EN: Temperature sensor OPA2 enable control 0: Disable 1: Enable Bit 5 OP1EN: Temperature sensor OPA1 enable control 0: Disable 1: Enable Bit 4~0 Unimplemented, read as "0" • TSC2 Register Bit 7 6 5 4 3 2 Name VREFP_EXT BIAS D5 D4 D3 D2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 TSCLK_S1 TSCLK_S0 Bit 7 VREFP_EXT: A/D converter positive reference voltage select 0: Temperature reference voltage – VTSVREF 1: Determined by VREFS bit This bit is used to select the A/D converter positive reference voltage. When this bit is set to 1, the A/D converter reference voltage is determines by the VREFS bit in the ADCR1 register. However, this bit should be set low to select the VTSVREF voltage as the A/D converter reference voltage together with proper configurations of the OPA2 input signal and gain. Bit 6 BIAS: OPA2 bias voltage select 0: VTSVREF 1: Internal A/D converter power Bit 5~2 D5~D2: Data bits for internal used These bits should be kept low and can not be changed. Bit 1~0 TSCLK_S1~TSCLK_S0: Temperature sensor clock source tTSCLK select 00: tTSCLK = tADCK/4 01: tTSCLK = tADCK/8 1x: tTSCLK = tADCK/16 The temperature sensor signal conversion time can be obtained using the equation: Temperature sensor signal conversion time = (5×N+1+16) × tADCK In the above equation "N" represents the divided ratio, 4, 8 or 16, which is determined by the TSCLK_S1 and TSCLK_S0 bits. • TSC3Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — K_VPTAT — — — — — R/W — — R/W — — — — — POR — — 0 — — — — — Bit 7~6 Unimplemented, read as "0" Bit 5 K_VPTAT: OPA1 input voltage select 0: VBG 1: VPTAT This bit is used to select the OPA1 input voltage to obtain the internal temperature sensor reference voltage. Bit 4~0 Unimplemented, read as "0" 162 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Operation The START bit in the ADCR0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the ADCR0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the system clock fSYS and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 8MHz, the ADCK2~ADCK0 bits should not be set to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. However, the recommended A/D clock period is from 1μs to 2μs if the input signal to be converted is the temperature sensor output voltage or reference voltage. A/D Clock Period (tADCK) fSYS ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] ADCK[2:0] = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 (fSYS) (fSYS/2) (fSYS/4) (fSYS/8) (fSYS/16) (fSYS/32) (fSYS/64) (fSYS/128) 1 MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 2 MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 128μs * 64μs * 4 MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8 MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 12 MHz 83ns * 167ns * 333ns * 667ns 1.33μs 2.67μs 5.33μs 10.67μs * 16 MHz 62.5ns * 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 20 MHz 50ns * 100ns * 200ns * 400ns * 800ns 1.6μs 3.2μs 6.4μs A/D Clock Period Examples for External Analog Inputs However, the recommended A/D clock period is from 1μs to 2μs if the input signal to be converted is the temperature sensor output voltage or reference voltage. Controlling the power on/off function of the A/D converter circuitry is implemented using the ADCEN bit in the ADCR0 register. This bit must be set high to power on the A/D converter. When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used. Rev. 1.40 163 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Reference Voltage The reference voltage supply to the A/D Converter can be supplied from the positive power supply pin, VDD, an external reference source supplied on pin VREF or an internal temperature sensor reference voltage VTSVREF. The internal temperature sensor reference voltage can be derived from the intenal VBG or VPTAT voltage selected using the K_VPTAT bit in the TSC3 register and then amplified through a programmable gain amplifier except the one sourced from VDD. The PGA gain can be equal to 1.675 or 1 selected by the K_REFO bit in the TSC0 register. As the VREF pin is pin-shared with other functions, when the VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control bits should first be properly configured to disable other pin-shared functions. A/D Converter Input Pins All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions. The corresponding pin-shared function selection bits in the PxS0 and PxS1 registers, determine whether the external input pins are setup as A/D converter analog channel inputs or whether they have other functions. If the corresponding pin is setup to be an A/D converter analog channel input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pin, VREF. However, the reference voltage can also be supplied from the power supply pin or an internal temperature sensor circuit, a choice which is made through the VREFP_EXT and VREFS bits in the TSC2 and ADCR1 register respectively. Note that the analog input signal values must not be allowed to exceed the value of the selected A/D reference voltage. Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary. However, an A/D conversion for an internal temperature sensor signal will take a total of 56 A/D clock cycles. Maximum single A/D conversion rate = A/D clock period / 16 (External channel input signal) Maximum single A/D conversion rate = A/D clock period / 56 (Internal Temperature sensor signal) The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. Rev. 1.40 164 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver tON�ST ADCEN off on off A/D sa�pling ti�e tADS A/D sa�pling ti�e tADS Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion on START ADBZ ACS[3:0] (TSE=0) End of A/D �onve�sion x011B A/D �hannel swit�h End of A/D �onve�sion x010B tADC A/D �onve�sion ti�e Sta�t of A/D �onve�sion x000B tADC A/D �onve�sion ti�e x001B tADC A/D �onve�sion ti�e A/D Conversion Timing – External Channel Input Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by properly programming the ADCK2~ADCK0 bits in the ADCR1 register. • Step 2 Enable the A/D converter by setting the ADCEN bit in the ADCR0 register to one. • Step 3 Select which signal is to be connected to the internal A/D converter by correctly configuring the ACS3~ACS0 bits If the TSE bit is 0 and ACS3~ACS0 bits are equal to x000~x111, then an external channel input is selected. If the TSE bit is 1 and ACS3~ACS0 bits are equal to 1xxx, then the relevant internal temperature sensor signal is selected. • Step 4 Select the reference voltgage source by configuring the K_VPTAT, K_REFO and VREFS bits. • Step 5 Select the A/D converter output data format by configuring the ADRFS bit. • Step 6 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt bontrol bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance. • Step 7 The A/D conversion procedure can now be initialized by setting the START bit from low to high and then low again. • Step 8 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is complete, the ADBZ flag will go low and then the output data can be read from ADRH and ADRL registers. Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit in the ADCR0 register is used, the interrupt enable step above can be omitted. However, the interrupt method must be used to check for the end of the conversion process and obtain the corresponding digital output data if the auto-conversion mode is enabled. Rev. 1.40 165 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADCEN low in the ADCR register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Converter Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the reference voltage, this gives a single bit analog input value of reference voltage value divided by 4096. 1 LSB = VREF ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × VREF ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. Ideal A/D Transfer Function Rev. 1.40 166 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE; disable ADC interrupt set VREFP_EXT ; deselect the temperature sensor reference voltage mov a,03H; select fSYS/8 as A/D clock and A/D internal power supply mov ADCR1,a ; as reference voltage set ADCEN mov a,03H ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20H mov ADCR0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D : polling_EOC: sz ADBZ ; poll the ADCR0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling : mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Rev. 1.40 167 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Example: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt set VREFP_EXT ; deselect the temperature sensor reference voltage mov a,03H; select fSYS/8 as A/D clock and A/D internal power supply mov ADCR1,a ; as reference voltage set ADCEN mov a,03h ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20H mov ADCR0,a ; enable and connect AN0 channel to A/D converter : Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE; enable ADC interrupt set EMI ; enable global interrupt : : ADC_ISR: ; ADC interrupt service routine mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : mov a, ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.40 168 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four-line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pullhigh control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices, etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the devices can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, these devices provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.40 169 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SPI Master/Slave Connection SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC2 D7 D6 CKPOLB CKEG MLS SIMD D7 D6 D5 D4 D3 3 2 1 0 SIMEN SIMICF CSEN WCOL TRF D2 D1 D0 SIMDEB1 SIMDEB0 SPI Registers List • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Rev. 1.40 170 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc. • SIMC0 Register Rev. 1.40 Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 R/W R/W R/W R/W — R/W POR 1 1 1 — 0 2 1 0 SIMEN SIMICF R/W R/W R/W 0 0 0 SIMDEB1 SIMDEB0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce Time Selection Described elsewhere. Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI slave mode Incomplete Transfer Flag 0: SIM SPI slave mode incomplete condition not occurred 1: SIM SPI slave mode incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operates in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 together with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However, the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program. 171 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • SIMC2 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0 TRF: SPI Transmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. 172 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG = 0 Rev. 1.40 173 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Note: For SPI slave mode, if SIMEN=1 and CSEN=0, the SPI is always enabled and ignores the SCS level. SPI Slave Mode Timing – CKEG = 1 SPI Transfer Control Flow Chart Rev. 1.40 174 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection I2C interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. Rev. 1.40 175 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) No Devounce fSYS > 2 MHz fSYS > 5 MHz 2 system clock debounce fSYS > 4 MHz fSYS > 10 MHz fSYS > 8 MHz fSYS > 20 MHz 4 system clock debounce I2C Fast Mode (400kHz) I C Minimum fSYS Frequency 2 I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Bit Register Name 7 6 5 4 3 2 0 SIMC0 SIM2 SIM1 SIM0 — SIMEN SIMICF SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMTOC SIMTOEN SIMDEB1 SIMDEB0 1 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Registers List Rev. 1.40 176 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown • SIMA Register The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x Bit 7~1 Bit 0 x "x": unknown IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0 Undefined bit The bit can be read or written by the application program. There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency.The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status. • SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W R/W POR 1 1 1 — 0 0 Bit 7~5 Rev. 1.40 3 2 SIMDEB1 SIMDEB0 1 0 SIMEN SIMICF R/W R/W 0 0 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. 177 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. SIMICF: SIM SPI slave mode Incomplete Transfer Flag Described elsewhere. Bit 0 • SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Rev. 1.40 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. 178 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0 RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match, 8-bit data transfer completion or I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 bits to "110" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. Rev. 1.40 179 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver I2C Bus Initialisation Flow Chart • I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. • I2C Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out occurrence. When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. Rev. 1.40 180 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. • I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". • I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Rev. 1.40 181 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram I2C Bus ISR Flow Chart Rev. 1.40 182 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus "START" & "address match"condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. S C L S ta rt IIC S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 1 A C K 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out When an I C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: 2 Register After I2C Time-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I2C Register after Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms. Rev. 1.40 183 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver • SIMTOC Register Bit 7 Name SIMTOEN 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7 SIMTOEN: SIM I2C Time-out control 0: Disable 1: Enable Bit 6 SIMTOF: SIM I2C Time-out flag 0: No time-out occurred 1: Time-out occurred Bit 5~0 SIMTOS5~SIMTOS0: SIM I2C Time-out period selection I2C Time-out clock source is fSUB/32 I2C Time-out period is equal to (SIMTOS [5 : 0] + 1) × 32 f SUB UART Interface These devices contain an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, asynchronous communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Separately enabled transmitter and receiver • 2-byte Deep FIFO Receive Data Buffer • RX pin wake-up function • Transmit and receive interrupts • Rev. 1.40 Interrupts can be initialized by the following conditions: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect 184 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver T�ans�itte� Shift Registe� (TSR) MSB ………………………… LSB TX Pin TX Registe� (TXR) RX Pin Re�eive� Shift Registe� (RSR) MSB ………………………… LSB RX Registe� (RXR) Buffe� Baud Rate Gene�ato� fSYS Data to �e t�ans�itted Data �e�eived MCU Data Bus UART Data Transfer Block Diagram UART External Pin To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX and RX pins are the UART transmitter and receiver pins respectively. The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UART function is used. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TXEN or RXEN bit, the TX or RX pin will be set to a floating state. At this time whether the internal pullhigh resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pullhigh function control bit. UART Data Transfer Scheme The above diagram shows the overall data transfer structure arrangement for the UART interface. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the TXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR_ RXR data registers. Rev. 1.40 185 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 TXRX7~TXRX0: UART Transmit/Receive Data bits USR Register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only and further explanations are given below. Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error. When the flag is "1", it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4 OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is "0", it indicates that there is no overrun error. When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. 186 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Rev. 1.40 Bit 3 RIDLE: Receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty. When the flag is "1", it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: Transmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: Transmit TXR data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicates that the character is not transferred to the transmitter shift register. When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. 187 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UCR1 Register The UCR1 register together with the UCR2 register are the UART control registers that are used to set the various options for the UART function such as overall on/off control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Rev. 1.40 0 "x": unknown UARTEN: UART function enable control 0: Disable UART; TX and RX pins are in a floating state. 1: Enable UART; TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to "0", the UART will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to "1", the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This bit is the parity function enable bit. When this bit is equal to 1, the parity function will be enabled. If the bit is equal to 0, then the parity function will be disabled. PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will be selected. If the bit is equal to 0, then even parity type will be selected. STOPS: Number of stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits format are used. If the bit is equal to "0", then only one stop bit format is used. TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is equal to "0", there are no break characters and the TX pin operats normally. When the bit is equal to "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. 188 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below. Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART Transmitter enable control 0: UART Transmitter is disabled 1: UART Transmitter is enabled The TXEN bit is the Transmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be set in a floating state. If the TXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be set in a floating state. Bit 6 RXEN: UART Receiver enable control 0: UART Receiver is disabled 1: UART Receiver is enabled The RXEN bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receiver buffers will be reset. In this situation the RX pin will be set in a floating state. If the RXEN bit is equal to "1" and the UARTEN bit is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be set in a floating state. Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register, BRG, controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. 189 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Rev. 1.40 Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, has a value of "1", then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the receiver wake-up function. If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake up the device. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the receiver interrupt. If this bit is equal to 1 and when the receiver overrun flag OERR or received data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0 TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UART interrupt request flag will not be influenced by the condition of the TXIF flag. 190 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the BRG register and the second is the value of the BRGH bit within the UCR2 control register. The BRGH bit decides, if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register, N, which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) f SYS [64( N + 1)] fSYS [16( N + 1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in the UCR2 register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = Re-arranging this equation gives N = Giving a value for N = f SYS [64( N + 1)] fSYS −1 (BR × 64) 4000000 − 1 = 12.0208 (4800 × 64) To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives 4000000 an actual or calculated baud rate value of BR= [64(12 + 1)] = 4808 Therefore the error is equal to Rev. 1.40 4808 − 4800 = 0.16% 4800 191 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits and one or two stop bits. Parity is supported by the UART hardware and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and these two pins will be used as an I/O or other pin-shared functional pin. When the UART function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9. The PRT bit controls the choice if odd or even parity. The PREN bit controls the parity on/off function. The STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bit Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format Rev. 1.40 192 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. 8-Bit Data Format 9-Bit Data Format UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/ O or other pin-shared function. Transmitting Data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit LSB first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. Rev. 1.40 193 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level, then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, will be stored in the RX8 bit in the UCR1 register. At the receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is received on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Rev. 1.40 194 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Receiving Data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin to the shift register, with the least significant bit LSB first. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the 3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur: • The RXIF bit in the USR register will be set then RXR register has data available, at least one more character can be read. • When the contents of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated. • If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A RXR register read execution Receiving Break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Rev. 1.40 195 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag, RXIF, in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a 3th byte can continue to be received. Before the 3th byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Noise Error – NF Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame, the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared in any reset. Parity Error – PERR The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. Rev. 1.40 196 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UART Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. UCR� Registe� USR Registe� T�ans�itte� E�pty Flag TXIF TEIE T�ans�itte� Idle Flag TIDLE TIIE 1 RIE OR Re�eive� Data Availa�le RXIF WAKE 0 1 Re�eive� Ove��un Flag OERR RX Pin Wake-up 0 ADDEN URE 0 1 EMI 0 1 Inte��upt signal to MCU 1 0 1 0 0 UART Inte��upt Request Flag URF 0 1 RX7 if BNO=0 RX8 if BNO=1 1 UCR� Registe� UART Interrupt Structure Rev. 1.40 197 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register, enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is equal to 0, then a Receive Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN Bit 9 if BNO=1 Bit 8 if BNO=0 UART Interrupt Generated 0 √ 0 1 1 √ 0 X 1 √ ADDEN Bit Function UART Power Down and Wake-up When the MCU system clock is switched off, the UART will cease to function. If the MCU executes the "HALT" instruction and switches off the system clock while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU executes the "HALT" instruction and switches off the system clock while receiving data, then the reception of data will likewise be paused. When the MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the IDLE or SLEEP mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the IDLE0 or SLEEP Mode, then a falling edge on the RX pin will wake up the MCU from the IDLE0 or SLEEP Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Rev. 1.40 198 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin shared with the I/O pins, with the desired function chosen via the pin-shared selection register bit. Keys are organised into several groups, with each group known as a module and having a module number, M0 to Mn. Each module is a fully independent set of four Touch Keys and each Touch Key has its own oscillator. Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device BS66F370 BS66F360 BS66F350 BS66F340 Total Key Number Touch Key Module Touch Key M0 KEY1~KEY4 36 28 20 12 M1 KEY5~KEY8 M2 KEY9~KEY12 M3 KEY13~KEY16 M4 KEY17~KEY20 M5 KEY21~KEY24 M6 KEY25~KEY28 M7 KEY29~KEY32 M8 KEY33~KEY36 M0 KEY1~KEY4 M1 KEY5~KEY8 M2 KEY9~KEY12 M3 KEY13~KEY16 M4 KEY17~KEY20 M5 KEY21~KEY24 M6 KEY25~KEY28 M0 KEY1~KEY4 M1 KEY5~KEY8 M2 KEY9~KEY12 M3 KEY13~KEY16 M4 KEY17~KEY20 M0 KEY1~KEY4 M1 KEY5~KEY8 M2 KEY9~KEY12 Touch Key Structure Rev. 1.40 199 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Key KEY 1 OSC TKMn1�DH / TKMn1�DL ( to Data Me�o�y Se�to� �) Key KEY � OSC Mux . Filte� Multif�equen�y 1�-�it C/F Counte� TKCFOV Key KEY 3 OSC MnDFEN Key KEY 4 OSC TKMnC� TKMnROH / TKMnROL ( f�o� Data Me�o�y Se�to� �) MnTSS fSYS/4 Refe�en�e Os�illato� Filte� TKTMR M U X 8-�it Ti�e Slot Counte� �-�it unit pe�iod �ounte� TKRCOV Module 0 Module n 1�-�it C/F Counte� Value (Se�to� �) TKTMR 8-�it Ti�e Slot Counte� P�eload Registe� fSYS fSYS/� fSYS/4 fSYS/8 Refe�en�e Os�. Capa�ito� Value (Se�to� �) Ove�flow M U X 1�-�it Counte� TK1�OV TK1�DL / TK1�DH TK1�S1~TK1�S0 Tou�h Key Data Me�o�y Note: The structure contained in the dash line is identical for each touch key module which contains four touch keys. Touch Key Function Block Diagram Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the Touch Key module number. The series of devices has up to seven Touch Key Modules dependent upon the selected device. Name TKTMR Description Touch key time slot 8-bit counter proload register TKC0 Touch key function Control register 0 TKC1 Touch key function Control register 1 TK16DL Touch key function 16-bit counter low byte TK16DH Touch key function 16-bit counter high byte TKMn16DL Touch key module n 16-bit C/F counter low byte TKMn16DH Touch key module n 16-bit C/F counter high byte TKMnROL Touch key module n reference oscillator capacitor select low byte TKMnROH Touch key module n reference oscillator capacitor select high byte TKMnC0 Touch key module n Control register 0 TKMnC1 Touch key module n Control register 1 TKMnC2 Touch key module n Control register 2 Touch Key Module Registers List Rev. 1.40 200 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 TKTMR D7 D6 D5 D4 D3 D2 D1 D0 — TKMOD TKBUSY TKC1 D7 D6 D5 TSCS TK16S1 TK16S0 TKFS1 TKFS0 TK16DL D7 D6 D5 D4 D3 D2 D1 D0 TK16DH D15 D14 D13 D12 D11 D10 D9 D8 TKC0 TKRAMC TKRCOV TKCFOV TK16OV TKST TKMn16DL D7 D6 D5 D4 D3 D2 D1 D0 TKMn16DH D15 D14 D13 D12 D11 D10 D9 D8 TKMnROL D7 D6 D5 D4 D3 D2 D1 D0 TKMnROH — — — — — — D9 D8 TKMnC0 — — MnDFEN D4 MnROEN MnKOEN MnK4EN MnK3EN MnK2EN MnK1EN TKMnC1 MnTSS — TKMnC2 MnSK31 MnSK30 MnSK21 MnSK20 MnSOFC MnSOF2 MnSOF1 MnSOF0 MnSK11 MnSK10 MnSK01 MnSK00 Touch Key Function Registers List TKTMR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 D7~D0: Touch key time slot 8-bit counter proload register The touch key time slot counter proload register is used to determine the touch key time slot overflow time. The time slot unit period is obtained by a 5-bit counter and equal to 32 time slot clock cycles. Therefore, the time slot counter overflow time is equal to the following equation shown. Time slot counter overflow time= (256 - TKTMR[7:0])×32 tTSC, where tTSC is the time slot counter clock. Bit 7~0 TKC0 Register Bit Name Rev. 1.40 7 6 TKRAMC TKRCOV 5 4 3 2 1 0 TKST TKCFOV TK16OV — TKMOD TKBUSY R/W R/W R/W R/W R/W R/W — R/W R/W POR 0 0 0 0 0 — 0 0 Bit 7 TKRAMC: Touch key Data RAM access control 0: Accessed by MCU 1: Accessed by Touch key module This bit determines that the touch key RAM is used by the MCU or touch key module. However, the touch key module will have the priority to access the touch key RAM when the touch key module operates in the auto scan mode, i.e., the TKST bit state is changed from 0 to 1 when the TKMOD bit is set low. After the touch key auto scan operation is completed, i.e., the TKBUSY bit state is changed from 1 to 0, the touch key RAM access will be controlled by the TKRAMC bit. Therefore, it is recommended to set the TKRAMC bit to 1 when the touch key module operates in the auto scan mode. Otherwise, the contents of the touch key RAM may be modified as this RAM space is configured by the touch key module followed by the MCU access. Bit 6 TKRCOV: Touch key time slot counter overflow flag 0: No overflow occurs 1: Overflow occurs 201 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.40 This bit can be accessed by application programs. When this bit is set by touch key time slot counter overflow, the corrrespondingn touch key interrupt request flag will be set. However, if this bit is set by application programs, the touch key interrupt request flag will not be affected. In auto scan mode, if the time slot counter overflows but the touch key auto scan operation is not completed, the TKRCOV bit will not be set. At this time, the touch key module n 16-bit C/F counter, touch key function 16-bit counter and 5-bit time slot unit period counter will be automatically cleared but the 8-bit time slot counter will be reloaded from the 8-bit time slot counter preload register. When the touch key auto scan operation is completed, the TKRCOV bit and the Touch Key Interrupt request flag, TKMF, will be set and all modules key and reference oscillators will automatically stop. The touch key modules 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter will be automatically switched off. In manual scan mode, if the time slot counter overflows, the TKRCOV bit and the Touch Key Interrupt request flag, TKMF, will be set and all modules key and reference oscillators will automatically stop. The touch key module 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter will be automatically switched off. TKST: Touch key detection Start control 0: Stopped or no operation 0→1: Start detection In all modules the touch key module 16-bit C/F counter, touch key function 16-bit counter and 5-bit time slot unit period counter will automatically be cleared when this bit is cleared to zero. However, the 8-bit programmable time slot counter will not be cleared. When this bit is changed from low to high, the touch key module 16-bit C/F counter, touch key function 16-bit counter, 5-bit time slot unie period counter and 8-bit time slot counter will be switched on together with the key and reference oscillators to drive the corresponding counters. TKCFOV: Touch key module 16-bit C/F counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key module 16-bit C/F counter overflow and must be cleared to 0 by application programs. TK16OV: Touch key function 16-bit counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key function 16-bit counter overflow and must be cleared to 0 by application programs. Unimplemented, read as "0" TKMOD: Touch key scan mode select 0: Auto scan mode 1: Manual scan mode In manual scan mode the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read after the scan operation finishes by application program. In auto scan mode the data movement which is described above is implemented by hardware. The individual reference oscillator capacitor value and 16-bit C/F counter content for all scanned keys will be read from and written into a dedicated Touch Key Data Memory area. In auto scan mode the keys to be scaned can be arranged in a specific sequence which is determined by the MnSK3[1:0] ~ MnSK0[1:0] bits in the TKMnC2 register. The scan operation will not be stopped until all arranged keys are scanned. TKBUSY: Touch key scan operation busy flag 0: Not busy – no scan operation is executed or scan operation is complete 1: Busy – scan operation is executing This bit indicates whether the touch key scan operation is executing or not. It is set to 1 when the TKST bit is set high to start the scan operation and cleared to 0 when the touch key time slot counter overflows. 202 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKC1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 TSCS TK16S1 TK16S0 TKFS1 TKFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 D7~D5: Data bits for test only These bits are used for test purpose only and must be kept as "000" for normal operations. Bit 4 TSCS: Touch key time slot counter select 0: Each touch key module uses its own time slot counter 1: All touch key modules use Module 0 time slot counter Bit 3~2 TK16S1~TK16S0: Touch key function 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 Bit 1~0 TKFS1~TKFS0: Touch Key oscillator and Reference oscillator frequency select 00: 500 kHz 01: 1000 kHz 10: 1500 kHz 11: 2000 kHz TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair Register Bit Name TK16DH 7 6 5 4 3 TK16DL 2 1 D15 D14 D13 D12 D11 D10 D9 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can be used to calibrate the reference or key oscillator frequency. When the touch key time slot counter overflows in the manual scan mode, this 16-bit counter will be stopped and the counter content will be unchanged. However, this 16-bit counter content will be cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the time slot 3 in the auto scan mode. This register pair will be cleared to zero when the TKST bit is set low. TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair Register Bit Name TKMn16DH 7 6 5 4 3 TKMn16DL 2 1 D15 D14 D13 D12 D11 D10 D9 0 7 6 5 4 3 2 1 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n 16-bit C/F counter value. This 16-bit C/ F counter will be stopped and the counter content will be kept unchanged when the touch key time slot counter overflows in the manual scan mode. However, this 16-bit C/F counter content will be cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the time slot 3 when the auto scan mode is selected. This register pair will be cleared to zero when the TKST bit is set low. Rev. 1.40 203 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair Register TKMnROH TKMnROL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W — — — — — — POR — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n reference oscillator capacitor value. This register pair will be loaded with the corresponding next time slot capacitor value from the dedicated touch key data memory at the end of the current time slot when the auto scan mode is selected. The reference oscillator internal capacitor value = TKMn [9 : 0]x 50pF . 1024 TKMnC0 Register Rev. 1.40 Bit 7 6 5 4 Name — — MnDFEN D4 3 R/W — — R/W R/W R/W POR — — 0 0 0 2 1 0 MnSOF1 MnSOF0 R/W R/W R/W 0 0 0 MnSOFC MnSOF2 Bit 7~6 Unimplemented, read as "0" Bit 5 MnDFEN: Touch key module n multi-frequency control 0: Disable 1: Enable This bit is used to control the touch key oscillator frequency doubling function. When this bit is set to 1, the key oscillator frequency will be doubled. Bit 4 D4: Data bit for test only The bit is used for test purpose only and must be kept as "0" for normal operations. Bit 3 MnSOFC: Touch key module n C-to-F oscillator frequency hopping function control select 0: Controlled by the MnSOF2~MnSOF0 1: Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value. Bit 2~0 MnSOF2~MnSOF0: Touch key module n Reference and Key oscillators hopping frequency select 000: fHOP0 – Min. hopping frequency 001: fHOP1 010: fHOP2 011: fHOP3 100: fHOP4 – Selected touch key oscillator frequency 101: fHOP5 110: fHOP6 111: fHOP7 – Max. hopping frequency This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value. 204 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnC1 Register Rev. 1.40 Bit 7 6 Name MnTSS — 5 4 R/W R/W — R/W R/W POR 0 — 0 0 3 2 1 0 MnK3EN MnK2EN MnK1EN R/W R/W R/W R/W 0 0 0 0 MnROEN MnKOEN MnK4EN Bit 7 MnTSS: Touch key module n time slot counter clock source select 0: Touch key module n reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: Touch key module n Reference oscillator enable control 0: Disable 1: Enable This bit is used to enable the touch key module n reference oscillator. In auto scan mode the reference oscillator will automatically be enabled by setting the MnROEN bit high when the TKST bit is set from low to high if the reference oscillator is selected as the time slot clock source. The combination of the MnTSS, TSCS and MnK4EN~MnK1EN bits determines whether the reference oscillator is used or not. When the TKBUSY bit is changed from high to low, the MnROEN bit will automatically be set low to disable the reference oscillator. In manual scan mode the reference oscillator should first be enabled before setting the TKST bit from low to high if the reference oscillator is selected to be used and will be disabled when the TKBUSY bit is changed from high to low. Bit 4 MnKOEN: Touch key module n Key oscillator enable control 0: Disable 1: Enable This bit is used to enable the touch key module n key oscillator. In auto scan mode the key oscillator will automatically be enabled by setting the MnKOEN bit high when the TKST bit is set form low to high. When the TKBUSY bit is changed from high to low, the MnKOEN bit will automatically be set low to disable the key oscillator. In manual scan mode the key oscillator shoule first be enabled before setting the TKST bit from low to high if the relevant key is enabled to be scanned and will be disabled when the TKBUSY bit is changed from high to low. Bit 3 MnK4EN: Touch key module n Key 4 enable control 0: Disable 1: Enable Bit 2 MnK3EN: Touch key module n Key 3 enable control 0: Disable 1: Enable Bit 1 MnK2EN: Touch key module n Key 2 enable control 0: Disable 1: Enable Bit 0 MnK1EN: Touch key module n Key 1 enable control 0: Disable 1: Enable 205 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnC2 Register Bit 7 6 5 4 3 2 1 0 Name MnSK31 MnSK30 MnSK21 MnSK20 MnSK11 MnSK10 MnSK01 MnSK00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 0 0 1 0 0 Bit 7~6 MnSK31~MnSK30: Touch key module n time slot 3 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 3 and only available in the auto scan mode. Bit 5~4 MnSK21~MnSK20: Touch key module n time slot 2 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 2 and only available in the auto scan mode. Bit 3~2 MnSK11~MnSK10: Touch key module n time slot 1 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 1 and only available in the auto scan mode. Bit 1~0 MnSK01~MnSK00: Touch key module n time slot 0 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or used as the multiplexer for scan key select in the manual mode. Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. Rev. 1.40 206 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKST MnKOEN MnROEN Ha�dwa�e set to “0” KEY OSC CLK Refe�en�e OSC CLK fCFTMCK Ena�le fCFTMCK (MnDFEN=0) fCFTMCK (MnDFEN=0) TKBUSY TKRCOV Set Tou�h Key inte��upt �equest flag Touch Key Mamual Scan Mode Timing Diagram Each touch key module contains four touch key inputs which are shared logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a Touch Key interrupt signal will be generated in the manual scan mode. Using the TSCS bit in the TKC1 register can select the module 0 time slot counter as the time slot counter for all modules. All modules use the same started signal, TKST, in the TKC0 register. The touch key module 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter in all modules will be automatically cleared when the TKST bit is cleared to zero, but the 8-Bit programmable time slot counter will not be cleared. The overflow time is setup by user. When the TKST bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be automatically stopped and the 16bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched off when the time slot counter overflows. The clock source for the time slot counter is sourced from the reference oscillator or fSYS/4 which is selected using the MnTSS bit in the TKMnC1 register. The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, KEY1 ~ KEY4 are contained in module 0, KEY5 ~ KEY8 are contained in module 1, KEY9 ~ KEY12 are contained in module 3, etc. Each touch key module has an identical structure. Rev. 1.40 207 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Auto Scan Mode There are two scan modes contained for the touch key function. The auto scan mode can minisize the load of the application programs and improve the touch key scan operation performance. The auto scan mode and manual scan mode are selected using the TKMOD bit in the TKC0 register. When the TKMOD bit is set low, the auto scan mode is selcted to scan the keys in each module in a specific sequence determined by the MnSK3[1:0]~MnSK0[1:0] in the TKMnC2 register. Key Auto S�an Cy�le TKST Ti�e slot 0 Module 0 Ti�e slot 1 Ti�e slot 1 Ti�e slot � Ti�e slot � Ti�e slot 3 Ti�e slot 3 Ti�e slot 0 Module 1 Ti�e slot 1 Ti�e slot 1 Ti�e slot � Ti�e slot � Ti�e slot 3 Ti�e slot 3 Ti�e slot 0 Module n Ti�e slot 1 Ti�e slot 1 Ti�e slot � Ti�e slot � Ti�e slot 3 Ti�e slot 3 TKBUSY Clea�ed �y softwa�e TKRCOV Tou�h Key Data Me�o�y A��ess : Set Tou�h Key inte��upt �equest flag : Read �N �ytes f�o� Tou�h Key Data Me�o�y to TKMnROH/TKMnROL �egiste�s : W�ite �N �ytes f�o� TKMn1�DH/TKMn1�DL �egiste�s to Tou�h Key Data Me�o�y N = Tou�h Key Module Nu��e�; n = Module Se�ial Nu��e� Touch Key Auto Scan Mode Timing Diagram Rev. 1.40 208 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In the auto scan mode the key oscillator and reference oscillator will automatically be enabled when the TKST bit is set from low to high and disabled automatically when the TKBUSY bit changes from high to low. When the TKST bit is set from low to high in the auto scan mode, the first reference oscillator internal capacitor value will be read from a specific location of the dedicated touch key data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will be written into the last location of the corresponding touch key module data memory. After this the selected key will be scanned in time slot 0. At the end of the time slot 0 key scan operation, the reference oscillator internal capacitor value for the next selected key will be read from the touch key data memory and loaded into the the next TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value of the current scanned key will be written into the corresponding touch key data memory. The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3. After four keys are scanned, the TKRCOV bit will be set high and the TKBUSY bit will be set low. At the end of the auto scan mode, the first reference oscillator internal capacitor value will again be read from the touch key data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will again be written into the relevant touch key data memory. Touch Key Data Memory The device provides two dedicated Data Memory area for the touch key auto scan mode. One area is used to store the 16-bit C/F counter values of the touch key module 0~n and located in Data Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of the touch key module 0~n and located in Data Memory Sector 6. Touch Key Data Memory Device Sector : Address BS66F340 5: 00H~17H 6: 00H~17H BS66F350 5: 00H~27H 6: 00H~27H BS66F360 5: 00H~37H 6: 00H~37H BS66F370 5: 00H~47H 6: 00H~47H Touch Key Data Memory Summary Rev. 1.40 209 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 16-bit C/F counter value (Sector 5) 00H 01H 02H Ref. OSC Capacitor value (Sector 6) TKM016DL_K1 TKM0ROL_K1 TKM016DH_K1 TKM0ROH_K1 TKM016DL_K2 TKM0ROL_K2 TKM016DH_K2 TKM0ROH_K2 TKM016DL_K3 Module 0 TKM016DH_K3 Touch Key Circuit 16-bit C/F counter TKM016DL_K4 TKM0ROL_K4 TKM016DH_K4 TKM0ROH_K4 TKM116DL_K1 TKM1ROL_K1 TKM116DH_K1 TKM1ROH_K1 TKM116DL_K2 TKM116DH_K2 TKMnROL / TKMnROH Step 1 10-bit Ref. OSC capacitor TKM116DL_K3 TKM1ROL_K2 Module 1 TKM116DH_K3 Step 2 TKM1ROL_K3 TKM1ROH_K3 TKM116DL_K4 TKM1ROL_K4 TKM1ROH_K4 TKM216DL_K1 TKM2ROL_K1 TKM216DH_K1 TKM2ROH_K1 TKM216DL_K2 TKM216DL_K3 TKM2ROL_K2 Module 2 TKM216DH_K3 TKM2ROH_K2 TKM2ROL_K3 TKM2ROH_K3 TKM216DL_K4 TKM2ROL_K4 TKM216DH_K4 TKM2ROH_K4 TKMn16DL_K1 TKMnROL_K1 TKMn16DH_K1 TKMnROH_K1 TKMn16DL_K2 TKMn16DH_K2 TKMn16DL_K3 TKMn16DH_K3 xxH TKM1ROH_K2 TKM116DH_K4 TKM216DH_K2 TKMn16DL / TKMn16DH TKM0ROL_K3 TKM0ROH_K3 TKMnROL_K2 Module n TKMnROH_K2 TKMnROL_K3 TKMnROH_K3 TKMn16DL_K4 TKMnROL_K4 TKMn16DH_K4 TKMnROH_K4 Touch Key Data Memory Map Rev. 1.40 210 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Scan Operation Flow Chart Start Write Ref. OSC Capacitor to TKMnROH/TKMnROL Touch Key Manual Scan Operation Start Set Start bit TKST 0 à 1 ð Busy flag TKBUSY=1 Initiate Time Slot & 16-bit C/F Counter All Time Slot & 16-bit C/F Counter Start to count Time Slot & 16-bit C/F Counter Keep counting TKRCOV=0 All Time Slot Counter overflow ? TKRCOV=1 Touch key busy flag TKBUSY=0 Generate Interrupt request flag Read C/F counter from TKMn16DH/TKMn16DL Touch key scan end Set TKST bit 1 à 0 End Touch Key Manual Scan Mode Flow Chart – TKMOD=1, TSCS=0 Rev. 1.40 211 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Start Write Ref. OSC internal Capacitor value to Data Memory (Sector 6 ) Touch Key Auto Scan Operation Start Set Start bit TKST 0 à 1 ð Busy flag TKBUSY=1 Load Ref. OSC internal Capacitor value from Data Memory (Sector 6 ) Store C/F counter value to Data Memory (Sector 5 ) Touch key busy flag TKBUSY=0 Initiate Time Slot & 16-bit C/F Counter TKRCOV = 1 Generate Interrupt request flag All Time Slot counter & 16-bit C/F counter Start to count Touch key scan end Set TKST bit 1 à 0 Time Slot & 16-bit C/F Counter Keep counting No All Time Slot Counter overflow ? Read C/F counter value from Data Memory (Sector 5) Yes All key scan finish ? No Change next key End Yes Touch Key Auto Scan Mode Flow Chart – TKMOD=0, TSCS=0 Touch Key Interrupt The touch key only has single interrupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. The 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. Progrsmming Considerations After the relevant registers are setup, the touch key detection process is initiated the changing the TKST Bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag which is the time slot counter flag will go high when the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. Rev. 1.40 212 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN VBGEN VLVD2 VLVD1 VLVD0 R/W — — R R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Uunimplemented, read as "0" Bit 5 LVDO: LVD output flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4 LVDEN: Low Voltage Detector Enable control 0: Disable 1: Enable Bit 3 VBGEN: Bandgap Voltage Output Enable control 0: Disable 1: Enable Bit 2~0 VLVD2~VLVD0: LVD Voltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V 213 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.40 214 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Touch Key, Time Base, LVD, EEPROM, SIM, UART and the A/D converter, etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual interrupts as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag EMI — — INTn Pins INTnE INTnF n=0~1 Touch Key — Global Notes TKME TKMF UART URE URF — Multi-function MFnE MFnF n=0~3 A/D Converter ADE ADF — Time Base TBnE TBnF n=0~1 LVD LVE LVF — EEPROM write operation DEE DEF — SIM SIME SIMF — CTMnPE CTMnPF CTMnAE CTMnAF PTMPE PTMPF PTMAE PTMAF STMPE STMPF STMAE STMAF CTM PTM STM n=0~1 — — Interrupt Register Bit Naming Conventions Rev. 1.40 215 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — TKMF INT1F INT0F TKME INT1E INT0E EMI INTC1 ADF MF1F MF0F URF ADE MF1E MF0E URE INTC2 MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E MFI0 — — CTM0AF CTM0PF — — CTM0AE CTM0PE CTM1AE CTM1PE MFI1 STMAF STMPF CTM1AF CTM1PF STMAE STMPE MFI2 — SIMF PTMAF PTMPF — SIME PTMAE PTMPE MFI3 — — DEF LVF — — DEE LVE Interrupt Registers List INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 0 Bit 7~4 Bit 3~2 Bit 1~0 Unimplemented, read as "0" INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 Name — TKMF INT1F INT0F TKME INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W — 0 0 0 0 0 0 0 POR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Rev. 1.40 Unimplemented, read as "0" TKMF: Touch key interrupt request flag 0: No request 1: Interrupt request INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request TKME: Touch key interrupt control 0: Disable 1: Enable INT1E: INT1 interrupt control 0: Disable 1: Enable INT0E: INT0 interrupt control 0: Disable 1: Enable 216 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 0 EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Name ADF MF1F MF0F URF ADE MF1E MF0E URE R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 POR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request MF1F: Multi-function 1 interrupt request flag 0: No request 1: Interrupt request MF0F: Multi-function 0 interrupt request flag 0: No request 1: Interrupt request URF: UART transfer interrupt request flag 0: No request 1: Interrupt request ADE: A/D Converter interrupt control 0: Disable 1: Enable MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable MF0E: Multi-function 0 interrupt control 0: Disable 1: Enable URE: UART transfer interrupt control 0: Disable 1: Enable INTC2 Register Rev. 1.40 Bit 7 6 5 4 3 2 1 0 Name MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF3F: Multi-function 3 interrupt request flag 0: No request 1: Interrupt request Bit 6 TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 MF2F: Multi-function 2 interrupt request flag 0: No request 1: Interrupt request Bit 3 MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable 217 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Bit 1 TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 0 MF2E: Multi-function 2 interrupt control 0: Disable 1: Enable MFI0 Register Bit 7 6 5 4 3 2 Name — — CTM0AF CTM0PF — — R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 1 0 Bit 7~6 Bit 5 Bit 4 Bit 3~2 Bit 1 Bit 0 1 0 CTM0AE CTM0PE Unimplemented, read as "0" CTM0AF: CTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request CTM0PF: CTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Unimplemented, read as "0" CTM0AE: CTM0 Comparator A match Interrupt control 0: Disable 1: Enable CTM0PE: CTM0 Comparator P match Interrupt control 0: Disable 1: Enable MFI1 Register Rev. 1.40 Bit 7 6 5 4 3 2 Name STMAF STMPF CTM1AF CTM1PF STMAE STMPE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 STMAF: STM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6 STMPF: STM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5 CTM1AF: CTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 CTM1PF: CTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 STMAE: STM Comparator A match Interrupt control 0: Disable 1: Enable Bit 2 STMPE: STM Comparator P match Interrupt control 0: Disable 1: Enable 218 CTM1AE CTM1PE December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 CTM1AE: CTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 CTM1PE: CTM1 Comparator P match Interrupt control 0: Disable 1: Enable MFI2 Register Bit 7 6 5 4 3 2 1 0 Name — SIMF PTMAF PTMPF — SIME PTMAE PTMPE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 5 PTMAF: PTM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMPF: PTM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 SIME: SIM Interrupt control 0: Disable 1: Enable Bit 1 PTMAE: PTM Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 PTMPE: PTM Comparator P match Interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name — — DEF LVF — — DEE LVE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Bit 7 Bit 4 Bit 3~2 Bit 1 Bit 0 Rev. 1.40 Unimplemented, read as "0" DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Unimplemented, read as "0" DEE: Data EEPROM Interrupt control 0: Disable 1: Enable LVE: LVD Interrupt control 0: Disable 1: Enable 219 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/ D conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.40 220 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Legend xxF Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits Interrupts contained within Multi-Function Interrupts CTM0 P CTM0PF CTM0PE CTM0 A CTM0AF CTM0AE CTM1 P CTM1PF CTM1PE CTM1 A CTM1AF CTM1AE STM P STMPF STMPE STM A STMAF STMAE PTM P PTMPF PTMPE PTM A PTMAF PTMAE SIM SIMF SIME LVD LVF LVE EEPROM DEF DEE EMI auto disabled in ISR Interrupt Name Request Flags Enable Bits Master Enable INT0 Pin INT0F INT0E EMI INT1 Pin INT1F INT1E EMI 08H Touch Key TKMF TKME EMI 0CH UART URF URE EMI 10H M. Funct. 0 MF0F MF0E EMI 14H M. Funct. 1 MF1F MF1E EMI 18H A/D ADF ADE EMI 1CH M. Funct. 2 MF2F MF2E EMI 20H Time Base 0 TB0F TB0E EMI 24H Time Base 1 TB1F TB1E EMI 28H M. Funct. 3 MF3F MF3E EMI 2CH Vector Priority High 04H Low Interrupt Scheme External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.40 221 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Interrupt For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the Touch Key interrupt enable TKME must be first set. An actual Touch Key interrupt will take place when the Touch Key request flag, TKMF, is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the Touch Key interrupt request flag, TKMF, will be automatically reset and the EMI Bit will be automatically cleared to disable other interrupts. UART Transfer Interrupt The UART Transfer Interrupt is controlled by several UART transfer conditions. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and UART Interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the UART Interrupt vector, will take place. When the interrupt is serviced, the UART Interrupt flag, URF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupt Within the device there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM interrupts, LVD interrupt, EEPROM write operation interrupt and SIM interface interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program. Rev. 1.40 222 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Time Base Interrupt The function of the Time Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer. When this happens its interrupt request flag, TBnF, will be set. To allow the program to branch to its respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bit, TBnE, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL0[1:0] and CLKSEL1[1:0] bits in the PSCR0 and PSCR1 register respectively. fSYS fSYS/4 fSUB M U X fPSC0 Prescaler 0 TB0ON fPSC0/28 ~ fPSC0/215 M U X TB0[2:0] CLKSEL0[1:0] fSYS fSYS/4 fSUB M U X fPSC1 Time Base 0 Interrupt Prescaler 1 fPSC1/28 ~ fPSC1/215 M U X TB1ON CLKSEL1[1:0] Time Base 1 Interrupt TB1[2:0] Time Base Interrupts PSCR0 Register Bit 7 6 5 4 3 2 Name — — — — — — 1 0 CLKSEL01 CLKSEL00 R/W — — — — — — R/W R/W POR — — — — — — 0 0 1 0 Bit 7~2 unimplemented, read as "0" Bit 1~0 CLKSEL01~CLKSEL00: Prescaler 0 clock source selection 00: fSYS 01: fSYS/4 1x: fSUB PSCR1 Register Rev. 1.40 Bit 7 6 5 4 3 2 Name — — — — — — R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 unimplemented, read as "0" Bit 1~0 CLKSEL11~CLKSEL10: Prescaler 1 clock source selection 00: fSYS 01: fSYS/4 1x: fSUB 223 CLKSEL11 CLKSEL10 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TB0C Register Bit 7 6 5 4 3 2 1 0 Name TB0ON — — — — TB02 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB0ON: Time Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0 TB02~TB00: Time Base 0 time-out period selection 000: 28/fPSC0 001: 29/fPSC0 010: 210/fPSC0 011: 211/fPSC0 100: 212/fPSC0 101: 213/fPSC0 110: 214/fPSC0 111: 215/fPSC0 TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON — — — — TB12 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB1ON: Time Base 1 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0 TB12~TB10: Time Base 1 time-out period selection 000: 28/fPSC1 001: 29/fPSC1 010: 210/fPSC1 011: 211/fPSC1 100: 212/fPSC1 101: 213/fPSC1 110: 214/fPSC1 111: 215/fPSC1 Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface, an I2C slave address match or I2C bus time-out occurrence. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, the Serial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and any of the above described situations occurs, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.40 224 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. EEPROM Interrupt The EEPROM Write Interrupt is contained within the Multi-function Interrupt. An EEPROM Write Interrupt request will take place when the EEPROM Write Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Write Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector will take place. When the EEPROM Write Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the Multi-function interrupt request flag will be automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupt The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request flags and two enable control bits. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However, only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.40 225 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.40 226 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Application Circuits KEY1 A/D Analog Signals SPI/I�C Co��uni�ation Devi�e RX KEYx 3�7�8Hz Syste� C�ystal I/O RS_DIR XT1 TX XT� RS488 T�ans�eive� OSC1 I/O OSC� VDD TM VDD 0.1uF 10uF VSS TM I/O PWM / Captu�e Buzze� Cont�ol Devi�e BS66F3x0 Rev. 1.40 227 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.40 228 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry Bit from where it can be examined and the necessary serial Bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual Bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data Bits. Bit Operations The ability to provide single Bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port Bit programming where individual Bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-Bit output port, manipulate the input data to ensure that other Bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these Bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.40 229 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract immediate data from ACC with Carry Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,x SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.40 230 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table (specific page) to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT" instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the "CLR WDT" instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.40 231 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic LADD A,[m] LADDM A,[m] LADC A,[m] LADCM A,[m] LSUB A,[m] LSUBM A,[m] LSBC A,[m] LSBCM A,[m] LDAA [m] Logic Operation LAND A,[m] LOR A,[m] LXOR A,[m] LANDM A,[m] LORM A,[m] LXORM A,[m] LCPL [m] LCPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.40 232 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None 3Note 3Note 3Note None None None 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Read table to TBLH and Data Memory LTABRDL [m] Read table (last page) to TBLH and Data Memory LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and LITABRDL [m] Data Memory Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.40 233 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.40 Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z 234 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CALL addr Description Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) CPLA [m] Description Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) Rev. 1.40 Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C 235 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z Operation Affected flag(s) Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z HALT Description Operation Operation Affected flag(s) Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None JMP addr Description Rev. 1.40 236 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z Operation Affected flag(s) OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) Rev. 1.40 Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None 237 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver RLA [m] Description Operation Affected flag(s) RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) Rev. 1.40 Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C 238 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver RRCA [m] Description Operation Affected flag(s) SBC A,[m] Description Operation Affected flag(s) SBC A, x Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) Rev. 1.40 Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None 239 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SNZ [m] Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) Rev. 1.40 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ 240 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SUB A,x Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) Rev. 1.40 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None 241 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TABRD [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s) ITABRD [m] Description Operation Affected flag(s) ITABRDL [m] Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.40 Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z 242 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) LADCM A,[m] Description Operation Affected flag(s) LADD A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC Operation Affected flag(s) LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None LANDM A,[m] Description Rev. 1.40 243 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LCPL [m] Description Operation Affected flag(s) LCPLA [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z LDAA [m] Description Operation Operation Affected flag(s) Rev. 1.40 244 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z Operation Affected flag(s) LORM A,[m] Description Operation Affected flag(s) LRL [m] Description Operation Affected flag(s) LRLA [m] Description Operation Affected flag(s) LRLC [m] Description Operation Affected flag(s) LRLCA [m] Description Operation Affected flag(s) Rev. 1.40 Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C 245 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LRR [m] Description Operation Affected flag(s) LRRA [m] Description Operation Affected flag(s) LRRC [m] Description Operation Affected flag(s) LRRCA [m] Description Operation Affected flag(s) LSBC A,[m] Description Operation Affected flag(s) LSBCM A,[m] Description Operation Affected flag(s) Rev. 1.40 Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ 246 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSDZA [m] Description Operation Operation Affected flag(s) LSIZA [m] Description Operation Affected flag(s) LSNZ [m].i Description Operation Affected flag(s) Rev. 1.40 Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None 247 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSNZ [m] Description Operation Affected flag(s) LSUB A,[m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSUBM A,[m] Description Operation Affected flag(s) LSZ [m] Description Operation Affected flag(s) LSZA [m] Description Operation Affected flag(s) Rev. 1.40 Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None 248 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSZ [m].i Description Operation Affected flag(s) LTABRD [m] Description Operation Affected flag(s) LTABRDL [m] Description Operation Affected flag(s) LITABRD [m] Description Operation Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRDL [m] Description Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None Operation Affected flag(s) LXOR A,[m] Description Operation Affected flag(s) LXORM A,[m] Description Operation Affected flag(s) Rev. 1.40 Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z 249 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.40 250 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — 0.020 C 0.012 — C’ — 0.705 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° ― 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 10.300 BSC — B — 7.500 BSC — C 0.31 — 0.51 C’ — 17.900 BSC — 2.65 D — — E — 1.270 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° ― 8° 251 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.390 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.0098 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 9.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 252 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.032 BSC — F 0.012 0.015 0.018 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.45 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 253 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Rev. 1.40 Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° ― 7° 254 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 64-pin LQFP (7mm×7mm) Outline Dimensions Symbol Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.016 BSC — F 0.005 0.007 0.009 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.40 Dimensions in inch Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.40 BSC — F 0.13 0.18 0.23 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 255 December 15, 2016 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 256 December 15, 2016