Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 LMK00804B Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer 1 Features • 1 • • • • • 3 Description Four LVCMOS/LVTTL Outputs with 7 Ω Output Impedance – Additive Jitter: 0.04 ps RMS (typ) @ 125 MHz – Noise Floor: –166 dBc/Hz (typ) @ 125 MHz – Output Frequency: 350 MHz (max) – Output Skew: 35 ps (max) – Part-to-Part Skew: 700 ps (max) Two Selectable Inputs – CLK, nCLK Pair Accepts LVPECL, LVDS, HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL – LVCMOS_CLK Accepts LVCMOS/LVTTL Synchronous Clock Enable Core/Output Power Supplies: – 3.3 V/3.3 V – 3.3 V/2.5 V – 3.3 V/1.8 V – 3.3 V/1.5 V Package: 16-Lead TSSOP Industrial Temperature Range: –40ºC to +85ºC 2 Applications • • • • • • The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or highimpedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability. See also Device Comparison Table for descriptions of CDCLVC1310 and LMK00725 parts. Device Information PART NUMBER PACKAGE LMK00804B BODY SIZE (NOM) TSSOP (16) 5.00 mm × 4.40 mm 1. For all available packages, see the orderable addendum at the end of the datasheet. Wireless and Wired Infrastructure Networking and Data Communications Servers and Computing Medical Imaging Portable Test and Measurement High-End A/V Additive Jitter vs VDDO Supply and Temperature 4 Simplified Schematic 0.10 LVCMOS RPD _CLK RPD CLK RPU/ nCLK RPD CLK_SEL 0.09 D Q 0 Q0 1 Q1 RPU Q2 RPU = Pullup RPD = Pulldown (1) ±40C 25°C 85°C fCLK = 125 MHz Input Slew Rate = 3 V/ns 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 1.5 Q3 OE Additive Jitter (ps RMS) CLK_EN RPU 1.8 2.5 VDDO Supply (V) 3.3 C002 RPU RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown. See Figure 10 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 9 1 1 1 1 3 3 4 Pin Characteristics .................................................... 4 Absolute Maximum Ratings ...................................... 4 Handling Ratings....................................................... 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Power Supply Characteristics ................................... 5 LVCMOS / LVTTL DC Characteristics ...................... 5 Differential Input DC Characteristics......................... 6 Electrical Characteristics (VDDO = 3.3 V ± 5%)....... 6 Electrical Characteristics (VDDO = 2.5 V ± 5%)..... 7 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V) 8 Electrical Characteristics (VDDO = 1.5 V ± 5%)..... 9 Typical Characteristics .......................................... 10 Parameter Measurement Information ................ 11 Detailed Description ............................................ 12 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 13 13 10 Applications and Implementation...................... 14 10.1 10.2 10.3 10.4 10.5 10.6 Application Information.......................................... Output Clock Interface Circuit ............................... Input Detail ............................................................ Input Clock Interface Circuits ................................ Typical Applications .............................................. Do's and Don'ts ..................................................... 14 14 14 15 18 21 11 Power Supply Recommendations ..................... 23 11.1 Power Supply Considerations............................... 23 12 Layout................................................................... 24 12.1 Layout Guidelines ................................................. 24 12.2 Layout Example .................................................... 25 13 Device and Documentation Support ................. 26 13.1 13.2 13.3 13.4 Device Support...................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 14 Mechanical, Packaging, and Orderable Information ........................................................... 26 Changes from Original (June 2014) to Revision A Page • Added Device Comparison Table .......................................................................................................................................... 3 • Changed Human Body Model (HBM) value from 2000 to 1000 ............................................................................................ 4 • Changed Charged Device Model (CDM) value from 750 to 250 .......................................................................................... 4 2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 5 Device Comparison Table PART NUMBER DESCRIPTION CDCLVC1310 10 outputs LVCMOS fanout buffer with Diff, Single-Ended, or Crystal Input LMK00725 5 output LVPECL fanout buffer with Differential or Single-Ended Input 6 Pin Configuration and Functions 16 Pin PW Package Top View GND 1 16 Q0 OE 2 15 VDDO VDD 3 14 Q1 CLK_EN 4 13 GND CLK 5 12 Q2 nCLK 6 11 VDDO CLK_SEL 7 10 Q3 LVCMOS_CLK 8 9 GND Pin Functions TERMINAL NAME GND NUMBER TYPE (1) DESCRIPTION 1, 9, 13 G Power supply ground OE 2 I, RPU VDD 3 P CLK_EN 4 I, RPU 0 = Outputs are forced to logic low state 1 = Outputs are enabled with LVCMOS/LVTT levels CLK 5 I, RPD Non-inverting differential clock input 0. nCLK 6 I, RPD/RPU CLK_SEL 7 I, RPU 0 = Select LVCMOS_CLK 1 = Select CLK, nCLK LVCMOS_CLK 8 I, RPD Single-ended clock input. Accepts LVCMOS/LVTTL levels. Q3, Q2, Q1, Q0 10, 12, 14, 16 O Single-ended clock outputs with LVCMOS/LVTTL levels, 7Ω output impedance 11, 15 P Output supply terminals Output enable input. 0 = Outputs in Hi-Z state 1 = Outputs in active state Power supply terminal Synchronous clock enable input. Inverting differential clock input 0. Internally biased to VDD/2 when left floating Clock select input. VDDO (1) G = Ground, I = Input, O = Output, P = Power, RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 3 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 7 Specifications 7.1 Pin Characteristics MIN TYP MAX UNIT CIN Input Capacitance 1 pF RPU Input Pullup Resistance 51 kΩ RPD Input Pulldown Resistance 51 kΩ CPD Power Dissipation Capacitance (per output) 2 pF ROUT Output impedance 7 Ω 7.2 Absolute Maximum Ratings (1) (2) Over operating free-air temperature range (unless otherwise noted) MAX UNIT VDD Core Supply Voltage –0.3 MIN 3.6 V VDDO Output Supply Voltage –0.3 3.6 V VIN Input Voltage Range –0.3 VDD +0.3 V TJ Junction Temperature 150 °C (1) (2) TYP Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. 7.3 Handling Ratings MIN Tstg Storage temperature range V(ESD) (1) (2) (3) Electrostatic discharge (1) –65 MAX UNIT 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (2) 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3) 250 V Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.4 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) VDD VDDO Core Supply Voltage Output Supply Voltage TA Ambient Temperature TJ Junction Temperature 4 MIN TYP MAX UNIT 3.135 3.3 3.465 V 3.135 3.3 3.465 2.375 2.5 2.625 1.65 1.8 1.95 1.425 1.5 1.575 -40 Submit Documentation Feedback V 85 °C 125 °C Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 7.5 Thermal Information Over operating free-air temperature range (unless otherwise noted) THERMAL METRIC (1) R θJA (1) MIN TYP Package Thermal Impedance, Junction to Air (0 LFPM) MAX UNIT 116 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.6 Power Supply Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT IDD Power Supply Current through VDD 21 mA IDDO Power Supply Current through VDDO 5 mA 7.7 LVCMOS / LVTTL DC Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CLK_EN, VIH Input High Voltage CLK_SEL, OE LVCMOS_CLK CLK_EN, VIL Input Low Voltage CLK_SEL, OE LVCMOS_CLK CLK_EN, IIH Input High Current CLK_SEL, OE LVCMOS_CLK CLK_EN, IIL Input Low Current CLK_SEL, OE LVCMOS_CLK VOH Output High Voltage (1) Output Low Voltage (1) Output Hi-Z Current Low IOZH Output Hi-Z Current High (1) MAX UNIT 2 VDD + 0.3 V 2 VDD + 0.3 V –0.3 0.8 –0.3 1.3 5 VDD = 3.465 V, VIN = 3.465 V 150 V µA VDD = 3.465 V, VIN = 0 V –150 VDD = 3.465 V, VIN = 0 V –5 VDDO = 3.3 V ± 5% 2.6 VDDO = 2.5 V ± 5% 1.8 VDDO = 1.8 V ± 0.15 V 1.5 µA V VDDO – 0.3 VDDO = 3.3 V ± 5% 0.5 VDDO = 2.5 V ± 5% 0.5 VDDO = 1.8 V ± 0.15 V 0.4 VDDO = 1.5 V ± 5% IOZL TYP VDD = 3.465 V, VIN = 3.465 V VDDO = 1.5 V ± 5% VOL MIN V 0.35 –5 5 µA Outputs terminated with 50 Ω to VDDO/2. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 5 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 7.8 Differential Input DC Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER VID Differential Input Voltage Swing, (VIH-VIL) (1) VICM Input Common Mode Voltage (1) (2) IIH Input High Current IIL (1) (2) (3) Input Low Current TEST CONDITIONS MIN TYP MAX 0.15 1.3 V 0.5 VDD – 0.85 V nCLK VDD = 3.465 V, VIN = 3.465 V 150 CLK VDD = 3.465 V, VIN = 3.465 V 150 nCLK VDD = 3.465 V , VIN = 0 V CLK VDD = 3.465 V, VIN = 0 V (3) (3) UNIT µA -150 µA -5 VIL should not be less than -0.3 V. Input common mode voltage is defined as VIH. For IIH and IIL measurements on CLK or nCLK, one must comply with VID and VICM specifications by using the appropriate bias on nCLK or CLK. 7.9 Electrical Characteristics (VDDO = 3.3 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER tPDLH Propagation Delay, Low to High LVCMOS_CLK CLK/nCLK (5) (3) tSK(O) Output Skew (2) (6) (7) tSK(PP) Part-to-Part Skew (3) (7) (8) tR/tF Output Rise/Fall Time JADD (1) (2) (3) (4) (5) (6) (7) (8) (9) 6 TEST CONDITIONS MIN TYP MAX UNIT 350 MHz 1.1 2.1 ns 0.95 2.2 ns 35 ps 700 ps 700 ps Maximum Output Frequency (1) (2) fOUT (4) , 0°C to 70°C –40°C to 85°C Measured on rising edge (3) Additive Jitter (9) 20% to 80% f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band 50 0.04 ps RMS There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations. These AC parameters are specified by characterization. Not tested in production. These AC parameters are specified by design. Not tested in production Measured from the VDD/2 of the input to the VDDO/2 of the output. Measured from the differential input crossing point to VDDO/2 of the output. Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. Parameter is defined in accordance with JEDEC Standard 65. Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. Buffer Additive Jitter: JADD = SQRT(JSYSTEM 2 - JSOURCE2), where JSYSTEM is the RMS jitter of the system output (source+buffer) and JSOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 Electrical Characteristics (VDDO = 3.3 V ± 5%) (continued) Over recommended operating free-air temperature range (unless otherwise noted), VDD = VDDO = 3.3V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f = 125 MHz, Input slew rate ≥ 3 V/ns PNFLOOR Phase Noise Floor (10) 10 kHz offset -155 100 kHz offset -162 1 MHz offset -166 10 MHz offset -166 20 MHz offset dBc/Hz -166 REF = CLK/nCLK 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% ODC Output Duty Cycle (11) (12) tEN Output Enable Time 5 ns tDIS Output Disable Time 5 ns (10) Buffer Phase Noise Floor: PNFLOOR (dBc/Hz) = 10 x log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)], where PNSYSTEM is the phase noise floor of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (11) These AC parameters are specified by design. Not tested in production (12) 50% Input duty cycle 7.10 Electrical Characteristics (VDDO = 2.5 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER fOUT Maximum Output Frequency (1) tPDLH Propagation Delay, Low to High (3) tSK(O) Output Skew (2) (6) (7) tSK(PP) Part-to-Part Skew (3) (7) (8) tR/tF Output Rise/Fall Time (3) TEST CONDITIONS LVCMOS_CLK (4), CLK/nCLK (5) (9) JADD Additive Jitter ODC Output Duty Cycle (3) (10) MIN TYP MAX UNIT 350 MHz 1.1 2.1 ns 0.95 2.2 (2) 0°C to 70°C –40°C to 85°C Measured on rising edge 20% to 80% 50 f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band 35 ps 700 ps 700 ps 0.04 ps RMS REF = CLK/nCLK 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% tEN Output Enable Time 5 ns tDIS Output Disable Time 5 ns (1) (2) (3) (4) (5) (6) (7) (8) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations. These AC parameters are specified by characterization. Not tested in production. These AC parameters are specified by design. Not tested in production. Measured from the VDD/2 of the input to the VDDO/2 of the output. Measured from the differential input crossing point to VDDO/2 of the output. Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. Parameter is defined in accordance with JEDEC Standard 65. Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (9) Buffer Additive Jitter: JADD = SQRT(JSYSTEM2 - JSOURCE2), where JSYSTEM is the RMS jitter of the system output (source+buffer) and JSOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (10) 50% Input Duty Cycle Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 7 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 7.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 0.15 V. All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER fOUT tPDLH Propagation Delay, LVCMOS_CLK CLK/nCLK (5) Low to High (3) tSK(O) Output Skew (2) (6) (7) tSK(PP) Part-to-Part Skew (3) (7) (8) tR/tF TEST CONDITIONS MIN TYP MAX UNIT 350 MHz 1.1 2.2 ns 0.95 2.3 ns 35 ps 700 ps 700 ps Maximum Output Frequency (1) (2) Output Rise/Fall Time (4) , 0°C to 70°C –40°C to 85°C Measured on rising edge (3) 20% to 80% 100 f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band JADD Additive Jitter (9) ODC Output Duty Cycle (3) (10) tEN Output Enable Time 5 ns tDIS Output Disable Time 5 ns 0.04 ps RMS REF = CLK/nCLK 45% 55% REF = LVCMOS_CLK, f ≤ 300 MHz 45% 55% (1) (2) (3) (4) (5) (6) (7) (8) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations. These AC parameters are specified by characterization. Not tested in production. These AC parameters are specified by design. Not tested in production. Measured from the VDD/2 of the input to the VDDO/2 of the output. Measured from the differential input crossing point to VDDO/2 of the output. Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. Parameter is defined in accordance with JEDEC Standard 65. Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (9) Buffer Additive Jitter: JADD = SQRT(JSYSTEM2 - JSOURCE 2), where JSYSTEM is the RMS jitter of the system output (source+buffer) and JSOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (10) 50% Input Duty Cycle 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 7.12 Electrical Characteristics (VDDO = 1.5 V ± 5%) Over recommended operating free-air temperature range (unless otherwise noted), VDD = 3.3V ± 5%, VDDO = 1.5V ± 5%, All AC parameters measured at ≤ 350 MHz unless otherwise noted. PARAMETER fOUT tPDLH Propagation Delay, LVCMOS_CLK CLK/nCLK (5) Low to High (3) tSK(O) Output Skew (2) (6) (7) tSK(PP) Part-to-Part Skew (2) (7) (8) tR/tF TEST CONDITIONS MIN TYP MAX UNIT 350 MHz 1.1 2.2 ns 0.95 2.3 ns 35 ps 1 ns 900 ps Maximum Output Frequency (1) (2) Output Rise/Fall Time (4) , 0°C to 70°C –40°C to 85°C Measured on rising edge (3) 20% to 80% 100 f=125 MHz, Input slew rate ≥ 3 V/ns, 12 kHz to 20 MHz integration band JADD Additive Jitter (9) ODC Output Duty Cycle (3) (10) tEN Output Enable Time 5 ns tDIS Output Disable Time 5 ns 0.04 ps RMS f ≤ 166 MHz 45% 55% f > 166 MHz 42% 58% (1) (2) (3) (4) (5) (6) (7) (8) There is no minimum input / output frequency provided the input slew rate is sufficiently fast. Refer to Input Slew Rate Considerations. These AC parameters are specified by characterization. Not tested in production. These AC parameters are specified by design. Not tested in production. Measured from the VDD/2 of the input to the VDDO/2 of the output. Measured from the differential input crossing point to VDDO/2 of the output. Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output. Parameter is defined in accordance with JEDEC Standard 65. Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, operating at the same supply voltage, same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device. (9) Buffer Additive Jitter: JADD = SQRT(JSYSTEM2 - J SOURCE2), where JSYSTEM is the RMS jitter of the system output (source+buffer) and JSOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality ultra-low-noise oscillators. Please refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details. (10) 50% Input Duty Cycle Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 9 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 7.13 Typical Characteristics Unless otherwise noted: VDD = 3.3 V, VDDO = 3.3 V, TA = 25°C 0.30 0.09 Additive Jitter (ps RMS) 0.25 Additive Jitter (ps RMS) 0.10 100 MHz 125 MHz 250 MHz 350 MHz 0.20 0.15 0.10 0.05 ±40C 25°C 85°C fCLK = 125 MHz Input Slew Rate = 3 V/ns 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 0.00 0 1 2 3 4 5 Input Slew Rate (V/ns) 6 ±152 ±154 ±156 ±158 ±160 ±162 ±164 ±166 ±168 0 1 2 3 4 5 Input Slew Rate (V/ns) 10 ±158 ±159 3.3 C002 ±40C 25°C 85°C fCLK = 125 MHz Input Slew Rate = 3 V/ns ±160 ±161 ±162 ±163 ±164 ±165 ±166 ±167 ±168 1.5 6 1.8 2.5 VDDO Supply (V) C003 Figure 3. Phase Noise Floor vs Input Slew Rate 2.5 Figure 2. Additive Jitter vs VDDO Supply and Temperature 100 MHz 125 MHz 250 MHz 350 MHz ±150 1.8 VDDO Supply (V) Phase Noise @ 10 MHz Offset (dBc/Hz) Phase Noise @ 10 MHz Offset (dBc/Hz) Figure 1. Additive Jitter vs Input Slew Rate ±148 1.5 C001 3.3 C004 Figure 4. Phase Noise Floor vs VDDO Supply and Temperature Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 8 Parameter Measurement Information VCC VIH = VICM nCLK VID = |VIH ± VIL| CLK VIL VCM GND NOTE: VCM = VICM - VID/2 = (V IH + VIL)/2 Figure 5. Differential Input Level space VOH 80% VOUT 20% VOL Q tR tF Figure 6. Output Voltage, and Rise and Fall Times space LVCMOS Input LVCMOS_CLK nCLK CLK Differential Input tPD LVCMOS Outputx Qx tSK LVCMOS Outputy Qy Figure 7. Output Skew and Propagation Delay Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 11 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 9 Detailed Description 9.1 Overview The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability. 9.2 Functional Block Diagram CLK_EN RPU LVCMOS RPD _CLK RPD CLK RPU/ nCLK RPD CLK_SEL D Q 0 Q0 1 Q1 RPU Q2 RPU = Pullup RPD = Pulldown Q3 OE 12 RPU Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 9.3 Feature Description 9.3.1 Clock Enable Timing After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 8. In the enabled mode, the output states are a function of the CLK/nCLK or LVCMOS_CLK inputs as described in Clock Input Function. LVCMOS_CLK nCLK CLK Disabled CLK_EN Enabled Qx Figure 8. Clock Enable Timing Diagram 9.4 Device Functional Modes The device can provide fan-out and level translation from differential or single-ended input to LVCMOS/LVTTL output, where the output VOH and VOL levels are determined by the VDDO output supply voltage and output load condition. Refer to the Clock Input Function. 9.4.1 Clock Input Function Table 1. INPUTS OUTPUTS INPUT to OUTPUT MODE POLARITY CLK (or LVCMOS_CLK) nCLK Qx 0 1 LOW Differential (or SingleEnded) to Single-Ended Non-inverting 1 0 HIGH Differential (or SingleEnded) to Single-Ended Non-inverting 0 Floating or Biased LOW Single-Ended to SingleEnded Non-inverting 1 Floating or Biased HIGH Single-Ended to SingleEnded Non-inverting Biased 0 HIGH Single-Ended to SingleEnded Inverting Biased 1 LOW Single-Ended to SingleEnded Inverting Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 13 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 10 Applications and Implementation 10.1 Application Information Refer to the following sections for output clock and input clock interface circuits. 10.2 Output Clock Interface Circuit VDDO RS= 43 LVCMOS Input Zo = 50 LMK00804 Parasitic Input Capacitance Figure 9. LVCMOS Output Configuration 10.3 Input Detail LMK00804 LVCMOS_CLK 51k CLK 51k VDD 51k nCLK 51k Figure 10. Clock Input Components 14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 10.4 Input Clock Interface Circuits 3.3 V 3.3V LMK00804B Rs LVMOS _CLK Zo = 50Ω Zo Clock generator: Zo + Rs = 50Ω Figure 11. LVCMOS_CLK Input Configuration 3.3V 3.3V 3.3V 3.3V LMK00804B R = 100Ω R = 1kΩ Rs CLK Zo = 50Ω Zo DUT nCLK R = 100Ω R = 1kΩ C = 0.1µF Clock generator: Zo + Rs = 50Ω (1) The Thevenin/split termination values (R = 100 Ω) at the CLK input may be adjusted to provide a small differential offset voltage (50 mV, for example) between the CLK and nCLK inputs to prevent input chatter if the LVCMOS driver is tri-stated. For example, using 105 Ω 1% to 3.3 V rail and 97.6 Ω 1% to GND will provide a –60 mV offset voltage (VnCLK-VCLK) and ensure a logic low state if the LVCMOS driver is tri-stated. Figure 12. Single-Ended/LVCMOS Input DC Configuration 3.3V LMK00804B 3.3V R = 125 3.3V R = 125 Zo = 50 CLK LVPECL output nCLK DUT Zo = 50 R = 84 R = 84 Figure 13. LVPECL Input Configuration Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 15 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com Input Clock Interface Circuits (continued) 3.3V 3.3V LMK00804B Zo = 50 CLK LVPECL output DUT nCLK Zo = 50 R = 50 R = 50 R = 50 Figure 14. Alternative LVPECL Input Configuration 3.3V 3.3V LMK00804B R = 33 Zo = 50 CLK HCSL output nCLK DUT Zo = 50 R = 33 R = 50 R = 50 Figure 15. HCSL Input Configuration 3.3V LMK00804B 3.3V Zo = 50 CLK LVDS output R = 100 DUT nCLK Zo = 50 Figure 16. LVDS Input Configuration 16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 Input Clock Interface Circuits (continued) 3.3V 2.5V R = 120 LMK00804B 3.3V R = 120 Zo = 60 CLK SSTL output DUT nCLK Zo = 60 R = 120 R = 120 Figure 17. SSTL Input Configuration Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 17 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 10.5 Typical Applications 10.5.1 Design Requirements For high-performance devices, limitations of the equipment influence phase-noise measurements. The noise floor of the equipment is often higher than the noise floor of the device. The real noise floor of the device is probably lower. It is important to understand that system-level phase noise measured at the DUT output is influenced by the input source and the measurement equipment. For Figure 18 and Figure 19 system-level phase noise plots, a Rohde & Schwarz SMA100A low-noise signal generator was cascaded with an Agilent 70429A K95 single-ended to differential converter block with ultra-low phase noise and fast edge slew rate (>3 V/ns) to provide a very low-noise clock input source to the LMK00804B. An Agilent E5052 source signal analyzer with ultra-low measurement noise floor was used to measure the phase noise of the input source (SMA100A + 70429A K95) and system output (input source + LMK00804B). The input source phase noise is shown by the light yellow trace, and the system output phase noise is shown by the dark yellow trace. 10.5.2 Detailed Design Procedure The additive phase noise or noise floor of the buffer (PNFLOOR) can be computed as follows: PNFLOOR (dBc/Hz) = 10 x log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)] where • • PNSYSTEM is the phase noise of the system output (source+buffer) PNSOURCE is the phase noise of the input source (1) The additive jitter of the buffer (JADD) can be computed as follows: JADD = SQRT(JSYSTEM2– JSOURCE2) where: • • 18 JSYSTEM is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz JSOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz Submit Documentation Feedback (2) Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 Typical Applications (continued) 10.5.3 Application Curves 10.5.3.1 System-Level Phase Noise and Additive Jitter Measurement Figure 18. 125 MHz Input Phase Noise (57 fs rms, Light Blue), and Output Phase Noise (71 fs rms, Dark Blue), Additive Jitter = 42 fs rms Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 19 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com Typical Applications (continued) Figure 19. 156.25 MHz Input Phase Noise (57 fs rms, Light Blue), and Output Phase Noise (72 fs rms, Dark Blue), Additive Jitter = 44 fs rms 20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 10.6 Do's and Don'ts 10.6.1 Power Considerations The following power consideration refers to the device-consumed power consumption only. The device power consumption is the sum of static power and dynamic power. The dynamic power usage consists of two components: • Power used by the device as it switches states • Power required to charge any output load The output load can be capacitive-only or capacitive and resistive. Use the following formula to calculate the power consumption of the device: PDev = Pstat + Pdyn + PCload Pstat = (IDD × VDD) + (IDDO × VDDO) Pdyn + PCload = (IDDO,dyn + IDDO,Cload) × VDDO (3) (4) where: • • IDDO,dyn = CPD × VDDO × f × n [mA] IDDO,Cload = Cload × VDDO × f × n [mA] (5) Example for power consumption of the LMK00804B: 4 outputs are switching, f = 100 MHz, VDD = VDDO = 3.465 V and assuming Cload = 5 pF per output: PDev = 90 mW + 34 mW = 124 mW Pstat = (21 mA × 3.465 V) + (5 mA × 3.465 V)= 90 mW Pdyn + PCload = (2.8 mA + 6.9 mA) x 3.465 V = 34 mW IDD,dyn = 2 pF × 3.465 V × 100 MHz × 4 = 2.8 mA IDD,Cload = 5 pF × 3.465 V x 100 MHz × 4 = 6.9 mA (6) (7) (8) (9) (10) NOTE For dimensioning the power supply, consider the total power consumption. The total power consumption is the sum of device power consumption and the power consumption of the load. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 21 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com Do's and Don'ts (continued) 10.6.2 Recommendations for Unused Input and Output Pins • CLK_SEL, CLK_EN, and OE: These inputs all have internal pull-up (RPU) according to Table 2 and can be left floating if unused. Table 2 shows the default floating state of these inputs: Table 2. Input Floating Default States INPUT • • • FLOATING STATE SELECTION CLK_SEL CLK/nCLK selected CLK_EN Synchronous outputs enable OE Outputs enabled CLK/nCLK Inputs: See Figure 10 for the internal connections. When using single ended input, take note of the internal pull-up and pull-down to make sure the unused input is properly biased. To interface a singleended input to the CLK/nCLK input, the configuration shown in Figure 12 is recommended. LVCMOS_CLK Input: See Figure 10 for the internal connection. The internal pull-down (RPD) resistor ensures a low state when this input is left floating. Outputs: Any unused output can be left floating with no trace connected. 10.6.3 Input Slew Rate Considerations LMK00804B employs high-speed and low-latency circuit topology, allowing the device to achieve ultra-low additive jitter/phase noise and high-frequency operation. To take advantage of these benefits in the system application, it is optimal for the input signal to have a high slew rate of 3 V/ns or greater. Driving the input with a slower slew rate can degrade the additive jitter and noise floor performance. For this reason, a differential signal input is recommended over single-ended because it typically provides higher slew rate and common-moderejection. Refer to the “Additive Jitter vs. Input Slew Rate” plots in Typical Characteristics. Also, using an input signal with very slow input slew rate, such as less than 0.05 V/ns, has the tendency to cause output switching noise to feed-back to the input stage and cause the output to chatter. This is especially true when driving either input in single-ended fashion with a very slow slew rate, such as a sine-wave input signal. 22 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 11 Power Supply Recommendations 11.1 Power Supply Considerations While there is no strict power supply sequencing requirement, it is generally best practice to sequence the core supply voltage (VDD) before the output supply voltage (VDDO). 11.1.1 Power-Supply Filtering High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter or phase noise is critical to applications. Use of filter capacitors eliminates the low-frequency noise from power supply, where the bypass capacitors provide the very low-impedance path for high-frequency noise and guard the power-supply system against induced fluctuations. The bypass capacitors also provide instantaneous current surges as required by the device, and should have low ESR. To use the bypass capacitors properly, place them very close to the power supply terminals and lay out traces with short loops to minimize inductance. TI recommends to adding as many highfrequency (for example, 0.1 µF) bypass capacitors as there are supply terminals in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply to isolate the high-frequency switching noises generated by the clock driver, preventing them from leaking into the board supply. Choosing an appropriate ferrite bead with very low DC resistance is important, because it is imperative to provide adequate isolation between the board supply and the chip supply. It is also imperative to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation. Board Supply Vcc Chip Supply Ferrite Bead C 10 µF C 1 µF 0.1 µF (3 places, one per Vcc pin) Figure 20. Power-Supply Decoupling Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 23 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com Power Supply Considerations (continued) 11.1.2 Thermal Management For reliability and performance reasons, limit the die temperature to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125°C. Assuming the conditions in the Power Considerations section and operating at an ambient temperature of 70°C with all outputs loaded, here is an estimate of the LMK00804B junction temperature: TJ= TA+ PTotal x θJA= 70 °C + (124 mW x 116 °C/W) = 70 °C + 14.4 °C = 84.4 °C (11) Here are some recommendations for improving heat flow away from the die: • Use multi-layer boards • Specify a higher copper thickness for the board • Increase the number of vias from the top level ground plane under and around the device to internal layers and to the bottom layer with as much copper area flow on each level as possible • Apply air flow • Leave unused outputs floating 12 Layout 12.1 Layout Guidelines 12.1.1 Ground Planes Solid ground planes are recommended as they provide a low-impedance return paths between the device and its bypass capacitors and its clock source and destination devices. Avoid return paths of other system circuitry (for example, high-speed/digital logic, switching power supplies, and so forth) from passing through the local ground of the device to minimize noise coupling, which could induce added jitter and spurious noise. 12.1.2 Power Supply Pins Follow the power supply schematic and layout example described in Power-Supply Filtering. 12.1.3 Differential Input Termination • Place input termination or biasing resistors as close as possible to the CLK/nCLK pins. • Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities. Intra-pair skew should be also be minimized on the differential input traces. • If not used, CLK/nCLK inputs may be left floating. 12.1.4 LVCMOS Input Termination • When the LVCMOS_CLK input is driven from a LVCMOS driver that is series terminated to match the characteristic impedance of the trace, then input termination is not necessary; otherwise, place the input termination resistor as close as possible to the LVCMOS_CLK input. • Avoid or minimize vias in the 50 Ω input trace to minimize impedance discontinuities. • If not used, LVCMOS_CLK input may be left floating. 12.1.5 Output Termination • Place 43 Ω series termination resistors as close as possible to the Qx outputs at the launch of the 50 Ω traces. • Avoid or minimize vias in the 50 Ω input traces to minimize impedance discontinuities. • If not used, any Qx output should be left floating and not routed. 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B LMK00804B www.ti.com SNAS642A – JUNE 2014 – REVISED JULY 2014 12.2 Layout Example Please refer to the LMK00804BEVM for a layout example. A sample PCB layer is shown below. Figure 21. Sample PCB Layout, Layer 1 (Top View) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B 25 LMK00804B SNAS642A – JUNE 2014 – REVISED JULY 2014 www.ti.com 13 Device and Documentation Support 13.1 Device Support For device and documentation support, please direct your inquiries to the TI E2E Support Forums for Clocking Products. 13.2 Trademarks All trademarks are the property of their respective owners. 13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LMK00804B PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMK00804BPW ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00804B LMK00804BPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 K00804B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMK00804BPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK00804BPWR TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated