M MCP41XXX/42XXX Single/Dual Digital Potentiometer with SPI™ Interface Features Description • 256 taps for each potentiometer • Potentiometer values for 10 kΩ, 50 kΩ and 100 kΩ • Single and dual versions • SPI™ serial interface (mode 0,0 and 1,1) • ±1 LSB max INL & DNL • Low power CMOS technology • 1 µA maximum supply current in static operation • Multiple devices can be daisy-chained together (MCP42XXX only) • Shutdown feature open circuits of all resistors for maximum power savings • Hardware shutdown pin available on MCP42XXX only • Single supply operation (2.7V - 5.5V) • Industrial temperature range: -40°C to +85°C • Extended temperature range: -40°C to +125°C The MCP41XXX and MCP42XXX devices are 256position, digital potentiometers available in 10 kΩ, 50 kΩ and 100 kΩ resistance versions. The MCP41XXX is a single-channel device and is offered in an 8-pin PDIP or SOIC package. The MCP42XXX contains two independent channels in a 14-pin PDIP, SOIC or TSSOP package. The wiper position of the MCP41XXX/42XXX varies linearly and is controlled via an industry-standard SPI interface. The devices consume <1 µA during static operation. A software shutdown feature is provided that disconnects the “A” terminal from the resistor stack and simultaneously connects the wiper to the “B” terminal. In addition, the dual MCP42XXX has a SHDN pin that performs the same function in hardware. During shutdown mode, the contents of the wiper register can be changed and the potentiometer returns from shutdown to the new value. The wiper is reset to the mid-scale position (80h) upon power-up. The RS (reset) pin implements a hardware reset and also returns the wiper to mid-scale. The MCP42XXX SPI interface includes both the SI and SO pins, allowing daisy-chaining of multiple devices. Channel-to-channel resistance matching on the MCP42XXX varies by less than 1%. These devices operate from a single 2.7 - 5.5V supply and are specified over the extended and industrial temperature ranges. Block Diagram RS SHDN VDD VSS Wiper Register Control Logic SI SCK Wiper Resistor Register Array 1* 16-Bit Shift Register PB1 PA1 PW1 S0 *Potentiometer P1 is only available on the dual MCP42XXX version. Package Types PDIP/SOIC CS SCK SI VSS 2 3 4 8 7 6 5 VDD PB0 PW0 PA0 PDIP/SOIC/TSSOP 1 14 2 13 3 4 5 6 7 MCP42XXX CS SCK SI VSS PB1 PW1 PA1 2003 Microchip Technology Inc. 1 MCP41XXX CS PB0 Resistor Array 0 PA0 PW0 12 11 10 9 8 VDD SO SHDN RS PB0 PW0 PA0 DS11195C-page 1 MCP41XXX/42XXX 1.0 ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS: 10 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions Rheostat Mode Nominal Resistance Rheostat Differential Non Linearity Rheostat Integral Non Linearity TA = +25°C (Note 1) R 8 10 12 kΩ R-DNL -1 ±1/4 +1 LSB Note 2 Note 2 R-INL -1 ±1/4 +1 LSB Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 52 100 Ω VDD = 5.5V, IW = 1 mA, code 00h RW — 73 125 Ω VDD = 2.7V, IW = 1 mA, code 00h IW -1 — +1 mA ∆R/R — 0.2 1 % Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3 ∆VW/∆T — 1 — Wiper Current Nominal Resistance Match MCP42010 only, P0 to P1; TA = +25°C Potentiometer Divider Voltage Divider Tempco Full Scale Error Zero Scale Error ppm/°C Code 80h VWFSE -2 -0.7 0 LSB Code FFh, VDD = 5V, see Figure 2-25 VWFSE -2 -0.7 0 LSB Code FFh, VDD = 3V, see Figure 2-25 VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 5V, see Figure 2-25 VWZSE 0 +0.7 +2 LSB Code 00h, VDD = 3V, see Figure 2-25 Resistor Terminals Voltage Range VA,B,W Capacitance (CA or CB) Capacitance CW 0 — VDD — 15 — pF f = 1 MHz, Code = 80h, see Figure 2-30 — 5.6 — pF f = 1 MHz, Code = 80h, see Figure 2-30 Note 4 Dynamic Characteristics (All dynamic characteristics use VDD = 5V) Bandwidth -3dB Settling Time Resistor Noise Voltage Crosstalk BW — 1 — MHz tS — 2 — µS eNWB — 9 — nV/√Hz CT — -95 — dB VB = 0V, Measured at Code 80h, Output Load = 30 PF VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30 pF VA = Open, Code 80h, f =1 kHz VA = VDD, VB = 0V (Note 5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V VHYS — 0.05VDD — Hysteresis of Schmitt Trigger Inputs Low-Level Output Voltage VOL — — 0.40 V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400 µA, VDD = 5V ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1 MHz Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10 MHz, SO = Open, Code FFh (Note 6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Input Leakage Current Pin Capacitance (All inputs/outputs) IOL = 2.1 mA, VDD = 5V Power Requirements Note 1: 2: 3: 4: 5: 6: VAB = VDD, no connection on wiper. Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50 µA for VDD = 3V and IW = 400 µA for VDD = 5V for 10 kΩ version. See Figure 2-26 for test circuit. INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit. Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure 2-25. Measured at VW pin where the voltage on the adjacent VW pin is swinging full-scale. Supply current is independent of current through the potentiometers. DS11195C-page 2 2003 Microchip Technology Inc. MCP41XXX/42XXX DC CHARACTERISTICS: 50 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max Units Conditions R 35 50 65 kΩ R-DNL -1 ±1/4 +1 LSB Note 2 Note 2 Rheostat Mode Nominal Resistance Rheostat Differential Non-Linearity Rheostat Integral Non-Linearity TA = +25°C (Note 1) R-INL -1 ±1/4 +1 LSB Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 125 175 Ω VDD = 5.5V, IW = 1 mA, code 00h RW — 175 250 Ω VDD = 2.7V, IW = 1 mA, code 00h IW -1 — +1 mA ∆R/R — 0.2 1 % Wiper Current Nominal Resistance Match MCP42050 only, P0 to P1;TA = +25°C Potentiometer Divider Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3 Voltage Divider Tempco ∆VW/∆T — 1 — Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure 2-25 VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure 2-25 VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure 2-25 VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure 2-25 Zero-Scale Error ppm/°C Code 80h Resistor Terminals Voltage Range VA,B,W Capacitance (CA or CB) Capacitance CW 0 — VDD — 11 — pF f =1 MHz, Code = 80h, see Figure 2-30 — 5.6 — pF f =1 MHz, Code = 80h, see Figure 2-30 Note 4 Dynamic Characteristics (All dynamic characteristics use VDD = 5V) Bandwidth -3dB Settling Time Resistor Noise Voltage Crosstalk BW — 280 — MHz tS — 8 — µS eNWB — 20 — nV/√Hz CT — -95 — dB VB = 0V, Measured at Code 80h, Output Load = 30 PF VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30 pF VA = Open, Code 80h, f =1 kHz VA = VDD, VB = 0V (Note 5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation. Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V VHYS — 0.05VDD — Hysteresis of Schmitt Trigger Inputs Low-Level Output Voltage VOL — — 0.40 V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400 µA, VDD = 5V ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1 MHz Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10 MHz, SO = Open, Code FFh (Note 6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Input Leakage Current Pin Capacitance (All inputs/outputs) IOL = 2.1 mA, VDD = 5V Power Requirements Note 1: 2: 3: 4: 5: 6: VAB = VDD, no connection on wiper. Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = VDD/R for +3V or +5V for 50 kΩ version. See Figure 2-26 for test circuit. INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit. Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure 2-25. Measured at VW pin where the voltage on the adjacent VW pin is swinging full scale. Supply current is independent of current through the potentiometers. 2003 Microchip Technology Inc. DS11195C-page 3 MCP41XXX/42XXX DC CHARACTERISTICS: 100 kΩ VERSION Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C (TSSOP devices are only specified at +25°C and +85°C). Typical specifications represent values for VDD = 5V, VSS = 0V, VB = 0V, TA = +25°C. Parameters Sym Min Typ Max R R-DNL Units Conditions 70 100 130 kΩ -1 ±1/4 +1 LSB Note 2 Note 2 Rheostat Mode Nominal Resistance Rheostat Differential Non-Linearity Rheostat Integral Non-Linearity TA = +25°C (Note 1) R-INL -1 ±1/4 +1 LSB Rheostat Tempco ∆RAB/∆T — 800 — ppm/°C Wiper Resistance RW — 125 175 Ω VDD = 5.5V, IW = 1 mA, code 00h RW — 175 250 Ω VDD = 2.7V, IW = 1 mA, code 00h IW -1 — +1 mA ∆R/R — 0.2 1 % Resolution N 8 — — Bits Monotonicity N 8 — — Bits Differential Non-Linearity DNL -1 ±1/4 +1 LSB Note 3 Integral Non-Linearity INL -1 ±1/4 +1 LSB Note 3 Voltage Divider Tempco ∆VW/∆T — 1 — Full-Scale Error VWFSE -1 -0.25 0 LSB Code FFh, VDD = 5V, see Figure 2-25 VWFSE -1 -0.35 0 LSB Code FFh, VDD = 3V, see Figure 2-25 VWZSE 0 +0.25 +1 LSB Code 00h, VDD = 5V, see Figure 2-25 VWZSE 0 +0.35 +1 LSB Code 00h, VDD = 3V, see Figure 2-25 Wiper Current Nominal Resistance Match MCP42010 only, P0 to P1;TA = +25°C Potentiometer Divider Zero-Scale Error ppm/°C Code 80h Resistor Terminals Voltage Range VA,B,W Capacitance (CA or CB) Capacitance CW 0 — VDD — 11 — pF f =1 MHz, Code = 80h, see Figure 2-30 — 5.6 — pF f =1 MHz, Code = 80h, see Figure 2-30 Note 4 Dynamic Characteristics (All dynamic characteristics use VDD = 5V.) Bandwidth -3dB Settling Time Resistor Noise Voltage Crosstalk BW — 145 — MHz tS — 18 — µS eNWB — 29 — nV/√Hz CT — -95 — dB VB = 0V, Measured at Code 80h, Output Load = 30 PF VA = VDD,VB = 0V, ±1% Error Band, Transition from Code 00h to Code 80h, Output Load = 30 pF VA = Open, Code 80h, f =1 kHz VA = VDD, VB = 0V (Note 5) Digital Inputs/Outputs (CS, SCK, SI, SO) See Figure 2-12 for RS and SHDN pin operation. Schmitt Trigger High-Level Input Voltage VIH 0.7VDD — — V Schmitt Trigger Low-Level Input Voltage VIL — — 0.3VDD V VHYS — 0.05VDD — Hysteresis of Schmitt Trigger Inputs Low-Level Output Voltage VOL — — 0.40 V High-Level Output Voltage VOH VDD - 0.5 — — V IOH = -400 µA, VDD = 5V ILI -1 — +1 µA CS = VDD, VIN = VSS or VDD, includes VA SHDN=0 CIN, COUT — 10 — pF VDD = 5.0V, TA = +25°C, fc = 1 MHz Operating Voltage Range VDD 2.7 — 5.5 V Supply Current, Active IDDA — 340 500 µA VDD = 5.5V, CS = VSS, fSCK = 10 MHz, SO = Open, Code FFh (Note 6) Supply Current, Static IDDS — 0.01 1 µA CS, SHDN, RS = VDD = 5.5V, SO = Open (Note 6) Power Supply Sensitivity PSS — 0.0015 0.0035 %/% VDD = 4.5V - 5.5V, VA = 4.5V, Code 80h PSS — 0.0015 0.0035 %/% VDD = 2.7V - 3.3V, VA = 2.7V, Code 80h Input Leakage Current Pin Capacitance (All inputs/outputs) IOL = 2.1 mA, VDD = 5V Power Requirements Note 1: 2: 3: 4: 5: 6: VAB = VDD, no connection on wiper. Rheostat position non-linearity R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from the ideal between successive tap positions. IW = 50 µA for VDD = 3V and IW = 400 µA for VDD = 5V for 10 kΩ version. See Figure 2-26 for test circuit. INL and DNL are measured at VW with the device configured in the voltage divider or potentiometer mode. VA = VDD and VB = 0V. DNL specification limits of ±1 LSB max are specified monotonic operating conditions. See Figure 2-25 for test circuit. Resistor terminals A,B and W have no restrictions on polarity with respect to each other. Full-scale and zero-scale error were measured using Figure 2-25. Measured at VW pin where the voltage on the adjacent VW pin is swinging full-scale. Supply current is independent of current through the potentiometers. DS11195C-page 4 2003 Microchip Technology Inc. MCP41XXX/42XXX Absolute Maximum Ratings † VDD...................................................................................7.0V † Notice: Stresses above those listed under “maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All inputs and outputs w.r.t. VSS ............... -0.6V to VDD +1.0V Storage temperature .....................................-60°C to +150°C Ambient temp. with power applied ................-60°C to +125°C ESD protection on all pins ..................................................≥ 2 kV AC TIMING CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +2.7V to 5.5V, TA = -40°C to +85°C. Parameter Sym Min. Typ. Max. Units Clock Frequency FCLK — — 10 MHz Clock High Time tHI 40 — — ns Clock Low Time Conditions VDD = 5V (Note 1) tLO 40 — — ns tCSSR 40 — — ns Data Input Setup Time tSU 40 — — ns Data Input Hold Time tHD 10 — — ns SCK Fall to SO Valid Propagation Delay tDO — 80 ns SCK Rise to CS Rise Hold Time tCHS — — ns SCK Rise to CS Fall Delay tCS0 10 — — ns CS Rise to CLK Rise Hold tCS1 100 — — ns CS High Time tCSH 40 — — ns Reset Pulse Width tRS 150 — — ns Note 2 tRSCS 150 — — ns Note 2 CS rising to RS or SHDN falling delay time tSE 40 — — ns Note 3 CS low time tCSL 100 — — ns Note 3 tSH 150 — — ns Note 3 CS Fall to First Rising CLK Edge RS Rising to CS Falling Delay Time Shutdown Pulse Width Note 1: 2: 3: 30 CL = 30 pF (Note 2) When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO) and data input setup time (tSU). Max. clock frequency is therefore ~ 5.8 MHz based on SCK rise and fall times of 5 ns, tHI = 40 ns, tDO = 80 ns and tSU = 40 ns. Applies only to the MCP42XXX devices. Applies only when using hardware pins to exit software shutdown mode, MCP42XXX only. 2003 Microchip Technology Inc. DS11195C-page 5 MCP41XXX/42XXX tCSH CS 1/FCLK tCSSR tHI tCSO SCK tCHS tLO tCS1 tSU tHD SI msb in tDO (First 16 bits out are always zeros) SO tS ±1% Error Band VOUT FIGURE 1-1: ±1% Detailed Serial interface Timing. Wiper position is changed to mid-scale (80h) if RS is held low for 150 ns Code 80h is latched on rising edge of RS CS tRSCS tRS RS tS VOUT FIGURE 1-2: ±1% Error Band ±1% Reset Timing. tCSL CS tSE tRS RS tSE tSH SHDN FIGURE 1-3: DS11195C-page 6 Software Shutdown Exit Timing. 2003 Microchip Technology Inc. MCP41XXX/42XXX 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V. 14 VDD = +3V to +5V Nominal Resistance (kΩ) Normalized Resistance (Ω) 1 0.8 0.6 0.4 RWB RWA 0.2 10 8 4 2 0 64 96 128 160 Code (Decimal) 192 224 Potentiometer INL Error (LSB) TA = -40°C to +85°C Refer to Figure 2-25 0 32 64 96 5 FIGURE 2-4: vs. Temperature. Nominal Resistance 10 kΩ 70 60 RAB 50 40 30 RWB Code = 80h 20 10 MCP41050, MCP42050 (50 kΩ potentiometers) 0 -40 -25 -10 128 160 192 224 256 5 TA = -40°C to +85°C VA = 3V 60 50 40 30 20 10 0 -10 0 32 64 96 128 160 192 224 256 FIGURE 2-5: vs. Temperature. 50 65 80 95 110 125 FIGURE 2-3: Potentiometer Mode Tempco vs. Code. Nominal Resistance 50 kΩ 120 RAB 100 80 RWB Code = 80h 60 40 20 MCP41100, MCP42100 (100 kΩ potentiometers) 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Code (Decimal) 2003 Microchip Technology Inc. 35 140 Nominal Resistance (kΩ) Potentiometer Mode TempCo (ppm / °C) Potentiometer INL Error vs. 70 20 Temperature (°C) Code (Decimal) FIGURE 2-2: Code. 20 35 50 65 80 95 110 125 Temperature (°C) FIGURE 2-1: Normalized Wiper to End Terminal Resistance vs. Code. 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 MCP41010, MCP42010 (10 kΩ potentiometers) -40 -25 -10 256 Nominal Resistance (kΩ) 32 RWB Code = 80h 6 0 0 RAB 12 FIGURE 2-6: vs. Temperature. Nominal Resistance 100 kΩ DS11195C-page 7 MCP41XXX/42XXX Refer to Figure 2-27 TA = +85°C TA = +25°C TA = -40°C 0 32 64 FIGURE 2-7: Code. 96 128 160 Code (Decimal) 224 TA = -40°C to +85°C, VA = no connect, RWB measured 2500 2000 1500 1000 500 0 0 32 64 96 280 VDD = 5V 230 130 80 VDD = 3V 30 5 FIGURE 2-10: Temperature. 1000 Active Supply Current vs. A - VDD = 5.5V, Code = AAh B - VDD = 3.3V, Code = AAh C - VDD = 5.5V, Code = FFh D - VDD = 3.3V, Code = FFh 900 800 700 500 400 A C 300 200 100 D 1k 10k 100 10 1 -40 -25 -10 5 20 35 50 65 80 95 11 12 0 5 Temperature (°C) FIGURE 2-9: Temperature. DS11195C-page 8 Static Current vs. FIGURE 2-11: Clock Frequency. RS & SHDN Sink Current (mA) Static Current (nA) 1000 B 600 0 128 160 192 224 256 Rheostat Mode Tempco vs. 20 35 50 65 80 95 110 125 Temperature (°C) Code (Decimal) FIGURE 2-8: Code. FCLK = 3 MHz Code = FFh 180 -40 -25 -10 256 Rheostat INL Error vs. 3000 Rheostat Mode TempCo (ppm / °C) 192 Active Supply Current (µA) 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 Active Supply Current (mA) Rheostat INL Error (LSB) Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V. 100k 1M Clock Frequency (Hz) 10M Active Supply Current vs. 1 VDD = 5.5V 0 -1 -2 -3 -4 -5 -6 -7 0 2 4 6 RS & SHDN Pin Voltage (V) FIGURE 2-12: Reset & Shutdown Pins Current vs. Voltage. 2003 Microchip Technology Inc. MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V. Number of Occurrences 180 160 140 CL = 27 pF MCP41010,MCP42010 Code = 00h, Sample Size = 400 VOUT 120 FFh 100 80 00h 60 40 20 CS 0 47 48 49 50 51 52 53 54 55 56 57 58 59 Wiper Resistance (Ω) FIGURE 2-13: 10 kΩ Device Wiper Resistance Histogram. Number of Occurrences 140 FIGURE 2-16: Full-Scale Settling Time. CL = 27 pF MCP41050, MCP41100, MCP42050, MCP42100 Code = 00h, Sample Size = 796 120 100 Code = 80h VOUT 80 60 40 20 CS 0 115 117 119 121 123 125 127 129 131 133 Wiper Resistance (Ω) FIGURE 2-14: 50 kΩ, 100 kΩ Device Wiper Resistance Histogram. FIGURE 2-17: Time. Digital Feed through vs. 6 CL = 17 pF Code = FFh 0 Code = 80h -6 Code = 40h VOUT Code = 7Fh Code = 80h Gain (dB) -12 Code = 20h -18 Code = 10h -24 Code = 08h -30 Code = 04h -36 Code = 02h -42 CS -48 -54 -60 FIGURE 2-15: One Position Settling Time. 2003 Microchip Technology Inc. Code = 01h CL = 30pF, Refer to Figure 2-29 MCP41010, MCP42010 (10kΩ potentiometers) 100 1k 10k 100k Frequency (Hz) 1M 10M FIGURE 2-18: Gain vs. Frequency for 10 kΩ Potentiometer. DS11195C-page 9 MCP41XXX/42XXX Note: Unless otherwise indicated, curve represents 10 kΩ, 50 kΩ and 100 kΩ devices, VDD = 5V, VSS = 0V, TA = +25°C, VB = 0V. 6 35 Code = 80h -6 Code = 40h -12 Code = 10h -24 Code = 08h -30 Code = 04h -36 Code = 02h -42 100 1k 10k 100k Frequency (Hz) 6 1M 100 kΩ Potentiometer Wiper Resistance (Ω) Code = 20h -18 Code = 10h -24 Code = 08h -30 Code = 04h -36 Code = 02h -42 Code = 01h -48 CL = 30pF, Refer to Figure 2-29 MCP41100, MCP42100 (100kΩ potentiometers) -54 100 1k 100k Frequency (Hz) 10k Frequency (Hz) 100k VDD = 2.7V 500 400 300 200 VDD = 5V 100 0 1 2 3 FIGURE 2-23: Voltage. 279 kHz 10 kΩ -18 -24 50 kΩ CL = 30 pF, Code = 80h Refer to Figure 2-29 1k FIGURE 2-21: DS11195C-page 10 10k 100k Frequency (Hz) Code = 00h Refer to Figure 2-27 -3 dB Bandwidths. 350 300 VDD = 2.7V 250 200 150 VDD = 5V 100 50 0 100 kΩ 1M Wiper Resistance (Ω) 1.06 MHz 145 kHz 5 10 kΩ Wiper Resistance vs. 400 -6 4 Terminal B Voltage (V) 450 -30 10M MCP41010, MCP42010 Iw = 1 mA, Code = 00h, Refer to Figure 2-27 600 1M 0 -12 1M 0 FIGURE 2-20: Gain vs. Frequency for 100kΩ Potentiometer. -36 10k 700 Code = 40h -12 1k FIGURE 2-22: Power Supply Rejection Ratio vs. Frequency. Code = 80h -6 Gain (dB) 0 10M Code = FFh 0 Gain (dB) 50 kΩ Potentiometer 15 5 FIGURE 2-19: Gain vs. Frequency for 50kΩ Potentiometer. -60 20 10 CL = 30pF, Refer to Figure 2-29 MCP41050, MCP42050 (50kΩ potentiometers) -54 -60 25 Code = 01h -48 VDD = 4.5V to 5.5V, Code = 80h, CL = 27 pF, VA = 4V Refer to Figure 2-28 10 kΩ Potentiometer 30 Code = 20h -18 PSRR (dB) Gain (dB) 40 Code = FFh 0 10M 0 1 2 3 4 5 Terminal B Voltage (V) FIGURE 2-24: 50 kΩ & 100 kΩ Wiper Resistance vs. Voltage. 2003 Microchip Technology Inc. MCP41XXX/42XXX 2.1 Parametric Test Circuits A V+ B DUT VA V+ = VDD 1LSB = V+/256 VDD A V+ W B DUT + VMEAS* - W + V MEAS* - *Assume infinite input impedance V+ = VDD ± 10% FIGURE 2-25: Potentiometer Divider NonLinearity Error Test Circuit (DNL, INL). PSRR (dB) = 20LOG ( PSS (%/%) = ∆VDD ∆VMEAS No Connection *Assume infinite input impedance A FIGURE 2-28: Power Supply Sensitivity Test Circuit (PSS, PSRR). IW W B + - VMEAS* DUT A VIN *Assume infinite input impedance Rsw = 0.1V Isw Code = 00h A W B ISW + - +5V W ~ VOUT + - DUT B OFFSET GND FIGURE 2-26: Resistor Position NonLinearity Error Test Circuit (Rheostat operation DNL, INL). DUT ∆VDD ) ∆VMEAS 2.5V DC FIGURE 2-29: Circuit. Gain vs. Frequency Test A 0.1V DUT B +5V VSS = 0 to VDD VIN FIGURE 2-27: Circuit. Wiper Resistance Test ~ + 2.5V DC Offset FIGURE 2-30: 2003 Microchip Technology Inc. VOUT MCP601 Capacitance Test Circuit. DS11195C-page 11 MCP41XXX/42XXX 3.0 PIN DESCRIPTIONS 3.1 PA0, PA1 3.9 Shutdown (SHDN) (MCP42XXX devices only) Potentiometer Wiper Connection. The Shutdown pin has a Schmitt Trigger input. Pulling this pin low will put the device in a power-saving mode where A terminal is opened and the B and W terminals are connected for all potentiometers. This pin should not be toggled low when the CS pin is low. In order to minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown in Figure 2-12. This pin will draw negligible current at logic level ‘0’ and logic level ‘1’. Do not leave this pin floating. 3.4 TABLE 3-1: Potentiometer Terminal A Connection. 3.2 PB0, PB1 Potentiometer Terminal B Connection. 3.3 PW0, PW1 Chip Select (CS) This is the SPI port chip select pin and is used to execute a new command after it has been loaded into the shift register. This pin has a Schmitt Trigger input. 3.5 Serial Clock (SCK) This is the SPI port clock pin and is used to clock-in new register data. Data is clocked into the SI pin on the rising edge of the clock and out the SO pin on the falling edge of the clock. This pin is gated to the CS pin (i.e., the device will not draw any more current if the SCK pin is toggling when the CS pin is high). This pin has a Schmitt Trigger input. 3.6 Serial Data Input (SI) This is the SPI port serial data input pin. The command and data bytes are clocked into the shift register using this pin. This pin is gated to the CS pin (i.e., the device will not draw any more current if the SI pin is toggling when the CS pin is high). This pin has a Schmitt Trigger input. 3.7 Serial Data Output (SO) (MCP42XXX devices only) This is the SPI port serial data output pin used for daisy-chaining more than one device. Data is clocked out of the SO pin on the falling edge of clock. This is a push-pull output and does not go to a high-impedance state when CS is high. It will drive a logic-low when CS is high. 3.8 Reset (RS) (MCP42XXX devices only) The Reset pin will set all potentiometers to mid-scale (Code 80h) if this pin is brought low for at least 150 ns. This pin should not be toggled low when the CS pin is low. It is possible to toggle this pin when the SHDN pin is low. In order to minimize power consumption, this pin has an active pull-up circuit. The performance of this circuit is shown in Figure 2-12. This pin will draw negligible current at logic level ‘0’ and logic level ‘1’. Do not leave this pin floating. DS11195C-page 12 MCP41XXX Pins Pin # Name Function 1 CS Chip Select 2 SCK Serial Clock 3 SI Serial Data Input 4 VSS Ground 5 PA0 Terminal A Connection For Pot 0 6 PW0 Wiper Connection For Pot 0 7 PB0 Terminal B Connection For Pot 0 8 VDD Power TABLE 3-2: MCP42XXX Pins Pin # Name Function 1 CS Chip Select 2 SCK Serial Clock 3 SI Serial Data Input 4 VSS Ground 5 PB1 Terminal B Connection For Pot 1 6 PW1 Wiper Connection For Pot 1 7 PA1 Terminal A Connection For Pot 1 8 PA0 Terminal A Connection For Pot 0 9 PW0 Wiper Connection For Pot 0 10 PB0 Terminal B Connection For Pot 0 11 RS Reset Input 12 SHDN Shutdown Input 13 SO Data Out for Daisy-Chaining 14 VDD Power 2003 Microchip Technology Inc. MCP41XXX/42XXX 4.0 APPLICATIONS INFORMATION The MCP41XXX/42XXX devices are 256 position single and dual digital potentiometers that can be used in place of standard mechanical pots. Resistance values of 10 kΩ, 50 kΩ and 100 kΩ are available. As shown in Figure 4-1, each potentiometer is made up of a variable resistor and an 8-bit (256 position) data register that determines the wiper position. There is a nominal wiper resistance of 52Ω for the 10 kΩ version, 125Ω for the 50 kΩ and 100 kΩ versions. For the dual devices, the channel-to-channel matching variation is less than 1%. The resistance between the wiper and either of the resistor endpoints varies linearly according to the value stored in the data register. Code 00h effectively connects the wiper to the B terminal. At power-up, all data registers will automatically be loaded with the mid-scale value (80h). The serial interface provides the means for loading data into the shift register, which is then transferred to the data registers. The serial interface also provides the means to place individual potentiometers in the shutdown mode for maximum power savings. The SHDN pin can also be used to put all potentiometers in shutdown mode and the RS pin is provided to set all potentiometers to mid-scale (80h). PW0 PA0 PW1 PB0 PA1 PB1 RDAC2 RDAC1 Data Register 0 Data Register 1 D7 D7 D0 D0 RS Decode Logic CS D7 D0 16-bit Shift Register SCK SI SO SHDN FIGURE 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B, without changing the state of the data registers. VDD VDD µC Data Lines MCP4XXXX 0.1 uF 0.1 uF B W A To Application Circuit 2003 Microchip Technology Inc. When laying out the circuit for your digital potentiometer, bypass capacitors should be used. These capacitors should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high-frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. DS11195C-page 13 MCP41XXX/42XXX 4.1 Modes of Operation Digital potentiometer applications can be divided into two categories: rheostat mode and potentiometer, or voltage divider, mode. 4.1.1 RHEOSTAT MODE In the rheostat mode, the potentiometer is used as a two-terminal resistive element. The unused terminal should be tied to the wiper, as shown in Figure 4-2. Note that reversing the polarity of the A and B terminals will not affect operation. 4.1.2 POTENTIOMETER MODE In the potentiometer mode, all three terminals of the device are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This mode is sometimes called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure 4-3. Note that reversing the polarity of the A and B terminals will not affect operation. V1 A A W W B B MCP4XXXX V2 MCP4XXXX Resistor FIGURE 4-2: Two-terminal or rheostat configuration for the digital potentiometer. Acting as a resistive element in the circuit, resistance is controlled by changing the wiper setting. Using the device in this mode allows control of the total resistance between the two nodes. The total measured resistance would be the least at code 00h, where the wiper is tied to the B terminal. The resistance at this code is equal to the wiper resistance, typically 52Ω for the 10 kΩ MCP4X010 devices, 125Ω for the 50 kΩ (MCP4X050), and 100 kΩ (MCP4X100) devices. For the 10 kΩ device, the LSB size would be 39.0625Ω (assuming 10 kΩ total resistance). The resistance would then increase with this LSB size until the total measured resistance at code FFh would be 9985.94Ω. The wiper will never directly connect to the A terminal of the resistor stack. FIGURE 4-3: divider mode. Three terminal or voltage In this configuration, the ratio of the internal resistance defines the temperature coefficient of the device. The resistor matching of the RWB resistor to the RAB resistor performs with a typical temperature coefficient of 1 ppm/°C (measured at code 80h). At lower codes, the wiper resistance temperature coefficient will dominate. Figure 2-3 shows the effect of the wiper. Above the lower codes, this figure shows that 70% of the states will typically have a temperature coefficient of less than 5 ppm/°C. 30% of the states will typically have a ppm/°C of less than 1. In the 00h state, the total resistance is the wiper resistance. To avoid damage to the internal wiper circuitry in this configuration, care should be taken to ensure the current flow never exceeds 1 mA. For dual devices, the variation of channel-to-channel matching of the total resistance from A to B is less than 1%. The device-to-device matching, however, can vary up to 30%. In the rheostat mode, the resistance has a positive temperature coefficient. The change in wiperto-end terminal resistance over temperature is shown in Figure 2-8. The most variation over temperature will occur in the first 6% of codes (code 00h to 0Fh) due to the wiper resistance coefficient affecting the total resistance. The remaining codes are dominated by the total resistance tempco RAB, typically 800 ppm/°C. DS11195C-page 14 2003 Microchip Technology Inc. MCP41XXX/42XXX 4.2 Typical Applications 4.2.1 PROGRAMMABLE SINGLE-ENDED AMPLIFIERS Potentiometers are often used to adjust system reference levels or gain. Programmable gain circuits using digital potentiometers can be realized in a number of different ways. An example of a single-supply, inverting gain amplifier is shown in Figure 4-4. Due to the high input impedance of the amplifier, the wiper resistance is not included in the transfer function. For a single-supply, non-inverting gain configuration, the circuit in Figure 4-5 can be used. . MCP41010 B A VDD W -IN - MCP606 +IN + VREF V OUT VOUT VSS 10 R R = – V IN ------B- + V REF 1 + ------B- R R A A Where: Absolute Gain (V/V) VIN R AB ( 256 – D n ) R A = -------------------------------------256 In order for these circuits to work properly, care must be taken in a few areas. For linear operation, the analog input and output signals must be in the range of VSS to VDD for the potentiometer and input and output rails of the op-amp. The circuit in Figure 4-4 requires a virtual ground or reference input to the non-inverting input of the amplifier. Refer to Application Note 682, “Using Single-Supply Operational Amplifiers in Embedded Systems” (DS00682), for more details. At power-up or reset (RS), the resistance is set to mid-scale, with RA and RB matching. Based on the transfer function for the circuit, the gain is -1 V/V. As the code is increased and the wiper moves towards the A terminal, the gain increases. Conversely, when the wiper is moved towards the B terminal, the gain decreases. Figure 4-6 shows this relationship. Notice the pseudo-logarithmic gain around decimal code 128. As the wiper approaches either terminal, the step size in the gain calculation increases dramatically. Due to the mismatched ratio of RA and RB at the extreme high and low codes, small increments in wiper position can dramatically affect the gain. As shown in Figure 4-3, recommended gains lie between 0.1 and 10 V/V. R AB D n R B = ----------------256 R AB = Total Resistance of pot D n = Wiper setting forD n = 0 to 255 1 0.1 0 FIGURE 4-4: Single-supply, programmable, inverting gain amplifier using a digital potentiometer. VDD VIN +IN MCP606 -IN RA W VOUT VSS RB MCP41010 Where: R AB ( 256 – D n ) R A = -------------------------------------256 R V OUT = V IN 1 + ------B- R A R AB D n R B = ----------------256 128 192 256 Decimal code (0-255) FIGURE 4-6: Gain vs. Code for inverting and differential amplifier circuits. 4.2.2 + 64 PROGRAMMABLE DIFFERENTIAL AMPLIFIER An example of a differential input amplifier using digital potentiometers is shown in Figure 4-7. For the transfer function to hold, both pots must be programmed to the same code. The resistor-matching from channel-tochannel within a dual device can be used as an advantage in this circuit. This circuit will also show stable operation over temperature due to the low potentiometer temperature coefficient. Figure 4-6 also shows the relationship between gain and code for this circuit. As the wiper approaches either terminal, the step size in the gain calculation increases dramatically. This circuit is recommended for gains between 0.1 and 10 V/V. R AB = Total Resistance of pot D n = Wiper setting forD n = 0 to 255 FIGURE 4-5: Single-supply, programmable, non-inverting gain amplifier. 2003 Microchip Technology Inc. DS11195C-page 15 MCP41XXX/42XXX 4.3 1/2 MCP42010 A B VB (SIG -) -IN VA A 1/2 MCP42010 (SIG +) Where: RA VDD + VOUT MCP601 +IN - VSS B VREF RB R AB D n = ----------------256 R AB = Total Resistance of pot D n = Wiper setting forDn = 0 to 255 NOTE: Potentiometer values must be equal FIGURE 4-7: Single Supply programmable differential amplifier using digital potentiometers. PROGRAMMABLE OFFSET TRIM For applications requiring only a programmable voltage reference, the circuit in Figure 4-8 can be used. This circuit shows the device used in the potentiometer mode along with two resistors and a buffered output. This creates a circuit with a linear relationship between voltage-out and programmed code. Resistors R1 and R2 can be used to increase or decrease the output voltage step size. The potentiometer in this mode is stable over temperature. The operation of this circuit over temperature is shown in Figure 2-3. The worst performance over temperature will occur at the lower codes due to the dominating wiper resistance. R1 and R2 can also be used to affect the boundary voltages, thereby eliminating the use of these lower codes. VDD VDD MCP41010 R1 -IN B R2 - MCP606 OUT +IN + VSS 0.1 uF A VSS FIGURE 4-8: By changing the values of R1 and R2, the voltage output resolution of this programmable voltage reference circuit is affected. DS11195C-page 16 When programming the digital potentiometer settings, the following equations can be used to calculate the resistances. Programming code 00h effectively brings the wiper to the B terminal, leaving only the wiper resistance. Programming higher codes will bring the wiper closer to the A terminal of the potentiometer. The equations in Figure 4-9 can be used to calculate the terminal resistances. Figure 4-10 shows an example calculation using a 10 kΩ potentiometer. R V OUT = ( V A – V B ) ------BRA R AB ( 256 – D n ) = -------------------------------------256 4.2.3 Calculating Resistances PA PW PB ( R AB ) ( 256 – D n ) - + RW R WA ( D n ) = ------------------------------------------256 ( R AB ) ( D n ) - + RW R WB ( D n ) = --------------------------256 Where: PA is the A terminal PB is the B terminal PW is the wiper terminal RWA is resistance between Terminal A and wiper RWB is resistance between Terminal B and Wiper RAB is overall resistance for pot (10 kΩ, 50 kΩ or 100 kΩ) RW is wiper resistance Dn is 8-bit value in data register for pot number n FIGURE 4-9: Potentiometer resistances are a function of code. It should be noted that, when using these equations for most feedback amplifier circuits (see Figure 4-4 and Figure 4-5), the wiper resistance can be omitted due to the high impedance input of the amplifier. PA 10 kΩ PW Example: R = 10 kΩ Code = C0h = 192d PB ( R AB ) ( 256 – D n ) R WA ( D n ) = ------------------------------------------- + RW 256 ( 10k Ω ) ( 256 – 192 ) R WA ( C0h ) = --------------------------------------------------- + 52 Ω 256 R WA ( C0h ) = 2552 Ω ( R AB ) ( D n ) - + RW R WB ( D n ) = --------------------------256 ( 10k Ω ) ( 192 ) R WB ( C0h ) = ----------------------------------- + 52 Ω 256 R WB ( C0h ) = 7552 Ω Note: All values shown are typical and actual results will vary. FIGURE 4-10: calculations. Example Resistance 2003 Microchip Technology Inc. MCP41XXX/42XXX 5.0 SERIAL INTERFACE Communications from the controller to the MCP41XXX/42XXX digital potentiometers is accomplished using the SPI serial interface. This interface allows three commands: 1. 2. 3. Write a new value to the potentiometer data register(s). Cause a channel to enter low power shutdown mode. NOP (No Operation) command. Executing any command is accomplished by setting CS low and then clocking-in a command byte followed by a data byte into the 16-bit shift register. The command is executed when CS is raised. Data is clockedin on the rising edge of clock and out the SO pin on the falling edge of the clock (see Figure 5-1). The device will track the number of clocks (rising edges) while CS is low and will abort all commands if the number of clocks is not a multiple of 16. 5.1 Command Byte The first byte sent is always the command byte, followed by the data byte. The command byte contains two command select bits and two potentiometer select bits. Unused bits are ‘don’t care’ bits. The command select bits are summarized in Figure 5-2. The command select bits C1 and C0 (bits 4:5) of the command byte determine which command will be executed. If the command bits are both 0’s or 1’s, then a NOP command will be executed once all 16 bits have been loaded. This command is useful when using the daisychain configuration. When the command bits are 0,1, a write command will be executed with the 8 bits sent in the data byte. The data will be written to the potentiometer(s) determined by the potentiometer select bits. If the command bits are 1,0, then a shutdown command will be executed on the potentiometers determined by the potentiometer select bits. For the MCP42XXX devices, the potentiometer select bits P1 and P0 (bits 0:1) determine which potentiometers are to be acted upon by the command. A corresponding ‘1’ in the position signifies that the command for that potentiometer will get executed, while a ‘0’ signifies that the command will not effect that potentiometer (see Figure 5-2). 5.2 Writing Data Into Data Registers When new data is written into one or more of the potentiometer data registers, the write command is followed by the data byte for the new value. The command select bits C1, C0 are set to 0,1. The potentiometer selection bits P1 and P0 allow new values to be written to potentiometer 0, potentiometer 1 (or both) with a single command. A ‘1’ for either P1 or P0 will cause the data to be written to the respective data register and a ‘0’ for P1 or P0 will cause no change. See Figure 5-2 for the command format summary. 2003 Microchip Technology Inc. 5.3 Using The Shutdown Command The shutdown command allows the user to put the application circuit into a power-saving mode. In this mode, the A terminal is open-circuited and the B and W terminals are shorted together. The command select bits C1, C0 are set to 1,0. The potentiometer selection bits P1 and P0 allow each potentiometer to be shutdown independently. If either P1 or P0 are high, the respective potentiometer will enter shutdown mode. A ‘0’ for P1 or P0 will have no effect. The eight data bits following the command byte still need to be transmitted for the shutdown command, but they are ‘don’t care’ bits. See Figure 5-2 for command format summary. Once a particular potentiometer has entered the shutdown mode, it will remain in this mode until: • A new value is written to the potentiometer data register, provided that the SHDN pin is high. The device will remain in the shutdown mode until the rising edge of the CS is detected, at which time the device will come out of shutdown mode and the new value will be written to the data register(s). If the SHDN pin is low when the new value is received, the registers will still be set to the new value, but the device will remain in shutdown mode. This scenario assumes that a valid command was received. If an invalid command was received, the command will be ignored and the device will remain in the shutdown mode. It is also possible to use the hardware shutdown pin and reset pin to remove a device from software shutdown. To do this, a low pulse on the chip select line must first be sent. For multiple devices, sharing a single SHDN or RESET line allows you to pick an individual device on that chain to remove from software shutdown mode. See Figure 1-3 for timing. With a preceding chip select pulse, either of these situations will also remove a device from software shutdown: • A falling edge is seen on the RS pin and held low for at least 150 ns, provided that the SHDN pin is high. If the SHDN pin is low, the registers will still be set to mid-scale, but the device will remain in shutdown mode. This condition assumes that CS is high, as bringing the RS pin low while CS is low is an invalid state and results are indeterminate. • A rising edge on the SHDN pin is seen after being low for at least 100 ns, provided that the CS pin is high. Toggling the SHDN pin low while CS is low is an invalid state and results are indeterminate. • The device is powered-down and back up. Note: The hardware SHDN pin will always put the device in shutdown regardless of whether a potentiometer has already been put in the shutdown mode using the software command. DS11195C-page 17 MCP41XXX/42XXX Data is always latched in on the rising edge of SCK. Data is always clocked out of the SO pin after the falling edge of SCK. Data Registers are loaded on rising edge of CS. Shift register is loaded with zeros at this time. CS† 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK COMMAND Byte Don’t Care Bits X SI X Command Bits Don’t Care Bits C1 C0 X Data Byte Channel Select Bits New Register Data X P1* P0 D7 D6 D5 D4 D3 D2 D1 D0 First 16 bits shifted out will always be zeros SO‡ X SO pin will always drive low when CS goes high. † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. * P1 is a ‘don’t care’ bit for the MCP41XXX. FIGURE 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer. COMMAND BYTE X X C1 C0 X Command Selection Bits C1 C0 Command X P1* P0 Potentiometer Selection Bits Command Summary P1* P0 Potentiometer Selections 0 0 None No Command will be executed. 0 0 0 1 Write Data Write the data contained in Data Byte to the potentiometer(s) determined by the potentiometer selection bits. Dummy Code: Neither Potentiometer affected. 0 1 Command executed on Potentiometer 0. 1 0 Command executed on Potentiometer 1. 1 1 Command executed on both Potentiometers. 1 0 Shutdown Potentiometer(s) determined by potentiometer selection bits will enter Shutdown Mode. Data bits for this command are ‘don’t cares’. 1 1 None No Command will be executed. FIGURE 5-2: DS11195C-page 18 Command Byte Format. 2003 Microchip Technology Inc. MCP41XXX/42XXX 5.4 Daisy-Chain Configuration Multiple MCP42XXX devices can be connected in a daisy-chain configuration, as shown in Figure 5-4, by connecting the SO pin from one device to the SI pin on the next device. The data on the SO pin is the output of the 16-bit shift register. The daisy-chain configuration allows the system designer to communicate with several devices without using a separate CS line for each device. The example shows a daisy-chain configuration with three devices, although any number of devices (with or without the same resistor values) can be configured this way. While it is not possible to use a MCP41XXX at the beginning or middle of a daisy-chain (because it does not provide the serial data out (SO) pin), it is possible to use the device at the end of a chain. As shown in the timing diagram in Figure 5-3, data will be clocked-out of the SO pin on the falling edge of the clock. The SO pin has a CMOS push-pull output and will drive low when CS goes high. SO will not go to a high-impedance state when CS is held high. When using the daisy-chain configuration, the maximum clock speed possible is reduced to ~5.8 MHz, because of the propagation delay of the data coming out of the SO pin. When using the daisy-chain configuration, keep in mind that the shift register of each device is automatically loaded with zeros whenever a command is executed (CS = high). Because of this, the first 16 bits that come out of the SO pin once the CS line goes low will always be zeros. This means that when the first command is being loaded into a device, it will always shift a NOP command into the next device on the chain because the command bits (and all the other bits) will be zeros. This feature makes it necessary only to send command and data bytes to the device farthest down the chain that needs a new command. For example, if there were three devices on the chain and it was desired to send a command to the device in the middle, only 32 bytes of data need to be transmitted. The last device on the chain will have a NOP loaded from the previous device so no registers will be affected when the CS pin is raised to execute the command. The user must always ensure that multiples of 16 clocks are always provided (while CS is low), as all commands will abort if the number of clocks provided is not a multiple of 16. Data Registers for all devices are loaded on Rising Edge of CS CS 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10 111213141516 1 2 3 4 5 6 7 8 9 10 111213141516 SCK Command Byte for Device 3 SI Data Byte for Device 3 X XC C X X P P D DD DDDD D SO First 16 bits shifted out will always be zeros Command Byte for Device 2 Data Byte for Device 2 Command Byte for Device 1 Data Byte for Device 1 X XC C X X P P D DD DDDD D X XC C X X P P D DD DDDD D Command and Data for Device 3 start shifting out after the first 16 clocks Command and Data for Device 2 start shifting out after the first 32 clocks X XC C X X P P D DD DD DD D X XC C X X P P D DD DDDD D † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. FIGURE 5-3: Timing Diagram for Daisy-Chain Configuration. 2003 Microchip Technology Inc. DS11195C-page 19 MCP41XXX/42XXX CS SCK SO Microcontroller CS SCK SO SI Device 1 EXAMPLE: CS SCK SI SO Device 2 If you want to load the following command/data into each part in the chain. Device 2 XX01XX10 11110000 c SI Device 3 XX10XX00 10101010 After 16 clocks, Device 2 and Device 3 will both have all zeros clocked in from the previous part’s shift register. Device 1 XX10XX00 10101010 Device 2 00000000 00000000 d Clock-In the command and data for Device 2 (16 more clocks). The data that was previously loaded gets shifted to the next device on the chain. SCK Device 3* Device 1 XX10XX11 11001100 Start by setting CS low and clocking in the command and data that will end up in Device 3 (16 clocks). CS Device 3 00000000 00000000 After 32 clocks, Device 2 has the data previously loaded into Device 1 and Device 3 gets 16 more zeros. Device 1 XX01XX10 11110000 Device 2 XX10XX00 10101010 Device 3 00000000 00000000 e Clock-In the data for Device 1 (16 more clocks). The data that was previously loaded into Device 1 gets shifted into Device 2 and Device 3 contains the first byte loaded. Raise the CS line to execute the commands for all 3 devices at the same time. FIGURE 5-4: DS11195C-page 20 After 48 clocks, all 3 devices have the proper command/ data loaded into their shift registers. Device 1 XX10XX11 11001100 Device 2 XX01XX10 11110000 Device 3 XX10XX00 10101010 * Last device on a daisy-chain may be a single channel MCP41XXX device. Daisy-Chain Configuration. 2003 Microchip Technology Inc. MCP41XXX/42XXX 5.5 Reset (RS) Pin Operation The Reset pin (RS) will automatically set all potentiometer data latches to mid-scale (Code 80h) when pulled low (provided that the pin is held low at least 150 ns and CS is high). The reset will execute regardless of the position of the SCK, SHDN and SI pins. It is possible to toggle RS low and back high while SHDN is low. In this case, the potentiometer registers will reset to mid-scale, but the potentiometer will remain in shutdown mode until the SHDN pin is raised. TABLE 5-1: TRUTH TABLE FOR LOGIC INPUTS SCK CS RS SHDN Action X Ø H H Communication is initiated with device. Device comes out of standby mode. L L H H No action. Device is waiting for data to be clocked into shift register or CS to go high to execute command. ¦ L H X Shift one bit into shift register. The shift register can be loaded while the SHDN pin is low. Ø L H X Shift one bit out of shift register on the SO pin. The SO pin is active while the SHDN pin is low. When held low, the shutdown pin causes the application circuit to go into a power-saving mode by open-circuiting the A terminal and shorting the B and W terminals for all potentiometers. Data register contents are not affected by entering shutdown mode (i.e., when the SHDN pin is raised, the data register contents are the same as before the shutdown mode was entered). X ¦ H H Based on command bits, either load data from shift register into data latches or execute shutdown command. Neither command executed unless multiples of 16 clocks have been entered while CS is low. SO pin goes to a logic low. While in shutdown mode, it is still possible to clock in new values for the data registers, as well as toggling the RS pin to cause all data registers to go to mid-scale. The new values will take affect when the SHDN pin is raised. X H H H Static Operation. X H Ø H All data registers set and latched to code 80h. X H Ø L All data registers set and latched to code 80h. Device is in hardware shutdown mode and will remain in this mode. X H H Ø All potentiometers put into hardware shutdown mode; terminal A is open and W is shorted to B. X H H ¦ All potentiometers exit hardware shutdown mode. Potentiometers will also exit software shutdown mode if this rising edge occurs after a low pulse on CS. Contents of data latches are restored. Note: 5.6 Bringing the RS pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when RS and/or CS are brought high. Shutdown (SHDN) Pin Operation If the device is powered-up with the SHDN pin held low, it will power-up in the shutdown mode with the data registers set to mid-scale. Note: 5.7 Bringing the SHDN pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when SHDN and/or CS are brought high. Power-up Considerations When the device is powered on, the data registers will be set to mid-scale (80h). A power-on reset circuit is utilized to ensure that the device powers up in this known state. 2003 Microchip Technology Inc. DS11195C-page 21 MCP41XXX/42XXX 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 It is possible to operate the devices in SPI modes 0,0 and 1,1. The only difference between these two modes is that, when using mode 1,1, the clock idles in the high state, while in mode 0,0, the clock idles in the low state. In both modes, data is clocked into the devices on the rising edge of SCK and data is clocked out the SO pin once the falling edge of SCK. Operations using mode 0,0 are shown in Figure 5-1. The example in Figure 5-5 shows mode 1,1. Data is always clocked out the SO pin after the falling edge of SCK. Data is always latched in on the rising edge of SCK. CS† 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D1 D0 Data Registers are loaded on rising edge of CS. Shift register is loaded with zeros at this time. SCK COMMAND BYTE Don’t Care Bits SI SO‡ X X Command Bits C1 C0 Don’t Care Bits X X DATA BYTE Channel Select Bits P1* P0 New Register Data D7 D6 D5 D4 D3 D2 First 16 bits Shifted out will always be zeros X SO pin will always drive low when CS goes high. † There must always be multiples of 16 clocks while CS is low or commands will abort. ‡ The serial data out pin (SO) is only available on the MCP42XXX device. FIGURE 5-5: DS11195C-page 22 Timing Diagram for SPI Mode 1,1 Operation. 2003 Microchip Technology Inc. MCP41XXX/42XXX 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP41010 I/P256 0313 8-Lead SOIC (150 mil) Example: XXXXXXXX XXXXYYWW NNN MCP41050 I/SN0313 256 14-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) MCP42010 I/P 0313256 Example: 42050ISL XXXXXXXXXXX 0313256 XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP (4.4mm) * Example: XXXXXXXX YYWW 0313 NNN 256 Legend: XX...X YY WW NNN Note: * 42100I Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. 2003 Microchip Technology Inc. DS11195C-page 23 MCP41XXX/42XXX 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS11195C-page 24 2003 Microchip Technology Inc. MCP41XXX/42XXX 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2003 Microchip Technology Inc. DS11195C-page 25 MCP41XXX/42XXX 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 B1 β eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS11195C-page 26 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2003 Microchip Technology Inc. MCP41XXX/42XXX 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2003 Microchip Technology Inc. DS11195C-page 27 MCP41XXX/42XXX 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c φ β A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS11195C-page 28 2003 Microchip Technology Inc. MCP41XXX/42XXX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP41010: Single Digital Potentiometer (10 kΩ) MCP41010T: Single Digital Potentiometer (10 kΩ) (Tape and Reel) MCP41050: Single Digital Potentiometer (50 kΩ) (Tape and Reel) MCP41050T: Single Digital Potentiometer (50 kΩ) MCP41100: Single Digital Potentiometer (100 kΩ) (Tape and Reel) MCP41100T: Single Digital Potentiometer (100 kΩ) MCP42010: Dual Digital Potentiometer (10 kΩ) MCP42010T: Dual Digital Potentiometer (10 kΩ) (Tape and Reel) MCP42050: Dual Digital Potentiometer (50 kΩ) MCP42050T: Dual Digital Potentiometer (50 kΩ) (Tape and Reel) MCP42100: Dual Digital Potentiometer (100 kΩ) MCP42100T: Dual Digital Potentiometer (100 kΩ) (Tape and Reel) Temperature Range: Package: I E P SN SL ST = = -40°C to +85°C -40°C to +125°C = = = = Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead TSSOP (4.4mm Body), 14-lead Examples: a) b) c) h) i) MCP41010-I/SN: I-Temp., 8LD SOIC pkg. MCP41010-E/P: E-Temp., 8LD PDIP pkg. MCP41010T-I/SN: Tape and Reel, I-Temp., 8LD SOIC pkg. MCP41050-E/SN: E-Temp., 8LD SOIC pkg. MCP41050-I/P: I-Temp., 8LD PDIP pkg. MCP41050-E/SN: E-Temp., 8LD SOIC pkg. MCP41100-I/SN: I-Temp., 8LD SOIC package. MCP41100-E/P: E-Temp., 8LD PDIP pkg. MCP41100T-I/SN: I-Temp., 8LD SOIC pkg. a) b) c) MCP42010-E/P: MCP42010-I/SL: MCP42010-E/ST: d) MCP42010T-I/ST: e) f) MCP42050-E/P: MCP42050T-I/SL: g) h) MCP42050-E/SL: MCP42050-I/ST: i) MCP42050T-I/SL: j) MCP42050T-I/ST: k) l) m) MCP42100-E/P: MCP42100-I/SL: MCP42100-E/ST: n) MCP42100T-I/SL: o) MCP42100T-I/ST: d) e) f) g) E-Temp., 14LD PDIP pkg. I-Temp., 14LD SOIC pkg. E-Temp., 14LD TSSOP pkg. Tape and Reel, I-Temp., 14LD TSSOP pkg. E-Temp., 14LD PDIP pkg. Tape and Reel, I-Temp., 14LD SOIC pkg. E-Temp., 14LD SOIC pkg. I-Temp., 14LD TSSOP pkg. Tape and Reel, I-Temp., 14LD SOIC pkg. Tape and Reel, I-Temp., 14LD TSSOP pkg. E-Temp., 14LD PDIP pkg. I-Temp., 14LD SOIC pkg. E-Temp., 14LD TSSOP pkg. Tape and Reel, I-Temp., 14LD SOIC pkg. Tape and Reel, I-Temp., 14LD TSSOP pkg. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS11195C-page 29 MCP41XXX/42XXX NOTES: DS11195C-page 30 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS11195C-page 31 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc.