TI1 DRA725 Infotainment applications processor Datasheet

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
DRA72x Infotainment Applications Processor
Silicon Revision 2.0
1 Device Overview
1.1
Features
1
• Architecture Designed for Infotainment
Applications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
– 2D and 3D Graphics
• ARM® Cortex®-A15 Microprocessor Subsystem
• C66x Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x and
C64x+
– Up to Thirty-two 16 × 16-Bit Fixed-Point
Multiplies per Cycle
• Up to 512KB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR3/DDR3L Memory Interface (EMIF) Module
– Supports up to DDR3-1333 (667 MHz)
– Up to 2GB Across Single Chip Select
• Dual ARM® Cortex®-M4 Image Processing Units
(IPU)
• IVA-HD Subsystem
• Display Subsystem
– Display Controller With DMA Engine and up to
Three Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0
Compliant
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante™ GC320 Core
• Video Processing Engine (VPE)
• Single-Core PowerVR® SGX544 3D GPU
• One Video Input Port (VIP) Module
– Support for up to Four Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
Controller
• 2-Port Gigabit Ethernet (GMAC)
– Up to Two External Ports
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Six High-Speed Inter-Integrated Circuit (I2C) Ports
• HDQ™/1-Wire® Interface
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces
(McSPI)
• Quad SPI Interface (QSPI)
• Media Local Bus Subsystem (MLBSS)
• Real-Time Clock Subsystem (RTCSS)
• SATA Interface
• Eight Multichannel Audio Serial Port (McASP)
Modules
• SuperSpeed USB 3.0 Dual-Role Device
• High-Speed USB 2.0 Dual-Role Device
• High-Speed USB 2.0 On-The-Go
• Four MultiMedia Card/Secure Digital/Secure Digital
Input Output Interfaces (MMC/SD/SDIO)
• PCI Express® 3.0 Subsystems With Two 5-Gbps
Lanes
– One 2-lane Gen2-Compliant Port
– or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
– CAN 2.0B Protocol
• MIPI® CSI-2 Camera Serial Interface
• Up to 215 General-Purpose I/O (GPIO) Pins
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA
(ABC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
1.2
•
•
•
•
Applications
Human-Machine Interface (HMI)
Navigation
Digital and Analog Radio
Rear Seat Entertainment
1.3
www.ti.com
•
•
•
Multimedia Playback
AM/FM/RDS and Digital Radio Decoding
ADAS and Jacinto 6 Integration
Description
DRA72x ("Jacinto 6 Eco") infotainment applications processors are developed on the same architecture as
Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile
experiences.
DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family,
allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly
implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6
and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully
integrated mixed processor solution.
Programmability is provided by a single-core ARM Cortex-A15 RISC CPU with Neon™ extensions and a
TI C66x VLIW floating-point DSP core. The ARM processor lets developers keep control functions
separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity
of the system software.
Additionally, TI provides a complete set of development tools for the ARM, and DSP, including C
compilers and a debugging interface for visibility into source code execution.
The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.
Device Information
PART NUMBER
DRA72x
2
Device Overview
PACKAGE
BODY SIZE
FCBGA (760)
23.0 mm × 23.0 mm
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1.4
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Functional Block Diagram
Figure 1-1 is functional block diagram for the device.
DRA72x
MPU
IVA HD
(1x ARM
Cortex–A15)
1080p Video
Co-Processor
CSI2 x2
CAL
Radio Accelerators
VCP x2
GPU
BB2D
(1x SGX544 3D)
(GC320 2D)
HD ATL
Display Subsystem
1x GFX Pipeline
DSP
(1x C66x
Co-Processor)
IPU1
(Dual Cortex–M4)
3x Video Pipeline
IPU2
Blend / Scale
(Dual Cortex–M4)
EDMA
LCD1
sDMA
LCD2
LCD3
HDMI 1.4a
VIP x1
MMU x2
VPE
High-Speed Interconnect
System
Spinlock
Connectivity
Timers x16
1x USB 3.0
Mailbox x13
WDT
PWM SS x3
Dual Mode FS/HS/SS
w/ PHY
GPIO x8
RTC SS
HDQ
2x USB 2.0
MOST150
Dual Mode FS/HS
1x PHY, 1x ULPI
GMAC AVB
KBD
MediaLB
Program/Data Storage
Serial Interfaces
UART x10
QSPI
McSPI x4
McASP x8
512-KB
RAM with ECC
I2C x6
OCMC
EMIF x1
1x 32-bit
DDR3/3L
GPMC / ELM
(NAND/NOR/
Async)
256-KB ROM
DCAN x2
PCIe SS x2
MMC / SD x4
SATA
DMM
intro-001
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Figure 1-1. DRA72x Block Diagram
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Device Overview
3
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Table of Contents
1
2
3
Device Overview ......................................... 1
7.12
Timers .............................................. 246
1.1
Features .............................................. 1
7.13
Inter-Integrated Circuit Interface (I2C) ............. 246
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
7.14
7.15
1.4
Functional Block Diagram
HDQ / 1-Wire Interface (HDQ1W) ................. 249
Universal Asynchronous Receiver Transmitter
(UART) ............................................. 252
Revision History ......................................... 5
Device Comparison ..................................... 6
7.16
Multichannel Serial Peripheral Interface (McSPI)
253
7.17
Quad Serial Peripheral Interface (QSPI)
259
Device Comparison Table ............................ 6
7.18
Terminal Configuration and Functions .............. 8
7.19
4.1
Terminal Assignment ................................. 8
4.2
Ball Characteristics ................................... 9
7.20
7.21
4.3
Multiplexing Characteristics ......................... 71
4.4
Signal Descriptions .................................. 88
3.1
4
5
6
7
.........................................
5.1
Absolute Maximum Ratings........................
5.2
ESD Ratings .......................................
5.3
Power on Hour (POH) Limits ......................
5.4
Recommended Operating Conditions .............
5.5
Operating Performance Points .....................
5.6
Power Consumption Summary ....................
5.7
Electrical Characteristics ...........................
5.8
Thermal Characteristics ............................
5.9
Power Supply Sequences .........................
Clock Specifications .................................
6.1
Input Clock Specifications .........................
6.2
DPLLs, DLLs Specifications .......................
Specifications
3
126
126
127
127
128
131
153
153
163
174
175
184
7.1
Timing Test Conditions ............................ 188
7.2
Interface Clock Specifications
.....................
Timing Parameters and Information ...............
188
188
Recommended Clock and Control Signal Transition
Behavior............................................ 190
7.5
Virtual and Manual I/O Timing Modes ............. 190
7.6
Video Input Ports (VIP) ............................ 192
7.7
7.8
Display Subsystem - Video Output Ports .......... 211
Display Subsystem - High-Definition Multimedia
Interface (HDMI) ................................... 221
7.9
Camera Serial Interface 2 CAL bridge (CSI2) ..... 222
7.10
External Memory Interface (EMIF)................. 222
7.11
General-Purpose Memory Controller (GPMC) ..... 222
Table of Contents
8
162
Timing Requirements and Switching
Characteristics ........................................ 188
7.3
7.4
4
...........................
9
.
..........
Multichannel Audio Serial Port (McASP) ..........
Universal Serial Bus (USB) ........................
Serial Advanced Technology Attachment (SATA) .
263
283
284
Peripheral Component Interconnect Express
(PCIe) .............................................. 285
7.22
Controller Area Network Interface (DCAN) ........ 285
7.23
Ethernet Interface (GMAC_SW) ................... 286
7.24
Media Local Bus (MLB) interface .................. 299
7.25
eMMC/SD/SDIO
7.26
General-Purpose Interface (GPIO) ................ 324
7.27
Audio Tracking Logic (ATL) ........................ 325
7.28
System and Miscellaneous interfaces ............. 325
7.29
Test Interfaces ..................................... 325
...................................
300
Applications, Implementation, and Layout ...... 330
........................................
8.1
Introduction
8.2
Power Optimizations ............................... 331
8.3
Core Power Domains .............................. 342
...........................
..............................
8.6
Clock Routing Guidelines ..........................
8.7
DDR3 Board Design and Layout Guidelines.......
Device and Documentation Support ..............
9.1
Device Nomenclature ..............................
9.2
Tools and Software ................................
9.3
Documentation Support ............................
9.4
Receiving Notification of Documentation Updates.
9.5
Community Resources.............................
9.6
Related Links ......................................
9.7
Trademarks ........................................
9.8
Electrostatic Discharge Caution ...................
9.9
Export Control Notice ..............................
9.10 Glossary............................................
8.4
Single-Ended Interfaces
8.5
Differential Interfaces
330
352
354
375
376
400
400
402
402
403
403
403
403
404
404
404
10 Mechanical Packaging and Orderable
Information ............................................. 405
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2 Revision History
Changes from August 1, 2016 to January 30, 2017 (from A Revision (July 2016) to B Revision)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
Updated Features list ................................................................................................................ 1
Updated DSIS Description for "blank" in Section 4.2 ........................................................................... 11
Added a note regarding rstoutn in Table 4-30 ................................................................................. 119
Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 4-30 ...................................... 119
Updated ESD Ratings table to include HDMI pins specifics ................................................................. 127
Fixed typos and clean-up in Table 5-4 .......................................................................................... 128
Updated IQ1833 Buffers DC Electrical Characteristics Table ............................................................... 156
Updated rstoutn timing in Figure 5-4 ............................................................................................ 164
Added DSS_VIRTUAL1 and MMC2_VIRTUAL2 options to the Timing Chapter Section 7 .............................. 190
Changed GPMC 1 Load / 5 Load to Default Mode / Alternate Mode in Table 7-2 ........................................ 190
Added new timing information for VIP, DSS VOUT, GPMC, McSPI, QSPI, McASP and Ethernet Interfaces ........ 192
Added missing balls for vin1b in IOSET7 in Table 7-4 ....................................................................... 194
Updated Manual Modes for VIP, DSS and MMC modules ................................................................... 201
Updated are Virtual Mode Case Details for McASP2 when AXR(Inputs)/CLKX/FSX in 80MHz and non-80MHz
operation. .......................................................................................................................... 270
Fixed typo in naming of Figure 7-47 to Figure 7-50 ........................................................................... 277
Removed 1149.7 (cJTAG) support from the DRA72x family of devices.................................................... 328
Updated details for SMPS1 of the TPS65917 PMIC in Table 8-5 ........................................................... 346
Updated capacitor value in diagram for PLL supply decoupling ............................................................ 356
Updated symbolization in Printed Device Reference Figure 9-1 and Nomenclature Description Table 9-1 ........... 401
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3 Device Comparison
3.1
Device Comparison Table
Table 3-1 shows a comparison between devices, highlighting the differences.
Table 3-1. Device Comparison
Device
Features
DRA722
DRA724
DRA725
DRA726
H
J
L
P
Processors/Accelerators
Speed Grades
ARM Single Cortex-A15 Microprocessor (MPU)
Subsystem
MPU core 0
Yes
C66x VLIW DSP
DSP1
Yes
BitBLT 2D Hardware Acceleration Engine (BB2D)
BB2D
Yes
VOUT1
Yes
VOUT2
Yes
VOUT3
Yes
HDMI
Yes
IPU1
Yes
Display Subsystem
Dual ARM Cortex-M4 Image Processing Unit (IPU)
IPU2
Yes
Image Video Accelarator (IVA)
IVA
Yes
SGX544 Single-Core 3D Graphics Processing Unit
(GPU)
GPU
Yes
vin1a
Yes
vin1b
Yes
vin2a
Yes
vin2b
Yes
VPE
Yes
Video Input Port (VIP)
VIP1
Video Processing Engine (VPE)
Program/Data Storage
On-Chip Shared Memory (RAM)
OCMC_RAM1
General-Purpose Memory Controller (GPMC)
GPMC
Yes
EMIF1
up to 2GB across single chip select
DDR3 Memory Controller
SECDED/ECC
Dynamic Memory Manager (DMM)
512KB
(1)
No
DMM
Yes
ATL
Yes
VCP1
Yes
VCP2
Yes
DCAN1
Yes
DCAN2
Yes
Enhanced DMA (EDMA)
EDMA
Yes
System DMA (DMA_SYSTEM)
DMA_SYSTEM
Yes
Radio Support
Audio Tracking Logic (ATL)
Viterbi Coprocessor (VCP)
Peripherals
Dual Controller Area Network (DCAN) Interface
Ethernet Subsystem (Ethernet SS)
General-Purpose I/O (GPIO)
GMAC_SW[0]
MII, RMII, or RGMII
GMAC_SW[1]
MII, RMII, or RGMII
GPIO
2
Up to 215
Inter-Integrated Circuit Interface (I C)
I2C
6
System Mailbox Module
MAILBOX
13
Media Local Bus Subsystem (MLBSS)
MLB
(1)
6
Yes
ECC is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.
Device Comparison
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Table 3-1. Device Comparison (continued)
Device
Features
DRA722
Camera Adaptation Layer (CAL) Camera Serial
Interface 2 (CSI2)
Multichannel Audio Serial Port (McASP)
MultiMedia Card/Secure Digital/Secure Digital Input
Output Interface (MMC/SD/SDIO)
DRA724
CSI2_0
1 CLK + 4 Data
CSI2_1
1 CLK + 2 Data
McASP1
16 serializers
McASP2
16 serializers
McASP3
4 serializers
McASP4
4 serializers
McASP5
4 serializers
McASP6
4 serializers
McASP7
4 serializers
McASP8
4 serializers
MMC1
1x UHSI 4b
MMC2
1x eMMC 8b
MMC3
1x SDIO 8b
MMC4
PCI Express 3.0 Port with Integrated PHY
DRA725
1x SDIO 4b
PCIe_SS1
Up to two lanes (second lane shared with PCIe_SS2 and
USB1)
PCIe_SS2
Single lane (shared with PCIe_SS1 and USB1)
Serial Advanced Technology Attachment (SATA)
SATA
Yes
Real-Time Clock Subsystem (RTCSS)
RTCSS
Yes
Multichannel Serial Peripheral Interface (McSPI)
McSPI
4
HDQ1W
HDQ1W
Yes
Quad SPI (QSPI)
QSPI
Yes
Spinlock Module
SPINLOCK
Yes
Keyboard Controller (KBD)
KBD
Yes
Timers, General-Purpose
TIMERS GP
16
Timer, Watchdog
WD TIMER
Yes
PWMSS1
Yes
PWMSS2
Yes
PWMSS3
Yes
Pulse-Width Modulation Subsystem (PWMSS)
Universal Asynchronous Receiver/Transmitter (UART) UART
Universal Serial Bus (USB3.0)
Universal Serial Bus (USB2.0)
DRA726
10
USB1 (Super-Speed,
Dual-Role-Device
[DRD])
Yes
USB2 (High-Speed,
Dual-Role-Device
[DRD], with
embedded HS PHY)
Yes
USB3 (High-Speed,
OTG2.0, with ULPI)
Yes
USB4 (High-Speed,
OTG2.0, with ULPI)
No
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4 Terminal Configuration and Functions
4.1
Terminal Assignment
Figure 4-1 shows the ball locations for the 760 plastic ball grid array (PBGA) package and isused in
conjunction with Table 4-2 through Table 4-35 to locate signal names and ball grid numbers.
SPRS906_BALL_01
Figure 4-1. ABC S-PBGA-N760 Package (Bottom View)
NOTE
The following bottom balls are not pinned out: AF7, AF10, AF13, AF16, AF19, AE4, AE25,
AB26, W3, W26, T3, T26, N3, N26, K3, K26, G3, D4, D25, C10, C13, C16, C19, C22.
These balls do not exist on the package.
NOTE
The following bottom balls are not connected: AH11, AH12, AG2, AG8, AG11, AG12, AF4,
AF6, AF8, AF9, AE3, AE5, AE6, AE8, AE9, AD3, AD8, AD9, Y15, Y16, V18, V19, U18, U19,
U22, U23, U24, U25, U26, U27, U28, T22, T23, T27, T28, R20, R22, R23, R24, R25, R26,
R27, R28, P19, P22, P23, P24, P25, P26, P27, N20, N22, N23, N27, N28, M20, M21, M22,
M23, M24, M25, M26, M27, M28, L20, L21, L22, L23, L24, L25, L26, L27, L28, K20, K21,
K22, K23, K27, K28, J20, J21, J22, J23, J24, J25, J26, J27, H20, H21, H22, H23, H24, H25,
H26, H27, H28, G22, G23, G24, G25, G26, G27, G28, F24, F25, F26, F27, F28, E24, E26,
E27, E28.
These balls can be connected as desired, including to VSS. For users designing DRA74x /
DRA75x compatible PCB, please refer to DRA75x/DRA74x Data Manual for appropriate
requirements.
4.1.1
Unused Balls Connection Requirements
This section describes the connection requirements of the unused and reserved balls.
8
Terminal Configuration and Functions
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NOTE
The following balls are reserved: A27, K14, Y5, Y10, B28
These balls must be left unconnected.
NOTE
All unused power supply balls must be supplied with the voltages specified in the
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are
included in Section 4.4, Signal Descriptions.
Table 4-1. Unused Balls Specific Connection Requirements
Balls
Connection Requirements
AE15, AC15, AE14, D20, AD17, AC16, V27
These balls must be connected to GND through an external pull
resistor if unused.
E20, D21, E23, C20, C21, V28, F18
These balls must be connect to the corresponding power supply
through an external pull resistor if unused.
AF14 (rtc_iso)
This ball should be connected to the corresponding power supply
through an external pull resistor if unused; or can be connected to
F22 (porz) when RTC unused (level translation may be needed)
AB17 (rtc_porz)
This ball should be connected to VSS when RTC is unused; or can
be connected to F22 (porz) when RTC unused (level translation may
be needed)
NOTE
All other unused signal balls with a Pad Configuration register can be left unconnected with
their internal pullup or pulldown resistor enabled.
NOTE
All other unused signal balls without a Pad Configuration register can be left unconnected.
4.2
Ball Characteristics
Table 4-2 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER:This column lists ball numbers on the bottom side associated with each signal on the
bottom.
2. BALL NAME: This column lists mechanical name from package device (name is taken from muxmode
0).
3. SIGNAL NAME:This column lists names of signals multiplexed on each ball (also notice that the name
of the ball is the signal name in muxmode 0).
NOTE
Table 4-2 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in Section 4.4, Signal Descriptions.
NOTE
In driver off mode, the buffer is configured in high-impedance.
Terminal Configuration and Functions
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NOTE
In some cases Table 4-2 may present more than one signal name per muxmode for the
same ball. First signal in the list is the dominant function as selected via
CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual
functions
are
controlled
via
CTRL_CORE_ALT_SELECT_MUX
or
CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
4. MUXMODE: Multiplexing mode number:
(a) MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
NOTE
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
(b) MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
5. TYPE: Signal type and direction:
– I = Input
– O = Output
– IO = Input or Output
– D = Open drain
– DS = Differential Signaling
– A = Analog
– PWR = Power
– GND = Ground
– CAP = LDO Capacitor
6. BALL RESET STATE: The state of the terminal at power-on reset:
– drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
– drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
– OFF: High-impedance
– PD: High-impedance with an active pulldown resistor
– PU: High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal)
– drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
– drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
– drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
– OFF: High-impedance
– PD: High-impedance with an active pulldown resistor
– PU: High-impedance with an active pullup resistor
NOTE
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power, Reset, and Clock Management / PRCM Reset Management Functional
Description section of the Device TRM.
8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
10
Terminal Configuration and Functions
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rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
9. IO VOLTAGE VALUE: This column describes the IO voltage value (VDDS supply).
10. POWER: The voltage supply that powers the terminal IO buffers.
11. HYS: Indicates if the input buffer is with hysteresis:
– Yes: With hysteresis
– No: Without hysteresis
An empty box means "Yes".
NOTE
For more information, see the hysteresis values in Section 5.7, Electrical Characteristics.
12. BUFFER TYPE: Drive strength of the associated output buffer.
NOTE
For programmable buffer strength:
– The default value is given in Table 4-2.
– A note describes all possible values according to the selected muxmode.
13. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
– 0: Logic 0 driven on the peripheral's input signal port.
– 1: Logic 1 driven on the peripheral's input signal port.
– blank: Pin state driven on the peripheral's input signal port.
NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
NOTE
Some of the EMIF1 signals have an additional state change at the release of porz. The state
that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_csn0, ddr1_ck, ddr1_nck, ddr1_casn, ddr1_rasn, ddr1_wen,
ddr1_ba[2:0], ddr1_a[15:0].
OFF for: ddr1_ecc_d[7:0], ddr1_dqm[3:0], ddr1_dqm_ecc, ddr1_dqs[3:0], ddr1_dqsn[3:0],
ddr1_dqs_ecc, ddr1_dqsn_ecc, ddr1_d[31:0].
NOTE
ECC is not available on this device, but signal names are retained for consistency with the
DRA7xx family of devices.
Terminal Configuration and Functions
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Copyright © 2016–2017, Texas Instruments Incorporated
11
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
NOTE
Dual rank support is not available on this device, but signal names are retained for
consistency with the DRA7xx family of devices.
12
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
K9
cap_vbbldo_dsp
cap_vbbldo_dsp
CAP
Y14
cap_vbbldo_gpu
cap_vbbldo_gpu
CAP
J10
cap_vbbldo_iva
cap_vbbldo_iva
CAP
J16
cap_vbbldo_mpu
cap_vbbldo_mpu
CAP
T20
cap_vddram_core1
cap_vddram_core1
CAP
L9
cap_vddram_core3
cap_vddram_core3
CAP
J19
cap_vddram_core4
cap_vddram_core4
CAP
J9
cap_vddram_dsp
cap_vddram_dsp
CAP
Y13
cap_vddram_gpu
cap_vddram_gpu
CAP
K16
cap_vddram_iva
cap_vddram_iva
CAP
K19
cap_vddram_mpu
cap_vddram_mpu
AE1
csi2_0_dx0
csi2_0_dx0
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AF1
csi2_0_dx1
csi2_0_dx1
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AF2
csi2_0_dx2
csi2_0_dx2
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AH4
csi2_0_dx3
csi2_0_dx3
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AH3
csi2_0_dx4
csi2_0_dx4
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AD2
csi2_0_dy0
csi2_0_dy0
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AE2
csi2_0_dy1
csi2_0_dy1
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AF3
csi2_0_dy2
csi2_0_dy2
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AG4
csi2_0_dy3
csi2_0_dy3
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AG3
csi2_0_dy4
csi2_0_dy4
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AG5
csi2_1_dx0
csi2_1_dx0
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AG6
csi2_1_dx1
csi2_1_dx1
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AH7
csi2_1_dx2
csi2_1_dx2
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AH5
csi2_1_dy0
csi2_1_dy0
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AH6
csi2_1_dy1
csi2_1_dy1
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
AG7
csi2_1_dy2
csi2_1_dy2
0
I
1.8
vdda_csi
Yes
LVCMOS
CSI2
PU/PD
DSIS [14]
CAP
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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13
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
G19
G20
BALL NAME [2]
dcan1_rx
dcan1_tx
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
dcan1_rx
0
IO
uart8_txd
2
O
mmc2_sdwp
3
I
sata1_led
4
O
hdmi1_cec
6
IO
gpio1_15
14
IO
Driver off
15
I
dcan1_tx
0
IO
uart8_rxd
2
I
mmc2_sdcd
3
I
hdmi1_hpd
6
IO
gpio1_14
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PU
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv3
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
1
0
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
AD20
ddr1_a0
ddr1_a0
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC19
ddr1_a1
ddr1_a1
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC20
ddr1_a2
ddr1_a2
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB19
ddr1_a3
ddr1_a3
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF21
ddr1_a4
ddr1_a4
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AH22
ddr1_a5
ddr1_a5
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG23
ddr1_a6
ddr1_a6
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE21
ddr1_a7
ddr1_a7
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF22
ddr1_a8
ddr1_a8
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE22
ddr1_a9
ddr1_a9
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AD21
ddr1_a10
ddr1_a10
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AD22
ddr1_a11
ddr1_a11
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC21
ddr1_a12
ddr1_a12
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF18
ddr1_a13
ddr1_a13
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE17
ddr1_a14
ddr1_a14
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
14
DSIS [14]
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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DRA722, DRA724, DRA725, DRA726
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
AD18
ddr1_a15
ddr1_a15
0
O
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF17
ddr1_ba0
ddr1_ba0
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE18
ddr1_ba1
ddr1_ba1
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB18
ddr1_ba2
ddr1_ba2
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC18
ddr1_casn
ddr1_casn
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG24
ddr1_ck
ddr1_ck
0
O
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG22
ddr1_cke
ddr1_cke
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AH23
ddr1_csn0
ddr1_csn0
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB16
ddr1_csn1
ddr1_csn1
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF25
ddr1_d0
ddr1_d0
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF26
ddr1_d1
ddr1_d1
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG26
ddr1_d2
ddr1_d2
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AH26
ddr1_d3
ddr1_d3
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF24
ddr1_d4
ddr1_d4
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE24
ddr1_d5
ddr1_d5
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF23
ddr1_d6
ddr1_d6
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE23
ddr1_d7
ddr1_d7
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC23
ddr1_d8
ddr1_d8
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF27
ddr1_d9
ddr1_d9
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG27
ddr1_d10
ddr1_d10
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF28
ddr1_d11
ddr1_d11
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE26
ddr1_d12
ddr1_d12
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC25
ddr1_d13
ddr1_d13
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
DSIS [14]
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
15
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
AC24
ddr1_d14
ddr1_d14
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AD25
ddr1_d15
ddr1_d15
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
V20
ddr1_d16
ddr1_d16
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
W20
ddr1_d17
ddr1_d17
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB28
ddr1_d18
ddr1_d18
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC28
ddr1_d19
ddr1_d19
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC27
ddr1_d20
ddr1_d20
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y19
ddr1_d21
ddr1_d21
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB27
ddr1_d22
ddr1_d22
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y20
ddr1_d23
ddr1_d23
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA23
ddr1_d24
ddr1_d24
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y22
ddr1_d25
ddr1_d25
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y23
ddr1_d26
ddr1_d26
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA24
ddr1_d27
ddr1_d27
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y24
ddr1_d28
ddr1_d28
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA26
ddr1_d29
ddr1_d29
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA25
ddr1_d30
ddr1_d30
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA28
ddr1_d31
ddr1_d31
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AD23
ddr1_dqm0
ddr1_dqm0
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AB23
ddr1_dqm1
ddr1_dqm1
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC26
ddr1_dqm2
ddr1_dqm2
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AA27
ddr1_dqm3
ddr1_dqm3
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
V26
ddr1_dqm_ecc
ddr1_dqm_ecc
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
16
Terminal Configuration and Functions
DSIS [14]
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
AH25
ddr1_dqs0
ddr1_dqs0
0
IO
PD
PD
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
AE27
ddr1_dqs1
ddr1_dqs1
0
IO
PD
PD
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
AD27
ddr1_dqs2
ddr1_dqs2
0
IO
PD
PD
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
Y28
ddr1_dqs3
ddr1_dqs3
0
IO
PD
PD
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
AG25
ddr1_dqsn0
ddr1_dqsn0
0
IO
PU
PU
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
AE28
ddr1_dqsn1
ddr1_dqsn1
0
IO
PU
PU
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
AD28
ddr1_dqsn2
ddr1_dqsn2
0
IO
PU
PU
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
Y27
ddr1_dqsn3
ddr1_dqsn3
0
IO
PU
PU
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
V28
ddr1_dqsn_ecc
ddr1_dqsn_ecc
0
IO
PU
PU
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
V27
ddr1_dqs_ecc
ddr1_dqs_ecc
0
IO
PD
PD
1.35/1.5
vdds_ddr1
NA
LVCMOS
DDR
PUx/PDy
W22
ddr1_ecc_d0
ddr1_ecc_d0
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
V23
ddr1_ecc_d1
ddr1_ecc_d1
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
W19
ddr1_ecc_d2
ddr1_ecc_d2
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
W23
ddr1_ecc_d3
ddr1_ecc_d3
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y25
ddr1_ecc_d4
ddr1_ecc_d4
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
V24
ddr1_ecc_d5
ddr1_ecc_d5
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
V25
ddr1_ecc_d6
ddr1_ecc_d6
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
Y26
ddr1_ecc_d7
ddr1_ecc_d7
0
IO
PD
PD
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AH24
ddr1_nck
ddr1_nck
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AE20
ddr1_odt0
ddr1_odt0
0
O
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AC17
ddr1_odt1
ddr1_odt1
0
O
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AF20
ddr1_rasn
ddr1_rasn
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
AG21
ddr1_rst
ddr1_rst
0
O
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
DSIS [14]
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Y18
ddr1_vref0
ddr1_vref0
0
PWR
OFF
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
NA
AH21
ddr1_wen
ddr1_wen
0
O
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
G21
emu0
emu0
0
IO
PU
PU
0
1.8/3.3
vddshv3
Yes
gpio8_30
14
IO
Dual Voltage PU/PD
LVCMOS
emu1
0
IO
PU
PU
0
1.8/3.3
vddshv3
Yes
gpio8_31
14
IO
Dual Voltage PU/PD
LVCMOS
gpio6_10
0
IO
PU
PU
15
1.8/3.3
vddshv7
Yes
mdio_mclk
1
O
Dual Voltage PU/PD
LVCMOS
i2c3_sda
2
IO
1
usb3_ulpi_d7
3
IO
0
vin2b_hsync1
4
I
vin1a_clk0
9
I
ehrpwm2A
10
O
gpio6_10
14
IO
Driver off
15
I
gpio6_11
0
IO
mdio_d
1
IO
i2c3_scl
2
IO
1
usb3_ulpi_d6
3
IO
0
vin2b_vsync1
4
I
vin1a_de0
9
I
ehrpwm2B
10
O
gpio6_11
14
IO
Driver off
15
I
gpio6_14
0
IO
mcasp1_axr8
1
IO
dcan2_tx
2
IO
1
uart10_rxd
3
I
1
vout2_hsync
6
O
vin2a_hsync0
vin1a_hsync0
8
I
i2c3_sda
9
IO
timer1
10
IO
gpio6_14
14
IO
Driver off
15
I
D24
AC5
AB4
E21
18
emu1
gpio6_10
gpio6_11
gpio6_14
1
0
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
PU
PU
15
Terminal Configuration and Functions
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
F20
F21
R6
BALL NAME [2]
gpio6_15
gpio6_16
gpmc_a0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PU
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv3
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
gpio6_15
0
IO
mcasp1_axr9
1
IO
dcan2_rx
2
IO
uart10_txd
3
O
vout2_vsync
6
O
vin2a_vsync0
vin1a_vsync0
8
I
i2c3_scl
9
IO
timer2
10
IO
gpio6_15
14
IO
Driver off
15
I
gpio6_16
0
IO
mcasp1_axr10
1
IO
vout2_fld
6
O
vin2a_fld0
vin1a_fld0
8
I
clkout1
9
O
timer3
10
IO
gpio6_16
14
IO
Driver off
15
I
gpmc_a0
0
O
vin1a_d16
2
I
vout3_d16
3
O
vin2a_d0
vin1a_d0
4
I
vin1b_d0
6
I
0
i2c4_scl
7
IO
1
uart5_rxd
8
I
1
gpio7_3
gpmc_a26
gpmc_a16
14
IO
Driver off
15
I
0
1
1
PU
PD
PU
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
T9
T6
T7
20
BALL NAME [2]
gpmc_a1
gpmc_a2
gpmc_a3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I
vout3_d17
3
O
vin2a_d1
vin1a_d1
4
I
vin1b_d1
6
I
0
i2c4_sda
7
IO
1
uart5_txd
8
O
gpio7_4
14
IO
Driver off
15
I
gpmc_a2
0
O
vin1a_d18
2
I
vout3_d18
3
O
vin2a_d2
vin1a_d2
4
I
vin1b_d2
6
I
0
uart7_rxd
7
I
1
uart5_ctsn
8
I
1
gpio7_5
14
IO
Driver off
15
I
gpmc_a3
0
O
qspi1_cs2
1
O
vin1a_d19
2
I
vout3_d19
3
O
vin2a_d3
vin1a_d3
4
I
vin1b_d3
6
I
uart7_txd
7
O
uart5_rtsn
8
O
gpio7_6
14
IO
Driver off
15
I
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
O
vddshv10
Yes
PULL
UP/DOWN
TYPE [13]
2
1.8/3.3
vddshv10
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
vin1a_d17
PD
15
POWER [10]
gpmc_a1
PD
PD
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
1
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
P6
R9
R5
BALL NAME [2]
gpmc_a4
gpmc_a5
gpmc_a6
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv10
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
gpmc_a4
0
O
qspi1_cs3
1
O
vin1a_d20
2
I
vout3_d20
3
O
vin2a_d4
vin1a_d4
4
I
vin1b_d4
6
I
0
i2c5_scl
7
IO
1
uart6_rxd
8
I
1
gpio1_26
14
IO
Driver off
15
I
gpmc_a5
0
O
vin1a_d21
2
I
vout3_d21
3
O
vin2a_d5
vin1a_d5
4
I
vin1b_d5
6
I
0
i2c5_sda
7
IO
1
uart6_txd
8
O
gpio1_27
14
IO
Driver off
15
I
gpmc_a6
0
O
vin1a_d22
2
I
vout3_d22
3
O
vin2a_d6
vin1a_d6
4
I
vin1b_d6
6
I
0
uart8_rxd
7
I
1
uart6_ctsn
8
I
1
gpio1_28
14
IO
Driver off
15
I
1
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
P5
N7
R4
N9
22
BALL NAME [2]
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_a10
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_a7
0
O
vin1a_d23
2
I
vout3_d23
3
O
vin2a_d7
vin1a_d7
4
I
vin1b_d7
6
I
uart8_txd
7
O
uart6_rtsn
8
O
gpio1_29
14
IO
Driver off
15
I
gpmc_a8
0
O
vin1a_hsync0
2
I
vout3_hsync
3
O
vin1b_hsync1
6
I
timer12
7
IO
spi4_sclk
8
IO
gpio1_30
14
IO
Driver off
15
I
gpmc_a9
0
O
vin1a_vsync0
2
I
vout3_vsync
3
O
vin1b_vsync1
6
I
timer11
7
IO
spi4_d1
8
IO
gpio1_31
14
IO
Driver off
15
I
gpmc_a10
0
O
vin1a_de0
2
I
vout3_de
3
O
vin1b_clk1
6
I
timer10
7
IO
spi4_d0
8
IO
gpio2_0
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv10
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
P9
P4
R3
T2
BALL NAME [2]
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv10
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
gpmc_a11
0
O
vin1a_fld0
2
I
vout3_fld
3
O
vin2a_fld0
vin1a_fld0
4
I
vin1b_de1
6
I
timer9
7
IO
spi4_cs0
8
IO
gpio2_1
14
IO
Driver off
15
I
gpmc_a12
0
O
vin2a_clk0
vin1a_clk0
4
I
gpmc_a0
5
O
vin1b_fld1
6
I
timer8
7
IO
spi4_cs1
8
IO
1
dma_evt1
9
I
0
gpio2_2
14
IO
Driver off
15
I
gpmc_a13
0
O
qspi1_rtclk
1
I
vin2a_hsync0
vin1a_hsync0
4
I
timer7
7
IO
spi4_cs2
8
IO
1
dma_evt2
9
I
0
gpio2_3
14
IO
Driver off
15
I
gpmc_a14
0
O
qspi1_d3
1
IO
vin2a_vsync0
vin1a_vsync0
4
I
timer6
7
IO
spi4_cs3
8
IO
gpio2_4
14
IO
Driver off
15
I
0
0
1
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
U2
U1
P3
R2
K7
24
BALL NAME [2]
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_a15
0
O
qspi1_d2
1
IO
vin2a_d8
vin1a_d8
4
I
timer5
7
IO
gpio2_5
14
IO
Driver off
15
I
gpmc_a16
0
O
qspi1_d0
1
IO
vin2a_d9
vin1a_d9
4
I
gpio2_6
14
IO
Driver off
15
I
gpmc_a17
0
O
qspi1_d1
1
IO
vin2a_d10
vin1a_d10
4
I
gpio2_7
14
IO
Driver off
15
I
gpmc_a18
0
O
qspi1_sclk
1
IO
vin2a_d11
vin1a_d11
4
I
gpio2_8
14
IO
Driver off
15
I
gpmc_a19
0
O
mmc2_dat4
1
IO
gpmc_a13
2
O
vin2a_d12
vin1a_d12
4
I
vin2b_d0
vin1b_d0
6
I
gpio2_9
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
PD
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
PD
PD
15
15
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
1.8/3.3
POWER [10]
vddshv10
vddshv10
vddshv10
HYS [11]
Yes
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
Terminal Configuration and Functions
DSIS [14]
0
0
0
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
M7
J5
K6
J7
BALL NAME [2]
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_a20
0
O
mmc2_dat5
1
IO
gpmc_a14
2
O
vin2a_d13
vin1a_d13
4
I
vin2b_d1
vin1b_d1
6
I
gpio2_10
14
IO
Driver off
15
I
gpmc_a21
0
O
mmc2_dat6
1
IO
gpmc_a15
2
O
vin2a_d14
vin1a_d14
4
I
vin2b_d2
vin1b_d2
6
I
gpio2_11
14
IO
Driver off
15
I
gpmc_a22
0
O
mmc2_dat7
1
IO
gpmc_a16
2
O
vin2a_d15
vin1a_d15
4
I
vin2b_d3
vin1b_d3
6
I
gpio2_12
14
IO
Driver off
15
I
gpmc_a23
0
O
mmc2_clk
1
IO
gpmc_a17
2
O
vin2a_fld0
vin1a_fld0
4
I
vin2b_d4
vin1b_d4
6
I
gpio2_13
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
PD
PD
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
PD
PD
PD
15
15
15
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
POWER [10]
vddshv11
vddshv11
vddshv11
vddshv11
HYS [11]
Yes
Yes
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
DSIS [14]
1
1
1
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
J4
J6
H4
H5
M6
26
BALL NAME [2]
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_ad0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_a24
0
O
mmc2_dat0
1
IO
gpmc_a18
2
O
vin1a_d8
4
I
vin2b_d5
vin1b_d5
6
I
gpio2_14
14
IO
Driver off
15
I
gpmc_a25
0
O
mmc2_dat1
1
IO
gpmc_a19
2
O
vin1a_d9
4
I
vin2b_d6
vin1b_d6
6
I
gpio2_15
14
IO
Driver off
15
I
gpmc_a26
0
O
mmc2_dat2
1
IO
gpmc_a20
2
O
vin1a_d10
4
I
vin2b_d7
vin1b_d7
6
I
gpio2_16
14
IO
Driver off
15
I
gpmc_a27
0
O
mmc2_dat3
1
IO
gpmc_a21
2
O
vin1a_d11
4
I
vin2b_hsync1
vin1b_hsync1
6
I
gpio2_17
14
IO
Driver off
15
I
gpmc_ad0
0
IO
vin1a_d0
2
I
vout3_d0
3
O
gpio1_6
14
IO
sysboot0
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv11
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
1
0
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
1
0
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
1
0
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
1
0
OFF
OFF
15
Terminal Configuration and Functions
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
M2
L5
M1
L6
L4
L3
L2
BALL NAME [2]
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_ad1
0
IO
vin1a_d1
2
I
vout3_d1
3
O
gpio1_7
14
IO
sysboot1
15
I
gpmc_ad2
0
IO
vin1a_d2
2
I
vout3_d2
3
O
gpio1_8
14
IO
sysboot2
15
I
gpmc_ad3
0
IO
vin1a_d3
2
I
vout3_d3
3
O
gpio1_9
14
IO
sysboot3
15
I
gpmc_ad4
0
IO
vin1a_d4
2
I
vout3_d4
3
O
gpio1_10
14
IO
sysboot4
15
I
gpmc_ad5
0
IO
vin1a_d5
2
I
vout3_d5
3
O
gpio1_11
14
IO
sysboot5
15
I
gpmc_ad6
0
IO
vin1a_d6
2
I
vout3_d6
3
O
gpio1_12
14
IO
sysboot6
15
I
gpmc_ad7
0
IO
vin1a_d7
2
I
vout3_d7
3
O
gpio1_13
14
IO
sysboot7
15
I
BALL
RESET
STATE [6]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
POWER [10]
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
HYS [11]
Yes
Yes
Yes
Yes
Yes
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
L1
K2
J1
J2
H1
J3
H2
28
BALL NAME [2]
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_ad8
0
IO
vin1a_d8
2
I
vout3_d8
3
O
gpio7_18
14
IO
sysboot8
15
I
gpmc_ad9
0
IO
vin1a_d9
2
I
vout3_d9
3
O
gpio7_19
14
IO
sysboot9
15
I
gpmc_ad10
0
IO
vin1a_d10
2
I
vout3_d10
3
O
gpio7_28
14
IO
sysboot10
15
I
gpmc_ad11
0
IO
vin1a_d11
2
I
vout3_d11
3
O
gpio7_29
14
IO
sysboot11
15
I
gpmc_ad12
0
IO
vin1a_d12
2
I
vout3_d12
3
O
gpio1_18
14
IO
sysboot12
15
I
gpmc_ad13
0
IO
vin1a_d13
2
I
vout3_d13
3
O
gpio1_19
14
IO
sysboot13
15
I
gpmc_ad14
0
IO
vin1a_d14
2
I
vout3_d14
3
O
gpio1_20
14
IO
sysboot14
15
I
BALL
RESET
STATE [6]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
Terminal Configuration and Functions
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
POWER [10]
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
HYS [11]
Yes
Yes
Yes
Yes
Yes
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
H3
N1
N6
M4
BALL NAME [2]
gpmc_ad15
gpmc_advn_ale
gpmc_ben0
gpmc_ben1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
OFF
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I
vout3_d15
3
O
gpio1_21
14
IO
sysboot15
15
I
gpmc_advn_ale
0
O
gpmc_cs6
1
O
clkout2
2
O
gpmc_wait1
3
I
vin2a_vsync0
vin1a_vsync0
4
I
gpmc_a2
5
O
gpmc_a23
6
O
timer3
7
IO
i2c3_sda
8
IO
1
dma_evt2
9
I
0
gpio2_23
gpmc_a19
14
IO
Driver off
15
I
gpmc_ben0
0
O
gpmc_cs4
1
O
vin2b_de1
vin1b_de1
6
I
timer2
7
IO
dma_evt3
9
I
gpio2_26
gpmc_a21
14
IO
Driver off
15
I
gpmc_ben1
0
O
gpmc_cs5
1
O
vin2b_clk1
vin1b_clk1
4
I
gpmc_a3
5
O
vin2b_fld1
vin1b_fld1
6
I
timer1
7
IO
dma_evt4
9
I
gpio2_27
gpmc_a22
14
IO
Driver off
15
I
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
IO
vddshv10
Yes
PULL
UP/DOWN
TYPE [13]
2
1.8/3.3
vddshv10
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
vin1a_d15
PU
15
POWER [10]
gpmc_ad15
PU
OFF
I/O
VOLTAGE
VALUE [9]
0
0
Dual Voltage PU/PD
LVCMOS
1
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
P7
T1
H6
P2
30
BALL NAME [2]
gpmc_clk
gpmc_cs0
gpmc_cs1
gpmc_cs2
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PU
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv10
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
gpmc_clk
0
IO
gpmc_cs7
1
O
0
clkout1
2
O
gpmc_wait1
3
I
vin2a_hsync0
vin1a_hsync0
4
I
vin2a_de0
vin1a_de0
5
I
vin2b_clk1
vin1b_clk1
6
I
timer4
7
IO
i2c3_scl
8
IO
1
dma_evt1
9
I
0
gpio2_22
gpmc_a20
14
IO
Driver off
15
I
gpmc_cs0
0
O
gpio2_19
14
IO
Driver off
15
I
gpmc_cs1
0
O
mmc2_cmd
1
IO
gpmc_a22
2
O
vin2a_de0
vin1a_de0
4
I
vin2b_vsync1
vin1b_vsync1
6
I
gpio2_18
14
IO
Driver off
15
I
gpmc_cs2
0
O
qspi1_cs0
1
IO
gpio2_20
gpmc_a23
gpmc_a13
14
IO
Driver off
15
I
1
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
PU
PU
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
PU
PU
15
Terminal Configuration and Functions
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
P1
M5
N2
M3
BALL NAME [2]
gpmc_cs3
gpmc_oen_ren
gpmc_wait0
gpmc_wen
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
gpmc_cs3
0
O
qspi1_cs1
1
O
vin1a_clk0
2
I
vout3_clk
3
O
gpmc_a1
5
O
gpio2_21
gpmc_a24
gpmc_a14
14
IO
Driver off
15
I
gpmc_oen_ren
0
O
gpio2_24
14
IO
Driver off
15
I
gpmc_wait0
0
I
gpio2_28
gpmc_a25
gpmc_a15
14
IO
Driver off
15
I
gpmc_wen
0
O
gpio2_25
14
IO
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PU
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv10
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
1
0
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
Driver off
15
I
AG16
hdmi1_clockx
hdmi1_clockx
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AH16
hdmi1_clocky
hdmi1_clocky
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AG17
hdmi1_data0x
hdmi1_data0x
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AH17
hdmi1_data0y
hdmi1_data0y
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AG18
hdmi1_data1x
hdmi1_data1x
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AH18
hdmi1_data1y
hdmi1_data1y
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AG19
hdmi1_data2x
hdmi1_data2x
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
AH19
hdmi1_data2y
hdmi1_data2y
0
O
1.8
vdda_hdmi
NA
HDMIPHY
Pdy
C20
i2c1_scl
i2c1_scl
0
IO
1.8/3.3
vddshv3
Yes
Driver off
15
I
Dual Voltage PU/PD
LVCMOS I2C
C21
i2c1_sda
i2c1_sda
0
IO
1.8/3.3
vddshv3
Yes
Driver off
15
I
Dual Voltage PU/PD
LVCMOS I2C
i2c2_scl
0
IO
15
1.8/3.3
vddshv3
Yes
1
IO
Dual Voltage PU/PD
LVCMOS I2C
1
hdmi1_ddc_sda
Driver off
15
I
i2c2_sda
0
IO
15
1.8/3.3
vddshv3
Yes
1
IO
Dual Voltage PU/PD
LVCMOS I2C
1
hdmi1_ddc_scl
Driver off
15
I
ljcb_clkn
0
IO
1.8
vdda_pcie
NA
LJCB
F17
C25
AH15
i2c2_scl
i2c2_sda
ljcb_clkn
NA
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
AG15
ljcb_clkp
ljcb_clkp
0
IO
B14
mcasp1_aclkr
mcasp1_aclkr
0
IO
mcasp7_axr2
1
IO
vout2_d0
6
O
vin2a_d0
vin1a_d0
8
I
i2c4_sda
10
IO
gpio5_0
14
IO
Driver off
15
I
mcasp1_aclkx
0
IO
vin1a_fld0
7
I
i2c3_sda
10
IO
gpio7_31
14
IO
Driver off
15
I
mcasp1_axr0
0
IO
uart6_rxd
3
I
vin1a_vsync0
7
I
0
i2c5_sda
10
IO
1
gpio5_2
14
IO
Driver off
15
I
mcasp1_axr1
0
IO
uart6_txd
3
O
vin1a_hsync0
7
I
0
i2c5_scl
10
IO
1
gpio5_3
14
IO
Driver off
15
I
mcasp1_axr2
0
IO
mcasp6_axr2
1
IO
uart6_ctsn
3
I
vout2_d2
6
O
vin2a_d2
vin1a_d2
8
I
gpio5_4
14
IO
Driver off
15
I
C14
G12
F12
G13
32
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
PD
PD
15
1.8
vdda_pcie
NA
LJCB
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
NA
0
0
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
PD
PD
PD
PD
PD
PD
15
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
1
0
0
0
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
J11
E12
F13
C12
D12
BALL NAME [2]
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
mcasp1_axr3
0
IO
mcasp6_axr3
1
IO
uart6_rtsn
3
O
vout2_d3
6
O
vin2a_d3
vin1a_d3
8
I
gpio5_5
14
IO
Driver off
15
I
mcasp1_axr4
0
IO
mcasp4_axr2
1
IO
vout2_d4
6
O
vin2a_d4
vin1a_d4
8
I
gpio5_6
14
IO
Driver off
15
I
mcasp1_axr5
0
IO
mcasp4_axr3
1
IO
vout2_d5
6
O
vin2a_d5
vin1a_d5
8
I
gpio5_7
14
IO
Driver off
15
I
mcasp1_axr6
0
IO
mcasp5_axr2
1
IO
vout2_d6
6
O
vin2a_d6
vin1a_d6
8
I
gpio5_8
14
IO
Driver off
15
I
mcasp1_axr7
0
IO
mcasp5_axr3
1
IO
vout2_d7
6
O
vin2a_d7
vin1a_d7
8
I
timer4
10
IO
gpio5_9
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
PD
PD
PD
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
PD
PD
PD
PD
15
15
15
15
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
POWER [10]
vddshv3
vddshv3
vddshv3
vddshv3
vddshv3
HYS [11]
Yes
Yes
Yes
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B12
A11
B13
A12
E14
34
BALL NAME [2]
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
IO
spi3_sclk
3
IO
0
vin1a_d15
7
I
0
timer5
10
IO
gpio5_10
14
IO
Driver off
15
I
mcasp1_axr9
0
IO
mcasp6_axr1
1
IO
spi3_d1
3
IO
0
vin1a_d14
7
I
0
timer6
10
IO
gpio5_11
14
IO
Driver off
15
I
mcasp1_axr10
0
IO
mcasp6_aclkx
1
IO
mcasp6_aclkr
2
IO
spi3_d0
3
IO
0
vin1a_d13
7
I
0
timer7
10
IO
gpio5_12
14
IO
Driver off
15
I
mcasp1_axr11
0
IO
mcasp6_fsx
1
IO
mcasp6_fsr
2
IO
spi3_cs0
3
IO
1
vin1a_d12
7
I
0
timer8
10
IO
gpio4_17
14
IO
Driver off
15
I
mcasp1_axr12
0
IO
mcasp7_axr0
1
IO
spi3_cs1
3
IO
1
vin1a_d11
7
I
0
timer9
10
IO
gpio4_18
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
15
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
IO
vddshv3
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv3
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
mcasp6_axr0
PD
15
POWER [10]
mcasp1_axr8
PD
PD
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
0
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
A13
G14
F14
J14
D14
BALL NAME [2]
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_fsr
mcasp1_fsx
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
mcasp1_axr13
0
IO
mcasp7_axr1
1
IO
vin1a_d10
7
I
timer10
10
IO
gpio6_4
14
IO
Driver off
15
I
mcasp1_axr14
0
IO
mcasp7_aclkx
1
IO
mcasp7_aclkr
2
IO
vin1a_d9
7
I
timer11
10
IO
gpio6_5
14
IO
Driver off
15
I
mcasp1_axr15
0
IO
mcasp7_fsx
1
IO
mcasp7_fsr
2
IO
vin1a_d8
7
I
timer12
10
IO
gpio6_6
14
IO
Driver off
15
I
mcasp1_fsr
0
IO
mcasp7_axr3
1
IO
vout2_d1
6
O
vin2a_d1
vin1a_d1
8
I
i2c4_scl
10
IO
gpio5_1
14
IO
Driver off
15
I
mcasp1_fsx
0
IO
vin1a_de0
7
I
i2c3_scl
10
IO
gpio7_30
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv3
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
E15
A19
B15
A15
C15
A16
D15
36
BALL NAME [2]
mcasp2_aclkr
mcasp2_aclkx
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
mcasp2_aclkr
0
IO
mcasp8_axr2
1
IO
vout2_d8
6
O
vin2a_d8
vin1a_d8
8
I
Driver off
15
I
mcasp2_aclkx
0
IO
vin1a_d7
7
I
Driver off
15
I
mcasp2_axr0
0
IO
vout2_d10
6
O
vin2a_d10
vin1a_d10
8
I
Driver off
15
I
mcasp2_axr1
0
IO
vout2_d11
6
O
vin2a_d11
vin1a_d11
8
I
Driver off
15
I
mcasp2_axr2
0
IO
mcasp3_axr2
1
IO
vin1a_d5
7
I
gpio6_8
14
IO
Driver off
15
I
mcasp2_axr3
0
IO
mcasp3_axr3
1
IO
vin1a_d4
7
I
gpio6_9
14
IO
Driver off
15
I
mcasp2_axr4
0
IO
mcasp8_axr0
1
IO
vout2_d12
6
O
vin2a_d12
vin1a_d12
8
I
gpio1_4
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
PD
15
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
1.8/3.3
POWER [10]
vddshv3
vddshv3
HYS [11]
Yes
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B16
B17
A17
A20
A18
B18
BALL NAME [2]
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_fsr
mcasp2_fsx
mcasp3_aclkx
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
IO
IO
vout2_d13
6
O
vin2a_d13
vin1a_d13
8
I
gpio6_7
14
IO
Driver off
15
I
mcasp2_axr6
0
IO
mcasp8_aclkx
1
IO
mcasp8_aclkr
2
IO
vout2_d14
6
O
vin2a_d14
vin1a_d14
8
I
gpio2_29
14
IO
Driver off
15
I
mcasp2_axr7
0
IO
mcasp8_fsx
1
IO
mcasp8_fsr
2
IO
vout2_d15
6
O
vin2a_d15
vin1a_d15
8
I
gpio1_5
14
IO
Driver off
15
I
mcasp2_fsr
0
IO
mcasp8_axr3
1
IO
vout2_d9
6
O
vin2a_d9
vin1a_d9
8
I
Driver off
15
I
mcasp2_fsx
0
IO
vin1a_d6
7
I
Driver off
15
I
mcasp3_aclkx
0
IO
mcasp3_aclkr
1
IO
mcasp2_axr12
2
IO
0
uart7_rxd
3
I
1
vin1a_d3
7
I
0
gpio5_13
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv3
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
mcasp8_axr1
PD
15
POWER [10]
mcasp2_axr5
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B19
C17
F15
C18
38
BALL NAME [2]
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mcasp4_aclkx
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
IO
uart7_ctsn
3
I
1
uart5_rxd
4
I
1
vin1a_d1
7
I
0
Driver off
15
I
mcasp3_axr1
0
IO
mcasp2_axr15
2
IO
uart7_rtsn
3
O
uart5_txd
4
O
vin1a_d0
7
I
0
vin1a_fld0
9
I
0
Driver off
15
I
mcasp3_fsx
0
IO
mcasp3_fsr
1
IO
mcasp2_axr13
2
IO
uart7_txd
3
O
vin1a_d2
7
I
gpio5_14
14
IO
Driver off
15
I
mcasp4_aclkx
0
IO
mcasp4_aclkr
1
IO
spi3_sclk
2
IO
0
uart8_rxd
3
I
1
i2c4_sda
4
IO
1
vout2_d16
6
O
vin2a_d16
vin1a_d16
8
I
vin1a_d15
9
I
Driver off
15
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
IO
vddshv3
Yes
PULL
UP/DOWN
TYPE [13]
2
1.8/3.3
vddshv3
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
mcasp2_axr14
PD
15
POWER [10]
mcasp3_axr0
PD
PD
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
0
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
G16
D17
A21
BALL NAME [2]
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv3
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
mcasp4_axr0
0
IO
spi3_d0
2
IO
0
uart8_ctsn
3
I
1
uart4_rxd
4
I
1
vout2_d18
6
O
vin2a_d18
vin1a_d18
8
I
vin1a_d13
9
I
i2c6_scl
14
IO
Driver off
15
I
mcasp4_axr1
0
IO
spi3_cs0
2
IO
uart8_rtsn
3
O
uart4_txd
4
O
vout2_d19
6
O
vin2a_d19
vin1a_d19
8
I
vin1a_d12
9
I
i2c6_sda
14
IO
Driver off
15
I
mcasp4_fsx
0
IO
mcasp4_fsr
1
IO
spi3_d1
2
IO
uart8_txd
3
O
i2c4_scl
4
IO
vout2_d17
6
O
vin2a_d17
vin1a_d17
8
I
vin1a_d14
9
I
Driver off
15
I
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
1
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AA3
AB3
AA4
40
BALL NAME [2]
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv7
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
mcasp5_aclkx
0
IO
mcasp5_aclkr
1
IO
0
spi4_sclk
2
IO
0
uart9_rxd
3
I
1
i2c5_sda
4
IO
1
mlb_clk
5
I
1
vout2_d20
6
O
vin2a_d20
vin1a_d20
8
I
vin1a_d11
9
I
Driver off
15
I
mcasp5_axr0
0
IO
spi4_d0
2
IO
uart9_ctsn
3
I
1
uart3_rxd
4
I
1
mlb_sig
5
IO
1
vout2_d22
6
O
vin2a_d22
vin1a_d22
8
I
vin1a_d9
9
I
Driver off
15
I
mcasp5_axr1
0
IO
spi4_cs0
2
IO
uart9_rtsn
3
O
uart3_txd
4
O
mlb_dat
5
IO
vout2_d23
6
O
vin2a_d23
vin1a_d23
8
I
vin1a_d8
9
I
Driver off
15
I
0
PD
PD
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AB9
U4
V1
BALL NAME [2]
mcasp5_fsx
mdio_d
mdio_mclk
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv7
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
mcasp5_fsx
0
IO
mcasp5_fsr
1
IO
0
spi4_d1
2
IO
uart9_txd
3
O
i2c5_scl
4
IO
vout2_d21
6
O
vin2a_d21
vin1a_d21
8
I
vin1a_d10
9
I
Driver off
15
I
mdio_d
0
IO
uart3_ctsn
1
I
mii0_txer
3
O
0
vin2a_d0
4
I
0
vin1b_d0
5
I
0
gpio5_16
14
IO
Driver off
15
I
mdio_mclk
0
O
uart3_rtsn
1
O
mii0_col
3
I
vin2a_clk0
4
I
vin1b_clk1
5
I
gpio5_15
14
IO
0
1
0
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv9
vddshv9
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
1
1
0
0
Driver off
15
I
AB2
mlbp_clk_n
mlbp_clk_n
0
I
vdds_mlbp
No
BMLB18
NA
AB1
mlbp_clk_p
mlbp_clk_p
0
I
vdds_mlbp
No
BMLB18
NA
AA2
mlbp_dat_n
mlbp_dat_n
0
IO
OFF
OFF
vdds_mlbp
No
BMLB18
NA
AA1
mlbp_dat_p
mlbp_dat_p
0
IO
OFF
OFF
vdds_mlbp
No
BMLB18
NA
AC2
mlbp_sig_n
mlbp_sig_n
0
IO
OFF
OFF
vdds_mlbp
No
BMLB18
NA
AC1
mlbp_sig_p
mlbp_sig_p
0
IO
OFF
OFF
vdds_mlbp
No
BMLB18
NA
W6
mmc1_clk
mmc1_clk
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
1
gpio6_21
14
IO
SDIO2KV183 Pux/PDy
3
Driver off
15
I
mmc1_cmd
0
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
14
IO
SDIO2KV183 Pux/PDy
3
1
gpio6_22
Driver off
15
I
Y6
mmc1_cmd
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AA6
Y4
AA5
Y3
W7
Y9
AD4
AC4
42
BALL NAME [2]
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_sdwp
mmc3_clk
mmc3_cmd
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
mmc1_dat0
0
IO
gpio6_23
14
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO2KV183 Pux/PDy
3
1
Driver off
15
I
mmc1_dat1
0
IO
gpio6_24
14
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO2KV183 Pux/PDy
3
1
Driver off
15
I
mmc1_dat2
0
IO
gpio6_25
14
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO2KV183 Pux/PDy
3
1
Driver off
15
I
mmc1_dat3
0
IO
gpio6_26
14
IO
PU
PU
15
1.8/3.3
vddshv8
Yes
SDIO2KV183 Pux/PDy
3
1
Driver off
15
I
mmc1_sdcd
0
I
uart6_rxd
3
I
PU
PU
15
1.8/3.3
vddshv8
Yes
Dual Voltage PU/PD
LVCMOS
1
i2c4_sda
4
IO
gpio6_27
14
IO
Driver off
15
I
mmc1_sdwp
0
I
uart6_txd
3
O
i2c4_scl
4
IO
gpio6_28
14
IO
Driver off
15
I
mmc3_clk
0
IO
usb3_ulpi_d5
3
IO
vin2b_d7
4
I
0
vin1a_d7
9
I
0
ehrpwm2_tripzone_input
10
IO
0
gpio6_29
14
IO
Driver off
15
I
mmc3_cmd
0
IO
spi3_sclk
1
IO
usb3_ulpi_d4
3
IO
0
vin2b_d6
4
I
0
vin1a_d6
9
I
0
eCAP2_in_PWM2_out
10
IO
0
gpio6_30
14
IO
Driver off
15
I
1
1
PD
PD
15
1.8/3.3
vddshv8
Yes
Dual Voltage PU/PD
LVCMOS
0
1
PU
PU
PU
PU
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
vddshv7
vddshv7
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
0
1
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AC7
AC6
AC9
AC3
BALL NAME [2]
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
IO
uart5_rxd
2
I
1
usb3_ulpi_d3
3
IO
0
vin2b_d5
4
I
0
vin1a_d5
9
I
0
eQEP3A_in
10
I
0
gpio6_31
14
IO
Driver off
15
I
mmc3_dat1
0
IO
spi3_d0
1
IO
uart5_txd
2
O
usb3_ulpi_d2
3
IO
0
vin2b_d4
4
I
0
vin1a_d4
9
I
0
eQEP3B_in
10
I
0
gpio7_0
14
IO
Driver off
15
I
mmc3_dat2
0
IO
spi3_cs0
1
IO
uart5_ctsn
2
I
1
usb3_ulpi_d1
3
IO
0
vin2b_d3
4
I
0
vin1a_d3
9
I
0
eQEP3_index
10
IO
0
gpio7_1
14
IO
Driver off
15
I
mmc3_dat3
0
IO
spi3_cs1
1
IO
uart5_rtsn
2
O
usb3_ulpi_d0
3
IO
0
vin2b_d2
4
I
0
vin1a_d2
9
I
0
eQEP3_strobe
10
IO
0
gpio7_2
14
IO
Driver off
15
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv7
vddshv7
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
IO
vddshv7
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv7
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
spi3_d1
PU
15
POWER [10]
mmc3_dat0
PU
PU
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
0
1
0
1
1
1
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AC8
AD6
AB8
AB5
D21
44
BALL NAME [2]
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
nmin_dsp
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
IO
uart10_rxd
2
I
1
usb3_ulpi_nxt
3
I
0
vin2b_d1
4
I
0
vin1a_d1
9
I
0
ehrpwm3A
10
O
gpio1_22
14
IO
Driver off
15
I
mmc3_dat5
0
IO
spi4_d1
1
IO
uart10_txd
2
O
usb3_ulpi_dir
3
I
0
vin2b_d0
4
I
0
vin1a_d0
9
I
0
ehrpwm3B
10
O
gpio1_23
14
IO
Driver off
15
I
mmc3_dat6
0
IO
spi4_d0
1
IO
uart10_ctsn
2
I
usb3_ulpi_stp
3
O
vin2b_de1
4
I
vin1a_hsync0
9
I
0
ehrpwm3_tripzone_input
10
IO
0
gpio1_24
14
IO
Driver off
15
I
mmc3_dat7
0
IO
spi4_cs0
1
IO
uart10_rtsn
2
O
usb3_ulpi_clk
3
I
vin2b_clk1
4
I
vin1a_vsync0
9
I
0
eCAP3_in_PWM3_out
10
IO
0
gpio1_25
14
IO
Driver off
15
I
nmin_dsp
0
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
IO
vddshv7
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv7
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
spi4_sclk
PU
15
POWER [10]
mmc3_dat4
PU
PU
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
0
1
0
1
0
1
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
PD
PD
Terminal Configuration and Functions
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Y11
on_off
on_off
0
O
PU
drive 1 (OFF)
1.8/3.3
vddshv5
Yes
BC1833IHHV PU/PD
AG13
pcie_rxn0
pcie_rxn0
0
I
OFF
OFF
1.8
vdda_pcie0
NA
SERDES
NA
AH13
pcie_rxp0
pcie_rxp0
0
I
OFF
OFF
1.8
vdda_pcie0
NA
SERDES
NA
AG14
pcie_txn0
pcie_txn0
0
O
1.8
vdda_pcie0
NA
SERDES
NA
AH14
pcie_txp0
pcie_txp0
0
O
1.8
vdda_pcie0
NA
SERDES
NA
F22
porz
porz
0
I
1.8/3.3
vddshv3
Yes
IHHV1833
PU/PD
E23
resetn
resetn
0
I
PU
PU
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
U5
rgmii0_rxc
rgmii0_rxc
0
I
PD
PD
1.8/3.3
vddshv9
Yes
rmii1_txen
2
O
Dual Voltage PU/PD
LVCMOS
mii0_txclk
3
I
0
vin2a_d5
4
I
0
vin1b_d5
5
I
0
usb3_ulpi_d2
6
IO
0
gpio5_26
14
IO
Driver off
15
I
rgmii0_rxctl
0
I
rmii1_txd1
2
O
mii0_txd3
3
O
vin2a_d6
4
I
0
vin1b_d6
5
I
0
usb3_ulpi_d3
6
IO
0
gpio5_27
14
IO
Driver off
15
I
rgmii0_rxd0
0
I
rmii0_txd0
1
O
mii0_txd0
3
O
vin2a_fld0
4
I
vin1b_fld1
5
I
0
usb3_ulpi_d7
6
IO
0
gpio5_31
14
IO
Driver off
15
I
V5
W2
rgmii0_rxctl
rgmii0_rxd0
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
vddshv9
vddshv9
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
Y2
V3
V4
W9
46
BALL NAME [2]
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
O
mii0_txd1
3
O
vin2a_d9
4
I
0
usb3_ulpi_d6
6
IO
0
gpio5_30
14
IO
Driver off
15
I
rgmii0_rxd2
0
I
rmii0_txen
1
O
mii0_txen
3
O
vin2a_d8
4
I
0
usb3_ulpi_d5
6
IO
0
gpio5_29
14
IO
Driver off
15
I
rgmii0_rxd3
0
I
rmii1_txd0
2
O
mii0_txd2
3
O
vin2a_d7
4
I
0
vin1b_d7
5
I
0
usb3_ulpi_d4
6
IO
0
gpio5_28
14
IO
Driver off
15
I
rgmii0_txc
0
O
uart3_ctsn
1
I
rmii1_rxd1
2
I
0
mii0_rxd3
3
I
0
vin2a_d3
4
I
0
vin1b_d3
5
I
0
usb3_ulpi_clk
6
I
0
spi3_d0
7
IO
0
spi4_cs2
8
IO
1
gpio5_20
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
vddshv9
vddshv9
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
I
vddshv9
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv9
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
rmii0_txd1
PD
15
POWER [10]
rgmii0_rxd1
PD
PD
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
V9
U6
V6
BALL NAME [2]
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
O
O
rmii1_rxd0
2
I
0
mii0_rxd2
3
I
0
vin2a_d4
4
I
0
vin1b_d4
5
I
0
usb3_ulpi_stp
6
O
spi3_cs0
7
IO
1
spi4_cs3
8
IO
1
gpio5_21
14
IO
Driver off
15
I
rgmii0_txd0
0
O
rmii0_rxd0
1
I
mii0_rxd0
3
I
0
vin2a_d10
4
I
0
usb3_ulpi_d1
6
IO
0
spi4_cs0
7
IO
1
uart4_rtsn
8
O
gpio5_25
14
IO
Driver off
15
I
rgmii0_txd1
0
O
rmii0_rxd1
1
I
mii0_rxd1
3
I
vin2a_vsync0
4
I
vin1b_vsync1
5
I
0
usb3_ulpi_d0
6
IO
0
spi4_d0
7
IO
0
uart4_ctsn
8
IO
1
gpio5_24
14
IO
Driver off
15
I
PD
PD
15
1.8/3.3
vddshv9
vddshv9
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv9
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
uart3_rtsn
PD
15
POWER [10]
rgmii0_txctl
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
Terminal Configuration and Functions
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
U7
V7
U3
BALL NAME [2]
rgmii0_txd2
rgmii0_txd3
RMII_MHZ_50_CLK
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv9
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
rgmii0_txd2
0
O
rmii0_rxer
1
I
mii0_rxer
3
I
vin2a_hsync0
4
I
vin1b_hsync1
5
I
0
usb3_ulpi_nxt
6
I
0
spi4_d1
7
IO
0
uart4_txd
8
O
gpio5_23
14
IO
Driver off
15
I
rgmii0_txd3
0
O
rmii0_crs
1
I
mii0_crs
3
I
vin2a_de0
4
I
vin1b_de1
5
I
0
usb3_ulpi_dir
6
I
0
spi4_sclk
7
IO
0
uart4_rxd
8
I
1
gpio5_22
14
IO
Driver off
15
I
RMII_MHZ_50_CLK
0
IO
vin2a_d11
4
I
gpio5_17
14
IO
0
0
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
0
PD
PD
Driver off
15
I
F23
rstoutn
rstoutn
0
O
PD
PD
E18
rtck
rtck
0
O
PU
OFF
gpio8_29
14
IO
15
0
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
AF14
rtc_iso
rtc_iso
0
I
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
AE14
rtc_osc_xi_clkin32
rtc_osc_xi_clkin32
0
I
1.8
vdda_rtc
No
LVCMOS
OSC
NA
AD14
rtc_osc_xo
rtc_osc_xo
0
O
1.8
vdda_rtc
No
LVCMOS
OSC
NA
AB17
rtc_porz
rtc_porz
0
I
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
AH9
sata1_rxn0
sata1_rxn0
0
I
OFF
OFF
1.8
vdda_sata
NA
SATAPHY
NA
AG9
sata1_rxp0
sata1_rxp0
0
I
OFF
OFF
1.8
vdda_sata
NA
SATAPHY
NA
AG10
sata1_txn0
sata1_txn0
0
O
1.8
vdda_sata
NA
SATAPHY
NA
AH10
sata1_txp0
sata1_txp0
0
O
1.8
vdda_sata
NA
SATAPHY
NA
48
DSIS [14]
Terminal Configuration and Functions
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
A24
A22
B21
B20
B25
F16
A25
BALL NAME [2]
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
spi1_d0
spi1_d1
spi1_sclk
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
spi1_cs0
0
IO
gpio7_10
14
IO
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
Driver off
15
I
spi1_cs1
0
IO
sata1_led
2
O
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
spi2_cs1
3
IO
gpio7_11
14
IO
Driver off
15
I
spi1_cs2
0
IO
uart4_rxd
1
I
mmc3_sdcd
2
I
1
spi2_cs2
3
IO
1
dcan2_tx
4
IO
1
mdio_mclk
5
O
1
hdmi1_hpd
6
IO
gpio7_12
14
IO
Driver off
15
I
spi1_cs3
0
IO
uart4_txd
1
O
mmc3_sdwp
2
I
0
spi2_cs3
3
IO
1
dcan2_rx
4
IO
1
mdio_d
5
IO
1
hdmi1_cec
6
IO
gpio7_13
14
IO
Driver off
15
I
spi1_d0
0
IO
gpio7_9
14
IO
Driver off
15
I
spi1_d1
0
IO
gpio7_8
14
IO
Driver off
15
I
spi1_sclk
0
IO
gpio7_7
14
IO
Driver off
15
I
1
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
1
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B24
G17
B22
A26
BALL NAME [2]
spi2_cs0
spi2_d0
spi2_d1
spi2_sclk
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
spi2_cs0
0
IO
uart3_rtsn
1
O
uart5_txd
2
O
gpio7_17
14
IO
Driver off
15
I
spi2_d0
0
IO
uart3_ctsn
1
I
uart5_rxd
2
I
gpio7_16
14
IO
Driver off
15
I
spi2_d1
0
IO
uart3_txd
1
O
gpio7_15
14
IO
Driver off
15
I
spi2_sclk
0
IO
uart3_rxd
1
I
gpio7_14
14
IO
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
Driver off
15
I
tclk
tclk
0
I
PU
PU
0
1.8/3.3
vddshv3
Yes
IQ1833
D23
tdi
tdi
0
I
PU
PU
0
1.8/3.3
vddshv3
Yes
gpio8_27
14
I
Dual Voltage PU/PD
LVCMOS
F19
tdo
tdo
0
O
PU
PU
0
1.8/3.3
vddshv3
Yes
gpio8_28
14
IO
Dual Voltage PU/PD
LVCMOS
0
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
F18
tms
tms
0
I
PU
PU
D20
trstn
trstn
0
I
PD
PD
E25
uart1_ctsn
uart1_ctsn
0
I
PU
PU
uart9_rxd
2
I
mmc4_clk
3
IO
gpio7_24
14
IO
Driver off
15
I
uart1_rtsn
0
O
uart9_txd
2
O
mmc4_cmd
3
IO
gpio7_25
14
IO
Driver off
15
I
50
uart1_rtsn
1
1
E20
C27
DSIS [14]
15
1
PU/PD
1
1
1
PU
PU
15
Terminal Configuration and Functions
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
1
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B27
C26
D27
C28
D28
BALL NAME [2]
uart1_rxd
uart1_txd
uart2_ctsn
uart2_rtsn
uart2_rxd
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I
gpio7_22
14
IO
Driver off
15
I
uart1_txd
0
O
mmc4_sdwp
3
I
gpio7_23
14
IO
Driver off
15
I
uart2_ctsn
0
I
uart3_rxd
2
I
mmc4_dat2
3
IO
1
uart10_rxd
4
I
1
uart1_dtrn
5
O
gpio1_16
14
IO
Driver off
15
I
uart2_rtsn
0
O
uart3_txd
1
O
uart3_irtx
2
O
mmc4_dat3
3
IO
uart10_txd
4
O
uart1_rin
5
I
gpio1_17
14
IO
Driver off
15
I
uart2_rxd
0
I
uart3_ctsn
1
I
uart3_rctx
2
O
mmc4_dat0
3
IO
1
uart2_rxd
4
I
1
uart1_dcdn
5
I
1
gpio7_26
14
IO
Driver off
15
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv4
vddshv4
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
I
vddshv4
Yes
PULL
UP/DOWN
TYPE [13]
3
1.8/3.3
vddshv4
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
mmc4_sdcd
PU
15
POWER [10]
uart1_rxd
PU
PU
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
1
0
1
1
Dual Voltage PU/PD
LVCMOS
1
1
PU
PU
15
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
1
1
Terminal Configuration and Functions
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
D26
V2
Y1
BALL NAME [2]
uart2_txd
uart3_rxd
uart3_txd
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PU
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PU
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv4
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
uart2_txd
0
O
uart3_rtsn
1
O
Dual Voltage PU/PD
LVCMOS
uart3_sd
2
O
mmc4_dat1
3
IO
uart2_txd
4
O
uart1_dsrn
5
I
gpio7_27
14
IO
Driver off
15
I
uart3_rxd
0
I
rmii1_crs
2
I
mii0_rxdv
3
I
0
vin2a_d1
4
I
0
vin1b_d1
5
I
0
spi3_sclk
7
IO
0
gpio5_18
14
IO
Driver off
15
I
uart3_txd
0
O
rmii1_rxer
2
I
mii0_rxclk
3
I
0
vin2a_d2
4
I
0
vin1b_d2
5
I
0
spi3_d1
7
IO
0
spi4_cs1
8
IO
1
gpio5_19
14
IO
1
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv9
vddshv9
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Driver off
15
I
AC12
usb1_dm
usb1_dm
0
IO
OFF
OFF
3.3
vdda33v_usb NA
1
USBPHY
NA
AD12
usb1_dp
usb1_dp
0
IO
OFF
OFF
3.3
vdda33v_usb NA
1
USBPHY
NA
AB10
usb1_drvvbus
usb1_drvvbus
0
O
PD
PD
1.8/3.3
vddshv6
timer16
7
IO
Dual Voltage PU/PD
LVCMOS
gpio6_12
14
IO
Driver off
15
I
15
Yes
AF11
usb2_dm
usb2_dm
0
IO
3.3
vdda33v_usb No
2
USBPHY
NA
AE11
usb2_dp
usb2_dp
0
IO
3.3
vdda33v_usb No
2
USBPHY
NA
52
DSIS [14]
Terminal Configuration and Functions
1
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
AC10
AF12
AE12
AC11
AD11
BALL NAME [2]
usb2_drvvbus
usb_rxn0
usb_rxp0
usb_txn0
usb_txp0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
usb2_drvvbus
0
O
timer15
7
IO
gpio6_13
14
IO
Driver off
15
I
usb_rxn0
0
I
pcie_rxn1
1
I
usb_rxp0
0
I
pcie_rxp1
1
I
usb_txn0
0
O
pcie_txn1
1
O
usb_txp0
0
O
pcie_txp1
1
O
H13, H14, J17,
J18, L7, L8, N10,
N13, P11, P12,
P13, R11, R16,
R19, T13, T16,
T19, U13, U16,
U8, U9, V16, V8
vdd
vdd
PWR
AA12
vdda33v_usb1
vdda33v_usb1
PWR
Y12
vdda33v_usb2
vdda33v_usb2
PWR
P14
vdda_core_gmac
vdda_core_gmac
PWR
W12
vdda_csi
vdda_csi
PWR
R17
vdda_ddr
vdda_ddr
PWR
N11
vdda_debug
vdda_debug
PWR
N12
vdda_dsp_iva
vdda_dsp_iva
PWR
R14
vdda_gpu
vdda_gpu
PWR
Y17
vdda_hdmi
vdda_hdmi
PWR
N16
vdda_mpu_abe
vdda_mpu_abe
PWR
AD16, AE16
vdda_osc
vdda_osc
PWR
AA17
vdda_pcie
vdda_pcie
PWR
AA16
vdda_pcie0
vdda_pcie0
PWR
M14
vdda_per
vdda_per
PWR
P15
vdda_pll_spare
vdda_pll_spare
PWR
AB13
vdda_rtc
vdda_rtc
PWR
V13
vdda_sata
vdda_sata
PWR
AA13
vdda_usb1
vdda_usb1
PWR
AB12
vdda_usb2
vdda_usb2
PWR
W14
vdda_usb3
vdda_usb3
PWR
P16
vdda_video
vdda_video
PWR
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
PD
OFF
OFF
15
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
1.8/3.3
vddshv6
Yes
Dual Voltage PU/PD
LVCMOS
OFF
1.8
vdda_usb1
NA
SERDES
NA
OFF
1.8
vdda_usb1
NA
SERDES
NA
1.8
vdda_usb1
NA
SERDES
NA
1.8
vdda_usb1
NA
SERDES
NA
DSIS [14]
Terminal Configuration and Functions
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www.ti.com
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
G18, H17, M8,
M9, N8, P8, R8,
T8, V21, V22,
W17, W18
BALL NAME [2]
MUXMODE
[4]
TYPE [5]
vdds18v
PWR
AA18, AA19, N21, vdds18v_ddr1
P20, P21, W21,
Y21
vdds18v_ddr1
PWR
E3, E5, G4, G5,
H8, H9
vddshv1
vddshv1
PWR
B6, D10, E10,
H10, H11
vddshv2
vddshv2
PWR
B23, D16, D22,
E16, E22, G15,
H15, H16, H18,
H19
vddshv3
vddshv3
PWR
C24
vddshv4
vddshv4
PWR
V12
vddshv5
vddshv5
PWR
AD5, AD7, AE7,
AF5
vddshv6
vddshv6
PWR
AB6, AB7
vddshv7
vddshv7
PWR
W8, Y8
vddshv8
vddshv8
PWR
U10, W4, W5
vddshv9
vddshv9
PWR
N4, N5, P10, R10, vddshv10
R7, T4, T5
vddshv10
PWR
J8, K8
vddshv11
vddshv11
PWR
AA21, AA22,
AB21, AB22,
AB24, AB25,
AC22, AD26,
AG20, AG28,
AH27, T24, T25,
W16, W27
vdds_ddr1
vdds_ddr1
PWR
AA7, Y7
vdds_mlbp
vdds_mlbp
PWR
K10, K11, L10,
L11, M10, M11
vdd_dsp
vdd_dsp
PWR
U11, U12, V10,
V11, V14, W10,
W11, W13
vdd_gpu
vdd_gpu
PWR
J13, K12, K13,
L12, M12, M13
vdd_iva
vdd_iva
PWR
K17, K18, L15,
L16, L17, L18,
L19, M15, M16,
M17, M18, N17,
N18, P17, P18,
R18
vdd_mpu
vdd_mpu
PWR
AB15
vdd_rtc
vdd_rtc
PWR
54
vdds18v
SIGNAL NAME [3]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
Terminal Configuration and Functions
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
E1
F2
F3
D1
BALL NAME [2]
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d2
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
I
O
emu5
5
O
kbd_row0
9
I
0
eQEP1A_in
10
I
0
gpio3_28
gpmc_a27
gpmc_a17
14
IO
Driver off
15
I
vin2a_d0
0
I
vout2_d23
4
O
emu10
5
O
uart9_ctsn
7
I
1
spi4_d0
8
IO
0
kbd_row4
9
I
0
ehrpwm1B
10
O
gpio4_1
14
IO
Driver off
15
I
vin2a_d1
0
I
vout2_d22
4
O
emu11
5
O
uart9_rtsn
7
O
spi4_cs0
8
IO
1
kbd_row5
9
I
0
ehrpwm1_tripzone_input
10
IO
0
gpio4_2
14
IO
Driver off
15
I
vin2a_d2
0
I
vout2_d21
4
O
emu12
5
O
uart10_rxd
8
I
1
kbd_row6
9
I
0
eCAP1_in_PWM1_out
10
IO
0
gpio4_3
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
PULL
UP/DOWN
TYPE [13]
4
1.8/3.3
vddshv1
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
vout2_fld
PD
15
POWER [10]
vin2a_clk0
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
E2
D2
F4
C1
56
BALL NAME [2]
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vin2a_d3
0
I
vout2_d20
4
O
emu13
5
O
uart10_txd
8
O
kbd_col0
9
O
ehrpwm1_synci
10
I
gpio4_4
14
IO
Driver off
15
I
vin2a_d4
0
I
vout2_d19
4
O
emu14
5
O
uart10_ctsn
8
I
kbd_col1
9
O
ehrpwm1_synco
10
O
gpio4_5
14
IO
Driver off
15
I
vin2a_d5
0
I
vout2_d18
4
O
emu15
5
O
uart10_rtsn
8
O
kbd_col2
9
O
eQEP2A_in
10
I
gpio4_6
14
IO
Driver off
15
I
vin2a_d6
0
I
vout2_d17
4
O
emu16
5
O
mii1_rxd1
8
I
kbd_col3
9
O
eQEP2B_in
10
I
gpio4_7
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv1
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
1
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
E4
F5
E6
D3
BALL NAME [2]
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vin2a_d7
0
I
vout2_d16
4
O
emu17
5
O
mii1_rxd2
8
I
kbd_col4
9
O
eQEP2_index
10
IO
gpio4_8
14
IO
Driver off
15
I
vin2a_d8
0
I
vout2_d15
4
O
emu18
5
O
mii1_rxd3
8
I
kbd_col5
9
O
eQEP2_strobe
10
IO
gpio4_9
gpmc_a26
14
IO
Driver off
15
I
vin2a_d9
0
I
vout2_d14
4
O
emu19
5
O
mii1_rxd0
8
I
kbd_col6
9
O
ehrpwm2A
10
O
gpio4_10
gpmc_a25
14
IO
Driver off
15
I
vin2a_d10
0
I
mdio_mclk
3
O
vout2_d13
4
O
kbd_col7
9
O
ehrpwm2B
10
O
gpio4_11
gpmc_a24
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv1
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
1
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
F6
D5
C2
C3
C4
58
BALL NAME [2]
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
IO
vout2_d12
4
O
kbd_row7
9
I
0
ehrpwm2_tripzone_input
10
IO
0
gpio4_12
gpmc_a23
14
IO
Driver off
15
I
vin2a_d12
0
I
rgmii1_txc
3
O
vout2_d11
4
O
mii1_rxclk
8
I
kbd_col8
9
O
eCAP2_in_PWM2_out
10
IO
gpio4_13
14
IO
Driver off
15
I
vin2a_d13
0
I
rgmii1_txctl
3
O
vout2_d10
4
O
mii1_rxdv
8
I
0
kbd_row8
9
I
0
eQEP3A_in
10
I
0
gpio4_14
14
IO
Driver off
15
I
vin2a_d14
0
I
rgmii1_txd3
3
O
vout2_d9
4
O
mii1_txclk
8
I
0
eQEP3B_in
10
I
0
gpio4_15
14
IO
Driver off
15
I
vin2a_d15
0
I
rgmii1_txd2
3
O
vout2_d8
4
O
mii1_txd0
8
O
eQEP3_index
10
IO
gpio4_16
14
IO
Driver off
15
I
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
I
vddshv1
Yes
PULL
UP/DOWN
TYPE [13]
3
1.8/3.3
vddshv1
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
mdio_d
PD
15
POWER [10]
vin2a_d11
PD
PD
I/O
VOLTAGE
VALUE [9]
Dual Voltage PU/PD
LVCMOS
0
1
0
0
0
PD
PD
PD
PD
PD
PD
15
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B2
D6
C5
A3
BALL NAME [2]
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv1
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
vin2a_d16
0
I
vin2b_d7
2
I
0
rgmii1_txd1
3
O
vout2_d7
4
O
mii1_txd1
8
O
eQEP3_strobe
10
IO
gpio4_24
14
IO
Driver off
15
I
vin2a_d17
0
I
vin2b_d6
2
I
rgmii1_txd0
3
O
vout2_d6
4
O
mii1_txd2
8
O
ehrpwm3A
10
O
gpio4_25
14
IO
Driver off
15
I
vin2a_d18
0
I
vin2b_d5
2
I
rgmii1_rxc
3
I
vout2_d5
4
O
mii1_txd3
8
O
ehrpwm3B
10
O
gpio4_26
14
IO
Driver off
15
I
vin2a_d19
0
I
vin2b_d4
2
I
rgmii1_rxctl
3
I
vout2_d4
4
O
mii1_txer
8
O
0
ehrpwm3_tripzone_input
10
IO
0
gpio4_27
14
IO
Driver off
15
I
0
0
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv1
vddshv1
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
Dual Voltage PU/PD
LVCMOS
0
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
B3
B4
B5
A4
60
BALL NAME [2]
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv1
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
vin2a_d20
0
I
vin2b_d3
2
I
0
rgmii1_rxd3
3
I
vout2_d3
4
O
mii1_rxer
8
I
0
eCAP3_in_PWM3_out
10
IO
0
gpio4_28
14
IO
Driver off
15
I
vin2a_d21
0
I
vin2b_d2
2
I
rgmii1_rxd2
3
I
vout2_d2
4
O
mii1_col
8
I
gpio4_29
14
IO
Driver off
15
I
vin2a_d22
0
I
vin2b_d1
2
I
rgmii1_rxd1
3
I
vout2_d1
4
O
mii1_crs
8
I
gpio4_30
14
IO
Driver off
15
I
vin2a_d23
0
I
vin2b_d0
2
I
rgmii1_rxd0
3
I
vout2_d0
4
O
mii1_txen
8
O
gpio4_31
14
IO
Driver off
15
I
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
G2
H7
G1
BALL NAME [2]
vin2a_de0
vin2a_fld0
vin2a_hsync0
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
I
I
vin2b_fld1
2
I
vin2b_de1
3
I
vout2_de
4
O
emu6
5
O
kbd_row1
9
I
0
eQEP1B_in
10
I
0
gpio3_29
14
IO
Driver off
15
I
vin2a_fld0
0
I
vin2b_clk1
2
I
vout2_clk
4
O
emu7
5
O
eQEP1_index
10
IO
gpio3_30
gpmc_a27
gpmc_a18
14
IO
Driver off
15
I
vin2a_hsync0
0
I
vin2b_hsync1
3
I
vout2_hsync
4
O
emu8
5
O
uart9_rxd
7
I
1
spi4_sclk
8
IO
0
kbd_row2
9
I
0
eQEP1_strobe
10
IO
0
gpio3_31
gpmc_a27
14
IO
Driver off
15
I
vddshv1
Yes
PULL
UP/DOWN
TYPE [13]
1
1.8/3.3
vddshv1
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
vin2a_fld0
PD
15
POWER [10]
vin2a_de0
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
G6
D11
F11
G10
62
BALL NAME [2]
vin2a_vsync0
vout1_clk
vout1_d0
vout1_d1
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
I
I
vout2_vsync
4
O
emu9
5
O
uart9_txd
7
O
spi4_d1
8
IO
0
kbd_row3
9
I
0
ehrpwm1A
10
O
gpio4_0
14
IO
Driver off
15
I
vout1_clk
0
O
vin2a_fld0
vin1a_fld0
3
I
vin1a_fld0
4
I
0
spi3_cs0
8
IO
1
gpio4_19
14
IO
Driver off
15
I
vout1_d0
0
O
uart5_rxd
2
I
vin2a_d16
vin1a_d16
3
I
vin1a_d16
4
I
0
spi3_cs2
8
IO
1
gpio8_0
14
IO
Driver off
15
I
vout1_d1
0
O
uart5_txd
2
O
vin2a_d17
vin1a_d17
3
I
vin1a_d17
4
I
gpio8_1
14
IO
Driver off
15
I
PD
PD
PD
PD
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
Yes
PULL
UP/DOWN
TYPE [13]
3
1.8/3.3
vddshv1
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
vin2b_vsync1
PD
15
POWER [10]
vin2a_vsync0
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
1
Dual Voltage PU/PD
LVCMOS
0
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
F10
G11
E9
F9
BALL NAME [2]
vout1_d2
vout1_d3
vout1_d4
vout1_d5
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vout1_d2
0
O
emu2
2
O
vin2a_d18
vin1a_d18
3
I
vin1a_d18
4
I
obs0
5
O
obs16
6
O
obs_irq1
7
O
gpio8_2
14
IO
Driver off
15
I
vout1_d3
0
O
emu5
2
O
vin2a_d19
vin1a_d19
3
I
vin1a_d19
4
I
obs1
5
O
obs17
6
O
obs_dmarq1
7
O
gpio8_3
14
IO
Driver off
15
I
vout1_d4
0
O
emu6
2
O
vin2a_d20
vin1a_d20
3
I
vin1a_d20
4
I
obs2
5
O
obs18
6
O
gpio8_4
14
IO
Driver off
15
I
vout1_d5
0
O
emu7
2
O
vin2a_d21
vin1a_d21
3
I
vin1a_d21
4
I
obs3
5
O
obs19
6
O
gpio8_5
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv2
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
F8
E7
E8
D9
D7
64
BALL NAME [2]
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_d10
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vout1_d6
0
O
emu8
2
O
vin2a_d22
vin1a_d22
3
I
vin1a_d22
4
I
obs4
5
O
obs20
6
O
gpio8_6
14
IO
Driver off
15
I
vout1_d7
0
O
emu9
2
O
vin2a_d23
vin1a_d23
3
I
vin1a_d23
4
I
gpio8_7
14
IO
Driver off
15
I
vout1_d8
0
O
uart6_rxd
2
I
vin2a_d8
vin1a_d8
3
I
vin1a_d8
4
I
gpio8_8
14
IO
Driver off
15
I
vout1_d9
0
O
uart6_txd
2
O
vin2a_d9
vin1a_d9
3
I
vin1a_d9
4
I
gpio8_9
14
IO
Driver off
15
I
vout1_d10
0
O
emu3
2
O
vin2a_d10
vin1a_d10
3
I
vin1a_d10
4
I
obs5
5
O
obs21
6
O
obs_irq2
7
O
gpio8_10
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv2
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
D8
A5
C6
C8
BALL NAME [2]
vout1_d11
vout1_d12
vout1_d13
vout1_d14
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vout1_d11
0
O
emu10
2
O
vin2a_d11
vin1a_d11
3
I
vin1a_d11
4
I
obs6
5
O
obs22
6
O
obs_dmarq2
7
O
gpio8_11
14
IO
Driver off
15
I
vout1_d12
0
O
emu11
2
O
vin2a_d12
vin1a_d12
3
I
vin1a_d12
4
I
obs7
5
O
obs23
6
O
gpio8_12
14
IO
Driver off
15
I
vout1_d13
0
O
emu12
2
O
vin2a_d13
vin1a_d13
3
I
vin1a_d13
4
I
obs8
5
O
obs24
6
O
gpio8_13
14
IO
Driver off
15
I
vout1_d14
0
O
emu13
2
O
vin2a_d14
vin1a_d14
3
I
vin1a_d14
4
I
obs9
5
O
obs25
6
O
gpio8_14
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv2
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
C7
B7
B8
A7
66
BALL NAME [2]
vout1_d15
vout1_d16
vout1_d17
vout1_d18
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vout1_d15
0
O
emu14
2
O
vin2a_d15
vin1a_d15
3
I
vin1a_d15
4
I
obs10
5
O
obs26
6
O
gpio8_15
14
IO
Driver off
15
I
vout1_d16
0
O
uart7_rxd
2
I
vin2a_d0
vin1a_d0
3
I
vin1a_d0
4
I
gpio8_16
14
IO
Driver off
15
I
vout1_d17
0
O
uart7_txd
2
O
vin2a_d1
vin1a_d1
3
I
vin1a_d1
4
I
gpio8_17
14
IO
Driver off
15
I
vout1_d18
0
O
emu4
2
O
vin2a_d2
vin1a_d2
3
I
vin1a_d2
4
I
obs11
5
O
obs27
6
O
gpio8_18
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv2
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
1
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
A8
C9
A9
B9
BALL NAME [2]
vout1_d19
vout1_d20
vout1_d21
vout1_d22
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
vout1_d19
0
O
emu15
2
O
vin2a_d3
vin1a_d3
3
I
vin1a_d3
4
I
obs12
5
O
obs28
6
O
gpio8_19
14
IO
Driver off
15
I
vout1_d20
0
O
emu16
2
O
vin2a_d4
vin1a_d4
3
I
vin1a_d4
4
I
obs13
5
O
obs29
6
O
gpio8_20
14
IO
Driver off
15
I
vout1_d21
0
O
emu17
2
O
vin2a_d5
vin1a_d5
3
I
vin1a_d5
4
I
obs14
5
O
obs30
6
O
gpio8_21
14
IO
Driver off
15
I
vout1_d22
0
O
emu18
2
O
vin2a_d6
vin1a_d6
3
I
vin1a_d6
4
I
obs15
5
O
obs31
6
O
gpio8_22
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv2
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
PD
PD
15
1.8/3.3
vddshv2
Yes
Dual Voltage PU/PD
LVCMOS
0
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
A10
B10
B11
C11
E11
68
BALL NAME [2]
vout1_d23
vout1_de
vout1_fld
vout1_hsync
vout1_vsync
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
DSIS [14]
O
O
vin2a_d7
vin1a_d7
3
I
vin1a_d7
4
I
0
spi3_cs3
8
IO
1
gpio8_23
14
IO
Driver off
15
I
vout1_de
0
O
vin2a_de0
vin1a_de0
3
I
vin1a_de0
4
I
0
spi3_d1
8
IO
0
gpio4_20
14
IO
Driver off
15
I
vout1_fld
0
O
vin2a_clk0
vin1a_clk0
3
I
vin1a_clk0
4
I
0
spi3_cs1
8
IO
1
gpio4_21
14
IO
Driver off
15
I
vout1_hsync
0
O
vin2a_hsync0
vin1a_hsync0
3
I
vin1a_hsync0
4
I
0
spi3_d0
8
IO
0
gpio4_22
14
IO
Driver off
15
I
vout1_vsync
0
O
vin2a_vsync0
vin1a_vsync0
3
I
vin1a_vsync0
4
I
0
spi3_sclk
8
IO
0
gpio4_23
14
IO
Driver off
15
I
PD
PD
PD
PD
PD
PD
15
15
15
Terminal Configuration and Functions
1.8/3.3
1.8/3.3
1.8/3.3
vddshv2
vddshv2
vddshv2
vddshv2
Yes
PULL
UP/DOWN
TYPE [13]
2
1.8/3.3
vddshv2
BUFFER
TYPE [12]
0
15
1.8/3.3
HYS [11]
emu19
PD
15
POWER [10]
vout1_d23
PD
PD
I/O
VOLTAGE
VALUE [9]
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
Dual Voltage PU/PD
LVCMOS
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
A1, A14, A2, A23, vss
A28, A6, AA14,
AA15, AA20, AA8,
AA9, AB14, AB20,
AD1, AD24, AG1,
AH1, AH2, AH20,
AH28, B1, D13,
D19, E13, E19,
F1, F7, G7, G8,
G9, H12, J12,
J15, J28, K1, K15,
K24, K25, K4, K5,
L13, L14, M19,
N14, N15, N19,
N24, N25, P28,
R1, R12, R13,
R21, T10, T11,
T12, T14, T15,
T17, T18, T21,
U14, U15, U17,
U20, U21, V15,
V17, W1, W15,
W24, W25, W28
vss
GND
AA10, AH8
vssa_csi
vssa_csi
GND
AD19, AE19
vssa_hdmi
vssa_hdmi
GND
AF15
vssa_osc0
vssa_osc0
GND
AC14
vssa_osc1
vssa_osc1
GND
AD13, AE13
vssa_pcie
vssa_pcie
GND
AE10
vssa_sata
vssa_sata
GND
AA11, AB11
vssa_usb
vssa_usb
GND
AD10
vssa_usb3
vssa_usb3
GND
R15
vssa_video
vssa_video
AD17
Wakeup0
Wakeup0
0
I
dcan1_rx
1
I
gpio1_0
sys_nirq2
14
I
Driver off
15
I
Wakeup3
0
I
sys_nirq1
1
I
gpio1_3
dcan2_rx
14
I
AC16
Wakeup3
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
DSIS [14]
GND
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
1
15
1.8/3.3
vddshv5
Yes
IHHV1833
PU/PD
Driver off
15
I
AE15
xi_osc0
xi_osc0
0
I
1.8
vdda_osc
No
LVCMOS
Analog
NA
AC15
xi_osc1
xi_osc1
0
I
1.8
vdda_osc
No
LVCMOS
Analog
NA
AD15
xo_osc0
xo_osc0
0
O
1.8
vdda_osc
No
LVCMOS
Analog
NA
Terminal Configuration and Functions
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
BALL NAME [2]
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
BALL
RESET
STATE [6]
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
AC13
xo_osc1
xo_osc1
0
A
D18
xref_clk0
xref_clk0
0
I
mcasp2_axr8
1
IO
mcasp1_axr4
2
IO
mcasp1_ahclkx
3
O
mcasp5_ahclkx
4
O
atl_clk0
5
O
vin1a_d0
7
I
0
hdq0
8
IO
1
clkout2
9
O
timer13
10
IO
gpio6_17
14
IO
Driver off
15
I
xref_clk1
0
I
mcasp2_axr9
1
IO
mcasp1_axr5
2
IO
mcasp2_ahclkx
3
O
mcasp6_ahclkx
4
O
atl_clk1
5
O
vin1a_clk0
7
I
timer14
10
IO
gpio6_18
14
IO
Driver off
15
I
xref_clk2
0
I
mcasp2_axr10
1
IO
mcasp1_axr6
2
IO
mcasp3_ahclkx
3
O
mcasp7_ahclkx
4
O
atl_clk2
5
O
vout2_clk
6
O
vin2a_clk0
vin1a_clk0
8
I
timer15
10
IO
gpio6_19
14
IO
Driver off
15
I
E17
B26
70
xref_clk1
xref_clk2
PD
PD
15
1.8
vdda_osc
No
LVCMOS
Analog
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
DSIS [14]
NA
0
0
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
PD
PD
15
Terminal Configuration and Functions
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
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Table 4-2. Ball Characteristics(1) (continued)
BALL NUMBER
[1]
C23
BALL NAME [2]
xref_clk3
SIGNAL NAME [3]
MUXMODE
[4]
TYPE [5]
xref_clk3
0
I
mcasp2_axr11
1
IO
mcasp1_axr7
2
IO
mcasp4_ahclkx
3
O
mcasp8_ahclkx
4
O
atl_clk3
5
O
vout2_de
6
O
hdq0
7
IO
vin2a_de0
vin1a_de0
8
I
clkout3
9
O
timer16
10
IO
gpio6_20
14
IO
Driver off
15
I
BALL
RESET
STATE [6]
PD
BALL
BALL
RESET REL.
RESET REL.
MUXMODE
STATE [7]
[8]
PD
15
I/O
VOLTAGE
VALUE [9]
1.8/3.3
POWER [10]
vddshv3
HYS [11]
Yes
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
Dual Voltage PU/PD
LVCMOS
DSIS [14]
0
0
1
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
4.3
Multiplexing Characteristics
Table 4-3 describes the device multiplexing (no characteristics are available in this table).
NOTE
This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal
Descriptions.
Terminal Configuration and Functions
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NOTE
For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration
section of the Device TRM.
NOTE
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (Hi-Z mode is not an input signal).
NOTE
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be
avoided.
NOTE
In some cases Table 4-3 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function
as selected via CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
NOTE
ECC is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within
a single IOSET are used. The IOSETs are defined in the corresponding tables.
NOTE
Dual rank support is not available on this device, but signal names are retained for consistency with the DRA7xx family of devices.
72
Terminal Configuration and Functions
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Table 4-3. Multiplexing Characteristics
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
Y23
ddr1_d26
Y19
ddr1_d21
AE15
xi_osc0
AH24
ddr1_nck
AG15
ljcb_clkp
AF24
ddr1_d4
V25
ddr1_ecc_d6
AB16
ddr1_csn1
AG19
hdmi1_data2x
AF21
ddr1_a4
AG5
csi2_1_dx0
W23
ddr1_ecc_d3
Y27
ddr1_dqsn3
AC24
ddr1_d14
AF28
ddr1_d11
AA23
ddr1_d24
AD18
ddr1_a15
AH16
hdmi1_clocky
AH5
csi2_1_dy0
AC20
ddr1_a2
AA24
ddr1_d27
W19
ddr1_ecc_d2
AG21
ddr1_rst
AE28
ddr1_dqsn1
AC11
usb_txn0
AG25
ddr1_dqsn0
AC17
ddr1_odt1
AG4
csi2_0_dy3
W20
ddr1_d17
AF14
rtc_iso
AA27
ddr1_dqm3
AF25
ddr1_d0
AF2
csi2_0_dx2
AF23
ddr1_d6
AG18
hdmi1_data1x
AH6
csi2_1_dy1
AG10
sata1_txn0
AF20
ddr1_rasn
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
pcie_txn1
Terminal Configuration and Functions
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
74
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
V26
ddr1_dqm_ec
c
V20
ddr1_d16
AH13
pcie_rxp0
AC18
ddr1_casn
AG9
sata1_rxp0
AH23
ddr1_csn0
AE11
usb2_dp
Y24
ddr1_d28
AH15
ljcb_clkn
AD20
ddr1_a0
AA25
ddr1_d30
AA1
mlbp_dat_p
AD14
rtc_osc_xo
AC25
ddr1_d13
AB23
ddr1_dqm1
AE1
csi2_0_dx0
AH19
hdmi1_data2y
AB27
ddr1_d22
AG14
pcie_txn0
Y28
ddr1_dqs3
AB19
ddr1_a3
AH10
sata1_txp0
AG24
ddr1_ck
AE24
ddr1_d5
AC15
xi_osc1
AC21
ddr1_a12
AB1
mlbp_clk_p
AF12
usb_rxn0
AH9
sata1_rxn0
AC26
ddr1_dqm2
AA28
ddr1_d31
AD23
ddr1_dqm0
AE27
ddr1_dqs1
AF27
ddr1_d9
V24
ddr1_ecc_d5
AG27
ddr1_d10
AF22
ddr1_a8
AA2
mlbp_dat_n
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
pcie_rxn1
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
AH21
ddr1_wen
AE21
ddr1_a7
AC12
usb1_dm
Y20
ddr1_d23
AC27
ddr1_d20
AE23
ddr1_d7
AG22
ddr1_cke
AD27
ddr1_dqs2
AH14
pcie_txp0
AH26
ddr1_d3
AD21
ddr1_a10
Y25
ddr1_ecc_d4
AE17
ddr1_a14
AG7
csi2_1_dy2
AH18
hdmi1_data1y
AH22
ddr1_a5
W22
ddr1_ecc_d0
V23
ddr1_ecc_d1
AE12
usb_rxp0
AE14
rtc_osc_xi_clki
n32
AF3
csi2_0_dy2
AB2
mlbp_clk_n
AG23
ddr1_a6
AG6
csi2_1_dx1
AB18
ddr1_ba2
AG17
hdmi1_data0x
AF26
ddr1_d1
AD11
usb_txp0
AC1
mlbp_sig_p
V27
ddr1_dqs_ecc
AF17
ddr1_ba0
AE26
ddr1_d12
AC19
ddr1_a1
AG13
pcie_rxn0
AB28
ddr1_d18
Y26
ddr1_ecc_d7
AH3
csi2_0_dx4
AD22
ddr1_a11
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
pcie_rxp1
pcie_txp1
Terminal Configuration and Functions
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
AD28
ddr1_dqsn2
AD2
csi2_0_dy0
AE18
ddr1_ba1
AE20
ddr1_odt0
AF11
usb2_dm
AD15
xo_osc0
AH7
csi2_1_dx2
AE22
ddr1_a9
Y18
ddr1_vref0
AC13
xo_osc1
AC2
mlbp_sig_n
AD12
usb1_dp
Y22
ddr1_d25
AH17
hdmi1_data0y
AH4
csi2_0_dx3
AE2
csi2_0_dy1
AG26
ddr1_d2
AH25
ddr1_dqs0
AF18
ddr1_a13
AC28
ddr1_d19
AG3
csi2_0_dy4
V28
ddr1_dqsn_ec
c
AC23
ddr1_d8
F22
porz
AG16
hdmi1_clockx
AF1
csi2_0_dx1
AA26
ddr1_d29
AD25
ddr1_d15
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
0x1400
CTRL_CORE_PAD_
GPMC_AD0
M6
gpmc_ad0
vin1a_d0
vout3_d0
gpio1_6
sysboot0
0x1404
CTRL_CORE_PAD_
GPMC_AD1
M2
gpmc_ad1
vin1a_d1
vout3_d1
gpio1_7
sysboot1
0x1408
CTRL_CORE_PAD_
GPMC_AD2
L5
gpmc_ad2
vin1a_d2
vout3_d2
gpio1_8
sysboot2
0x140C
CTRL_CORE_PAD_
GPMC_AD3
M1
gpmc_ad3
vin1a_d3
vout3_d3
gpio1_9
sysboot3
0x1410
CTRL_CORE_PAD_
GPMC_AD4
L6
gpmc_ad4
vin1a_d4
vout3_d4
gpio1_10
sysboot4
0x1414
CTRL_CORE_PAD_
GPMC_AD5
L4
gpmc_ad5
vin1a_d5
vout3_d5
gpio1_11
sysboot5
76
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3*
4*
14*
15
0x1418
CTRL_CORE_PAD_
GPMC_AD6
L3
gpmc_ad6
vin1a_d6
vout3_d6
5*
gpio1_12
sysboot6
0x141C
CTRL_CORE_PAD_
GPMC_AD7
L2
gpmc_ad7
vin1a_d7
vout3_d7
gpio1_13
sysboot7
0x1420
CTRL_CORE_PAD_
GPMC_AD8
L1
gpmc_ad8
vin1a_d8
vout3_d8
gpio7_18
sysboot8
0x1424
CTRL_CORE_PAD_
GPMC_AD9
K2
gpmc_ad9
vin1a_d9
vout3_d9
gpio7_19
sysboot9
0x1428
CTRL_CORE_PAD_
GPMC_AD10
J1
gpmc_ad10
vin1a_d10
vout3_d10
gpio7_28
sysboot10
0x142C
CTRL_CORE_PAD_
GPMC_AD11
J2
gpmc_ad11
vin1a_d11
vout3_d11
gpio7_29
sysboot11
0x1430
CTRL_CORE_PAD_
GPMC_AD12
H1
gpmc_ad12
vin1a_d12
vout3_d12
gpio1_18
sysboot12
0x1434
CTRL_CORE_PAD_
GPMC_AD13
J3
gpmc_ad13
vin1a_d13
vout3_d13
gpio1_19
sysboot13
0x1438
CTRL_CORE_PAD_
GPMC_AD14
H2
gpmc_ad14
vin1a_d14
vout3_d14
gpio1_20
sysboot14
0x143C
CTRL_CORE_PAD_
GPMC_AD15
H3
gpmc_ad15
vin1a_d15
vout3_d15
gpio1_21
sysboot15
0x1440
CTRL_CORE_PAD_
GPMC_A0
R6
gpmc_a0
vin1a_d16
vout3_d16
vin2a_d0
vin1a_d0
vin1b_d0
i2c4_scl
uart5_rxd
gpio7_3
gpmc_a26
gpmc_a16
Driver off
0x1444
CTRL_CORE_PAD_
GPMC_A1
T9
gpmc_a1
vin1a_d17
vout3_d17
vin2a_d1
vin1a_d1
vin1b_d1
i2c4_sda
uart5_txd
gpio7_4
Driver off
0x1448
CTRL_CORE_PAD_
GPMC_A2
T6
gpmc_a2
vin1a_d18
vout3_d18
vin2a_d2
vin1a_d2
vin1b_d2
uart7_rxd
uart5_ctsn
gpio7_5
Driver off
0x144C
CTRL_CORE_PAD_
GPMC_A3
T7
gpmc_a3
qspi1_cs2
vin1a_d19
vout3_d19
vin2a_d3
vin1a_d3
vin1b_d3
uart7_txd
uart5_rtsn
gpio7_6
Driver off
0x1450
CTRL_CORE_PAD_
GPMC_A4
P6
gpmc_a4
qspi1_cs3
vin1a_d20
vout3_d20
vin2a_d4
vin1a_d4
vin1b_d4
i2c5_scl
uart6_rxd
gpio1_26
Driver off
0x1454
CTRL_CORE_PAD_
GPMC_A5
R9
gpmc_a5
vin1a_d21
vout3_d21
vin2a_d5
vin1a_d5
vin1b_d5
i2c5_sda
uart6_txd
gpio1_27
Driver off
0x1458
CTRL_CORE_PAD_
GPMC_A6
R5
gpmc_a6
vin1a_d22
vout3_d22
vin2a_d6
vin1a_d6
vin1b_d6
uart8_rxd
uart6_ctsn
gpio1_28
Driver off
0x145C
CTRL_CORE_PAD_
GPMC_A7
P5
gpmc_a7
vin1a_d23
vout3_d23
vin2a_d7
vin1a_d7
vin1b_d7
uart8_txd
uart6_rtsn
gpio1_29
Driver off
0x1460
CTRL_CORE_PAD_
GPMC_A8
N7
gpmc_a8
vin1a_hsync0 vout3_hsync
vin1b_hsync1 timer12
spi4_sclk
gpio1_30
Driver off
0x1464
CTRL_CORE_PAD_
GPMC_A9
R4
gpmc_a9
vin1a_vsync0 vout3_vsync
vin1b_vsync1 timer11
spi4_d1
gpio1_31
Driver off
0x1468
CTRL_CORE_PAD_
GPMC_A10
N9
gpmc_a10
vin1a_de0
vout3_de
vin1b_clk1
timer10
spi4_d0
gpio2_0
Driver off
0x146C
CTRL_CORE_PAD_
GPMC_A11
P9
gpmc_a11
vin1a_fld0
vout3_fld
vin1b_de1
timer9
spi4_cs0
gpio2_1
Driver off
0x1470
CTRL_CORE_PAD_
GPMC_A12
P4
gpmc_a12
vin1b_fld1
timer8
spi4_cs1
gpio2_2
Driver off
vin2a_fld0
vin1a_fld0
vin2a_clk0
vin1a_clk0
gpmc_a0
6*
7
8*
9
dma_evt1
10
Terminal Configuration and Functions
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www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
1
2
3*
4*
5*
6*
7
8*
0x1474
CTRL_CORE_PAD_
GPMC_A13
R3
gpmc_a13
qspi1_rtclk
vin2a_hsync0
vin1a_hsync0
timer7
spi4_cs2
0x1478
CTRL_CORE_PAD_
GPMC_A14
T2
gpmc_a14
qspi1_d3
vin2a_vsync0
vin1a_vsync0
timer6
spi4_cs3
0x147C
CTRL_CORE_PAD_
GPMC_A15
U2
gpmc_a15
qspi1_d2
vin2a_d8
vin1a_d8
timer5
0x1480
CTRL_CORE_PAD_
GPMC_A16
U1
gpmc_a16
qspi1_d0
0x1484
CTRL_CORE_PAD_
GPMC_A17
P3
gpmc_a17
0x1488
CTRL_CORE_PAD_
GPMC_A18
R2
0x148C
CTRL_CORE_PAD_
GPMC_A19
0x1490
9
10
14*
15
gpio2_3
Driver off
gpio2_4
Driver off
gpio2_5
Driver off
vin2a_d9
vin1a_d9
gpio2_6
Driver off
qspi1_d1
vin2a_d10
vin1a_d10
gpio2_7
Driver off
gpmc_a18
qspi1_sclk
vin2a_d11
vin1a_d11
gpio2_8
Driver off
K7
gpmc_a19
mmc2_dat4
gpmc_a13
vin2a_d12
vin1a_d12
vin2b_d0
vin1b_d0
gpio2_9
Driver off
CTRL_CORE_PAD_
GPMC_A20
M7
gpmc_a20
mmc2_dat5
gpmc_a14
vin2a_d13
vin1a_d13
vin2b_d1
vin1b_d1
gpio2_10
Driver off
0x1494
CTRL_CORE_PAD_
GPMC_A21
J5
gpmc_a21
mmc2_dat6
gpmc_a15
vin2a_d14
vin1a_d14
vin2b_d2
vin1b_d2
gpio2_11
Driver off
0x1498
CTRL_CORE_PAD_
GPMC_A22
K6
gpmc_a22
mmc2_dat7
gpmc_a16
vin2a_d15
vin1a_d15
vin2b_d3
vin1b_d3
gpio2_12
Driver off
0x149C
CTRL_CORE_PAD_
GPMC_A23
J7
gpmc_a23
mmc2_clk
gpmc_a17
vin2a_fld0
vin1a_fld0
vin2b_d4
vin1b_d4
gpio2_13
Driver off
0x14A0
CTRL_CORE_PAD_
GPMC_A24
J4
gpmc_a24
mmc2_dat0
gpmc_a18
vin1a_d8
vin2b_d5
vin1b_d5
gpio2_14
Driver off
0x14A4
CTRL_CORE_PAD_
GPMC_A25
J6
gpmc_a25
mmc2_dat1
gpmc_a19
vin1a_d9
vin2b_d6
vin1b_d6
gpio2_15
Driver off
0x14A8
CTRL_CORE_PAD_
GPMC_A26
H4
gpmc_a26
mmc2_dat2
gpmc_a20
vin1a_d10
vin2b_d7
vin1b_d7
gpio2_16
Driver off
0x14AC
CTRL_CORE_PAD_
GPMC_A27
H5
gpmc_a27
mmc2_dat3
gpmc_a21
vin1a_d11
vin2b_hsync1
vin1b_hsync1
gpio2_17
Driver off
0x14B0
CTRL_CORE_PAD_
GPMC_CS1
H6
gpmc_cs1
mmc2_cmd
gpmc_a22
vin2a_de0
vin1a_de0
vin2b_vsync1
vin1b_vsync1
gpio2_18
Driver off
0x14B4
CTRL_CORE_PAD_
GPMC_CS0
T1
gpmc_cs0
gpio2_19
Driver off
0x14B8
CTRL_CORE_PAD_
GPMC_CS2
P2
gpmc_cs2
qspi1_cs0
gpio2_20
gpmc_a23
gpmc_a13
Driver off
0x14BC
CTRL_CORE_PAD_
GPMC_CS3
P1
gpmc_cs3
qspi1_cs1
vin1a_clk0
vout3_clk
gpio2_21
gpmc_a24
gpmc_a14
Driver off
0x14C0
CTRL_CORE_PAD_
GPMC_CLK
P7
gpmc_clk
gpmc_cs7
clkout1
gpmc_wait1
vin2a_hsync0 vin2a_de0
vin1a_hsync0 vin1a_de0
vin2b_clk1
vin1b_clk1
timer4
i2c3_scl
dma_evt1
gpio2_22
gpmc_a20
Driver off
0x14C4
CTRL_CORE_PAD_
GPMC_ADVN_ALE
N1
gpmc_advn_al gpmc_cs6
e
clkout2
gpmc_wait1
vin2a_vsync0 gpmc_a2
vin1a_vsync0
gpmc_a23
timer3
i2c3_sda
dma_evt2
gpio2_23
gpmc_a19
Driver off
0x14C8
CTRL_CORE_PAD_
GPMC_OEN_REN
M5
gpmc_oen_re
n
gpio2_24
Driver off
0x14CC
CTRL_CORE_PAD_
GPMC_WEN
M3
gpmc_wen
gpio2_25
Driver off
78
dma_evt2
gpmc_a1
Terminal Configuration and Functions
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www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3*
4*
5*
6*
7
8*
0x14D0
CTRL_CORE_PAD_
GPMC_BEN0
N6
gpmc_ben0
gpmc_cs4
0x14D4
CTRL_CORE_PAD_
GPMC_BEN1
M4
gpmc_ben1
gpmc_cs5
0x14D8
CTRL_CORE_PAD_
GPMC_WAIT0
N2
gpmc_wait0
0x1554
CTRL_CORE_PAD_V E1
IN2A_CLK0
vin2a_clk0
0x1558
CTRL_CORE_PAD_V G2
IN2A_DE0
vin2a_de0
0x155C
CTRL_CORE_PAD_V H7
IN2A_FLD0
vin2a_fld0
0x1560
CTRL_CORE_PAD_V G1
IN2A_HSYNC0
vin2a_hsync0
vin2b_hsync1 vout2_hsync
emu8
uart9_rxd
spi4_sclk
0x1564
CTRL_CORE_PAD_V G6
IN2A_VSYNC0
vin2a_vsync0
vin2b_vsync1 vout2_vsync
emu9
uart9_txd
0x1568
CTRL_CORE_PAD_V F2
IN2A_D0
vin2a_d0
vout2_d23
emu10
0x156C
CTRL_CORE_PAD_V F3
IN2A_D1
vin2a_d1
vout2_d22
emu11
0x1570
CTRL_CORE_PAD_V D1
IN2A_D2
vin2a_d2
vout2_d21
0x1574
CTRL_CORE_PAD_V E2
IN2A_D3
vin2a_d3
0x1578
CTRL_CORE_PAD_V D2
IN2A_D4
0x157C
vin2a_fld0
vin2b_clk1
vin1b_clk1
vin2b_fld1
vin2b_de1
vin2b_clk1
gpmc_a3
9
10
14*
15
vin2b_de1
vin1b_de1
timer2
dma_evt3
gpio2_26
gpmc_a21
Driver off
vin2b_fld1
vin1b_fld1
timer1
dma_evt4
gpio2_27
gpmc_a22
Driver off
gpio2_28
gpmc_a25
gpmc_a15
Driver off
vout2_fld
emu5
kbd_row0
eQEP1A_in
gpio3_28
gpmc_a27
gpmc_a17
Driver off
vout2_de
emu6
kbd_row1
eQEP1B_in
gpio3_29
Driver off
vout2_clk
emu7
eQEP1_index gpio3_30
gpmc_a27
gpmc_a18
Driver off
kbd_row2
eQEP1_strob gpio3_31
e
gpmc_a27
Driver off
spi4_d1
kbd_row3
ehrpwm1A
gpio4_0
Driver off
uart9_ctsn
spi4_d0
kbd_row4
ehrpwm1B
gpio4_1
Driver off
uart9_rtsn
spi4_cs0
kbd_row5
ehrpwm1_trip gpio4_2
zone_input
Driver off
emu12
uart10_rxd
kbd_row6
eCAP1_in_P
WM1_out
gpio4_3
Driver off
vout2_d20
emu13
uart10_txd
kbd_col0
ehrpwm1_syn gpio4_4
ci
Driver off
vin2a_d4
vout2_d19
emu14
uart10_ctsn
kbd_col1
ehrpwm1_syn gpio4_5
co
Driver off
CTRL_CORE_PAD_V F4
IN2A_D5
vin2a_d5
vout2_d18
emu15
uart10_rtsn
kbd_col2
eQEP2A_in
gpio4_6
Driver off
0x1580
CTRL_CORE_PAD_V C1
IN2A_D6
vin2a_d6
vout2_d17
emu16
mii1_rxd1
kbd_col3
eQEP2B_in
gpio4_7
Driver off
0x1584
CTRL_CORE_PAD_V E4
IN2A_D7
vin2a_d7
vout2_d16
emu17
mii1_rxd2
kbd_col4
eQEP2_index gpio4_8
Driver off
0x1588
CTRL_CORE_PAD_V F5
IN2A_D8
vin2a_d8
vout2_d15
emu18
mii1_rxd3
kbd_col5
eQEP2_strob gpio4_9
e
gpmc_a26
Driver off
0x158C
CTRL_CORE_PAD_V E6
IN2A_D9
vin2a_d9
vout2_d14
emu19
mii1_rxd0
kbd_col6
ehrpwm2A
gpio4_10
gpmc_a25
Driver off
0x1590
CTRL_CORE_PAD_V D3
IN2A_D10
vin2a_d10
mdio_mclk
vout2_d13
kbd_col7
ehrpwm2B
gpio4_11
gpmc_a24
Driver off
0x1594
CTRL_CORE_PAD_V F6
IN2A_D11
vin2a_d11
mdio_d
vout2_d12
kbd_row7
ehrpwm2_trip gpio4_12
zone_input
gpmc_a23
Driver off
0x1598
CTRL_CORE_PAD_V D5
IN2A_D12
vin2a_d12
rgmii1_txc
vout2_d11
mii1_rxclk
kbd_col8
eCAP2_in_P
WM2_out
gpio4_13
Driver off
0x159C
CTRL_CORE_PAD_V C2
IN2A_D13
vin2a_d13
rgmii1_txctl
vout2_d10
mii1_rxdv
kbd_row8
eQEP3A_in
gpio4_14
Driver off
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
14*
15
0x15A0
CTRL_CORE_PAD_V C3
IN2A_D14
vin2a_d14
rgmii1_txd3
vout2_d9
mii1_txclk
eQEP3B_in
gpio4_15
Driver off
0x15A4
CTRL_CORE_PAD_V C4
IN2A_D15
vin2a_d15
rgmii1_txd2
vout2_d8
mii1_txd0
eQEP3_index gpio4_16
Driver off
0x15A8
CTRL_CORE_PAD_V B2
IN2A_D16
vin2a_d16
vin2b_d7
rgmii1_txd1
vout2_d7
mii1_txd1
eQEP3_strob gpio4_24
e
Driver off
0x15AC
CTRL_CORE_PAD_V D6
IN2A_D17
vin2a_d17
vin2b_d6
rgmii1_txd0
vout2_d6
mii1_txd2
ehrpwm3A
gpio4_25
Driver off
0x15B0
CTRL_CORE_PAD_V C5
IN2A_D18
vin2a_d18
vin2b_d5
rgmii1_rxc
vout2_d5
mii1_txd3
ehrpwm3B
gpio4_26
Driver off
0x15B4
CTRL_CORE_PAD_V A3
IN2A_D19
vin2a_d19
vin2b_d4
rgmii1_rxctl
vout2_d4
mii1_txer
ehrpwm3_trip gpio4_27
zone_input
Driver off
0x15B8
CTRL_CORE_PAD_V B3
IN2A_D20
vin2a_d20
vin2b_d3
rgmii1_rxd3
vout2_d3
mii1_rxer
eCAP3_in_P
WM3_out
gpio4_28
Driver off
0x15BC
CTRL_CORE_PAD_V B4
IN2A_D21
vin2a_d21
vin2b_d2
rgmii1_rxd2
vout2_d2
mii1_col
gpio4_29
Driver off
0x15C0
CTRL_CORE_PAD_V B5
IN2A_D22
vin2a_d22
vin2b_d1
rgmii1_rxd1
vout2_d1
mii1_crs
gpio4_30
Driver off
0x15C4
CTRL_CORE_PAD_V A4
IN2A_D23
vin2a_d23
vin2b_d0
rgmii1_rxd0
vout2_d0
mii1_txen
gpio4_31
Driver off
0x15C8
CTRL_CORE_PAD_V D11
OUT1_CLK
vout1_clk
vin2a_fld0
vin1a_fld0
vin1a_fld0
spi3_cs0
gpio4_19
Driver off
0x15CC
CTRL_CORE_PAD_V B10
OUT1_DE
vout1_de
vin2a_de0
vin1a_de0
vin1a_de0
spi3_d1
gpio4_20
Driver off
0x15D0
CTRL_CORE_PAD_V B11
OUT1_FLD
vout1_fld
vin2a_clk0
vin1a_clk0
vin1a_clk0
spi3_cs1
gpio4_21
Driver off
0x15D4
CTRL_CORE_PAD_V C11
OUT1_HSYNC
vout1_hsync
vin2a_hsync0 vin1a_hsync0
vin1a_hsync0
spi3_d0
gpio4_22
Driver off
0x15D8
CTRL_CORE_PAD_V E11
OUT1_VSYNC
vout1_vsync
vin2a_vsync0 vin1a_vsync0
vin1a_vsync0
spi3_sclk
gpio4_23
Driver off
0x15DC
CTRL_CORE_PAD_V F11
OUT1_D0
vout1_d0
uart5_rxd
vin2a_d16
vin1a_d16
vin1a_d16
spi3_cs2
gpio8_0
Driver off
0x15E0
CTRL_CORE_PAD_V G10
OUT1_D1
vout1_d1
uart5_txd
vin2a_d17
vin1a_d17
vin1a_d17
gpio8_1
Driver off
0x15E4
CTRL_CORE_PAD_V F10
OUT1_D2
vout1_d2
emu2
vin2a_d18
vin1a_d18
vin1a_d18
obs0
obs16
obs_irq1
gpio8_2
Driver off
0x15E8
CTRL_CORE_PAD_V G11
OUT1_D3
vout1_d3
emu5
vin2a_d19
vin1a_d19
vin1a_d19
obs1
obs17
obs_dmarq1
gpio8_3
Driver off
0x15EC
CTRL_CORE_PAD_V E9
OUT1_D4
vout1_d4
emu6
vin2a_d20
vin1a_d20
vin1a_d20
obs2
obs18
gpio8_4
Driver off
0x15F0
CTRL_CORE_PAD_V F9
OUT1_D5
vout1_d5
emu7
vin2a_d21
vin1a_d21
vin1a_d21
obs3
obs19
gpio8_5
Driver off
0x15F4
CTRL_CORE_PAD_V F8
OUT1_D6
vout1_d6
emu8
vin2a_d22
vin1a_d22
vin1a_d22
obs4
obs20
gpio8_6
Driver off
0x15F8
CTRL_CORE_PAD_V E7
OUT1_D7
vout1_d7
emu9
vin2a_d23
vin1a_d23
vin1a_d23
gpio8_7
Driver off
0x15FC
CTRL_CORE_PAD_V E8
OUT1_D8
vout1_d8
uart6_rxd
vin2a_d8
vin1a_d8
vin1a_d8
gpio8_8
Driver off
80
0
1
2
3*
4*
5*
6*
7
Terminal Configuration and Functions
8*
9
10
Copyright © 2016–2017, Texas Instruments Incorporated
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DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3*
4*
5*
6*
0x1600
CTRL_CORE_PAD_V D9
OUT1_D9
vout1_d9
uart6_txd
vin2a_d9
vin1a_d9
vin1a_d9
0x1604
CTRL_CORE_PAD_V D7
OUT1_D10
vout1_d10
emu3
vin2a_d10
vin1a_d10
vin1a_d10
obs5
obs21
0x1608
CTRL_CORE_PAD_V D8
OUT1_D11
vout1_d11
emu10
vin2a_d11
vin1a_d11
vin1a_d11
obs6
obs22
0x160C
CTRL_CORE_PAD_V A5
OUT1_D12
vout1_d12
emu11
vin2a_d12
vin1a_d12
vin1a_d12
obs7
0x1610
CTRL_CORE_PAD_V C6
OUT1_D13
vout1_d13
emu12
vin2a_d13
vin1a_d13
vin1a_d13
0x1614
CTRL_CORE_PAD_V C8
OUT1_D14
vout1_d14
emu13
vin2a_d14
vin1a_d14
0x1618
CTRL_CORE_PAD_V C7
OUT1_D15
vout1_d15
emu14
0x161C
CTRL_CORE_PAD_V B7
OUT1_D16
vout1_d16
0x1620
CTRL_CORE_PAD_V B8
OUT1_D17
0x1624
7
8*
9
10
14*
15
gpio8_9
Driver off
obs_irq2
gpio8_10
Driver off
obs_dmarq2
gpio8_11
Driver off
obs23
gpio8_12
Driver off
obs8
obs24
gpio8_13
Driver off
vin1a_d14
obs9
obs25
gpio8_14
Driver off
vin2a_d15
vin1a_d15
vin1a_d15
obs10
obs26
gpio8_15
Driver off
uart7_rxd
vin2a_d0
vin1a_d0
vin1a_d0
gpio8_16
Driver off
vout1_d17
uart7_txd
vin2a_d1
vin1a_d1
vin1a_d1
gpio8_17
Driver off
CTRL_CORE_PAD_V A7
OUT1_D18
vout1_d18
emu4
vin2a_d2
vin1a_d2
vin1a_d2
obs11
obs27
gpio8_18
Driver off
0x1628
CTRL_CORE_PAD_V A8
OUT1_D19
vout1_d19
emu15
vin2a_d3
vin1a_d3
vin1a_d3
obs12
obs28
gpio8_19
Driver off
0x162C
CTRL_CORE_PAD_V C9
OUT1_D20
vout1_d20
emu16
vin2a_d4
vin1a_d4
vin1a_d4
obs13
obs29
gpio8_20
Driver off
0x1630
CTRL_CORE_PAD_V A9
OUT1_D21
vout1_d21
emu17
vin2a_d5
vin1a_d5
vin1a_d5
obs14
obs30
gpio8_21
Driver off
0x1634
CTRL_CORE_PAD_V B9
OUT1_D22
vout1_d22
emu18
vin2a_d6
vin1a_d6
vin1a_d6
obs15
obs31
gpio8_22
Driver off
0x1638
CTRL_CORE_PAD_V A10
OUT1_D23
vout1_d23
emu19
vin2a_d7
vin1a_d7
vin1a_d7
gpio8_23
Driver off
0x163C
CTRL_CORE_PAD_
MDIO_MCLK
V1
mdio_mclk
uart3_rtsn
mii0_col
vin2a_clk0
vin1b_clk1
gpio5_15
Driver off
0x1640
CTRL_CORE_PAD_
MDIO_D
U4
mdio_d
uart3_ctsn
mii0_txer
vin2a_d0
vin1b_d0
gpio5_16
Driver off
0x1644
CTRL_CORE_PAD_R U3
MII_MHZ_50_CLK
RMII_MHZ_50
_CLK
gpio5_17
Driver off
0x1648
CTRL_CORE_PAD_U V2
ART3_RXD
uart3_rxd
rmii1_crs
mii0_rxdv
vin2a_d1
vin1b_d1
spi3_sclk
gpio5_18
Driver off
0x164C
CTRL_CORE_PAD_U Y1
ART3_TXD
uart3_txd
rmii1_rxer
mii0_rxclk
vin2a_d2
vin1b_d2
spi3_d1
spi4_cs1
gpio5_19
Driver off
0x1650
CTRL_CORE_PAD_R W9
GMII0_TXC
rgmii0_txc
uart3_ctsn
rmii1_rxd1
mii0_rxd3
vin2a_d3
vin1b_d3
usb3_ulpi_clk spi3_d0
spi4_cs2
gpio5_20
Driver off
0x1654
CTRL_CORE_PAD_R V9
GMII0_TXCTL
rgmii0_txctl
uart3_rtsn
rmii1_rxd0
mii0_rxd2
vin2a_d4
vin1b_d4
usb3_ulpi_stp spi3_cs0
spi4_cs3
gpio5_21
Driver off
0x1658
CTRL_CORE_PAD_R V7
GMII0_TXD3
rgmii0_txd3
rmii0_crs
mii0_crs
vin2a_de0
vin1b_de1
usb3_ulpi_dir spi4_sclk
uart4_rxd
gpio5_22
Driver off
0x165C
CTRL_CORE_PAD_R U7
GMII0_TXD2
rgmii0_txd2
rmii0_rxer
mii0_rxer
vin2a_hsync0 vin1b_hsync1 usb3_ulpi_nxt spi4_d1
uart4_txd
gpio5_23
Driver off
spi3_cs3
vin2a_d11
Terminal Configuration and Functions
Copyright © 2016–2017, Texas Instruments Incorporated
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81
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
14*
15
0x1660
CTRL_CORE_PAD_R V6
GMII0_TXD1
rgmii0_txd1
rmii0_rxd1
mii0_rxd1
vin2a_vsync0 vin1b_vsync1 usb3_ulpi_d0 spi4_d0
uart4_ctsn
gpio5_24
Driver off
0x1664
CTRL_CORE_PAD_R U6
GMII0_TXD0
rgmii0_txd0
rmii0_rxd0
mii0_rxd0
vin2a_d10
uart4_rtsn
gpio5_25
Driver off
0x1668
CTRL_CORE_PAD_R U5
GMII0_RXC
rgmii0_rxc
rmii1_txen
mii0_txclk
vin2a_d5
vin1b_d5
usb3_ulpi_d2
gpio5_26
Driver off
0x166C
CTRL_CORE_PAD_R V5
GMII0_RXCTL
rgmii0_rxctl
rmii1_txd1
mii0_txd3
vin2a_d6
vin1b_d6
usb3_ulpi_d3
gpio5_27
Driver off
0x1670
CTRL_CORE_PAD_R V4
GMII0_RXD3
rgmii0_rxd3
rmii1_txd0
mii0_txd2
vin2a_d7
vin1b_d7
usb3_ulpi_d4
gpio5_28
Driver off
0x1674
CTRL_CORE_PAD_R V3
GMII0_RXD2
rgmii0_rxd2
rmii0_txen
mii0_txen
vin2a_d8
usb3_ulpi_d5
gpio5_29
Driver off
0x1678
CTRL_CORE_PAD_R Y2
GMII0_RXD1
rgmii0_rxd1
rmii0_txd1
mii0_txd1
vin2a_d9
usb3_ulpi_d6
gpio5_30
Driver off
0x167C
CTRL_CORE_PAD_R W2
GMII0_RXD0
rgmii0_rxd0
rmii0_txd0
mii0_txd0
vin2a_fld0
usb3_ulpi_d7
gpio5_31
Driver off
0x1680
CTRL_CORE_PAD_U AB10
SB1_DRVVBUS
usb1_drvvbus
timer16
gpio6_12
Driver off
0x1684
CTRL_CORE_PAD_U AC10
SB2_DRVVBUS
usb2_drvvbus
timer15
gpio6_13
Driver off
0x1688
CTRL_CORE_PAD_
GPIO6_14
E21
gpio6_14
mcasp1_axr8 dcan2_tx
uart10_rxd
vout2_hsync
vin2a_hsync0 i2c3_sda
vin1a_hsync0
timer1
gpio6_14
Driver off
0x168C
CTRL_CORE_PAD_
GPIO6_15
F20
gpio6_15
mcasp1_axr9 dcan2_rx
uart10_txd
vout2_vsync
vin2a_vsync0 i2c3_scl
vin1a_vsync0
timer2
gpio6_15
Driver off
0x1690
CTRL_CORE_PAD_
GPIO6_16
F21
gpio6_16
mcasp1_axr1
0
vout2_fld
vin2a_fld0
vin1a_fld0
clkout1
timer3
gpio6_16
Driver off
0x1694
CTRL_CORE_PAD_X D18
REF_CLK0
xref_clk0
mcasp2_axr8 mcasp1_axr4 mcasp1_ahclk mcasp5_ahclk atl_clk0
x
x
vin1a_d0
hdq0
clkout2
timer13
gpio6_17
Driver off
0x1698
CTRL_CORE_PAD_X E17
REF_CLK1
xref_clk1
mcasp2_axr9 mcasp1_axr5 mcasp2_ahclk mcasp6_ahclk atl_clk1
x
x
vin1a_clk0
timer14
gpio6_18
Driver off
0x169C
CTRL_CORE_PAD_X B26
REF_CLK2
xref_clk2
mcasp2_axr1 mcasp1_axr6 mcasp3_ahclk mcasp7_ahclk atl_clk2
0
x
x
vout2_clk
timer15
gpio6_19
Driver off
0x16A0
CTRL_CORE_PAD_X C23
REF_CLK3
xref_clk3
mcasp2_axr1 mcasp1_axr7 mcasp4_ahclk mcasp8_ahclk atl_clk3
1
x
x
vout2_de
timer16
gpio6_20
Driver off
0x16A4
CTRL_CORE_PAD_
MCASP1_ACLKX
C14
mcasp1_aclkx
vin1a_fld0
i2c3_sda
gpio7_31
Driver off
0x16A8
CTRL_CORE_PAD_
MCASP1_FSX
D14
mcasp1_fsx
vin1a_de0
i2c3_scl
gpio7_30
Driver off
0x16AC
CTRL_CORE_PAD_
MCASP1_ACLKR
B14
mcasp1_aclkr mcasp7_axr2
vout2_d0
vin2a_d0
vin1a_d0
i2c4_sda
gpio5_0
Driver off
0x16B0
CTRL_CORE_PAD_
MCASP1_FSR
J14
mcasp1_fsr
vout2_d1
vin2a_d1
vin1a_d1
i2c4_scl
gpio5_1
Driver off
0x16B4
CTRL_CORE_PAD_
MCASP1_AXR0
G12
mcasp1_axr0
uart6_rxd
vin1a_vsync0
i2c5_sda
gpio5_2
Driver off
0x16B8
CTRL_CORE_PAD_
MCASP1_AXR1
F12
mcasp1_axr1
uart6_txd
vin1a_hsync0
i2c5_scl
gpio5_3
Driver off
0x16BC
CTRL_CORE_PAD_
MCASP1_AXR2
G13
mcasp1_axr2 mcasp6_axr2
uart6_ctsn
gpio5_4
Driver off
82
0
1
2
3*
mcasp7_axr3
4*
5*
6*
7
usb3_ulpi_d1 spi4_cs0
vin1b_fld1
8*
9
vin2a_clk0
vin1a_clk0
hdq0
vout2_d2
Terminal Configuration and Functions
vin2a_de0
vin1a_de0
vin2a_d2
vin1a_d2
clkout3
10
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
0x16C0
CTRL_CORE_PAD_
MCASP1_AXR3
J11
mcasp1_axr3 mcasp6_axr3
0x16C4
CTRL_CORE_PAD_
MCASP1_AXR4
E12
0x16C8
CTRL_CORE_PAD_
MCASP1_AXR5
0x16CC
2
3*
uart6_rtsn
4*
5*
6*
7
8*
9
10
14*
15
vout2_d3
vin2a_d3
vin1a_d3
gpio5_5
Driver off
mcasp1_axr4 mcasp4_axr2
vout2_d4
vin2a_d4
vin1a_d4
gpio5_6
Driver off
F13
mcasp1_axr5 mcasp4_axr3
vout2_d5
vin2a_d5
vin1a_d5
gpio5_7
Driver off
CTRL_CORE_PAD_
MCASP1_AXR6
C12
mcasp1_axr6 mcasp5_axr2
vout2_d6
vin2a_d6
vin1a_d6
gpio5_8
Driver off
0x16D0
CTRL_CORE_PAD_
MCASP1_AXR7
D12
mcasp1_axr7 mcasp5_axr3
vout2_d7
vin2a_d7
vin1a_d7
timer4
gpio5_9
Driver off
0x16D4
CTRL_CORE_PAD_
MCASP1_AXR8
B12
mcasp1_axr8 mcasp6_axr0
spi3_sclk
vin1a_d15
timer5
gpio5_10
Driver off
0x16D8
CTRL_CORE_PAD_
MCASP1_AXR9
A11
mcasp1_axr9 mcasp6_axr1
spi3_d1
vin1a_d14
timer6
gpio5_11
Driver off
0x16DC
CTRL_CORE_PAD_
MCASP1_AXR10
B13
mcasp1_axr1 mcasp6_aclkx mcasp6_aclkr spi3_d0
0
vin1a_d13
timer7
gpio5_12
Driver off
0x16E0
CTRL_CORE_PAD_
MCASP1_AXR11
A12
mcasp1_axr1 mcasp6_fsx
1
spi3_cs0
vin1a_d12
timer8
gpio4_17
Driver off
0x16E4
CTRL_CORE_PAD_
MCASP1_AXR12
E14
mcasp1_axr1 mcasp7_axr0
2
spi3_cs1
vin1a_d11
timer9
gpio4_18
Driver off
0x16E8
CTRL_CORE_PAD_
MCASP1_AXR13
A13
mcasp1_axr1 mcasp7_axr1
3
vin1a_d10
timer10
gpio6_4
Driver off
0x16EC
CTRL_CORE_PAD_
MCASP1_AXR14
G14
mcasp1_axr1 mcasp7_aclkx mcasp7_aclkr
4
vin1a_d9
timer11
gpio6_5
Driver off
0x16F0
CTRL_CORE_PAD_
MCASP1_AXR15
F14
mcasp1_axr1 mcasp7_fsx
5
vin1a_d8
timer12
gpio6_6
Driver off
0x16F4
CTRL_CORE_PAD_
MCASP2_ACLKX
A19
mcasp2_aclkx
vin1a_d7
Driver off
0x16F8
CTRL_CORE_PAD_
MCASP2_FSX
A18
mcasp2_fsx
vin1a_d6
Driver off
0x16FC
CTRL_CORE_PAD_
MCASP2_ACLKR
E15
mcasp2_aclkr mcasp8_axr2
vout2_d8
vin2a_d8
vin1a_d8
Driver off
0x1700
CTRL_CORE_PAD_
MCASP2_FSR
A20
mcasp2_fsr
vout2_d9
vin2a_d9
vin1a_d9
Driver off
0x1704
CTRL_CORE_PAD_
MCASP2_AXR0
B15
mcasp2_axr0
vout2_d10
vin2a_d10
vin1a_d10
Driver off
0x1708
CTRL_CORE_PAD_
MCASP2_AXR1
A15
mcasp2_axr1
vout2_d11
vin2a_d11
vin1a_d11
Driver off
0x170C
CTRL_CORE_PAD_
MCASP2_AXR2
C15
mcasp2_axr2 mcasp3_axr2
vin1a_d5
gpio6_8
Driver off
0x1710
CTRL_CORE_PAD_
MCASP2_AXR3
A16
mcasp2_axr3 mcasp3_axr3
vin1a_d4
gpio6_9
Driver off
0x1714
CTRL_CORE_PAD_
MCASP2_AXR4
D15
mcasp2_axr4 mcasp8_axr0
vout2_d12
vin2a_d12
vin1a_d12
gpio1_4
Driver off
0x1718
CTRL_CORE_PAD_
MCASP2_AXR5
B16
mcasp2_axr5 mcasp8_axr1
vout2_d13
vin2a_d13
vin1a_d13
gpio6_7
Driver off
0x171C
CTRL_CORE_PAD_
MCASP2_AXR6
B17
mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr
vout2_d14
vin2a_d14
vin1a_d14
gpio2_29
Driver off
mcasp6_fsr
mcasp7_fsr
mcasp8_axr3
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
0
1
2
3*
4*
5*
7
CTRL_CORE_PAD_
MCASP2_AXR7
A17
mcasp2_axr7 mcasp8_fsx
0x1724
CTRL_CORE_PAD_
MCASP3_ACLKX
B18
mcasp3_aclkx mcasp3_aclkr mcasp2_axr1 uart7_rxd
2
0x1728
CTRL_CORE_PAD_
MCASP3_FSX
F15
mcasp3_fsx
0x172C
CTRL_CORE_PAD_
MCASP3_AXR0
B19
mcasp3_axr0
mcasp2_axr1 uart7_ctsn
4
uart5_rxd
vin1a_d1
0x1730
CTRL_CORE_PAD_
MCASP3_AXR1
C17
mcasp3_axr1
mcasp2_axr1 uart7_rtsn
5
uart5_txd
vin1a_d0
0x1734
CTRL_CORE_PAD_
MCASP4_ACLKX
C18
mcasp4_aclkx mcasp4_aclkr spi3_sclk
uart8_rxd
i2c4_sda
vout2_d16
0x1738
CTRL_CORE_PAD_
MCASP4_FSX
A21
mcasp4_fsx
spi3_d1
uart8_txd
i2c4_scl
0x173C
CTRL_CORE_PAD_
MCASP4_AXR0
G16
mcasp4_axr0
spi3_d0
uart8_ctsn
0x1740
CTRL_CORE_PAD_
MCASP4_AXR1
D17
mcasp4_axr1
spi3_cs0
0x1744
CTRL_CORE_PAD_
MCASP5_ACLKX
AA3
0x1748
CTRL_CORE_PAD_
MCASP5_FSX
0x174C
mcasp3_fsr
mcasp8_fsr
6*
0x1720
vout2_d15
mcasp2_axr1 uart7_txd
3
8*
9
10
vin2a_d15
vin1a_d15
14*
15
gpio1_5
Driver off
vin1a_d3
gpio5_13
Driver off
vin1a_d2
gpio5_14
Driver off
Driver off
vin1a_fld0
Driver off
vin2a_d16
vin1a_d16
vin1a_d15
Driver off
vout2_d17
vin2a_d17
vin1a_d17
vin1a_d14
Driver off
uart4_rxd
vout2_d18
vin2a_d18
vin1a_d18
vin1a_d13
i2c6_scl
Driver off
uart8_rtsn
uart4_txd
vout2_d19
vin2a_d19
vin1a_d19
vin1a_d12
i2c6_sda
Driver off
mcasp5_aclkx mcasp5_aclkr spi4_sclk
uart9_rxd
i2c5_sda
vout2_d20
vin2a_d20
vin1a_d20
vin1a_d11
Driver off
AB9
mcasp5_fsx
spi4_d1
uart9_txd
i2c5_scl
vout2_d21
vin2a_d21
vin1a_d21
vin1a_d10
Driver off
CTRL_CORE_PAD_
MCASP5_AXR0
AB3
mcasp5_axr0
spi4_d0
uart9_ctsn
uart3_rxd
mlb_sig
vout2_d22
vin2a_d22
vin1a_d22
vin1a_d9
Driver off
0x1750
CTRL_CORE_PAD_
MCASP5_AXR1
AA4
mcasp5_axr1
spi4_cs0
uart9_rtsn
uart3_txd
mlb_dat
vout2_d23
vin2a_d23
vin1a_d23
vin1a_d8
Driver off
0x1754
CTRL_CORE_PAD_
MMC1_CLK
W6
mmc1_clk
gpio6_21
Driver off
0x1758
CTRL_CORE_PAD_
MMC1_CMD
Y6
mmc1_cmd
gpio6_22
Driver off
0x175C
CTRL_CORE_PAD_
MMC1_DAT0
AA6
mmc1_dat0
gpio6_23
Driver off
0x1760
CTRL_CORE_PAD_
MMC1_DAT1
Y4
mmc1_dat1
gpio6_24
Driver off
0x1764
CTRL_CORE_PAD_
MMC1_DAT2
AA5
mmc1_dat2
gpio6_25
Driver off
0x1768
CTRL_CORE_PAD_
MMC1_DAT3
Y3
mmc1_dat3
gpio6_26
Driver off
0x176C
CTRL_CORE_PAD_
MMC1_SDCD
W7
mmc1_sdcd
uart6_rxd
i2c4_sda
gpio6_27
Driver off
0x1770
CTRL_CORE_PAD_
MMC1_SDWP
Y9
mmc1_sdwp
uart6_txd
i2c4_scl
gpio6_28
Driver off
0x1774
CTRL_CORE_PAD_
GPIO6_10
AC5
gpio6_10
mdio_mclk
i2c3_sda
usb3_ulpi_d7 vin2b_hsync1
vin1a_clk0
ehrpwm2A
gpio6_10
Driver off
0x1778
CTRL_CORE_PAD_
GPIO6_11
AB4
gpio6_11
mdio_d
i2c3_scl
usb3_ulpi_d6 vin2b_vsync1
vin1a_de0
ehrpwm2B
gpio6_11
Driver off
0x177C
CTRL_CORE_PAD_
MMC3_CLK
AD4
mmc3_clk
usb3_ulpi_d5 vin2b_d7
vin1a_d7
ehrpwm2_trip gpio6_29
zone_input
Driver off
84
mcasp4_fsr
mcasp5_fsr
mlb_clk
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
BALL
NUMBER
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
14*
15
usb3_ulpi_d4 vin2b_d6
vin1a_d6
eCAP2_in_P
WM2_out
gpio6_30
Driver off
uart5_rxd
usb3_ulpi_d3 vin2b_d5
vin1a_d5
eQEP3A_in
gpio6_31
Driver off
spi3_d0
uart5_txd
usb3_ulpi_d2 vin2b_d4
vin1a_d4
eQEP3B_in
gpio7_0
Driver off
mmc3_dat2
spi3_cs0
uart5_ctsn
usb3_ulpi_d1 vin2b_d3
vin1a_d3
eQEP3_index gpio7_1
Driver off
AC3
mmc3_dat3
spi3_cs1
uart5_rtsn
usb3_ulpi_d0 vin2b_d2
vin1a_d2
eQEP3_strob gpio7_2
e
Driver off
CTRL_CORE_PAD_
MMC3_DAT4
AC8
mmc3_dat4
spi4_sclk
uart10_rxd
usb3_ulpi_nxt vin2b_d1
vin1a_d1
ehrpwm3A
gpio1_22
Driver off
0x1798
CTRL_CORE_PAD_
MMC3_DAT5
AD6
mmc3_dat5
spi4_d1
uart10_txd
usb3_ulpi_dir vin2b_d0
vin1a_d0
ehrpwm3B
gpio1_23
Driver off
0x179C
CTRL_CORE_PAD_
MMC3_DAT6
AB8
mmc3_dat6
spi4_d0
uart10_ctsn
usb3_ulpi_stp vin2b_de1
vin1a_hsync0 ehrpwm3_trip gpio1_24
zone_input
Driver off
0x17A0
CTRL_CORE_PAD_
MMC3_DAT7
AB5
mmc3_dat7
spi4_cs0
uart10_rtsn
usb3_ulpi_clk vin2b_clk1
vin1a_vsync0 eCAP3_in_P
WM3_out
gpio1_25
Driver off
0x17A4
CTRL_CORE_PAD_S A25
PI1_SCLK
spi1_sclk
gpio7_7
Driver off
0x17A8
CTRL_CORE_PAD_S F16
PI1_D1
spi1_d1
gpio7_8
Driver off
0x17AC
CTRL_CORE_PAD_S B25
PI1_D0
spi1_d0
gpio7_9
Driver off
0x17B0
CTRL_CORE_PAD_S A24
PI1_CS0
spi1_cs0
gpio7_10
Driver off
0x17B4
CTRL_CORE_PAD_S A22
PI1_CS1
spi1_cs1
gpio7_11
Driver off
0x17B8
CTRL_CORE_PAD_S B21
PI1_CS2
spi1_cs2
0x17BC
CTRL_CORE_PAD_S B20
PI1_CS3
0x17C0
0x1780
CTRL_CORE_PAD_
MMC3_CMD
AC4
mmc3_cmd
spi3_sclk
0x1784
CTRL_CORE_PAD_
MMC3_DAT0
AC7
mmc3_dat0
spi3_d1
0x1788
CTRL_CORE_PAD_
MMC3_DAT1
AC6
mmc3_dat1
0x178C
CTRL_CORE_PAD_
MMC3_DAT2
AC9
0x1790
CTRL_CORE_PAD_
MMC3_DAT3
0x1794
2
3*
4*
5*
6*
7
8*
9
10
sata1_led
spi2_cs1
uart4_rxd
mmc3_sdcd
spi2_cs2
dcan2_tx
mdio_mclk
hdmi1_hpd
gpio7_12
Driver off
spi1_cs3
uart4_txd
mmc3_sdwp
spi2_cs3
dcan2_rx
mdio_d
hdmi1_cec
gpio7_13
Driver off
CTRL_CORE_PAD_S A26
PI2_SCLK
spi2_sclk
uart3_rxd
gpio7_14
Driver off
0x17C4
CTRL_CORE_PAD_S B22
PI2_D1
spi2_d1
uart3_txd
gpio7_15
Driver off
0x17C8
CTRL_CORE_PAD_S G17
PI2_D0
spi2_d0
uart3_ctsn
uart5_rxd
gpio7_16
Driver off
0x17CC
CTRL_CORE_PAD_S B24
PI2_CS0
spi2_cs0
uart3_rtsn
uart5_txd
gpio7_17
Driver off
0x17D0
CTRL_CORE_PAD_D G20
CAN1_TX
dcan1_tx
uart8_rxd
mmc2_sdcd
hdmi1_hpd
gpio1_14
Driver off
0x17D4
CTRL_CORE_PAD_D G19
CAN1_RX
dcan1_rx
uart8_txd
mmc2_sdwp
hdmi1_cec
gpio1_15
Driver off
0x17E0
CTRL_CORE_PAD_U B27
ART1_RXD
uart1_rxd
mmc4_sdcd
gpio7_22
Driver off
0x17E4
CTRL_CORE_PAD_U C26
ART1_TXD
uart1_txd
mmc4_sdwp
gpio7_23
Driver off
sata1_led
Terminal Configuration and Functions
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
REGISTER NAME
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
14*
15
0x17E8
CTRL_CORE_PAD_U E25
ART1_CTSN
uart1_ctsn
uart9_rxd
mmc4_clk
gpio7_24
Driver off
0x17EC
CTRL_CORE_PAD_U C27
ART1_RTSN
uart1_rtsn
uart9_txd
mmc4_cmd
gpio7_25
Driver off
0x17F0
CTRL_CORE_PAD_U D28
ART2_RXD
uart2_rxd
uart3_ctsn
uart3_rctx
mmc4_dat0
uart2_rxd
uart1_dcdn
gpio7_26
Driver off
0x17F4
CTRL_CORE_PAD_U D26
ART2_TXD
uart2_txd
uart3_rtsn
uart3_sd
mmc4_dat1
uart2_txd
uart1_dsrn
gpio7_27
Driver off
0x17F8
CTRL_CORE_PAD_U D27
ART2_CTSN
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
0x17FC
CTRL_CORE_PAD_U C28
ART2_RTSN
uart2_rtsn
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
gpio1_17
Driver off
0x1800
CTRL_CORE_PAD_I C21
2C1_SDA
i2c1_sda
Driver off
0x1804
CTRL_CORE_PAD_I C20
2C1_SCL
i2c1_scl
Driver off
0x1808
CTRL_CORE_PAD_I C25
2C2_SDA
i2c2_sda
hdmi1_ddc_sc
l
Driver off
0x180C
CTRL_CORE_PAD_I F17
2C2_SCL
i2c2_scl
hdmi1_ddc_sd
a
Driver off
0x1818
CTRL_CORE_PAD_
WAKEUP0
AD17
Wakeup0
dcan1_rx
gpio1_0
sys_nirq2
Driver off
0x1824
CTRL_CORE_PAD_
WAKEUP3
AC16
Wakeup3
sys_nirq1
gpio1_3
dcan2_rx
Driver off
0x1828
CTRL_CORE_PAD_
ON_OFF
Y11
on_off
0x182C
CTRL_CORE_PAD_R AB17
TC_PORZ
rtc_porz
0x1830
CTRL_CORE_PAD_T F18
MS
tms
0x1834
CTRL_CORE_PAD_T D23
DI
tdi
gpio8_27
0x1838
CTRL_CORE_PAD_T F19
DO
tdo
gpio8_28
0x183C
CTRL_CORE_PAD_T E20
CLK
tclk
0x1840
CTRL_CORE_PAD_T D20
RSTN
trstn
0x1844
CTRL_CORE_PAD_R E18
TCK
rtck
gpio8_29
0x1848
CTRL_CORE_PAD_E G21
MU0
emu0
gpio8_30
0x184C
CTRL_CORE_PAD_E D24
MU1
emu1
gpio8_31
0x185C
CTRL_CORE_PAD_R E23
ESETN
resetn
0x1860
CTRL_CORE_PAD_N D21
MIN_DSP
nmin_dsp
86
0
1
uart3_txd
2
3*
4*
5*
6*
Terminal Configuration and Functions
7
8*
9
10
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Table 4-3. Multiplexing Characteristics (continued)
ADDRESS
0x1864
REGISTER NAME
BALL
NUMBER
CTRL_CORE_PAD_R F23
STOUTN
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
0
1
2
3*
4*
5*
6*
7
8*
9
10
14*
15
rstoutn
1. NA in table stands for Not Applicable.
Terminal Configuration and Functions
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4.4
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Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The name of the signal passing through the pin.
NOTE
The subsystem multiplexing signals are not described in Table 4-2 and Table 4-3.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
– I = Input
– O = Output
– IO = Input or output
– D = Open Drain
– DS = Differential
– A = Analog
– PWR = Power
– GND = Ground
4. BALL: Associated ball(s) bottom
NOTE
For more information, see the Control Module / Control Module Register Manual section of
the device TRM.
4.4.1
Video Input Ports (VIP)
NOTE
For more information, see the Video Input Port (VIP) section of the device TRM.
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only for VIN1 and VIN2 if signals within a single IOSET
are used. The IOSETs are defined in Table 7-4.
Table 4-4. VIP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video
capture. Input data is sampled on the CLK0 edge.
I
AC5 / B11 / E17 /
P1 / P4 / B26
vin1a_d0
Video Input 1 Port A Data input
I
AD6 / B7 / C17 /
D18 / M6 / R6 / B14
vin1a_d1
Video Input 1 Port A Data input
I
AC8 / B19 / B8 / M2
/ T9 / J14
vin1a_d2
Video Input 1 Port A Data input
I
A7 / AC3 / F15 / L5 /
T6 / G13
vin1a_d3
Video Input 1 Port A Data input
I
A8 / AC9 / B18 / M1
/ T7 / J11
vin1a_d4
Video Input 1 Port A Data input
I
A16 / AC6 / C9 / L6 /
P6 / E12
Video Input 1
vin1a_clk0
88
Terminal Configuration and Functions
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vin1a_d5
DESCRIPTION
Video Input 1 Port A Data input
I
A9 / AC7 / C15 / L4 /
R9 / F13
vin1a_d6
Video Input 1 Port A Data input
I
A18 / AC4 / B9 / L3 /
R5 / C12
vin1a_d7
Video Input 1 Port A Data input
I
A10 / A19 / AD4 / L2
/ P5 / D12
vin1a_d8
Video Input 1 Port A Data input
I
AA4 / E8 / F14 / L1 /
U2 / J4 / E15
vin1a_d9
Video Input 1 Port A Data input
I
AB3 / D9 / G14 / K2
/ U1 / J6 / A20
vin1a_d10
Video Input 1 Port A Data input
I
A13 / AB9 / D7 / J1 /
P3 / H4 / B15
vin1a_d11
Video Input 1 Port A Data input
I
AA3 / D8 / E14 / J2 /
R2 / H5 / A15
vin1a_d12
Video Input 1 Port A Data input
I
A12 / A5 / D17 / H1 /
K7 / D15
vin1a_d13
Video Input 1 Port A Data input
I
B13 / C6 / G16 / J3 /
M7 / B16
vin1a_d14
Video Input 1 Port A Data input
I
A11 / A21 / C8 / H2 /
J5 / B17
vin1a_d15
Video Input 1 Port A Data input
I
B12 / C18 / C7 / H3
/ K6 / A17
vin1a_d16
Video Input 1 Port A Data input
I
F11 / R6 / C18
vin1a_d17
Video Input 1 Port A Data input
I
G10 / T9 / A21
vin1a_d18
Video Input 1 Port A Data input
I
F10 / T6 / G16
vin1a_d19
Video Input 1 Port A Data input
I
G11 / T7 / D17
vin1a_d20
Video Input 1 Port A Data input
I
E9 / P6 / AA3
vin1a_d21
Video Input 1 Port A Data input
I
F9 / R9 / AB9
vin1a_d22
Video Input 1 Port A Data input
I
F8 / R5 / AB3
vin1a_d23
Video Input 1 Port A Data input
I
E7 / P5 / AA4
vin1a_de0
Video Input 1 Port A Field ID input
I
AB4 / B10 / D14 /
N9 / H6 / C23 / P7
vin1a_fld0
Video Input 1 Port A Field ID input
I
C14 / C17 / D11 /
P9 / J7 / F21
vin1a_hsync0
Video Input 1 Port A Horizontal Sync input
I
AB8 / C11 / F12 /
N7 / R3 / P7 / E21
vin1a_vsync0
Video Input 1 Port A Vertical Sync input
I
AB5 / E11 / G12 /
R4 / T2 / N1 / F20
vin1b_clk1
Video Input 1 Port B Clock input
I
N9 / V1 / M4 / P7
vin1b_d0
Video Input 1 Port B Data input
I
R6 / U4 / K7
vin1b_d1
Video Input 1 Port B Data input
I
T9 / V2 / M7
vin1b_d2
Video Input 1 Port B Data input
I
T6 / Y1 / J5
vin1b_d3
Video Input 1 Port B Data input
I
T7 / W9 / K6
vin1b_d4
Video Input 1 Port B Data input
I
P6 / V9 / J7
vin1b_d5
Video Input 1 Port B Data input
I
R9 / U5 / J4
vin1b_d6
Video Input 1 Port B Data input
I
R5 / V5 / J6
vin1b_d7
Video Input 1 Port B Data input
I
P5 / V4 / H4
vin1b_de1
Video Input 1 Port B Field ID input
I
P9 / V7 / N6
vin1b_fld1
Video Input 1 Port B Field ID input
I
P4 / W2 / M4
vin1b_hsync1
Video Input 1 Port B Horizontal Sync input
I
N7 / U7 / H5
vin1b_vsync1
Video Input 1 Port B Vertical Sync input
I
R4 / V6 / H6
Video Input 2
Terminal Configuration and Functions
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Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
90
TYPE
BALL
vin2a_clk0
DESCRIPTION
Video Input 2 Port A Clock input
I
B11 / B26 / E1 / P4 /
V1
vin2a_d0
Video Input 2 Port A Data input
I
B14 / B7 / F2 / R6 /
U4
vin2a_d1
Video Input 2 Port A Data input
I
B8 / F3 / J14 / T9 /
V2
vin2a_d2
Video Input 2 Port A Data input
I
A7 / D1 / G13 / T6 /
Y1
vin2a_d3
Video Input 2 Port A Data input
I
A8 / E2 / J11 / T7 /
W9
vin2a_d4
Video Input 2 Port A Data input
I
C9 / D2 / E12 / P6 /
V9
vin2a_d5
Video Input 2 Port A Data input
I
A9 / F13 / F4 / R9 /
U5
vin2a_d6
Video Input 2 Port A Data input
I
B9 / C1 / C12 / R5 /
V5
vin2a_d7
Video Input 2 Port A Data input
I
A10 / D12 / E4 / P5 /
V4
vin2a_d8
Video Input 2 Port A Data input
I
E15 / E8 / F5 / U2 /
V3
vin2a_d9
Video Input 2 Port A Data input
I
A20 / D9 / E6 / U1 /
Y2
vin2a_d10
Video Input 2 Port A Data input
IO
B15 / D3 / D7 / P3 /
U6
vin2a_d11
Video Input 2 Port A Data input
IO
A15 / D8 / F6 / R2 /
U3
vin2a_d12
Video Input 2 Port A Data input
I
A5 / D15 / D5 / K7
vin2a_d13
Video Input 2 Port A Data input
I
B16 / C2 / C6 / M7
vin2a_d14
Video Input 2 Port A Data input
I
B17 / C3 / C8 / J5
vin2a_d15
Video Input 2 Port A Data input
I
A17 / C4 / C7 / K6
vin2a_d16
Video Input 2 Port A Data input
I
B2 / C18 / F11
vin2a_d17
Video Input 2 Port A Data input
I
A21 / D6 / G10
vin2a_d18
Video Input 2 Port A Data input
I
C5 / F10 / G16
vin2a_d19
Video Input 2 Port A Data input
I
A3 / D17 / G11
vin2a_d20
Video Input 2 Port A Data input
I
AA3 / B3 / E9
vin2a_d21
Video Input 2 Port A Data input
I
AB9 / B4 / F9
vin2a_d22
Video Input 2 Port A Data input
I
AB3 / B5 / F8
vin2a_d23
Video Input 2 Port A Data input
I
A4 / AA4 / E7
vin2a_de0
Video Input 2 Port A Field ID input
I
B10 / C23 / G2 / H6
/ P7 / V7
vin2a_fld0
Video Input 2 Port A Field ID input
I
D11 / F21 / G2 / H7
/ J7 / P9 / W2
vin2a_hsync0
Video Input 2 Port A Horizontal Sync input
I
C11 / E21 / G1 / P7
/ R3 / U7
vin2a_vsync0
Video Input 2 Port A Vertical Sync input
I
E11 / F20 / G6 / N1 /
T2 / V6
vin2b_clk1
Video Input 2 Port B Clock input
I
AB5 / H7 / M4 / P7
vin2b_d0
Video Input 2 Port B Data input
I
A4 / AD6 / K7
vin2b_d1
Video Input 2 Port B Data input
I
AC8 / B5 / M7
vin2b_d2
Video Input 2 Port B Data input
I
AC3 / B4 / J5
vin2b_d3
Video Input 2 Port B Data input
I
AC9 / B3 / K6
vin2b_d4
Video Input 2 Port B Data input
I
A3 / AC6 / J7
vin2b_d5
Video Input 2 Port B Data input
I
AC7 / C5 / J4
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Table 4-4. VIP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vin2b_d6
DESCRIPTION
Video Input 2 Port B Data input
I
AC4 / D6 / J6
vin2b_d7
Video Input 2 Port B Data input
I
AD4 / B2 / H4
vin2b_de1
Video Input 2 Port B Field ID input
I
AB8 / G2 / N6
vin2b_fld1
Video Input 2 Port B Field ID input
I
G2 / M4
vin2b_hsync1
Video Input 2 Port B Horizontal Sync input
I
AC5 / G1 / H5
vin2b_vsync1
Video Input 2 Port B Vertical Sync input
I
AB4 / G6 / H6
4.4.2
Display Subsystem – Video Output Ports
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in Table 7-16.
Table 4-5. DSS Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
DPI Video Output 1
vout1_clk
Video Output 1 Clock output
O
D11
vout1_de
Video Output 1 Data Enable output
O
B10
vout1_fld
Video Output 1 Field ID output. This signal is not used for embedded sync modes.
O
B11
vout1_hsync
Video Output 1 Horizontal Sync output. This signal is not used for embedded sync
modes.
O
C11
vout1_vsync
Video Output 1 Vertical Sync output. This signal is not used for embedded sync modes.
O
E11
vout1_d0
Video Output 1 Data output
O
F11
vout1_d1
Video Output 1 Data output
O
G10
vout1_d2
Video Output 1 Data output
O
F10
vout1_d3
Video Output 1 Data output
O
G11
vout1_d4
Video Output 1 Data output
O
E9
vout1_d5
Video Output 1 Data output
O
F9
vout1_d6
Video Output 1 Data output
O
F8
vout1_d7
Video Output 1 Data output
O
E7
vout1_d8
Video Output 1 Data output
O
E8
vout1_d9
Video Output 1 Data output
O
D9
vout1_d10
Video Output 1 Data output
O
D7
vout1_d11
Video Output 1 Data output
O
D8
vout1_d12
Video Output 1 Data output
O
A5
vout1_d13
Video Output 1 Data output
O
C6
vout1_d14
Video Output 1 Data output
O
C8
vout1_d15
Video Output 1 Data output
O
C7
vout1_d16
Video Output 1 Data output
O
B7
vout1_d17
Video Output 1 Data output
O
B8
vout1_d18
Video Output 1 Data output
O
A7
vout1_d19
Video Output 1 Data output
O
A8
vout1_d20
Video Output 1 Data output
O
C9
vout1_d21
Video Output 1 Data output
O
A9
vout1_d22
Video Output 1 Data output
O
B9
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Table 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
Video Output 1 Data output
O
A10
vout2_clk
Video Output 2 Clock output
O
H7 / B26
vout2_de
Video Output 2 Data Enable output
O
G2 / C23
vout1_d23
DESCRIPTION
DPI Video Output 2
vout2_fld
Video Output 2 Field ID output. This signal is not used for embedded sync modes.
O
E1 / F21
vout2_hsync
Video Output 2 Horizontal Sync output. This signal is not used for embedded sync
modes.
O
G1 / E21
vout2_vsync
Video Output 2 Vertical Sync output. This signal is not used for embedded sync modes.
O
G6 / F20
vout2_d0
Video Output 2 Data output
O
A4 / B14
vout2_d1
Video Output 2 Data output
O
B5 / J14
vout2_d2
Video Output 2 Data output
O
B4 / G13
vout2_d3
Video Output 2 Data output
O
B3 / J11
vout2_d4
Video Output 2 Data output
O
A3 / E12
vout2_d5
Video Output 2 Data output
O
C5 / F13
vout2_d6
Video Output 2 Data output
O
D6 / C12
vout2_d7
Video Output 2 Data output
O
B2 / D12
vout2_d8
Video Output 2 Data output
O
C4 / E15
vout2_d9
Video Output 2 Data output
O
C3 / A20
vout2_d10
Video Output 2 Data output
O
C2 / B15
vout2_d11
Video Output 2 Data output
O
D5 / A15
vout2_d12
Video Output 2 Data output
O
F6 / D15
vout2_d13
Video Output 2 Data output
O
D3 / B16
vout2_d14
Video Output 2 Data output
O
E6 / B17
vout2_d15
Video Output 2 Data output
O
F5 / A17
vout2_d16
Video Output 2 Data output
O
E4 / C18
vout2_d17
Video Output 2 Data output
O
C1 / A21
vout2_d18
Video Output 2 Data output
O
F4 / G16
vout2_d19
Video Output 2 Data output
O
D2 / D17
vout2_d20
Video Output 2 Data output
O
E2 / AA3
vout2_d21
Video Output 2 Data output
O
D1 / AB9
vout2_d22
Video Output 2 Data output
O
F3 / AB3
vout2_d23
Video Output 2 Data output
O
F2 / AA4
vout3_clk
Video Output 3 Clock output
O
P1
vout3_d0
Video Output 3 Data output
O
M6
vout3_d1
Video Output 3 Data output
O
M2
vout3_d2
Video Output 3 Data output
O
L5
vout3_d3
Video Output 3 Data output
O
M1
vout3_d4
Video Output 3 Data output
O
L6
vout3_d5
Video Output 3 Data output
O
L4
vout3_d6
Video Output 3 Data output
O
L3
vout3_d7
Video Output 3 Data output
O
L2
vout3_d8
Video Output 3 Data output
O
L1
vout3_d9
Video Output 3 Data output
O
K2
vout3_d10
Video Output 3 Data output
O
J1
vout3_d11
Video Output 3 Data output
O
J2
vout3_d12
Video Output 3 Data output
O
H1
vout3_d13
Video Output 3 Data output
O
J3
DPI Video Output 3
92
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Table 4-5. DSS Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
vout3_d14
DESCRIPTION
Video Output 3 Data output
O
H2
vout3_d15
Video Output 3 Data output
O
H3
vout3_d16
Video Output 3 Data output
O
R6
vout3_d17
Video Output 3 Data output
O
T9
vout3_d18
Video Output 3 Data output
O
T6
vout3_d19
Video Output 3 Data output
O
T7
vout3_d20
Video Output 3 Data output
O
P6
vout3_d21
Video Output 3 Data output
O
R9
vout3_d22
Video Output 3 Data output
O
R5
vout3_d23
Video Output 3 Data output
O
P5
vout3_de
Video Output 3 Data Enable output
O
N9
vout3_fld
Video Output 3 Field ID output. This signal is not used for embedded sync modes.
O
P9
vout3_hsync
Video Output 3 Horizontal Sync output. This signal is not used for embedded sync
modes.
O
N7
vout3_vsync
Video Output 3 Vertical Sync output. This signal is not used for embedded sync modes.
O
R4
4.4.3
Display Subsystem – High-Definition Multimedia Interface (HDMI)
NOTE
For more information, see the Display Subsystem / Display Subsystem Overview of the
device TRM.
Table 4-6. HDMI Signal Descriptions
SIGNAL NAME
DESCRIPTION
hdmi1_cec
HDMI consumer electronic control
hdmi1_hpd
HDMI display hot plug detect
TYPE
BALL
IOD
B20/ G19
IO
B21/ G20
hdmi1_ddc_scl
HDMI display data channel clock
IOD
C25
hdmi1_ddc_sda
HDMI display data channel data
IOD
F17
hdmi1_clockx
HDMI clock differential positive or negative
ODS
AG16
hdmi1_clocky
HDMI clock differential positive or negative
ODS
AH16
hdmi1_data2x
HDMI data 2 differential positive or negative
ODS
AG19
hdmi1_data2y
HDMI data 2 differential positive or negative
ODS
AH19
hdmi1_data1x
HDMI data 1 differential positive or negative
ODS
AG18
hdmi1_data1y
HDMI data 1 differential positive or negative
ODS
AH18
hdmi1_data0x
HDMI data 0 differential positive or negative
ODS
AG17
hdmi1_data0y
HDMI data 0 differential positive or negative
ODS
AH17
4.4.4
Camera Serial Interface 2 CAL bridge (CSI2)
NOTE
For more information, see the CAL Subsystem / CAL Subsystem Overview of the device
TRM.
Table 4-7. CSI 2 Signal Descriptions
SIGNAL NAME
csi2_0_dx0
DESCRIPTION
Serial data/clock input - line 0 (position 1)
TYPE
BALL
I
AE1
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Table 4-7. CSI 2 Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
csi2_0_dy0
DESCRIPTION
Serial data/clock input - line 0 (position 1)
I
AD2
csi2_0_dx1
Serial data/clock input - line 1 (position 2)
I
AF1
csi2_0_dy1
Serial data/clock input - line 1 (position 2)
I
AE2
csi2_0_dx2
Serial data/clock input - line 2 (position 3)
I
AF2
csi2_0_dy2
Serial data/clock input - line 2 (position 3)
I
AF3
csi2_0_dx3
Serial data/clock input - line 3 (position 4)
I
AH4
csi2_0_dy3
Serial data/clock input - line 3 (position 4)
I
AG4
csi2_0_dx4
Serial data input only - line 4 (position 5)
(1)
I
AH3
csi2_0_dy4
Serial data input only - line 4 (position 5) (1)
I
AG3
csi2_1_dx0
Serial data/clock input - line 0 (position 1)
I
AG5
csi2_1_dy0
Serial data/clock input - line 0 (position 1)
I
AH5
csi2_1_dx1
Serial data/clock input - line 1 (position 2)
I
AG6
csi2_1_dy1
Serial data/clock input - line 1 (position 2)
I
AH6
csi2_1_dx2
Serial data/clock input - line 2 (position 3)
I
AH7
csi2_1_dy2
Serial data/clock input - line 2 (position 3)
I
AG7
(1) Line 4 (position 5) supports only data. For more information see CAL Subsystem of the device TRM.
4.4.5
External Memory Interface (EMIF)
NOTE
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
NOTE
Dual rank support is not available on this device, but signal names are retained for
consistency with the DRA7xx family of devices.
NOTE
ECC is not available on this device, but signal names are retained for consistency with the
DRA7xx family of devices.
NOTE
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-8,
EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of
SDRAM memories.
Table 4-8. EMIF Signal Descriptions
SIGNAL NAME
94
DESCRIPTION
TYPE
BALL
AH23
ddr1_csn0
EMIF1 Chip Select 0
O
ddr1_csn1
EMIF1 Chip Select 1
O
AB16
ddr1_cke
EMIF1 Clock Enable
O
AG22
ddr1_ck
EMIF1 Clock
O
AG24
ddr1_nck
EMIF1 Negative Clock
O
AH24
ddr1_odt0
EMIF1 On-Die Termination for Chip Select 0
O
AE20
ddr1_odt1
EMIF1 On-Die Termination for Chip Select 1
O
AC17
Terminal Configuration and Functions
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Table 4-8. EMIF Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
ddr1_casn
DESCRIPTION
EMIF1 Column Address Strobe
O
AC18
ddr1_rasn
EMIF1 Row Address Strobe
O
AF20
ddr1_wen
EMIF1 Write Enable
O
AH21
ddr1_rst
EMIF1 Reset output (DDR3-SDRAM only)
O
AG21
ddr1_ba0
EMIF1 Bank Address
O
AF17
ddr1_ba1
EMIF1 Bank Address
O
AE18
ddr1_ba2
EMIF1 Bank Address
O
AB18
ddr1_a0
EMIF1 Address Bus
O
AD20
ddr1_a1
EMIF1 Address Bus
O
AC19
ddr1_a2
EMIF1 Address Bus
O
AC20
ddr1_a3
EMIF1 Address Bus
O
AB19
ddr1_a4
EMIF1 Address Bus
O
AF21
ddr1_a5
EMIF1 Address Bus
O
AH22
ddr1_a6
EMIF1 Address Bus
O
AG23
ddr1_a7
EMIF1 Address Bus
O
AE21
ddr1_a8
EMIF1 Address Bus
O
AF22
ddr1_a9
EMIF1 Address Bus
O
AE22
ddr1_a10
EMIF1 Address Bus
O
AD21
ddr1_a11
EMIF1 Address Bus
O
AD22
ddr1_a12
EMIF1 Address Bus
O
AC21
ddr1_a13
EMIF1 Address Bus
O
AF18
ddr1_a14
EMIF1 Address Bus
O
AE17
ddr1_a15
EMIF1 Address Bus
O
AD18
ddr1_d0
EMIF1 Data Bus
IO
AF25
ddr1_d1
EMIF1 Data Bus
IO
AF26
ddr1_d2
EMIF1 Data Bus
IO
AG26
ddr1_d3
EMIF1 Data Bus
IO
AH26
ddr1_d4
EMIF1 Data Bus
IO
AF24
ddr1_d5
EMIF1 Data Bus
IO
AE24
ddr1_d6
EMIF1 Data Bus
IO
AF23
ddr1_d7
EMIF1 Data Bus
IO
AE23
ddr1_d8
EMIF1 Data Bus
IO
AC23
ddr1_d9
EMIF1 Data Bus
IO
AF27
ddr1_d10
EMIF1 Data Bus
IO
AG27
ddr1_d11
EMIF1 Data Bus
IO
AF28
ddr1_d12
EMIF1 Data Bus
IO
AE26
ddr1_d13
EMIF1 Data Bus
IO
AC25
ddr1_d14
EMIF1 Data Bus
IO
AC24
ddr1_d15
EMIF1 Data Bus
IO
AD25
ddr1_d16
EMIF1 Data Bus
IO
V20
ddr1_d17
EMIF1 Data Bus
IO
W20
ddr1_d18
EMIF1 Data Bus
IO
AB28
ddr1_d19
EMIF1 Data Bus
IO
AC28
ddr1_d20
EMIF1 Data Bus
IO
AC27
ddr1_d21
EMIF1 Data Bus
IO
Y19
ddr1_d22
EMIF1 Data Bus
IO
AB27
ddr1_d23
EMIF1 Data Bus
IO
Y20
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Table 4-8. EMIF Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
ddr1_d24
EMIF1 Data Bus
IO
AA23
ddr1_d25
EMIF1 Data Bus
IO
Y22
ddr1_d26
EMIF1 Data Bus
IO
Y23
ddr1_d27
EMIF1 Data Bus
IO
AA24
ddr1_d28
EMIF1 Data Bus
IO
Y24
ddr1_d29
EMIF1 Data Bus
IO
AA26
ddr1_d30
EMIF1 Data Bus
IO
AA25
ddr1_d31
EMIF1 Data Bus
IO
AA28
ddr1_ecc_d0
EMIF1 ECC Data Bus
IO
W22
ddr1_ecc_d1
EMIF1 ECC Data Bus
IO
V23
ddr1_ecc_d2
EMIF1 ECC Data Bus
IO
W19
ddr1_ecc_d3
EMIF1 ECC Data Bus
IO
W23
ddr1_ecc_d4
EMIF1 ECC Data Bus
IO
Y25
ddr1_ecc_d5
EMIF1 ECC Data Bus
IO
V24
ddr1_ecc_d6
EMIF1 ECC Data Bus
IO
V25
ddr1_ecc_d7
EMIF1 ECC Data Bus
IO
Y26
ddr1_dqm0
EMIF1 Data Mask
O
AD23
ddr1_dqm1
EMIF1 Data Mask
O
AB23
ddr1_dqm2
EMIF1 Data Mask
O
AC26
ddr1_dqm3
EMIF1 Data Mask
O
AA27
EMIF1 ECC Data Mask
O
V26
ddr1_dqs0
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AH25
ddr1_dqsn0
Data strobe 0 invert
IO
AG25
ddr1_dqs1
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AE27
ddr1_dqsn1
Data strobe 1 invert
IO
AE28
ddr1_dqs2
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AD27
ddr1_dqsn2
Data strobe 2 invert
IO
AD28
ddr1_dqs3
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
Y28
ddr1_dqsn3
ddr1_dqm_ecc
Data strobe 3 invert
IO
Y27
ddr1_dqs_ecc
EMIF1 ECC Data strobe input/output. This signal is output to the EMIF1 memory when
writing and input when reading.
IO
V27
ddr1_dqsn_ecc
EMIF1 ECC Complementary Data strobe
IO
V28
Reference Power Supply EMIF1
A
Y18
ddr1_vref0
4.4.6
General-Purpose Memory Controller (GPMC)
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
Table 4-9. GPMC Signal Descriptions
SIGNAL NAME
gpmc_ad0
96
DESCRIPTION
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
Terminal Configuration and Functions
TYPE
BALL
IO
M6
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Table 4-9. GPMC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpmc_ad1
DESCRIPTION
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
M2
gpmc_ad2
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
IO
L5
gpmc_ad3
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
IO
M1
gpmc_ad4
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
IO
L6
gpmc_ad5
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
IO
L4
gpmc_ad6
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
IO
L3
gpmc_ad7
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
IO
L2
gpmc_ad8
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
IO
L1
gpmc_ad9
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
IO
K2
gpmc_ad10
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
IO
J1
gpmc_ad11
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
IO
J2
gpmc_ad12
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
IO
H1
gpmc_ad13
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
IO
J3
gpmc_ad14
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
IO
H2
gpmc_ad15
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
IO
H3
gpmc_a0
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
O
R6 / P4
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
O
T9 / P1
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
O
T6 / N1
gpmc_a3
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
O
T7 / M4
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
O
P6
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
O
R9
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
O
R5
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
O
P5
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
O
N7
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
O
R4
gpmc_a10
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
O
N9
gpmc_a11
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P9
gpmc_a12
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P4
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Table 4-9. GPMC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpmc_a13
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
R3 / K7 / P2
gpmc_a14
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
T2 / M7 / P1
gpmc_a15
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
U2 / J5 / N2
gpmc_a16
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
U1 / K6 / R6
gpmc_a17
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
P3 / J7 / E1
gpmc_a18
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
R2 / J4 / H7
gpmc_a19
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K7 / J6
gpmc_a20
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
M7 / H4
gpmc_a21
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
J5 / H5
gpmc_a22
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
K6 / H6
gpmc_a23
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
F6 / J7 / N1 / P2
gpmc_a24
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
D3 / J4 / P1
gpmc_a25
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
E6 / J6 / N2
gpmc_a26
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
O
F5 / H4 / R6
gpmc_a27
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
O
G1 / H5 / E1 / H7
gpmc_cs0
GPMC Chip Select 0 (active low)
O
T1
gpmc_cs1
GPMC Chip Select 1 (active low)
O
H6
gpmc_cs2
GPMC Chip Select 2 (active low)
O
P2
gpmc_cs3
GPMC Chip Select 3 (active low)
O
P1
gpmc_cs4
GPMC Chip Select 4 (active low)
O
N6
gpmc_cs5
GPMC Chip Select 5 (active low)
O
M4
gpmc_cs6
GPMC Chip Select 6 (active low)
O
N1
gpmc_cs7
GPMC Chip Select 7 (active low)
O
P7
GPMC Clock output
IO
P7
gpmc_advn_ale
GPMC address valid active low or address latch enable
O
N1
gpmc_oen_ren
gpmc_clk(1)(2)
DESCRIPTION
GPMC output enable active low or read enable
O
M5
gpmc_wen
GPMC write enable active low
O
M3
gpmc_ben0
GPMC lower-byte enable active low
O
N6
M4
gpmc_ben1
GPMC upper-byte enable active low
O
gpmc_wait0
GPMC external indication of wait 0
I
N2
gpmc_wait1
GPMC external indication of wait 1
I
P7 / N1
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See Table 7-23 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and Table 7-25
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
98
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4.4.7
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Timers
NOTE
For more information, see the Timers section of the device TRM.
Table 4-10. Timers Signal Descriptions
SIGNAL NAME
TYPE
BALL
timer1
PWM output/event trigger input
IO
M4 / E21
timer2
PWM output/event trigger input
IO
N6 / F20
timer3
PWM output/event trigger input
IO
N1 / F21
timer4
PWM output/event trigger input
IO
P7 / D12
timer5
PWM output/event trigger input
IO
U2 / B12
timer6
PWM output/event trigger input
IO
T2 / A11
timer7
PWM output/event trigger input
IO
R3 / B13
timer8
PWM output/event trigger input
IO
P4 / A12
timer9
PWM output/event trigger input
IO
P9 / E14
timer10
PWM output/event trigger input
IO
N9 / A13
timer11
PWM output/event trigger input
IO
R4 / G14
timer12
PWM output/event trigger input
IO
N7 / F14
timer13
PWM output/event trigger input
IO
D18
timer14
PWM output/event trigger input
IO
E17
timer15
PWM output/event trigger input
IO
AC10 / B26
timer16
PWM output/event trigger input
IO
AB10 / C23
4.4.8
DESCRIPTION
Inter-Integrated Circuit Interface (I2C)
NOTE
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C
Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.
NOTE
I2C1 and I2C2 do NOT support HS-mode.
Table 4-11. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 1 (I2C1)
i2c1_scl
I2C1 Clock
IOD
C20
i2c1_sda
I2C1 Data
IOD
C21
Inter-Integrated Circuit Interface 2 (I2C2)
i2c2_scl
I2C2 Clock
IOD
F17
i2c2_sda
I2C2 Data
IOD
C25
Inter-Integrated Circuit Interface 3 (I2C3)
i2c3_scl
I2C3 Clock
IOD
P7/ D14/ AB4/ F20
i2c3_sda
I2C3 Data
IOD
N1/ C14/ AC5/ E21
Inter-Integrated Circuit Interface 4 (I2C4)
i2c4_scl
I2C4 Clock
IOD
R6/ J14/ A21/ Y9
i2c4_sda
I2C4 Data
IOD
T9/ B14/ C18/ W7
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Table 4-11. I2C Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 5 (I2C5)
i2c5_scl
I2C5 Clock
IOD
AB9/ P6/ F12
i2c5_sda
I2C5 Data
IOD
AA3/ R9/ G12
Inter-Integrated Circuit Interface 6 (I2C6)
4.4.9
i2c6_scl
I2C6 Clock
IOD
G16
i2c6_sda
I2C6 Data
IOD
D17
HDQ / 1-Wire Interface (HDQ1W)
NOTE
For more information, see the Serial Communication Interface / HDQ/1-Wire section of the
device TRM.
Table 4-12. HDQ / 1-Wire Signal Descriptions
SIGNAL NAME
hdq0
DESCRIPTION
HDQ or 1-wire protocol single interface pin
TYPE
BALL
IOD
D18/ C23
4.4.10 Universal Asynchronous Receiver Transmitter (UART)
NOTE
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Perypheral Booting / Initialization Phase for UART Boot section of the device
TRM.
Table 4-13. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
I
D28
Universal Asynchronous Receiver/Transmitter 1 (UART1)
uart1_dcdn
UART1 Data Carrier Detect active low
uart1_dsrn
UART1 Data Set Ready Active Low
I
D26
uart1_dtrn
UART1 Data Terminal Ready Active Low
O
D27
uart1_rin
UART1 Ring Indicator
I
C28
uart1_rxd
UART1 Receive Data
I
B27
C26
uart1_txd
UART1 Transmit Data
O
uart1_ctsn
UART1 clear to send active low
I
E25
uart1_rtsn
UART1 request to send active low
O
C27
Universal Asynchronous Receiver/Transmitter 2 (UART2)
uart2_rxd
UART2 Receive Data
I
D28
uart2_txd
UART2 Transmit Data
O
D26
uart2_ctsn
UART2 clear to send active low
I
D27
uart2_rtsn
UART2 request to send active low
O
C28
Universal Asynchronous Receiver/Transmitter 3 (UART3)/IrDA
100
uart3_rxd
UART3 Receive Data
I
V2/ AB3/ A26 / D27
uart3_txd
UART3 Transmit Data
O
Y1/ AA4/ B22/ C28
uart3_ctsn
UART3 clear to send active low
I
U4/ W9/ G17/ D28
uart3_rtsn
UART3 request to send active low
O
V1/ V9/ D26/ B24
uart3_rctx
Remote control data
O
D28
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Table 4-13. UART Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
uart3_sd
DESCRIPTION
Infrared transceiver configure/shutdown
O
D26
uart3_irrx
Infrared data input. Also functions as uart3_rxd Receive Data Input when IrDA
mode is not used.
I
D27
uart3_irtx
Infrared data output
O
C28
Universal Asynchronous Receiver/Transmitter 4 (UART4)
uart4_rxd
UART4 Receive Data
I
V7/ G16/ B21
uart4_txd
UART4 Transmit Data
O
U7/ D17/ B20
uart4_ctsn
UART4 clear to send active low
I
V6
uart4_rtsn
UART4 request to send active low
O
U6
Universal Asynchronous Receiver/Transmitter 5 (UART5)
uart5_rxd
UART5 Receive Data
I
R6/ F11/ B19/ AC7/
G17
uart5_txd
UART5 Transmit Data
O
T9/ G10/ C17/ AC6/
B24
uart5_ctsn
UART5 clear to send active low
I
T6 / AC9
uart5_rtsn
UART5 request to send active low
O
T7 / AC3
Universal Asynchronous Receiver/Transmitter 6 (UART6)
uart6_rxd
UART6 Receive Data
I
P6/ E8/ G12/ W7
uart6_txd
UART6 Transmit Data
O
R9/ D9/ F12/ Y9
uart6_ctsn
UART6 clear to send active low
I
R5 / G13
uart6_rtsn
UART6 request to send active low
O
P5 / J11
Universal Asynchronous Receiver/Transmitter 7 (UART7)
uart7_rxd
UART7 Receive Data
I
B18 / B7 / T6
uart7_txd
UART7 Transmit Data
O
B8 / F15 / T7
uart7_ctsn
UART7 clear to send active low
I
B19
uart7_rtsn
UART7 request to send active low
O
C17
Universal Asynchronous Receiver/Transmitter 8 (UART8)
uart8_rxd
UART8 Receive Data
I
C18 / G20 / R5
uart8_txd
UART8 Transmit Data
O
A21 / G19 / P5
uart8_ctsn
UART8 clear to send active low
I
G16
uart8_rtsn
UART8 request to send active low
O
D17
Universal Asynchronous Receiver/Transmitter 9 (UART9)
uart9_rxd
UART9 Receive Data
I
G1/ AA3/ E25
uart9_txd
UART9 Transmit Data
O
G6/ AB9/ C27
uart9_ctsn
UART9 clear to send active low
I
F2 / AB3
uart9_rtsn
UART9 request to send active low
O
F3/ AA4
Universal Asynchronous Receiver/Transmitter 10 (UART10)
uart10_rxd
UART10 Receive Data
I
D1/ E21/ AC8/ D27
uart10_txd
UART10 Transmit Data
O
E2/ F20/ AD6/ C28
uart10_ctsn
UART10 clear to send active low
I
D2 / AB8
uart10_rtsn
UART10 request to send active low
O
F4 / AB5
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4.4.11 Multichannel Serial Peripheral Interface (McSPI)
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are applicable for all combinations of signals for SPI1 and SPI2.
However, the timings are valid only for SPI3 and SPI4 if signals within a single
IOSET are used. The IOSETS are defined in Table 7-42.
NOTE
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (McSPI) section of the device TRM.
Table 4-14. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
SPI1 Clock
IO
A25
spi1_d1
SPI1 Data. Can be configured as either MISO or MOSI.
IO
F16
spi1_d0
SPI1 Data. Can be configured as either MISO or MOSI.
IO
B25
spi1_cs0
SPI1 Chip Select
IO
A24
spi1_cs1
SPI1 Chip Select
IO
A22
spi1_cs2
SPI1 Chip Select
IO
B21
spi1_cs3
SPI1 Chip Select
IO
B20
A26
Serial Peripheral Interface 1
spi1_sclk(1)
Serial Peripheral Interface 2
spi2_sclk(1)
SPI2 Clock
IO
spi2_d1
SPI2 Data. Can be configured as either MISO or MOSI.
IO
B22
spi2_d0
SPI2 Data. Can be configured as either MISO or MOSI.
IO
G17
spi2_cs0
SPI2 Chip Select
IO
B24
spi2_cs1
SPI2 Chip Select
IO
A22
spi2_cs2
SPI2 Chip Select
IO
B21
spi2_cs3
SPI2 Chip Select
IO
B20
SPI3 Clock
IO
AC4 / B12 / C18 /
E11 / V2
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
IO
A11 / A21 / AC7 /
B10 / Y1
spi3_d0
SPI3 Data. Can be configured as either MISO or MOSI.
IO
AC6 / B13 / C11 /
G16 / W9
spi3_cs0
SPI3 Chip Select
IO
A12 / AC9 / D11 /
D17 / V9
spi3_cs1
SPI3 Chip Select
IO
AC3 / B11 / E14
spi3_cs2
SPI3 Chip Select
IO
F11
spi3_cs3
SPI3 Chip Select
IO
A10
SPI4 Clock
IO
N7/ G1/ AA3/ V7/
AC8
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
IO
R4/ G6/ AB9/ U7/
AD6
spi4_d0
SPI4 Data. Can be configured as either MISO or MOSI.
IO
N9/ F2/ AB3/ V6/
AB8
Serial Peripheral Interface 3
spi3_sclk(1)
Serial Peripheral Interface 4
spi4_sclk(1)
102
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Table 4-14. SPI Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
spi4_cs0
DESCRIPTION
SPI4 Chip Select
IO
P9/ F3/ AA4/ U6/
AB5
spi4_cs1
SPI4 Chip Select
IO
P4 / Y1
spi4_cs2
SPI4 Chip Select
IO
R3 / W9
spi4_cs3
SPI4 Chip Select
IO
T2 / V9
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.12 Quad Serial Peripheral Interface (QSPI)
NOTE
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM.
Table 4-15. QSPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
IO
R2
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
I
R3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
U1
qspi1_d1
QSPI1 Data[1]. Input read data in all modes.
IO
P3
qspi1_d2
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
IO
U2
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
IO
T2
qspi1_cs0
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
IO
P2
qspi1_cs1
QSPI1 Chip Select[1]
O
P1
qspi1_cs2
QSPI1 Chip Select[2]
O
T7
qspi1_cs3
QSPI1 Chip Select[3]
O
P6
qspi1_sclk
QSPI1 Serial Clock
qspi1_rtclk
4.4.13 Multicannel Audio Serial Port (McASP)
NOTE
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the device TRM.
Table 4-16. McASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
G12
Multichannel Audio Serial Port 1
mcasp1_axr0
McASP1 Transmit/Receive Data
IO
mcasp1_axr1
McASP1 Transmit/Receive Data
IO
F12
mcasp1_axr2
McASP1 Transmit/Receive Data
IO
G13
mcasp1_axr3
McASP1 Transmit/Receive Data
IO
J11
mcasp1_axr4
McASP1 Transmit/Receive Data
IO
D18/ E12
mcasp1_axr5
McASP1 Transmit/Receive Data
IO
E17 / F13
mcasp1_axr6
McASP1 Transmit/Receive Data
IO
B26 / C12
mcasp1_axr7
McASP1 Transmit/Receive Data
IO
C23 / D12
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Table 4-16. McASP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mcasp1_axr8
DESCRIPTION
McASP1 Transmit/Receive Data
IO
E21 / B12
mcasp1_axr9
McASP1 Transmit/Receive Data
IO
F20/ A11
mcasp1_axr10
McASP1 Transmit/Receive Data
IO
F21 / B13
mcasp1_axr11
McASP1 Transmit/Receive Data
IO
A12
mcasp1_axr12
McASP1 Transmit/Receive Data
IO
E14
mcasp1_axr13
McASP1 Transmit/Receive Data
IO
A13
mcasp1_axr14
McASP1 Transmit/Receive Data
IO
G14
mcasp1_axr15
McASP1 Transmit/Receive Data
IO
F14
mcasp1_fsx
McASP1 Transmit Frame Sync
IO
D14
McASP1 Receive Bit Clock
IO
B14
McASP1 Receive Frame Sync
IO
J14
mcasp1_aclkr(1)
mcasp1_fsr
mcasp1_ahclkx
McASP1 Transmit High-Frequency Master Clock
O
D18
mcasp1_aclkx(1)
McASP1 Transmit Bit Clock
IO
C14
B15
Multichannel Audio Serial Port 2
mcasp2_axr0
McASP2 Transmit/Receive Data
IO
mcasp2_axr1
McASP2 Transmit/Receive Data
IO
A15
mcasp2_axr2
McASP2 Transmit/Receive Data
IO
C15
mcasp2_axr3
McASP2 Transmit/Receive Data
IO
A16
mcasp2_axr4
McASP2 Transmit/Receive Data
IO
D15
mcasp2_axr5
McASP2 Transmit/Receive Data
IO
B16
mcasp2_axr6
McASP2 Transmit/Receive Data
IO
B17
mcasp2_axr7
McASP2 Transmit/Receive Data
IO
A17
mcasp2_axr8
McASP2 Transmit/Receive Data
IO
D18
mcasp2_axr9
McASP2 Transmit/Receive Data
IO
E17
mcasp2_axr10
McASP2 Transmit/Receive Data
IO
B26
mcasp2_axr11
McASP2 Transmit/Receive Data
IO
C23
mcasp2_axr12
McASP2 Transmit/Receive Data
IO
B18
mcasp2_axr13
McASP2 Transmit/Receive Data
IO
F15
mcasp2_axr14
McASP2 Transmit/Receive Data
IO
B19
mcasp2_axr15
McASP2 Transmit/Receive Data
IO
C17
mcasp2_fsx
McASP2 Transmit Frame Sync
IO
A18
McASP2 Receive Bit Clock
IO
E15
McASP2 Receive Frame Sync
IO
A20
McASP2 Transmit High-Frequency Master Clock
O
E17
McASP2 Transmit Bit Clock
IO
A19
(1)
mcasp2_aclkr
mcasp2_fsr
mcasp2_ahclkx
(1)
mcasp2_aclkx
Multichannel Audio Serial Port 3
mcasp3_axr0
McASP3 Transmit/Receive Data
IO
B19
mcasp3_axr1
McASP3 Transmit/Receive Data
IO
C17
mcasp3_axr2
McASP3 Transmit/Receive Data
IO
C15
mcasp3_axr3
McASP3 Transmit/Receive Data
IO
A16
mcasp3_fsx
McASP3 Transmit Frame Sync
IO
F15
mcasp3_ahclkx
McASP3 Transmit High-Frequency Master Clock
O
B26
mcasp3_aclkx(1)
McASP3 Transmit Bit Clock
IO
B18
mcasp3_aclkr(1)
McASP3 Receive Bit Clock
IO
B18
McASP3 Receive Frame Sync
IO
F15
IO
G16
mcasp3_fsr
Multichannel Audio Serial Port 4
mcasp4_axr0
104
McASP4 Transmit/Receive Data
Terminal Configuration and Functions
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Table 4-16. McASP Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mcasp4_axr1
DESCRIPTION
McASP4 Transmit/Receive Data
IO
D17
mcasp4_axr2
McASP4 Transmit/Receive Data
IO
E12
mcasp4_axr3
McASP4 Transmit/Receive Data
IO
F13
mcasp4_fsx
McASP4 Transmit Frame Sync
IO
A21
mcasp4_ahclkx
McASP4 Transmit High-Frequency Master Clock
O
C23
mcasp4_aclkx(1)
McASP4 Transmit Bit Clock
IO
C18
mcasp4_aclkr(1)
McASP4 Receive Bit Clock
IO
C18
McASP4 Receive Frame Sync
IO
A21
mcasp4_fsr
Multichannel Audio Serial Port 5
mcasp5_axr0
McASP5 Transmit/Receive Data
IO
AB3
mcasp5_axr1
McASP5 Transmit/Receive Data
IO
AA4
mcasp5_axr2
McASP5 Transmit/Receive Data
IO
C12
mcasp5_axr3
McASP5 Transmit/Receive Data
IO
D12
mcasp5_fsx
McASP5 Transmit Frame Sync
IO
AB9
mcasp5_ahclkx
McASP5 Transmit High-Frequency Master Clock
O
D18
mcasp5_aclkx(1)
McASP5 Transmit Bit Clock
IO
AA3
mcasp5_aclkr(1)
McASP5 Receive Bit Clock
IO
AA3
McASP5 Receive Frame Sync
IO
AB9
mcasp5_fsr
Multichannel Audio Serial Port 6
mcasp6_axr0
McASP6 Transmit/Receive Data
IO
B12
mcasp6_axr1
McASP6 Transmit/Receive Data
IO
A11
mcasp6_axr2
McASP6 Transmit/Receive Data
IO
G13
mcasp6_axr3
McASP6 Transmit/Receive Data
IO
J11
mcasp6_ahclkx
McASP6 Transmit High-Frequency Master Clock
O
E17
mcasp6_aclkx(1)
McASP6 Transmit Bit Clock
IO
B13
McASP6 Transmit Frame Sync
IO
A12
McASP6 Receive Bit Clock
IO
B13
McASP6 Receive Frame Sync
IO
A12
mcasp6_fsx
mcasp6_aclkr(1)
mcasp6_fsr
Multichannel Audio Serial Port 7
mcasp7_axr0
McASP7 Transmit/Receive Data
IO
E14
mcasp7_axr1
McASP7 Transmit/Receive Data
IO
A13
mcasp7_axr2
McASP7 Transmit/Receive Data
IO
B14
mcasp7_axr3
McASP7 Transmit/Receive Data
IO
J14
mcasp7_ahclkx
McASP7 Transmit High-Frequency Master Clock
O
B26
mcasp7_aclkx(1)
McASP7 Transmit Bit Clock
IO
G14
McASP7 Transmit Frame Sync
IO
F14
McASP7 Receive Bit Clock
IO
G14
McASP7 Receive Frame Sync
IO
F14
mcasp7_fsx
mcasp7_aclkr(1)
mcasp7_fsr
Multichannel Audio Serial Port 8
mcasp8_axr0
McASP8 Transmit/Receive Data
IO
D15
mcasp8_axr1
McASP8 Transmit/Receive Data
IO
B16
mcasp8_axr2
McASP8 Transmit/Receive Data
IO
E15
mcasp8_axr3
McASP8 Transmit/Receive Data
IO
A20
mcasp8_ahclkx
McASP8 Transmit High-Frequency Master Clock
O
C23
mcasp8_aclkx(1)
McASP8 Transmit Bit Clock
IO
B17
McASP8 Transmit Frame Sync
IO
A17
McASP8 Receive Bit Clock
IO
B17
mcasp8_fsx
mcasp8_aclkr(1)
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Table 4-16. McASP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
mcasp8_fsr
McASP8 Receive Frame Sync
TYPE
BALL
IO
A17
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
4.4.14 Universal Serial Bus (USB)
NOTE
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
Table 4-17. Universal Serial Bus Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
usb1_dp
USB1 USB2.0 differential signal pair (positive)
IODS
AD12
usb1_dm
USB1 USB2.0 differential signal pair (negative)
IODS
AC12
O
AB10
Universal Serial Bus 1
usb1_drvvbus
USB1 Drive VBUS signal
(1)
usb_rxn0
USB1 USB3.0 receiver negative lane
IDS
AF12
usb_rxp0(1)
USB1 USB3.0 receiver positive lane
IDS
AE12
usb_txn0(1)
USB1 USB3.0 transmitter negative lane
ODS
AC11
usb_txp0(1)
USB1 USB3.0 transmitter positive lane
ODS
AD11
Universal Serial Bus 2
usb2_dp
USB2 USB2.0 differential signal pair (positive)
IO
AE11
usb2_dm
USB2 USB2.0 differential signal pair (negative)
IO
AF11
USB2 Drive VBUS signal
O
AC10
usb2_drvvbus
Universal Serial Bus 3
usb3_ulpi_d0
USB3 - ULPI 8-bit data bus
IODS
AC3 / V6
usb3_ulpi_d1
USB3 - ULPI 8-bit data bus
IODS
AC9 / U6
usb3_ulpi_d2
USB3 - ULPI 8-bit data bus
IO
AC6 / U5
usb3_ulpi_d3
USB3 - ULPI 8-bit data bus
IO
AC7 / V5
usb3_ulpi_d4
USB3 - ULPI 8-bit data bus
IO
AC4 / V4
usb3_ulpi_d5
USB3 - ULPI 8-bit data bus
IO
AD4 / V3
usb3_ulpi_d6
USB3 - ULPI 8-bit data bus
IO
AB4 / Y2
usb3_ulpi_d7
USB3 - ULPI 8-bit data bus
IO
AC5 / W2
usb3_ulpi_nxt
USB3 - ULPI next
I
AC8 / U7
usb3_ulpi_dir
USB3 - ULPI bus direction
I
AD6 / V7
usb3_ulpi_stp
USB3 - ULPI stop
O
AB8 / V9
usb3_ulpi_clk
USB3 - ULPI functional clock
I
AB5 / W9
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.4.15 SATA
NOTE
For more information, see the Serial Communication Interfaces / SATA section of the device
TRM.
106
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Table 4-18. SATA Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
sata1_rxn0
SATA differential negative receiver lane 0
IDS
AH9
sata1_rxp0
SATA differential positive receiver lane 0
IDS
AG9
sata1_txn0
SATA differential negative transmitter lane 0
ODS
AG10
sata1_txp0
SATA differential positive transmitter lane 0
ODS
AH10
sata1_led
SATA channel activity indicator
O
A22 / G19
4.4.16 Peripheral Component Interconnect Express (PCIe)
NOTE
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device
TRM.
Table 4-19. PCIe Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
AG13
pcie_rxn0
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.
IDS
pcie_rxp0
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.
IDS
AH13
pcie_txn0
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.
ODS
AG14
pcie_txp0
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.
ODS
AH14
pcie_rxn1
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IDS
AF12
pcie_rxp1
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IDS
AE12
pcie_txn1
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
ODS
AC11
pcie_txp1
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
ODS
AD11
ljcb_clkp
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(positive)
IODS
AG15
ljcb_clkn
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(negative)
IODS
AH15
4.4.17 Controller Area Network Interface (DCAN)
NOTE
For more information, see the Serial Communication Interface / DCAN section of the device
TRM.
Table 4-20. DCAN Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
DCAN 1
dcan1_tx
DCAN1 transmit data pin
IO
G20
dcan1_rx
DCAN1 receive data pin
IO
G19 / AD17
dcan2_tx
DCAN2 transmit data pin
IO
E21/ B21
dcan2_rx
DCAN2 receive data pin
IO
F20/ B20/ AC16
DCAN 2
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4.4.18 Ethernet Interface (GMAC_SW)
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in Table 7-72, Table 7-75, Table 7-80 and Table 7-87.
NOTE
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the device TRM.
Table 4-21. GMAC Signal Descriptions
SIGNAL NAME
108
TYPE
BALL
rgmii0_txc
DESCRIPTION
RGMII0 Transmit Clock
O
W9
rgmii0_txctl
RGMII0 Transmit Enable
O
V9
rgmii0_txd3
RGMII0 Transmit Data
O
V7
rgmii0_txd2
RGMII0 Transmit Data
O
U7
rgmii0_txd1
RGMII0 Transmit Data
O
V6
rgmii0_txd0
RGMII0 Transmit Data
O
U6
rgmii0_rxc
RGMII0 Receive Clock
I
U5
rgmii0_rxctl
RGMII0 Receive Control
I
V5
rgmii0_rxd3
RGMII0 Receive Data
I
V4
rgmii0_rxd2
RGMII0 Receive Data
I
V3
rgmii0_rxd1
RGMII0 Receive Data
I
Y2
rgmii0_rxd0
RGMII0 Receive Data
I
W2
rgmii1_txc
RGMII1 Transmit Clock
O
D5
rgmii1_txctl
RGMII1 Transmit Enable
O
C2
rgmii1_txd3
RGMII1 Transmit Data
O
C3
rgmii1_txd2
RGMII1 Transmit Data
O
C4
rgmii1_txd1
RGMII1 Transmit Data
O
B2
rgmii1_txd0
RGMII1 Transmit Data
O
D6
rgmii1_rxc
RGMII1 Receive Clock
I
C5
rgmii1_rxctl
RGMII1 Receive Control
I
A3
rgmii1_rxd3
RGMII1 Receive Data
I
B3
rgmii1_rxd2
RGMII1 Receive Data
I
B4
rgmii1_rxd1
RGMII1 Receive Data
I
B5
rgmii1_rxd0
RGMII1 Receive Data
I
A4
mii1_rxd1
MII1 Receive Data
I
C1
mii1_rxd2
MII1 Receive Data
I
E4
mii1_rxd3
MII1 Receive Data
I
F5
mii1_rxd0
MII1 Receive Data
I
E6
mii1_rxclk
MII1 Receive Clock
I
D5
mii1_rxdv
MII1 Receive Data Valid
I
C2
mii1_txclk
MII1 Transmit Clock
I
C3
mii1_txd0
MII1 Transmit Data
O
C4
mii1_txd1
MII1 Transmit Data
O
B2
mii1_txd2
MII1 Transmit Data
O
D6
Terminal Configuration and Functions
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Table 4-21. GMAC Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
mii1_txd3
DESCRIPTION
MII1 Transmit Data
O
C5
mii1_txer
MII1 Transmit Error
I
A3
mii1_rxer
MII1 Receive Data Error
I
B3
mii1_col
MII1 Collision Detect (Sense)
I
B4
mii1_crs
MII1 Carrier Sense
I
B5
mii1_txen
MII1 Transmit Data Enable
O
A4
mii0_rxd1
MII0 Receive Data
I
V6
mii0_rxd2
MII0 Receive Data
I
V9
mii0_rxd3
MII0 Receive Data
I
W9
mii0_rxd0
MII0 Receive Data
I
U6
mii0_rxclk
MII0 Receive Clock
I
Y1
mii0_rxdv
MII0 Receive Data Valid
I
V2
mii0_txclk
MII0 Transmit Clock
I
U5
mii0_txd0
MII0 Transmit Data
O
W2
mii0_txd1
MII0 Transmit Data
O
Y2
mii0_txd2
MII0 Transmit Data
O
V4
mii0_txd3
MII0 Transmit Data
O
V5
mii0_txer
MII0 Transmit Error
I
U4
mii0_rxer
MII0 Receive Data Error
I
U7
mii0_col
MII0 Collision Detect (Sense)
I
V1
mii0_crs
MII0 Carrier Sense
I
V7
mii0_txen
MII0 Transmit Data Enable
O
V3
rmii1_crs
RMII1 Carrier Sense
I
V2
rmii1_rxer
RMII1 Receive Data Error
I
Y1
rmii1_rxd1
RMII1 Receive Data
I
W9
rmii1_rxd0
RMII1 Receive Data
I
V9
rmii1_txen
RMII1 Transmit Data Enable
O
U5
rmii1_txd1
RMII1 Transmit Data
O
V5
rmii1_txd0
RMII1 Transmit Data
O
V4
rmii0_crs
RMII0 Carrier Sense
I
V7
rmii0_rxer
RMII0 Receive Data Error
I
U7
rmii0_rxd1
RMII0 Receive Data
I
V6
rmii0_rxd0
RMII0 Receive Data
I
U6
rmii0_txen
RMII0 Transmit Data Enable
O
V3
rmii0_txd1
RMII0 Transmit Data
O
Y2
rmii0_txd0
RMII0 Transmit Data
O
W2
mdio_mclk
Management Data Serial Clock
O
AC5 / V1 / B21 / D3
Management Data
IO
AB4 / U4 / B20 / F6
mdio_d
4.4.19 Media Local Bus (MLB) Interface
NOTE
FMLB in 6-pin mode may require pull ups/ downs on SIG and DAT bus signals.
For additional details, please consult the MLB bus interface specification.
Terminal Configuration and Functions
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NOTE
For more information, see the Serial Communication Interface / Media Local Bus (MLB)
section of the device TRM.
Table 4-22. MLB Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
mlb_sig
Media Local Bus (MLB) Subsystem signal
IO
AB3
mlb_dat
Media Local Bus (MLB) Subsystem data
IO
AA4
mlb_clk
Media Local Bus (MLB) Subsystem clock
I
AA3
mlbp_sig_p
Media Local Bus (MLB) Subsystem signal differential pair (positive)
IODS
AC1
mlbp_sig_n
Media Local Bus (MLB) Subsystem signal differential pair (negative)
IODS
AC2
mlbp_dat_p
Media Local Bus (MLB) Subsystem data differential pair (positive)
IODS
AA1
mlbp_dat_n
Media Local Bus (MLB) Subsystem data differential pair (negative)
IODS
AA2
mlbp_clk_p
Media Local Bus (MLB) Subsystem clock differential pair (positive)
IDS
AB1
mlbp_clk_n
Media Local Bus (MLB) Subsystem clock differential pair (negative)
IDS
AB2
TYPE
BALL
W6
4.4.20 eMMC/SD/SDIO
NOTE
For more information, see the HS MMC/SDIO section of the device TRM.
Table 4-23. eMMC/SD/SDIO Signal Descriptions
SIGNAL NAME
DESCRIPTION
Multi Media Card 1
mmc1_clk(1)
MMC1 clock
IO
mmc1_cmd
MMC1 command
IO
Y6
mmc1_sdcd
MMC1 Card Detect
I
W7
mmc1_sdwp
MMC1 Write Protect
I
Y9
mmc1_dat0
MMC1 data bit 0
IO
AA6
mmc1_dat1
MMC1 data bit 1
IO
Y4
mmc1_dat2
MMC1 data bit 2
IO
AA5
mmc1_dat3
MMC1 data bit 3
IO
Y3
mmc2_clk(1)
MMC2 clock
IO
J7
mmc2_cmd
MMC2 command
IO
H6
Multi Media Card 2
mmc2_sdcd
MMC2 Card Detect
I
G20
mmc2_sdwp
MMC2 Write Protect
I
G19
mmc2_dat0
MMC2 data bit 0
IO
J4
mmc2_dat1
MMC2 data bit 1
IO
J6
mmc2_dat2
MMC2 data bit 2
IO
H4
mmc2_dat3
MMC2 data bit 3
IO
H5
mmc2_dat4
MMC2 data bit 4
IO
K7
mmc2_dat5
MMC2 data bit 5
IO
M7
mmc2_dat6
MMC2 data bit 6
IO
J5
mmc2_dat7
MMC2 data bit 7
IO
K6
mmc3_clk(1)
MMC3 clock
IO
AD4
mmc3_cmd
MMC3 command
IO
AC4
Multi Media Card 3
110
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Table 4-23. eMMC/SD/SDIO Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
I
B21
mmc3_sdcd
MMC3 Card Detect
mmc3_sdwp
MMC3 Write Protect
I
B20
mmc3_dat0
MMC3 data bit 0
IO
AC7
mmc3_dat1
MMC3 data bit 1
IO
AC6
mmc3_dat2
MMC3 data bit 2
IO
AC9
mmc3_dat3
MMC3 data bit 3
IO
AC3
mmc3_dat4
MMC3 data bit 4
IO
AC8
mmc3_dat5
MMC3 data bit 5
IO
AD6
mmc3_dat6
MMC3 data bit 6
IO
AB8
mmc3_dat7
MMC3 data bit 7
IO
AB5
mmc4_clk(1)
MMC4 clock
IO
E25
mmc4_cmd
MMC4 command
IO
C27
mmc4_sdcd
MMC4 Card Detect
I
B27
mmc4_sdwp
MMC4 Write Protect
I
C26
mmc4_dat0
MMC4 data bit 0
IO
D28
mmc4_dat1
MMC4 data bit 1
IO
D26
mmc4_dat2
MMC4 data bit 2
IO
D27
mmc4_dat3
MMC4 data bit 3
IO
C28
Multi Media Card 4
(1) By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer
to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal
loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as
close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad
loopback clock pin between VIH and VIL must be less than VHYS.
4.4.21 General-Purpose Interface (GPIO)
NOTE
For more information, see the General-Purpose Interface section of the device TRM.
Table 4-24. GPIOs Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
GPIO 1
gpio1_0
General-Purpose Input
I
AD17
gpio1_3
General-Purpose Input
I
AC16
gpio1_4
General-Purpose Input/Output
IO
D15
gpio1_5
General-Purpose Input/Output
IO
A17
gpio1_6
General-Purpose Input/Output
IO
M6
gpio1_7
General-Purpose Input/Output
IO
M2
gpio1_8
General-Purpose Input/Output
IO
L5
gpio1_9
General-Purpose Input/Output
IO
M1
gpio1_10
General-Purpose Input/Output
IO
L6
gpio1_11
General-Purpose Input/Output
IO
L4
gpio1_12
General-Purpose Input/Output
IO
L3
gpio1_13
General-Purpose Input/Output
IO
L2
gpio1_14
General-Purpose Input/Output
IO
G20
gpio1_15
General-Purpose Input/Output
IO
G19
gpio1_16
General-Purpose Input/Output
IO
D27
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Table 4-24. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio1_17
DESCRIPTION
General-Purpose Input/Output
IO
C28
gpio1_18
General-Purpose Input/Output
IO
H1
gpio1_19
General-Purpose Input/Output
IO
J3
gpio1_20
General-Purpose Input/Output
IO
H2
gpio1_21
General-Purpose Input/Output
IO
H3
gpio1_22
General-Purpose Input/Output
IO
AC8
gpio1_23
General-Purpose Input/Output
IO
AD6
gpio1_24
General-Purpose Input/Output
IO
AB8
gpio1_25
General-Purpose Input/Output
IO
AB5
gpio1_26
General-Purpose Input/Output
IO
P6
gpio1_27
General-Purpose Input/Output
IO
R9
gpio1_28
General-Purpose Input/Output
IO
R5
gpio1_29
General-Purpose Input/Output
IO
P5
gpio1_30
General-Purpose Input/Output
IO
N7
gpio1_31
General-Purpose Input/Output
IO
R4
gpio2_0
General-Purpose Input/Output
IO
N9
gpio2_1
General-Purpose Input/Output
IO
P9
gpio2_2
General-Purpose Input/Output
IO
P4
gpio2_3
General-Purpose Input/Output
IO
R3
gpio2_4
General-Purpose Input/Output
IO
T2
gpio2_5
General-Purpose Input/Output
IO
U2
gpio2_6
General-Purpose Input/Output
IO
U1
gpio2_7
General-Purpose Input/Output
IO
P3
gpio2_8
General-Purpose Input/Output
IO
R2
gpio2_9
General-Purpose Input/Output
IO
K7
gpio2_10
General-Purpose Input/Output
IO
M7
gpio2_11
General-Purpose Input/Output
IO
J5
gpio2_12
General-Purpose Input/Output
IO
K6
gpio2_13
General-Purpose Input/Output
IO
J7
gpio2_14
General-Purpose Input/Output
IO
J4
gpio2_15
General-Purpose Input/Output
IO
J6
gpio2_16
General-Purpose Input/Output
IO
H4
gpio2_17
General-Purpose Input/Output
IO
H5
gpio2_18
General-Purpose Input/Output
IO
H6
gpio2_19
General-Purpose Input/Output
IO
T1
gpio2_20
General-Purpose Input/Output
IO
P2
gpio2_21
General-Purpose Input/Output
IO
P1
gpio2_22
General-Purpose Input/Output
IO
P7
gpio2_23
General-Purpose Input/Output
IO
N1
gpio2_24
General-Purpose Input/Output
IO
M5
gpio2_25
General-Purpose Input/Output
IO
M3
gpio2_26
General-Purpose Input/Output
IO
N6
gpio2_27
General-Purpose Input/Output
IO
M4
gpio2_28
General-Purpose Input/Output
IO
N2
gpio2_29
General-Purpose Input/Output
IO
B17
GPIO 2
GPIO 3
112
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Table 4-24. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio3_28
DESCRIPTION
General-Purpose Input/Output
IO
E1
gpio3_29
General-Purpose Input/Output
IO
G2
gpio3_30
General-Purpose Input/Output
IO
H7
gpio3_31
General-Purpose Input/Output
IO
G1
gpio4_0
General-Purpose Input/Output
IO
G6
gpio4_1
General-Purpose Input/Output
IO
F2
gpio4_2
General-Purpose Input/Output
IO
F3
gpio4_3
General-Purpose Input/Output
IO
D1
gpio4_4
General-Purpose Input/Output
IO
E2
gpio4_5
General-Purpose Input/Output
IO
D2
gpio4_6
General-Purpose Input/Output
IO
F4
gpio4_7
General-Purpose Input/Output
IO
C1
gpio4_8
General-Purpose Input/Output
IO
E4
GPIO 4
gpio4_9
General-Purpose Input/Output
IO
F5
gpio4_10
General-Purpose Input/Output
IO
E6
gpio4_11
General-Purpose Input/Output
IO
D3
gpio4_12
General-Purpose Input/Output
IO
F6
gpio4_13
General-Purpose Input/Output
IO
D5
gpio4_14
General-Purpose Input/Output
IO
C2
gpio4_15
General-Purpose Input/Output
IO
C3
gpio4_16
General-Purpose Input/Output
IO
C4
gpio4_17
General-Purpose Input/Output
IO
A12
gpio4_18
General-Purpose Input/Output
IO
E14
gpio4_19
General-Purpose Input/Output
IO
D11
gpio4_20
General-Purpose Input/Output
IO
B10
gpio4_21
General-Purpose Input/Output
IO
B11
gpio4_22
General-Purpose Input/Output
IO
C11
gpio4_23
General-Purpose Input/Output
IO
E11
gpio4_24
General-Purpose Input/Output
IO
B2
gpio4_25
General-Purpose Input/Output
IO
D6
gpio4_26
General-Purpose Input/Output
IO
C5
gpio4_27
General-Purpose Input/Output
IO
A3
gpio4_28
General-Purpose Input/Output
IO
B3
gpio4_29
General-Purpose Input/Output
IO
B4
gpio4_30
General-Purpose Input/Output
IO
B5
gpio4_31
General-Purpose Input/Output
IO
A4
gpio5_0
General-Purpose Input/Output
IO
B14
gpio5_1
General-Purpose Input/Output
IO
J14
gpio5_2
General-Purpose Input/Output
IO
G12
gpio5_3
General-Purpose Input/Output
IO
F12
gpio5_4
General-Purpose Input/Output
IO
G13
gpio5_5
General-Purpose Input/Output
IO
J11
gpio5_6
General-Purpose Input/Output
IO
E12
gpio5_7
General-Purpose Input/Output
IO
F13
gpio5_8
General-Purpose Input/Output
IO
C12
GPIO 5
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Table 4-24. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio5_9
DESCRIPTION
General-Purpose Input/Output
IO
D12
gpio5_10
General-Purpose Input/Output
IO
B12
gpio5_11
General-Purpose Input/Output
IO
A11
gpio5_12
General-Purpose Input/Output
IO
B13
gpio5_13
General-Purpose Input/Output
IO
B18
gpio5_14
General-Purpose Input/Output
IO
F15
gpio5_15
General-Purpose Input/Output
IO
V1
gpio5_16
General-Purpose Input/Output
IO
U4
gpio5_17
General-Purpose Input/Output
IO
U3
gpio5_18
General-Purpose Input/Output
IO
V2
gpio5_19
General-Purpose Input/Output
IO
Y1
gpio5_20
General-Purpose Input/Output
IO
W9
gpio5_21
General-Purpose Input/Output
IO
V9
gpio5_22
General-Purpose Input/Output
IO
V7
gpio5_23
General-Purpose Input/Output
IO
U7
gpio5_24
General-Purpose Input/Output
IO
V6
gpio5_25
General-Purpose Input/Output
IO
U6
gpio5_26
General-Purpose Input/Output
IO
U5
gpio5_27
General-Purpose Input/Output
IO
V5
gpio5_28
General-Purpose Input/Output
IO
V4
gpio5_29
General-Purpose Input/Output
IO
V3
gpio5_30
General-Purpose Input/Output
IO
Y2
gpio5_31
General-Purpose Input/Output
IO
W2
gpio6_4
General-Purpose Input/Output
IO
A13
gpio6_5
General-Purpose Input/Output
IO
G14
gpio6_6
General-Purpose Input/Output
IO
F14
gpio6_7
General-Purpose Input/Output
IO
B16
gpio6_8
General-Purpose Input/Output
IO
C15
GPIO 6
114
gpio6_9
General-Purpose Input/Output
IO
A16
gpio6_10
General-Purpose Input/Output
IO
AC5
gpio6_11
General-Purpose Input/Output
IO
AB4
gpio6_12
General-Purpose Input/Output
IO
AB10
gpio6_13
General-Purpose Input/Output
IO
AC10
gpio6_14
General-Purpose Input/Output
IO
E21
gpio6_15
General-Purpose Input/Output
IO
F20
gpio6_16
General-Purpose Input/Output
IO
F21
gpio6_17
General-Purpose Input/Output
IO
D18
gpio6_18
General-Purpose Input/Output
IO
E17
gpio6_19
General-Purpose Input/Output
IO
B26
gpio6_20
General-Purpose Input/Output
IO
C23
gpio6_21
General-Purpose Input/Output
IO
W6
gpio6_22
General-Purpose Input/Output
IO
Y6
gpio6_23
General-Purpose Input/Output
IO
AA6
gpio6_24
General-Purpose Input/Output
IO
Y4
gpio6_25
General-Purpose Input/Output
IO
AA5
gpio6_26
General-Purpose Input/Output
IO
Y3
Terminal Configuration and Functions
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Table 4-24. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio6_27
DESCRIPTION
General-Purpose Input/Output
IO
W7
gpio6_28
General-Purpose Input/Output
IO
Y9
gpio6_29
General-Purpose Input/Output
IO
AD4
gpio6_30
General-Purpose Input/Output
IO
AC4
gpio6_31
General-Purpose Input/Output
IO
AC7
gpio7_0
General-Purpose Input/Output
IO
AC6
gpio7_1
General-Purpose Input/Output
IO
AC9
gpio7_2
General-Purpose Input/Output
IO
AC3
gpio7_3
General-Purpose Input/Output
IO
R6
gpio7_4
General-Purpose Input/Output
IO
T9
gpio7_5
General-Purpose Input/Output
IO
T6
gpio7_6
General-Purpose Input/Output
IO
T7
gpio7_7
General-Purpose Input/Output
IO
A25
gpio7_8
General-Purpose Input/Output
IO
F16
gpio7_9
General-Purpose Input/Output
IO
B25
gpio7_10
General-Purpose Input/Output
IO
A24
gpio7_11
General-Purpose Input/Output
IO
A22
gpio7_12
General-Purpose Input/Output
IO
B21
gpio7_13
General-Purpose Input/Output
IO
B20
gpio7_14
General-Purpose Input/Output
IO
A26
gpio7_15
General-Purpose Input/Output
IO
B22
gpio7_16
General-Purpose Input/Output
IO
G17
gpio7_17
General-Purpose Input/Output
IO
B24
gpio7_18
General-Purpose Input/Output
IO
L1
gpio7_19
General-Purpose Input/Output
IO
K2
gpio7_22
General-Purpose Input/Output
IO
B27
gpio7_23
General-Purpose Input/Output
IO
C26
gpio7_24
General-Purpose Input/Output
IO
E25
gpio7_25
General-Purpose Input/Output
IO
C27
gpio7_26
General-Purpose Input/Output
IO
D28
gpio7_27
General-Purpose Input/Output
IO
D26
gpio7_28
General-Purpose Input/Output
IO
J1
gpio7_29
General-Purpose Input/Output
IO
J2
gpio7_30
General-Purpose Input/Output
IO
D14
gpio7_31
General-Purpose Input/Output
IO
C14
gpio8_0
General-Purpose Input/Output
IO
F11
gpio8_1
General-Purpose Input/Output
IO
G10
gpio8_2
General-Purpose Input/Output
IO
F10
gpio8_3
General-Purpose Input/Output
IO
G11
gpio8_4
General-Purpose Input/Output
IO
E9
gpio8_5
General-Purpose Input/Output
IO
F9
gpio8_6
General-Purpose Input/Output
IO
F8
gpio8_7
General-Purpose Input/Output
IO
E7
gpio8_8
General-Purpose Input/Output
IO
E8
gpio8_9
General-Purpose Input/Output
IO
D9
GPIO 7
GPIO 8
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Table 4-24. GPIOs Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
gpio8_10
DESCRIPTION
General-Purpose Input/Output
IO
D7
gpio8_11
General-Purpose Input/Output
IO
D8
gpio8_12
General-Purpose Input/Output
IO
A5
gpio8_13
General-Purpose Input/Output
IO
C6
gpio8_14
General-Purpose Input/Output
IO
C8
gpio8_15
General-Purpose Input/Output
IO
C7
gpio8_16
General-Purpose Input/Output
IO
B7
gpio8_17
General-Purpose Input/Output
IO
B8
gpio8_18
General-Purpose Input/Output
IO
A7
gpio8_19
General-Purpose Input/Output
IO
A8
gpio8_20
General-Purpose Input/Output
IO
C9
gpio8_21
General-Purpose Input/Output
IO
A9
gpio8_22
General-Purpose Input/Output
IO
B9
gpio8_23
General-Purpose Input/Output
IO
A10
gpio8_27
General-Purpose Input
I
D23
gpio8_28
General-Purpose Input/Output
IO
F19
gpio8_29
General-Purpose Input/Output
IO
E18
gpio8_30
General-Purpose Input/Output
IO
G21
gpio8_31
General-Purpose Input/Output
IO
D24
4.4.22 Keyboard controller (KBD)
NOTE
For more information, see Keyboard Controller section of the device TRM.
Table 4-25. Keyboard Signal Descriptions
SIGNAL NAME
116
DESCRIPTION
TYPE
BALL
kbd_row0
Keypad row 0
I
E1
kbd_row1
Keypad row 1
I
G2
kbd_row2
Keypad row 2
I
G1
kbd_row3
Keypad row 3
I
G6
kbd_row4
Keypad row 4
I
F2
kbd_row5
Keypad row 5
I
F3
kbd_row6
Keypad row 6
I
D1
kbd_row7
Keypad row 7
I
F6
kbd_row8
Keypad row 8
I
C2
kbd_col0
Keypad column 0
O
E2
kbd_col1
Keypad column 1
O
D2
kbd_col2
Keypad column 2
O
F4
kbd_col3
Keypad column 3
O
C1
kbd_col4
Keypad column 4
O
E4
kbd_col5
Keypad column 5
O
F5
kbd_col6
Keypad column 6
O
E6
kbd_col7
Keypad column 7
O
D3
kbd_col8
Keypad column 8
O
D5
Terminal Configuration and Functions
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4.4.23 Pulse Width Modulation (PWM) Interface
NOTE
For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM.
Table 4-26. PWM Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
PWMSS1
eQEP1A_in
EQEP1 Quadrature Input A
I
E1
eQEP1B_in
EQEP1 Quadrature Input B
I
G2
eQEP1_index
EQEP1 Index Input
IO
H7
eQEP1_strobe
EQEP1 Strobe Input
IO
G1
ehrpwm1A
EHRPWM1 Output A
O
G6
ehrpwm1B
EHRPWM1 Output B
O
F2
EHRPWM1 Trip Zone Input
IO
F3
IO
D1
ehrpwm1_tripzone_in
put
eCAP1_in_PWM1_out ECAP1 Capture Iniput / PWM Output
ehrpwm1_synci
EHRPWM1 Sync Input
I
E2
ehrpwm1_synco
EHRPWM1 Sync Output
O
D2
eQEP2A_in
EQEP2 Quadrature Input A
I
F4
eQEP2B_in
EQEP2 Quadrature Input B
I
C1
E4
PWMSS2
eQEP2_index
EQEP2 Index Input
IO
eQEP2_strobe
EQEP2 Strobe Input
IO
F5
ehrpwm2A
EHRPWM2 Output A
O
AC5 / E6
ehrpwm2B
EHRPWM2 Output B
O
AB4 / D3
EHRPWM2 Trip Zone Input
IO
AD4 / F6
IO
AC4 / D5
ehrpwm2_tripzone_in
put
eCAP2_in_PWM2_out ECAP2 Capture Iniput / PWM Output
PWMSS3
eQEP3A_in
EQEP3 Quadrature Input A
I
AC7 / C2
eQEP3B_in
EQEP3 Quadrature Input B
I
AC6 / C3
AC9 / C4
eQEP3_index
EQEP3 Index Input
IO
eQEP3_strobe
EQEP3 Strobe Input
IO
AC3 / B2
ehrpwm3A
EHRPWM3 Output A
O
AC8 / D6
ehrpwm3B
EHRPWM3 Output B
O
AD6 / C5
EHRPWM3 Trip Zone Input
IO
AB8 / A3
IO
AB5 / B3
ehrpwm3_tripzone_in
put
eCAP3_in_PWM3_out ECAP3 Capture Iniput / PWM Output
4.4.24 Audio Tracking Logic (ATL)
NOTE
For more information, see the Audio Tracking Logic (ATL) section of the device TRM.
Table 4-27. ATL Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
atl_clk0
Audio Tracking Logic Clock 0
O
D18
atl_clk1
Audio Tracking Logic Clock 1
O
E17
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Table 4-27. ATL Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
atl_clk2
Audio Tracking Logic Clock 2
O
B26
atl_clk3
Audio Tracking Logic Clock 3
O
C23
4.4.25 Test Interfaces
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in Table 7-145.
NOTE
For more information, see the On-Chip Debug Support / Debug Ports section of the device
TRM.
Table 4-28. Debug Signal Descriptions
SIGNAL NAME
118
DESCRIPTION
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
TYPE
BALL
IO
F18
D23
tdi
JTAG test data
I
tdo
JTAG test port data
O
F19
tclk
JTAG test clock
I
E20
trstn
JTAG test reset
I
D20
rtck
JTAG return clock
O
E18
emu0
Emulator pin 0
IO
G21
emu1
Emulator pin 1
IO
D24
emu2
Emulator pin 2
O
F10
emu3
Emulator pin 3
O
D7
emu4
Emulator pin 4
O
A7
emu5
Emulator pin 5
O
E1 / G11
emu6
Emulator pin 6
O
G2 / E9
emu7
Emulator pin 7
O
H7 / F9
emu8
Emulator pin 8
O
G1 / F8
emu9
Emulator pin 9
O
G6 / E7
emu10
Emulator pin 10
O
F2 / D8
emu11
Emulator pin 11
O
F3 / A5
emu12
Emulator pin 12
O
D1 / C6
emu13
Emulator pin 13
O
E2 / C8
emu14
Emulator pin 14
O
D2 / C7
emu15
Emulator pin 15
O
F4 / A8
emu16
Emulator pin 16
O
C1 / C9
emu17
Emulator pin 17
O
E4 / A9
emu18
Emulator pin 18
O
F5 / B9
emu19
Emulator pin 19
O
E6 / A10
Terminal Configuration and Functions
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4.4.26 System and Miscellaneous
4.4.26.1 Sysboot
NOTE
For more information, see the Initialization (ROM Code) section of the device TRM.
Table 4-29. Sysboot Signal Descriptions
SIGNAL NAME
TYPE
BALL
sysboot0
DESCRIPTION
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M6
sysboot1
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M2
sysboot2
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L5
sysboot3
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
M1
sysboot4
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L6
sysboot5
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L4
sysboot6
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L3
sysboot7
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L2
sysboot8
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
L1
sysboot9
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
K2
sysboot10
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J1
sysboot11
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J2
sysboot12
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H1
sysboot13
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
J3
sysboot14
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H2
sysboot15
Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
H3
4.4.26.2 Power, Reset, and Clock Management (PRCM)
NOTE
For more information, see PRCM section of the device TRM.
Table 4-30. PRCM Signal Descriptions
SIGNAL NAME
clkout1
DESCRIPTION
Device Clock output 1. Can be used externally for devices with noncritical timing requirements, or for debug, or as a reference clock on
GPMC as described in Table 7-23 GPMC/NOR Flash Interface
Switching Characteristics - Synchronous Mode - Default and Table 725 GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode - Alternate.
TYPE
BALL
O
F21 / P7
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Table 4-30. PRCM Signal Descriptions (continued)
SIGNAL NAME
TYPE
BALL
clkout2
Device Clock output 2. Can be used externally for devices with noncritical timing requirements, or for debug.
O
D18 / N1
clkout3
Device Clock output 3. Can be used xternally for devices with noncritical timing requirements, or for debug.
O
C23
rstoutn
Reset out (Active low). This pin asserts low in response to any global
reset condition on the device. (2)
O
F23
resetn
Device Reset Input
I
E23
Power on Reset (active low). This pin must be asserted low until all
device supplies are valid (see reset sequence/requirements)
I
F22
xref_clk0
External Reference Clock 0. For Audio and other Peripherals.
I
D18
xref_clk1
External Reference Clock 1. For Audio and other Peripherals.
I
E17
xref_clk2
External Reference Clock 2. For Audio and other Peripherals.
I
B26
xref_clk3
External Reference Clock 3. For Audio and other Peripherals.
I
C23
xi_osc0
System Oscillator OSC0 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
I
AE15
xo_osc0
System Oscillator OSC0 Crystal output
O
AD15
xi_osc1
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used
I
AC15
xo_osc1
Auxiliary Oscillator OSC1 Crystal output
O
AC13
RMII Reference Clock (50MHz). This pin is an input when external
reference is used or output when internal reference is used.
IO
U3
porz
RMII_MHZ_50_CLK(1)
DESCRIPTION
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.4.26.3 Real-Time Clock (RTC) Interface
NOTE
For more information, see the Real-Time Clock (RTC) chapter of the device TRM.
Table 4-31. RTC Signal Descriptions
SIGNAL NAME
TYPE
BALL
Wakeup0
RTC External Wakeup Input 0
I
AD17
Wakeup3
RTC External Wakeup Input 3
I
AC16
rtc_porz
RTC Power Domain Power-On Reset Input
I
AB17
RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as
an RTC clock input when an external oscillator is used.
I
AE14
rtc_osc_xi_clkin32
rtc_osc_xo
120
DESCRIPTION
RTC Oscillator Output
O
AD14
rtc_iso(1)
RTC domain Isolation Signal
I
AF14
on_off
RTC Power Enable output pin
O
Y11
Terminal Configuration and Functions
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(1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be
achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.
4.4.26.4 System Direct Memory Access (SDMA)
NOTE
For more information, see the DMA Controllers / System DMA section of the device TRM.
Table 4-32. SDMA Signal Descriptions
SIGNAL NAME
TYPE
BALL
dma_evt1
DESCRIPTION
System DMA Event Input 1
I
P7 / P4
dma_evt2
System DMA Event Input 2
I
N1 / R3
dma_evt3
System DMA Event Input 3
I
N6
dma_evt4
System DMA Event Input 4
I
M4
4.4.26.5 Interrupt Controllers (INTC)
NOTE
For more information, see the Interrupt Controllers section of the device TRM.
Table 4-33. INTC Signal Descriptions
SIGNAL NAME
TYPE
BALL
nmin_dsp
DESCRIPTION
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the ARM cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or
ARM processors.
I
D21
sys_nirq2
External interrupt event to any device INTC
I
AD17
sys_nirq1
External interrupt event to any device INTC
I
AC16
TYPE
BALL
4.4.26.6 Observability
NOTE
For more information, see the Control Module section of the device TRM.
Table 4-34. Observability Signal Descriptions
SIGNAL NAME DESCRIPTION
obs0
Observation Output 0
O
F10
obs1
Observation Output 1
O
G11
obs2
Observation Output 2
O
E9
obs3
Observation Output 3
O
F9
obs4
Observation Output 4
O
F8
obs5
Observation Output 5
O
D7
obs6
Observation Output 6
O
D8
obs7
Observation Output 7
O
A5
obs8
Observation Output 8
O
C6
obs9
Observation Output 9
O
C8
obs10
Observation Output 10
O
C7
obs11
Observation Output 11
O
A7
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Table 4-34. Observability Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
obs12
Observation Output 12
O
A8
obs13
Observation Output 13
O
C9
obs14
Observation Output 14
O
A9
obs15
Observation Output 15
O
B9
obs16
Observation Output 16
O
F10
obs17
Observation Output 17
O
G11
obs18
Observation Output 18
O
E9
obs19
Observation Output 19
O
F9
obs20
Observation Output 20
O
F8
obs21
Observation Output 21
O
D7
obs22
Observation Output 22
O
D8
obs23
Observation Output 23
O
A5
obs24
Observation Output 24
O
C6
obs25
Observation Output 25
O
C8
obs26
Observation Output 26
O
C7
obs27
Observation Output 27
O
A7
obs28
Observation Output 28
O
A8
obs29
Observation Output 29
O
C9
obs30
Observation Output 30
O
A9
obs31
Observation Output 31
O
B9
obs_dmarq1
DMA Request External Observation Output 1
O
G11
obs_dmarq2
DMA Request External Observation Output 2
O
D8
obs_irq1
IRQ External Observation Output 1
O
F10
obs_irq2
IRQ External Observation Output 2
O
D7
4.4.27 Power Supplies
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the device TRM.
Table 4-35. Power Supply Signal Descriptions
SIGNAL NAME
vdd
122
DESCRIPTION
Core voltage domain supply
Terminal Configuration and Functions
TYPE
BALL
PWR
H13 / H14 / J17 / J18
/ L7 / L8 / N10 / N13 /
P11 / P12 / P13 / R11
/ R16 / R19 / T13 /
T16 / T19 / U13 / U16
/ U8 / U9 / V16 / V8
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Table 4-35. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
vss
TYPE
BALL
GND
A1 / A14 / A2 / A23 /
A28 / A6 / AA14 /
AA15 / AA20 / AA8 /
AA9 / AB14 / AB20 /
AD1 / AD24 / AG1 /
AH1 / AH2 / AH20 /
AH28 / B1 / D13 /
D19 / E13 / E19 / F1 /
F7 / G7 / G8 / G9 /
H12 / J12 / J15 / J28 /
K1 / K15 / K24 / K25 /
K4 / K5 / L13 / L14 /
M19 / N14 / N15 /
N19 / N24 / N25 / P28
/ R1 / R12 / R13 /
R21 / T10 / T11 / T12
/ T14 / T15 / T17 /
T18 / T21 / U14 / U15
/ U17 / U20 / U21 /
V15 / V17 / W1 / W15
/ W24 / W25 / W28
Ground
cap_vbbldo_gpu(1)
External capacitor connection for the GPU vbb ldo output
CAP
Y14
cap_vbbldo_iva(1)
External capacitor connection for the IVA vbb ldo output
CAP
J10
cap_vbbldo_mpu(1)
External capacitor connection for the MPU vbb ldo output
CAP
J16
(1)
External capacitor connection for the DSP vbb ldo output
CAP
K9
cap_vddram_core1(1)
cap_vbbldo_dsp
External capacitor connection for the Core SRAM array ldo1 output
CAP
T20
cap_vddram_core3(1)
External capacitor connection for the Core SRAM array ldo3 output
CAP
L9
(1)
cap_vddram_core4
External capacitor connection for the Core SRAM array ldo4 output
CAP
J19
cap_vddram_mpu(1)
External capacitor connection for the MPU SRAM array ldo output
CAP
K19
cap_vddram_gpu(1)
External capacitor connection for the GPU SRAM array ldo output
CAP
Y13
cap_vddram_iva(1)
External capacitor connection for the IVA SRAM array ldo output
CAP
K16
(1)
cap_vddram_dsp
External capacitor connection for the DSP
CAP
J9
DSP PLL and IVA PLL analog power supply
PWR
N12
DPLL_CORE and CORE HSDIVIDER analog power supply
PWR
P14
DPLL_SPARE analog power supply
PWR
P15
DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply
PWR
M14
vdda_mpu_abe
MPU_ABE PLL analog power supply
PWR
N16
vdda33v_usb1
HS USB1 3.3V analog power supply. If USB1 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb1_dm/usb1_dp pins are left unconnected
- The USB1 PHY is kept powered down
PWR
AA12
vdda33v_usb2
HS USB2 3.3V analog power supply. If USB2 is not used, this pin can
alternatively be connected to VSS if the following requirements are met:
- The usb2_dm/usb2_dp pins are left unconnected
- The USB2 PHY is kept powered down
PWR
Y12
DPLL_DDR and DDR HSDIVIDER analog power supply
PWR
R17
DPLL_DEBUG analog power supply
PWR
N11
vdda_gpu
DPLL_GPU analog power supply
PWR
R14
vdda_hdmi
vdda_dsp_iva
vdda_core_gmac
vdda_pll_spare
vdda_per
vdda_ddr
vdda_debug
PLL_HDMI and HDMI analog power supply
PWR
Y17
vdda_osc
HFOSC analog power supply
PWR
AD16 / AE16
vdda_pcie
DPLL_PCIe_REF and PCIe analog power supply
PWR
AA17
vdda_pcie0
PCIe ch0 RX/TX analog power supply
PWR
AA16
AB13
RTC bias and RTC LFOSC analog power supply
PWR
vdda_sata
vdda_rtc
DPLL_SATA and SATA RX/TX analog power supply
PWR
V13
vdda_usb1
DPLL_USB and HS USB1 1.8V analog power supply
PWR
AA13
Terminal Configuration and Functions
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Table 4-35. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vdda_usb2
HS USB2 1.8V analog power supply
PWR
AB12
vdda_usb3
DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply
PWR
W14
CSI Interface 1.8v Supply
PWR
W12
VIDEO1 and VIDEO2 PLL analog power supply
PWR
P16
1.8V power supply
PWR
G18 / H17 / M8 / M9 /
N8 / P8 / R8 / T8 /
V21 / V22 / W17 /
W18
EMIF1 bias power supply
PWR
AA18 / AA19 / N21 /
P20 / P21 / W21 /
Y21
vddshv1
Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group
pins
PWR
E3 / E5 / G4 / G5 / H8
/ H9
vddshv2
Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group
pins
PWR
B6 / D10 / E10 / H10 /
H11
vddshv3
Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power
Group pins
PWR
B23 / D16 / D22 / E16
/ E22 / G15 / H15 /
H16 / H18 / H19
vddshv4
Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group
pins
PWR
C24
vddshv5
Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group
pins
PWR
V12
vddshv6
Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group
pins
PWR
AD5 / AD7 / AE7 /
AF5
vddshv7
Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group
pins
PWR
AB6 / AB7
vddshv8
Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group
pins
PWR
W8 / Y8
vddshv9
Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group
pins
PWR
U10 / W4 / W5
vddshv10
Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group
pins
PWR
N4 / N5 / P10 / R10 /
R7 / T4 / T5
vddshv11
Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group
pins
PWR
J8 / K8
vdds_ddr1
EMIF1 power supply (1.5V for DDR3 mode / 1.35V DDR3L mode)
PWR
AA21 / AA22 / AB21 /
AB22 / AB24 / AB25 /
AC22 / AD26 / AG20 /
AG28 / AH27 / T24 /
T25 / W16 / W27
vdds_mlbp
vdda_csi
vdda_video
vdds18v
vdds18v_ddr1
124
MLBP IO power supply
PWR
AA7 / Y7
vdd_dsp
DSP voltage domain supply
PWR
K10 / K11 / L10 / L11
/ M10 / M11
vdd_gpu
GPU voltage domain supply
PWR
U11 / U12 / V10 / V11
/ V14 / W10 / W11 /
W13
vdd_iva
IVA voltage domain supply
PWR
J13 / K12 / K13 / L12
/ M12 / M13
vdd_mpu
MPU voltage domain supply
PWR
K17 / K18 / L15 / L16
/ L17 / L18 / L19 /
M15 / M16 / M17 /
M18 / N17 / N18 /
P17 / P18 / R18
vdd_rtc
RTC voltage domain supply
PWR
AB15
vssa_hdmi
DPLL_HDMI and HDMI PHY analog ground
GND
AD19 / AE19
vssa_osc0
OSC0 analog ground
GND
AF15
vssa_osc1
OSC1 analog ground
GND
AC14
Terminal Configuration and Functions
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Table 4-35. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
vssa_pcie
PCIe analog ground
GND
AD13 / AE13
vssa_sata
SATA analog ground
GND
AE10
vssa_usb
HS USB1 and HS USB2 analog ground
GND
AA11 / AB11
vssa_usb3
DPLL_USB and USB3.0 RX/TX analog ground
GND
AD10
CSI Interface 0v Supply
GND
AA10 / AH8
DPLL_VIDEO1 analog ground
GND
R15
vssa_csi
vssa_video
(1) This pin must always be connected via a 1-µF capacitor to vss.
Terminal Configuration and Functions
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5 Specifications
NOTE
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
NOTE
The index numbers 1 and 2 which is part of the EMIF1 signal prefixes (ddr1_*) listed in
Table 4-8, EMIF Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1
type of SDRAM memories.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
5.1
Absolute Maximum Ratings
Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those listed under Section 5.4, Recommended Operating Conditions, is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Table 5-1. Absolute Maximum Rating Over Junction Temperature Range
PARAMETER(1)
VSUPPLY (Steady-State)
126
Specifications
Supply Voltage Ranges (SteadyState)
MIN
MAX
UNIT
Core (vdd, vdd_mpu, vdd_gpu,
vdd_dsp, vdd_iva, vdd_rtc)
-0.3
1.5
V
Analog (vdda_usb1, vdda_usb2,
vdda_per, vdda_ddr, vdda_debug,
vdda_mpu_abe, vdda_usb3,
vdda_csi, vdda_core_gmac,
vdda_pll_spare, vdda_dsp_iva,
vdda_gpu, dda_hdmi, vdda_pcie,
vdda_pcie0, vdda_sata,
vdda_video, vdda_osc, vdda_rtc)
-0.3
2.0
V
Analog 3.3V (vdda33v_usb1,
vdda33v_usb2)
-0.3
3.8
V
vdds18v, vdds18v_ddr1,
vdds_mlbp, vdds_ddr1
-0.3
2.1
V
vddshv1-11 (1.8V mode)
-0.3
2.1
V
vddshv1-7 (3.3V mode), vddshv9-11
(3.3V mode)
-0.3
3.8
V
vddshv8 (3.3V mode)
-0.3
3.6
V
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Table 5-1. Absolute Maximum Rating Over Junction Temperature Range (continued)
PARAMETER(1)
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
MIN
MAX
UNIT
Core I/Os
-0.3
1.5
V
Analog I/Os (except HDMI)
-0.3
2.0
V
HDMI I/Os
-0.3
3.5
V
I/O 1.35V
-0.3
1.65
V
I/O 1.5V
-0.3
1.8
V
1.8V I/Os
-0.3
2.1
V
3.3V I/Os (except those powered by
vddshv8)
-0.3
3.8
V
3.3V I/Os (powered by vddshv8)
-0.3
SR
Maximum slew rate, all supplies
VIO (Transient Overshoot /
Undershoot)
Input and Output Voltage Ranges (Transient Overshoot/Undershoot)
Note: valid for up to 20% of the signal period
TJ
Operating junction temperature
range
TSTG
Storage temperature range after soldered onto PC Board
Automotive
(3)
3.6
V
105
V/s
0.2*VDD
V
-40
+125
°C
-55
+150
°C
(2)
Latch-up I-Test
I-test , All I/Os (if different levels then one line per level)
-100
100
mA
Latch-up OV-Test
Over-voltage Test(4), All supplies (if different levels then one line per level)
N/A
1.5*Vsup
ply max
V
(1) See I/Os supplied by this power pin in Table 4-2 Ball Characteristics
(2) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(3) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(4) Per JEDEC JESD78 at 125°C.
5.2
ESD Ratings
Table 5-2. ESD Ratings
VALUE
Human-Body model (HBM), per AEC Q100-002(1)
VESD Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±1000
HDMIPHY Pins
(AG16, AH16, AG19,
AH19, AG18, AH18,
AG17, AH17)
±200
All Pins (other than
HDMIPHY)
±250
Corner pins (A1,
AH1, A28, AH28)
±750
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3
Power on Hour (POH) Limits
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
NOTE
POH is a functional of voltage, temperature and time. Usage at higher voltages and
temperatures will result in a reduction in POH to achieve the same reliability performance.
For assessment of alternate use cases, contact your local TI representative.
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Table 5-3. Power on Hour (POH) Limits
IP
Duty Cycle
Voltage Domain
Voltage (V) (max)
Frequency (MHz)
(max)
Tj(°C)
POH
ARM
70%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
30%
vdd_mpu
Retention
0
40%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
60%
vdd_mpu
OPP_HIGH
1000
55%
vdd_mpu
OPP_HIGH
1500
Automotive Profile(1)
20000
Others(2)
45%
vdd_mpu
OPP_NOM
1000
100%
vdd_mpu
OPP_HIGH
1176
Automotive Profile(1)
20000
100%
vdd_mpu
OPP_NOM
1000
Automotive Profile(1)
20000
100%
All
Automotive Profile(1)
20000
All Support OPPs
(1) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
10%@125°C.
(2) Others covers all other IP's voltage and temperature combinations that are not specified in the table, and are constrained by other
sections of this data manual.
5.4
Recommended Operating Conditions
The device is used under the recommended operating conditions described in Table 5-4.
NOTE
Logic functions and parameter values are not assured out of the range specified in the
recommended operating conditions.
Table 5-4. Recommended Operating Conditions
PARAMETER
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
See Section 5.5
V
vdd_mpu
Supply voltage range for MPU domain
See Section 5.5
V
vdd_gpu
GPU voltage domain supply
See Section 5.5
V
vdd_dsp
DSP voltage domain supply
See Section 5.5
V
vdd_iva
IVA voltage domain supply
See Section 5.5
V
vdd_rtc
RTC voltage domain supply
See Section 5.5
vdda_usb1
DPLL_USB and HS USB1 1.8V
analog power supply
1.71
1.80
1.71
1.80
Maximum noise (peak-peak)
vdda_usb2
HS USB2 1.8V analog power supply
HS USB1 3.3V analog power supply.If
USB1 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb1_dm/usb1_dp pins are left
unconnected
- The USB1 PHY is kept powered
down
Maximum noise (peak-peak)
128
Specifications
1.89
1.836
1.89
50
Maximum noise (peak-peak)
vdda33v_usb1
V
1.836
mVPPmax
50
3.135
3.3
50
V
V
mVPPmax
3.366
3.465
V
mVPPmax
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Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vdda33v_usb2
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
HS USB2 3.3V analog power supply. If
USB2 is not used, this pin can
alternatively be connected to VSS if
the following requirements are met:
- The usb2_dm/usb2_dp pins are left
unconnected
- The USB2 PHY is kept powered
down
3.135
3.3
3.366
3.465
Maximum noise (peak-peak)
vdda_per
PER PLL and PER HSDIVIDER
analog power supply
50
1.71
Maximum noise (peak-peak)
vdda_ddr
DPLL_DDR and DDR HSDIVIDER
analog power supply
1.71
1.80
DPLL_DEBUG analog power supply
1.71
1.80
DPLL_DSP and DPLL_IVA analog
power supply
1.71
1.80
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.71
1.80
DPLL_SPARE analog power supply
vdda_gpu
DPLL_GPU analog power supply
1.71
PLL_HDMI and HDMI analog power
supply
DPLL_PCIe_REF and PCIe analog
power supply
1.80
1.71
1.80
PCIe ch0 RX/TX analog power supply
1.71
1.80
DPLL_SATA and SATA RX/TX analog
power supply
DPLL_USB_OTG_SS and USB3.0
RX/TX analog power supply
1.71
DPLL_VIDEO1 analog power supply
MLBP IO power supply
1.80
1.71
1.80
DPLL_MPU analog power supply
1.71
1.80
HFOSC analog power supply
RTC bias and RTC LFOSC analog
power supply
Maximum noise (peak-peak)
1.89
1.836
1.89
1.836
1.89
1.836
1.89
1.71
1.80
1.80
50
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V
mVPPmax
V
mVPPmax
1.89
V
mVPPmax
1.836
1.89
1.836
1.89
1.836
1.89
V
mVPPmax
V
mVPPmax
V
mVPPmax
1.89
V
mVPPmax
1.836
1.89
V
mVPPmax
1.89
50
1.71
V
mVPPmax
1.80
1.80
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_rtc
1.836
50
1.71
V
mVPPmax
50
1.71
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_osc
1.89
50
Maximum noise (peak-peak)
vdda_mpu_abe
1.836
V
mVPPmax
1.80
1.71
Maximum noise (peak-peak)
vdds_mlbp
1.89
50
Maximum noise (peak-peak)
vdda_video
1.836
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_usb3
1.89
50
Maximum noise (peak-peak)
vdda_sata
1.836
50
Maximum noise (peak-peak)
vdda_pcie0
1.80
1.71
Maximum noise (peak-peak)
vdda_pcie
1.89
50
Maximum noise (peak-peak)
vdda_hdmi
1.836
50
Maximum noise (peak-peak)
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_pll_spare
1.89
50
Maximum noise (peak-peak)
vdda_core_gmac
1.836
50
Maximum noise (peak-peak)
vdda_dsp_iva
V
mVPPmax
50
Maximum noise (peak-peak)
vdda_debug
1.80
UNIT
V
mVPPmax
1.89
V
mVPPmax
Specifications
129
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Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vdda_csi
DESCRIPTION
CSI Interface 1.8v Supply
MIN (2)
NOM
MAX DC (3)
MAX (2)
1.71
1.80
1.836
1.89
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
vdds18v
1.8V power supply
50
Maximum noise (peak-peak)
vdds18v_ddr1
EMIF1 bias power supply
1.71
vdds_ddr1
1.80
V
mVPPmax
50
Maximum noise (peak-peak)
UNIT
V
mVPPmax
1.836
1.89
50
V
mVPPmax
EMIF1 power supply
(1.5V for DDR3 mode /
1.35V DDR3L mode)
1.35-V
Mode
1.28
1.35
1.377
1.42
1.5-V Mode
1.43
1.50
1.53
1.57
Maximum noise (peakpeak)
1.35-V
Mode
50
V
mVPPmax
1.5-V Mode
vddshv5
vddshv1
vddshv10
vddshv11
vddshv2
vddshv3
vddshv4
130
Specifications
Dual Voltage (1.8V or
3.3V) power supply for
the RTC Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the VIN2 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
Dual Voltage (1.8V or
1.8-V Mode
3.3V) power supply for
3.3-V Mode
the GPMC Power Group
pins
1.71
1.80
1.836
1.89
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
Dual Voltage (1.8V or
3.3V) power supply for
the MMC2 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the VOUT Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the GENERAL Power
Group pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the MMC4 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
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Table 5-4. Recommended Operating Conditions (continued)
PARAMETER
vddshv6
vddshv7
vddshv8
vddshv9
DESCRIPTION
MIN (2)
NOM
MAX DC (3)
MAX (2)
Dual Voltage (1.8V or
3.3V) power supply for
the VIN1 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the WIFI Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the MMC1 Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.8-V Mode
1.71
1.80
1.836
1.89
3.3-V Mode
3.135
3.30
3.366
3.465
Maximum noise (peakpeak)
1.8-V Mode
50
UNIT
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
50
V
mVPPmax
3.3-V Mode
V
50
mVPPmax
3.3-V Mode
vss
Ground supply
0
V
vssa_hdmi
DPLL_HDMI and HDMI PHY analog
ground
0
V
vssa_pcie
PCIe analog ground
0
V
vssa_usb
HS USB1 and HS USB2 analog
ground
0
V
vssa_usb3
DPLL_USB and USB3.0 RX/TX
analog ground
0
V
vssa_csi
CSI Interface 0v Supply
0
V
vssa_sata
SATA TX ground
0
V
vssa_video
DPLL_VIDEO1 analog ground
0
V
vssa_osc0
OSC0 analog ground
0
V
vssa_osc1
OSC1 analog ground
0
V
(1)
TJ
Operating junction
temperature range
Automotive
ddr1_vref0
Reference Power Supply EMIF1
-40
+125
0.5*vdds_ddr1
°C
V
(1) Refer to Power on Hours table Table 5-3 for limitations.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
5.5
Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
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CAUTION
The OPP voltage and frequency values may change following the silicon
characterization result.
Table 5-5 describes the maximum supported frequency per speed grade for DRA72x devices.
Table 5-5. Speed Grade Maximum Frequency
Device Speed
Maximum frequency (MHz)
MPU
DSP
IVA
GPU
IPU
L3
DDR3/DDR3L
DRA72xxP
1500
700
532
532
212.8
266
667 (DDR3-1333)
DRA72xxL
1176
700
532
532
212.8
266
667 (DDR3-1333)
DRA72xxJ
1000
700
532
532
212.8
266
667 (DDR3-1333)
DRA72xxH
800
700
532
532
212.8
266
667 (DDR3-1333)
(1) N/A in this table stands for Not Applicable.
5.5.1
AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in Table 5-6.
Table 5-6. AVS and ABB Requirements per vdd_* Supply
Supply
AVS Required?
vdd_core
Yes, for all OPPs
No
vdd_mpu
Yes, for all OPPs
Yes, for all OPPs
vdd_iva
Yes, for all OPPs
Yes, for all OPPs
vdd_dsp
Yes, for all OPPs
Yes, for all OPPs
vdd_gpu
Yes, for all OPPs
Yes, for all OPPs
vdd_rtc
No
No
5.5.2
ABB Required?
Voltage And Core Clock Specifications
Table 5-7 shows the recommended OPP per voltage domain.
Table 5-7. Voltage Domains Operating Performance Points (1)
DOMAIN
CONDITION
OPP_NOM
MIN (3)
VD_CORE (V)
BOOT (Before AVS is
enabled) (5)
After AVS is enabled
BOOT (Before AVS is
enabled) (5)
After AVS is enabled
(5)
VD_RTC (V)
132
(7)
Specifications
-
1.15
AVS
AVS
Voltage Voltage
(6)
(6) –
3.5%
(5)
VD_MPU (V)
1.11
1.11
1.15
AVS
AVS
Voltage Voltage
(6)
(6)
–
3.5%
0.84
OPP_OD
NOM (2) MAX (3)
0.88 to
1.06
MIN (3)
OPP_HIGH
NOM (2) MAX (3)
MIN (3)
NOM (2) MAX DC
(4)
1.2
Not Applicable
Not Applicable
1.16
Not Applicable
Not Applicable
1.2
Not Applicable
Not Applicable
1.16
1.16
AVS
AVS
AVS
AVS
AVS
Voltage Voltage Voltage Voltage Voltage
(6)
(6)
(6)
(6)
–
+ 5%
(6) –
3.5%
3.5%
Not Applicable
AVS
Voltage
(6)
+2%
MAX (3)
AVS
Voltage
+ 5%
(6)
Not Applicable
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Table 5-7. Voltage Domains Operating Performance Points (1) (continued)
DOMAIN
CONDITION
OPP_NOM
MIN (3)
Others (V)
BOOT (Before AVS is
enabled) (5)
After AVS is enabled
(5)
1.02
OPP_OD
NOM (2) MAX (3)
1.06
AVS
AVS
Voltage Voltage
(6)
(6)
–
3.5%
1.16
1.16
MIN (3)
NOM (2) MAX (3)
Not Applicable
OPP_HIGH
MIN (3)
NOM (2) MAX DC
(4)
MAX (3)
Not Applicable
AVS
AVS
AVS
AVS
AVS
Voltage Voltage Voltage Voltage Voltage
(6)
(6)
(6)
(6)
(6)
–
+ 5%
–
3.5%
3.5%
AVS
Voltage
(6)
+2%
AVS
Voltage
+ 5%
(6)
(1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with
the ability to modify the voltage to comply with future recommendations.
(2) In a typical implementation, the power supply should target the NOM voltage.
(3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(4) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(6) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
– OPP_NOM for MPU: 0.85 V – 1.15 V
– OPP_NOM for CORE and Others: 0.85 V - 1.15 V
– OPP_OD: 0.94 V - 1.15 V
– OPP_HIGH: 1.05 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(7) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
(8) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM
boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-8. Supported OPP vs Max Frequency (2)
DESCRIPTION
OPP_NOM
OPP_OD
OPP_HIGH
Max Freq. (MHz)
Max Freq. (MHz)
Max Freq. (MHz)
MPU_CLK
1000
1176
1500
DSP_CLK
600
700
700
IVA_GCLK
388.3
430
532
GPU_CLK
425.6
500
532
CORE_IPUx_CLK
212.8
N/A
N/A
L3_CLK
266
N/A
N/A
DDR3 / DDR3L
667 (DDR3-1333)
N/A
N/A
RTC_FCLK
0.034
N/A
N/A
VD_MPU
VD_DSP
VD_IVA
VD_GPU
VD_CORE
VD_RTC
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(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-5).
5.5.3
Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
Table 5-9. Maximum Supported Frequency
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
AES1
AES1_L3_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
AES2
AES2_L3_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
ATL
ATL_ICLK_L3
Int
266
ATL_L3_GICLK
CORE_X2_CLK
DPLL_CORE
ATLPCLK
Func
266
ATL_GFCLK
CORE_X2_CLK
DPLL_CORE
PER_ABE_X1_GF
CLK
DPLL_ABE
FUNC_32K_CLK
OSC1
RTC Oscillator
BB2D
HDMI_CLK
DPLL_HDMI
VIDEO1_CLK
DPLL_VIDEO1
BB2D_FCLK
Func
354.6
BB2D_GFCLK
BB2D_GFCLK
DPLL_CORE
BB2D_ICLK
Int
266
DSS_L3_GICLK
CORE_X2_CLK
DPLL_CORE
COUNTER_32K_F
CLK
Func
0.032
FUNC_32K_CLK
SYS_CLK1/610
OSC1
COUNTER_32K_IC
LK
Int
38.4
WKUPAON_GICLK
CTRL_MODULE_B
ANDGAP
L3INSTR_TS_GCL
K
Int
CTRL_MODULE_C
ORE
L4CFG_L4_GICLK
Int
133
L4CFG_L4_GICLK
CTRL_MODULE_
WKUP
WKUPAON_GICLK
Int
38.4
WKUPAON_GICLK
DCAN1
DCAN1_FCLK
COUNTER_32K
Func
DCAN1_ICLK
134
Int
4.8
38.4
266
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
L3INSTR_TS_GCLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
SYS_CLK2
OSC2
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN1_SYS_CLK
WKUPAON_GICLK
DCAN2
DCAN2_FCLK
Func
38.4
DCAN2_SYS_CLK
SYS_CLK1
OSC1
DCAN2_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DES3DES
DES_CLK_L3
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DLL
EMIF_DLL_FCLK
Func
EMIF_DLL_FC
LK
EMIF_DLL_GCLK
EMIF_DLL_GCLK
DPLL_DDR
DLL_AGING
FCLK
Int
38.4
L3INSTR_DLL_AGING
_GCLK
Specifications
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
DMA_CRYPTO
DMA_CRYPTO_FC
LK
Int &
Func
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DMA_CRYPTO_IC
LK
Int
133
L4SEC_L4_GICLK
CORE_X2_CLK
DPLL_CORE
DMM_CLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DMM
DPLL_DEBUG
SYSCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
OSC1
DSP1
DSP1_FICLK
Int &
Func
DSP_CLK
DSP1_GFCLK
DSP_GFCLK
DPLL_DSP
DSS
DSS_HDMI_CEC_
CLK
Func
0.032
HDMI_CEC_GFCLK
SYS_CLK1/610
OSC1
DSS_HDMI_PHY_
CLK
Func
48
HDMI_PHY_GFCLK
FUNC_192M_CLK
DPLL_PER
DSS_CLK
Func
192
DSS_GFCLK
DSS_CLK
DPLL_PER
HDMI_CLKINP
Func
38.4
HDMI_DPLL_CLK
SYS_CLK1
OSC1
DSS DISPC
SYS_CLK2
OSC2
DSS_L3_ICLK
Int
266
DSS_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VIDEO1_CLKINP
Func
38.4
VIDEO1_DPLL_CLK
SYS_CLK1
OSC1
SYS_CLK2
OSC2
SYS_CLK1
OSC1
VIDEO2_CLKINP
Func
38.4
VIDEO2_DPLL_CLK
DPLL_DSI1_A_CL
K1
Func
209.3
N/A
DPLL_DSI1_B_CL
K1
Func
209.3
DPLL_DSI1_C_CL
K1
Func
209.3
DPLL_HDMI_CLK1
Func
185.6
LCD1_CLK
Func
LCD2_CLK
N/A
SYS_CLK2
OSC2
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT1
DPLL_VIDEO1
VIDEO1_CLKOUT3
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
DPLL_ABE_X2_CL
K
DPLL_ABE
N/A
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT3
DPLL_VIDEO1
N/A
HDMI_CLK
DPLL_HDMI
209.3
N/A
DPLL_DSI1_A_CL
K1
See DSS data in
the rows above
Func
209.3
N/A
DPLL_DSI1_B_CL
K1
LCD3_CLK
Func
209.3
N/A
DPLL_DSI1_C_CL
K1
F_CLK
Func
209.3
N/A
DPLL_DSI1_A_CL
K1
DSS_CLK
DSS_CLK
DSS_CLK
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
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Specifications
135
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
CUSTEFUSE_L4_GICL
K
CORE_X2_CLK
DPLL_CORE
38.4
CUSTEFUSE_SYS_GF
CLK
SYS_CLK1
OSC1
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
EFUSE_CTRL_CU
ST
ocp_clk
Int
133
sys_clk
Func
ELM_ICLK
Int
ELM
PRCM Clock Name
EMIF_OCP_FW
L3_CLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
EMIF_PHY1
EMIF_PHY1_FCLK
Func
DDR
EMIF_PHY_GCLK
EMIF_PHY_GCLK
DPLL_DDR
EMIF1
EMIF1_ICLK
Int
266
EMIF_L3_GICLK
CORE_X2_CLK
DPLL_CORE
FPKA
PKA_CLK
Int &
Func
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GMAC_SW
CPTS_RFT_CLK
Func
266
GMAC_RFT_CLK
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
GPIO1
GPIO2
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
MAIN_CLK
Int
125
GMAC_MAIN_CLK
GMAC_250M_CLK
DPLL_GMAC
MHZ_250_CLK
Func
250
GMII_250MHZ_CLK
GMII_250MHZ_CL
K
DPLL_GMAC
MHZ_5_CLK
Func
5
RGMII_5MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
MHZ_50_CLK
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
RMII1_MHZ_50_CL
K
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
RMII2_MHZ_50_CL
K
Func
50
RMII_50MHZ_CLK
GMAC_RMII_HS_C
LK
DPLL_GMAC
GPIO1_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
OSC1
GPIO1_DBCLK
Func
0.032
WKUPAON_SYS_GFC
LK
WKUPAON_32K_G
FCLK
GPIO2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO2_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
OSC1
GPIO3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO3_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
OSC1
GPIO4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO4_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
RTC Oscillator
RTC Oscillator
GPIO3
RTC Oscillator
GPIO4
GPIO5
GPIO6
136
Specifications
DPLL_CORE
OSC1
RTC Oscillator
GPIO5_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO5_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
DPLL_CORE
OSC1
RTC Oscillator
GPIO6_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
GPIO6_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
DPLL_CORE
OSC1
RTC Oscillator
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
GPIO7
GPIO7_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO7_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
PIDBCLK
Func
0.032
GPIO_GFCLK
GPIO8
OSC1
RTC Oscillator
GPIO8_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPIO8_DBCLK
Func
0.032
GPIO_GFCLK
FUNC_32K_CLK
OSC1
PIDBCLK
Func
0.032
GPIO_GFCLK
GPMC
GPMC_FCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
GPU
GPU_FCLK1
Func
GPU_CLK
GPU_CORE_GCLK
CORE_GPU_CLK
DPLL_CORE
GPU_FCLK2
Func
GPU_CLK
GPU_HYD_GCLK
RTC Oscillator
PER_GPU_CLK
DPLL_PER
GPU_GCLK
DPLL_GPU
CORE_GPU_CLK
DPLL_CORE
PER_GPU_CLK
DPLL_PER
GPU_GCLK
DPLL_GPU
GPU_ICLK
Int
266
GPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDMI PHY
DSS_HDMI_PHY_
CLK
Func
38.4
HDMI_PHY_GFCLK
FUNC_192M_CLK
DPLL_PER
HDQ1W
HDQ1W_ICLK
Int &
Func
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
HDQ1W_FCLK
Func
12
PER_12M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C1_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C1_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C2_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C3_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
DPLL_CORE
I2C1
I2C2
I2C3
I2C4
I2C5
I2C6
I2C4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
I2C4_FCLK
Func
96
PER_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C5_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C5_FCLK
Func
96
IPU_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
I2C6_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
I2C6_FCLK
Func
96
IPU_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
IEEE1500_2_OCP
PI_L3CLK
Int &
Func
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
IPU1
IPU1_GFCLK
Int &
Func
425.6
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
CORE_IPU_ISS_B
OOST_CLK
DPLL_CORE
CORE_IPU_ISS_B
OOST_CLK
DPLL_CORE
IPU2
IPU2_GFCLK
Int &
Func
425.6
IPU2_GFCLK
IVA
IVA_GCLK
Int
IVA_GCLK
IVA_GCLK
IVA_GFCLK
DPLL_IVA
KBD
KBD_FCLK
Func
0.032
WKUPAON_SYS_GFC
LK
WKUPAON_32K_G
FCLK
OSC1
PICLKKBD
Func
0.032
WKUPAON_SYS_GFC
LK
L3_INSTR
RTC Oscillator
KBD_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
PICLKOCP
Int
38.4
WKUPAON_GICLK
DPLL_ABE_X2_CL
K
DPLL_ABE
L3_CLK
Int
L3_CLK
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
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Specifications
137
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
L3_MAIN
L3_CLK1
Int
L3_CLK
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L3_CLK2
Int
L3_CLK
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_CFG
L4_CFG_CLK
Int
133
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER1
L4_PER1_CLK
Int
133
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER2
L4_PER2_CLK
Int
133
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_PER3
L4_PER3_CLK
Int
133
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
L4_WKUP
L4_WKUP_CLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
138
MAILBOX1
MAILBOX1_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX2
MAILBOX2_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX3
MAILBOX3_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX4
MAILBOX4_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX5
MAILBOX5_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX6
MAILBOX6_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX7
MAILBOX7_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX8
MAILBOX8_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX9
MAILBOX9_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX10
MAILBOX10_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX11
MAILBOX11_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX12
MAILBOX12_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MAILBOX13
MAILBOX13_FLCK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
Specifications
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
McASP1
MCASP1_AHCLKR
Func
100
MCASP1_AHCLKR
MCASP1_AHCLKX
MCASP1_FCLK
MCASP1_ICLK
Func
Func
Int
100
192
266
MCASP1_AHCLKX
MCASP1_AUX_GFCLK
PLL / OSC /
Source Clock
Name
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATLCLK0
Module ATL
ATLCLK1
Module ATL
ATLCLK2
Module ATL
ATLCLK3
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATLCLK0
Module ATL
ATLCLK1
Module ATL
ATLCLK2
Module ATL
ATLCLK3
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
IPU_L3_GICLK
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Specifications
139
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
McASP2
MCASP2_AHCLKR
Func
100
MCASP2_AHCLKR
MCASP2_AHCLKX
MCASP2_FCLK
MCASP2_ICLK
140
Specifications
Func
Func
Int
100
192
266
MCASP2_AHCLKX
MCASP2_AUX_GFCLK
PLL / OSC /
Source Clock
Name
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
L4PER2_L3_GICLK
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www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
McASP3
MCASP3_AHCLKX
Func
100
MCASP3_AHCLKX
MCASP3_FCLK
McASP4
Func
192
MCASP3_AUX_GFCLK
PLL / OSC /
Source Clock
Name
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
MCASP3_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP4_AHCLKX
Func
100
MCASP4_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
MCASP4_FCLK
MCASP4_ICLK
Func
Int
192
266
MCASP4_AUX_GFCLK
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
L4PER2_L3_GICLK
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VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
Specifications
141
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
McASP5
MCASP5_AHCLKX
Func
100
MCASP5_AHCLKX
MCASP5_FCLK
McASP6
MCASP5_AUX_GFCLK
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP6_AHCLKX
Func
100
MCASP6_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
MCASP6_ICLK
Specifications
192
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
MCASP5_ICLK
MCASP6_FCLK
142
Func
PLL / OSC /
Source Clock
Name
Func
Int
192
266
MCASP6_AUX_GFCLK
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
SYS_CLK1
OSC1
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
PER_ABE_X1_GF
CLK
DPLL_ABE
L4PER2_L3_GICLK
VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
McASP7
MCASP7_AHCLKX
Func
100
MCASP7_AHCLKX
MCASP7_FCLK
McASP8
MCASP7_AUX_GFCLK
DPLL_ABE
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MCASP8_AHCLKX
Func
100
MCASP8_AHCLKX
DPLL_ABE_X2_CL
K
DPLL_ABE
MCASP8_ICLK
McSPI2
192
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
MCASP7_ICLK
MCASP8_FCLK
McSPI1
Func
PLL / OSC /
Source Clock
Name
Func
192
Int
266
MCASP8_AUX_GFCLK
SYS_CLK1
OSC1
FUNC_96M_AON_
CLK
DPLL_PER
ATL_CLK3
Module ATL
ATL_CLK2
Module ATL
ATL_CLK1
Module ATL
ATL_CLK0
Module ATL
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
MLB_CLK
Module MLB
MLBP_CLK
Module MLB
PER_ABE_X1_GF
CLK
DPLL_ABE
L4PER2_L3_GICLK
VIDEO1_CLK
DPLL_ABE
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
SPI1_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
SPI1_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
SPI2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SPI2_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
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Specifications
143
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
McSPI3
SPI3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SPI3_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
McSPI4
SPI4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SPI4_FCLK
Func
48
PER_48M_GFCLK
PER_48M_GFCLK
DPLL_PER
MLB_SS
MLB_L3_ICLK
Int
266
MLB_SHB_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MLB_L4_ICLK
Int
133
MLB_SPB_L4_GICLK
CORE_X2_CLK
DPLL_CORE
MLB_FCLK
Func
266
MLB_SYS_L3_GFCLK
CORE_X2_CLK
DPLL_CORE
CTRLCLK
Int &
Func
96
LVDSRX_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
CSI2_0
CSI2_1
MMC1
CTRLCLK
Int &
Func
96
LVDSRX_96M_GFCLK
FUNC_192M_CLK
DPLL_PER
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
MMC1_CLK_32K
Func
0.032
L3INIT_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC1_FCLK
Func
192
MMC1_GFCLK
FUNC_192M_CLK
DPLL_PER
FUNC_256M_CLK
DPLL_PER
MMC1_ICLK1
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC1_ICLK2
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
MMC2_CLK_32K
Func
0.032
L3INIT_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC2_FCLK
Func
192
MMC2_GFCLK
FUNC_192M_CLK
DPLL_PER
FUNC_256M_CLK
DPLL_PER
128
MMC2
128
MMC3
MMC2_ICLK1
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC2_ICLK2
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
MMC3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMC3_CLK_32K
Func
0.032
L4PER_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC3_FCLK
Func
48
MMC3_GFCLK
FUNC_192M_CLK
DPLL_PER
CORE_X2_CLK
DPLL_CORE
192
MMC4
MMC4_ICLK
Int
266
L4PER_L3_GICLK
MMC4_CLK_32K
Func
0.032
L4PER_32K_GFCLK
FUNC_32K_CLK
OSC1
MMC4_FCLK
Func
48
MMC4_GFCLK
FUNC_192M_CLK
DPLL_PER
192
MMU_EDMA
MMU1_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MMU_PCIESS
MMU2_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
MPU
MPU_CLK
Int &
Func
MPU_CLK
MPU_GCLK
MPU_GCLK
DPLL_MPU
MPU_EMU_DBG
FCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
OSC1
MPU_GCLK
DPLL_MPU
OCMC_RAM1
OCMC1_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCMC_ROM
OCMC_L3_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCP_WP_NOC
PICLKOCPL3
Int
266
L3INSTR_L3_GICLK
CORE_X2_CLK
DPLL_CORE
OCP2SCP1
L4CFG1_ADAPTE
R_CLKIN
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
144
Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
L4CFG2_ADAPTE
R_CLKIN
Int
133
L4CFG_L4_GICLK
CORE_X2_CLK
DPLL_CORE
OCP2SCP3
L4CFG3_ADAPTE
R_CLKIN
Int
133
L3INIT_L4_GICLK
CORE_X2_CLK
DPLL_CORE
PCIESS1
PCIE1_PHY_WKU
P_CLK
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
RTC Oscillator
Instance Name
Input Clock Name
OCP2SCP2
PCIESS2
PRCM_MPU
PCIe_SS1_FICLK
Int
266
PCIE_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PCIEPHY_CLK
Func
2500
PCIE_PHY_GCLK
PCIE_PHY_GCLK
APLL_PCIE
PCIEPHY_CLK_DI
V
Func
1250
PCIE_PHY_DIV_GCLK
PCIE_PHY_DIV_G
CLK
APLL_PCIE
PCIE1_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE1_PWR_CLK
Func
38.4
PCIE_SYS_GFCLK
SYS_CLK1
OSC1
PCIE2_PHY_WKU
P_CLK
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
RTC Oscillator
PCIe_SS2_FICLK
Func
266
PCIE_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PCIEPHY_CLK
Func
2500
PCIE_PHY_GCLK
PCIE_PHY_GCLK
APLL_PCIE
PCIEPHY_CLK_DI
V
Func
1250
PCIE_PHY_DIV_GCLK
PCIE_PHY_DIV_G
CLK
APLL_PCIE
PCIE2_REF_CLKI
N
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
PCIE2_PWR_CLK
Func
38.4
PCIE_SYS_GFCLK
SYS_CLK1
OSC1
32K_CLK
Func
0.032
FUNC_32K_CLK
SYS_CLK1/610
OSC1
SYS_CLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
PWMSS1
PWMSS1_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PWMSS2
PWMSS2_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
PWMSS3
PWMSS3_GICLK
Int &
Func
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
QSPI
QSPI_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
QSPI_FCLK
Func
128
QSPI_GFCLK
FUNC_256M_CLK
DPLL_PER
PER_QSPI_CLK
DPLL_PER
RNG
RNG_ICLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
RTC_SS
RTC_ICLK
Int
133
RTC_L4_GICLK
CORE_X2_CLK
DPLL_CORE
RTC_FCLK
Func
RTC_FCLK
RTC Oscillator
SAR_ROM
SATA
PRCM_ROM_CLO
CK
Int
266
RTC_AUX_CLK
SYS_32K
FUNC_32K_CLK
SYS_CLK1/610
OSC1
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SATA_FICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SATA_PMALIVE_F
CLK
Func
48
L3INIT_48M_GFCLK
FUNC_192M_CLK
DPLL_PER
REF_CLK
Func
38
SATA_REF_GFCLK
SYS_CLK1
OSC1
SDMA
SDMA_FCLK
Int &
Func
266
DMA_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SHA2MD51
SHAM_1_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SHA2MD52
SHAM_2_CLK
Int
266
L4SEC_L3_GICLK
CORE_X2_CLK
DPLL_CORE
SL2
IVA_GCLK
Int
IVA_GCLK
IVA_GCLK
IVA_GFCLK
DPLL_IVA
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Specifications
145
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
SMARTREFLEX_C
ORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
DPLL_CORE
SYSCLK
Func
38.4
WKUPAON_ICLK
SMARTREFLEX_D
SP
SMARTREFLEX_G
PU
SMARTREFLEX_IV
AHD
SMARTREFLEX_M
PU
MCLK
Int
133
COREAON_L4_GICLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
MCLK
Int
133
COREAON_L4_GICLK
CORE_X2_CLK
SYSCLK
Func
38.4
WKUPAON_ICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SPINLOCK
SPINLOCK_ICLK
Int
266
L4CFG_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER1
TIMER1_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
TIMER1_FCLK
Func
100
TIMER1_GFCLK
RTC Oscillator
146
Specifications
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
Copyright © 2016–2017, Texas Instruments Incorporated
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DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER2
TIMER2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER2_FCLK
Func
100
TIMER2_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER3
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
TIMER3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER3_FCLK
Func
100
TIMER3_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER4
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
TIMER4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER4_FCLK
Func
100
TIMER4_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
Copyright © 2016–2017, Texas Instruments Incorporated
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Specifications
147
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER5
TIMER5_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER5_FCLK
Func
100
TIMER5_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER6
TIMER6_ICLK
Int
266
IPU_L3_GICLK
TIMER6_FCLK
Func
100
TIMER6_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER7
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
TIMER7_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER7_FCLK
Func
100
TIMER7_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
148
Specifications
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
Copyright © 2016–2017, Texas Instruments Incorporated
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DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER8
TIMER8_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER8_FCLK
Func
100
TIMER8_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER9
TIMER9_ICLK
Int
266
L4PER_L3_GICLK
TIMER9_FCLK
Func
100
TIMER9_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER10
TIMER10_ICLK
Int
266
L4PER_L3_GICLK
TIMER10_FCLK
Func
100
TIMER10_GFCLK
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
CORE_X2_CLK
DPLL_CORE
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER11
TIMER11_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER11_FCLK
Func
100
TIMER11_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER12
TIMER13
TIMER12_ICLK
Int
38.4
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER12_FCLK
Func
0.032
OSC_32K_CLK
RC_CLK
RC oscillator
TIMER13_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER13_FCLK
Func
100
TIMER13_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER14
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
TIMER14_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER14_FCLK
Func
100
TIMER14_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
150
Specifications
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER15
TIMER15_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER15_FCLK
Func
100
TIMER15_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
TIMER16
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
TIMER16_ICLK
Int
266
L4PER3_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TIMER16_FCLK
Func
100
TIMER16_GFCLK
SYS_CLK1
OSC1
FUNC_32K_CLK
OSC1
RTC Oscillator
SYS_CLK2
OSC2
XREF_CLK0
XREF_CLK0
XREF_CLK1
XREF_CLK1
XREF_CLK2
XREF_CLK2
XREF_CLK3
XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
TPCC
TPCC_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TPTC1
TPTC0_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
TPTC2
TPTC1_GCLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART1
UART1_FCLK
Func
48
UART1_GFCLK
FUNC_192M_CLK
DPLL_PER
UART1_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART2
UART2_FCLK
Func
48
UART2_GFCLK
FUNC_192M_CLK
DPLL_PER
UART2_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART3
UART3_FCLK
Func
48
UART3_GFCLK
FUNC_192M_CLK
DPLL_PER
UART3_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART4_FCLK
Func
48
UART4_GFCLK
FUNC_192M_CLK
DPLL_PER
UART4_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART5
UART5_FCLK
Func
48
UART5_GFCLK
FUNC_192M_CLK
DPLL_PER
UART5_ICLK
Int
266
L4PER_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART6
UART6_FCLK
Func
48
UART6_GFCLK
FUNC_192M_CLK
DPLL_PER
UART6_ICLK
Int
266
IPU_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART7
UART7_FCLK
Func
48
UART7_GFCLK
FUNC_192M_CLK
DPLL_PER
UART7_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART8
UART8_FCLK
Func
48
UART8_GFCLK
FUNC_192M_CLK
DPLL_PER
UART8_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART4
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Table 5-9. Maximum Supported Frequency (continued)
Module
Clock Sources
Instance Name
Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
UART9
UART9_FCLK
Func
48
UART9_GFCLK
FUNC_192M_CLK
DPLL_PER
UART9_ICLK
Int
266
L4PER2_L3_GICLK
CORE_X2_CLK
DPLL_CORE
UART10
UART10_FCLK
Func
48
UART10_GFCLK
FUNC_192M_CLK
DPLL_PER
UART10_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
USB1
USB2
USB1_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB3PHY_REF_C
LK
Func
34.3
USB_LFPS_TX_GFCL
K
CORE_USB_OTG_
SS_LFPS_TX_CLK
DPLL_CORE
USB2PHY1_TREF
_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB2PHY1_REF_
CLK
Func
960
L3INIT_960M_GFCLK
L3INIT_960_GFCL
K
DPLL_USB
USB2_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB2PHY2_TREF
_CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB2PHY2_REF_
CLK
Func
960
L3INIT_960M_GFCLK
L3INIT_960_GFCL
K
DPLL_USB
USB3_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
USB3PHY_PWRS_
CLK
Func
38.4
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC1
USB_PHY1_CORE USB2PHY1_WKUP
_CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_CLK1/610
OSC1
USB_PHY2_CORE USB2PHY2_WKUP
_CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_CLK1/610
OSC1
USB_PHY3_CORE USB3PHY_WKUP_
CLK
Func
0.032
COREAON_32K_GFCL
K
SYS_CLK1/610
OSC1
USB3
VCP1
VCP1_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VCP2
VCP2_CLK
Int
266
L3MAIN1_L3_GICLK
CORE_X2_CLK
DPLL_CORE
VIP1
L3_CLK_PROC_CL
K
Int &
Func
266
VIP1_GCLK
CORE_X2_CLK
DPLL_CORE
CORE_ISS_MAIN_
CLK
DPLL_CORE
VPE
L3_CLK_PROC_CL
K
Int &
Func
300
VPE_GCLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT4
DPLL_VIDEO1
WD_TIMER1
PIOCPCLK
Int
38.4
WKUPAON_GICLK
WD_TIMER2
Specifications
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
PITIMERCLK
Func
0.032
OSC_32K_CLK
RC_CLK
RC oscillator
WD_TIMER2_ICLK
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC1
DPLL_ABE_X2_CL
K
DPLL_ABE
WKUPAON_32K_G
FCLK
RTC Oscillator
WD_TIMER2_FCL
K
152
SYS_CLK1
Func
0.032
WKUPAON_SYS_GFC
LK
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5.6
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Power Consumption Summary
NOTE
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7
Electrical Characteristics
NOTE
The data specified in Section 5.7.1 through Section 5.7.14 are subject to change.
NOTE
The interfaces or signals described in Section 5.7.1 through Section 5.7.14 correspond to the
interfaces or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
5.7.1
LVCMOS DDR DC Electrical Characteristics
Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.
NOTE
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control
Module of the Device TRM.
Table 5-10. LVCMOS DDR DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0],
ddr1_cke, ddr1_odt[1:0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc;
Balls: AH23 / AB16 / AG22 / AE20 / AC17 / AC18 / AF20 /AH21 / AG21 / AF17 / AE18 / AB18 / AD20 / AC19 / AC20 / AB19 / AF21 / AH22
/ AG23 / AE21 / AF22 / AE22 / AD21 / AD22 / AC21 / AF18 / AE17 / AD18 / AF25 / AF26 / AG26 / AH26 / AF24 / AE24 / AF23 / AE23 /
AC23 / AF27 / AG27 / AF28 / AE26 / AC25 / AC24 / AD25 / V20 / W20 / AB28 / AC28 / AC27 / Y19 / AB27 / Y20 / AA23 / Y22 / Y23 / AA24
/ Y24 / AA26 / AA25 / AA28 / W22 / V23 / W19 / W23 / Y25 / V24 / V25 / Y26 / AD23 / AB23 / AC26 / AA27 / V26;
Driver Mode
VOH
High-level output threshold (IOH = 0.1 mA)
VOL
Low-level output threshold (IOL = 0.1 mA)
CPAD
Pad capacitance (including package capacitance)
ZO
Output impedance (drive
strength)
0.9*VDDS
V
l[2:0] = 000
(Imp80)
80
l[2:0] = 001
(Imp60)
60
l[2:0] = 010
(Imp48)
48
l[2:0] = 011
(Imp40)
40
l[2:0] = 100
(Imp34)
34
0.1*VDDS
V
3
pF
Ω
Single-Ended Receiver Mode
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Table 5-10. LVCMOS DDR DC Electrical Characteristics (continued)
PARAMETER
MIN
VIH
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VIL
Low-level input threshold
VCM
Input common-mode voltage
CPAD
Pad capacitance (including package capacitance)
NOM
MAX
UNIT
VREF+0.1
VDDS+0.2
V
-0.2
VREF-0.1
V
VREF 10%vdds
VREF+
10%vdds
V
3
pF
Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc
Bottom Balls: AH25 / AG25 / AE27 / AE28 / AD27 / AD28 / Y28 / Y27 / V27 / V28 / AG24 / AH24
Driver Mode
VOH
High-level output threshold (IOH = 0.1 mA)
VOL
Low-level output threshold (IOL = 0.1 mA)
CPAD
Pad capacitance (including package capacitance)
ZO
Output impedance (drive
strength)
0.9*VDDS
V
l[2:0] = 000
(Imp80)
80
l[2:0] = 001
(Imp60)
60
l[2:0] = 010
(Imp48)
48
l[2:0] = 011
(Imp40)
40
l[2:0] = 100
(Imp34)
34
0.1*VDDS
V
3
pF
Ω
Single-Ended Receiver Mode
VIH
High-level input threshold
DDR3/DDR3L
VREF+0.1
VDDS+0.2
V
VIL
Low-level input threshold
DDR3/DDR3L
-0.2
VREF-0.1
V
VCM
Input common-mode voltage
VREF 10%vdds
VREF+
10%vdds
V
CPAD
Pad capacitance (including package capacitance)
3
pF
0.2
vdds+0.4
V
VREF 10%vdds
VREF+
10%vdds
V
3
pF
Differential Receiver Mode
VSWING
Input voltage swing
DDR3/DDR3L
VCM
Input common-mode voltage
CPAD
Pad capacitance (including package capacitance)
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the
corresponding ball, see Table 4-2, POWER [10] column.
(2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name
and the corresponding ball, see Table 4-2, POWER [10] column.
5.7.2
HDMIPHY DC Electrical Characteristics
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification and are not
reproduced here.
5.7.3
Dual Voltage LVCMOS I2C DC Electrical Characteristics
Table 5-11 summarizes the DC electrical characteristics for Dual Voltage LVCMOS I2C Buffers.
NOTE
For more information on the I/O cell configurations, see the Control Module section of the
Device TRM.
154
Specifications
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Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: i2c2_scl; i2c1_scl; i2c1_sda; i2c2_sda;
Balls: F17 / C20 / C21 / C25
I2C Standard Mode – 1.8 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
0.1*VDDS
V
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF
0.2*VDDS
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
IOLmin
Low-level output current @VOL=0.2*VDDS
tOF
3
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
mA
250
ns
I2C Fast Mode – 1.8 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.1*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
12
µA
CIN
Input capacitance
10
pF
0.2*VDDS
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
IOLmin
Low-level output current @VOL=0.2*VDDS
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 400 pF
3
20+0.1*Cb
mA
250
ns
I2C Standard Mode – 3.3 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.05*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDS
31
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
31
80
µA
CIN
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
V
IOLmin
Low-level output current @VOL=0.4V
3
mA
IOLmin
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
6
mA
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Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
tOF
MIN
NOM
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
MAX
UNIT
250
ns
I2C Fast Mode – 3.3 V
VIH
Input high-level threshold
VIL
Input low-level threshold
Vhys
Hysteresis
0.7*VDDS
V
0.3*VDDS
V
0.05*VDDS
V
IIN
Input current at each I/O pin with an input voltage
between 0.1*VDDS to 0.9*VDDSS
31
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
31
80
µA
CIN
Input capacitance
10
pF
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
V
IOLmin
Low-level output current @VOL=0.4V
3
mA
IOLmin
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
6
mA
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1*Cb
250
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
40
290
ns
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see Table 4-2, POWER [10] column.
5.7.4
IQ1833 Buffers DC Electrical Characteristics
Table 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
Table 5-12. IQ1833 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk;
Balls: E20;
1.8-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH)
VIL
Input low-level threshold (Does not meet JEDEC VIL)
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
0.75 *
VDDS
V
0.25 *
VDDS
100
2
V
mV
11
µA
1
pF
3.3-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH)
VIL
Input low-level threshold (Does not meet JEDEC VIL)
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
156
Specifications
2.0
V
0.6
400
5
V
mV
11
µA
1
pF
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5.7.5
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
IHHV1833 Buffers DC Electrical Characteristics
Table 5-13 summarizes the DC electrical characteristics for IHHV1833 Buffers.
Table 5-13. IHHV1833 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: porz / rtc_porz / wakeup3 / wakeup0;
Balls: F22 / AB17 / AD17 / AC16;
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
1.2
V
0.4
V
40
mV
0.02
1
µA
1
pF
3.3-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
CPAD
Pad capacitance (including package capacitance)
5.7.6
1.2
V
0.4
V
40
mV
5
8
µA
1
pF
LVCMOS OSC Buffers DC Electrical Characteristics
Table 5-14 summarizes the DC electrical characteristics for LVCMOS OSC Buffers.
Table 5-14. LVCMOS OSC Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: rtc_osc_xi_clkin32 / rtc_osc_xo;
Balls: AE14 / AD14;
1.8-V Mode
5.7.7
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
CPAD
Pad capacitance (including package capacitance)
0.65 *
VDDS
V
0.35 *
VDDS
V
150
mV
3
pF
LVCMOS CSI2 DC Electrical Characteristics
Table 5-15 summarizes the DC electrical characteristics for LVSMOS CSI2 Buffers.
Table 5-15. LVCMOS CSI2 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signals MUXMODE0 : csi2_0_dx[4:0]; csi2_0_dy[4:0]; csi2_1_dx[2:0]; csi2_1_dy[2:0];
Bottom Balls: AE1 / AD2 / AF1 / AE2 / AF2 / AF3 / AH4 / AG4 / AH3 / AG3 / AG5 / AH5 / AG6 / AH6 / AH7 / AG7
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
VIH
Input high-level voltage
1350
mV
VIL
Input low-level voltage
880
550
mV
VITH
Input high-level threshold
880
mV
VITL
Input low-level threshold
550
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Table 5-15. LVCMOS CSI2 DC Electrical Characteristics (continued)
PARAMETER
VHYS
Input hysteresis
MIN
NOM
MAX
UNIT
25
mV
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
VIH
Input high-level voltage
VIL
Input low-level voltage
880
VITH
Input high-level threshold
VITL
Input low-level threshold
VHYS
Input hysteresis
mV
300
mV
880
mV
300
mV
25
mV
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
VIDTH
Differential input high-level threshold
VIDTL
Differential input low-level threshold
–70
mV
VIDMAX
Maximum differential input voltage
270
mV
VIHHS
Single-ended input high voltage
460
mV
VILHS
Single-ended input low voltage
VCMRXDC
ZID
70
mV
–40
Differential input common-mode voltage
70
Differential input impedance
80
mV
100
330
mV
125
Ω
(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference
between the VITH threshold and the VITL threshold.
(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VODMAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-7 CSI 2 Signal Descriptions.
5.7.8
BMLB18 Buffers DC Electrical Characteristics
Table 5-16 summarizes the DC electrical characteristics for BMLB18 Buffers.
Table 5-16. BMLB18 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: mlbp_dat_n / mlbp_dat_p / mlbp_sig_n / mlbp_sig_p / mlbp_clk_n / mlbp_clk_p;
Balls: AA2 / AA1 / AC2 / AC1 / AB2 / AB1;
1.8-V Mode
VIH/VIL
Input high-level threshold
VHYS
Input hysteresis voltage
VOD
Differential output voltage (measured with 50ohm resistor
between PAD and PADN)
VCM
Common mode output voltage
CPAD
Pad capacitance (including package capacitance)
158
Specifications
VCM ±
50mV
V
NONE
mV
300
500
mV
1
1.5
V
4
pF
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5.7.9
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
BC1833IHHV Buffers DC Electrical Characteristics
Table 5-17 summarizes the DC electrical characteristics for BC1833IHHV Buffers.
Table 5-17. BC1833IHHV Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: on_off;
Balls: Y11;
1.8-V Mode
VOH
Output high-level threshold (IOH = 2 mA)
VDDS0.45
VOL
Output low-level threshold (IOL = 2 mA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
6
IIN
Input current at each I/O pin
6
IOZ
CPAD
V
0.45
V
mA
12
µA
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
6
µA
Pad capacitance (including package capacitance)
4
pF
3.3-V Mode
VOH
Output high-level threshold (IOH = 100 µA)
VOL
Output low-level threshold (IOL = 100 µA)
VDDS-0.2
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
IIN
Input current at each I/O pin
60
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I(PAD)) is measured and is reported as IOZ
60
µA
CPAD
Pad capacitance (including package capacitance)
4
pF
0.2
6
V
mA
5.7.10 USBPHY DC Electrical Characteristics
NOTE
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
NOTE
USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0
dated April 27, 2000 including ECNs and Errata as applicable.
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5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
Table 5-18 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers.
Table 5-18. Dual Voltage SDIO1833 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
30
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
30
µA
IIN with
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
50
120
210
µA
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
60
120
200
µA
5
pF
pulldown
enabled
IIN with
pullup
enabled
1.27
V
0.58
50
CPAD
Pad capacitance (including package capacitance)
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
(2)
V
mV
1.4
V
0.45
V
3.3-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
IIN
Input current at each I/O pin
110
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
110
µA
IIN with
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
40
100
290
µA
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
10
100
290
µA
5
pF
pulldown
enabled
IIN with
pullup
enabled
0.625 ×
VDDS
V
0.25 × VDDS
40
CPAD
Pad capacitance (including package capacitance)
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
(2)
V
mV
0.75 × VDDS
V
0.125 ×
VDDS
V
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see Table 4-2, POWER [10] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
Table 5-19 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.
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Table 5-19. Dual Voltage LVCMOS DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
VOH
Output high-level threshold (IOH = 2 mA)
VOL
Output low-level threshold (IOL = 2 mA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
IIN
Input current at each I/O pin
16
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
16
µA
IIN with pulldown
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
50
120
210
µA
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
60
120
200
µA
enabled
CPAD
Pad capacitance (including package capacitance)
4
pF
ZO
Output impedance (drive strength)
enabled
IIN with pullup
0.65*VDDS
V
0.35*VDDS
100
V
mV
VDDS-0.45
V
0.45
6
V
mA
40
Ω
3.3-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
VOH
Output high-level threshold (IOH = 100 µA)
VOL
Output low-level threshold (IOL = 100 µA)
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
IIN
Input current at each I/O pin
65
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD))
is measured and is reported as IOZ
65
µA
IIN with pulldown
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
40
100
200
µA
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
10
100
290
µA
enabled
CPAD
Pad capacitance (including package capacitance)
4
pF
ZO
Output impedance (drive strength)
enabled
IIN with pullup
2
V
0.8
200
V
mV
VDDS-0.2
V
0.2
6
V
mA
40
Ω
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see Table 4-2, POWER [10] column.
5.7.13 SATAPHY DC Electrical Characteristics
NOTE
The SATA module is compliant with the electrical parameters specified in the SATA-IO SATA
Specification, Revision 3.2, August 7, 2013.
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5.7.14 PCIEPHY DC Electrical Characteristics
NOTE
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 3.0.
5.8
Thermal Characteristics
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Table 5-4, Recommended Operating Conditions.
A BCI compact thermal model for this Device is available and recommended for use when modeling
thermal performance in a system.
Therefore, it is recommended to perform thermal simulations at the system level with the worst case
device power consumption.
5.8.1
Package Thermal Characteristics
Table 5-20 provides the thermal resistance characteristics for the package used on this device.
NOTE
Power dissipation of 1.5 W and an ambient temperature of 85ºC is assumed for ABC
package.
Table 5-20. Thermal Resistance Characteristics
PARAMETER
DESCRIPTION
°C/W(1)
AIR FLOW (m/s)(2)
T1
RΘJC
Junction-to-case
0.41
N/A
T2
RΘJB
Junction-to-board
4.74
N/A
Junction-to-free air
11.9
0
8.9
1
8.0
2
T6
7.4
3
T7
0.22
0
T8
0.22
1
0.22
2
T10
0.23
3
T11
4.12
0
T12
3.73
1
3.59
2
3.48
3
NO.
T3
T4
T5
T9
T13
RΘJA
ΨJT
ΨJB
Junction-to-moving air
Junction-to-package top
Junction-to-board
T14
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement,
which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more
information, see these EIA/JEDEC standards:
– JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
– JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
– JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
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5.9
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation. The power supply names described in this section comprise a superset of a family of
compatible devices. Some members of this family will not include a subset of these power supplies and
their associated device modules. Refer to the Section 4.2, Ball Characteristics of the Section 4, Terminal
Configuration and Functions to determine which power supplies are applicable.
Figure 5-1 and Figure 5-2 describe the device Power Sequencing when RTC-mode is used.
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Note 4
vdda_rtc
Note 5
(3)
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_dsp_iva, vdda_video,
vdda_mpu_abe, vdda_osc, vdda_csi
vdd_rtc
(3)
vdds_ddr1, ddr1_vref0
VD_CORE BOOT voltage
vdd
VD_MPU BOOT voltage
vdd_mpu
VD_IVA BOOT voltage
vdd_iva
VD_GPU BOOT voltage
vdd_gpu
VD_DSPEVE BOOT voltage
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie1, vdda_sata,
vdda_usb3
vddshv5
(3)
Note 6
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
Note 9
rtc_porz
Note 11
resetn/porz
Note 12
sysboot[15:0]
Note 13
Valid Config
Note 14
rstoutn
SPRS906_ELCH_01
Figure 5-1. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
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(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) If RTC-mode is used then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be
combined with other rails.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5
Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9, vddshv10,
vddshv11
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3
vddshv5
(4)
vdd_dsp
vdd_gpu
vdd_iva
vdd_mpu
vdd
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva,
vdda_core_gmac, vdda_gpu, vdda_video,
vdda_mpu_abe, vdda_osc, vdda_csi
vdd_rtc
(4)
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_rtc
(4)
xi_osc0
SPRS906_ELCH_02
Figure 5-2. Power-Down Sequencing
(1) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(2) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(3) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(4) If RTC-mode is supported then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot
be combined with other rails.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
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(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
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Figure 5-3 describes the RTC-mode Power Sequencing.
Note 5 Note 4
Note 4 Note 3
vdds18v, vdds_mlbp, vdds18v_ddr1
vdda_rtc
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac,
vdda_gpu, vdda_video, vdda_mpu,
vdda_osc, vdda_csi
vdd_rtc
vdds_ddr1, ddr1_vref0
vdd
R
T
C
vdd_mpu
M
O
D
E
vdd_iva
vdd_gpu
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3
vddshv5
vddshv1, vddshv2, vddshv3, vddshv4,
vddshv6, vddshv7, vddshv9, vddshv10,
vddshv11
Note 6
Note 8
vdda33v_usb1, vdda33v_usb2
Note 9
Note 7
vddshv8
rtc_porz
resetn/porz
SPRS906_ELCH_03
Figure 5-3. RTC Mode Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
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(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(4) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(5) vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
(8) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshvn rail is never higher
than 2.0 V above the vdds18v rail.
(9) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
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Figure 5-4 and Figure 5-5, describe the device Power Sequencing when RTC-mode is NOT used.
Note 4
Note 5
vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(3)
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac, vdda_gpu,
vdda_video, vdda_mpu, vdda_osc, vdda_csi
vdds_ddr1, ddr1_vref0
VD_CORE BOOT voltage
vdd, vdd_rtc
(3)
VD_MPU BOOT voltage
vdd_mpu
VD_IVA BOOT voltage
vdd_iva
VD_GPU BOOT voltage
vdd_gpu
VD_DSP BOOT voltage
vdd_dsp
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3
vddshv1, vddshv2, vddshv3, vddshv4,
(3)
vddshv5 , vddshv6, vddshv7, vddshv9,
vddshv10, vddshv11
Note 6
vdda33v_usb1, vdda33v_usb2
Note 7
vddshv8
xi_osc0
Note 9
rtc_porz
Note 11
resetn/porz
Note 12
sysboot[15:0]
Note 13
Valid Config
Note 14
rstoutn
SPRS906_ELCH_04
Figure 5-4. Power-Up Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) If RTC-mode is not supported then the following combinations are approved:
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- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails.
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn
rails but vddshv8 must ramp after vdd.
(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.
(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.
(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.
(11) Pulse duration: resetn/porz must remain low a minimum of 12P(15) after xi_osc0 is stable and at a valid frequency.
(12) Setup time: sysboot[15:0] pins must be valid 2P(15) before porz is de-asserted high.
(13) Hold time: sysboot[15:0] pins must be valid 15P(15) after porz is de-asserted high.
(14) resetn to rstoutn delay is 2ms.
(15) P = 1/(SYS_CLK1/610) frequency in ns.
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Note 5
Note 6
porz
Note 8
vddshv8
vdda33v_usb1, vdda33v_usb2
Note 7
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_pcie, vdda_pcie0, vdda_sata,
vdda_usb3
vdd_dsp
vdd_gpu
vdd_iva
vdd_mpu
vdd, vdd_rtc
(4)
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
vdda_dsp_iva, vdda_core_gmac,
vdda_gpu, vdda_video, vdda_mpu,
vdda_osc, vdda_csi
vdds18v, vdds_mlbp, vdds18v_ddr1,
(4)
vdda_rtc
xi_osc0
SPRS906_ELCH_05
Figure 5-5. Power-Down Sequencing
(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.
(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
(4) If RTC-mode is not used then the following combinations are approved:
- vdda_rtc can be combined with vdds18v
- vdd_rtc can be combined with vdd
- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails
If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.
(6) vdd must ramp after or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.
(7) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If
vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is
never higher than 2.0 V above the vdds18v rail.
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(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp
down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other
vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
Figure 5-6 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.
Figure 5-6. vddshv* Supplies Falling After vdds18v Supplies Delta
(1) Vdelta MAX = 2V
(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.
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6 Clock Specifications
NOTE
For more information, see Power Reset and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
• The 32 kHz frequency is used for low frequency operation. It supplies the wake-up domain for
operation in lowest power mode. This is an optional clock and will be supplied by on chip divider + mux
(FUNC_32K_CLK) incase it is not available on external pin.
• The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources
of the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the
wake-up (WKUP) domain is supplied.
Figure 6-1 shows the external input clock sources and the output clocks to peripherals.
174
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DEVICE
From quartz (32 kHz) or from CMOS square clock source (32 kHz).
rtc_osc_xi_clkin32
To quartz (from oscillator output).
rtc_osc_xo
rstoutn
Warm reset output.
resetn
Device reset input.
porz
Power ON Reset.
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xi_osc0
xo_osc0
To quartz (from oscillator output).
xi_osc1
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xo_osc1
To quartz (from oscillator output).
clkout1
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
clkout2
clkout3
xref_clk0
xref_clk1
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk2
xref_clk3
Boot Mode Configuration
sysboot[15:0]
Figure 6-1. Clock Interface
6.1
Input Clock Specifications
6.1.1
Input Clock Requirements
•
•
•
The source of the internal system clock (SYS_CLK1) could be either:
– A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc0 and xo_osc0.
The source of the internal system clock (SYS_CLK2) could be either:
– A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc1 and xo_osc1.
The source of the internal system clock (SYS_32K) could be either:
– A CMOS clock that enters on the rtc_osc_xi_clkin32 ball and supports external LVCMOS clock
generators
– A crystal oscillator clock managed by rtc_osc_xi_clkin32 and rtc_osc_xo.
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System Oscillator OSC0 Input Clock
SYS_CLKIN1 is received directly from oscillator OSC0. For more information about SYS_CLKIN1 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.2.1
OSC0 External Crystal
An external crystal is connected to the device pins. Figure 6-2 describes the crystal implementation.
Device
xo_osc0
xi_osc0
vssa_osc0
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_03
Figure 6-2. OSC0 Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-2, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-3. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-1 summarizes
the required electrical constraints.
and Table 6-5
Table 6-1. OSC0 Crystal Electrical Characteristics
NAME
fp
MIN
TYP
MAX
19.2, 20, 27
UNIT
MHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
100
Ω
ESR(Cf1,Cf2)
(1)
176
DESCRIPTION
Parallel resonance crystal frequency
Crystal ESR
Clock Specifications
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Table 6-1. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
ESR = 30 Ω
ESR = 40 Ω
ESR = 50 Ω
CO
ESR = 60 Ω
Crystal shunt capacitance
ESR = 80 Ω
ESR = 100 Ω
LM
Crystal motional inductance for fp = 20 MHz
CM
Crystal motional capacitance
MIN
TYP
MAX
19.2 MHz, 20 MHz, 27 MHz
7
pF
19.2 MHz, 20 MHz
7
pF
27 MHz
5
pF
7
pF
5
pF
19.2 MHz, 20 MHz
27 MHz
Not Supported
19.2 MHz, 20 MHz
27 MHz
-
Not Supported
19.2 MHz, 20 MHz
3
27 MHz
pF
Not Supported
-
10.16
mH
3.42
fF
Ethernet and MLB not used
tj(xiosc0)
UNIT
(1)
Frequency accuracy , xi_osc0
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
ppm
MLB using derived clock
±50
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-2 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-2. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
6.1.2.2
MIN
TYP
MAX
19.2, 20, 27 MHz
UNIT
MHz
4
ms
OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN1 clock input to the system. The external connections to support this are shown in Figure 6-4.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Device
xi_osc0
xo_osc0
vssa_osc0
NC
SPRS906_CLK_04
Figure 6-4. 1.8-V LVCMOS-Compatible Clock Input
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Table 6-3 summarizes the OSC0 input clock electrical characteristics.
Table 6-3. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
f
MIN
Frequency
TYP
MAX
UNIT
19.2, 20, 27
CIN
Input capacitance
IIN
Input current (3.3V mode)
MHz
2.184
2.384
2.584
pF
4
6
10
µA
Table 6-4 details the OSC0 input clock timing requirements.
Table 6-4. OSC0 Input Clock Timing Requirements
NAME
DESCRIPTION
1/
CK0
tc(xiosc0)
CK1
MIN
Frequency, xi_osc0
TYP
19.2, 20, 27
tw(xiosc0)
Pulse duration, xi_osc0 low or high
tj(xiosc0)
Period jitter(1), xi_osc0
tR(xiosc0)
Rise time, xi_osc0
tF(xiosc0)
Fall time, xi_osc0
0.45
*
tc(xiosc0)
Ethernet and MLB not used
tj(xiosc0)
MAX
(2)
Frequency accuracy , xi_osc0
UNIT
MHz
0.55 *
tc(xiosc0)
ns
0.01 ×
tc(xiosc0)
ns
5
ns
5
ns
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
ppm
MLB using derived clock
±50
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
SPRS906_CLK_05
Figure 6-5. xi_osc0 Input Clock
6.1.3
Auxiliary Oscillator OSC1 Input Clock
SYS_CLKIN2 is received directly from oscillator OSC1. For more information about SYS_CLKIN2 see
Device TRM, Chapter: Power, Reset, and Clock Management.
6.1.3.1
OSC1 External Crystal
An external crystal is connected to the device pins. Figure 6-6 describes the crystal implementation.
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Device
xo_osc1
xi_osc1
vssa_osc1
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_06
Figure 6-6. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-6, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-7. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-5 summarizes
the required electrical constraints.
Table 6-5. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
MIN
Parallel resonance crystal frequency
TYP
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
ESR(Cf1,Cf2) Crystal ESR
MHz
24
pF
24
pF
100
Ω
19.2 MHz ≤ fp ≤ 32 MHz
7
pF
ESR = 40 Ω
19.2 MHz ≤ fp ≤ 32 MHz
5
pF
19.2 MHz ≤ fp ≤ 25 MHz
7
pF
25 MHz < fp ≤ 27 MHz
5
pF
27 MHz < fp ≤ 32 MHz
Crystal shunt capacitance
UNIT
ESR = 30 Ω
ESR = 50 Ω
CO
MAX
Range from 19.2 to 32
ESR = 60 Ω
7
pF
23 MHz < fp ≤ 25 MHz
5
pF
LM
Crystal motional inductance for fp = 20 MHz
CM
Crystal motional capacitance
Not Supported
-
19.2 MHz ≤ fp ≤ 23 MHz
5
pF
23 MHz ≤ fp ≤ 25 MHz
3
pF
25 MHz < fp ≤ 32 MHz
ESR = 100 Ω
-
19.2 MHz ≤ fp ≤ 23 MHz
25 MHz < fp ≤ 32 MHz
ESR = 80 Ω
Not Supported
Not Supported
19.2 MHz ≤ fp ≤ 20 MHz
20 MHz < fp ≤ 32 MHz
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Not Supported
pF
-
10.16
mH
3.42
fF
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Table 6-5. OSC1 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
Ethernet and MLB not used
tj(xiosc1)
(1)
Frequency accuracy , xi_osc1
MAX
UNIT
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
ppm
MLB using derived clock
±50
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-6 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-6. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
fp
Oscillation frequency
tsX
Start-up time
6.1.3.2
MIN
TYP
MAX
Range from 19.2 to 32
UNIT
MHz
4
ms
OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN2 clock input to the system. The external connections to support this are shown in, Figure 6-8.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (vss).
Device
xi_osc1
xo_osc1
vssa_osc1
NC
SPRS906_CLK_07
Figure 6-8. 1.8-V LVCMOS-Compatible Clock Input
Table 6-7 summarizes the OSC1 input clock electrical characteristics.
Table 6-7. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
180
DESCRIPTION
Frequency
TYP
MAX
Range from 12 to 38.4
CIN
Input capacitance
IIN
Input current (3.3V mode)
tsX
Start-up time(1)
Clock Specifications
MIN
UNIT
MHz
2.819
3.019
3.219
pF
4
6
10
µA
See(2)
ms
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(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 6-6, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 6-8 details the OSC1 input clock timing requirements.
Table 6-8. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
CK0
1/
tc(xiosc1)
Frequency, xi_osc1
CK1
tw(xiosc1)
Pulse duration, xi_osc1 low or high
tj(xiosc1)
Period jitter(1), xi_osc1
tR(xiosc1)
Rise time, xi_osc1
tF(xiosc1)
Fall time, xi_osc1
TYP
Range from 12 to 38.4
0.45 *
tc(xiosc1)
UNIT
MHz
0.55 *
tc(xiosc1)
ns
0.01 ×
tc(xiosc1)
ns
5
ns
5
ns
(3)
Ethernet and MLB not used
tj(xiosc1)
MAX
(2)
Frequency accuracy , xi_osc1
±200
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
ppm
MLB using derived clock
±50
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
CK0
CK1
CK1
xi_osc1
SPRS906_CLK_08
Figure 6-9. xi_osc1 Input Clock
6.1.4
RTC Oscillator Input Clock
SYS_32K is received directly from RTC Oscillator. For more information about SYS_32K see the Device
TRM, Power, Reset, and Clock Management chapter.
6.1.4.1
RTC Oscillator External Crystal
An external crystal is connected to the device pins. Figure 6-10 describes the crystal implementation.
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Device
rtc_osc_xo
rtc_osc_xi_clkin32
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_01
Figure 6-10. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 6-10, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator rtc_osc_xi_clkin32 and rtc_osc_xo pins.
CL=
Cf1Cf2
(Cf1+Cf2)
Figure 6-11. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-9 summarizes
the required electrical constraints.
Table 6-9. RTC Crystal Electrical Characteristics
NAME
DESCRIPTION
fp
MIN
TYP
Parallel resonance crystal frequency
MAX
32.768
UNIT
kHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
24
pF
80
kΩ
5
pF
ESR(Cf1,Cf2)
Crystal ESR
CO
Crystal shunt capacitance
LM
Crystal motional inductance for fp = 32,768 kHz
CM
Crystal motional capacitance
tj(rtc_osc_xi_clkin32)
10.7
mH
2.2
Frequency accuracy, rtc_osc_xi_clkin32
pF
fF
±200
ppm
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-10 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-10. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
182
DESCRIPTION
Oscillation frequency
Clock Specifications
MIN
TYP
32.768
MAX
UNIT
kHz
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Table 6-10. Oscillator Switching Characteristics—Crystal Mode (continued)
NAME
tsX
6.1.4.2
DESCRIPTION
MIN
TYP
MAX
Start-up time
UNIT
4
ms
RTC Oscillator Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_32K clock input to the system. The external connections to support this are shown in Figure 6-12.
The rtc_osc_xi_clkin32 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The rtc_osc_xo
pin is left unconnected.
Device
rtc_osc_xi_clkin32
rtc_osc_xo
NC
SPRS906_CLK_10
Figure 6-12. LVCMOS-Compatible Clock Input
Table 6-11 summarizes the RTC Oscillator input clock electrical characteristics.
Table 6-11. RTC Oscillator Input Clock Electrical Characteristics—Bypass Mode
NAME
CK0
CK1
DESCRIPTION
1/tc(rtc_osc_xi_clkin32)
tw(rtc_osc_xi_clkin32)
MIN
Frequency, rtc_osc_xi_clkin32
Pulse duration, rtc_osc_xi_clkin32 low or
high
CIN
Input capacitance
IIN
Input current (3.3V mode)
tsX
Start-up time
TYP
MAX
32.768
UNIT
kHz
0.45 *
0.55 *
tc(rtc_osc_xi_clkin32)
tc(rtc_osc_xi_clkin32)
ns
2.178
2.378
2.578
pF
4
6
10
µA
See (1)
ms
(1) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is
inapplication mode and receives a wave. The switching time in this case is about 100 μs.
CK0
CK1
CK1
rtc_osc_xi_clkin32
SPRS906_CLK_11
Figure 6-13. rtc_osc_xi_clkin32 Input Clock
6.2
DPLLs, DLLs Specifications
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NOTE
For more information, see:
• Power, Reset, and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
• Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
• They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
• DPLL_MPU: It supplies the MPU subsystem clocking internally.
• DPLL_IVA: It feeds the IVA subsystem clocking.
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
• DPLL_ABE: It provides clocks to various modules within the device.
• DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
• DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
• DPLL_DSP: It feeds the DSP Subsystem clocking.
• DPLL_GPU: It supplies clock for the GPU Subsystem.
• DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
• DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
• APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
• DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
•
•
•
•
•
DPLL_VIDEO1; (It is controlled from DSS)
DPLL_HDMI; (It is controlled from DSS)
DPLL_SATA; (It is controlled from SATA)
DPLL_DEBUG; (It is controlled from DEBUGSS)
DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
184
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6.2.1
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DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 6-12 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications introduction.
Table 6-12. DPLL Control Type
DPLL NAME
TYPE
CONTROLLED BY PRCM
DPLL_ABE
Table 6-13 (Type A)
Yes(1)
DPLL_CORE
Table 6-13 (Type A)
Yes(1)
DPLL_DEBUGSS
Table 6-13 (Type A)
No(2)
DPLL_DSP
Table 6-13 (Type A)
Yes(1)
DPLL_GMAC
Table 6-13 (Type A)
Yes(1)
DPLL_HDMI
Table 6-14 (Type B)
No(2)
DPLL_IVA
Table 6-13 (Type A)
Yes(1)
DPLL_MPU
Table 6-13 (Type A)
Yes(1)
DPLL_PER
Table 6-13 (Type A)
Yes(1)
APLL_PCIE
Table 6-13 (Type A)
Yes(1)
DPLL_PCIE_REF
Table 6-14 (Type B)
Yes(1)
DPLL_SATA
Table 6-14 (Type B)
No(2)
DPLL_USB
Table 6-14 (Type B)
Yes(1)
DPLL_USB_OTG_SS
Table 6-14 (Type B)
No(2)
DPLL_VIDEO1
Table 6-13 (Type A)
No(2)
DPLL_DDR
Table 6-13 (Type A)
Yes(1)
DPLL_GPU
Table 6-13 (Type A)
Yes(1)
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
Table 6-13. DPLL Type A Characteristics
NAME
finput
DESCRIPTION
CLKINP input frequency
MIN
0.032
TYP
MAX
UNIT
52
MHz
FINP
COMMENTS
finternal
Internal reference frequency
0.15
52
MHz
REFCLK
fCLKINPHIF
CLKINPHIF input frequency
10
1400
MHz
FINPHIF
0.001
600
MHz
Bypass mode: fCLKOUT =
fCLKINPULOW / (M1 + 1) if
ulowclken = 1(6)
20(1)
1400(2)
MHz
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
fCLKINPULOW
fCLKOUT
CLKINPULOW input frequency
CLKOUT output frequency
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Table 6-13. DPLL Type A Characteristics (continued)
NAME
fCLKOUTx2
DESCRIPTION
MIN
CLKOUTx2 output frequency
TYP
MAX
UNIT
COMMENTS
40(1)
2200(2)
MHz
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
20
(4)
1400
MHz
FINPHIF / M3 if clkinphifsel = 1
40(3)
2200(4)
MHz
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
40
2800
MHz
2 × [M / (N + 1)] × FINP (in
locked condition)
(3)
fCLKOUTHIF
CLKOUTHIF output frequency
fCLKDCOLDO
DCOCLKLDO output
frequency
tlock
Frequency lock time
6 + 350 ×
REFCLK
µs
plock
Phase lock time
6 + 500 ×
REFCLK
µs
6 + 70 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
6 + 120 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
3.55 + 70 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
3.55 + 120 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
trelock-L
Relock time—Frequency
lock(5) (LP relock time from
bypass)
prelock-L
Relock time—Phase lock(5)
(LP relock time from bypass)
trelock-F
Relock time—Frequency
lock(5) (fast relock time from
bypass)
prelock-F
Relock time—Phase lock(5)
(fast relock time from bypass)
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
Table 6-14. DPLL Type B Characteristics
NAME
MAX
UNIT
CLKINP input clock frequency
0.62
60
MHz
FINP
finternal
REFCLK internal reference
clock frequency
0.62
2.5
MHz
[1 / (N + 1)] × FINP
fCLKINPULOW
CLKINPULOW bypass input
clock frequency
0.001
600
MHz
Bypass mode: fCLKOUT =
fCLKINPULOW / (M1 + 1) If
ulowclken = 1(4)
fCLKLDOOUT
CLKOUTLDO output clock
frequency
20(1)(5)
2500(2)(5)
MHz
M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
CLKOUT output clock
frequency
20(1)(5)
1450(2)(5)
MHz
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
750(5)
finput
fCLKOUT
fCLKDCOLDO
DESCRIPTION
MIN
Internal oscillator (DCO) output
clock frequency
TYP
1500(5)
MHz
(5)
2500(5)
MHz
–2.5%
2.5%
1250
COMMENTS
[M / (N + 1)] × FINP (in locked
condition)
CLKOUTLDO period jitter
tJ
CLKOUT period jitter
The period jitter at the output
clocks is ± 2.5% peak to peak
CLKDCOLDO period jitter
tlock
Frequency lock time
350 ×
REFCLKs
µs
plock
Phase lock time
500 ×
REFCLKs
µs
9 + 30 ×
REFCLKs
µs
(3)
trelock-L
186
Relock time—Frequency lock
(LP relock time from bypass)
Clock Specifications
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Table 6-14. DPLL Type B Characteristics (continued)
NAME
DESCRIPTION
prelock-L
Relock time—Phase lock(3) (LP
relock time from bypass)
MIN
TYP
MAX
UNIT
9 + 125 ×
REFCLKs
COMMENTS
µs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
6.2.2
DLL Characteristics
Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
Table 6-15. DLL Characteristics
NAME
MAX
UNIT
finput
Input clock frequency (EMIF_DLL_FCLK)
266
MHz
tlock
Lock time
50k
cycles
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
cycles
trelock
6.2.3
DESCRIPTION
MIN
TYP
DPLL and DLL Noise Isolation
NOTE
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
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7 Timing Requirements and Switching Characteristics
7.1
Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
7.2
7.2.1
Interface Clock Specifications
Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
7.2.2
Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
7.3
Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
Table 7-1. Timing Parameters
SUBSCRIPTS
188
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
F
Fall time
H
High
L
Low
R
Rise time
V
Valid
IV
Invalid
Timing Requirements and Switching Characteristics
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Table 7-1. Timing Parameters (continued)
SUBSCRIPTS
7.3.1
SYMBOL
PARAMETER
AE
Active Edge
FE
First Edge
LE
Last Edge
Z
High impedance
Parameter Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see Note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
7.3.1.1
1.8V and 3.3V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Timing Requirements and Switching Characteristics
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Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.3.1.2
1.8V and 3.3V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
7.3.1.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report (literature number SPRA839). If needed, external logic hardware such as buffers may be
used to compensate any timing differences.
7.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
7.5
Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
Table 7-2. Modes Summary
Virtual or Manual IO Mode Name
Data Manual Timing Mode
DPI Video Output
No Virtual or Manual IO Timing Mode Required
DPI1/3 Video Output Default Timings - Rising-edge Clock Reference
DSS_VIRTUAL1
DPI1/3 Video Output Default Timings - Falling-edge Clock Reference
VOUT1_MANUAL1
DPI1 Video Output Alternate Timings
VOUT2_IOSET1_MANUAL1
DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL2
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET1_MANUAL3
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
VOUT2_IOSET2_MANUAL1
DPI2 Video Output IOSET2 Alternate Timings
VOUT2_IOSET2_MANUAL2
DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET2_MANUAL3
DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference
VOUT3_MANUAL1
DPI3 Video Output Alternate Timings
GPMC
No Virtual or Manual IO Timing Mode Required
190
GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
Timing Requirements and Switching Characteristics
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Table 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
GPMC_VIRTUAL1
GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required
McASP1 Asynchronous and Synchronous Transmit Timings
MCASP1_VIRTUAL1_SYNC_RX
See Table 7-52
MCASP1_VIRTUAL2_ASYNC_RX
See Table 7-52
No Virtual or Manual IO Timing Mode Required
McASP2 Asynchronous and Synchronous Transmit Timings
MCASP2_VIRTUAL1_SYNC_RX_80M
See Table 7-53
MCASP2_VIRTUAL2_ASYNC_RX
See Table 7-53
MCASP2_VIRTUAL3_SYNC_RX
See Table 7-53
MCASP2_VIRTUAL4_ASYNC_RX_80M
See Table 7-53
No Virtual or Manual IO Timing Mode Required
McASP3 Synchronous Transmit Timings
MCASP3_VIRTUAL2_SYNC_RX
See Table 7-54
No Virtual or Manual IO Timing Mode Required
McASP4 Synchronous Transmit Timings
MCASP4_VIRTUAL1_SYNC_RX
See Table 7-55
No Virtual or Manual IO Timing Mode Required
McASP5 Synchronous Transmit Timings
MCASP5_VIRTUAL1_SYNC_RX
See Table 7-56
No Virtual or Manual IO Timing Mode Required
McASP6 Synchronous Transmit Timings
MCASP6_VIRTUAL1_SYNC_RX
See Table 7-57
No Virtual or Manual IO Timing Mode Required
McASP7 Synchronous Transmit Timings
MCASP7_VIRTUAL2_SYNC_RX
See Table 7-58
No Virtual or Manual IO Timing Mode Required
McASP8 Synchronous Transmit Timings
MCASP8_VIRTUAL1_SYNC_RX
See Table 7-59
eMMC/SD/SDIO
No Virtual or Manual IO Timing Mode Required
MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12
(Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and
Pad Loopback) Timings
MMC1_VIRTUAL1
MMC1 SDR50 (Pad Loopback) Timings
MMC1_VIRTUAL4
MMC1 DS (Internal Loopback) Timings
MMC1_VIRTUAL5
MMC1 SDR50 (Internal Loopback) Timings
MMC1_VIRTUAL6
MMC1 DDR50 (Internal Loopback) Timings
MMC1_MANUAL1
MMC1 DDR50 (Pad Loopback) Timings
MMC1_MANUAL2
MMC1 SDR104 Timings
No Virtual or Manual IO Timing Mode Required
MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
MMC2_VIRTUAL2
MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC2_MANUAL1
MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL2
MMC2 DDR (Internal Loopback Manual) Timings
MMC2_MANUAL3
MMC2 HS200 Timings
No Virtual or Manual IO Timing Mode Required
MMC3 DS, SDR12, HS, SDR25 Timings
MMC3_MANUAL1
MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required
MMC4 DS, SDR12, HS, SDR25 Timings
QSPI
No Virtual or Manual IO Timing Mode Required
QSPI Mode 3 Timings
QSPI1_MANUAL1
QSPI Mode 0 Timings
GMAC
No Virtual or Manual IO Timing Mode Required
GMAC MII0/1 Timings
GMAC_RGMII0_MANUAL1
GMAC RGMII0 with Transmit Clock Internal Delay Enabled
GMAC_RGMII1_MANUAL1
GMAC RGMII1 with Transmit Clock Internal Delay Enabled
GMAC_RMII0_MANUAL1
GMAC RMII0 Timings
Timing Requirements and Switching Characteristics
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Table 7-2. Modes Summary (continued)
Virtual or Manual IO Mode Name
Data Manual Timing Mode
GMAC_RMII1_MANUAL1
GMAC RMII1 Timings
VIP
VIP_MANUAL1
VIN2A (IOSET10) Rise-Edge Capture Mode Timings
VIP_MANUAL2
VIN2A (IOSET10) Fall-Edge Capture Mode Timings
VIP_MANUAL3
VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIP_MANUAL4
VIN2B (IOSET1/2/7) Rise-Edge Capture Mode Timings
VIP_MANUAL5
VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIP_MANUAL6
VIN2B (IOSET1/2/7) Fall-Edge Capture Mode Timings
VIP_MANUAL7
VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) Rise-Edge Capture
Mode Timings
VIP_MANUAL8
VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL9
VIN1B (IOSET6) Rise-Edge Capture Mode Timings
VIP_MANUAL10
VIN1B (IOSET5) and VIN2B (IOSET9) Rise-Edge Capture Mode Timings
VIP_MANUAL11
VIN1B (IOSET5) and VIN2B (IOSET9) Fall-Edge Capture Mode Timings
VIP_MANUAL12
VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) Fall-Edge Capture Mode
Timings
VIP_MANUAL13
VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL14
VIN1B (IOSET6) Fall-Edge Capture Mode Timings
VIP_MANUAL15
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIP_MANUAL16
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA,
INTC, MLB
No Virtual or Manual IO Timing Mode Required
7.6
All Modes
Video Input Ports (VIP)
The Device includes 1 Video Input Ports (VIP).
Table 7-3, Figure 7-4 and Figure 7-5 present timings and switching characteristics of the VIPs.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in Table 7-4.
Table 7-3. Timing Requirements for VIP (3)(4)(5)
NO.
PARAMETER
DESCRIPTION
V1
tc(CLK)
Cycle time, vinx_clki (3) (5)
MIN
V2
tw(CLKH)
Pulse duration, vinx_clki high (3) (5)
6.06
(3) (5)
MAX
(2)
UNIT
ns
0.45*P
(2)
ns
0.45*P
(2)
ns
V3
tw(CLKL)
Pulse duration, vinx_clki low
V4
tsu(CTL/DATA-CLK)
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5)
3.11
(2)
ns
V6
th(CLK-CTL/DATA)
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5)
-0.05 (2)
ns
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
192
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V3
V2
V1
vinx_clki
SPRS906_TIMING_VIP_01
Figure 7-4. Video Input Ports clock signal
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
Figure 7-5. Video Input Ports timings
Timing Requirements and Switching Characteristics
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In Table 7-4 and Table 7-5 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.
Table 7-4. VIN1 IOSETs
SIGNALS
IOSET2
BALL
IOSET4 (1)
IOSET3
MUX
BALL
MUX
BALL
MUX
IOSET5 (1)
BALL
MUX
IOSET6 (1)
BALL
IOSET7 (1)
IOSET8
IOSET9
IOSET10
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin1a
vin1a_clk0
P1
2
B11
4
B11
3
P4
4
P4
4
B26
8
AC5
9
E17
7
E17
7
vin1a_hsync0
N7
2
C11
4
C11
3
R3
4
P7
4
E21
8
AB8
9
F12
7
F12
7
vin1a_vsync0
R4
2
E11
4
E11
3
T2
4
N1
4
F20
8
AB5
9
G12
7
G12
7
vin1a_fld0
P9
2
D11
4
D11
3
P9
4
J7
4
F21
8
C17
9
C14
7
C14
7
vin1a_de0
N9
2
B10
4
B10
3
P7
5
H6
4
C23
8
AB4
9
D14
7
D14
7
vin1a_d0
M6
2
B7
4
B7
3
R6
4
R6
4
B14
8
AD6
9
D18
7
C17
7
vin1a_d1
M2
2
B8
4
B8
3
T9
4
T9
4
J14
8
AC8
9
B19
7
B19
7
vin1a_d2
L5
2
A7
4
A7
3
T6
4
T6
4
G13
8
AC3
9
F15
7
F15
7
vin1a_d3
M1
2
A8
4
A8
3
T7
4
T7
4
J11
8
AC9
9
B18
7
B18
7
vin1a_d4
L6
2
C9
4
C9
3
P6
4
P6
4
E12
8
AC6
9
A16
7
A16
7
vin1a_d5
L4
2
A9
4
A9
3
R9
4
R9
4
F13
8
AC7
9
C15
7
C15
7
vin1a_d6
L3
2
B9
4
B9
3
R5
4
R5
4
C12
8
AC4
9
A18
7
A18
7
vin1a_d7
L2
2
A10
4
A10
3
P5
4
P5
4
D12
8
AD4
9
A19
7
A19
7
vin1a_d8
L1
2
E8
4
E8
3
U2
4
U2
4
E15
8
AA4
9
F14
7
F14
7
vin1a_d9
K2
2
D9
4
D9
3
U1
4
U1
4
A20
8
AB3
9
G14
7
G14
7
vin1a_d10
J1
2
D7
4
D7
3
P3
4
P3
4
B15
8
AB9
9
A13
7
A13
7
vin1a_d11
J2
2
D8
4
D8
3
R2
4
R2
4
A15
8
AA3
9
E14
7
E14
7
vin1a_d12
H1
2
A5
4
A5
3
K7
4
K7
4
D15
8
D17
9
A12
7
A12
7
vin1a_d13
J3
2
C6
4
C6
3
M7
4
M7
4
B16
8
G16
9
B13
7
B13
7
vin1a_d14
H2
2
C8
4
C8
3
J5
4
J5
4
B17
8
A21
9
A11
7
A11
7
vin1a_d15
H3
2
C7
4
C7
3
K6
4
K6
4
A17
8
C18
9
B12
7
B12
7
vin1a_d16
R6
2
F11
4
F11
3
C18
8
vin1a_d17
T9
2
G10
4
G10
3
A21
8
vin1a_d18
T6
2
F10
4
F10
3
G16
8
vin1a_d19
T7
2
G11
4
G11
3
D17
8
vin1a_d20
P6
2
E9
4
E9
3
AA3
8
vin1a_d21
R9
2
F9
4
F9
3
AB9
8
vin1a_d22
R5
2
F8
4
F8
3
AB3
8
vin1a_d23
P5
2
E7
4
E7
3
AA4
8
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Table 7-4. VIN1 IOSETs (continued)
SIGNALS
IOSET2
BALL
MUX
IOSET3
BALL
MUX
IOSET4 (1)
BALL
MUX
IOSET5 (1)
BALL
MUX
IOSET6 (1)
BALL
IOSET7 (1)
MUX
BALL
MUX
IOSET8
BALL
IOSET9
MUX
BALL
IOSET10
MUX
BALL
MUX
vin1b
vin1b_clk1
P7
6
M4
4
V1
5
N9
6
vin1b_hsync1
H5
6
H5
6
U7
5
N7
6
vin1b_vsync1
H6
6
H6
6
V6
5
R4
6
vin1b_fld1
M4
6
W2
5
P4
6
vin1b_de1
N6
6
N6
6
V7
5
P9
6
vin1b_d0
K7
6
K7
6
U4
5
R6
6
vin1b_d1
M7
6
M7
6
V2
5
T9
6
vin1b_d2
J5
6
J5
6
Y1
5
T6
6
vin1b_d3
K6
6
K6
6
W9
5
T7
6
vin1b_d4
J7
6
J7
6
V9
5
P6
6
vin1b_d5
J4
6
J4
6
U5
5
R9
6
vin1b_d6
J6
6
J6
6
V5
5
R5
6
vin1b_d7
H4
6
H4
6
V4
5
P5
6
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad
Configuration Registers.
Table 7-5. VIN2 IOSETs
SIGNALS
IOSET1
BALL
MUX
IOSET2
BALL
MUX
IOSET4
BALL
IOSET5
MUX
BALL
IOSET7 (1)
IOSET6
MUX
BALL
IOSET8 (1)
IOSET9 (1)
IOSET10 (1)
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
P4
4
B26
8
vin2a
vin2a_clk0
E1
0
E1
0
V1
4
B11
3
P4
4
vin2a_hsync0
G1
0
G1
0
U7
4
C11
3
R3
4
P7
4
E21
8
vin2a_vsync0
G6
0
G6
0
V6
4
E11
3
T2
4
N1
4
F20
8
vin2a_fld0
H7
0
G2
1
W2
4
D11
3
P9
4
J7
4
F21
8
vin2a_de0
G2
0
V7
4
B10
3
P7
5
H6
4
C23
8
vin2a_d0
F2
0
F2
0
U4
4
B7
3
R6
4
R6
4
B14
8
vin2a_d1
F3
0
F3
0
V2
4
B8
3
T9
4
T9
4
J14
8
vin2a_d2
D1
0
D1
0
Y1
4
A7
3
T6
4
T6
4
G13
8
vin2a_d3
E2
0
E2
0
W9
4
A8
3
T7
4
T7
4
J11
8
vin2a_d4
D2
0
D2
0
V9
4
C9
3
P6
4
P6
4
E12
8
vin2a_d5
F4
0
F4
0
U5
4
A9
3
R9
4
R9
4
F13
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Table 7-5. VIN2 IOSETs (continued)
SIGNALS
IOSET1
BALL
IOSET2
MUX
BALL
IOSET4
MUX
IOSET5
IOSET7 (1)
IOSET6
IOSET8 (1)
IOSET9 (1)
IOSET10 (1)
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin2a_d6
C1
0
C1
0
V5
4
B9
3
R5
4
R5
4
C12
8
vin2a_d7
E4
0
E4
0
V4
4
A10
3
P5
4
P5
4
D12
8
vin2a_d8
F5
0
F5
0
V3
4
E8
3
U2
4
U2
4
E15
8
vin2a_d9
E6
0
E6
0
Y2
4
D9
3
U1
4
U1
4
A20
8
vin2a_d10
D3
0
D3
0
U6
4
D7
3
P3
4
P3
4
B15
8
vin2a_d11
F6
0
F6
0
U3
4
D8
3
R2
4
R2
4
A15
8
vin2a_d12
D5
0
D5
0
A5
3
K7
4
K7
4
D15
8
vin2a_d13
C2
0
C2
0
C6
3
M7
4
M7
4
B16
8
vin2a_d14
C3
0
C3
0
C8
3
J5
4
J5
4
B17
8
vin2a_d15
C4
0
C4
0
C7
3
K6
4
K6
4
A17
8
vin2a_d16
B2
0
B2
0
F11
3
C18
8
vin2a_d17
D6
0
D6
0
G10
3
A21
8
vin2a_d18
C5
0
C5
0
F10
3
G16
8
vin2a_d19
A3
0
A3
0
G11
3
D17
8
vin2a_d20
B3
0
B3
0
E9
3
AA3
8
vin2a_d21
B4
0
B4
0
F9
3
AB9
8
vin2a_d22
B5
0
B5
0
F8
3
AB3
8
vin2a_d23
A4
0
A4
0
E7
3
AA4
8
vin2b
vin2b_clk1
P7
6
M4
4
H7
2
H7
2
AB5
4
vin2b_hsync1
H5
6
H5
6
G1
3
G1
3
AC5
4
vin2b_vsync1
H6
6
H6
6
G6
3
G6
3
AB4
4
G2
2
vin2b_fld1
M4
6
vin2b_de1
N6
6
N6
6
G2
3
AB8
4
vin2b_d0
K7
6
K7
6
A4
2
A4
2
AD6
4
vin2b_d1
M7
6
M7
6
B5
2
B5
2
AC8
4
vin2b_d2
J5
6
J5
6
B4
2
B4
2
AC3
4
vin2b_d3
K6
6
K6
6
B3
2
B3
2
AC9
4
vin2b_d4
J7
6
J7
6
A3
2
A3
2
AC6
4
vin2b_d5
J4
6
J4
6
C5
2
C5
2
AC7
4
vin2b_d6
J6
6
J6
6
D6
2
D6
2
AC4
4
vin2b_d7
H4
6
H4
6
B2
2
B2
2
AD4
4
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(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad
Configuration Registers.
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module chapter in the Device TRM.
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Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Manual Functions Mapping for VIP1 2A IOSET10 for a definition of the Manual modes.
Table 7-6 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-6. Manual Functions Mapping for VIP1 2A IOSET10
BALL
BALL NAME
VIP_MANUAL1
VIP_MANUAL2
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
E21
gpio6_14
1400
240
1767
0
CFG_GPIO6_14_IN
vin2a_hsync0
F20
gpio6_15
1170
240
1522
0
CFG_GPIO6_15_IN
vin2a_vsync0
8
F21
gpio6_16
1470
0
1600
0
CFG_GPIO6_16_IN
vin2a_fld0
B14
mcasp1_aclkr
2145
200
2509
0
CFG_MCASP1_ACLKR_IN
vin2a_d0
G13
mcasp1_axr2
2740
900
2680
1180
CFG_MCASP1_AXR2_IN
vin2a_d2
J11
mcasp1_axr3
2933
200
2700
600
CFG_MCASP1_AXR3_IN
vin2a_d3
E12
mcasp1_axr4
2901
240
2660
700
CFG_MCASP1_AXR4_IN
vin2a_d4
F13
mcasp1_axr5
2600
840
2640
920
CFG_MCASP1_AXR5_IN
vin2a_d5
C12
mcasp1_axr6
2718
240
3081
0
CFG_MCASP1_AXR6_IN
vin2a_d6
D12
mcasp1_axr7
2983
240
2540
800
CFG_MCASP1_AXR7_IN
vin2a_d7
J14
mcasp1_fsr
2203
240
2566
0
CFG_MCASP1_FSR_IN
vin2a_d1
E15
mcasp2_aclkr
2143
240
2492
0
CFG_MCASP2_ACLKR_IN
vin2a_d8
B15
mcasp2_axr0
2543
240
2905
0
CFG_MCASP2_AXR0_IN
vin2a_d10
A15
mcasp2_axr1
2664
240
2730
400
CFG_MCASP2_AXR1_IN
vin2a_d11
D15
mcasp2_axr4
2792
240
2750
400
CFG_MCASP2_AXR4_IN
vin2a_d12
B16
mcasp2_axr5
2621
300
2983
0
CFG_MCASP2_AXR5_IN
vin2a_d13
B17
mcasp2_axr6
1903
100
2086
0
CFG_MCASP2_AXR6_IN
vin2a_d14
A17
mcasp2_axr7
2928
200
2670
700
CFG_MCASP2_AXR7_IN
vin2a_d15
A20
mcasp2_fsr
2291
200
2654
0
CFG_MCASP2_FSR_IN
vin2a_d9
C18
mcasp4_aclkx
1433
0
1540
0
CFG_MCASP4_ACLKX_IN
vin2a_d16
G16
mcasp4_axr0
2500
0
2560
0
CFG_MCASP4_AXR0_IN
vin2a_d18
D17
mcasp4_axr1
2379
100
2599
0
CFG_MCASP4_AXR1_IN
vin2a_d19
A21
mcasp4_fsx
1500
1400
1900
1040
CFG_MCASP4_FSX_IN
vin2a_d17
AA3
mcasp5_aclkx
3740
1850
3900
1700
CFG_MCASP5_ACLKX_IN
vin2a_d20
AB3
mcasp5_axr0
3800
2760
3800
2800
CFG_MCASP5_AXR0_IN
vin2a_d22
AA4
mcasp5_axr1
4099
2500
3900
2870
CFG_MCASP5_AXR1_IN
vin2a_d23
AB9
mcasp5_fsx
3740
2100
3860
2060
CFG_MCASP5_FSX_IN
vin2a_d21
B26
xref_clk2
0
0
0
0
CFG_XREF_CLK2_IN
vin2a_clk0
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Table 7-6. Manual Functions Mapping for VIP1 2A IOSET10 (continued)
BALL
BALL NAME
C23
xref_clk3
VIP_MANUAL1
VIP_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
1440
0
1623
0
CFG REGISTER
MUXMODE
CFG_XREF_CLK3_IN
vin2a_de0
8
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-7 Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.
Table 7-7 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6)
BAL
L
BALL NAME
U3
VIP_MANUAL3
VIP_MANUAL5
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
RMII_MHZ_50
_CLK
2616
1379
2798
1294
U4
mdio_d
2558
1105
2790
954
CFG REGISTER
MUXMODE
0
1
2
3
4
CFG_RMII_MHZ_50_CLK_I
N
-
-
-
-
vin2a_d11
CFG_MDIO_D_IN
-
-
-
-
vin2a_d0
V1
mdio_mclk
998
463
1029
431
CFG_MDIO_MCLK_IN
-
-
-
-
vin2a_clk0
U5
rgmii0_rxc
2658
862
2896
651
CFG_RGMII0_RXC_IN
-
-
-
-
vin2a_d5
V5
rgmii0_rxctl
2658
1628
2844
1518
CFG_RGMII0_RXCTL_IN
-
-
-
-
vin2a_d6
W2
rgmii0_rxd0
2638
1123
2856
888
CFG_RGMII0_RXD0_IN
-
-
-
-
vin2a_fld0
Y2
rgmii0_rxd1
2641
1737
2804
1702
CFG_RGMII0_RXD1_IN
-
-
-
-
vin2a_d9
V3
rgmii0_rxd2
2641
1676
2801
1652
CFG_RGMII0_RXD2_IN
-
-
-
-
vin2a_d8
V4
rgmii0_rxd3
2644
1828
2807
1790
CFG_RGMII0_RXD3_IN
-
-
-
-
vin2a_d7
W9
rgmii0_txc
2638
1454
2835
1396
CFG_RGMII0_TXC_IN
-
-
-
-
vin2a_d3
V9
rgmii0_txctl
2672
1663
2831
1640
CFG_RGMII0_TXCTL_IN
-
-
-
-
vin2a_d4
U6
rgmii0_txd0
2604
1442
2764
1417
CFG_RGMII0_TXD0_IN
-
-
-
-
vin2a_d10
V6
rgmii0_txd1
2683
1598
2843
1600
CFG_RGMII0_TXD1_IN
-
-
-
-
vin2a_vsync
0
U7
rgmii0_txd2
2563
1483
2816
1344
CFG_RGMII0_TXD2_IN
-
-
-
-
vin2a_hsync
0
V7
rgmii0_txd3
2717
1461
2913
1310
CFG_RGMII0_TXD3_IN
-
-
-
-
vin2a_de0
V2
uart3_rxd
2445
1145
2743
923
CFG_UART3_RXD_IN
-
-
-
-
vin2a_d1
Y1
uart3_txd
2650
1197
2842
1080
CFG_UART3_TXD_IN
-
-
-
-
vin2a_d2
E1
vin2a_clk0
0
0
0
0
CFG_VIN2A_CLK0_IN
vin2a_clk0
-
-
-
-
F2
vin2a_d0
1812
102
1936
0
CFG_VIN2A_D0_IN
vin2a_d0
-
-
-
-
F3
vin2a_d1
1701
439
2229
10
CFG_VIN2A_D1_IN
vin2a_d1
-
-
-
-
D3
vin2a_d10
1720
215
2031
0
CFG_VIN2A_D10_IN
vin2a_d10
-
-
-
-
200
Timing Requirements and Switching Characteristics
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-7. Manual Functions Mapping for VIN2A (IOSET4/5/6) (continued)
BAL
L
BALL NAME
F6
VIP_MANUAL3
VIP_MANUAL5
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
vin2a_d11
1622
0
1702
0
D5
vin2a_d12
1350
412
1819
C2
vin2a_d13
1613
147
1476
C3
vin2a_d14
1149
516
1701
C4
vin2a_d15
1530
450
CFG REGISTER
MUXMODE
0
1
2
3
4
CFG_VIN2A_D11_IN
vin2a_d11
-
-
-
-
0
CFG_VIN2A_D12_IN
vin2a_d12
-
-
-
-
260
CFG_VIN2A_D13_IN
vin2a_d13
-
-
-
-
0
CFG_VIN2A_D14_IN
vin2a_d14
-
-
-
-
2021
0
CFG_VIN2A_D15_IN
vin2a_d15
-
-
-
-
B2
vin2a_d16
1512
449
2044
11
CFG_VIN2A_D16_IN
vin2a_d16
-
vin2b_d7
-
-
D6
vin2a_d17
1293
488
1839
5
CFG_VIN2A_D17_IN
vin2a_d17
-
vin2b_d6
-
-
C5
vin2a_d18
2140
371
2494
0
CFG_VIN2A_D18_IN
vin2a_d18
-
vin2b_d5
-
-
A3
vin2a_d19
2041
275
1699
611
CFG_VIN2A_D19_IN
vin2a_d19
-
vin2b_d4
-
-
D1
vin2a_d2
1675
35
1736
0
CFG_VIN2A_D2_IN
vin2a_d2
-
-
-
-
B3
vin2a_d20
1972
441
2412
88
CFG_VIN2A_D20_IN
vin2a_d20
-
vin2b_d3
-
-
B4
vin2a_d21
1957
556
2391
161
CFG_VIN2A_D21_IN
vin2a_d21
-
vin2b_d2
-
-
B5
vin2a_d22
2011
433
2446
102
CFG_VIN2A_D22_IN
vin2a_d22
-
vin2b_d1
-
-
A4
vin2a_d23
1962
523
2395
145
CFG_VIN2A_D23_IN
vin2a_d23
-
vin2b_d0
-
-
E2
vin2a_d3
1457
361
1943
0
CFG_VIN2A_D3_IN
vin2a_d3
-
-
-
-
D2
vin2a_d4
1535
0
1601
0
CFG_VIN2A_D4_IN
vin2a_d4
-
-
-
-
F4
vin2a_d5
1676
271
2052
0
CFG_VIN2A_D5_IN
vin2a_d5
-
-
-
-
C1
vin2a_d6
1513
0
1571
0
CFG_VIN2A_D6_IN
vin2a_d6
-
-
-
-
E4
vin2a_d7
1616
141
1855
0
CFG_VIN2A_D7_IN
vin2a_d7
-
-
-
-
F5
vin2a_d8
1286
437
1224
618
CFG_VIN2A_D8_IN
vin2a_d8
-
-
-
-
E6
vin2a_d9
1544
265
1373
509
CFG_VIN2A_D9_IN
vin2a_d9
-
-
-
-
G2
vin2a_de0
1732
208
1949
0
CFG_VIN2A_DE0_IN
vin2a_de0
vin2a_fld0
vin2b_fld1
vin2b_de1
-
H7
vin2a_fld0
1461
562
1983
151
CFG_VIN2A_FLD0_IN
vin2a_fld0
-
vin2b_clk1
-
-
G1
vin2a_hsync0
1877
0
1943
0
CFG_VIN2A_HSYNC0_IN
vin2a_hsync
0
-
-
vin2b_hsync
1
-
G6
vin2a_vsync0
1566
0
1612
0
CFG_VIN2A_VSYNC0_IN
vin2a_vsync
0
-
-
vin2b_vsync
1
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-8 Manual Functions Mapping for VIN2B (IOSET1/2/7) for a definition of the Manual modes.
Table 7-8 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Timing Requirements and Switching Characteristics
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Table 7-8. Manual Functions Mapping for VIN2B (IOSET1/2/7)
BALL
AC5
BALL NAME
VIP_MANUAL4
VIP_MANUAL6
CFG REGISTER
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
gpio6_10
2829
884
3009
892
MUXMODE
2
3
4
CFG_GPIO6_10_IN
-
-
vin2b_hsync1
AB4
gpio6_11
2648
1033
2890
1096
CFG_GPIO6_11_IN
-
-
vin2b_vsync1
AD4
mmc3_clk
2794
1074
2997
1089
CFG_MMC3_CLK_IN
-
-
vin2b_d7
AC4
mmc3_cmd
2789
1162
2959
1210
CFG_MMC3_CMD_IN
-
-
vin2b_d6
AC7
mmc3_dat0
2689
1180
2897
1269
CFG_MMC3_DAT0_IN
-
-
vin2b_d5
AC6
mmc3_dat1
2605
1219
2891
1219
CFG_MMC3_DAT1_IN
-
-
vin2b_d4
AC9
mmc3_dat2
2616
703
2947
590
CFG_MMC3_DAT2_IN
-
-
vin2b_d3
AC3
mmc3_dat3
2760
1235
2931
1342
CFG_MMC3_DAT3_IN
-
-
vin2b_d2
AC8
mmc3_dat4
2757
880
2979
891
CFG_MMC3_DAT4_IN
-
-
vin2b_d1
AD6
mmc3_dat5
2688
1177
2894
1262
CFG_MMC3_DAT5_IN
-
-
vin2b_d0
AB8
mmc3_dat6
2638
1165
2894
1187
CFG_MMC3_DAT6_IN
-
-
vin2b_de1
AB5
mmc3_dat7
995
182
1202
107
CFG_MMC3_DAT7_IN
-
-
vin2b_clk1
B2
vin2a_d16
1423
0
1739
0
CFG_VIN2A_D16_IN
vin2b_d7
-
-
D6
vin2a_d17
1253
0
1568
0
CFG_VIN2A_D17_IN
vin2b_d6
-
-
C5
vin2a_d18
2080
0
2217
0
CFG_VIN2A_D18_IN
vin2b_d5
-
-
A3
vin2a_d19
1849
0
2029
0
CFG_VIN2A_D19_IN
vin2b_d4
-
-
B3
vin2a_d20
1881
50
2202
0
CFG_VIN2A_D20_IN
vin2b_d3
-
-
B4
vin2a_d21
1917
167
2313
0
CFG_VIN2A_D21_IN
vin2b_d2
-
-
B5
vin2a_d22
1955
79
2334
0
CFG_VIN2A_D22_IN
vin2b_d1
-
-
A4
vin2a_d23
1899
145
2288
0
CFG_VIN2A_D23_IN
vin2b_d0
-
-
G2
vin2a_de0
1568
261
2048
0
CFG_VIN2A_DE0_IN
vin2b_fld1
vin2b_de1
-
H7
vin2a_fld0
0
0
0
0
CFG_VIN2A_FLD0_IN
vin2b_clk1
-
-
G1
vin2a_hsync0
1793
0
2011
0
CFG_VIN2A_HSYNC0_IN
-
vin2b_hsync1
-
G6
vin2a_vsync0
1382
0
1632
0
CFG_VIN2A_VSYNC0_IN
-
vin2b_vsync1
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-9 Manual Functions Mapping for VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8)
for a definition of the Manual modes.
Table 7-9 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
202
Timing Requirements and Switching Characteristics
Copyright © 2016–2017, Texas Instruments Incorporated
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Product Folder Links: DRA722 DRA724 DRA725 DRA726
DRA722, DRA724, DRA725, DRA726
www.ti.com
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-9. Manual Functions Mapping for VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3(1)
3(1)
4(1)
4(1)
5
6
vin1b_d0
R6
gpmc_a0
3080
1792
3376
1632
CFG_GPMC_A0_IN
vin1a_d16
-
-
vin2a_d0
-
-
T9
gpmc_a1
2958
1890
3249
1749
CFG_GPMC_A1_IN
vin1a_d17
-
-
vin2a_d1
-
-
vin1b_d1
N9
gpmc_a10
3073
1653
3388
1433
CFG_GPMC_A10_IN
vin1a_de0
-
-
-
-
-
vin1b_clk1
P9
gpmc_a11
3014
1784
3290
1693
CFG_GPMC_A11_IN
vin1a_fld0
-
-
vin2a_fld0
vin1a_fld0
-
vin1b_de1
K7
gpmc_a19
1385
0
1246
0
CFG_GPMC_A19_IN
-
-
-
vin2a_d12
-
-
vin2b_d0
T6
gpmc_a2
3041
1960
3322
1850
CFG_GPMC_A2_IN
vin1a_d18
-
-
vin2a_d2
-
-
vin1b_d2
M7
gpmc_a20
859
0
720
0
CFG_GPMC_A20_IN
-
-
-
vin2a_d13
-
-
vin2b_d1
J5
gpmc_a21
1465
0
1334
0
CFG_GPMC_A21_IN
-
-
-
vin2a_d14
-
-
vin2b_d2
K6
gpmc_a22
1210
0
1064
0
CFG_GPMC_A22_IN
-
-
-
vin2a_d15
-
-
vin2b_d3
J7
gpmc_a23
1111
0
954
0
CFG_GPMC_A23_IN
-
-
-
vin2a_fld0
-
-
vin2b_d4
J4
gpmc_a24
1137
0
1051
0
CFG_GPMC_A24_IN
-
-
-
-
-
-
vin2b_d5
J6
gpmc_a25
1402
0
1283
0
CFG_GPMC_A25_IN
-
-
-
-
-
-
vin2b_d6
H4
gpmc_a26
1298
0
1153
0
CFG_GPMC_A26_IN
-
-
-
-
-
-
vin2b_d7
H5
gpmc_a27
934
0
870
0
CFG_GPMC_A27_IN
-
-
-
-
-
-
vin2b_hsyn
c1
T7
gpmc_a3
3019
2145
3296
2050
CFG_GPMC_A3_IN
vin1a_d19
-
-
vin2a_d3
-
-
vin1b_d3
P6
gpmc_a4
3063
1981
3357
1829
CFG_GPMC_A4_IN
vin1a_d20
-
-
vin2a_d4
-
-
vin1b_d4
R9
gpmc_a5
3021
1954
3304
1840
CFG_GPMC_A5_IN
vin1a_d21
-
-
vin2a_d5
-
-
vin1b_d5
R5
gpmc_a6
3062
1716
3348
1592
CFG_GPMC_A6_IN
vin1a_d22
-
-
vin2a_d6
-
-
vin1b_d6
P5
gpmc_a7
3260
1889
3583
1631
CFG_GPMC_A7_IN
vin1a_d23
-
-
vin2a_d7
-
-
vin1b_d7
N7
gpmc_a8
3033
1702
3328
1547
CFG_GPMC_A8_IN
vin1a_hsyn
c0
-
-
-
-
-
vin1b_hsyn
c1
R4
gpmc_a9
2991
1905
3281
1766
CFG_GPMC_A9_IN
vin1a_vsyn
c0
-
-
-
-
-
vin1b_vsyn
c1
M6
gpmc_ad0
2907
1342
3181
1255
CFG_GPMC_AD0_IN
vin1a_d0
-
-
-
-
-
-
M2
gpmc_ad1
2858
1321
3132
1234
CFG_GPMC_AD1_IN
vin1a_d1
-
-
-
-
-
-
J1
gpmc_ad10
2920
1384
3223
1204
CFG_GPMC_AD10_IN
vin1a_d10
-
-
-
-
-
-
J2
gpmc_ad11
2719
1310
3019
1198
CFG_GPMC_AD11_IN
vin1a_d11
-
-
-
-
-
-
H1
gpmc_ad12
2845
1135
3160
917
CFG_GPMC_AD12_IN
vin1a_d12
-
-
-
-
-
-
J3
gpmc_ad13
2765
1225
3045
1119
CFG_GPMC_AD13_IN
vin1a_d13
-
-
-
-
-
-
H2
gpmc_ad14
2845
1150
3153
952
CFG_GPMC_AD14_IN
vin1a_d14
-
-
-
-
-
-
H3
gpmc_ad15
2766
1453
3044
1355
CFG_GPMC_AD15_IN
vin1a_d15
-
-
-
-
-
-
L5
gpmc_ad2
2951
1296
3226
1209
CFG_GPMC_AD2_IN
vin1a_d2
-
-
-
-
-
-
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Table 7-9. Manual Functions Mapping for VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) (continued)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
(1)
3
(1)
4(1)
4(1)
5
6
M1
gpmc_ad3
2825
1154
3121
997
CFG_GPMC_AD3_IN
vin1a_d3
-
-
-
-
-
-
L6
gpmc_ad4
2927
1245
3246
1014
CFG_GPMC_AD4_IN
vin1a_d4
-
-
-
-
-
-
L4
gpmc_ad5
2923
1251
3217
1098
CFG_GPMC_AD5_IN
vin1a_d5
-
-
-
-
-
-
L3
gpmc_ad6
2958
1342
3238
1239
CFG_GPMC_AD6_IN
vin1a_d6
-
-
-
-
-
-
L2
gpmc_ad7
2900
1244
3174
1157
CFG_GPMC_AD7_IN
vin1a_d7
-
-
-
-
-
-
L1
gpmc_ad8
2845
1585
3125
1482
CFG_GPMC_AD8_IN
vin1a_d8
-
-
-
-
-
K2
gpmc_ad9
2779
1343
3086
1223
CFG_GPMC_AD9_IN
vin1a_d9
-
-
-
-
-
-
N6
gpmc_ben0
1555
0
1425
0
CFG_GPMC_BEN0_IN
-
-
-
-
-
-
vin2b_de1
M4
gpmc_ben1
1501
0
1397
0
CFG_GPMC_BEN1_IN
-
-
-
vin2b_clk1
-
-
vin2b_fld1
P7
gpmc_clk
0
0
0
0
CFG_GPMC_CLK_IN
-
-
-
vin2a_hsyn
c0
-
vin2a_de0
vin2b_clk1
H6
gpmc_cs1
1192
0
1102
0
CFG_GPMC_CS1_IN
-
-
-
vin2a_de0
-
-
vin2b_vsyn
c1
P1
gpmc_cs3
1324
374
1466
353
CFG_GPMC_CS3_IN
vin1a_clk0
-
-
-
-
-
-
D1
1
vout1_clk
1648
885
1762
928
CFG_VOUT1_CLK_IN
-
vin2a_fld0
vin1a_fld0
vin1a_fld0
-
-
-
F11
vout1_d0
2197
565
2734
215
CFG_VOUT1_D0_IN
-
vin2a_d16
vin1a_d16
vin1a_d16
-
-
-
G1
0
vout1_d1
2221
576
2750
230
CFG_VOUT1_D1_IN
-
vin2a_d17
vin1a_d17
vin1a_d17
-
-
-
D7
vout1_d10
1800
863
1910
916
CFG_VOUT1_D10_IN
-
vin2a_d10
vin1a_d10
vin1a_d10
-
-
-
D8
vout1_d11
1656
931
1780
945
CFG_VOUT1_D11_IN
-
vin2a_d11
vin1a_d11
vin1a_d11
-
-
-
A5
vout1_d12
1719
1086
1866
1041
CFG_VOUT1_D12_IN
-
vin2a_d12
vin1a_d12
vin1a_d12
-
-
-
C6
vout1_d13
1757
928
1851
1022
CFG_VOUT1_D13_IN
-
vin2a_d13
vin1a_d13
vin1a_d13
-
-
-
C8
vout1_d14
2279
345
2788
0
CFG_VOUT1_D14_IN
-
vin2a_d14
vin1a_d14
vin1a_d14
-
-
-
C7
vout1_d15
1810
874
2786
69
CFG_VOUT1_D15_IN
-
vin2a_d15
vin1a_d15
vin1a_d15
-
-
-
B7
vout1_d16
1763
774
1880
807
CFG_VOUT1_D16_IN
-
vin2a_d0
vin1a_d0
vin1a_d0
-
-
-
B8
vout1_d17
1695
788
1805
838
CFG_VOUT1_D17_IN
-
vin2a_d1
vin1a_d1
vin1a_d1
-
-
-
A7
vout1_d18
1777
590
1871
684
CFG_VOUT1_D18_IN
-
vin2a_d2
vin1a_d2
vin1a_d2
-
-
-
A8
vout1_d19
2047
22
2196
0
CFG_VOUT1_D19_IN
-
vin2a_d3
vin1a_d3
vin1a_d3
-
-
-
F10
vout1_d2
1809
941
2759
178
CFG_VOUT1_D2_IN
-
vin2a_d18
vin1a_d18
vin1a_d18
-
-
-
C9
vout1_d20
1676
944
1795
973
CFG_VOUT1_D20_IN
-
vin2a_d4
vin1a_d4
vin1a_d4
-
-
-
A9
vout1_d21
1712
688
1848
670
CFG_VOUT1_D21_IN
-
vin2a_d5
vin1a_d5
vin1a_d5
-
-
-
B9
vout1_d22
1698
557
2443
0
CFG_VOUT1_D22_IN
-
vin2a_d6
vin1a_d6
vin1a_d6
-
-
-
204
Timing Requirements and Switching Characteristics
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-9. Manual Functions Mapping for VIN1A (IOSET2/3) and VIN1B (IOSET4) and VIN2B (IOSET8) (continued)
BA BALL NAME
LL
VIP_MANUAL7
VIP_MANUAL12
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
2
3
(1)
3
(1)
4(1)
4(1)
5
6
A1
0
vout1_d23
1627
1035
1726
1116
CFG_VOUT1_D23_IN
-
vin2a_d7
vin1a_d7
vin1a_d7
-
-
-
G1
1
vout1_d3
2427
429
2853
167
CFG_VOUT1_D3_IN
-
vin2a_d19
vin1a_d19
vin1a_d19
-
-
-
E9
vout1_d4
2351
412
2845
85
CFG_VOUT1_D4_IN
-
vin2a_d20
vin1a_d20
vin1a_d20
-
-
-
F9
vout1_d5
1634
983
1729
1076
CFG_VOUT1_D5_IN
-
vin2a_d21
vin1a_d21
vin1a_d21
-
-
-
F8
vout1_d6
1776
880
2736
107
CFG_VOUT1_D6_IN
-
vin2a_d22
vin1a_d22
vin1a_d22
-
-
-
E7
vout1_d7
2272
351
2757
53
CFG_VOUT1_D7_IN
-
vin2a_d23
vin1a_d23
vin1a_d23
-
-
-
E8
vout1_d8
1724
898
1819
990
CFG_VOUT1_D8_IN
-
vin2a_d8
vin1a_d8
vin1a_d8
-
-
-
D9
vout1_d9
2281
566
2804
195
CFG_VOUT1_D9_IN
-
vin2a_d9
vin1a_d9
vin1a_d9
-
-
-
B1
0
vout1_de
1734
749
1828
842
CFG_VOUT1_DE_IN
-
vin2a_de0
vin1a_de0
vin1a_de0
-
-
-
B1
1
vout1_fld
0
0
0
0
CFG_VOUT1_FLD_IN
-
vin2a_clk0
vin1a_clk0
vin1a_clk0
-
-
-
C1
1
vout1_hsync
1634
606
2399
0
CFG_VOUT1_HSYNC_I
N
-
vin2a_hsyn vin1a_hsyn vin1a_hsyn
c0
c0
c0
-
-
-
E1
1
vout1_vsync
1887
0
2068
0
CFG_VOUT1_VSYNC_I
N
-
vin2a_vsyn vin1a_vsyn vin1a_vsyn
c0
c0
c0
-
-
-
(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad Configuration
Registers.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-10 Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) for a definition
of the Manual modes.
Table 7-10 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-10. Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9)
BALL
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
3
4
5
R6
gpmc_a0
1891
427
2176
0
CFG_GPMC_A0_IN
-
vin2a_d0
-
T9
gpmc_a1
1713
513
2109
0
CFG_GPMC_A1_IN
-
vin2a_d1
-
P9
gpmc_a11
1797
317
2036
0
CFG_GPMC_A11_IN
-
vin2a_fld0
-
P4
gpmc_a12
0
0
0
0
CFG_GPMC_A12_IN
-
vin2a_clk0
-
R3
gpmc_a13
1876
391
2144
0
CFG_GPMC_A13_IN
-
vin2a_hsync0
-
Timing Requirements and Switching Characteristics
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Table 7-10. Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) (continued)
BALL
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
3
4
5
T2
gpmc_a14
1720
756
2384
38
CFG_GPMC_A14_IN
-
vin2a_vsync0
-
U2
gpmc_a15
1502
368
1804
0
CFG_GPMC_A15_IN
-
vin2a_d8
-
U1
gpmc_a16
1651
355
1902
0
CFG_GPMC_A16_IN
-
vin2a_d9
-
P3
gpmc_a17
1642
338
1862
0
CFG_GPMC_A17_IN
-
vin2a_d10
-
R2
gpmc_a18
1612
0
1406
0
CFG_GPMC_A18_IN
-
vin2a_d11
-
K7
gpmc_a19
1463
152
1418
0
CFG_GPMC_A19_IN
-
vin2a_d12
-
T6
gpmc_a2
1789
646
2310
0
CFG_GPMC_A2_IN
-
vin2a_d2
-
M7
gpmc_a20
1124
0
933
0
CFG_GPMC_A20_IN
-
vin2a_d13
-
J5
gpmc_a21
1491
206
1483
0
CFG_GPMC_A21_IN
-
vin2a_d14
-
K6
gpmc_a22
1218
245
1254
0
CFG_GPMC_A22_IN
-
vin2a_d15
-
J7
gpmc_a23
1216
0
1021
0
CFG_GPMC_A23_IN
-
vin2a_fld0
-
T7
gpmc_a3
1789
766
2451
8
CFG_GPMC_A3_IN
-
vin2a_d3
-
P6
gpmc_a4
1842
646
2329
0
CFG_GPMC_A4_IN
-
vin2a_d4
-
R9
gpmc_a5
1778
556
2215
0
CFG_GPMC_A5_IN
-
vin2a_d5
-
R5
gpmc_a6
1783
443
2088
0
CFG_GPMC_A6_IN
-
vin2a_d6
-
P5
gpmc_a7
2207
370
2393
0
CFG_GPMC_A7_IN
-
vin2a_d7
N1
gpmc_advn_ale
1755
116
1745
0
CFG_GPMC_ADVN_ALE_IN
-
vin2a_vsync0
-
P7
gpmc_clk
1896
351
2152
0
CFG_GPMC_CLK_IN
-
vin2a_hsync0
vin2a_de0
H6
gpmc_cs1
1337
74
1288
0
CFG_GPMC_CS1_IN
-
vin2a_de0
-
D11
vout1_clk
1939
332
2486
0
CFG_VOUT1_CLK_IN
vin2a_fld0
-
-
F11
vout1_d0
2140
647
2617
386
CFG_VOUT1_D0_IN
vin2a_d16
-
-
G10
vout1_d1
2104
615
2620
314
CFG_VOUT1_D1_IN
vin2a_d17
-
-
D7
vout1_d10
2139
406
2675
85
CFG_VOUT1_D10_IN
vin2a_d10
-
-
D8
vout1_d11
1944
534
2569
125
CFG_VOUT1_D11_IN
vin2a_d11
-
-
A5
vout1_d12
1966
659
2646
154
CFG_VOUT1_D12_IN
vin2a_d12
-
-
C6
vout1_d13
2048
447
2624
87
CFG_VOUT1_D13_IN
vin2a_d13
-
-
C8
vout1_d14
2222
548
2700
286
CFG_VOUT1_D14_IN
vin2a_d14
-
-
C7
vout1_d15
2072
443
2664
67
CFG_VOUT1_D15_IN
vin2a_d15
-
-
B7
vout1_d16
2044
455
2634
82
CFG_VOUT1_D16_IN
vin2a_d0
-
-
B8
vout1_d17
1971
246
2433
0
CFG_VOUT1_D17_IN
vin2a_d1
-
-
A7
vout1_d18
2104
120
2440
0
CFG_VOUT1_D18_IN
vin2a_d2
-
-
A8
vout1_d19
1888
0
2105
0
CFG_VOUT1_D19_IN
vin2a_d3
-
-
206
Timing Requirements and Switching Characteristics
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DRA722, DRA724, DRA725, DRA726
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-10. Manual Functions Mapping for VIN1A (IOSET4/5/6) and VIN2A (IOSET7/8/9) (continued)
BALL
BALL NAME
VIP_MANUAL8
VIP_MANUAL13
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
3
4
5
F10
vout1_d2
2170
237
2624
0
CFG_VOUT1_D2_IN
vin2a_d18
-
-
C9
vout1_d20
1942
512
2579
91
CFG_VOUT1_D20_IN
vin2a_d4
-
-
A9
vout1_d21
1997
141
2324
0
CFG_VOUT1_D21_IN
vin2a_d5
-
-
B9
vout1_d22
1949
0
2165
0
CFG_VOUT1_D22_IN
vin2a_d6
-
-
A10
vout1_d23
1871
704
2522
269
CFG_VOUT1_D23_IN
vin2a_d7
-
-
G11
vout1_d3
2319
417
2740
191
CFG_VOUT1_D3_IN
vin2a_d19
-
-
E9
vout1_d4
2300
369
2739
137
CFG_VOUT1_D4_IN
vin2a_d20
-
-
F9
vout1_d5
1923
579
2527
191
CFG_VOUT1_D5_IN
vin2a_d21
-
-
F8
vout1_d6
2148
396
2622
138
CFG_VOUT1_D6_IN
vin2a_d22
-
-
E7
vout1_d7
2212
335
2653
110
CFG_VOUT1_D7_IN
vin2a_d23
-
-
E8
vout1_d8
1962
573
2573
178
CFG_VOUT1_D8_IN
vin2a_d8
-
-
D9
vout1_d9
2312
335
2725
138
CFG_VOUT1_D9_IN
vin2a_d9
-
-
B10
vout1_de
1973
414
2551
52
CFG_VOUT1_DE_IN
vin2a_de0
-
-
B11
vout1_fld
0
0
0
0
CFG_VOUT1_FLD_IN
vin2a_clk0
-
-
C11
vout1_hsync
1813
261
2277
0
CFG_VOUT1_HSYNC_IN
vin2a_hsync0
-
-
E11
vout1_vsync
1665
0
1881
0
CFG_VOUT1_VSYNC_IN
vin2a_vsync0
-
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-11 Manual Functions Mapping for VIN1B (IOSET6) for a definition of the Manual modes.
Table 7-11 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-11. Manual Functions Mapping for VIN1B (IOSET6)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
6
R6
gpmc_a0
1873
702
2202
441
CFG_GPMC_A0_IN
-
vin1b_d0
T9
gpmc_a1
1629
772
2057
413
CFG_GPMC_A1_IN
-
vin1b_d1
N9
gpmc_a10
0
0
0
0
CFG_GPMC_A10_IN
-
vin1b_clk1
P9
gpmc_a11
1851
1011
2126
856
CFG_GPMC_A11_IN
-
vin1b_de1
P4
gpmc_a12
2009
601
2289
327
CFG_GPMC_A12_IN
-
vin1b_fld1
T6
gpmc_a2
1734
898
2131
573
CFG_GPMC_A2_IN
-
vin1b_d2
T7
gpmc_a3
1757
1076
2106
812
CFG_GPMC_A3_IN
-
vin1b_d3
P6
gpmc_a4
1794
893
2164
559
CFG_GPMC_A4_IN
-
vin1b_d4
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Table 7-11. Manual Functions Mapping for VIN1B (IOSET6) (continued)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
6
R9
gpmc_a5
1726
853
2120
523
CFG_GPMC_A5_IN
-
vin1b_d5
R5
gpmc_a6
1792
612
2153
338
CFG_GPMC_A6_IN
-
vin1b_d6
P5
gpmc_a7
2117
610
2389
304
CFG_GPMC_A7_IN
-
vin1b_d7
N7
gpmc_a8
1758
653
2140
308
CFG_GPMC_A8_IN
-
vin1b_hsync1
R4
gpmc_a9
1705
899
2067
646
CFG_GPMC_A9_IN
-
vin1b_vsync1
U4
mdio_d
1945
671
2265
414
CFG_MDIO_D_IN
vin1b_d0
-
V1
mdio_mclk
255
119
337
0
CFG_MDIO_MCLK_IN
vin1b_clk1
-
U5
rgmii0_rxc
2057
909
2341
646
CFG_RGMII0_RXC_IN
vin1b_d5
-
V5
rgmii0_rxctl
2121
1139
2323
988
CFG_RGMII0_RXCTL_IN
vin1b_d6
-
W2
rgmii0_rxd0
2070
655
2336
340
CFG_RGMII0_RXD0_IN
vin1b_fld1
-
V4
rgmii0_rxd3
2092
1357
2306
1216
CFG_RGMII0_RXD3_IN
vin1b_d7
-
W9
rgmii0_txc
2088
1205
2328
1079
CFG_RGMII0_TXC_IN
vin1b_d3
-
V9
rgmii0_txctl
2143
1383
2312
1311
CFG_RGMII0_TXCTL_IN
vin1b_d4
-
V6
rgmii0_txd1
2078
1189
2324
1065
CFG_RGMII0_TXD1_IN
vin1b_vsync1
-
U7
rgmii0_txd2
1928
1125
2306
763
CFG_RGMII0_TXD2_IN
vin1b_hsync1
-
V7
rgmii0_txd3
2255
971
2401
846
CFG_RGMII0_TXD3_IN
vin1b_de1
-
V2
uart3_rxd
1829
747
2220
400
CFG_UART3_RXD_IN
vin1b_d1
-
Y1
uart3_txd
2030
837
2324
568
CFG_UART3_TXD_IN
vin1b_d2
-
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-12 Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9) for a definition of the
Manual modes.
Table 7-12 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-12. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
4
6
K7
gpmc_a19
1600
943
2023
477
CFG_GPMC_A19_IN
vin2a_d12
vin2b_d0
M7
gpmc_a20
1440
621
1875
136
CFG_GPMC_A20_IN
vin2a_d13
vin2b_d1
J5
gpmc_a21
1602
1066
2021
604
CFG_GPMC_A21_IN
vin2a_d14
vin2b_d2
K6
gpmc_a22
1395
983
1822
519
CFG_GPMC_A22_IN
vin2a_d15
vin2b_d3
J7
gpmc_a23
1571
716
2045
200
CFG_GPMC_A23_IN
vin2a_fld0
vin2b_d4
J4
gpmc_a24
1463
832
1893
396
CFG_GPMC_A24_IN
-
vin2b_d5
208
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Table 7-12. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9) (continued)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
4
6
J6
gpmc_a25
1426
1166
1842
732
CFG_GPMC_A25_IN
-
vin2b_d6
H4
gpmc_a26
1362
1094
1797
584
CFG_GPMC_A26_IN
-
vin2b_d7
H5
gpmc_a27
1283
809
1760
338
CFG_GPMC_A27_IN
-
vin2b_hsync1
N6
gpmc_ben0
1978
780
2327
389
CFG_GPMC_BEN0_IN
-
vin2b_de1
M4
gpmc_ben1
0
0
0
0
CFG_GPMC_BEN1_IN
vin2b_clk1
vin2b_fld1
H6
gpmc_cs1
1411
982
1857
536
CFG_GPMC_CS1_IN
vin2a_de0
vin2b_vsync1
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-13 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.
Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-13. Manual Functions Mapping for VIN1A (IOSET8/9/10)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
7
9
AC5
gpio6_10
2131
2198
2170
2180
CFG_GPIO6_10_IN
-
vin1a_clk0
AB4
gpio6_11
3720
2732
4106
2448
CFG_GPIO6_11_IN
-
vin1a_de0
C14
mcasp1_aclkx
2447
0
3042
0
CFG_MCASP1_ACLKX_IN
vin1a_fld0
-
G12
mcasp1_axr0
3061
0
3380
292
CFG_MCASP1_AXR0_IN
vin1a_vsync0
-
F12
mcasp1_axr1
3113
0
3396
304
CFG_MCASP1_AXR1_IN
vin1a_hsync0
-
B13
mcasp1_axr10
2803
0
3362
0
CFG_MCASP1_AXR10_IN
vin1a_d13
-
A12
mcasp1_axr11
3292
0
3357
546
CFG_MCASP1_AXR11_IN
vin1a_d12
-
E14
mcasp1_axr12
2854
0
3145
320
CFG_MCASP1_AXR12_IN
vin1a_d11
-
A13
mcasp1_axr13
2813
0
3229
196
CFG_MCASP1_AXR13_IN
vin1a_d10
-
G14
mcasp1_axr14
2471
0
3053
0
CFG_MCASP1_AXR14_IN
vin1a_d9
-
F14
mcasp1_axr15
2815
0
3225
201
CFG_MCASP1_AXR15_IN
vin1a_d8
-
B12
mcasp1_axr8
2965
0
3427
83
CFG_MCASP1_AXR8_IN
vin1a_d15
-
A11
mcasp1_axr9
3082
0
3253
440
CFG_MCASP1_AXR9_IN
vin1a_d14
-
D14
mcasp1_fsx
2898
0
3368
139
CFG_MCASP1_FSX_IN
vin1a_de0
-
A19
mcasp2_aclkx
2413
0
2972
0
CFG_MCASP2_ACLKX_IN
vin1a_d7
-
C15
mcasp2_axr2
2478
0
3062
0
CFG_MCASP2_AXR2_IN
vin1a_d5
-
A16
mcasp2_axr3
2806
0
3175
242
CFG_MCASP2_AXR3_IN
vin1a_d4
-
A18
mcasp2_fsx
2861
78
2936
599
CFG_MCASP2_FSX_IN
vin1a_d6
-
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Table 7-13. Manual Functions Mapping for VIN1A (IOSET8/9/10) (continued)
BALL
BALL NAME
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
7
9
B18
mcasp3_aclkx
1583
0
1878
0
CFG_MCASP3_ACLKX_IN
vin1a_d3
-
B19
mcasp3_axr0
2873
0
3109
375
CFG_MCASP3_AXR0_IN
vin1a_d1
-
C17
mcasp3_axr1
1625
1400
2072
1023
CFG_MCASP3_AXR1_IN
vin1a_d0
vin1a_fld0
F15
mcasp3_fsx
2792
0
3146
257
CFG_MCASP3_FSX_IN
vin1a_d2
-
C18
mcasp4_aclkx
1547
268
1776
0
CFG_MCASP4_ACLKX_IN
-
vin1a_d15
G16
mcasp4_axr0
2362
587
2815
193
CFG_MCASP4_AXR0_IN
-
vin1a_d13
D17
mcasp4_axr1
2326
667
2769
304
CFG_MCASP4_AXR1_IN
-
vin1a_d12
A21
mcasp4_fsx
924
2573
1338
2219
CFG_MCASP4_FSX_IN
-
vin1a_d14
AA3
mcasp5_aclkx
3731
2106
4130
1708
CFG_MCASP5_ACLKX_IN
-
vin1a_d11
AB3
mcasp5_axr0
3800
3013
4159
2776
CFG_MCASP5_AXR0_IN
-
vin1a_d9
AA4
mcasp5_axr1
3828
2951
4179
2733
CFG_MCASP5_AXR1_IN
-
vin1a_d8
AB9
mcasp5_fsx
3675
2447
4074
2142
CFG_MCASP5_FSX_IN
-
vin1a_d10
AD4
mmc3_clk
3907
2744
4260
2450
CFG_MMC3_CLK_IN
-
vin1a_d7
AC4
mmc3_cmd
3892
2768
4242
2470
CFG_MMC3_CMD_IN
-
vin1a_d6
AC7
mmc3_dat0
3786
2765
4156
2522
CFG_MMC3_DAT0_IN
-
vin1a_d5
AC6
mmc3_dat1
3673
2961
4053
2667
CFG_MMC3_DAT1_IN
-
vin1a_d4
AC9
mmc3_dat2
3818
2447
4209
2096
CFG_MMC3_DAT2_IN
-
vin1a_d3
AC3
mmc3_dat3
3902
2903
4259
2672
CFG_MMC3_DAT3_IN
-
vin1a_d2
AC8
mmc3_dat4
3905
2622
4259
2342
CFG_MMC3_DAT4_IN
-
vin1a_d1
AD6
mmc3_dat5
3807
2824
4167
2595
CFG_MMC3_DAT5_IN
-
vin1a_d0
AB8
mmc3_dat6
3724
2818
4123
2491
CFG_MMC3_DAT6_IN
-
vin1a_hsync0
AB5
mmc3_dat7
3775
2481
4159
2161
CFG_MMC3_DAT7_IN
-
vin1a_vsync0
D18
xref_clk0
1971
0
2472
0
CFG_XREF_CLK0_IN
vin1a_d0
-
E17
xref_clk1
0
192
0
603
CFG_XREF_CLK1_IN
vin1a_clk0
-
210
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
Timing Requirements and Switching Characteristics
MUXMODE
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7.7
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Display Subsystem - Video Output Ports
Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI
Video Output 2 and DPI Video Output 3.
NOTE
The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
• 24-bit data bus (data[23:0])
• Horizontal synchronization signal (HSYNC)
• Vertical synchronization signal (VSYNC)
• Data enable (DE)
• Field ID (FID)
• Pixel clock (CLK)
NOTE
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-16.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
Table 7-14, Table 7-15 and Figure 7-6 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics(1)(2)
NO.
D1
PARAMETE
R
tc(clk)
DESCRIPTION
Cycle time, output pixel clock vouti_clk
MODE
MIN
MAX
UNIT
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
11.76
(3)
ns
DPI1/3 in 3.3V mode
13.33(3)
ns
D2
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
P*0.5-1
ns
D3
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
-2.5
2.5
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Table 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics(1)(2) (continued)
NO.
PARAMETE
R
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
D5
td(clk-ctlV)
D6
DESCRIPTION
MODE
MIN
MAX
UNIT
DPI1
-2.5
2.5
ns
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
2.5
ns
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
2.5
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
-2.5
2.5
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
-2.5
2.5
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
-2.5
2.5
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI3
-2.5
2.5
ns
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
Table 7-15. DPI Video Output i (i = 1..3) Alternate Switching Characteristics(2)
NO.
D1
PARAMETE
R
tc(clk)
DESCRIPTION
Cycle time, output pixel clock vouti_clk
MODE
MIN
MAX
(3)
UNIT
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
6.06
ns
DPI1/3 in 3.3V mode
13.33(3)
ns
D2
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
P*0.5-1
ns
D3
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI1
1.51
4.55
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI1
1.51
4.55
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
1.51
4.55
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
1.51
4.55
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
1.51
4.55
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (xref_clk2 clock
reference)
1.51
4.55
ns
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
1.51
4.55
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI3
1.51
4.55
ns
212
(1)
(1)
Timing Requirements and Switching Characteristics
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D3
D1
D4
Falling-edge Clock Reference
vouti_clk
D6
Rising-edge Clock Reference
vouti_clk
vouti_vsync
D6
vouti_hsync
D5
vouti_d[23:0]
data_1 data_2
data_n
D6
vouti_de
D6
vouti_fld
even
odd
SWPS049-018
(1)(2)(3)
Figure 7-6. DPI Video Output
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In Table 7-16 are presented the specific groupings of signals (IOSET) for use with VOUT2.
Table 7-16. VOUT2 IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
F2
4
AA4
6
vout2_d22
F3
4
AB3
6
vout2_d21
D1
4
AB9
6
vout2_d20
E2
4
AA3
6
vout2_d19
D2
4
D17
6
vout2_d18
F4
4
G16
6
vout2_d17
C1
4
A21
6
vout2_d16
E4
4
C18
6
vout2_d15
F5
4
A17
6
vout2_d14
E6
4
B17
6
vout2_d13
D3
4
B16
6
vout2_d12
F6
4
D15
6
vout2_d11
D5
4
A15
6
vout2_d10
C2
4
B15
6
vout2_d23
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Table 7-16. VOUT2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
vout2_d9
C3
4
A20
6
vout2_d8
C4
4
E15
6
vout2_d7
B2
4
D12
6
vout2_d6
D6
4
C12
6
vout2_d5
C5
4
F13
6
vout2_d4
A3
4
E12
6
vout2_d3
B3
4
J11
6
vout2_d2
B4
4
G13
6
vout2_d1
B5
4
J14
6
vout2_d0
A4
4
B14
6
vout2_vsync
G6
4
F20
6
vout2_hsync
G1
4
E21
6
vout2_clk
H7
4
B26
6
vout2_fld
E1
4
F21
6
vout2_de
G2
4
C23
6
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-17 Virtual
Functions Mapping for VOUT1 for a definition of the Virtual modes.
Table 7-17 presents the values for DELAYMODE bitfield.
Table 7-17. Virtual Functions Mapping for DSS VOUT1
BALL
BALL NAME
Delay Mode Value
DSS_VIRTUAL1
214
MUXMODE
0
3
H3
gpmc_ad15
14
vout3_d15
D9
vout1_d9
15
N7
gpmc_a8
15
L6
gpmc_ad4
14
E8
vout1_d8
15
M6
gpmc_ad0
14
F9
vout1_d5
15
J3
gpmc_ad13
14
vout3_d13
vout3_d18
vout1_d9
vout3_hsync
vout3_d4
vout1_d8
vout3_d0
vout1_d5
T6
gpmc_a2
15
M2
gpmc_ad1
14
vout3_d1
P6
gpmc_a4
15
vout3_d20
B10
vout1_de
15
vout1_de
vout1_d16
B7
vout1_d16
15
R5
gpmc_a6
15
A9
vout1_d21
15
H2
gpmc_ad14
14
vout3_d22
vout1_d21
vout3_d14
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Table 7-17. Virtual Functions Mapping for DSS VOUT1 (continued)
BALL
BALL NAME
Delay Mode Value
DSS_VIRTUAL1
MUXMODE
0
T9
gpmc_a1
15
E7
vout1_d7
15
vout1_d7
C11
vout1_hsync
15
vout1_hsync
D11
vout1_clk
15
vout1_clk
P1
gpmc_cs3
15
B9
vout1_d22
15
vout1_d22
G11
vout1_d3
15
vout1_d3
R4
gpmc_a9
15
D8
vout1_d11
15
J2
gpmc_ad11
14
3
vout3_d17
vout3_clk
vout3_vsync
vout1_d11
vout3_d11
L3
gpmc_ad6
14
D7
vout1_d10
15
vout3_d6
L5
gpmc_ad2
14
F10
vout1_d2
15
M1
gpmc_ad3
14
vout3_d3
P5
gpmc_a7
15
vout3_d23
T7
gpmc_a3
15
A7
vout1_d18
15
vout1_d18
C7
vout1_d15
15
vout1_d15
J1
gpmc_ad10
14
vout3_d10
vout3_d7
vout1_d10
vout3_d2
vout1_d2
vout3_d19
L2
gpmc_ad7
14
N9
gpmc_a10
15
F11
vout1_d0
15
vout1_d0
G10
vout1_d1
15
vout1_d1
R9
gpmc_a5
15
vout3_d21
L1
gpmc_ad8
14
vout3_d8
F8
vout1_d6
15
L4
gpmc_ad5
14
A10
vout1_d23
15
vout1_d23
E11
vout1_vsync
15
vout1_vsync
C9
vout1_d20
15
vout1_d20
R6
gpmc_a0
15
A8
vout1_d19
15
vout1_d19
vout1_d4
vout3_de
vout1_d6
vout3_d5
vout3_d16
E9
vout1_d4
15
H1
gpmc_ad12
14
B11
vout1_fld
15
P9
gpmc_a11
15
vout3_fld
K2
gpmc_ad9
14
vout3_d9
C6
vout1_d13
15
vout1_d13
B8
vout1_d17
15
vout1_d17
A5
vout1_d12
15
vout1_d12
C8
vout1_d14
15
vout1_d14
vout3_d12
vout1_fld
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See Table 7-2
Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-18
Manual Functions Mapping for DSS VOUT1 for a definition of the Manual modes.
Table 7-18 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-18. Manual Functions Mapping for DSS VOUT1
216
BALL
BALL NAME
VOUT1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
D11
vout1_clk
0
212
CFG_VOUT1_CLK_OUT
vout1_clk
0
F11
vout1_d0
2502
0
CFG_VOUT1_D0_OUT
vout1_d0
G10
vout1_d1
2402
0
CFG_VOUT1_D1_OUT
vout1_d1
D7
vout1_d10
2147
0
CFG_VOUT1_D10_OUT
vout1_d10
D8
vout1_d11
2249
0
CFG_VOUT1_D11_OUT
vout1_d11
A5
vout1_d12
2410
0
CFG_VOUT1_D12_OUT
vout1_d12
C6
vout1_d13
2129
0
CFG_VOUT1_D13_OUT
vout1_d13
C8
vout1_d14
2279
0
CFG_VOUT1_D14_OUT
vout1_d14
C7
vout1_d15
2266
23
CFG_VOUT1_D15_OUT
vout1_d15
B7
vout1_d16
1798
0
CFG_VOUT1_D16_OUT
vout1_d16
B8
vout1_d17
2243
0
CFG_VOUT1_D17_OUT
vout1_d17
A7
vout1_d18
2127
0
CFG_VOUT1_D18_OUT
vout1_d18
A8
vout1_d19
2096
0
CFG_VOUT1_D19_OUT
vout1_d19
F10
vout1_d2
2375
0
CFG_VOUT1_D2_OUT
vout1_d2
C9
vout1_d20
2105
0
CFG_VOUT1_D20_OUT
vout1_d20
A9
vout1_d21
2120
0
CFG_VOUT1_D21_OUT
vout1_d21
B9
vout1_d22
2013
65
CFG_VOUT1_D22_OUT
vout1_d22
A10
vout1_d23
1887
0
CFG_VOUT1_D23_OUT
vout1_d23
G11
vout1_d3
2429
0
CFG_VOUT1_D3_OUT
vout1_d3
E9
vout1_d4
2639
0
CFG_VOUT1_D4_OUT
vout1_d4
F9
vout1_d5
2319
0
CFG_VOUT1_D5_OUT
vout1_d5
F8
vout1_d6
2227
0
CFG_VOUT1_D6_OUT
vout1_d6
E7
vout1_d7
2309
0
CFG_VOUT1_D7_OUT
vout1_d7
E8
vout1_d8
1999
0
CFG_VOUT1_D8_OUT
vout1_d8
D9
vout1_d9
2276
0
CFG_VOUT1_D9_OUT
vout1_d9
B10
vout1_de
1933
0
CFG_VOUT1_DE_OUT
vout1_de
B11
vout1_fld
1825
0
CFG_VOUT1_FLD_OUT
vout1_fld
C11
vout1_hsync
1741
13
CFG_VOUT1_HSYNC_OUT
vout1_hsync
E11
vout1_vsync
2338
0
CFG_VOUT1_VSYNC_OUT
vout1_vsync
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Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2
Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-19
Manual Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.
Table 7-19 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
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Table 7-19. Manual Functions Mapping for DSS VOUT2 IOSET1
BALL
BALL NAME
VOUT2_IOSET1_MANUAL1
A_DELAY (ps) G_DELAY (ps)
218
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
CFG REGISTER
MUXMODE
4
E1
vin2a_clk0
2571
0
1059
0
1025
0
CFG_VIN2A_CLK0_OUT
vout2_fld
F2
vin2a_d0
2124
0
589
0
577
0
CFG_VIN2A_D0_OUT
vout2_d23
F3
vin2a_d1
2103
0
568
0
557
0
CFG_VIN2A_D1_OUT
vout2_d22
D3
vin2a_d10
2091
0
557
0
545
0
CFG_VIN2A_D10_OUT
vout2_d13
F6
vin2a_d11
2142
0
608
0
596
0
CFG_VIN2A_D11_OUT
vout2_d12
D5
vin2a_d12
2920
385
1816
255
1783
276
CFG_VIN2A_D12_OUT
vout2_d11
C2
vin2a_d13
2776
322
1872
192
1838
213
CFG_VIN2A_D13_OUT
vout2_d10
C3
vin2a_d14
2904
0
1769
0
1757
0
CFG_VIN2A_D14_OUT
vout2_d9
C4
vin2a_d15
2670
257
1665
127
1632
148
CFG_VIN2A_D15_OUT
vout2_d8
B2
vin2a_d16
2814
155
1908
31
1878
43
CFG_VIN2A_D16_OUT
vout2_d7
D6
vin2a_d17
3002
199
1897
69
1865
89
CFG_VIN2A_D17_OUT
vout2_d6
C5
vin2a_d18
1893
0
358
0
347
0
CFG_VIN2A_D18_OUT
vout2_d5
A3
vin2a_d19
1698
0
163
0
151
0
CFG_VIN2A_D19_OUT
vout2_d4
D1
vin2a_d2
2193
0
658
0
646
0
CFG_VIN2A_D2_OUT
vout2_d21
B3
vin2a_d20
1736
0
202
0
190
0
CFG_VIN2A_D20_OUT
vout2_d3
B4
vin2a_d21
1636
0
101
0
89
0
CFG_VIN2A_D21_OUT
vout2_d2
B5
vin2a_d22
1628
0
93
0
81
0
CFG_VIN2A_D22_OUT
vout2_d1
A4
vin2a_d23
1538
0
0
0
0
0
CFG_VIN2A_D23_OUT
vout2_d0
E2
vin2a_d3
1997
0
462
0
450
0
CFG_VIN2A_D3_OUT
vout2_d20
D2
vin2a_d4
2528
0
993
0
982
0
CFG_VIN2A_D4_OUT
vout2_d19
F4
vin2a_d5
2038
0
503
0
492
0
CFG_VIN2A_D5_OUT
vout2_d18
C1
vin2a_d6
1746
0
211
0
200
0
CFG_VIN2A_D6_OUT
vout2_d17
E4
vin2a_d7
2213
0
678
0
666
0
CFG_VIN2A_D7_OUT
vout2_d16
F5
vin2a_d8
2268
0
733
0
721
0
CFG_VIN2A_D8_OUT
vout2_d15
vout2_d14
E6
vin2a_d9
2170
0
635
0
623
0
CFG_VIN2A_D9_OUT
G2
vin2a_de0
2102
0
568
0
556
0
CFG_VIN2A_DE0_OUT
vout2_de
H7
vin2a_fld0
0
983
1398
1185
1385
1202
CFG_VIN2A_FLD0_OUT
vout2_clk
G1
vin2a_hsync0
2482
0
974
0
936
0
CFG_VIN2A_HSYNC0_
OUT
vout2_hsync
G6
vin2a_vsync0
2296
0
784
0
750
0
CFG_VIN2A_VSYNC0_
OUT
vout2_vsync
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Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-20 Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual
modes.
Table 7-20 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-20. Manual Functions Mapping for DSS VOUT2 IOSET2
BALL
BALL NAME
VOUT2_IOSET2_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
E21
gpio6_14
1983
0
79
0
68
F20
gpio6_15
2159
0
158
0
A_DELAY (ps) G_DELAY (ps)
VOUT2_IOSET2_MANUAL2
VOUT2_IOSET2_MANUAL3
CFG REGISTER
MUXMODE
0
CFG_GPIO6_14_OUT
vout2_hsync
148
0
CFG_GPIO6_15_OUT
vout2_vsync
6
F21
gpio6_16
1864
0
0
0
0
0
CFG_GPIO6_16_OUT
vout2_fld
B14
mcasp1_aclkr
2614
0
1255
0
1270
0
CFG_MCASP1_ACLKR
_OUT
vout2_d0
G13
mcasp1_axr2
2705
0
1350
0
1360
0
CFG_MCASP1_AXR2_
OUT
vout2_d2
J11
mcasp1_axr3
2865
0
1210
0
1219
0
CFG_MCASP1_AXR3_
OUT
vout2_d3
E12
mcasp1_axr4
2759
0
1404
0
1413
0
CFG_MCASP1_AXR4_
OUT
vout2_d4
F13
mcasp1_axr5
2980
0
1325
0
1335
0
CFG_MCASP1_AXR5_
OUT
vout2_d5
C12
mcasp1_axr6
2634
0
1275
0
1289
0
CFG_MCASP1_AXR6_
OUT
vout2_d6
D12
mcasp1_axr7
2658
0
1302
0
1311
0
CFG_MCASP1_AXR7_
OUT
vout2_d7
J14
mcasp1_fsr
2818
0
1163
0
1172
0
CFG_MCASP1_FSR_O
UT
vout2_d1
E15
mcasp2_aclkr
2728
0
1373
0
1382
0
CFG_MCASP2_ACLKR
_OUT
vout2_d8
B15
mcasp2_axr0
2513
0
319
534
308
560
CFG_MCASP2_AXR0_
OUT
vout2_d10
A15
mcasp2_axr1
2712
0
1357
0
1366
0
CFG_MCASP2_AXR1_
OUT
vout2_d11
D15
mcasp2_axr4
2529
0
1169
0
1184
0
CFG_MCASP2_AXR4_
OUT
vout2_d12
B16
mcasp2_axr5
2376
0
543
478
1029
0
CFG_MCASP2_AXR5_
OUT
vout2_d13
B17
mcasp2_axr6
2620
0
1265
0
1274
0
CFG_MCASP2_AXR6_
OUT
vout2_d14
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Table 7-20. Manual Functions Mapping for DSS VOUT2 IOSET2 (continued)
BALL
BALL NAME
VOUT2_IOSET2_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
A17
mcasp2_axr7
2492
0
354
483
845
0
CFG_MCASP2_AXR7_
OUT
vout2_d15
A20
mcasp2_fsr
2358
0
12
487
513
0
CFG_MCASP2_FSR_O
UT
vout2_d9
C18
mcasp4_aclkx
2524
0
1165
0
1179
0
CFG_MCASP4_ACLKX_
OUT
vout2_d16
G16
mcasp4_axr0
2578
0
797
0
806
0
CFG_MCASP4_AXR0_
OUT
vout2_d18
D17
mcasp4_axr1
2253
0
750
0
759
0
CFG_MCASP4_AXR1_
OUT
vout2_d19
A21
mcasp4_fsx
2478
0
823
0
832
0
CFG_MCASP4_FSX_O
UT
vout2_d17
AA3
mcasp5_aclkx
4672
1737
3256
1798
3226
1837
CFG_MCASP5_ACLKX_
OUT
vout2_d20
AB3
mcasp5_axr0
4642
1286
3226
1347
3196
1386
CFG_MCASP5_AXR0_
OUT
vout2_d22
AA4
mcasp5_axr1
4625
725
3209
786
3179
825
CFG_MCASP5_AXR1_
OUT
vout2_d23
AB9
mcasp5_fsx
4565
1062
3149
1123
3119
1162
CFG_MCASP5_FSX_O
UT
vout2_d21
B26
xref_clk2
0
49
1359
466
1341
512
CFG_XREF_CLK2_OUT
vout2_clk
C23
xref_clk3
1947
0
36
0
45
0
CFG_XREF_CLK3_OUT
vout2_de
A_DELAY (ps) G_DELAY (ps)
220
VOUT2_IOSET2_MANUAL2
VOUT2_IOSET2_MANUAL3
Timing Requirements and Switching Characteristics
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See Table 7-2
Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-21
Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
Table 7-21 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-21. Manual Functions Mapping for DSS VOUT3
BALL
7.8
BALL NAME
VOUT3_MANUAL1
CFG REGISTER
A_DELAY (ps)
G_DELAY (ps)
MUXMODE
3
R6
gpmc_a0
2395
0
CFG_GPMC_A0_OUT
vout3_d16
T9
gpmc_a1
2412
0
CFG_GPMC_A1_OUT
vout3_d17
N9
gpmc_a10
2473
0
CFG_GPMC_A10_OUT
vout3_de
P9
gpmc_a11
2906
0
CFG_GPMC_A11_OUT
vout3_fld
T6
gpmc_a2
2360
0
CFG_GPMC_A2_OUT
vout3_d18
T7
gpmc_a3
2391
0
CFG_GPMC_A3_OUT
vout3_d19
P6
gpmc_a4
2626
0
CFG_GPMC_A4_OUT
vout3_d20
R9
gpmc_a5
2338
0
CFG_GPMC_A5_OUT
vout3_d21
R5
gpmc_a6
2374
0
CFG_GPMC_A6_OUT
vout3_d22
P5
gpmc_a7
2432
0
CFG_GPMC_A7_OUT
vout3_d23
N7
gpmc_a8
3155
0
CFG_GPMC_A8_OUT
vout3_hsync
R4
gpmc_a9
2309
0
CFG_GPMC_A9_OUT
vout3_vsync
M6
gpmc_ad0
2360
0
CFG_GPMC_AD0_OUT
vout3_d0
M2
gpmc_ad1
2420
0
CFG_GPMC_AD1_OUT
vout3_d1
J1
gpmc_ad10
2235
0
CFG_GPMC_AD10_OU
T
vout3_d10
J2
gpmc_ad11
2253
0
CFG_GPMC_AD11_OU
T
vout3_d11
H1
gpmc_ad12
1949
427
CFG_GPMC_AD12_OU
T
vout3_d12
J3
gpmc_ad13
2318
0
CFG_GPMC_AD13_OU
T
vout3_d13
H2
gpmc_ad14
2123
0
CFG_GPMC_AD14_OU
T
vout3_d14
H3
gpmc_ad15
2195
29
CFG_GPMC_AD15_OU
T
vout3_d15
L5
gpmc_ad2
2617
0
CFG_GPMC_AD2_OUT
vout3_d2
M1
gpmc_ad3
2350
0
CFG_GPMC_AD3_OUT
vout3_d3
L6
gpmc_ad4
2324
0
CFG_GPMC_AD4_OUT
vout3_d4
L4
gpmc_ad5
2371
0
CFG_GPMC_AD5_OUT
vout3_d5
L3
gpmc_ad6
2231
0
CFG_GPMC_AD6_OUT
vout3_d6
L2
gpmc_ad7
2440
0
CFG_GPMC_AD7_OUT
vout3_d7
L1
gpmc_ad8
2479
0
CFG_GPMC_AD8_OUT
vout3_d8
K2
gpmc_ad9
2355
0
CFG_GPMC_AD9_OUT
vout3_d9
P1
gpmc_cs3
0
641
CFG_GPMC_CS3_OUT
vout3_clk
Display Subsystem - High-Definition Multimedia Interface (HDMI)
The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals
from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other
video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p
@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is
supported (differential).
Timing Requirements and Switching Characteristics
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NOTE
For more information, see the High-Definition Multimedia Interface chapter of the device
TRM
7.9
Camera Serial Interface 2 CAL bridge (CSI2)
NOTE
For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device
TRM
The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external
image sensor, data from memory. The CAL is a key component for the following multimedia applications:
camera viewfinder, video record, and still image capture. The CAL has two serial camera interfaces
(primary and secondary):
• The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes.
• The secondary serial interface (CSI2 Port B) is compliant with MIPI CSI-2 protocol with two data lanes.
7.9.1
CSI-2 MIPI D-PHY-1.5 V and 1.8 V
The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 4 data differential lanes plus 1 clock differential lane in synchronous mode,
double data rate:
• 1.5 Gbps (750 MHz) @OPP_NOM for each lane.
The CSI-2 port B is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 2 data lanes plus 1 clock lane (differential) in synchronous mode, double data
rate:
• 1.5 Gbps (750 MHz) @OPP_NOM for each lane, in synchronous mode.
7.10 External Memory Interface (EMIF)
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
• One interface with associated DDR3/DDR3L PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
7.11 General-Purpose Memory Controller (GPMC)
The GPMC is the unified memory controller that interfaces external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
NOTE
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
222
Timing Requirements and Switching Characteristics
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
7.11.1 GPMC/NOR Flash Interface Synchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-22 and Table 7-23 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-7, Figure 7-8, Figure 7-9, Figure 7-10, Figure 7-11 and
Figure 7-12).
Table 7-22. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default
NO.
PARAMETER
DESCRIPTION
F12
tsu(dV-clkH)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
F13
th(clkH-dV)
F21
tsu(waitV-clkH)
F22
th(clkH-waitV)
MIN
MAX
UNIT
3
ns
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
1.1
ns
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
2.5
ns
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.3
ns
NOTE
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
Table 7-23. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default
NO.
PARAMETER
F0
tc(clk)
Cycle time, output clock gpmc_clk period
DESCRIPTION
F2
td(clkH-nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
MIN
MAX
11.3
F-1.7
(7)
(6)
F3
td(clkH-nCSIV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
E-1.7
F4
td(ADDV-clk)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
B-1.8 (3)
F5
td(clkH-ADDIV)
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
UNIT
ns
F+4.3
(7)
ns
E+4.2
(6)
ns
B+4.3 (3)
ns
-1.8
ns
(3)
(3)
F6
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
B-4.3
B+1.5
ns
F7
td(clkH-nBEIV)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
D-1.5(5)
D+4.3(5)
ns
F8
td(clkH-nADV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
G-1.3 (8)
G+4.2 (8)
ns
(5)
(5)
ns
F9
td(clkH-nADVIV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
D-1.3
F10
td(clkH-nOE)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
H-1.0 (9)
H+3.2 (9)
ns
F11
td(clkH-nOEIV)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
E-1.0 (6)
E+3.2 (6)
ns
F14
td(clkH-nWE)
Delay time, gpmc_clk rising edge to gpmc_wen transition
I-0.9 (10)
I+4.2 (10)
ns
J+4.6
(11)
ns
J+4.3
(11)
ns
F15
td(clkH-Data)
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
J-2.1
(11)
F17
td(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
J-1.5
(11)
F18
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
G+4.2
A
(2)
ns
ns
F19
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
(4)
F20
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K
(12)
F23
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16 transition
0.5
ns
7.5
ns
Table 7-24. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F12
tsu(dV-clkH)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
2.5
ns
F13
th(clkH-dV)
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
1.9
ns
Timing Requirements and Switching Characteristics
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Table 7-24. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
F21
tsu(waitV-clkH)
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
2.5
ns
F22
th(clkH-waitV)
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
1.9
ns
Table 7-25. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate
NO.
F0
PARAMETER
tc(clk)
DESCRIPTION
MIN
Cycle time, output clock gpmc_clk period (13)
MAX
15.04
(7)
UNIT
ns
F+7.0
(7)
ns
F2
td(clkH-nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
F+0.6
F3
td(clkH-nCSIV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
E+0.6 (6)
E+7.0 (6)
ns
F4
td(ADDV-clk)
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
B-0.7 (3)
B+7.0 (3)
ns
F5
td(clkH-ADDIV)
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
F6
td(nBEV-clk)
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
B-7.0
B+0.4
ns
F7
td(clkH-nBEIV)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
D-0.4
D+7.0
ns
-0.7
ns
(8)
G+6.1
(8)
ns
F8
td(clkH-nADV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
G+0.7
F9
td(clkH-nADVIV)
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
D+0.7 (5)
D+6.1 (5)
ns
F10
td(clkH-nOE)
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
H+0.7 (9)
H+5.1 (9)
ns
F11
td(clkH-nOEIV)
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
E+0.7 (6)
E+5.1 (6)
ns
ns
F14
td(clkH-nWE)
Delay time, gpmc_clk rising edge to gpmc_wen transition
I+0.7
(10)
I+6.1
(10)
F15
td(clkH-Data)
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
J-0.4
(11)
J+4.9
(11)
ns
F17
td(clkH-nBE)
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
J-0.4
(11)
J+4.9
(11)
ns
F18
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(2)
F19
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
(4)
ns
F20
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K
(12)
ns
F23
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition
(14)
0.5
7.5
ns
ns
(1) Total GPMC load on any signal at 3.3V must not exceed 10pF.
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
with n the page burst access number.
(3) B = ClkActivationTime * GPMC_FCLK
(4) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For Burst write: C = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n the page burst
access number.
(5) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(6) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(7) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 * CSExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1:
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
F = (3 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
224
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(8) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV desactivated) in Reading mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 3) is a multiple of 4)
For ADV rising edge (ADV desactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 3) is a multiple of 4)
(9) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 * OEExtraDelay)) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE desactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 4)
Timing Requirements and Switching Characteristics
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- H = (3 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE desactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(11) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(12) For read:
K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(13) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(14) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(15) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
226
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
Address (MSB)
gpmc_a[10:1]
gpmc_a[27]
F6
F7
F19
gpmc_ben1
F6
F7
F19
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F13
F4
gpmc_ad[15:0]
F5
F12
Address (LSB)
D0
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_01
Figure 7-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F6
F7
F19
gpmc_ben1
F6
F7
F19
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F13
F12
D0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_02
Figure 7-8. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
228
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F6
F19
Valid
gpmc_ben1
F7
F6
F19
Valid
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F12
F4
gpmc_ad[15:0]
F5
F13
D0
Address (LSB)
F22
D1
F12
D2
D3
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_03
Figure 7-9. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F7
F6
F19
Valid
gpmc_ben1
F7
F6
F19
Valid
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F10
F11
gpmc_oen_ren
F12
F13
gpmc_ad[15:0]
D0
D1
F12
D2
D3
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_04
Figure 7-10. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits (GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
230
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F6
F17
F6
F17
F17
gpmc_ben1
F17
F17
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F14
F14
gpmc_wen
F15
gpmc_ad[15:0]
Address (LSB)
D0
F22
D1
F15
D2
F15
D3
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_05
Figure 7-11. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 0 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
Address
gpmc_a[27:1]
F17
F6
F17
F17
gpmc_ben1
F17
F6
F17
F17
gpmc_ben0
F8
F8
F20
F9
gpmc_advn_ale
F14
F14
gpmc_wen
F15
gpmc_ad[15:0]
D0
D1
F15
F15
D2
D3
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_06
Figure 7-12. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits (GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-26 and Table 7-27 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-13, Figure 7-14, Figure 7-15, Figure 7-16, Figure 7-17 and
Figure 7-18).
Table 7-26. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
FA5
232
PARAMETER
tacc(DAT)
DESCRIPTION
Data Maximum Access Time (GPMC_FCLK cycles)
MIN
MAX
UNIT
(1)
cycles
H
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Table 7-26. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode (continued)
NO.
PARAMETER
DESCRIPTION
FA20
tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
FA21
tacc2-pgmode(DAT)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
-
tsu(DV-OEH)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
MIN
MAX
UNIT
P
(2)
cycles
H
(1)
cycles
1.9
ns
1
ns
(1) H = Access Time * (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime * (TimeParaGranularity + 1)
Table 7-27. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
-
tr(DO)
Rising time, gpmc_ad[15:0] output data
0.447
4.067
ns
-
tf(DO)
Fallling time, gpmc_ad[15:0] output data
0.43
4.463
ns
FA0
tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
N
(1)
FA1
tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(2)
FA3
td(nCSV-nADVIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
FA4
td(nCSV-nOEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
FA9
td(AV-nCSV)
ns
ns
B-2
(3)
B+4
(3)
C-2
(4)
ns
C+4
(4)
Delay time, address bus valid to gpmc_cs[7:0] valid
J-2
ns
(5)
J+4
(5)
ns
J-2
(5)
J+4
(5)
FA10 td(nBEV-nCSV)
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
FA12 td(nCSV-nADVV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
ns
K-2
(6)
K+4
(6)
FA13 td(nCSV-nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
ns
L-2
(7)
L+4
(7)
ns
FA16 tw(AIV)
Pulse duration, address invalid between 2 successive R/W accesses
G
FA18 td(nCSV-nOEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
I-2
(9)
I+4
(9)
FA20 tw(AV)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
FA25 td(nCSV-nWEV)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
E-2
(11)
E+4
(11)
ns
FA27 td(nCSV-nWEIV)
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
F-2
(12)
F+4
(12)
ns
FA28 td(nWEV-DV)
Delay time, gpmc_ wen valid to data bus valid
FA29 td(DV-nCSV)
Delay time, data bus valid to gpmc_cs[7:0] valid
FA37 td(nOEV-AIV)
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus
phase end
D
ns
(8)
2
J-2
ns
ns
(10)
(5)
J+4
ns
(5)
2
ns
ns
(1) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(3) For reading: B = ((ADVRdOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(4) C = ((OEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(5) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
(6) K = ((ADVOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - CSExtraDelay)) * GPMC_FCLK
(7) L = ((OEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(8) G = Cycle2CycleDelay * GPMC_FCLK * (TimeParaGranularity +1)
(9) I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(11) E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(12) F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
Valid Address
gpmc_a[27:1]
FA0
FA10
gpmc_ben0
Valid
gpmc_ben1
Valid
FA0
FA10
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
DIR
OUT
IN
OUT
GPMC_07
Figure 7-13. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_csi
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
Address 1
FA0
FA0
FA10
FA10
gpmc_ben0
Valid
FA0
FA0
gpmc_ben1
Valid
Valid
Valid
FA10
FA10
FA3
FA3
FA12
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
DIR
OUT
FA14
IN
OUT
IN
GPMC_08
(1)(2)(3)
Figure 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA21
FA20
FA20
FA20
FA1
gpmc_csi
FA9
Add0
gpmc_a[27:1]
Add1
Add2
Add3
D0
D1
D2
Add4
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D3
gpmc_waitj
FA15
FA14
DIR
OUT
IN
OUT
SPRS91v_GPMC_09
Figure 7-15. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime
register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
236
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
Valid Address
gpmc_a[27:1]
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
Data OUT
gpmc_ad[15:0]
gpmc_waitj
DIR
OUT
GPMC_10
Figure 7-16. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
Valid
FA0
FA10
Valid
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
FA29
gpmc_ad[15:0]
FA37
Address (LSB)
Data IN
Data IN
FA15
FA14
DIR
OUT
IN
OUT
gpmc_waitj
GPMC_11
Figure 7-17. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
FA29
FA28
Valid Address (LSB)
gpmc_ad[15:0]
Data OUT
gpmc_waitj
OUT
DIR
GPMC_12
Figure 7-18. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-28 and Table 7-29 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-19, Figure 7-20, Figure 7-21 and Figure 7-22).
Table 7-28. GPMC/NAND Flash Interface Timing Requirements
NO.
GNF12
PARAMETER
DESCRIPTION
tacc(DAT)
Data maximum access time (GPMC_FCLK Cycles)
-
tsu(DV-OEH)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
MIN
MAX
J
(1)
UNIT
cycles
1.9
ns
1
ns
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(1) J = AccessTime * (TimeParaGranularity + 1)
Table 7-29. GPMC/NAND Flash Interface Switching Characteristics
NO.
MIN
MAX
UNIT
-
tr(DO)
PARAMETER
Rising time, gpmc_ad[15:0] output data
DESCRIPTION
0.447
4.067
ns
-
0.43
4.463
ns
tf(DO)
Fallling time, gpmc_ad[15:0] output data
GNF0
tw(nWEV)
Pulse duration, gpmc_wen valid time
GNF1
td(nCSV-nWEV)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
A
B-2
(2)
(1)
ns
B+4
(2)
ns
ns
GNF2
td(CLEH-nWEV)
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
C-2
(3)
C+4
(3)
GNF3
td(nWEV-DV)
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
D-2
(4)
D+4
(4)
ns
GNF4
td(nWEIV-DIV)
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
E-2
(5)
E+4
(5)
ns
GNF5
td(nWEIV-CLEIV)
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
F-2
(6)
F+4
(6)
ns
ns
GNF6
td(nWEIV-nCSIV)
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
G-2
(7)
G+4
(7)
GNF7
td(ALEH-nWEV)
Delay time, gpmc_advn_ale high to gpmc_wen valid
C-2
(3)
C+4
(3)
ns
GNF8
td(nWEIV-ALEIV)
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
F-2
(6)
F+4
(6)
ns
GNF9
tc(nWE)
Cycle time, write cycle time
GNF10 td(nCSV-nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
GNF13 tw(nOEV)
Pulse duration, gpmc_oen_ren valid time
GNF14 tc(nOE)
Cycle time, read cycle time
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
H
I-2
M-2
(9)
(12)
(8)
I+4
(9)
ns
ns
K
(10)
ns
L
(11)
ns
M+4
(12)
ns
(1) A = (WEOffTime - WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) B = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(3) C = ((WEOnTime - ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - ADVExtraDelay)) * GPMC_FCLK
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) E = (WrCycleTime - WEOffTime * (TimeParaGranularity + 1) - 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) F = (ADVWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay - WEExtraDelay ) * GPMC_FCLK
(7) G = (CSWrOffTime - WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - WEExtraDelay ) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(10) K = (OEOffTime - OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) M = (CSRdOffTime - OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay - OEExtraDelay ) * GPMC_FCLK
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GPMC_FCLK
GNF1
GNF6
GNF2
GNF5
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF0
gpmc_wen
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
(1)
Figure 7-19. GPMC / NAND Flash - Command Latch Cycle Timing
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF6
GNF7
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
gpmc_ad[15:0]
GNF4
Address
GPMC_14
Figure 7-20. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
Figure 7-21. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
(1)
Figure 7-22. GPMC / NAND Flash - Data Write Cycle Timing
(1) In gpmc_csi, i = 0 to 7.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
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Virtual IO Timings Modes must be used to guaranteed some IO timings for GPMC. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See Table 7-30 Virtual Functions Mapping for GPMC for a definition of the Virtual modes.
Table 7-30 presents the values for DELAYMODE bitfield.
Table 7-30. Virtual Functions Mapping for GPMC
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
gpmc_cs6
N1
gpmc_advn_al
e
15
gpmc_advn_al
e
H3
gpmc_ad15
13
gpmc_ad15
L3
gpmc_ad6
13
gpmc_ad6
L5
gpmc_ad2
13
gpmc_ad2
E6
vin2a_d9
9
M3
gpmc_wen
15
gpmc_wen
H2
gpmc_ad14
13
gpmc_ad14
R3
gpmc_a13
15
gpmc_a13
N7
gpmc_a8
14
gpmc_a8
T2
gpmc_a14
15
gpmc_a14
L6
gpmc_ad4
13
gpmc_ad4
H4
gpmc_a26
15
gpmc_a26
M6
gpmc_ad0
13
gpmc_ad0
N2
gpmc_wait0
15
gpmc_wait0
F6
vin2a_d11
9
M2
gpmc_ad1
13
gpmc_ad1
J3
gpmc_ad13
13
gpmc_ad13
T6
gpmc_a2
14
gpmc_a2
gpmc_ad5
L4
gpmc_ad5
13
F5
vin2a_d8
9
T1
gpmc_cs0
15
G1
vin2a_hsync0
9
2
3
5
6
gpmc_wait1
gpmc_a2
gpmc_a23
14(1)
14(1)
gpmc_a25
gpmc_a20
gpmc_a23
gpmc_a26
gpmc_cs0
gpmc_a27
P6
gpmc_a4
14
gpmc_a4
N6
gpmc_ben0
15
gpmc_ben0
R5
gpmc_a6
14
gpmc_a6
U2
gpmc_a15
15
gpmc_a15
J2
gpmc_ad11
13
gpmc_ad11
gpmc_cs4
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Table 7-30. Virtual Functions Mapping for GPMC (continued)
BALL
244
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
U1
gpmc_a16
15
gpmc_a16
T9
gpmc_a1
14
gpmc_a1
J4
gpmc_a24
15
gpmc_a24
gpmc_a18
J7
gpmc_a23
15
gpmc_a23
gpmc_a17
L1
gpmc_ad8
13
gpmc_ad8
J1
gpmc_ad10
13
gpmc_ad10
H1
gpmc_ad12
13
gpmc_ad12
M7
gpmc_a20
15
gpmc_a20
D3
vin2a_d10
9
3
5
6
14(1)
14(1)
gpmc_a14
gpmc_a24
P1
gpmc_cs3
14
gpmc_cs3
M5
gpmc_oen_ren
15
gpmc_oen_ren
R4
gpmc_a9
14
gpmc_a9
gpmc_a1
H6
gpmc_cs1
15
gpmc_cs1
M1
gpmc_ad3
13
gpmc_ad3
gpmc_a22
L2
gpmc_ad7
13
gpmc_ad7
P5
gpmc_a7
14
gpmc_a7
T7
gpmc_a3
14
gpmc_a3
M4
gpmc_ben1
15
gpmc_ben1
gpmc_cs5
P7
gpmc_clk
15
gpmc_clk
gpmc_cs7
K6
gpmc_a22
15
gpmc_a22
P2
gpmc_cs2
15
gpmc_cs2
H7
vin2a_fld0
11
N9
gpmc_a10
14
gpmc_a10
P4
gpmc_a12
15
gpmc_a12
P3
gpmc_a17
15
gpmc_a17
R9
gpmc_a5
14
gpmc_a5
J5
gpmc_a21
15
gpmc_a21
gpmc_a15
H5
gpmc_a27
15
gpmc_a27
gpmc_a21
K2
gpmc_ad9
13
gpmc_ad9
K7
gpmc_a19
15
gpmc_a19
gpmc_a13
J6
gpmc_a25
15
gpmc_a25
gpmc_a19
R6
gpmc_a0
14
gpmc_a0
gpmc_a3
gpmc_wait1
gpmc_a16
gpmc_a27
gpmc_a18
gpmc_a0
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Table 7-30. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
GPMC_VIRTUAL1
MUXMODE
0
1
E1
vin2a_clk0
11
R2
gpmc_a18
15
gpmc_a18
P9
gpmc_a11
14
gpmc_a11
2
3
5
6
14(1)
14(1)
gpmc_a27
gpmc_a17
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(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
7.12 Timers
The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz
synchronized timer (COUNTER_32K) that have the following features:
• Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
• Interrupts generated on overflow, compare, and capture
• Free-running 32-bit upward counter
• Supported modes:
– Compare and capture modes
– Auto-reload mode
– Start-stop mode
• On-the-fly read/write register (while counting)
The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following
features:
• Free-running 32-bit upward counter
• On-the-fly read/write register (while counting)
• Reset upon occurrence of a timer overflow condition
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU
watchdog timer.
The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
NOTE
For additional information on the Timer Module, see the Device TRM.
7.13 Inter-Integrated Circuit Interface (I2C)
The device includes 6 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
NOTE
Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is
not supported.
NOTE
Inter-integrated circuit i (i=1 to 6) module is also referred to as I2Ci.
NOTE
For more information, see the Multimaster High-Speed I2C Controller section of the Device
TRM.
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Table 7-31, Table 7-32 and Figure 7-23 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-31. Timing Requirements for I2C Input Timings(1)
NO.
1
PARAMETER
STANDARD MODE
DESCRIPTION
MIN
FAST MODE
MAX
MIN
MAX
UNIT
tc(SCL)
Cycle time, SCL
10
2.5
µs
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
µs
3
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
4
0.6
µs
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
(2)
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
7
th(SCLL-SDAV)
Hold time, SDA valid after SCL low
0(3)
8
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
9
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300(3)
ns
10
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
300(3)
ns
11
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
300(3)
ns
12
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
300(3)
ns
13
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
(5)
Cb
100
3.45(4)
ns
0(3)
0.9(4)
1.3
µs
(5)
(5)
(5)
(5)
4
0.6
µs
0
Capacitive load for each bus line
µs
400
50
ns
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Table 7-32. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1)
NO.
PARAMETER
DESCRIPTION
1
tc(SCL)
Cycle time, SCL
2
tsu(SCLH-SDAL)
3
Cb = 100 pF MAX
MIN
MAX
Cb = 400 pF (2)
MIN
UNIT
MAX
0.294
0.588
µs
Set-up time, SCL high before
SDA low (for a repeated START
condition)
160
160
ns
th(SDAL-SCLL)
Hold time, SCL low after SDA
low (for a repeated START
condition)
160
160
ns
4
tw(SCLL)
LOW period of the SCLH clock
160
320
ns
5
tw(SCLH)
HIGH period of the SCLH clock
60
120
ns
6
tsu(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10
10
ns
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Table 7-32. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1) (continued)
NO.
PARAMETER
DESCRIPTION
Cb = 400 pF (2)
Cb = 100 pF MAX
MIN
MAX
(3)
7
th(SCLL-SDAV)
Hold time, SDA valid after SCL
low
0
13
tsu(SCLH-SDAH)
Setup time, SCL high before
SDA high (for a STOP condition)
160
14
tw(SP)
Pulse duration, spike (must be
suppressed)
15
Cb (2)
Capacitive load for SDAH and
SCLH lines
16
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
MIN
70
0
UNIT
MAX
(3)
150
ns
160
0
10
ns
0
10
ns
100
400
pF
400
400
pF
(1) I2C HS-Mode is only supported on I2C3/4/5/6. I2C HS-Mode is not supported on I2C1/2.
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
9
11
I2Ci_SDA
6
8
14
4
13
5
10
I2Ci_SCL
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_01
Figure 7-23. I2C Receive Timing
Table 7-33 and Figure 7-24 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-33. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
NO.
16
PARAMETER
DESCRIPTION
STANDARD MODE
MIN
MAX
FAST MODE
MIN
MAX
UNIT
tc(SCL)
Cycle time, SCL
10
2.5
µs
17
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
µs
18
th(SDAL-SCLL)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100
ns
22
th(SCLL-SDAV)
Hold time, SDA valid after SCL low (for I2C
bus devices)
23
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
248
0
4.7
3.45
0
1.3
0.9
µs
µs
Timing Requirements and Switching Characteristics
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Table 7-33. Switching Characteristics Over Recommended Operating Conditions for I2C Output
Timings(2) (continued)
NO.
PARAMETER
STANDARD MODE
DESCRIPTION
MIN
FAST MODE
MAX
MIN
MAX
UNIT
24
tr(SDA)
Rise time, SDA
1000
20 + 0.1Cb
300(3)
ns
25
tr(SCL)
Rise time, SCL
1000
20 + 0.1Cb
300(3)
ns
26
tf(SDA)
Fall time, SDA
300
20 + 0.1Cb
300(3)
ns
27
tf(SCL)
Fall time, SCL
300
20 + 0.1Cb
300(3)
ns
28
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
29
Cp
Capacitance for each I2C pin
(1) (3)
(1) (3)
(1) (3)
(1) (3)
4
0.6
µs
10
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, I2C5 and I2C6 use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
NOTE
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
24
26
I2Ci_SDA
21
23
19
28
20
25
I2Ci_SCL
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_02
Figure 7-24. I2C Transmit Timing
7.14 HDQ / 1-Wire Interface (HDQ1W)
The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to
communicate between the master and the slave. The protocols employ an asynchronous return to one
mechanism where, after any command, the line is pulled high.
NOTE
For more information, see the HDQ / 1-Wire section of the Device TRM.
Timing Requirements and Switching Characteristics
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7.14.1 HDQ / 1-Wire - HDQ Mode
Table 7-34 and Table 7-35 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-25, Figure 7-26, Figure 7-27 and Figure 7-28).
Table 7-34. HDQ/1-Wire Timing Requirements-HDQ Mode
NO.
MIN
MAX
UNIT
1
tCYCH
PARAMETER
Read bit window timing
DESCRIPTION
190
250
µs
2
tHW1
Read one data valid after HDQ low
32(2)
66(2)
µs
(2)
3
tHW0
Read zero data hold after HDQ low
70
4
tRSPS
Response time from HDQ slave device(1)
190
(2)
145
320
µs
µs
(1) Defined by software.
(2) If the HDQ slave device drives a logic-low state after tHW0 maximum, it can be interpreted as a break pulse. For more information see
"HDQ / 1-Wire Switching Characteristics - HDQ Mode" and the HDQ/1-Wire chapter of the TRM.
Table 7-35. HDQ / 1-Wire Switching Characteristics - HDQ Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
5
tB
Break timing
190
µs
6
tBR
Break recovery time
40
µs
7
tCYCD
Write bit windows timing
190
8
tDW1
Write one data valid after HDQ low
0.5
50
µs
9
tDW0
Write zero data hold after HDQ low
86
145
µs
tB
µs
tBR
HDQ
SPRS906_TIMING_HDQ1W_01
Figure 7-25. HDQ Break and Break Recovery Timing - HDQ Interface Writing to Slave
tCYCH
tHW0
tHW1
HDQ
SPRS906_TIMING_HDQ1W_02
Figure 7-26. Device HDQ Interface Bit Read Timing (Data)
tCYCD
tDW0
tDW1
HDQ
SPRS906_TIMING_HDQ1W_03
Figure 7-27. Device HDQ Interface Bit Write Timing (Command / Address or Data)
250
Timing Requirements and Switching Characteristics
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Command_byte_written
Data_byte_received
tRSPS
0_(LSB)
Break
1
6
1
7_(MSB)
0_(LSB)
6
HDQ
SPRS906_TIMING_HDQ1W_04
Figure 7-28. HDQ Communication Timing
7.14.2 HDQ/1-Wire-1-Wire Mode
Table 7-36 and Table 7-37 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-29, Figure 7-30 and Figure 7-31).
Table 7-36. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
MIN
MAX
UNIT
10
tPDH
PARAMETER
Presence pulse delay high
DESCRIPTION
15
60
µs
11
tPDL
Presence pulse delay low
60
240
µs
12
tRDV
Read data valid time
tLOWR
15
µs
13
tREL
Read data release time
0
45
µs
Table 7-37. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
MIN
MAX
UNIT
14
tRSTL
PARAMETER
Reset time low
DESCRIPTION
480
960
µs
15
tRSTH
Reset time high
480
16
tSLOT
Bit cycle time
60
120
µs
17
tLOW1
Write bit-one time
1
15
µs
18
tLOW0
Write bit-zero time(2)
60
120
µs
19
tREC
Recovery time
1
20
tLOWR
Read bit strobe time(1)
1
µs
µs
15
µs
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) tLOWR must be less than tSLOT.
tRSTH
tPDH
tRTSL
tPDL
1-WIRE
SPRS906_TIMING_HDQ1W_05
Figure 7-29. 1-Wire-Break (Reset)
tSLOT_and_tREC
tRDV_and_tREL
tLOWR
1-WIRE
SPRS906_TIMING_HDQ1W_06
Figure 7-30. 1-Wire-Read Bit (Data)
Timing Requirements and Switching Characteristics
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tSLOT_and_tREC
tLOW0
tLOW1
1-WIRE
SPRS906_TIMING_HDQ1W_07
Figure 7-31. 1-Wire-Write Bit-One Timing (Command / Address or Data)
7.15 Universal Asynchronous Receiver Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one
UART supports IrDA features. Each UART can be used for configuration and data exchange with a
number of external peripheral devices or interprocessor communication between devices
The UARTi (where i = 1 to 10) include the following features:
• 16C750 compatibility
• 64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
• Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
• Break character detection and generation
• Configurable data format:
– Data bit: 5, 6, 7, or 8 bits
– Parity bit: Even, odd, none
– Stop-bit: 1, 1.5, 2 bit(s)
• Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
• Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
• Only UART3 supports IrDA
NOTE
For more information, see the UART section of the Device TRM.
Table 7-38, Table 7-39 and Figure 7-32 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
Table 7-38. Timing Requirements for UART
NO.
PARAMETER
DESCRIPTION
MIN
(1)
MAX
UNIT
(1)
ns
1.05U(1)
ns
4
tw(RX)
Pulse width, receive data bit, 15/30/100pF high or low
0.96U
5
tw(CTS)
Pulse width, receive start bit, 15/30/100pF high or low
0.96U(1)
1.05U
td(RTS-TX)
Delay time, transmit start bit to transmit data
P(2)
ns
td(CTS-TX)
Delay time, receive start bit to transmit data
P(2)
ns
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
Table 7-39. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
15 pF
f(baud)
2
252
tw(TX)
Maximum programmable baud rate
MAX
30 pF
0.23
100 pF
0.115
Pulse width, transmit data bit, 15/30/100 pF high or low
UNIT
12
U - 2(1)
U + 2(1)
MHz
ns
Timing Requirements and Switching Characteristics
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Table 7-39. Switching Characteristics Over Recommended Operating Conditions for UART (continued)
NO.
3
PARAMETER
tw(RTS)
DESCRIPTION
Pulse width, transmit start bit, 15/30/100 pF high or low
MIN
MAX
UNIT
U - 2(1)
U + 2(1)
ns
(1) U = UART baud time = 1/programmed baud rate
3
2
UARTi_TXD
Start
Bit
Data Bits
5
4
UARTi_RXD
Start
Bit
Data Bits
SPRS906_TIMING_UART_01
Figure 7-32. UART Timing
7.16 Multichannel Serial Peripheral Interface (McSPI)
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
• Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– SPI configuration per channel. This means, clock definition, polarity enabling and word width
• Power management through wake-up capabilities
• Programmable timing control between chip select and external clock generation
• Built-in FIFO available for a single channel.
• Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
Timing Requirements and Switching Characteristics
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CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in
Table 7-42.
Table 7-40, Figure 7-33 and Figure 7-34 present Timing Requirements for McSPI - Master Mode.
Table 7-40. Timing Requirements for SPI - Master Mode (1)
NO.
PARAMETER
DESCRIPTION
MODE
(1) (2)
SM1
tc(SPICLK)
Cycle time, spi_sclk
SPI1/2/3/
4
SM2
tw(SPICLKL)
Typical Pulse duration, spi_sclk low
SM3
tw(SPICLKH)
Typical Pulse duration, spi_sclk high
SM4
tsu(MISO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
(1)
MIN
MAX
ns
0.5*P-1
ns
0.5*P-1
ns
3.5
ns
20.8
(4)
(1)
(4)
(1)
SM5
th(SPICLK-MISO)
Hold time, spi_d[x] valid after spi_sclk active edge
SM6
td(SPICLK-SIMO)
Delay time, spi_sclk active edge to spi_d[x] transition
3.7
(1)
SM7
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
SM8
td(CS-SPICLK)
Delay time, spi_cs[x] active to spi_sclk first edge (1)
UNIT
(3)
ns
SPI1
-3.57
4.1
ns
SPI2
-3.9
3.6
ns
SPI3
-4.9
4.7
SPI4
-4.3
4.5
MASTER
_PHA0
B-4.2 (6)
ns
MASTER
_PHA1
A-4.2 (7)
ns
MASTER
_PHA0
A-4.2 (7)
ns
MASTER
_PHA1
B-4.2 (6)
ns
5
ns
(5)
(5)
SM9
td(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive
(1)
(5)
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
254
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
spim_sclk(OUT)
SM2
SM9
POL=0
SM3
SM1
SM2
POL=1
spim_sclk(OUT)
SM7
SM6
Bit n-1
spim_d(OUT)
SM6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
spim_sclk(OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
spim_sclk(OUT)
SM6
Bit n-1
spim_d(OUT)
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRS906_TIMING_McSPI_01
Figure 7-33. McSPI - Master Mode Transmit
Timing Requirements and Switching Characteristics
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
spim_sclk(OUT)
SM2
SM9
POL=0
SM3
SM1
SM2
POL=1
spim_sclk(OUT)
SM5
SM5
spim_d(IN)
SM4
SM4
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
spim_sclk(OUT)
SM3
SM9
POL=0
SM1
SM2
SM3
POL=1
spim_sclk(OUT)
SM5
SM4
SM4
Bit n-1
spim_d(IN)
SM5
Bit n-2
Bit n-3
Bit 1
Bit 0
SPRS906_TIMING_McSPI_02
Figure 7-34. McSPI - Master Mode Receive
Table 7-41, Figure 7-35 and Figure 7-36 present Timing Requirements for McSPI - Slave Mode.
Table 7-41. Timing Requirements for SPI - Slave Mode
PARAMETER
DESCRIPTION
SS1 (1)
NO.
tc(SPICLK)
Cycle time, spi_sclk
MODE
MIN
SS2 (1)
tw(SPICLKL)
Typical Pulse duration, spi_sclk low
0.45*P
(4)
ns
SS3
(1)
tw(SPICLKH)
Typical Pulse duration, spi_sclk high
0.45*P
(4)
ns
SS4
(1)
62.5
tsu(SIMO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge
5
th(SPICLK-SIMO)
Hold time, spi_d[x] valid after spi_sclk active edge
5
SS6 (1)
td(SPICLK-SOMI)
Delay time, spi_sclk active edge to mcspi_somi transition
SS7
256
td(CS-SOMI)
Delay time, spi_cs[x] active edge to mcspi_somi transition
UNIT
ns
(3)
SS5 (1)
(5)
MAX
(2)
ns
ns
SPI1/2/3
2
26.6
ns
SPI4
2
20.1
ns
20.95
ns
Timing Requirements and Switching Characteristics
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Table 7-41. Timing Requirements for SPI - Slave Mode (continued)
NO.
SS8 (1)
SS9
(1)
PARAMETER
DESCRIPTION
tsu(CS-SPICLK)
Setup time, spi_cs[x] valid before spi_sclk first edge
MODE
th(SPICLK-CS)
Hold time, spi_cs[x] valid after spi_sclk last edge
MIN
MAX
UNIT
5
ns
SPI1/2
5
ns
SPI3
7.5
ns
SPI4
6
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS2
SS1
SS3
POL=1
spim_sclk(IN)
SS7
SS6
Bit n-1
spim_d(OUT)
SS6
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS3
SS1
SS2
POL=1
spim_sclk(IN)
SS6
spim_d(OUT)
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRS906_TIMING_McSPI_03
Figure 7-35. McSPI - Slave Mode Transmit
Timing Requirements and Switching Characteristics
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PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS2
SS1
SS3
POL=1
spim_sclk(IN)
SS5
SS4
SS4
SS5
Bit n-1
spim_d(IN)
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
spim_sclk(IN)
SS3
SS9
POL=0
SS3
SS1
SS2
POL=1
spim_sclk(IN)
SS4
SS5
SS4
SS5
Bit n-1
spim_d(IN)
Bit n-2
Bit n-3
Bit 1
Bit0
SPRS906_TIMING_McSPI_04
Figure 7-36. McSPI - Slave Mode Receive
In Table 7-42 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
Table 7-42. McSPI3/4 IOSETs
SIGNALS
IOSET1
IOSET2
IOSET3
BALL
MUX
BALL
MUX
spi3_cs0
D11
8
V9
7
spi3_cs1
B11
8
AC3
1
spi3_cs2
F11
spi3_cs3
A10
spi3_d0
C11
8
W9
spi3_d1
B10
8
spi3_sclk
E11
8
BALL
IOSET4
IOSET5
MUX
BALL
MUX
BALL
MUX
A12
3
D17
2
AC9
1
E14
3
B11
8
AC3
1
8
F11
8
F11
8
8
A10
8
A10
8
7
B13
3
G16
2
AC6
1
Y1
7
A11
3
A21
2
AC7
1
V2
7
B12
3
C18
2
AC4
1
7
AA4
2
AB5
1
McSPI3
McSPI4
spi4_cs0
258
P9
8
F3
8
U6
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Table 7-42. McSPI3/4 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
spi4_cs1
P4
spi4_cs2
R3
spi4_cs3
IOSET3
BALL
MUX
8
P4
8
R3
T2
8
spi4_d0
N9
spi4_d1
R4
spi4_sclk
N7
IOSET4
BALL
MUX
8
Y1
8
W9
T2
8
8
F2
8
G6
8
G1
IOSET5
BALL
MUX
BALL
MUX
8
Y1
8
W9
8
Y1
8
8
W9
V9
8
8
V9
8
V9
8
8
V6
8
U7
7
AB3
2
AB8
1
7
AB9
2
AD6
8
V7
1
7
AA3
2
AC8
1
7.17 Quad Serial Peripheral Interface (QSPI)
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
• Programmable clock divider
• Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
• 4 external chip select signals
• Support for 3-, 4- or 6-pin SPI interface
• Programmable CS_N to DOUT delay from 0 to 3 DCLKs
• Programmable signal polarities
• Programmable active clock edge
• Software controllable interface allowing for any type of SPI transfer
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-43 and Table 7-44 Present Timing and Switching Characteristics for Quad SPI Interface.
Timing Requirements and Switching Characteristics
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Table 7-43. Switching Characteristics for QSPI
NO.
PARAMETER
DESCRIPTION
MODE
MIN
Q1
tc(SCLK)
Cycle time, sclk
Default Timing Mode,
Clock Mode 0
11.71
MAX
UNIT
ns
Default Timing Mode,
Clock Mode 3
20.8
ns
Q2
tw(SCLKL)
Pulse duration, sclk low
Y*P-1
ns
Q3
tw(SCLKH)
Pulse duration, sclk high
Y*P-1
ns
Q4
td(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0
(1)
(1)
Default Timing Mode
-M*P1.6 (2)
M*P+2.
6 (2) (3)
ns
(3)
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
Default Timing Mode
N*P-1.6
(2) (3)
N*P+2.
6 (2) (3)
ns
Q6
td(SCLK-D0)
Delay time, sclk falling edge to d[0] transition
Default Timing Mode
-1.6
2.6
ns
Q7
tena(CS-D0LZ)
Enable time, cs active edge to d[0] driven (lo-z)
-P-3.5
-P+2.5
ns
Q8
tdis(CS-D0Z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
-P-2.5
-P+2.0
ns
Q9
td(SCLK-D0)
Delay time, sclk first falling edge to first d[0] transition
-1.6
2.6
ns
PHA=0 Only, Default
Timing Mode
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
PHA=1
cs
Q5
Q1
POL=1
Q4
Q3
Q2
sclk
Q15
Q14
Q7
d[0]
d[3:1]
Q6
Q6
Command
Bit n-1
Command
Bit n-2
Q12 Q13
Read Data
Read Data
Bit 1
Bit 0
Q14
Q15
Q12 Q13
Read Data
Read Data
Bit 1
Bit 0
SPRS85v_TIMING_OSPI1_01
Figure 7-37. QSPI Read (Clock Mode 3)
260
Timing Requirements and Switching Characteristics
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PHA=0
cs
Q5
Q4
Q1
Q2
POL=0
Q3
sclk
POL=0
rtclk
Q7
d[0]
Q6
Q9
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
Q12 Q13
Read Data
Bit 1
d[3:1]
Q12 Q13
Read Data
Bit 0
SPRS85v_TIMING_OSPI1_02
Figure 7-38. QSPI Read (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-44. Timing Requirements for QSPI(3)(2)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
Q2
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Default Timing Mode,
Clock Mode 0
4.6
ns
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
Default Timing Mode,
Clock Mode 3
12.3
ns
th(RTCLK-D)
Hold time, d[3:0] valid after falling rtclk edge
Default Timing Mode,
Clock Mode 0
-0.1
ns
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
Default Timing Mode,
Clock Mode 3
0.1
ns
Q14
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk
edge
Default Timing Mode,
Clock Mode 3
12.3-P
ns
Q15
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk
edge
Default Timing Mode,
Clock Mode 3
0.1+P
ns
Q13
MAX
(1)
(1)
Timing Requirements and Switching Characteristics
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UNIT
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
PHA=1
cs
Q5
POL=1
Q1
Q4
Q3
Q2
sclk
Q7
d[0]
Command
Bit n-1
Write Data
Bit 1
Command
Bit n-2
Q8
Q6
Q6
Q6
Q6
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_03
Figure 7-39. QSPI Write (Clock Mode 3)
PHA=0
cs
Q5
Q4
POL=0
Q1
Q2
Q3
sclk
Q7
d[0]
Q9
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q8
Q6
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 7-40. QSPI Write (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
262
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for QSPI. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-45 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
Table 7-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-45. Manual Functions Mapping for QSPI
BALL
BALL NAME
QSPI1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
T7
gpmc_a3
0
0
CFG_GPMC_A3_OUT
qspi1_cs2
1
P6
gpmc_a4
0
0
CFG_GPMC_A4_OUT
qspi1_cs3
R3
gpmc_a13
0
0
CFG_GPMC_A13_IN
qspi1_rtclk
T2
gpmc_a14
2247
1186
CFG_GPMC_A14_IN
qspi1_d3
U2
gpmc_a15
2176
1197
CFG_GPMC_A15_IN
qspi1_d2
U1
gpmc_a16
2229
1268
CFG_GPMC_A16_IN
qspi1_d0
U1
gpmc_a16
0
0
CFG_GPMC_A16_OUT
qspi1_d0
P3
gpmc_a17
2251
1217
CFG_GPMC_A17_IN
qspi1_d1
R2
gpmc_a18
0
0
CFG_GPMC_A18_OUT
qspi1_sclk
P2
gpmc_cs2
0
0
CFG_GPMC_CS2_OUT
qspi1_cs0
P1
gpmc_cs3
0
0
CFG_GPMC_CS3_OUT
qspi1_cs1
7.18 Multichannel Audio Serial Port (McASP)
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
• McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
• McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
NOTE
For more information, see the Serial Communication Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-46, Table 7-47, Table 7-48 and Figure 7-41 present Timing Requirements for McASP1 to
McASP8.
Timing Requirements and Switching Characteristics
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Table 7-46. Timing Requirements for McASP1(1)
NO.
1
PARAMETER
DESCRIPTION
tc(AHCLKRX)
Cycle time, AHCLKR/X
MODE
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
7
8
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
tsu(AXR-ACLK)
Setup time, AXR input valid before ACLKR/X
th(ACLK-AXR)
Hold time, AXR input valid after ACLKR/X
MAX
20
2
6
MIN
UNIT
ns
(2)
0.35P
ns
20
ns
0.5R - 3
ns
ACLKR/X int
20.5
ns
ACLKR/X ext
in
ACLKR/X ext
out
4
ns
(3)
ACLKR/X int
-1
ns
ACLKR/X ext
in
ACLKR/X ext
out
1.7
ns
ACLKR/X int
21.6
ns
ACLKR/X ext
in
ACLKR/X ext
out
11.5
ns
ACLKR/X int
-1
ns
ACLKR/X ext
in
ACLKR/X ext
out
1.8
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-47. Timing Requirements for McASP2(1)
NO.
PARAMETER
DESCRIPTION
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
5
264
tw(ACLKRX)
tsu(AFSRX-ACLK)
Pulse duration, ACLKR/X high or low
Setup time, AFSR/X input valid before
ACLKR/X
MODE
MIN
MAX
UNIT
20
ns
0.35P
ns
(2)
Any Other Conditions
20
ns
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
12.5
ns
Any Other Conditions
0.5R - 3
ns
ACLKX/AFSX (In Sync Mode),
ACLKR/AFSR (In Async Mode),
and AXR are all inputs "80M"
Virtual IO Timing Modes
0.38R
ns
(3)
(3)
ACLKR/X int
20.3
ns
ACLKR/X ext in
ACLKR/X ext out
4.5
ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
Timing Requirements and Switching Characteristics
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Table 7-47. Timing Requirements for McASP2(1) (continued)
NO.
PARAMETER
DESCRIPTION
6
th(ACLK-AFSRX)
Hold time, AFSR/X input valid after ACLKR/X
7
8
tsu(AXR-ACLK)
th(ACLK-AXR)
MODE
MIN
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
1.8
ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
Setup time, AXR input valid before ACLKR/X
MAX
UNIT
ACLKR/X int
21.1
ns
ACLKR/X ext in
ACLKR/X ext out
4.5
ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
-1
ns
ACLKR/X ext in
ACLKR/X ext out
1.8
ns
ACLKR/X ext in
ACLKR/X ext out "80M" Virtual
IO Timing Modes
3
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-48. Timing Requirements for McASP3/4/5/6/7/8(1)
NO.
PARAMETER
DESCRIPTION
1
tc(AHCLKRX)
Cycle time, AHCLKR/X
2
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
3
tc(ACLKRX)
Cycle time, ACLKR/X
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
5
tsu(AFSRX-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
6
th(ACLK-AFSRX)
tsu(AXR-ACLK)
8
th(ACLK-AXR)
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
Hold time, AXR input valid after ACLKX
MODE
MIN
MAX
UNIT
20
ns
0.35P
ns
20
ns
0.5R - 3
ns
(2)
(3)
ACLKR/X int
19.7
ns
ACLKR/X ext in
ACLKR/X ext out
5.6
ns
ACLKR/X int
-1.1
ns
ACLKR/X ext in
ACLKR/X ext out
2.5
ns
ACLKX int
(ASYNC=0)
20.3
ns
ACLKR/X ext in
ACLKR/X ext out
5.1
ns
ACLKX int
(ASYNC=0)
-0.8
ns
ACLKR/X ext in
ACLKR/X ext out
2.5
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
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(3) R = ACLKR/X period in ns.
2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (CLKRP = CLKXP = 0) (A)
ACLKR/X (CLKRP = CLKXP = 1) (B)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0
A1
A30 A31 B0
B1
B30 B31 C0 C1
C2 C3
C31
SPRS906_TIMING_McASP_01
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
Figure 7-41. McASP Input Timing
Table 7-49, Table 7-50, Table 7-51 and Figure 7-42 present Switching Characteristics Over
Recommended Operating Conditions for McASP1 to McASP8.
Table 7-49. Switching Characteristics Over Recommended Operating Conditions for McASP1(1)
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, ACLKR/X
266
MODE
MIN
MAX
UNIT
20
ns
0.5P 2.5 (2)
ns
20
ns
Timing Requirements and Switching Characteristics
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Table 7-49. Switching Characteristics Over Recommended Operating Conditions for
McASP1(1) (continued)
NO.
PARAMETER
DESCRIPTION
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
MAX
UNIT
0.5P 2.5 (3)
ns
ACLKR/X int
-0.9
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
23.1
ns
ACLKR/X int
-1.4
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
24.2
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-50. Switching Characteristics Over Recommended Operating Conditions for McASP2
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, ACLKR/X
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
(1)
MAX
UNIT
20
ns
0.5P 2.5 (2)
ns
20
ns
0.5P 2.5 (3)
ns
ACLKR/X int
-1
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
23.2
ns
ACLKR/X int
-1.3
6
ns
ACLKR/X ext in
ACLKR/X ext out
2
23.7
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
Table 7-51. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1)
NO.
PARAMETER
DESCRIPTION
9
tc(AHCLKRX)
Cycle time, AHCLKR/X
10
tw(AHCLKRX)
Pulse duration, AHCLKR/X high or low
11
tc(ACLKRX)
Cycle time, ACLKR/X
12
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
MODE
MIN
MAX
ns
0.5P 2.5 (2)
ns
20
ns
0.5P 2.5 (3)
ns
Timing Requirements and Switching Characteristics
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UNIT
20
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Table 7-51. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1) (continued)
NO.
PARAMETER
DESCRIPTION
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
MODE
MIN
MAX
UNIT
ACLKR/X int
-0.5
6
ns
ACLKR/X ext in
ACLKR/X ext out
1.9
24.5
ns
ACLKR/X int
-1.4
7.1
ns
ACLKR/X ext in
ACLKR/X ext out
1.1
24.2
ns
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
268
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (CLKRP = CLKXP = 1) (A)
ACLKR/X (CLKRP = CLKXP = 0) (B)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
13
13
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/T ransmit)
A0
A1
A30 A31 B0 B1
B30 B31 C0
C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A.
B.
For CLKRP = CLKXP =
receiver is configured for
For CLKRP = CLKXP =
receiver is configured for
1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
rising edge (to shift data in).
0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
falling edge (to shift data in).
Figure 7-42. McASP Output Timing
Table 7-52 through Table 7-59 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see
Figure 7-43 through Figure 7-50).
Table 7-52. Virtual Mode Case Details for McASP1
No.
CASE
CASE Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
COIFOI
CLKX / FSX: Output
CLKR / FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL2_ASYNC_RX
See Figure 7-43
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Table 7-52. Virtual Mode Case Details for McASP1 (continued)
No.
CASE
CASE Description
Virtual Mode Settings
Signals
2
COIFIO
Notes
Virtual Mode Value
CLKX / FSR: Output
CLKR / FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP1_VIRTUAL2_ASYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
3
CIOFIO
CLKR / FSR: Output
CLKX / FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
4
CIOFOI
CLKR / FSX: Output
CLKX / FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL2_ASYNC_RX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX: Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output CLKX:
Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP1_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP1_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP1_VIRTUAL1_SYNC_RX
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
CO-FI-
CLKX: Output FSX:
Input
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-53. Virtual Mode Case Details for McASP2
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
COIFOI
CLKX / FSX:
Output CLKR /
FSR: Input
3
4
COIFIO
CIOFIO
CIOFOI
See Figure 7-43
(1)
AXR(Inputs)/CLKR/FSR
AXR(Inputs)/CLKR/FSR
2
Default (No Virtual Mode)(1)
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
MCASP2_VIRTUAL4_ASYNC_RX_80M (2)
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP2_VIRTUAL2_ASYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP2_VIRTUAL2_ASYNC_RX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP2_VIRTUAL2_ASYNC_RX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
MCASP2_VIRTUAL3_SYNC_RX
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
MCASP2_VIRTUAL3_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP2_VIRTUAL3_SYNC_RX(1)
AXR(Inputs)/CLKX/FSX
MCASP2_VIRTUAL3_SYNC_RX(1)
AXR(Inputs)/CLKX/FSX
MCASP2_VIRTUAL1_SYNC_RX_80M(2)
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
CO-FI-
CLKX: Output
FSX: Input
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
(1) Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are
bidirectional).
(2) Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.
270
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Table 7-54. Virtual Mode Case Details for McASP3
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX /
FSX: Output
CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKX /
FSR: Output
CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKR /
FSR: Output
CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
CLKR /
FSX: Output
CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FOCI-FOCI-FICO-FI-
CLKX /
FSX: Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP3_VIRTUAL2_SYNC_RX
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-55. Virtual Mode Case Details for McASP4
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP4_VIRTUAL1_SYNC_RX
7
CI-FI-
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
Timing Requirements and Switching Characteristics
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Table 7-55. Virtual Mode Case Details for McASP4 (continued)
No.
8
CASE
CO-FI-
CASE
Description
CLKX: Output
FSX: Input
Virtual Mode Settings
Notes
Signals
Virtual Mode Value
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-50
Table 7-56. Virtual Mode Case Details for McASP5
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP5_VIRTUAL1_SYNC_RX
CLKX: Output
FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
7
8
CI-FICO-FI-
Default (No Virtual Mode)
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-57. Virtual Mode Case Details for McASP6
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
272
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
See Figure 7-47
Timing Requirements and Switching Characteristics
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Table 7-57. Virtual Mode Case Details for McASP6 (continued)
No.
6
CASE
CI-FO-
CASE
Description
Virtual Mode Settings
Signals
Virtual Mode Value
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP6_VIRTUAL1_SYNC_RX
8
CO-FI-
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Notes
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-58. Virtual Mode Case Details for McASP7
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP7_VIRTUAL2_SYNC_RX
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
CO-FI-
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
Table 7-59. Virtual Mode Case Details for McASP8
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Notes
Virtual Mode Value
IP Mode : ASYNC
1
2
3
COIFOI
COIFIO
CIOFIO
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-43
See Figure 7-44
See Figure 7-45
Timing Requirements and Switching Characteristics
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Table 7-59. Virtual Mode Case Details for McASP8 (continued)
No.
4
CASE
CIOFOI
CASE
Description
Virtual Mode Settings
CLKR / FSX:
Output CLKX
/ FSR: Input
Notes
Signals
Virtual Mode Value
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-46
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
6
CI-FO-
FSX: Output
CLKX: Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
Input
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
CLKX:
Output FSX:
Input
AXR(Outputs)/CLKX/FSX
Default (No Virtual Mode)
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
8
CO-FI-
McASP
See Figure 7-47
See Figure 7-48
See Figure 7-49
See Figure 7-50
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_01
Figure 7-43. McASP1-8 COIFOI - ASYNC Mode
274
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McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_02
Figure 7-44. McASP1-8 COIFIO - ASYNC Mode
McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_03
Figure 7-45. McASP1-8 CIOFIO - ASYNC Mode
Timing Requirements and Switching Characteristics
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SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_04
Figure 7-46. McASP1-8 CIOFOI - ASYNC Mode
McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_05
Figure 7-47. McASP1-8 CO-FO- - SYNC Mode
276
Timing Requirements and Switching Characteristics
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McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_06
Figure 7-48. McASP1-8 CI-FO- - SYNC Mode
McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_07
Figure 7-49. McASP1-8 CI-FI- - SYNC Mode
Timing Requirements and Switching Characteristics
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SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_08
Figure 7-50. McASP1-8 CO-FI- - SYNC Mode
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
278
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP1. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See Table 7-60 Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.
Table 7-60 presents the values for DELAYMODE bitfield.
Table 7-60. Virtual Functions Mapping for McASP1
BALL
BALL NAME
Delay Mode Value
MUXMODE
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
0
C14
mcasp1_aclkx
15
14
mcasp1_aclkx
E21
gpio6_14
14
13
A13
mcasp1_axr13
15
14
mcasp1_axr13
E12
mcasp1_axr4
14
13
mcasp1_axr4
B26
xref_clk2
14
13
A11
mcasp1_axr9
15
14
D12
mcasp1_axr7
14
13
mcasp1_axr7
E14
mcasp1_axr12
15
14
mcasp1_axr12
F21
gpio6_16
14
13
mcasp1_axr10
mcasp1_axr9
1
2
3
mcasp1_axr8
mcasp1_axr6
mcasp1_axr9
F20
gpio6_15
14
13
C23
xref_clk3
14
13
C12
mcasp1_axr6
14
13
mcasp1_axr6
B13
mcasp1_axr10
15
14
mcasp1_axr10
J14
mcasp1_fsr
N/A
14
mcasp1_fsr
B12
mcasp1_axr8
15
14
mcasp1_axr8
A12
mcasp1_axr11
15
14
mcasp1_axr11
G13
mcasp1_axr2
14
13
mcasp1_axr2
D14
mcasp1_fsx
15
14
mcasp1_fsx
G14
mcasp1_axr14
15
14
mcasp1_axr14
F14
mcasp1_axr15
15
14
mcasp1_axr15
F12
mcasp1_axr1
15
14
mcasp1_axr1
B14
mcasp1_aclkr
N/A
14
mcasp1_aclkr
mcasp1_axr5
mcasp1_axr7
F13
mcasp1_axr5
14
13
E17
xref_clk1
15
14
G12
mcasp1_axr0
15
14
mcasp1_axr0
J11
mcasp1_axr3
14
13
mcasp1_axr3
D18
xref_clk0
15
14
mcasp1_axr5
mcasp1_axr4
mcasp1_ahclkx
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP2. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See Table 7-61 Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.
Table 7-61 presents the values for DELAYMODE bitfield.
Table 7-61. Virtual Functions Mapping for McASP2
BALL
BALL NAME
Delay Mode Value
MUXMODE
MCASP2_VIRTUAL1
_SYNC_RX_80M
MCASP2_VIRTUAL2
_ASYNC_RX
MCASP2_VIRTUAL3
_SYNC_RX
MCASP2_VIRTUAL4
_ASYNC_RX_80M
0
B19
mcasp3_axr0
15
14
10
9
B17
mcasp2_axr6
14
13
12
11
mcasp2_axr6
B16
mcasp2_axr5
14
13
12
11
mcasp2_axr5
A18
mcasp2_fsx
15
14
10
9
mcasp2_fsx
B26
xref_clk2
12
11
10
9
1
2
mcasp2_axr1
4
mcasp2_axr1
0
A16
mcasp2_axr3
15
14
10
9
mcasp2_axr3
E15
mcasp2_aclkr
N/A
14
N/A
13
mcasp2_aclkr
B18
mcasp3_aclkx
15
14
10
9
A19
mcasp2_aclkx
15
14
10
9
mcasp2_aclkx
mcasp2_axr7
mcasp2_axr1
2
A17
mcasp2_axr7
14
13
12
11
C23
xref_clk3
12
11
10
9
C17
mcasp3_axr1
15
14
10
8
mcasp2_axr1
5
F15
mcasp3_fsx
15
14
10
9
mcasp2_axr1
3
C15
mcasp2_axr2
15
14
10
9
mcasp2_axr2
D15
mcasp2_axr4
14
13
12
11
mcasp2_axr4
A20
mcasp2_fsr
N/A
14
N/A
13
mcasp2_fsr
E17
xref_clk1
10
9
8
6
A15
mcasp2_axr1
14
13
12
11
mcasp2_axr1
B15
mcasp2_axr0
14
13
12
11
mcasp2_axr0
D18
xref_clk0
10
9
8
6
280
Timing Requirements and Switching Characteristics
3
mcasp2_axr1
1
mcasp2_axr9
mcasp2_ahclkx
mcasp2_axr8
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP3/4/5/6/7/8. See Table 7-2 Modes Summary for a list of IO
timings requiring the use of Virtual IO Timings Modes. See Table 7-62 Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the
Virtual modes.
Table 7-62 presents the values for DELAYMODE bitfield.
Table 7-62. Virtual Functions Mapping for McASP3/4/5/6/7/8
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
MCASP3_VIRTUAL2_SYNC_RX
A16
mcasp2_axr3
8
B18
mcasp3_aclkx
8
mcasp3_aclkx
mcasp3_axr3
B19
mcasp3_axr0
8
mcasp3_axr0
C17
mcasp3_axr1
6
mcasp3_axr1
F15
mcasp3_fsx
8
mcasp3_fsx
C15
mcasp2_axr2
8
A21
mcasp4_fsx
14
mcasp4_fsx
mcasp4_fsr
C18
mcasp4_aclkx
14
mcasp4_aclkx
mcasp4_aclkr
G16
mcasp4_axr0
14
mcasp4_axr0
D17
mcasp4_axr1
14
mcasp4_axr1
F13
mcasp1_axr5
12
mcasp4_axr3
E12
mcasp1_axr4
12
mcasp4_axr2
AA3
mcasp5_aclkx
14
mcasp5_aclkx
mcasp5_aclkr
AB9
mcasp5_fsx
14
mcasp5_fsx
mcasp5_fsr
AA4
mcasp5_axr1
14
mcasp5_axr1
C12
mcasp1_axr6
12
AB3
mcasp5_axr0
14
D12
mcasp1_axr7
12
G13
mcasp1_axr2
12
mcasp6_axr2
J11
mcasp1_axr3
12
mcasp6_axr3
B13
mcasp1_axr10
10
mcasp6_aclkx
A11
mcasp1_axr9
10
mcasp6_axr1
B12
mcasp1_axr8
10
mcasp6_axr0
A12
mcasp1_axr11
10
mcasp6_fsx
mcasp3_aclkr
mcasp3_fsr
mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
mcasp5_axr2
mcasp5_axr0
mcasp5_axr3
MCASP6_VIRTUAL1_SYNC_RX
mcasp6_aclkr
mcasp6_fsr
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Table 7-62. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
MCASP7_VIRTUAL2_SYNC_RX
E14
mcasp1_axr12
10
mcasp7_axr0
F14
mcasp1_axr15
10
mcasp7_fsx
mcasp7_fsr
G14
mcasp1_axr14
10
mcasp7_aclkx
mcasp7_aclkr
A13
mcasp1_axr13
10
mcasp7_axr1
B14
mcasp1_aclkr
13
mcasp7_axr2
J14
mcasp1_fsr
13
mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
282
D15
mcasp2_axr4
10
A17
mcasp2_axr7
10
mcasp8_fsx
mcasp8_fsr
B17
mcasp2_axr6
10
mcasp8_aclkx
mcasp8_aclkr
A20
mcasp2_fsr
12
mcasp8_axr3
B16
mcasp2_axr5
10
mcasp8_axr1
E15
mcasp2_aclkr
12
mcasp8_axr2
Timing Requirements and Switching Characteristics
mcasp8_axr0
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7.19 Universal Serial Bus (USB)
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
• USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
• USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
• USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
NOTE
For more information, see the SuperSpeed USB DRD section of the Device TRM.
7.19.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
• USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
7.19.2 USB2 PHY
The USB2 interface supports the following applications:
• USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
7.19.3 USB3 DRD ULPI-SDR-Slave Mode-12-pin Mode
TheUSB3 DRD interfaces support the following application:
• USB ULPI port: this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+
v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum
frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit).
NOTE
The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4.
Table 7-63, Table 7-64 and Figure 7-51 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 7-63. Timing Requirements for ULPI SDR Slave Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
US1
tc(clk)
Cycle time, usb_ulpi_clk period
16.66
ns
US5
tsu(ctrlV-clkH)
Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk
rising edge
6.73
ns
US6
th(clkH-ctrlV)
Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk
rising edge
-0.41
ns
US7
tsu(dV-clkH)
Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge
6.73
ns
US8
th(clkH-dV)
Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge
-0.41
ns
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Table 7-64. Switching Characteristics for ULPI SDR Slave Mode
MIN
MAX
UNIT
US4
NO.
td(clkH-stpV)
PARAMETER
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
DESCRIPTION
0.44
8.35
ns
US9
td(clkL-doV)
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
0.44
8.35
ns
US1
US2
US3
usbk_ulpi_clk
US4
US4
usbk_ulpi_stp
US6
US5
usbk_ulpi_dir_&_nxt
US7
US9
US8
usbk_ulpi_d[7:0]
Data_IN
US9
Data_OUT
SPRS906_TIMING_USB_01
Figure 7-51. HS USB3 ULPI -SDR-Slave Mode-12-pin Mode
In Table 7-65 are presented the specific groupings of signals (IOSET) for use with USB3 signals.
Table 7-65. USB3 IOSETs
SIGNALS
IOSET2
IOSET3
BALL
MUX
BALL
MUX
AC5
4
W2
6
usb3_ulpi_d6
AB4
4
Y2
6
usb3_ulpi_d5
AD4
4
V3
6
usb3_ulpi_d4
AC4
4
V4
6
usb3_ulpi_d3
AC7
4
V5
6
usb3_ulpi_d2
AC6
4
U5
6
usb3_ulpi_d1
AC9
4
U6
6
usb3_ulpi_d7
usb3_ulpi_d0
AC3
4
V6
6
usb3_ulpi_nxt
AC8
4
U7
6
usb3_ulpi_dir
AD6
4
V7
6
usb3_ulpi_stp
AB8
4
V9
6
usb3_ulpi_clk
AB5
4
W9
6
7.20 Serial Advanced Technology Attachment (SATA)
The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:
• Gen2i, Gen2m, Gen2x: 3Gbps.
• Gen1i, Gen1m, Gen1x: 1.5Gbps.
NOTE
For more information, see the SATA Controller section of the Device TRM.
7.21 Peripheral Component Interconnect Express (PCIe)
284
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The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
• 16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
• Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
• Single virtual channel (VC0), single traffic class (TC0)
• Single function in end-point mode
• Automatic width and speed negotiation
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
• All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0
NOTE
For more information, see the PCIe Controller section of the Device TRM.
7.22 Controller Area Network Interface (DCAN)
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
NOTE
For more information, see the DCAN section of the Device TRM.
Timing Requirements and Switching Characteristics
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NOTE
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
Table 7-66, Table 7-67 and Figure 7-52 present timing and switching characteristics for DCANx Interface.
Table 7-66. Timing Requirements for DCANx Receive(1)
NO.
1
PARAMETER
DESCRIPTION
MIN
f(baud)
Maximum programmable baud rate
tw(DCANRX)
Pulse duration, receive data bit (DCANx_RX)
NOM
H - 15
MAX
UNIT
1
Mbps
H + 15
ns
(1) H = period of baud rate, 1/programmed baud rate.
Table 7-67. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
2
PARAMETER
DESCRIPTION
f(baud)
Maximum programmable baud rate
tw(DCANTX)
Pulse duration, transmit data bit (DCANx_TX)
MIN
H - 15
(1)
MAX
UNIT
1
Mbps
H + 15
ns
(1) H = period of baud rate, 1/programmed baud rate.
1
DCANx_RX
2
DCANx_TX
SPRS906_TIMING_DCAN_01
Figure 7-52. DCANx Timings
7.23 Ethernet Interface (GMAC_SW)
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
NOTE
For more information, see the Ethernet Subsystem section of the Device TRM.
NOTE
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-72, Table 7-75, Table 780 and Table 7-87.
286
Timing Requirements and Switching Characteristics
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CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-68 and Figure 7-53 present timing requirements for MIIn in receive operation.
7.23.1 GMAC MII Timings
Table 7-68. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
1
tc(RX_CLK)
Cycle time, miin_rxclk
2
3
4
tw(RX_CLKH)
tw(RX_CLKL)
tt(RX_CLK)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
Transition time, miin_rxclk
SPEED
MIN
MAX
UNIT
10 Mbps
400
100 Mbps
40
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
3
ns
100 Mbps
3
ns
ns
4
1
3
2
miin_rxclk
4
SPRS906_TIMING_GMAC_MIIRXCLK_01
Figure 7-53. Clock Timing (GMAC Receive) - MIIn operation
Table 7-69 and Figure 7-54 present timing requirements for MIIn in transmit operation.
Table 7-69. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
MIN
1
tc(TX_CLK)
Cycle time, miin_txclk
10 Mbps
400
ns
100 Mbps
40
ns
2
3
4
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, miin_txclk high
Pulse duration, miin_txclk low
Transition time, miin_txclk
MAX
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
140
260
ns
100 Mbps
14
26
ns
10 Mbps
3
ns
100 Mbps
3
ns
Timing Requirements and Switching Characteristics
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4
1
3
2
miin_txclk
4
SPRS906_TIMING_GMAC_MIITXCLK_02
Figure 7-54. Clock Timing (GMAC Transmit) - MIIn operation
Table 7-70 and Figure 7-55 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
Table 7-70. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tsu(RXD-RX_CLK)
1
tsu(RX_DV-RX_CLK)
Setup time, receive selected signals valid before miin_rxclk
8
ns
Hold time, receive selected signals valid after miin_rxclk
8
ns
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
2
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
SPRS906_TIMING_GMAC_MIIRCV_03
Figure 7-55. GMAC Receive Interface Timing MIIn operation
Table 7-71 and Figure 7-56 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 7-71. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
1
PARAMETER
td(TX_CLK-TXD)
td(TX_CLK-TX_EN)
DESCRIPTION
Delay time, miin_txclk to transmit selected signals valid
MIN
MAX
UNIT
0
25
ns
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
SPRS906_TIMING_GMAC_MIITX_04
Figure 7-56. GMAC Transmit Interface Timing MIIn operation
In Table 7-72 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
288
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Table 7-72. GMAC MII IOSETs
SIGNALS
IOSET5
IOSET6
BALL
MUX
BALL
mii1_txd3
C5
8
MUX
mii1_txd2
D6
8
mii1_txd1
B2
8
mii1_txd0
C4
8
mii1_rxd3
F5
8
mii1_rxd2
E4
8
mii1_rxd1
C1
8
mii1_rxd0
E6
8
mii0_txd3
V5
3
mii0_txd2
V4
3
mii0_txd1
Y2
3
mii0_txd0
W2
3
mii0_rxd3
W9
3
mii0_rxd2
V9
3
mii0_rxd1
V6
3
mii0_rxd0
U6
3
mii0_txclk
U5
3
mii1_col
B4
8
mii1_rxer
B3
8
mii1_txer
A3
8
mii1_txen
A4
8
mii1_crs
B5
8
mii1_rxclk
D5
8
mii1_txclk
C3
8
mii1_rxdv
C2
8
mii0_txer
U4
3
mii0_rxer
U7
3
mii0_rxdv
V2
3
mii0_crs
V7
3
mii0_col
V1
3
mii0_rxclk
Y1
3
mii0_txen
V3
3
7.23.2 GMAC MDIO Interface Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-73, Table 7-73 and Figure 7-57 present timing requirements for MDIO.
Timing Requirements and Switching Characteristics
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Table 7-73. Timing Requirements for MDIO Input
No
PARAMETER
MDIO1
tc(MDC)
MDIO2
DESCRIPTION
MIN
MAX
UNIT
Cycle time, MDC
400
ns
tw(MDCH)
Pulse Duration, MDC High
160
ns
MDIO3
tw(MDCL)
Pulse Duration, MDC Low
160
ns
MDIO4
tsu(MDIO-MDC)
Setup time, MDIO valid before MDC High
90
ns
MDIO5
th(MDIO_MDC)
Hold time, MDIO valid from MDC High
0
ns
Table 7-74. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
DESCRIPTION
MDIO6
tt(MDC)
Transition time, MDC
MIN
MDIO7
td(MDC-MDIO)
Delay time, MDC High to MDIO valid
10
MAX
UNIT
5
ns
390
ns
1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
SPRS906_TIMING_GMAC_MDIO_05
Figure 7-57. GMAC MDIO diagrams
In Table 7-75 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
Table 7-75. GMAC MDIO IOSETs
SIGNALS
IOSET7
IOSET8
IOSET9
BALL
MUX
BALL
MUX
mdio_d
F6
3
U4
mdio_mclk
D3
3
V1
IOSET10
BALL
MUX
BALL
MUX
0
AB4
1
B20
5
0
AC5
1
B21
5
7.23.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the device TRM for full details about RMII reference clock.
290
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CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-76, Table 7-77 and Figure 7-58 present timing requirements for GMAC RMIIn Receive.
Table 7-76. Timing Requirements for GMAC REF_CLK - RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII1 tc(REF_CLK)
Cycle time, REF_CLK
20
RMII2 tw(REF_CLKH)
Pulse duration, REF_CLK high
7
13
ns
ns
RMII3 tw(REF_CLKL)
Pulse duration, REF_CLK low
7
13
ns
RMII4 ttt(REF_CLK)
Transistion time, REF_CLK
3
ns
Table 7-77. Timing Requirements for GMAC RMIIn Receive
NO.
PARAMETER
DESCRIPTION
RMII5
tsu(RXD-REF_CLK)
Setup time, receive selected signals valid before REF_CLK
MIN
4
MAX
UNIT
ns
Hold time, receive selected signals valid after REF_CLK
2
ns
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
RMII6
th(REF_CLK-RXD)
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII4
RMII2
RMII5
RMII6
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS906_TIMING_GMAC_RGMIITX_09
Figure 7-58. GMAC Receive Interface Timing RMIIn operation
Table 7-78, Table 7-78 and Figure 7-59 present switching characteristics for GMAC RMIIn Transmit
10/100Mbit/s.
Table 7-78. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII7
tc(REF_CLK)
Cycle time, REF_CLK
20
RMII8
tw(REF_CLKH)
Pulse duration, REF_CLK high
7
13
ns
ns
RMII9
tw(REF_CLKL)
Pulse duration, REF_CLK low
7
13
ns
RMII10
tt(REF_CLK)
Transistion time, REF_CLK
3
ns
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Table 7-79. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn
Transmit 10/100 Mbits/s
NO.
PARAMETER
DESCRIPTION
td(REF_CLK-TXD)
RMII11
tdd(REF_CLK-TXEN)
RMIIn
MIN
MAX
UNIT
RMII0
2
13.5
ns
RMII1
2
13.8
ns
Delay time, REF_CLK high to selected transmit signals
valid
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
RMII7
RMII8
RMII9
RMII11
RMII10
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS906_TIMING_GMAC_RMIITX_07
Figure 7-59. GMAC Transmit Interface Timing RMIIn Operation
In Table 7-80 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
Table 7-80. GMAC RMII IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
RMII_MHZ_50_CLK
U3
0
U3
0
rmii1_txd1
V5
2
rmii1_txd0
V4
2
rmii1_rxd1
W9
2
rmii1_rxd0
V9
2
rmii0_txd1
Y2
1
rmii0_txd0
W2
1
rmii0_rxd1
V6
1
rmii0_rxd0
U6
1
rmii0_txen
V3
1
rmii0_rxer
U7
1
rmii0_crs
V7
1
rmii1_rxer
Y1
2
rmii1_txen
U5
2
rmii1_crs
V2
2
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-81 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
Table 7-81 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
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Table 7-81. Manual Functions Mapping for GMAC RMII0
BALL
BALL NAME
GMAC_RMII0_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
0
1
U3
RMII_MHZ_50_CLK
0
0
CFG_RMII_MHZ_50_CLK_IN
RMII_MHZ_50_CLK
U6
rgmii0_txd0
2444
804
CFG_RGMII0_TXD0_IN
rmii0_rxd0
V6
rgmii0_txd1
2453
981
CFG_RGMII0_TXD1_IN
rmii0_rxd1
U7
rgmii0_txd2
2356
847
CFG_RGMII0_TXD2_IN
rmii0_rxer
V7
rgmii0_txd3
2415
993
CFG_RGMII0_TXD3_IN
rmii0_crs
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-82 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
Table 7-82 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
Table 7-82. Manual Functions Mapping for GMAC RMII1
BALL
BALL NAME
GMAC_RMII1_MANUAL1
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
0
U3
RMII_MHZ_50_CLK
0
0
CFG_RMII_MHZ_50_CLK_IN
2
RMII_MHZ_50_CLK
V9
rgmii0_txctl
2450
909
CFG_RGMII0_TXCTL_IN
rmii1_rxd0
W9
rgmii0_txc
2327
926
CFG_RGMII0_TXC_IN
rmii1_rxd1
Y1
uart3_txd
2553
443
CFG_UART3_TXD_IN
rmii1_rxer
V2
uart3_rxd
1943
1110
CFG_UART3_RXD_IN
rmii1_crs
7.23.4 GMAC RGMII Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-83, Table 7-84 and Figure 7-60 present timing requirements for receive RGMIIn operation.
Table 7-83. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
1
2
3
4
PARAMETER
DESCRIPTION
tc(TXC)
Cycle time, rgmiin_txc
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
SPEED
MIN
MAX
UNIT
10 Mbps
360
440
ns
100 Mbps
36
44
ns
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
0.75
ns
100 Mbps
0.75
ns
1000 Mbps
0.75
ns
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Table 7-84. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before
rgmiin_rxc high/low
RGMII0/1
MIN
1
MAX
UNIT
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after
rgmiin_rxc high/low
RGMII0/1
1
ns
(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
1
4
2
rgmiin_rxc
4
3
(A)
5
1st Half-byte
6
2nd Half-byte
rgmiin_rxd[3:0]
rgmiin_rxctl
(B)
(B)
RGRXD[3:0]
RGRXD[7:4]
RXDV
RXERR
SPRS906_TIMING_GMAC_RGMIIRX_08
A.
B.
rgmiin_rxc must be externally delayed relative to the data and control pins.
Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
Figure 7-60. GMAC Receive Interface Timing, RGMIIn operation
Table 7-85, Table 7-86 and Figure 7-61 present switching characteristics for transmit - RGMIIn for
10/100/1000Mbit/s.
Table 7-85. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
1
2
3
4
294
PARAMETER
DESCRIPTION
tc(TXC)
Cycle time, rgmiin_txc
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
SPEED
MIN
MAX
UNIT
10 Mbps
360
440
ns
100 Mbps
36
44
ns
1000 Mbps
7.2
8.8
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
160
240
ns
100 Mbps
16
24
ns
1000 Mbps
3.6
4.4
ns
10 Mbps
0.75
ns
100 Mbps
0.75
ns
1000 Mbps
0.75
ns
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(1)
Table 7-86. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
NO.
5
6
PARAMETER
DESCRIPTION
tosu(TXD-TXC)
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
toh(TXC-TXD)
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
MODE
MIN
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
MAX
UNIT
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
ns
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
(2)
(3)
(2)
(3)
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
1
4
2
3
4
(A)
rgmiin_txc
[internal delay enabled]
5
(B)
1st Half-byte
rgmiin_txd[3:0]
2nd Half-byte
6
(B)
rgmiin_txctl
TXEN
TXERR
SPRS906_TIMING_GMAC_RGMIITX_09
A.
B.
TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
Figure 7-61. GMAC Transmit Interface Timing RGMIIn operation
In Table 7-87 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
Table 7-87. GMAC RGMII IOSETs
SIGNALS
IOSET3
IOSET4
BALL
MUX
rgmii1_txd3
C3
3
rgmii1_txd2
C4
3
rgmii1_txd1
B2
3
rgmii1_txd0
D6
3
rgmii1_rxd3
B3
3
rgmii1_rxd2
B4
3
BALL
MUX
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Table 7-87. GMAC RGMII IOSETs (continued)
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
rgmii1_rxd1
B5
3
rgmii1_rxd0
A4
3
rgmii1_rxctl
A3
3
rgmii0_txd3
V7
0
rgmii0_txd2
U7
0
rgmii0_txd1
V6
0
rgmii0_txd0
U6
0
rgmii0_rxd3
V4
0
rgmii0_rxd2
V3
0
rgmii0_rxd1
Y2
0
rgmii0_rxd0
W2
0
rgmii0_txc
W9
0
rgmii0_rxctl
V5
0
rgmii0_rxc
U5
0
rgmii0_txctl
V9
0
rgmii1_txc
D5
3
rgmii1_txctl
C2
3
rgmii1_rxc
C5
3
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-88 Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual
modes.
Table 7-88 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-88. Manual Functions Mapping for GMAC RGMII0
BALL
BALL NAME
GMAC_RGMII0_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
U5
rgmii0_rxc
413
0
CFG_RGMII0_RXC_IN
rgmii0_rxc
V5
rgmii0_rxctl
27
2296
CFG_RGMII0_RXCTL_IN
rgmii0_rxctl
W2
Y2
rgmii0_rxd0
3
1721
CFG_RGMII0_RXD0_IN
rgmii0_rxd0
rgmii0_rxd1
134
1786
CFG_RGMII0_RXD1_IN
rgmii0_rxd1
V3
rgmii0_rxd2
40
1966
CFG_RGMII0_RXD2_IN
rgmii0_rxd2
V4
rgmii0_rxd3
0
2057
CFG_RGMII0_RXD3_IN
rgmii0_rxd3
W9
rgmii0_txc
0
60
CFG_RGMII0_TXC_OUT
rgmii0_txc
V9
rgmii0_txctl
0
60
CFG_RGMII0_TXCTL_OUT
rgmii0_txctl
U6
rgmii0_txd0
0
60
CFG_RGMII0_TXD0_OUT
rgmii0_txd0
0
V6
rgmii0_txd1
0
0
CFG_RGMII0_TXD1_OUT
rgmii0_txd1
U7
rgmii0_txd2
0
60
CFG_RGMII0_TXD2_OUT
rgmii0_txd2
V7
rgmii0_txd3
0
120
CFG_RGMII0_TXD3_OUT
rgmii0_txd3
Timing Requirements and Switching Characteristics
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See Table 7-2 Modes Summary for a list of IO timings
requiring the use of Manual IO Timings Modes. See Table 7-89 Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual
modes.
Table 7-89 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
Table 7-89. Manual Functions Mapping for GMAC RGMII1
BALL
BALL NAME
A_DELAY (ps)
G_DELAY (ps)
C5
vin2a_d18
530
A3
vin2a_d19
B3
B4
298
GMAC_RGMII1_MANUAL1
CFG REGISTER
MUXMODE
0
CFG_VIN2A_D18_IN
rgmii1_rxc
71
1099
CFG_VIN2A_D19_IN
rgmii1_rxctl
vin2a_d20
142
1337
CFG_VIN2A_D20_IN
rgmii1_rxd3
vin2a_d21
114
1517
CFG_VIN2A_D21_IN
rgmii1_rxd2
B5
vin2a_d22
171
1331
CFG_VIN2A_D22_IN
rgmii1_rxd1
A4
vin2a_d23
0
1328
CFG_VIN2A_D23_IN
rgmii1_rxd0
D5
vin2a_d12
0
0
CFG_VIN2A_D12_OUT
rgmii1_txc
C2
vin2a_d13
170
0
CFG_VIN2A_D13_OUT
rgmii1_txctl
C3
vin2a_d14
150
0
CFG_VIN2A_D14_OUT
rgmii1_txd3
C4
vin2a_d15
0
0
CFG_VIN2A_D15_OUT
rgmii1_txd2
B2
vin2a_d16
60
0
CFG_VIN2A_D16_OUT
rgmii1_txd1
D6
vin2a_d17
60
0
CFG_VIN2A_D17_OUT
rgmii1_txd0
3
Timing Requirements and Switching Characteristics
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7.24 Media Local Bus (MLB) interface
The MLBSS allows connection to a MOST (Media Oriented Systems Transport) network controller for
transport of media and control data between multimedia nodes. The MLBSS supports the following
features:
• 3 pin mode compliant to MediaLB Physical Layer Specification v4.0
• 6 pin mode (3 differential pairs) compliant to MediaLB Physical Layer Specification v4.0
• Supports 256/512/1024Fs in 3 pin mode and 2048Fs in 6 pin mode
• Supports all types of transfer (Sync, Isoc, Async/Packet, Control) over 64 logical channels
• 16KB buffering for synchronous /isochronous/control/packet data in the subsystem
NOTE
For more information, see the Media Local Bus (MLB) section of the Device TRM.
NOTE
MLB in 6-pin mode may require pull ups/ downs on SIG and DAT bus signals. For additional
details, please consult the MLB bus interface specification.
Table 7-90 and Figure 7-62 present Timing Requirements for MLKCLK 3-Pin Option.
Table 7-90. Timing Requirements for MLBCLK 3-Pin Option
(1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
1
tc(MLBCLK)
Cycle time, MLB_CLK
512FS
39
ns
1024FS
19.5
ns
512FS
14
ns
1024FS
9.3
ns
512FS
14
ns
1024FS
6.1
ns
2
tw(MLBCLK)
Pulse duration, MLB_CLK high
3
tw(MLBCLK)
Pulse duration, MLB_CLK low
MAX
UNIT
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
2
4
1
MLB_CLK
3
4
SPRS906_TIMING_MLB_01
Figure 7-62. MLB_CLK Timing
Table 7-91 and Table 7-92 present Timing Requirements and Switching Characteristics for MLB 3-Pin
Option.
Table 7-91. Timing Requirements for Receive Data for the MLB 3-Pin Option
NO.
PARAMETER
DESCRIPTION
5
tsu(MLBDAT-MLBCLKL)
Setup time, MLB_DAT/MLB_SIG input valid before MLB_CLK
low
6
th(MLBCLKL-MLBDAT)
Hold time, MLB_DAT/MLB_SIG input valid after MLB_CLK
low
MODE
MIN
MAX
512FS
1
ns
1024FS
1
ns
512FS
4
ns
1024FS
2
ns
Timing Requirements and Switching Characteristics
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Table 7-92. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
7
td(MLBCLKH-MLBDATV)
Delay time, MLBCLKH rising to MLB_DAT/MLB_SIG valid
512FS
0
10
ns
1024FS
0
7
ns
512FS
0
14
ns
1024FS
0
6.1
ns
MAX
UNIT
8
tdis(MLBCLKL-
Disable time, MLBCLKH falling to MLB_DAT/MLB_SIG Hi-Z
MLBDATZ)
Table 7-93 and Figure 7-62 present Timing Requirements for MLKCLK 6-Pin Option.
Table 7-93. Timing Requirements for MLBCLK 6-Pin Option
(1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
1
tc(MLBCLKx)
Cycle time, MLB_CLKP/N
2048FS, 4096FS
10
ns
2
tw(MLBCLKx)
Pulse duration, MLB_CLKP/N high
2048FS, 4096FS
4.5
ns
3
tw(MLBCLKx)
Pulse duration, MLB_CLKP/N low
2048FS, 4096FS
4.5
ns
(1) The reference points for the rise and fall transitions are measured at 20%/80% of Vin+/-.
Table 7-94 and Table 7-95 present Timing Requirements and Switching Characteristics for MLB 6-Pin
Option.
Table 7-94. Timing Requirements for Receive Data for the MLB 6-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
MIN
5
tsu(DATx-CLKxH)
Setup time, MLBP_DATx/MLBP_SIGx input valid before
MLBP_CLKx rising
2048FS
1
ns
4096FS
0.5 n*P/2(1)(2)
ns
Hold time, MLBP_DATx/MLBP_SIGx input valid after
MLBP_CLKx rising
2048FS
0.5
ns
4096FS
0.6 +
n*P/2(1)(2)
ns
6
th(CLKxH-DATx)
MAX
UNIT
(1) P= tc(MLBCLKx) period.
(2) n=0 or 1, corresponding to two captures per clock cycle.
Table 7-95. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option
NO.
PARAMETER
DESCRIPTION
MODE
7
td(CLKxH-DATxV)
Delay time, MLBPCLKxH rising to MLB_DATx/MLB_SIGx valid
2048FS
4096FS
2048FS
4096FS
8
tdis(CLKPH-DATPZ)
Disable time, MLBPCLKxH rising to MLBP_DATx/MLBP_SIGx
Hi-Z
MIN
MAX
UNIT
0.5
7
ns
0.6 +
n*P/2(1)(2)
2.5 +
n*P/2
ns
0.5
7
ns
0.6 +
n*P/2(1)(2)
3.5 +
n*P/2
ns
(1) P= tc(MLBCLKx) period.
(2) n=0 or 1, corresponding to two captures per clock cycle.
7.25 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO)
NOTE
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
7.25.1 MMC1-SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
300
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•
•
•
•
•
•
•
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Default speed, 4-bit data, SDR, half-cycle
High speed, 4-bit data, SDR, half-cycle
SDR12, 4-bit data, half-cycle
SDR25, 4-bit data, half-cycle
UHS-I SDR50, 4-bit data, half-cycle
UHS-I SDR104, 4-bit data, half-cycle
UHS-I DDR50, 4-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
7.25.1.1 Default speed, 4-bit data, SDR, half-cycle
Table 7-96 and Table 7-97 present Timing requirements and Switching characteristics for MMC1 - Default
Speed in receiver and transmitter mode (see Figure 7-63 and Figure 7-64).
Table 7-96. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DSSD5
tsu(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
5.11
ns
DSSD6
th(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
20.46
ns
DSSD7
tsu(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
5.11
ns
DSSD8
th(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
20.46
ns
Table 7-97. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DSSD0
fop(clk)
Operating frequency, mmc1_clk
DSSD1
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
24
MHz
ns
DSSD2
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
DSSD3
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-14.93
14.93
ns
DSSD4
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-14.93
14.93
ns
(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD6
DSSD5
mmc1_cmd
DSSD8
DSSD7
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_01
Figure 7-63. MMC/SD/SDIO in - Default Speed - Receiver Mode
Timing Requirements and Switching Characteristics
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DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD3
mmc1_cmd
DSSD4
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_02
Figure 7-64. MMC/SD/SDIO in - Default Speed - Transmitter Mode
7.25.1.2 High speed, 4-bit data, SDR, half-cycle
Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - High
Speed in receiver and transmitter mode (see Figure 7-65 and Figure 7-66).
Table 7-98. Timing Requirements for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HSSD3
tsu(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
5.3
ns
HSSD4
th(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
2.6
ns
HSSD7
tsu(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
5.3
ns
HSSD8
th(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
2.6
ns
Table 7-99. Switching Characteristics for MMC1 - SD Card High Speed
NO.
HSSD1
PARAMETER
DESCRIPTION
MIN
fop(clk)
Operating frequency, mmc1_clk
MAX
UNIT
48
MHz
HSSD2H tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
HSSD2L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
HSSD5
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-7.6
3.6
ns
HSSD6
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-7.6
3.6
ns
(1) P = output mmc1_clk period in ns
HSSD1
HSSD2L
HSSD2H
mmc1_clk
HSSD3
HSSD4
mmc1_cmd
HSSD7
HSSD8
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_03
Figure 7-65. MMC/SD/SDIO in - High Speed - Receiver Mode
302
Timing Requirements and Switching Characteristics
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HSSD1
HSSD2H
HSSD2L
mmc1_clk
HSSD5
HSSD5
mmc1_cmd
HSSD6
HSSD6
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_04
Figure 7-66. MMC/SD/SDIO in - High Speed - Transmitter Mode
7.25.1.3 SDR12, 4-bit data, half-cycle
Table 7-100 and Table 7-101 present Timing requirements and Switching characteristics for MMC1 SDR12 in receiver and transmitter mode (see Figure 7-67 and Figure 7-68).
Table 7-100. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MODE
SDR12 tsu(cmdV-clkH)
5
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
SDR12 th(clkH-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
SDR12 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
SDR12 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MIN
MAX
UNIT
25.99
ns
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
25.99
ns
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
Table 7-101. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR120
fop(clk)
Operating frequency, mmc1_clk
SDR121
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
24
MHz
ns
SDR122
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185(1)
ns
SDR123
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-19.13
16.93
ns
SDR124
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-19.13
16.93
ns
(1) P = output mmc1_clk period in ns
SDR122
SDR121
SDR120
mmc1_clk
SDR126
SDR125
mmc1_cmd
SDR128
SDR127
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_05
Figure 7-67. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
Timing Requirements and Switching Characteristics
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SDR122
SDR121
SDR120
mmc1_clk
SDR123
mmc1_cmd
SDR124
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_06
Figure 7-68. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
7.25.1.4 SDR25, 4-bit data, half-cycle
Table 7-102 and Table 7-103 present Timing requirements and Switching characteristics for MMC1 SDR25 in receiver and transmitter mode (see Figure 7-69 and Figure 7-70).
Table 7-102. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SDR25 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
5.3
ns
SDR25 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
ns
SDR25 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
5.3
ns
SDR25 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
ns
Internal Loopback Clock
1.6
ns
Table 7-103. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR251
fop(clk)
Operating frequency, mmc1_clk
SDR252
H
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
48
MHz
ns
SDR252L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR255
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
SDR251
SDR252L
SDR252H
mmc1_clk
SDR253
SDR254
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
Figure 7-69. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
304
Timing Requirements and Switching Characteristics
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SDR251
SDR252H
SDR252L
mmc1_clk
HSSDR255
SDR255
mmc1_cmd
SDR256
SDR256
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_08
Figure 7-70. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
7.25.1.5 UHS-I SDR50, 4-bit data, half-cycle
Table 7-104 and Table 7-105 present Timing requirements and Switching characteristics for MMC1 SDR50 in receiver and transmitter mode (see Figure 7-71 and Figure 7-72).
Table 7-104. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SDR50 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
1.48
ns
SDR50 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.7
ns
SDR50 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
1.48
ns
SDR50 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.7
ns
Internal Loopback Clock
1.6
ns
Table 7-105. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
SDR501
fop(clk)
Operating frequency, mmc1_clk
SDR502
H
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
SDR502L tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR505
td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
ns
SDR506
td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-3.66
1.46
ns
96
UNIT
MHz
(1) P = output mmc1_clk period in ns
SDR501
SDR502L
SDR502H
mmc1_clk
SDR503
SDR504
mmc1_cmd
SDR507
SDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_09
Figure 7-71. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
Timing Requirements and Switching Characteristics
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SDR501
SDR502H
SDR502L
mmc1_clk
SDR505
SDR505
mmc1_cmd
SDR506
SDR506
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_10
Figure 7-72. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
7.25.1.6 UHS-I SDR104, 4-bit data, half-cycle
Table 7-106 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver
and transmitter mode (see Figure 7-73 and Figure 7-74).
Table 7-106. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
192
UNIT
SDR1041 fop(clk)
Operating frequency, mmc1_clk
MHz
SDR1042 tw(clkH)
H
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
SDR1042 tw(clkL)
L
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
SDR1045 td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-1.09
0.49
ns
SDR1046 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-1.09
0.49
ns
(1) P = output mmc1_clk period in ns
SDR1041
SDR1042L
SDR1042H
mmc1_clk
SDR1043
SDR1044
mmc1_cmd
SDR1047
SDR1048
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_11
Figure 7-73. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
SDR1041
SDR1042H
SDR1042L
mmc1_clk
SDR1045
SDR1045
mmc1_cmd
SDR1046
SDR1046
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_12
Figure 7-74. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
7.25.1.7 UHS-I DDR50, 4-bit data
Table 7-107 and Table 7-108 present Timing requirements and Switching characteristics for MMC1 DDR50 in receiver and transmitter mode (see Figure 7-75 and Figure 7-76).
306
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Table 7-107. Timing Requirements for MMC1 - SD Card DDR50 Mode
PARAME
TER
NO.
DESCRIPTION
MODE
DDR50 tsu(cmdV-clk)
5
Setup time, mmc1_cmd valid before mmc1_clk
transition
DDR50 th(clk-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk transition
DDR50 tsu(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
DDR50 th(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
Pad Loopback
MIN
MAX
UNIT
1.79
ns
2
ns
Pad Loopback
1.79
ns
Internal Loopback
1.79
ns
2
ns
1.6
ns
Internal Loopback
Table 7-108. Switching Characteristics for MMC1 - SD Card DDR50 Mode
PARAMETER
DESCRIPTION
DDR500
NO.
fop(clk)
Operating frequency, mmc1_clk
MIN
MAX
UNIT
DDR501
tw(clkH)
Pulse duration, mmc1_clk high
0.5*P0.185 (1)
ns
DDR502
tw(clkL)
Pulse duration, mmc1_clk low
0.5*P0.185 (1)
ns
DDR503
td(clk-cmdV)
Delay time, mmc1_clk transition to mmc1_cmd transition
1.225
6.6
ns
DDR504
td(clk-dV)
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
1.225
6.6
ns
48
MHz
(1) P = output mmc1_clk period in ns
DDR500
DDR502
DDR501
mmc1_clk
DDR505
DDR506
mmc1_cmd
DDR507
DDR507
DDR508
DDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_13
Figure 7-75. SDMMC - High Speed SD - DDR - Data/Command Receive
DDR500
DDR501
DDR502
mmc1_clk
DDR503(max)
DDR503(min)
mmc1_cmd
DDR504(max)
DDR504(min)
DDR504(max)
DDR504(min)
mmc1_dat[3:0]
MMC1_14
Figure 7-76. SDMMC - High Speed SD - DDR - Data/Command Transmit
Timing Requirements and Switching Characteristics
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NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-109 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
Table 7-109 presents the values for DELAYMODE bitfield.
Table 7-109. Virtual Functions Mapping for MMC1
BALL
BALL NAME
Delay Mode Value
MUXMODE
MMC1_
VIRTUAL1
MMC1_
VIRTUAL4
MMC1_
VIRTUAL5
MMC1_
VIRTUAL6
0
W6
mmc1_clk
15
12
11
10
mmc1_clk
Y6
mmc1_cmd
15
12
11
10
mmc1_cmd
AA6
mmc1_dat0
15
12
11
10
mmc1_dat0
Y4
mmc1_dat1
15
12
11
10
mmc1_dat1
AA5
mmc1_dat2
15
12
11
10
mmc1_dat2
Y3
mmc1_dat3
15
12
11
10
mmc1_dat3
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-110 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
Table 7-110 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
308
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Table 7-110. Manual Functions Mapping for MMC1
BALL
W6
BALL NAME
MMC1_MANUAL1
MMC1_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
mmc1_clk
588
0
-
-
CFG REGISTER
MUXMODE
CFG_MMC1_CLK_IN
mmc1_clk
0
Y6
mmc1_cmd
1000
0
-
-
CFG_MMC1_CMD_IN
mmc1_cmd
AA6
mmc1_dat0
1375
0
-
-
CFG_MMC1_DAT0_IN
mmc1_dat0
Y4
mmc1_dat1
1000
0
-
-
CFG_MMC1_DAT1_IN
mmc1_dat1
AA5
mmc1_dat2
1000
0
-
-
CFG_MMC1_DAT2_IN
mmc1_dat2
Y3
mmc1_dat3
1000
0
-
-
CFG_MMC1_DAT3_IN
mmc1_dat3
W6
mmc1_clk
1230
0
520
320
CFG_MMC1_CLK_OUT
mmc1_clk
Y6
mmc1_cmd
0
0
0
0
CFG_MMC1_CMD_OUT
mmc1_cmd
AA6
mmc1_dat0
56
0
40
0
CFG_MMC1_DAT0_OUT
mmc1_dat0
Y4
mmc1_dat1
76
0
83
0
CFG_MMC1_DAT1_OUT
mmc1_dat1
AA5
mmc1_dat2
91
0
98
0
CFG_MMC1_DAT2_OUT
mmc1_dat2
Y3
mmc1_dat3
99
0
106
0
CFG_MMC1_DAT3_OUT
mmc1_dat3
Y6
mmc1_cmd
0
0
51
0
CFG_MMC1_CMD_OEN
mmc1_cmd
AA6
mmc1_dat0
0
0
0
0
CFG_MMC1_DAT0_OEN
mmc1_dat0
Y4
mmc1_dat1
0
0
363
0
CFG_MMC1_DAT1_OEN
mmc1_dat1
AA5
mmc1_dat2
0
0
199
0
CFG_MMC1_DAT2_OEN
mmc1_dat2
Y3
mmc1_dat3
0
0
273
0
CFG_MMC1_DAT3_OEN
mmc1_dat3
7.25.2 MMC2 - eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
• Standard JC64 SDR, 8-bit data, half cycle
• High-speed JC64 SDR, 8-bit data, half cycle
• High-speed HS200 JEDS84, 8-bit data, half cycle
• High-speed JC64 DDR, 8-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
Timing Requirements and Switching Characteristics
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7.25.2.1 Standard JC64 SDR, 8-bit data, half cycle
Table 7-111 and Table 7-112 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter
mode (see Figure 7-77 and Figure 7-78).
Table 7-111. Timing Requirements for MMC2 - JC64 Standard SDR Mode
NO.
310
PARAMETER
DESCRIPTION
SSDR5
tsu(cmdV-clkH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
MIN
SSDR6
th(clkH-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
SSDR7
tsu(dV-clkH)
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
SSDR8
th(clkH-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
Timing Requirements and Switching Characteristics
MAX
UNIT
13.19
ns
8.4
ns
13.19
ns
8.4
ns
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Table 7-112. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO.
SSDR1
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
24
MHz
SSDR2H tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
ns
SSDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
SSDR3
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-16.96
16.96
ns
SSDR4
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-16.96
16.96
ns
(1) P = output mmc2_clk period in ns
SSDR2
SSDR2
SSDR1
mmc2_clk
SSDR6
SSDR5
mmc2_cmd
SSDR8
SSDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_01
Figure 7-77. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
SSDR2
SSDR1
mmc2_clk
SSDR3
mmc2_cmd
SSDR4
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_02
Figure 7-78. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
7.25.2.2 High-speed JC64 SDR, 8-bit data, half cycle
Table 7-113 and Table 7-114 present Timing requirements and Switching characteristics for MMC2 - High
speed SDR in receiver and transmitter mode (see Figure 7-79 and Figure 7-80).
Table 7-113. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
JC643
tsu(cmdV-clkH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
5.6
ns
JC644
th(clkH-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
2.6
ns
JC647
tsu(dV-clkH)
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
5.6
ns
JC648
th(clkH-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
2.6
ns
Timing Requirements and Switching Characteristics
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UNIT
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Table 7-114. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
PARAMETER
DESCRIPTION
JC641
NO.
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
UNIT
48
JC642H
tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
MHz
ns
JC642L
tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
JC645
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-6.64
6.64
ns
JC646
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-6.64
6.64
ns
(1) P = output mmc2_clk period in ns
JC641
JC642L
JC642H
mmc2_clk
JC643
JC644
mmc2_cmd
JC647
JC648
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_03
Figure 7-79. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
JC641
JC642L
JC642H
mmc2_clk
JC645
JC645
mmc2_cmd
JC646
JC646
mmc2_dat[7:0]
MMC2_04
Figure 7-80. MMC/SD/SDIO in - High Speed JC64 - transmitter Mode
7.25.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
Table 7-115 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see Figure 7-81).
312
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Table 7-115. Switching Characteristics for MMC2 - JEDS84 HS200 Mode
NO.
HS2001
PARAMETER
DESCRIPTION
fop(clk)
Operating frequency, mmc2_clk
MIN
MAX
192
UNIT
MHz
HS2002H tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172 (1)
ns
HS2002L tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172 (1)
ns
HS2005
td(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
-1.136
0.536
ns
HS2006
td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-1.136
0.536
ns
(1) P = output mmc2_clk period in ns
HS2001
HS2002L
HS2002H
mmc2_clk
HS2005
HS2005
mmc2_cmd
HS2006
HS2006
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_05
Figure 7-81. eMMC in - HS200 SDR - Transmitter Mode
7.25.2.4 High-speed JC64 DDR, 8-bit data
Table 7-116 and Table 7-117 present Timing requirements and Switching characteristics for MMC2 - High
speed DDR in receiver and transmitter mode (see Figure 7-82 and Figure 7-83).
Table 7-116. Timing Requirements for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
DDR3 tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk
transition
1.8
ns
DDR4 th(clk-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk
transition
1.6
ns
DDR7 tsu(dV-clk)
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
1.8
ns
DDR8 th(clk-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk
transition
Pad Loopback (1.8V and 3.3V),
Boot
1.6
ns
Internal Loopback (1.8V with
MMC2_VIRTUAL2)
1.86
ns
Internal Loopback (3.3V with
MMC2_VIRTUAL2)
1.95
ns
Internal Loopback (1.8V with
MMC2_MANUAL2)
Internal Loopback (3.3V with
MMC2_MANUAL2)
ns
1.6
ns
Table 7-117. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
NO.
DDR1
PARAMETER
DESCRIPTION
MAX
UNIT
fop(clk)
Operating frequency, mmc2_clk
MIN
48
MHz
ns
ns
DDR2H
tw(clkH)
Pulse duration, mmc2_clk high
0.5*P0.172
(1)
DDR2L
tw(clkL)
Pulse duration, mmc2_clk low
0.5*P0.172
(1)
Timing Requirements and Switching Characteristics
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Table 7-117. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DDR5
NO.
td(clk-cmdV)
Delay time, mmc2_clk transition to mmc2_cmd transition
2.9
7.14
ns
DDR6
td(clk-dV)
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
2.9
7.14
ns
(1) P = output mmc2_clk period in ns
DDR1
DDR2H
DDR2L
mmc2_clk
DDR3
DDR4
mmc2_cmd
DDR8
DDR8
DDR7
DDR8
DDR7
DDR7
DDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_07
Figure 7-82. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
DDR1
DDR2
DDR2
mmc2_clk
DDR5
DDR5
DDR5
DDR5
mmc2_cmd
DDR6
DDR6
DDReMMC6
DDR6
DDReMMC6
DDR6
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_08
Figure 7-83. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 7-118 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
Table 7-118 presents the values for DELAYMODE bitfield.
Table 7-118. Virtual Functions Mapping for MMC2
314
BALL
BALL NAME
Delay Mode Value
MUXMODE
MMC2_VIRTUAL2
1
H6
gpmc_cs1
13
mmc2_cmd
K7
gpmc_a19
13
mmc2_dat4
Timing Requirements and Switching Characteristics
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Table 7-118. Virtual Functions Mapping for MMC2 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
MMC2_VIRTUAL2
1
M7
gpmc_a20
13
mmc2_dat5
J5
gpmc_a21
13
mmc2_dat6
K6
gpmc_a22
13
mmc2_dat7
J7
gpmc_a23
13
mmc2_clk
J4
gpmc_a24
13
mmc2_dat0
J6
gpmc_a25
13
mmc2_dat1
H4
gpmc_a26
13
mmc2_dat2
H5
gpmc_a27
13
mmc2_dat3
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-119 Manual
Functions Mapping for MMC2 for a definition of the Manual modes.
Table 7-119 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-119. Manual Functions Mapping for MMC2
BAL BALL NAME
L
MMC2_MANUAL1
A_DELAY G_DELAY
(ps)
(ps)
MMC2_MANUAL2
MMC2_MANUAL3
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
1
K7
gpmc_a19
0
0
0
14
-
-
CFG_GPMC_A19_IN
mmc2_dat4
M7
gpmc_a20
119
0
127
0
-
-
CFG_GPMC_A20_IN
mmc2_dat5
J5
gpmc_a21
0
0
22
0
-
-
CFG_GPMC_A21_IN
mmc2_dat6
K6
gpmc_a22
18
0
72
0
-
-
CFG_GPMC_A22_IN
mmc2_dat7
J7
gpmc_a23
894
0
410
4000
-
-
CFG_GPMC_A23_IN
mmc2_clk
J4
gpmc_a24
30
0
82
0
-
-
CFG_GPMC_A24_IN
mmc2_dat0
J6
gpmc_a25
0
0
0
0
-
-
CFG_GPMC_A25_IN
mmc2_dat1
H4
gpmc_a26
23
0
77
0
-
-
CFG_GPMC_A26_IN
mmc2_dat2
H5
gpmc_a27
0
0
0
0
-
-
CFG_GPMC_A27_IN
mmc2_dat3
H6
gpmc_cs1
0
0
0
0
-
-
CFG_GPMC_CS1_IN
mmc2_cmd
K7
gpmc_a19
152
0
152
0
285
0
CFG_GPMC_A19_OUT mmc2_dat4
M7
gpmc_a20
206
0
206
0
189
0
CFG_GPMC_A20_OUT mmc2_dat5
J5
gpmc_a21
78
0
78
0
0
120
CFG_GPMC_A21_OUT mmc2_dat6
K6
gpmc_a22
2
0
2
0
0
70
CFG_GPMC_A22_OUT mmc2_dat7
J7
gpmc_a23
266
0
266
0
730
360
CFG_GPMC_A23_OUT
J4
gpmc_a24
0
0
0
0
0
0
CFG_GPMC_A24_OUT mmc2_dat0
mmc2_clk
J6
gpmc_a25
0
0
0
0
0
0
CFG_GPMC_A25_OUT mmc2_dat1
H4
gpmc_a26
43
0
43
0
70
0
CFG_GPMC_A26_OUT mmc2_dat2
H5
gpmc_a27
0
0
0
0
0
0
CFG_GPMC_A27_OUT mmc2_dat3
H6
gpmc_cs1
0
0
0
0
0
120
CFG_GPMC_CS1_OUT mmc2_cmd
K7
gpmc_a19
0
0
0
0
0
0
CFG_GPMC_A19_OEN mmc2_dat4
Timing Requirements and Switching Characteristics
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Table 7-119. Manual Functions Mapping for MMC2 (continued)
BAL BALL NAME
L
MMC2_MANUAL1
A_DELAY G_DELAY
(ps)
(ps)
MMC2_MANUAL2
MMC2_MANUAL3
A_DELAY
(ps)
G_DELAY
(ps)
A_DELAY
(ps)
G_DELAY
(ps)
CFG REGISTER
MUXMODE
1
M7
gpmc_a20
0
0
0
0
231
0
CFG_GPMC_A20_OEN mmc2_dat5
J5
gpmc_a21
0
0
0
0
39
0
CFG_GPMC_A21_OEN mmc2_dat6
K6
gpmc_a22
0
0
0
0
91
0
CFG_GPMC_A22_OEN mmc2_dat7
J4
gpmc_a24
0
0
0
0
176
0
CFG_GPMC_A24_OEN mmc2_dat0
J6
gpmc_a25
0
0
0
0
0
0
CFG_GPMC_A25_OEN mmc2_dat1
H4
gpmc_a26
0
0
0
0
101
0
CFG_GPMC_A26_OEN mmc2_dat2
H5
gpmc_a27
0
0
0
0
0
0
CFG_GPMC_A27_OEN mmc2_dat3
H6
gpmc_cs1
0
0
0
0
360
0
CFG_GPMC_CS1_OE
N
mmc2_cmd
7.25.3 MMC3 and MMC4-SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
• MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
• MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
• MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
• MMC3 8-bit data, UHS-I SDR50
NOTE
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
NOTE
For more information, see the MMC/SDIO chapter of the Device TRM.
7.25.3.1 MMC3 and MMC4, SD Default Speed
Figure 7-84 , Figure 7-85, and Table 7-120 through Table 7-123 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
Table 7-120. Timing Requirements for MMC3 - Default Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
DS5
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
5.11
MAX
UNIT
ns
DS6
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
20.46
ns
DS7
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
5.11
ns
DS8
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
20.46
ns
(1) i in [i:0] = 7
Table 7-121. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
DS0
fop(clk)
Operating frequency, mmc3_clk
DS1
tw(clkH)
Pulse duration, mmc3_clk high
316
MIN
0.5*P0.270 (1)
MAX
UNIT
24
MHz
ns
Timing Requirements and Switching Characteristics
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Table 7-121. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (2) (continued)
NO.
PARAMETER
DESCRIPTION
DS2
tw(clkL)
Pulse duration, mmc3_clk low
MIN
MAX
DS3
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-14.93
14.93
ns
DS4
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-14.93
14.93
ns
0.5*P0.270 (1)
UNIT
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-122. Timing Requirements for MMC4 - Default Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
DS5
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
5.11
MIN
MAX
UNIT
ns
DS6
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
20.46
ns
DS7
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
5.11
ns
DS8
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
20.46
ns
(1) i in [i:0] = 3
Table 7-123. Switching Characteristics for MMC4 - Default Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
DS0
fop(clk)
Operating frequency, mmc4_clk
MIN
MAX
UNIT
24
DS1
tw(clkH)
Pulse duration, mmc4_clk high
0.5*P0.270 (1)
MHz
ns
DS2
tw(clkL)
Pulse duration, mmc4_clk low
0.5*P0.270 (1)
ns
DS3
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-14.93
14.93
ns
DS4
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-14.93
14.93
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmcj_clk
DS6
DS5
mmcj_cmd
DS8
DS7
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_07
Figure 7-84. MMC/SD/SDIOj in - Default Speed - Receiver Mode
Timing Requirements and Switching Characteristics
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DS2
DS1
DS0
mmcj_clk
DS3
mmcj_cmd
DS4
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_08
Figure 7-85. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
7.25.3.2 MMC3 and MMC4, SD High Speed
Figure 7-86, Figure 7-87, and Table 7-124 through Table 7-127 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter
mode.
Table 7-124. Timing Requirements for MMC3 - SD/SDIO High Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HS3
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
5.3
ns
HS4
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
2.6
ns
HS7
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
5.3
ns
HS8
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
2.6
ns
(1) i in [i:0] = 7
Table 7-125. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
HS1
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
48
HS2H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
MHz
ns
HS2L
tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
HS5
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-7.6
3.6
ns
HS6
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-7.6
3.6
ns
MAX
UNIT
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-126. Timing Requirements for MMC4 - High Speed Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
HS3
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
5.3
ns
HS4
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
1.6
ns
HS7
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
5.3
ns
HS8
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
1.6
ns
(1) i in [i:0] = 3
Table 7-127. Switching Characteristics for MMC4 - High Speed Mode (2)
NO.
PARAMETER
DESCRIPTION
HS1
fop(clk)
Operating frequency, mmc4_clk
HS2H
tw(clkH)
Pulse duration, mmc4_clk high
318
MIN
0.5*P0.270 (1)
MAX
UNIT
48
MHz
ns
Timing Requirements and Switching Characteristics
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Table 7-127. Switching Characteristics for MMC4 - High Speed Mode (2) (continued)
PARAMETER
DESCRIPTION
HS2L
NO.
tw(clkL)
Pulse duration, mmc4_clk low
MIN
MAX
HS5
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-8.8
6.6
ns
HS6
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
ns
0.5*P0.270 (1)
UNIT
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
HS1
HS2H
HS2L
mmcj_clk
HS3
HS4
mmcj_cmd
HS7
HS8
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_09
Figure 7-86. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode
HS1
HS2H
HS2L
mmcj_clk
HS5
HS5
mmcj_cmd
HS6
HS6
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_10
Figure 7-87. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmitter Mode
7.25.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
Figure 7-88, Figure 7-89, and Table 7-128, through Table 7-131 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
Table 7-128. Timing Requirements for MMC3 - SDR12 Mode (1)
PARAMETER
DESCRIPTION
SDR125
NO.
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
SDR126
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
SDR127
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
SDR128
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
MAX
UNIT
25.99
ns
1.6
ns
25.99
ns
1.6
ns
(1) i in [i:0] = 7
Table 7-129. Switching Characteristics for MMC3 - SDR12 Mode (2)
NO.
PARAMETER
DESCRIPTION
SDR120
fop(clk)
Operating frequency, mmc3_clk
SDR121
tw(clkH)
Pulse duration, mmc3_clk high
MIN
MAX
UNIT
24
MHz
0.5*P0.270 (1)
Timing Requirements and Switching Characteristics
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Table 7-129. Switching Characteristics for MMC3 - SDR12 Mode (2) (continued)
PARAMETER
DESCRIPTION
SDR122
NO.
tw(clkL)
Pulse duration, mmc3_clk low
MIN
MAX
SDR123
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-19.13
16.93
ns
SDR124
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-19.13
16.93
ns
MAX
UNIT
0.5*P0.270 (1)
UNIT
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-130. Timing Requirements for MMC4 - SDR12 Mode (1)
PARAMETER
DESCRIPTION
SDR125
NO.
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
SDR126
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
SDR127
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
SDR128
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
MIN
25.99
ns
1.6
ns
25.99
ns
1.6
ns
(1) j in [i:0] = 3
Table 7-131. Switching Characteristics for MMC4 - SDR12 Mode (2)
PARAMETER
DESCRIPTION
SDR120
NO.
fop(clk)
Operating frequency, mmc4_clk
MIN
MAX
UNIT
24
SDR121
tw(clkH)
Pulse duration, mmc4_clk high
0.5*P0.270 (1)
MHz
ns
SDR122
tw(clkL)
Pulse duration, mmc4_clk low
0.5*P0.270 (1)
ns
SDR125
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-19.13
16.93
ns
SDR126
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-19.13
16.93
ns
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
SDR122
SDR121
SDR120
mmcj_clk
SDR126
SDR125
mmcj_cmd
SDR128
SDR127
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_11
Figure 7-88. MMC/SD/SDIOj in - SDR12 - Receiver Mode
320
Timing Requirements and Switching Characteristics
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SDR122
SDR121
SDR120
mmcj_clk
SDR123
mmcj_cmd
SDR124
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_12
Figure 7-89. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
7.25.3.4 MMC3 and MMC4, SD SDR25 Mode
Figure 7-90, Figure 7-91, and Table 7-132, through Table 7-135 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
Table 7-132. Timing Requirements for MMC3 - SDR25 Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR253
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
5.3
ns
SDR254
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
1.6
ns
SDR257
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
5.3
ns
SDR258
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
ns
(1) i in [i:0] = 7
Table 7-133. Switching Characteristics for MMC3 - SDR25 Mode (2)
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, mmc3_clk
MIN
MAX
UNIT
48
SDR252
H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
MHz
ns
SDR252L tw(clkL)
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
SDR255
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-8.8
6.6
ns
MAX
UNIT
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 7-134. Timing Requirements for MMC4 - SDR25 Mode (1)
PARAMETER
DESCRIPTION
MIN
SDR255
NO.
tsu(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
5.3
ns
SDR256
th(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
1.6
ns
SDR257
tsu(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
5.3
ns
SDR258
th(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
1.6
ns
(1) i in [i:0] = 3
Table 7-135. Switching Characteristics for MMC4 - SDR25 Mode (2)
PARAMETER
DESCRIPTION
SDR251
NO.
fop(clk)
Operating frequency, mmc4_clk
SDR252
H
tw(clkH)
Pulse duration, mmc4_clk high
MIN
MAX
UNIT
48
MHz
0.5*P0.270 (1)
Timing Requirements and Switching Characteristics
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Table 7-135. Switching Characteristics for MMC4 - SDR25 Mode (2) (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
0.5*P0.270 (1)
UNIT
SDR252L tw(clkL)
Pulse duration, mmc4_clk low
ns
SDR255
td(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
-8.8
6.6
ns
SDR256
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
6.6
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR252H
mmcj_clk
SDR253
SDR254
mmcj_cmd
SDR257
SDR258
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_13
Figure 7-90. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
mmcj_clk
SDR255
SDR255
mmcj_cmd
SDR256
SDR256
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_14
Figure 7-91. MMC/SD/SDIOj in - SDR25 - Transmitter Mode
7.25.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
Figure 7-92, Figure 7-93, Table 7-136, and Table 7-137 present Timing requirements and Switching
characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
Table 7-136. Timing Requirements for MMC3 - SDR50 Mode (1)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR503
tsu(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
1.48
ns
SDR504
th(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
1.6
ns
SDR507
tsu(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
1.48
ns
SDR508
th(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
ns
(1) i in [i:0] = 7
Table 7-137. Switching Characteristics for MMC3 - SDR50 Mode (2)
PARAMETER
DESCRIPTION
SDR501
NO.
fop(clk)
Operating frequency, mmc3_clk
SDR502
H
tw(clkH)
Pulse duration, mmc3_clk high
0.5*P0.270 (1)
ns
Pulse duration, mmc3_clk low
0.5*P0.270 (1)
ns
SDR502L tw(clkL)
322
MIN
MAX
UNIT
64
MHz
Timing Requirements and Switching Characteristics
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Table 7-137. Switching Characteristics for MMC3 - SDR50 Mode (2) (continued)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR505
NO.
td(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
-3.66
1.46
ns
SDR506
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-3.66
1.46
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
SDR501
SDR502L
SDR502H
mmcj_clk
SDR503
SDR504
mmcj_cmd
SDR507
SDR508
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_05
Figure 7-92. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
mmcj_clk
SDR505
SDR505
mmcj_cmd
SDR506
SDR506
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_06
Figure 7-93. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC3. See Table 7-2 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-138 Manual
Functions Mapping for MMC3 for a definition of the Manual modes.
Table 7-138 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
Table 7-138. Manual Functions Mapping for MMC3
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
A_DELAY (ps)
G_DELAY (ps)
MUXMODE
0
AD4
mmc3_clk
1085
21
CFG_MMC3_CLK_IN
AD4
mmc3_clk
1269
0
CFG_MMC3_CLK_OUT
mmc3_clk
mmc3_clk
AC4
mmc3_cmd
0
0
CFG_MMC3_CMD_IN
mmc3_cmd
AC4
mmc3_cmd
128
0
CFG_MMC3_CMD_OEN
mmc3_cmd
AC4
mmc3_cmd
98
0
CFG_MMC3_CMD_OUT
mmc3_cmd
AC7
mmc3_dat0
0
0
CFG_MMC3_DAT0_IN
mmc3_dat0
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Table 7-138. Manual Functions Mapping for MMC3 (continued)
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
A_DELAY (ps)
G_DELAY (ps)
MUXMODE
0
AC7
mmc3_dat0
362
0
CFG_MMC3_DAT0_OEN
mmc3_dat0
AC7
mmc3_dat0
0
0
CFG_MMC3_DAT0_OUT
mmc3_dat0
AC6
mmc3_dat1
7
0
CFG_MMC3_DAT1_IN
mmc3_dat1
AC6
mmc3_dat1
333
0
CFG_MMC3_DAT1_OEN
mmc3_dat1
AC6
mmc3_dat1
0
0
CFG_MMC3_DAT1_OUT
mmc3_dat1
AC9
mmc3_dat2
0
0
CFG_MMC3_DAT2_IN
mmc3_dat2
AC9
mmc3_dat2
402
0
CFG_MMC3_DAT2_OEN
mmc3_dat2
AC9
mmc3_dat2
0
0
CFG_MMC3_DAT2_OUT
mmc3_dat2
AC3
mmc3_dat3
203
0
CFG_MMC3_DAT3_IN
mmc3_dat3
AC3
mmc3_dat3
549
0
CFG_MMC3_DAT3_OEN
mmc3_dat3
AC3
mmc3_dat3
1
0
CFG_MMC3_DAT3_OUT
mmc3_dat3
AC8
mmc3_dat4
121
0
CFG_MMC3_DAT4_IN
mmc3_dat4
AC8
mmc3_dat4
440
0
CFG_MMC3_DAT4_OEN
mmc3_dat4
AC8
mmc3_dat4
206
0
CFG_MMC3_DAT4_OUT
mmc3_dat4
AD6
mmc3_dat5
336
0
CFG_MMC3_DAT5_IN
mmc3_dat5
AD6
mmc3_dat5
283
0
CFG_MMC3_DAT5_OEN
mmc3_dat5
AD6
mmc3_dat5
174
0
CFG_MMC3_DAT5_OUT
mmc3_dat5
AB8
mmc3_dat6
320
0
CFG_MMC3_DAT6_IN
mmc3_dat6
AB8
mmc3_dat6
443
0
CFG_MMC3_DAT6_OEN
mmc3_dat6
AB8
mmc3_dat6
0
0
CFG_MMC3_DAT6_OUT
mmc3_dat6
AB5
mmc3_dat7
2
0
CFG_MMC3_DAT7_IN
mmc3_dat7
AB5
mmc3_dat7
344
0
CFG_MMC3_DAT7_OEN
mmc3_dat7
AB5
mmc3_dat7
0
0
CFG_MMC3_DAT7_OUT
mmc3_dat7
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
7.26 General-Purpose Interface (GPIO)
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 215 pins.
These pins can be configured for the following applications:
• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
• Wake-up request generation in idle mode upon the detection of external events
NOTE
For more information, see the General-Purpose Interface chapter of the Device TRM.
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NOTE
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
7.27 Audio Tracking Logic (ATL)
The device contains four ATL modules that can be used for asynchronous sample rate conversion of
audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally
generates an averaged clock using cycle stealing via software.
NOTE
For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL)
chapter of the device-specific Technical Reference Manual.
NOTE
Audio Tracking Logic x (x= 1 to 4) module is also referred to as ATLx.
7.27.1 ATL Electrical Data/Timing
Table 7-139 and Figure 7-94 present switching characteristics for ATL
Table 7-139. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
NO.
PARAMETER
DESCRIPTION
1
tc(ATLCLKOUT)
Cycle time, ATL_CLKOUTx
2
tw(ATLCLKOUTL)
3
tw(ATLCLKOUTH)
MIN
MAX
UNIT
20
ns
Pulse Duration, ATL_CLKOUTx low
0.45*P - M(1)
ns
Pulse Duration, ATL_CLKOUTx high
0.45*P - M(1)
ns
(1) P = ATL_CLKOUTx period.
M = internal ATL PCLK period.
1
2
atl_clkx
3
SPRS906_TIMING_ATL_01
Figure 7-94. ATL_CLKOUTx Timing
7.28 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
• Sysboot Interface
• System DMA Interface
• Interrupt Controllers (INTC) Interface
• Observability Signal (OBS) Interface
7.29 Test Interfaces
The Device includes the following Test interfaces:
• IEEE 1149.1 Standard-Test-Access Port (JTAG)
• Trace Port Interface Unit (TPIU)
• Advanced Event Triggering Interface (AET)
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7.29.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
• 32KB embedded trace buffer (ETB)
• 5-pin system trace interface for debug
• Supports Advanced Event Triggering (AET)
• All processors can be emulated via JTAG ports
• All functions on EMU pins of the device:
– EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
– EMU[4:2] - STM trace only (single direction)
7.29.1.1 JTAG Electrical Data/Timing
Table 7-140, Table 7-141 and Figure 7-95 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-140. Timing Requirements for IEEE 1149.1 JTAG
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
62.29
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
24.92
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
24.92
ns
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high
6.23
ns
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high
6.23
ns
th(TCK-TDI)
Input hold time, TDI valid from TCK high
31.15
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
31.15
ns
3
4
Table 7-141. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
2
326
PARAMETER
td(TCKL-TDOV)
DESCRIPTION
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
0
30.5
ns
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1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
SPRS906_TIMING_JTAG_01
Figure 7-95. JTAG Timing
Table 7-142, Table 7-143 and Figure 7-96 assume testing over the recommended operating conditions
and electrical characteristic conditions below.
Table 7-142. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
1
tc(TCK)
Cycle time, TCK
62.29
ns
1a
tw(TCKH)
Pulse duration, TCK high (40% of tc)
24.92
ns
1b
tw(TCKL)
Pulse duration, TCK low (40% of tc)
24.92
ns
tsu(TDI-TCK)
Input setup time, TDI valid to TCK high
6.23
ns
tsu(TMS-TCK)
Input setup time, TMS valid to TCK high
6.23
ns
th(TCK-TDI)
Input hold time, TDI valid from TCK high
31.15
ns
th(TCK-TMS)
Input hold time, TMS valid from TCK high
31.15
ns
3
4
Table 7-143. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
0
27
ns
5
td(TCK-RTCK)
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the ARM is in the scan chain, the delay
time is a function of the ARM functional clock).
6
tc(RTCK)
Cycle time, RTCK
62.29
ns
7
tw(RTCKH)
Pulse duration, RTCK high (40% of tc)
24.92
ns
8
tw(RTCKL)
Pulse duration, RTCK low (40% of tc)
24.92
ns
5
TCK
6
7
8
RTCK
SPRS906_TIMING_JTAG_02
Figure 7-96. JTAG With RTCK Timing
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7.29.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-145.
7.29.2.1 TPIU PLL DDR Mode
Table 7-144 and Figure 7-97 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-144. Switching Characteristics for TPIU
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
TPIU1
tc(clk)
Cycle time, TRACECLK period
5.56
ns
TPIU4
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL transition
-1.61
1.98
ns
TPIU5
td(clk-dataV)
Skew time, TRACECLK transition to TRACEDATA[17:0]
-1.61
1.98
ns
TPIU1
TPIU2
TPIU3
TRACECLK
TPIU4
TPIU4
TRACECTL
TPIU5
TPIU5
TRACEDATA[X:0]
SPRS906_TIMING_TIMER_01
Figure 7-97. TPIU-PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
In Table 7-145 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
Table 7-145. TPIU IOSETs
SIGNALS
328
IOSET1
IOSET2
BALL
MUX
BALL
MUX
emu19
E6
5
A10
2
emu18
F5
5
B9
2
emu17
E4
5
A9
2
emu16
C1
5
C9
2
emu15
F4
5
A8
2
emu14
D2
5
C7
2
emu13
E2
5
C8
2
emu12
D1
5
C6
2
emu11
F3
5
A5
2
emu10
F2
5
D8
2
emu9
G6
5
E7
2
emu8
G1
5
F8
2
emu7
H7
5
F9
2
emu6
G2
5
E9
2
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Table 7-145. TPIU IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
MUX
BALL
MUX
emu5
E1
5
G11
2
emu4
A7
2
A7
2
emu3
D7
2
D7
2
emu2
F10
2
F10
2
emu1
D24
0
D24
0
emu0
G21
0
G21
0
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8 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
8.1
Introduction
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB
that can support TI’s latest Application Processor. This Processor is a high-performance processor
designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm
CMOS process technology.
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to
achieve the desirable high performance processing available on Device. The general principles and stepby-step approach for implementing good power integrity (PI) with specific requirements will be described
for the key Device power domains.
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.
Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on
prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on
PDN PI modeling and validation testing.
Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces
(i.e. USB2.0, USB3.0, HDMI, PCI, SATA), single-ended interfaces (i.e. DDR3, QSPI) and general purpose
interfaces using LVCMOS drivers that meet timing requirements while minimizing signal integrity (SI)
distortions on the PCB’s signaling traces. Signal trace lengths and flight times are aligned with FR-4
standard specification for PCBs.
Several different PCB layout stack-up examples have been presented to illustrate a typical number of
layers, signal assignments and controlled impedance requirements. Different Device interface signals
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final
layer count and layer assignments in each customer’s PCB design.
This guideline must be used as a supplement in complement to TI’s Application Processor, Power
Management IC (PMIC) and Audio Companion components along with other TI component technical
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out
Spreadsheet, Application Notes, etc.).
NOTE
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or
statutory, including any implied warranty of merchantability of fitness for a specific purpose,
for customer boards. The data described in this appendix are intended as guidelines only.
NOTE
These PCB guidelines are in a draft maturity and consequently, are subject to change
depending on design verification testing conducted during IC development and validation.
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8.1.1
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Initial Requirements and Guidelines
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.
The trace width and spacing must be chosen to yield the recommended differential impedance. For more
information see Section 8.5.1.
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power
nets from PMIC to the device.
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system
ESD.
8.2
Power Optimizations
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):
• Section 8.2.1, Step 1: PCB Stack-up
• Section 8.2.2, Step 2: Physical Placement
• Section 8.2.3, Step 3: Static Analysis
• Section 8.2.4, Step 4: Frequency Analysis
8.2.1
Step 1: PCB Stack-up
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these recommendations:
• Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground
planes must be solid to provide continuous return path for return current.
• Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)
maximizes the capacitance.
• Optimize the power and ground plane pair carrying high current supplies to key component power
domains as close as possible to the same surface where these components are placed (see Figure 81). This will help to minimize “loop inductance” encountered between supply decoupling capacitors and
component supply inputs and between power and ground plane pairs.
NOTE
1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,
helping to reduce Processor junction temperatures. In addition, it is preferable to have the
power / ground planes be adjacent to the PCB surface on which the Processor is mounted.
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Capacitor
Trace
DIE
Package
Via
3
1
Power/Ground
2
Ground/Power
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
Loop inductance
SPRS906_PCB_STACKUP_01
Figure 8-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
significant impact on the parasitic inductances of power current path as shown in Figure 8-1. For this
reason, it is recommended to consider layer order in the early stages of the PCB PDN design cycle,
putting high-priority supplies in the top half of the stackup (assuming high load and priority components
are mounted on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown
in the examples below (vias have parasitic inductances which impact the bottom layers more, so it is
advised to put the sensitive and high-priority power supplies on the top/same layers).
8.2.2
Step 2: Physical Placement
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The
following points are important for optimizing a PCB’s PDN:
• Minimizing the physical distance between power sources and key high load components is the first
step toward optimization. Placing source and load components on the same side of the PCB is
desirable. This will minimize via inductance impact for high current loads and steps
• External trace routing between components must be as wide as possible. The wider the traces, the
lower the DC resistance and consequently the lower the static IR drop.
• Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance
and improved high frequency performance of the PDN.
• Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling
capacitors, power inductors and current sensing resistors). Do not share vias among multiple
capacitors for connecting power supply and ground planes.
• Placement of vias must be as close as possible or even within a component’s solder pad if the PCB
technology you are using provides this capability.
• To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be
evaluated to determine the appropriate number of vias required to connect components.
Adding vias to bring the “via-to-pad” ratio to 1:1 will improve PDN performance.
• For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd
shield can be used to isolate coplanar supplies that may have high step currents or high frequency
switching transitions from coupling into low-noise supplies.
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vdd_mpu
vss
vdd
PCB_PO_8
Figure 8-2. Coplanar Shielding of Power Net Using Ground Guard-band
8.2.3
Step 3: Static Analysis
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the
board. Robust system performance can only be ensured by understanding how the system elements will
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC
Analysis.
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops
across power and ground planes, traces and vias. This ensures the application processor’s internal
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.
Components that are distant from their power source are particularly susceptible to IR drop. Designs that
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,
and copper area needed for load currents.
The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
L
r
1
=
σ ×t t
l
R = Rs ×
w
Rs =
W
t
SPRS906_PCB_STATIC_01
Figure 8-3. Depiction of Sheet Resistivity and Resistance
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate
power at high currents even though their resistance may be very small. Both voltage drop and power
dissipation are proportional to the resistance of the conductor.
Figure 8-4 shows a PCB-level static IR drop budget defined between the power management device
(PMIC) pins and the application processor’s balls when the PMIC is supplying power.
• It is highly recommended to physically place the PMIC as close as possible to the processor and on
the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for
the highest current rail.
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The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
L
r
1
=
σ ×t t
l
R = Rs ×
w
Rs =
W
t
SPRS906_PCB_STATIC_01
Figure 8-4. Static IR Drop Budget for PCB Only
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR
or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC
operating conditions) across power and ground pads of the transistors of the application processor device
is within a specified value of the nominal voltage for proper functionality of the device.
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal
voltage. For a 1.35-V supply, this would be ≤20 mV.
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration
violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is
recommended to perform the following analyses:
• Lumped resistance/IR drop analysis
• Distributed resistance/IR drop analysis
NOTE
The PMIC companion device supporting this processor has been designed with voltage
sensing feedback loop capabilities that enable a remote sense of the SMPS output voltage at
the point of use.
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As
such, the effective resistance of the PDN within this loop should be determined in order to optimize
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the
entire PDN route from SMPS output pin/ball to the Processor input power.
In the following sections each methodology is described in detail and an example has been provided of
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their
PCB PDN design.
8.2.3.1
PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement Figure 8-5 illustrates the pin-grouping/lumped concept.
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
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For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Sources
Multiport net
Sources
Branch
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Port/Pin
Sinks
Sinks
SPRS906_PCB_PDN_01
Figure 8-5. Pin-grouping concept: Lumped and Distributed Methodologies
8.2.4
Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
NOTE
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
•
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and
resistance.
Figure 8-6 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC
circuit with effective series resistance (ESR) and effective series inductance (ESL).
C
ESL
ESR
SPRS906_PCB_FREQ_01
Figure 8-6. Characteristics of a Real Capacitor With ESL and ESR
The magnitude of the impedance of this series model is given as:
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Z =
1 ö
æ
ESR 2 +ωESL
ç ωESL - ωC ÷
ø
è
2
where : w = 2π¦
SPRS906_PCB_FREQ_02
Figure 8-7. Series Model Impedance Equation
Figure 8-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of
55 MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance
and inductance as shown in the equation above.
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+01
1.0e+00
1.0e–01
1.0e–02
XC=1/ωC
XL=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
1.00e+006
1.00e+008
Frequency (MHz)
SPRS906_PCB_FREQ_03
Figure 8-8. Typical Impedance Profile of a Capacitor
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in Figure 8-1. The capacitor mounting inductance and resistance
values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use
footprints that have the lowest inductance configuration as shown in Figure 8-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in Figure 8-9. If the PCB manufacturing processes allow it and if
cost-effective, via-in-pad (VIP) geometries are strongly recommended.
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In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in Figure 8-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in Figure 89 are known as:
• 2-via, Skinny End Exit (2vSEE)
• 2-via, Wide End Exit (2vWEE)
• 2-via, Wide Side Exit (2vWSE)
• 4-via, Wide Side Exit (4vWSE)
• 2-via, In-Pad (2vIP)
Via
Via-in-pad
Pad
Trace
Mounting geometry for reduced inductance
SPRS906_PCB_FREQ_04
Figure 8-9. Capacitor Placement Geometry for Improved Mounting Inductance
NOTE
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see Figure 89).
2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
minimum inductance for top vs bottom-side placement.
3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
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5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the CORE power domain has yielded the vdd Impedance vs Frequency response
shown in Section 8.3.7.2, vdd Example Analysis. As the example shows the overall CORE PDN Reff meets
the maximum recommended PDN resistance of 10mΩ.
8.2.5
System ESD Generic Guidelines
8.2.5.1
System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the lowresistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in Figure 8-10) from connector to external protection because the interconnect may see between 15A to 30-A current in a short period of time during the ESD event.
Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Connector
Stub
inductance
Interconnection
inductance
vcc
Signal
VCC
VCC
Protected
circuit
Stub
inductance
Minimize such
inductance by
optimizing layout
Ground
inductance
Keep distance
between protected
circuit and external
protection
Signal
ESD
strike
External
protection
Keep external
protection closed by
connector
SPRS906_PCB_ESD_01
Figure 8-10. Placement Recommendation for an ESD External Protection
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NOTE
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground
the ESD protection to the board ground rather than any local ground (example isolated shield
or audio ground).
8.2.5.2
•
•
•
•
•
•
•
•
Miscellaneous EMC Guidelines to Mitigate ESD Immunity
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB
edges.
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the
drivers to minimize ESD coupling.
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled
current on the ring.
Fill unused portions of the PCB with ground plane.
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and
ground planes.
Shield long line length (strip lines) to minimize radiated ESD.
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in
one area.
BAD
BETTER
SPRS906_PCB_EMC_01
•
8.2.5.3
Figure 8-11. Trace Examples
Always route signal traces and their associated ground returns as close to one another as possible to
minimize the loop area enclosed by current flow:
– At high frequencies current follows the path of least inductance.
– At low frequencies current flows through the path of least resistance.
ESD Protection System Design Consideration
ESD protection system design consideration is covered in Section 8.5.2.2 of this document. The following
are additional considerations for ESD protection in a system.
• Metallic shielding for both ESD and EMI
• Chassis GND isolation from the board GND
• Air gap designed on board to absorb ESD energy
• Clamping diodes to absorb ESD energy
• Capacitors to divert ESD energy
• The use of external ESD components on the DP/DM lines may affect signal quality and are not
recommended.
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8.2.6
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EMI / EMC Issues Prevention
All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed
by the EMC regulations if some preventative steps are not taken.
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked
up by the circuitry interconnections.
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.
8.2.6.1
Signal Bandwidth
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW
with respect to its rise time, tR:
fBW ≈ 0.35 / tR
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start
to decay at 40 dB per decade instead of 20 dB per decade.
8.2.6.2
Signal Routing
8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN
transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved
protection it is recommended to place these emission sources in a shield can. If the shield can have a
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.
Leave some space between the lid and the components under it to limit the high-frequency currents
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of
interest; see Figure 8-8, Typical Impedance Profile of a Capacitor.
8.2.6.2.2 Signal Routing—Outer Layer Routing
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to
route only static signals and ensure that these static signals do not carry any high-frequency components
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor
near the signal source.
Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,
because their emissions energy is concentrated at the discrete harmonics and can become significant
even with poor radiators.
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is
effective only if the distance between the trace sides and the ground is smaller that the trace height above
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a
ground reference near the trace edges can increase EMI: see Section 8.2.6.3, Ground Guidelines.
8.2.6.3
Ground Guidelines
8.2.6.3.1 PCB Outer Layers
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be
filled with ground after the routing is completed and connected with an adequate number of vias to the
ground on the inner ground planes.
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8.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
8.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
8.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in Figure 8-12 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS906_PCB_EMC_02
Figure 8-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS906_PCB_EMC_03
Figure 8-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in Figure 8-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
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8.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
8.3
Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
8.3.1
General Constraints and Theory
•
•
•
•
•
•
•
342
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without
remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input
including any ground return losses.
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 5% of supply voltage when using
PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor
node to Device’s supply input including any ground return losses.
PMIC component DM and guidelines should be referenced for the following:
– Routing remote feedback sensing to optimize per each SMPS’s implementation
– Selecting power filtering capacitor values and PCB placement.
Max Effective Resistance (Reff) budget can range from 4 – 50mΩ for key Device power rails not
including ground returns depending upon maximum load currents and maximum DC voltage drop
budget (as discussed above).
Max Device supply input voltage difference budget of 5mV under max current loading shall be
maintained across all balls connected to a common power rail. This represents any voltage difference
that may exist between a remote sense point to any power input.
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending
upon maximum transient load currents.
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device
including ground returns are as follows:
– +/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~
200kHz)
– +/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
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Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output
power filter node including ground return is determined by applying the Frequency Domain Target
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general
regions of interest as can be seen in Figure 8-14.
– 1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very
low due to power filtering & bulk capacitor values when PDN has very low trace resistance (i.e.
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over
this low frequency range. This will ensure that a max transient current event will not cause a
voltage drop more than the PMIC’s current step response can support (typ 3%).
– 2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient
current event will not cause a voltage drop to be more than 5% of the min supply voltage.
Figure 8-14. PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events
such as transient noise, AC ripple, voltage dips etc.
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2.Typical max transient current is defined as 50% of max current draw possible.
8.3.2
Voltage Decoupling
Recommended power supply decoupling capacitors main characteristics for commercial products whose
ambient temperature is not to exceed +85C are shown in table below:
Table 8-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)
Value
Voltage [V]
Package
Stability
Dielectric
Capacitanc Temp Range
Temp
e
[°C]
Sensitivity
Tolerance
[%]
REFERENCE
22µF
6,3
0603
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM188R60J226MEA0L
10µF
4,0
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60G106ME44
4.7µF
6,3
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60J475ME95
2.2µF
6,3
0402
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM155R60J225ME95
1µF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J105MEA2
470nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60G474ME90
220nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J224ME90
100nF
6,3
0201
Class 2
X5R
- / + 20%
-55 to + 85
- / + 15
GRM033R60J104ME19
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation
factor.
Recommended power supply decoupling capacitors main characteristics for automotive products are
shown in table below:
Table 8-2. Automotive Applications Recommended Decoupling Capacitors Characteristics
Value
Voltage [V]
Package
Stability
Dielectric
Capacitanc
Temp
e
Range [°C]
Tolerance
22µF
6,3
1206
Class 2
X7R
- / + 20%
10µF
6,3
0805
Class 2
X7R
- / + 20%
4.7µF
10
0805
Class 2
X7R
2.2µF
6,3
0603
Class 2
(1)(2)
Temp
Sensitivity
[%]
REFERENCE
-55 to + 125
- / + 15
GCM31CR70J226ME23
-55 to + 125
- / + 15
GCM21BR70J106ME22
- / + 20%
-55 to + 125
- / + 15
GCM21BC71A475MA73
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R70J225ME22
1µF
16
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R71C105MA64
470nF
16
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188R71C474MA55
220nF
25
0603
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM188L81C224MA37
100nF
16
0402
Class 2
X7R
- / + 20%
-55 to + 125
- / + 15
GCM155R71C104MA55
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
8.3.3
Static PDN Analysis
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).
This is the total PCB power net routing resistance that is the sum of all the individual power net segments
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.
8.3.4
Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),
Impedance (Z) and PCB Frequency of Interest (Fpcb).
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LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
•
•
Table 8-3. Recommended PDN and Decoupling Characteristics
PDN Analysis:
Supply
Static
Dynamic
(1)(2)(3)(4)(5)
Number of Recommended Decoupling Capacitors
per Supply
Max
Impedance
[mΩ]
Frequency
range
of Interest
[MHz]
100
nF(6)
220
nF
470
nF
1μF
[mΩ]
Dec. Cap.
Max LL(8) (6)
[nH]
2.2
μF
4.7
μF
vdd_mpu
10
2
57
≤20
8
1
1
1
1
1
vdd_dsp, vdd_gpu,
vdd_iva
13
2.5
54
≤20
8
1
1
1
1
1
vdd
27
2
87
≤50
6
1
1
1
1
1
vdds_ddr1
10
2.5
200
≤100
8
4
cap_vbbldo_dsp
N/A
6
N/A
N/A
1
cap_vbbldo_gpu
N/A
6
N/A
N/A
1
cap_vbbldo_iva
N/A
6
N/A
N/A
1
cap_vbbldo_mpu
N/A
6
N/A
N/A
1
cap_vddram_core1
N/A
6
N/A
N/A
1
cap_vddram_core3
N/A
6
N/A
N/A
1
cap_vddram_core4
N/A
6
N/A
N/A
1
cap_vddram_dsp
N/A
6
N/A
N/A
1
cap_vddram_gpu
N/A
6
N/A
N/A
1
cap_vddram_iva
N/A
6
N/A
N/A
1
cap_vddram_mpu
N/A
6
N/A
N/A
1
Max Reff
(7)
2
10
μF
22
μF
1
1
2
1
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Reff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.
8.3.5
Power Supply Mapping
TPS65917 or TPS659039 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
• TI has validated their use with the Device
• Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
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Support for power sequencing requirements (refer to Section 5.9 Power Supply Sequences)
Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the
most stringent of the rails combined should be implemented for the particular supply rail.
It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain,
thereby having a single power supply driving the combined CORE, IVA and GPU domains.
For the combined rail, the following relaxations do apply:
• The AVS voltage of active rail in the combined rail needs to be used to set the power supply
• The decoupling capacitance should be set according to the active rail in the combined rail
Table 8-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS659039 PMIC.
Table 8-4. TPS659039 Power Supply Connections(1)
SMPS
Valid Combination 1:
Reference Platform
Valid Combination 2:
MPU Centric
TPS659039 Current
Rating Limitation (3) (4)
SMPS1/2/3(2)
vdd_mpu
vdd_mpu
SMPS1/2: 6A
SMPS1/2/3: 9A
SMPS3(2)
vdds_ddr1
vdds_ddr1
SMPS3: 3A
SMPS4/5
vdd_dsp
vdd_dsp, vdd_gpu,
vdd_iva
SMPS4/5: 4A
SMPS6
vdd_gpu
vdd
SMPS6: 2-3A
(BOOST_CURRENT=0/1)
SMPS7
vdd
Free
2A
SMPS8
vdd_iva
Free
1A
SMPS9
vdds18v
vdds18v
1A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Dual phase (SMPS1/2) can be used as long as the peak power consumption is maintained below the SMPS1/2 capacity
(a) For the latest rated output current specifications for the TPS659039 device, please refer to the PMIC data manual.
(b) MPU power consumption is highly system dependent. A detailed power consumption estimate must be performed to confirm
compatibility. Example: Single vs Dual MPU, OPP_NOM vs OPP_OD vs OPP_HIGH, TPS659039 configured with VI≥3V vs VI<3V,
etc. Contact your TI representative for details.
(3) Refer to the PMIC data manual for the latest TPS659039 specifications.
(4) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
Table 8-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS65917 PMIC.
Table 8-5. TPS65917 Power Supply Connections
346
TPS65917
Valid
Combination
1:
Valid
Combination 2:
TPS65917
Current Rating
Limitation (1) (3)
SMPS1
vdd_mpu
vdd_mpu
3.5A
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Table 8-5. TPS65917 Power Supply
Connections (continued)
TPS65917
Valid
Combination
1:
Valid
Combination 2:
TPS65917
Current Rating
Limitation (1) (3)
SMPS2
(2)
vdd_dsp,
vdd_gpu,
vdd_iva
vdd
3.5A
SMPS3
(2)
vdd
vdd_dspeve,
vdd_gpu,
vdd_iva
3A
SMPS4
(3)
vdds18v
vdds18v
1.5A
SMPS5
(4)
vdds_ddr1
vdds_ddr1
2A
(1) Refer to the TPS65917 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) DSP, EVE, GPU, and IVAHD power consumption is highly application-specific. Separate analysis must be performed to ensure output
current ratings (average and peak) is within the limits of the PMIC. VDD only supports OPP_NOM.
(3) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
(4) Furthermore, if SMPS5 is used for DDR power, both total memory + SoC power must be within the PMIC limits.
8.3.6
DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65917 PMIC LDOLN output is specifically designed to meet this low noise requirement.
NOTE
For more information about Input Voltage Sources, see Section 6.2 DPLLs, DLLs
Specifications.
Table 8-4 presents the voltage inputs that supply the DPLLs.
Table 8-6. Input Voltage Power Supplies for the DPLLs
8.3.7
POWER SUPPLY
DPLLs
vdda_per
DPLL_PER and PER HSDIVIDER analog power supply
vdda_ddr
DPLL_DDR and DDR HSDIVIDER analog power supply
vdda_debug
DPLL_DEBUG analog power supply
vdda_dsp_iva
DPLL_DSP and DPLL_IVA analog power supply
vdda_core_gmac
DPLL_CORE and HSDIVIDER analog power supply
vdda_gpu
DPLL_GPU analog power supply
vdda_video
DPLL_VIDEO1 analog power supply
vdda_mpu_abe
DPLL_MPU and DPLL_ABE analog power supply
vdda_osc
not DPLL input but is required to be supplied by low noise input voltage
vdda_pll_spare
DPLL_SPARE analog power supply
Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the
vdd_mpu key processor power domain.
NOTE
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
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Example Stack-up
Layer Assignments:
• Layer Top: Signal and Segmented Power Plane
– Processor and PMIC components placed on Top-side
• Layer 2: Gnd Plane1
• Layer 3: Signals
• Layer n: Power Plane1
• Layer n+1: Power Plane 2
• Layer n+2: Signal
• Layer n+3: Gnd Plane2
• Layer Bottom: Signal and Segmented Power Planes
– Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
• ½ oz for all signal layers.
• 1-2oz for all power plane for improved PCB heat spreading
8.3.7.2
vdd Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included)
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
Table 8-7. Example PCB vdd PI Analysis Summary
348
Parameter
Recommendation
OPP
OPP_NOM
Clocking Rate
266 MHz
Voltage Level
1V
Example PCB
1V
Max Current Draw
1A
1A
Max Effective Resistance: Power
Inductor Segment Total Reff
10mΩ
9.7 mΩ
Max Loop Inductance
2.0nH
0.97 –1.75nH
Impedance Target
57mΩ F<20Mhz
57mΩ F<20Mhz
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Figure 8-15 show a PCB layout example and the resulting PI analysis results.
PMIC
SMPS2
L1002
1.0uH, 4.5A, 1616
IHLP-1616ABER1R0M11
CORE_VDD
SoC
SMPS2_SW
C1014
VDD
47uF, 6.3V, X7R, 1210
GCM32ER70J476ME19
C363 , 364, 386, 388 ,
390, 498
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C395
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C394
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C393
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C456
2.2uF, 6.3V, X7R, 0603
GCM188R70J225KE22
C487
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
Figure 8-15. vdd Simplified SCH Diagram
NOTE
PCB Etch Resistance Breakdown, PDN Effective Resistance, and vdd routings are UNDER
DEVELOPMENT!
IR Drop: vdd (PCB Rev Oct25, CAD sPSI v13.1.1)
• Source Conditions: 1V @ 1A
• Power Plane/Trace Effective Resistances
– From PMIC SMPS to SoC load = 9.7mohm
– From Power Inductor to SoC load = 6mohm
– "Open-Loop" Voltage/IR Drop for 1A = 6mV
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Figure 8-16. vdd Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the CORE power domain determined the vdd decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 0.97 –1.75nH and were less than maximum 2.0nH recommended.
NOTE
Comparing loop inductances for capacitors at different distances from the SoC’s input power
balls shows an 18% reduction for caps placed closer. This was derived by averaging the
inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps with
distances less than 600mils (Avg LL = 1.096nH).
Table 8-8. Rail - vdd
Cap Ref
Des
Model Port
#
Loop Inductacne
[nH]
Footprint
Types
PCB Side
Distance to
Ball-Field
[mils]
Value [μF]
Size
C487
10
0.97
4vWSE
Top
521
4.7
0805
C393
6
1.11
4vWSE
Bottom
358
1.0
0603
C394
7
1.12
4vWSE
Bottom
357
0.47
0603
C456
9
1.13
4vWSE
Bottom
403
2.2
0603
C386
3
1.16
2vWSE
Bottom
40
0.1
0402
C395
8
1.18
4vWSE
Bottom
460
0.22
0603
C363
1
1.46
2vWSE
Bottom
40
0.1
0402
C390
5
1.48
2vWSE
Bottom
40
0.1
0402
C364
2
1.74
2vWSE
Bottom
40
0.1
0402
C498
11
1.74
2vWSE
Bottom
40
0.1
0402
C388
4
1.75
2vWSE
Bottom
40
0.1
0402
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Loop Inductance range: 0.97 –1.75nH
Figure 8-17. vdd Decoupling Cap Loop Inductances
Figure 8-18 shows vdd Impedance vs Frequency characteristics.
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173mohm @ 100MHz
87mohm @ 50MHz
27mohm @ 20MHz
9.9mohm @ 10MHz
Figure 8-18. vdd Impedance vs Frequency
8.4
8.4.1
Single-Ended Interfaces
General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
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Line spacing:
– For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see Figure 8-19).
W
D+
S = 2 W = 200 µm
SPRS906_PCB_SE_GND_01
•
•
•
8.4.2
Figure 8-19. Ground Guard Illustration
Length matching (unless otherwise specified):
– For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
– For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
Characteristic impedance
– Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
– For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
• The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
• The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
• The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
• The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-20.
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Propagation delays and matching:
– A to C = C to D = E to F.
– Matching skew: < 60pS
– A to B < 450pS
– B to C = as small as possible (<60pS)
Locate both R2 resistors
close together near the QSPI device
A
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
D
qspi1_rtclk
E
F
QSPI device
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS906_PCB_QSPI_01
Figure 8-20. QSPI Interface High Level Schematic
NOTE
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for finetuning if needed.
8.5
8.5.1
Differential Interfaces
General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
• As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
• Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
• Minimize external components on differential lanes (like external ESD, probe points).
• Through-hole pins are not recommended.
• Differential lanes mustn’t cross image planes (ground planes).
• No sharp bend on differential lanes.
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8.5.2
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
USB 2.0 Board Design and Layout Guidelines
This section discusses schematic guidelines when designing a universal serial bus (USB) system.
8.5.2.1
Background
Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs
operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.
The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto
the cable.
When designing a USB board, the signals of most interest are:
• Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
• Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily
filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4
(analog ground) must be able to return the current during data transmission, and must be filtered
sparingly.
• Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,
these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6
MHz (full speed), and 750 kHz (low speed).
• External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz
fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is
highly recommended.
8.5.2.2
USB PHY Layout Guide
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.1 General Routing and Placement
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
• Place the USB PHY and major components on the un-routed board first. For more details, see
Section 8.5.2.2.2.3.
• Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
• Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
• Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
• Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
• Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
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8.5.2.2.2 Specific Guidelines for USB PHY Layout
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for
the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip
as possible to minimize the inductance of the line and noise contributions to the system. An analog and
digital supply example is shown in Figure 8-21. In case of multiple power supply pins with the same
function, tie them up to a single low-impedance point in the board and then add the decoupling capacitors,
in addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance.
Take both EMI and jitter into account before altering the configuration.
Analog
Power Supply
Ferrite Bead
0.1 µF
Digital
Power Supply
0.01 µF
0.001 µF
1 µF
0.01 µF
0.001 µF
1 µF
SoC Board
AGND
Ferrite Bead
0.1 µF
DGND
SPRS906_PCB_USB20_01
Figure 8-21. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
Consider the recommendations listed below to achieve proper ESD/EMI performance:
• Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
• Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.
• If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the
immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.
8.5.2.2.2.2 Analog, Digital, and PLL Partitioning
If separate power planes are used, they must be tied together at one point through a low-impedance
bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail
close to the device. The analog ground, digital ground, and PLL ground must be tied together to the lowimpedance circuit board ground plane.
8.5.2.2.2.3 Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers
is recommended; two signal layers separated by a ground and power layer as shown in Figure 8-22.
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Signal 1
GND Plane
Power Plane
Signal 2
SPRS906_PCB_USB20_02
Figure 8-22. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this
layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in
the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must
be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
8.5.2.2.2.4 Cable Connector Socket
Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists
immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground
before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors
coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop
out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note
that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their
respective planes as soon as possible, respecting the filtering that may be in place between the connector
pin and the plane. See Figure 8-23 for a schematic example.
Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting
onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω
and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the
cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,
VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be
valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to
approximately 1 GHz, as shown in Figure 8-23.
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5
SHIELD_GND
4
GND
3
DP
2
DM
1
VBUS
Ferrite Bead
+5 V
U2
6
SHIELD_GND
USB Socket
U1
Ferrite Bead
SPRS906_PCB_USB20_03
Figure 8-23. USB Connector
8.5.2.2.2.5 Clock Routings
To address the system clock emissions between devices, place a ~10 to 130 Ω resistor in series with the
clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed
oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this
resistor should be as small as possible to get the desired effect. Place the resistor close to the device
generating the clock signal. If an external crystal is used, follow the guidelines detailed in the Selection
and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance
from the center of the clock trace to the center of any adjacent signal trace should be at least three times
the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall
times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of
the traces running parallel between the devices. Avoid using right angles when routing traces to minimize
the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces
beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown in
Figure 8-24.
3W
3W
W
Trace
SPRS906_PCB_USB20_04
Figure 8-24. 3W Spacing Rule
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8.5.2.2.2.6 Crystals/Oscillator
Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see Figure 8-25). Note
that frequencies from power sources or large capacitors can cause modulations within the clock and
should not be placed near the crystal. In these instances, errors such as dropped packets occur. A
placeholder for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator
startup.
Power is proportional to the current squared. The current is I = C*dv/dt, because dv/dt is a function of the
PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2
and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and
Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
X1
0.1 µF
Power Pins
XTAL
X0
0.001 µF
USB PHY
SPRS906_PCB_USB20_05
Figure 8-25. Power Supply and Clock Connection to the USB PHY
8.5.2.2.2.7 DP/DM Trace
Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed
operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on
the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the
traces tend to behave like an antenna and picks up noise generated by the surrounding components in
the environment. To minimize the effect of this behavior:
• DP/DM traces should always be matched lengths and must be no more than 4 inches in length;
otherwise, the eye opening may be degraded (see Figure 8-26).
• Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and
within two mils in length of each other. The measurement for trace length must be started from
device's balls.
• A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω
± 10%.
• DP/DM traces should not have any extra components to maintain signal integrity. For example, traces
cannot be routed to two USB connectors.
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Minimize
This Distance
VBUS
GND
D+
USB PHY
Cable
Connector
D+
Connector
D-
D-
SPRS906_PCB_USB20_06
Figure 8-26. USB PHY Connector and Cable Connector
8.5.2.2.2.8 DP/DM Vias
When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
8.5.2.2.2.9 Image Planes
An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing
plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a
USB board, the best image plane is the ground plane because it can be used for both analog and digital
circuits.
• Do not route traces so they cross from one plane to the other. This can cause a broken RF return path
resulting in an EMI radiating loop as shown in Figure 8-27. This is important for higher frequency or
repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal
plane above a solid ground plane.
• Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces
immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,
DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is
connected to the ground plane through vias.
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Do
Don't
SPRS906_PCB_USB20_07
•
Figure 8-27. Do Not Cross Plane Boundaries
Do not overlap planes that do not reference each other. For example, do not overlap a digital power
plane with an analog power plane as this produces a capacitance between the overlapping areas that
could pass RF emissions from one plane to the other, as shown in Figure 8-28.
Analog Power Plane
Unwanted Capacitance
Digital Power Plane
SPRS906_PCB_USB20_08
•
Figure 8-28. Do Not Overlap Planes
Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF
return loop, as shown in Figure 8-29.
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RF Return
Current
RF Return
Current
Slot in Image Plane
Slot in Image Plane
Bad
Better
SPRS906_PCB_USB20_09
Figure 8-29. Do Not Violate Image Planes
8.5.2.2.2.10 Power Regulators
Switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive
areas on a circuit board. Therefore, the switching power regulator should be kept away from the DP/DM
signals, the external clock crystal (or clock oscillator), and the USB PHY.
8.5.2.3
•
•
•
8.5.3
References
USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/
High
Speed
USB
Platform
Design
Guidelines,
Intel,
http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf
Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122)
2000,
USB 3.0 Board Design and Layout Guidelines
This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB
design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew,
signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to
ensure the USB3.0 interface requirements are met. The design rules stated within this document are
targeted at DEVICE mode electrical compliance. HOST mode and/or systems that do not include the 3m
USB cable and far-end 11-inch PCB trace required by DEVICE mode compliance testing may not need
the complete list of optimizations shown in this document; however, applying these optimizations to HOST
mode systems will lead to optimal DEVICE mode performance.
8.5.3.1
USB 3.0 interface introduction
The USB 3.0 has two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps
are needed on the board for TX traces.
Figure 8-30 present high level schematic diagram for USB 3.0 interface.
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GND
Device
AC Caps
GND GND
CMF
Vias (if necessary)
Vias (if necessary)
usb_rxp0
usb_rxn0
CMF
Vias (if necessary)
Vias (if necessary)
GND
USB 3.0
usb_txp0
usb_txn0
USB 3.0 connector
www.ti.com
Place near connector, and keep routing short
SPRS85x_PCB_USB30_1
Figure 8-30. USB 3.0 Interface High Level Schematic
NOTE
ESD components should be on a PCB layer next to a system GND plane layer so the
inductance of the via to GND will be minimal.
If vias are used, place the vias near the AC Caps or CMFs and under the SoC BGA, if
necessary.
AC Cap
SoC TX
USB 3.0 connector
via
Figure 8-31 present placement diagram for USB 3.0 interface.
AC Cap
via
via
CMF
SoC RX
via
CMF
SPRS85x_PCB_USB30_2
Figure 8-31. USB 3.0 placement diagram
Table 8-9. USB1 Component Reference
INTERFACE
COMPONENT
SUPPLIER
PART NUMBER
ESD
TI
TPD1E05U06
USB3 PHY
CMF
Murata
DLW21SN900HQ2
C
-
100nF (typical size: 0201)
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8.5.3.2
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USB 3.0 General routing rules
Some general routing guidelines regarding USB 3.0:
• Avoid crossing splits reference plane(s).
• Shorter trace length is preferred.
• Minimize the via usage and layer transition
• Keep large spacing between TX and RX pairs.
• Intra-lane delay mismatch between DP and DM less than 1ps. Same for RXp and RXn.
• Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
• Distance between ESD protection device and USB connector should be as short as possible.
• Distance between AC capacitors (TX only) and CMF should be as short as possible.
• USB 3.0 signals should always be routed over an adjacent ground plane.
Table 8-10 and Table 8-11 present routing specification and recommendations for USB1 in the device.
Table 8-10. USB1 Routing Specifications
PARAMETER
MIN
TYP
MAX
UNIT
3500
Mils
3
6
Mils
0
Stubs
90
96.3
Ω
2
Vias
Number of ground plane cuts allowed within
USB3 routing region (except for specific
ground carving as explained in this
document)
0
Cuts
Number of layers between USB3.0 routing
region and reference ground plane
0
Layers
Device balls to USB 3.0 connector trace
length
Skew within a differential pair
Number of stubs allowed on TX/RX traces
TX/RX pair differential impedance
83.7
Number of vias on each TX/RX trace
Differential pair to any other trace spacing
2xDS
3xDS
PCB trace width
6
Mils
PCB BGA escape via pad size
18
Mils
PCB BGA escape via hole size
10
Mils
1.
2.
3.
4.
Vias must be used in pairs and spaced equally along a signal path.
DS = differential spacing of the traces.
Exceptions may be necessary in the SoC package BGA area.
GND guard-bands on the same layer may be closer, but should not be allowed to affect the impedance
of the differential pair routing. GND guard-bands to isolate USB3.0 differential pairs from all other
signals are recommended.
Table 8-11. USB1 Routing Recommendations
364
Item
Description
Reason
ESD location
Place ESD component on same layer as connector (no via or stub to
ESD component)
Eliminate reflection loss from via
& stub to ESD
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
CMF part number
DLW21SN900HQ2
Manufacturer’s recommended
device
Connector
Use USB3.0 connector with supporting s-parameter model
Enable full signal chain
simulation
Carve Ground
Carve GND underneath AC Caps, ESD, CMF, and connector
Minimize capacitance under ESD
and CMF
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Table 8-11. USB1 Routing Recommendations (continued)
Item
Description
Reason
Round pads
Minimize pad size and round the corners of the pads for the ESD
and CMF components
Minimize capacitance
Vias
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Vias significantly degrade signal
integrity at 2.5GHz
via
Figure 8-32 presents an example layout, demonstrating the “carve GND” concept.
USB 3.0 connector
AC Cap
CMF
via
via
AC Cap
via
CMF
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
SPRS85x_PCB_USB30_3
Figure 8-32. USB 3.0 Example “carve GND” layout
8.5.4
HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
8.5.4.1
HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
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1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface
2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low speed interfaces, so nothing special is required for PCB layout of these
signals.
The TMDS channels are high speed differential pairs and therefore require the most care in layout.
Specifications for TMDS layout are below.
Figure 8-33 shows the HDMI interface schematic.
CMF
HDMI connector
hdmi_tx*hdmi_tx*+
GND
HDMI
GND
Device
Place near connector, and keep routing short
SPRS85x_PCB_HDMI_1
Figure 8-33. HDMI Interface High Level Schematic
Figure 8-34 presents placement diagram for HDMI interface.
HDMI connector
CMF
CMF
CMF
CMF
SPRS85x_PCB_HDMI_2
Figure 8-34. HDMI Placement Diagram
Table 8-12. HDMI Component Reference
INTERFACE
HDMI
366
DEVICE
SUPPLIER
PART NUMBER
ESD
TI
TPD1E05U06
CMF
Murata
DLW21SN900HQ2
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SPRS956B – MARCH 2016 – REVISED JANUARY 2017
TMDS General Routing Guidelines
The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance
and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because
differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 ohms impedance traces as possible. For best accuracy, work with your PCB fabricator to
ensure this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s
easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced
skin effect and therefore often result in better signal integrity.
Some general routing guidelines regarding TMDS:
• Avoid crossing splits reference plane(s).
• Shorter trace length is preferred.
• Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
• Distance between ESD protection device and HDMI connector should be as short as possible.
Table 8-13 shows the routing specifications for the TMDS signals.
Table 8-13. TMDS Routing Specifications
PARAMETER
MIN
TYP
Device balls to HDMI header trace length
Skew within a differential pair
3
Number of stubs allowed on TMDS traces
MAX
UNIT
4000
Mils
5
Mils
0
stubs
TMDS pair differential impedance
90
100
110
Ω
TMDS single-ended impedance
54
60
66
Ω
0
Vias
2×DS
3xDS
Number of vias on each TMDS trace
TMDS differential pair to any other trace spacing(1) (2) (3)
Number of ground plane cuts allowed within HDMI routing region (except for specific
ground carving as explained in this document)
Number of layers between HDMI routing region and reference ground plane
PCB trace width
Mils
0
Cuts
0
Layers
4.4
Mils
(1) DS = differential spacing of the traces.
(2) Exceptions may be necessary in the SoC package BGA area.
(3) GND guard-bands may be closer, but should not be allowed to affect the impedance of the differential pair routing. GND guard-bands to
isolate HDMI differential pairs from all other signals is recommended.
Table 8-14. TDMS Routing Recommendations
Item
Description
Reason
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
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Table 8-14. TDMS Routing Recommendations (continued)
Item
Description
Reason
Carve Ground
Carve GND underneath ESD and CMF
Minimize capacitance under ESD
and CMF
Round pads
Reduce pad size and round the corners of the pads for the ESD and
CMF components
Minimize capacitance
Routing layer
Route all signals only on the same layer as SoC
Minimize reflection loss
Figure 8-35presents an example layout, demonstrating the “carve GND” concept.
HDMI connector
CMF
ia
v AC Cap
CMF
CMF
a
iv AC Cap
a
iv
CMF
CMF
a
iv
CMF
Top Layer: Routing from SoC through CMF,
and ESD to connector.
Layer2, GND: Gaps carved in GND underneath,
CMF, ESD, and connector.
SPRS85x_PCB_HDMI_3
Figure 8-35. HDMI Example “carve GND” layout
8.5.4.3
TPD5S115
The TPD5S115 is an integrated HDMI companion chip solution. The device provides a regulated 5 V
output (5VOUT) for sourcing the HDMI power line. The TPD5S115 exceeds the IEC61000-4-2 (Level 4)
ESD protection level.
8.5.4.4
HDMI ESD Protection Device (Required)
Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the processor’s outputs. Therefore this HDMI interface requires the use of an ESD protection chip to
provide adequate ESD.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should be ESD protection circuit capacitance be more than 5pF.
TI manufactures these devices that provide ESD protection for HDMI signals such as the TPDxE05U06.
For more information see the www.ti.com website.
8.5.4.5
PCB Stackup Specifications
Table 8-15 shows the stackup and feature sizes required for HDMI.
Table 8-15. HDMI PCB Stackup Specifications
368
PARAMETER
MIN
TYP
MAX
UNIT
PCB Routing/Plane Layers
4
6
-
Layers
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Table 8-15. HDMI PCB Stackup Specifications (continued)
PARAMETER
MIN
TYP
MAX
UNIT
Signal Routing Layers
2
3
-
Layers
Number of ground plane cuts allowed within HDMI routing
region
-
-
0
Cuts
Number of layers between HDMI routing region and
reference ground plane
-
-
0
Layers
PCB Trace width
8.5.4.6
4
Mils
Grounding
Each TMDS channel has its own shield pin and they should be grounded to provide a return current path
for the TMDS signal.
8.5.5
SATA Board Design and Layout Guidelines
The device provides one SATA port. This section provides the timing specification for the SATA interface
as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace
skew, signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design
work to ensure the SATA interface requirements are met.
8.5.5.1
SATA Interface Schematic
Figure 8-36 shows the data portion of the SATA interface schematic.
DEVICE
SATA Interface
sata1_rxn0
C
sata1_rxp0
C
sata1_txn0l
C
sata1_txp0
C
SATA
Connector
SPRS906_PCB_SATA_01
Figure 8-36. SATA Interface High Level Schematic
NOTE
AC coupling capacitors (C) are required on the receive and transmit data pairs. Table 8-16
shows the requirements for these capacitors.
Table 8-16. SATA AC Coupling Capacitors Requirements
PARAMETER
MIN
TYP
MAX
UNIT
SATA AC coupling capacitor value
0.3
10
12
nF
0402
0603
EIA(1)(2)
SATA AC coupling capacitor package size
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.5.2
Compatible SATA Components and Modes
Table 8-17 shows the compatible SATA components and supported modes. Note that the only supported
configuration is an internal cable from the processor host to the SATA device.
Table 8-17. Compatible SATA Components and Modes
PARAMETER
MIN
MAX
UNIT
Transfer Rates
1.5
3
Gbps
SUPPORTED
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Table 8-17. Compatible SATA Components and Modes (continued)
8.5.5.3
PARAMETER
MIN
MAX
UNIT
SUPPORTED
Internal Cable
-
-
-
YES
PCB Stackup Specifications
Table 8-18 shows the stackup and feature sizes required for these types of SATA connections.
Table 8-18. SATA PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within SATA routing
region
-
-
0
Cuts
Number of layers between SATA routing area and
reference plane
-
-
0
Layers
8.5.5.4
PCB Routing clearance
4
Mils
PCB Trace width
4
Mils
Routing Specifications
The SATA data signal traces must be routed to achieve 100 Ohms (+/-10%) differential impedance and 60
ohms (+/-10%) single ended impedance. The signal ended impedance is required because differential
signals can’t be closely coupled on PCBs and therefore single ended impedance becomes important. 60
ohms is chosen for the single ended impedance to minimize problems caused by too low an impedance.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 100 ohms differential and 60 ohms single ended impedance traces as possible. For best
accuracy, work with your PCB fabricator to ensure this impedance is met.
Table 8-19 shows the routing specifications for the SATA data signals.
Table 8-19. SATA Routing Specifications
PARAMETER
MIN
TYP
SATA signal trace length (device balls to SATA connector)
MAX
UNIT
3050(1)
Mils
Differential pair trace skew matching
5
Mils
Number of stubs allowed on SATA traces(2)
0
stubs
TX/RX pair differential impedance
90
100
110
Ω
TX/RX single-ended impedance
54
60
66
Ω
0
Vias
Number of vias on each SATA trace
SATA differential pair to any other trace spacing
2×DS(3)
(1) Beyond this, signal integrity may suffer.
(2) Inline pads may be used for probing.
(3) DS = differential spacing of the SATA traces.
Table 8-20. SATA Routing Recommendations
Item
ESD part number
370
Applications, Implementation, and Layout
Description
Reason
None
ESD suppression generally not
used on SATA
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8.5.6
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
PCIe Board Design and Layout Guidelines
The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion.
8.5.6.1
PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCIe revision 2.0 specification. Please refer to the
PCIe specifications for all connections that are described in it. Those recommendations are more
descriptive and exhaustive than what is possible here.
The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
8.5.6.1.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. Table 8-21 shows the requirements for
these capacitors.
Table 8-21. PCIe AC Coupling Capacitors Requirements
PARAMETER
MIN
PCIe AC coupling capacitor value
90
PCIe AC coupling capacitor package size
TYP
MAX
UNIT
100
110
nF
0402
0603
EIA(1)(2)
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
8.5.6.1.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is
unimportant because each signal can change its polarity on die inside the chip. This means polarity within
a lane is unimportant for layout.
8.5.6.2
Non-standard PCIe connections
The following sections contain suggestions for any PCIe connection that is NOT described in the official
PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor
connection.
8.5.6.2.1 PCB Stackup Specifications
Table 8-22 shows the stackup and feature sizes required for these types of PCIe connections.
Table 8-22. PCIe PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within PCIe routing
region
-
-
0
Cuts
Number of layers between PCIe routing area and reference
plane (1)
-
-
0
Layers
PCB Routing clearance
4
Mils
PCB Trace width
4
Mils
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(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
8.5.6.2.2 Routing Specifications
8.5.6.2.2.1 Impedance
The PCIe data signal traces must be routed to achieve 100-Ω (±10%) differential impedance and 60-Ω
(±10%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG (www.pcisig.com).
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met. See Table 8-23 below.
8.5.6.2.2.2 Differential Coupling
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production. For PCBs with very tight space limitations (which are usually small) this can work, but for
most PCBs, the loosely coupled option is probably best.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and
trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate
impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect
and therefore often result in better signal integrity with a larger eye diagram opening.
Table 8-23 shows the routing specifications for the PCIe data signals.
Table 8-23. PCI-E Routing Specifications
PARAMETER
MIN
TYP
PCIe signal trace length
Differential pair trace matching
MAX
UNIT
4700(1)
Mils
5
Number of stubs allowed on PCIe traces(3)
TX/RX pair differential impedance
90
100
TX/RX single-ended impedance
54
60
(2)
Mils
0
stubs
110
Ω
66
Ω
Pad size of vias on PCIe trace
25(4)
Mils
Hole size of vias on PCIe trace
14
Mils
Number of vias on each PCIe trace
0
Vias
PCIe differential pair to any other trace spacing
2×DS(5)
(1) Beyond this, signal integrity may suffer.
(2) For example, RXP0 within 5 Mils of RXN0.
(3) Inline pads may be used for probing.
(4) 35-Mil antipad maximum recommended.
(5) DS = differential spacing of the PCIe traces.
Table 8-24. PCI-E Routing Recommendations
Item
ESD part number
372
Applications, Implementation, and Layout
Description
Reason
None
ESD suppression generally not
used on PCIe
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8.5.6.2.2.3 Pair Length Matching
Each signal in the differential pair should be matched to within 5 mils of its matching differential signal.
Length matching should be done as close to the mismatch as possible.
8.5.6.3
LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
• External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
• Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
• External AC coupling capacitors described in Table 8-25 should be populated at the ljcb_clkn /
ljcb_clkp inputs.
• All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External nearside termination to ground described in Table 8-26 is required on both of the ljcb_clkn / ljcb_clkp outputs
in this mode.
Table 8-25. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
ljcb_clkn / ljcb_clkp AC coupling capacitor value
100
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
0402
MAX
UNIT
nF
EIA(1)(2)
0603
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
Table 8-26. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
Ohms
8.5.7
CSI2 Board Design and Routing Guidelines
The MIPI D-PHY signals include the CSI2_0 and CSI2_1 camera serial interfaces to or from the Device.
For more information regarding the MIPI-PHY signals and corresponding balls, see Table 4-7, CSI2 Signal
Descriptions.
For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).
In the next section, the PCB guidelines of the following differential interfaces are presented:
• CSI2_0 and CSI2_1 MIPI CSI-2 at 1.5 Gbps
Table 8-27 lists the MIPI D-PHY interface signals in the Device.
Table 8-27. MIPI D-PHY Interface Signals in the Device
SIGNAL NAME
BOTTOM BALL
SIGNAL NAME
BOTTOM BALL
csi2_0_dx0
AE1
csi2_0_dy0
AD2
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Table 8-27. MIPI D-PHY Interface Signals in the Device (continued)
8.5.7.1
SIGNAL NAME
BOTTOM BALL
SIGNAL NAME
BOTTOM BALL
csi2_0_dx1
AF1
csi2_0_dy1
AE2
csi2_0_dx2
AF2
csi2_0_dy2
AF3
csi2_0_dx3
AH4
csi2_0_dy3
AG4
csi2_0_dx4
AH3
csi2_0_dy4
AG3
csi2_1_dx0
AG5
csi2_1_dy0
AH5
csi2_1_dx1
AG6
csi2_1_dy1
AH6
csi2_1_dx2
AH7
csi2_1_dy2
AG7
CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
8.5.7.1.1 General Guidelines
The general guidelines for the PCB differential lines are:
• Differential trace impedance Z0 = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)
• Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30
cm with common FR4 PCB and flex materials.
NOTE
Longer interconnect length can be supported at the expense of detailed simulations of the
complete link including driver and receiver models.
The general rule of thumb for the space S = 2 × W is not designated (see Figure 8-19, Guard Illustration).
It is because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The
electrical performance will be checked with the frequency-domain specification. Even though the designer
does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain
specification.
Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed
differential implementation, the pairs must be loosely coupled.
8.5.7.1.2 Length Mismatch Guidelines
8.5.7.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
The guidelines of the length mismatch for CSI-2 are presented in Table 8-28.
Table 8-28. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)
PARAMETER
TYPICAL VALUE
UNIT
Operating speed
1500
Mbps
UI (bit time)
667
ps
Intralane skew
Have to satisfy mode-conversion S parameters(1)
Interlane skew (UI / 50)
13.34
ps
(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22
8.5.7.1.3 Frequency-domain Specification Guidelines
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D
Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and
compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance
Specification for D-PHY Version v1-01-00_r0-03.
If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design
needs to be improved.
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8.6
8.6.1
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Clock Routing Guidelines
32-kHz Oscillator Routing
When designing the printed-circuit board:
• Keep the crystal as close as possible to the crystal pins X1 and X2.
• Keep the trace lengths short and small to reduce capacitor loading and prevent unwanted noise
pickup.
• Place a guard ring around the crystal and tie the ring to ground to help isolate the crystal from
unwanted noise pickup.
• Keep all signals out from beneath the crystal and the X1 and X2 pins to prevent noise coupling.
• Finally, an additional local ground plane on an adjacent PCB layer can be added under the crystal to
shield it from unwanted pickup from traces on other layers of the board. This plane must be isolated
from the regular PCB ground plane and tied to the GND pin of the RTC. The plane must not be any
larger than the perimeter of the guard ring. Make sure that this ground plane does not contribute to
significant capacitance (a few pF) between the signal line and ground on the connections that run from
X1 and X2 to the crystal.
Cap
Via to GND
X
1
Crystal
Cap
IC
X
2
Local ground plane
SPRS906_PCB_CLK_OSC_01
Figure 8-37. Slow Clock PCB Requirements
8.6.2
Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground. Figure 8-38 shows the grounding scheme for slow
(low frequency) clock generated from the internal oscillator.
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Device
rtc_osc_xo
rtc_osc_xi_clkin32
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_PCB_CLK_OSC_02
Figure 8-38. Grounding Scheme for Low-Frequency Clock
Figure 8-39 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
Rd
(Optional)
Crystal
Cf1
vssa_oscj
Cf2
SPRS906_PCB_CLK_OSC_03
(1)
j in *_osc = 0 or 1
Figure 8-39. Grounding Scheme for High-Frequency Clock
8.7
8.7.1
DDR3 Board Design and Layout Guidelines
DDR3 General Board Layout Guidelines
To
•
•
•
•
•
•
•
•
•
•
376
help ensure good signaling performance, consider the following board design guidelines:
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
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•
8.7.2
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
DDR3 Board Design and Layout Guidelines
8.7.2.1
Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-29 and
Figure 8-40.
Table 8-29. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
1
PARAMETER
tc(DDR_CLK)
MIN
MAX
UNIT
1.5
2.5(1)
ns
Cycle time, DDR_CLK
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
Figure 8-40. DDR3 Memory Controller Clock Timing
8.7.2.2
DDR3 EMIF
The processor contains one DDR3 EMIF.
8.7.2.3
DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-30 summarizes the supported device configurations.
Table 8-30. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
16
N
16
8
Y(1)
2
16
16
N
32
(1)
32
2
16
Y
3
16
N(3)
32
4
8
N
32
4
8
Y(2)
32
8
(3)
32
5
N
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(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) This is two mirrored pairs of DDR3 devices.
(3) Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the
DRA7xx family of devices.
8.7.2.4
DDR3 Interface Schematic
8.7.2.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. Figure 8-41 and Figure 8-42 show the schematic connections for 32-bit
interfaces using x16 devices.
8.7.2.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-41
and Figure 8-42); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
378
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32-bit DDR3 EMIF
16-Bit DDR3
Devices
ddr1_d31
DQ15
8
ddr1_d24
DQ8
ddr1_dqm3
ddr1_dqs3
ddr1_dqsn3
UDM
UDQS
UDQS
ddr1_d23
DQ7
8
ddr1_d16
ddr1_dqm2
ddr1_dqs2
ddr1_dqsn2
D08
LDM
LDQS
LDQS
ddr1_d15
DQ15
8
ddr1_d8
DQ8
ddr1_dqm1
ddr1_dqs1
ddr1_dqsn1
ddr1_d7
UDM
UDQS
UDQS
DQ7
8
ddr1_d0
ddr1_dqm0
ddr1_dqs0
ddr1_dqsn0
ddr1_ck
ddr1_nck
ddr1_odt0
ddr1_csn0
ddr1_odt1
ddr1_csn1
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
ODT
CS
ODT
CS
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
A15
CAS
RAS
WE
CKE
RST
Zo
0.1 µF
DDR_1V5
Zo
NC
16
ZQ
ddr1_vref0
0.1 µF
Zo
CK
CK
NC
ddr1_a15
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_cke
ddr1_rst
ZQ
DQ0
LDM
LDQS
LDQS
CK
CK
0.1 µF
DDR_VTT
Zo
Zo
DDR_VREF
ZQ
VREFDQ
VREFCA
ZQ
0.1 µF
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_02
Figure 8-41. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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32-bit DDR3 EMIF
8-Bit DDR3
Devices
8-Bit DDR3
Devices
ddrx_d31
DQ7
8
ddrx_d24
ddrx_dqm3
DQ0
NC
ddrx_dqs3
ddrx_dqsn3
DM/TQS
TDQS
DQS
DQS
ddrx_d23
DQ7
8
ddrx_d16
ddrx_dqm2
DQ0
NC
ddrx_dqs2
ddrx_dqsn2
ddrx_d15
DM/TQS
TDQS
DQS
DQS
DQ7
8
ddrx_d8
ddrx_dqm1
NC
ddrx_dqs1
ddrx_dqsn1
ddrx_d7
DQ0
DM/TQS
TDQS
DQS
DQS
DQ7
8
ddrx_d0
NC
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_ck
ddrx_nck
ddrx_odt0
ddrx_csn0
ddrx_odt1
ddrx_csn1
ddrx_ba0
ddrx_ba1
ddrx_ba2
ddrx_a0
16
ZQ
ddrx_vref0
0.1 µF
ZQ
CK
CK
CK
CK
CK
CK
ODT
CS
ODT
CS
ODT
CS
ODT
CS
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
Zo
0.1 µF
DDR_1V5
Zo
NC
NC
ddrx_a15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
Zo
DQ0
TDQS
DM/TQS
DQS
DQS
CK
CK
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
0.1 µF
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
0.1 µF
ZQ
ZQ
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
0.1 µF
A15
CAS
RAS
WE
CKE
RST
ZQ
VREFDQ
VREFCA
DDR_VTT
Zo
Zo
DDR_VREF
ZQ
0.1 µF
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_03
Figure 8-42. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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Compatible JEDEC DDR3 Devices
Table 8-31 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.
Table 8-31. Compatible JEDEC DDR3 Devices (Per Interface)
N
O.
1
PARAMETER
CONDITION
JEDEC DDR3 device speed grade(1)
MIN
MAX
DDR clock rate = 400MHz
DDR3-800
DDR3-1600
400MHz< DDR clock rate ≤ 533MHz
DDR3-1066
DDR3-1600
533MHz< DDR clock rate ≤ 667MHz
UNIT
DDR3-1333
DDR3-1600
2
JEDEC DDR3 device bit width
x8
x16
Bits
3
JEDEC DDR3 device count(2)
2
4
Devices
(1) Refer to Table 8-29 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see Section 8.7.2.4, Figure 8-41, and Figure 8-42.
8.7.2.6
PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in Table 8-32.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
Table 8-33.
Table 8-32. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
DESCRIPTION
1
Signal
Top routing mostly vertical
2
Plane
Ground
3
Plane
Split power plane
4
Plane
Split power plane or Internal routing
5
Plane
Ground
6
Signal
Bottom routing mostly horizontal
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Table 8-33. PCB Stackup Specifications
NO.
PARAMETER
MIN
PS1
PCB routing/plane layers
6
PS2
Signal routing layers
3
PS3
Full ground reference layers under DDR3 routing region(1)
TYP
MAX
1
(1)
PS4
Full 1.5-V power reference layers under the DDR3 routing region
PS5
Number of reference plane cuts allowed within DDR routing region(2)
0
PS6
Number of layers between DDR3 routing layer and reference plane(3)
0
PS7
PCB routing feature size
4
PS8
PCB trace width, w
4
PS9
Single-ended impedance, Zo
PS10
UNIT
1
50
(5)
Impedance control
Z-5
Z
Mils
Mils
75
Ω
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
8.7.2.7
Placement
Figure 8-43 shows the required placement for the processor as well as the DDR3 devices. The
dimensions for this figure are defined in Table 8-34. The placement does not restrict the side of the PCB
on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace
lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3
devices are omitted from the placement.
Figure 8-43. Placement Specifications
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Table 8-34. Placement Specifications DDR3
MAX
UNIT
KOD31 X1
NO.
PARAMETER
MIN
500
Mils
KOD32 X2
600
Mils
KOD33 X3
600
Mils
KOD34 Y1
1800
Mils
KOD35 Y2
600
Mils
KOD36 DDR3 keepout region (1)
KOD37 Clearance from non-DDR3 signal
to DDR3 keepout region (2) (3)
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
8.7.2.8
DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in Figure 8-44. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in Table 834. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.
Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the
DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the
two signals from the DDR3 controller should be separated from each other by the specification in Table 834 (see KOD37).
Figure 8-44. DDR3 Keepout Region
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Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.
Table 8-35 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 8-35. Bulk Bypass Capacitors
NO.
PARAMETER
MIN
MAX
UNIT
1
vdds_ddrx bulk bypass capacitor count(1)
1
Devices
2
vdds_ddrx bulk bypass total capacitance
22
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the highspeed (HS) bypass capacitors and DDR3 signal routing.
8.7.2.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-36 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-36.
Table 8-36. High-Speed Bypass Capacitors
NO.
PARAMETER
MIN
1
HS bypass capacitor package size(1)
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
3
Processor HS bypass capacitor count per vdds_ddrx rail(12)
4
Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)
TYP
MAX
UNIT
0201
0402
10 Mils
400
See Table 8-3 and (11)
Mils
Devices
See Table 8-3 and (11)
μF
(5)
5
Number of connection vias for each device power/ground ball
6
Trace length from device power/ground ball to connection via(2)
7
Distance, HS bypass capacitor to DDR device being bypassed
8
DDR3 device HS bypass capacitor count(7)
9
DDR3 device HS bypass capacitor total capacitance(7)
Vias
35
(6)
(8)(9)
10
Number of connection vias for each HS capacitor
11
Trace length from bypass capacitor connect to connection via(2)(9)
12
Number of connection vias for each DDR3 device power/ground ball(10)
13
Trace length from DDR3 device power/ground ball to connection via(2)(8)
70
Mils
150
Mils
12
Devices
0.85
μF
2
Vias
35
100
1
Mils
Vias
35
60
Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
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(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see Section 8.3, Core Power Domains.
8.7.2.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
8.7.2.11 Net Classes
Table 8-37 lists the clock net classes for the DDR3 interface. Table 8-38 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-37. Clock Net Class Definitions
CLOCK NET CLASS
CK
processor PIN NAMES
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
DQS1
ddrx_dqs1 / ddrx_dqsn1
DQS2(1)
ddrx_dqs2 / ddrx_dqsn2
(1)
ddrx_dqs3 / ddrx_dqsn3
DQS3
(1) Only used on 32-bit wide DDR3 memory systems.
Table 8-38. Signal Net Class Definitions
SIGNAL NET CLASS
ASSOCIATED CLOCK
NET CLASS
ADDR_CTRL
CK
DQ0
DQS0
ddrx_d[7:0], ddrx_dqm0
processor PIN NAMES
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
DQ1
DQS1
ddrx_d[15:8], ddrx_dqm1
DQ2(1)
DQS2
ddrx_d[23:16], ddrx_dqm2
DQ3(1)
DQS3
ddrx_d[31:24], ddrx_dqm3
(1) Only used on 32-bit wide DDR3 memory systems.
8.7.2.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
8.7.2.13 VREF_DDR Routing
ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
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8.7.2.14 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
8.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in Table 8-39.
8.7.2.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 8-45 shows the topology of the CK net classes and Figure 8-46 shows the topology for the
corresponding ADDR_CTRL net classes.
+ –
+ –
+ –
+ –
AS+
AS-
AS+
AS-
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
A4
A3
AT
Cac
+
–
Rcp
A1
A2
A3
A4
A3
0.1 µF
AT
Routed as Differential Pair
SPRS906_PCB_DDR3_06
Figure 8-45. CK Topology for Four x8 DDR3 Devices
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Processor
Address and Control
Output Buffer
A1
A3
A2
AS
AS
AS
AS
DDR Address and Control Input Buffers
A3
A4
Address and Control
Terminator
Rtt
Vtt
AT
SPRS906_PCB_DDR3_07
Figure 8-46. ADDR_CTRL Topology for Four x8 DDR3 Devices
8.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
A1
A1
Figure 8-47 shows the CK routing for four DDR3 devices placed on the same side of the PCB. Figure 8-48
shows the corresponding ADDR_CTRL routing.
DDR_1V5
A3
A3
=
A4
A4
A3
A3
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
SPRS906_PCB_DDR3_08
Figure 8-47. CK Routing for Four Single-Side DDR3 Devices
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Rtt
A3
=
A3
A4
AT
Vtt
AS
A2
SPRS906_PCB_DDR3_09
Figure 8-48. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
A1
A1
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. Figure 8-49 and Figure 8-50 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
DDR_1V5
=
A4
A4
A3
A3
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A3
A3
A2
A2
SPRS906_PCB_DDR3_10
Figure 8-49. CK Routing for Four Mirrored DDR3 Devices
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Rtt
=
A3
A4
AT
Vtt
AS
A3
A2
SPRS906_PCB_DDR3_11
Figure 8-50. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
8.7.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
8.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
Figure 8-51 shows the topology of the CK net classes and Figure 8-52 shows the topology for the
corresponding ADDR_CTRL net classes.
+ –
+ –
AS+
AS-
AS+
AS-
DDR Differential CK Input Buffers
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
A3
AT
Cac
+
–
Rcp
A1
A2
A3
0.1 µF
AT
Routed as Differential Pair
SPRS906_PCB_DDR3_12
Figure 8-51. CK Topology for Two DDR3 Devices
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Processor
Address and Control
Output Buffer
A1
AS
AS
DDR Address and Control Input Buffers
A3
A2
Address and Control
Terminator
Rtt
Vtt
AT
SPRS906_PCB_DDR3_13
Figure 8-52. ADDR_CTRL Topology for Two DDR3 Devices
8.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
A1
A1
Figure 8-53 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-54
shows the corresponding ADDR_CTRL routing.
DDR_1V5
A3
A3
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A2
A2
SPRS906_PCB_DDR3_14
Figure 8-53. CK Routing for Two Single-Side DDR3 Devices
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Rtt
A3
=
Vtt
AT
AS
A2
SPRS906_PCB_DDR3_15
Figure 8-54. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
A1
A1
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. Figure 8-55 and Figure 8-56 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
DDR_1V5
=
Rcp
Cac
Rcp
0.1 µF
AT
AT
AS+
AS-
A3
A3
A2
A2
SPRS906_PCB_DDR3_16
Figure 8-55. CK Routing for Two Mirrored DDR3 Devices
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Rtt
A3
=
Vtt
AT
AS
A2
SPRS906_PCB_DDR3_17
Figure 8-56. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
8.7.2.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
8.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
Figure 8-57 shows the topology of the CK net classes and Figure 8-58 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR Differential CK Input Buffer
AS+
AS-
+ –
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
Processor
Differential Clock
Output Buffer
A2
AT
Cac
+
–
Rcp
A1
A2
0.1 µF
AT
Routed as Differential Pair
SPRS906_PCB_DDR3_18
Figure 8-57. CK Topology for One DDR3 Device
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AS
DDR Address and Control Input Buffers
Processor
Address and Control
Output Buffer
A1
Address and Control
Terminator
Rtt
AT
Vtt
A2
SPRS906_PCB_DDR3_19
Figure 8-58. ADDR_CTRL Topology for One DDR3 Device
8.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
A1
A1
Figure 8-59 shows the CK routing for one DDR3 device placed on the same side of the PCB. Figure 8-60
shows the corresponding ADDR_CTRL routing.
DDR_1V5
Rcp
Cac
Rcp
0.1 µF
AT
AT
=
AS+
AS-
A2
A2
SPRS906_PCB_DDR3_20
Figure 8-59. CK Routing for One DDR3 Device
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Rtt
AT
=
Vtt
AS
A2
SPRS906_PCB_DDR3_21
Figure 8-60. ADDR_CTRL Routing for One DDR3 Device
8.7.2.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
8.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. Figure 8-61
and Figure 8-62 show these topologies.
Processor
DQS
IO Buffer
DQSn+
DQSn-
DDR
DQS
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_22
Figure 8-61. DQS Topology
Processor
DQ and DM
IO Buffer
Dn
DDR
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_23
Figure 8-62. DQ/DM Topology
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8.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
Figure 8-63 and Figure 8-64 show the DQS and DQ/DM routing.
DQSn+
DQSn-
DQS
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
Figure 8-63. DQS Routing With Any Number of Allowed DDR3 Devices
Dn
DQ and DM
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
Figure 8-64. DQ/DM Routing With Any Number of Allowed DDR3 Devices
8.7.2.17 Routing Specification
8.7.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-65 and Figure 8-66 show
this distance for four loads and two loads, respectively. It is from this distance that the specifications on
the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly
for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net
class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-39.
(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
A8
(A)
A8
(A)
Rtt
A3
=
A4
A3
AT
Vtt
AS
A2
SPRS906_PCB_DDR3_26
A.
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-65. CACLM for Four Address Loads on One Side of PCB
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(A)
A1
A8
CACLMY
CACLMX
A8
(A)
A8
(A)
Rtt
A3
=
AT
Vtt
AS
A2
SPRS906_PCB_DDR3_27
A.
It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
Figure 8-66. CACLM for Two Address Loads on One Side of PCB
Table 8-39. CK and ADDR_CTRL Routing Specification(2)(3)
NO.
PARAMETER
MAX
UNIT
500(1)
ps
A1+A2 skew
29
ps
A3 length
125
ps
CARS34
A3 skew(4)
6
ps
CARS35
(5)
A3 skew
6
ps
CARS36
A4 length
125
ps
CARS37
A4 skew
6
ps
CARS38
AS length
17
ps
1.3
14
ps
5
12
ps
1
ps
CARS31
A1+A2 length
CARS32
CARS33
MIN
TYP
5(1)
(1)
CARS39
AS skew
CARS310
AS+/AS- length
CARS311
AS+/AS- skew
(6)
CARS312
AT length
75
CARS313
AT skew(7)
14
ps
CARS314
AT skew(8)
CARS315
CK/ADDR_CTRL trace length
1020
ps
CARS316
Vias per trace
3(1)
vias
CARS317
Via count difference
1(15)
vias
CARS318
Center-to-center CK to other DDR3 trace spacing(9)
4w
CARS319
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
CARS320
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
3w
ps
1
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Table 8-39. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CARS321
CK center-to-center spacing(11)(12)
CARS322
CK spacing to other net(9)
CARS323
Rcp(13)
CARS324
Rtt(13)(14)
MIN
TYP
MAX
UNIT
Zo-1
Zo
Zo+1
Ω
Zo-5
Zo
Zo+5
Ω
4w
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rice time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
8.7.2.17.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
NOTE
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. Figure 8-67 shows this distance for
four loads. It is from this distance that the specifications on the lengths of the transmission lines for the
data bus are determined. For DQS and DQ/DM routing, these specifications are contained in Table 8-40.
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DQLMX0
DB0
DB1
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMY0
DQLMX2
DQLMY3
DQLMY2
DB3
DQLMY1
DQ[23:31]/DM3/DQS3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
SPRS906_PCB_DDR3_28
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
Figure 8-67. DQLM for Any Number of Allowed DDR3 Devices
Table 8-40. Data Routing Specification(2)
NO.
PARAMETER
MIN
TYP
MAX
UNIT
DRS31
DB0 length
340
ps
DRS32
DB1 length
340
ps
DRS33
DB2 length
340
ps
DRS34
DB3 length
340
ps
DRS35
(3)
DBn skew
5
ps
DRS36
DQSn+ to DQSn- skew
1
ps
DRS37
DQSn to DBn skew(3)(4)
5(10)
ps
(1)
vias
vias
DRS38
Vias per trace
2
DRS39
Via count difference
0(10)
DRS310
Center-to-center DBn to other DDR3 trace spacing(6)
4
w(5)
DRS311
Center-to-center DBn to other DBn trace spacing(7)
3
w(5)
4
w(5)
(8)(9)
DRS312
DQSn center-to-center spacing
DRS313
DQSn center-to-center spacing to other net
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rice time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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9 Device and Documentation Support
TI offers an extensive line of development tools, including methods to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules as listed below.
9.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, DRA72x). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of DRA72x devices in the ABC package type, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the Silicon Errata (literature
number SPRZ426 ).
400
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9.1.1
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Standard Package Symbolization
JACINTO
aBBBBBBrzYPPPQ1
XXXXXXX
ZZZ G1
YYY
PIN ONE INDICATOR
O
SPRS906_PACK_01
Figure 9-1. Printed Device Reference
NOTE
Some devices have a cosmetic circular marking visible on the top of the device package
which results from the production test process. These markings are cosmetic only with no
reliability impact.
9.1.2
Device Naming Convention
Table 9-1. Nomenclature Description
FIELD PARAMETER
a
BBBBBB
r
z
FIELD DESCRIPTION
Device evolution
stage(1)
Base production part
number
Device revision
Device Speed
VALUE
DESCRIPTION
X
Prototype
P
Preproduction (production test flow, no reliability data)
BLANK
Production
DRA722
J6Eco Ultra Low Tier
DRA724
J6Eco Low Tier
DRA725
J6Eco Mid Tier
DRA726
J6Eco High Tier
BLANK
SR 1.0
A
SR 2.0
P
Indicates the speed grade for each of the cores in the device. For more
information see Table 3-1, Device Comparison Table.
L
J
H
OTHER
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Table 9-1. Nomenclature Description (continued)
FIELD PARAMETER
Y
PPP
Q1
FIELD DESCRIPTION
Device type
Package designator
Automotive Designator
VALUE
General purpose (Prototype and Production)
E
Emulation (E) devices
D
High security prototype devices with TI Development keys (D)
Yn
Letter followed by number indicates HS device with customer key
ABC
BLANK
Q1
XXXXXXX
DESCRIPTION
G
ABC S-PBGA-N760 (23mm × 23mm) Package
Not meeting automotive qualification
Meeting Q100 equal requirements, with exceptions as specified in DM.
Lot Trace Code
YYY
Production Code, For TI use only
ZZZ
Production Code, For TI use only
O
Pin one designator
G1
ECAT—Green package designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still under development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
NOTE
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
9.2
Tools and Software
The following products support development for DRA72x platforms:
Development Tools
DRA72x Clock Tree Tool is interactive clock tree configuration software that allows the user to
visualize the device clock tree, interact with clock tree elements and view the effect on PRCM
registers, interact with the PRCM registers and view the effect on the device clock tree, and view a
trace of all the device registers affected by the user interaction with the clock tree.
DRA72x Register Descriptor Tool is an interactive device register configuration tool that allows users
to visualize the register state on power-on reset, and then customize the configuration of the device for
the specific use-case.
DRA72x Pad Configuration Tool is an interactive pad-configuration tool that allows the user to
visualize the device pad configuration state on power-on reset and then customize the configuration of
the pads for the specific use-case and identify the device register settings associated to that
configuration.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
9.3
Documentation Support
The following documents describe the DRA72x devices.
402
TRM
DRA72x (SR 2.0, 1.0) and DRA71x (SR 2.0) SoC for Automotive Infotainment Technical
Reference Manual Details the integration, the environment, the functional description, and
the programming models for each peripheral and subsystem in the DRA72x family of
devices.
Errata
DRA72x (SR 2.0, 1.0) and DRA71x (SR 2.0) SoC for Automotive Infotainment Silicon
Errata Describes known advisories, limitations, and cautions on silicon and provides
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workarounds.
9.4
Receiving Notification of Documentation Updates
To receive notification of documentation updates — including silicon errata — go to the product folder for
your device on www.ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
9.5
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki.
Established to help developers get started with Embedded Processors from Texas
Instruments and to foster innovation and growth of general knowledge about the hardware
and software surrounding these devices.
9.6
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9-2. Related Links
9.7
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DRA722
Click here
Click here
Click here
Click here
Click here
DRA724
Click here
Click here
Click here
Click here
Click here
DRA725
Click here
Click here
Click here
Click here
Click here
DRA726
Click here
Click here
Click here
Click here
Click here
Trademarks
ICEPick and SmartReflex are trademarks of Texas Instruments Incorporated.
ARM and Cortex are registered trademark of ARM Limited.
ETB, ARM9, CoreSight, ISA, and Neon are trademarks of ARM Limited.
HDMI is a trademark of HDMI Licensing, LLC.
HDQ is a trademark of Benchmarq.
1-Wire is a registered trademark of Maxim Integrated.
PowerVR is a registered trademark of Imagination Technologies Ltd.
SD is a registered trademark of Toshiba Corporation.
MMC and eMMC are trademarks of MultiMediaCard Association.
MIPI is a registered trademark of the Mobile Industry Processor Interface (MIPI) Alliance.
PCI Express is a registered trademark of PCI-SIG.
MediaLB is a trademark of Standard Microsystems Corporation.
Vivante is a registered trademark of Vivante Corporation.
All other trademarks are the property of their respective owners.
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9.8
www.ti.com
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
9.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
404
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10 Mechanical Packaging and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical Packaging and Orderable Information
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405
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRA722AHGABCQ1
ACTIVE
FCBGA
ABC
760
60
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
DRA722AHGABCQ1
JACINTO
DRA722AHGABCRQ1
ACTIVE
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
DRA722AHGABCQ1
JACINTO
DRA724JGABCRQ1
PREVIEW
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
DRA725AGGABCQ1
ACTIVE
FCBGA
ABC
760
60
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
DRA725AGGABCQ1
JACINTO
DRA725AGGABCRQ1
ACTIVE
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
DRA725AGGABCQ1
JACINTO
DRA725LGABCRQ1
PREVIEW
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA725LGABCQ1
JACINTOTM
DRA726APGABCQ1
ACTIVE
FCBGA
ABC
760
60
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA726APGABCQ1
DRA726APGABCRQ1
ACTIVE
FCBGA
ABC
760
250
Green (RoHS
& no Sb/Br)
Call TI | SNAGCU
Level-3-250C-168 HR
-40 to 125
DRA726APGABCQ1
-40 to 125
DRA724JGABCQ1
JACINTOTM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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