Single, 128-taps Low Voltage Digitally Controlled Potentiometer (XDCP™) ISL23318 Features The ISL23318 is a volatile, low voltage, low noise, low power, I2C Bus™, 128 Taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control logic on a monolithic CMOS integrated circuit. • 128 resistor taps The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. When powered on, the ISL23318’s wiper will always commence at mid-scale (64 tap position). The low voltage, low power consumption, and small package of the ISL23318 make it an ideal choice for use in battery operated equipment. In addition, the ISL23318 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the VCC value. This allows for low logic levels to be connected directly to the ISL23318 without passing through a voltage level shifter. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • I2C serial interface - No additional level translator for low bus supply - Two address pins allow up to four devices per bus • Power supply - VCC = 1.7V to 5.5V analog power supply - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply • Wiper resistance: 70Ω typical @ VCC = 3.3V • Shutdown Mode - forces the DCP into an end-to-end open circuit and RW is shorted to RL internally • Power-on preset to mid-scale (64 tap position) • Shutdown and standby current <2.8µA max • DCP terminal voltage from 0V to VCC • 10kΩ, 50kΩ or 100kΩ total resistance • Extended industrial temperature range: -40°C to +125°C • 10 Ld MSOP or 10 Ld UTQFN packages • Pb-free (RoHS compliant) Applications • Gain adjustment in battery powered instruments • Trimming sensor circuits • Power supply margining • RF power amplifier bias compensation 10000 VREF RESISTANCE (Ω) 8000 RH 6000 - 4000 RW ISL23318 VREF_M + ISL28114 2000 RL 0 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP POSITION, 10k DCP July 26, 2011 FN7887.0 1 FIGURE 2. VREF ADJUSTMENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners ISL23318 Block Diagram VCC VLOGIC SCL SDA I/O BLOCK A1 LEVEL SHIFTER A0 RH POWER-UP INTERFACE, CONTROL AND STATUS LOGIC WR VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY RL RW GND Pin Configurations Pin Descriptions ISL23318 (10 LD MSOP) TOP VIEW MSOP 1 UTQFN 10 SYMBOL DESCRIPTION VLOGIC I2C bus /logic supply. Range 1.2V to 5.5V VLOGIC 1 10 GND 2 1 SCL Logic Pin - Serial bus clock input SCL 2 9 VCC 3 2 SDA SDA 3 8 RH Logic Pin - Serial bus data input/open drain output A0 4 7 RW 4 3 A0 A1 5 6 RL Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 5 4 A1 Logic Pin - Hardwire slave address pin for I2C serial bus. Range: VLOGIC or GND 6 5 RL DCP “low” terminal 7 6 RW DCP wiper terminal 8 7 RH DCP “high” terminal 9 8 VCC Analog power supply. Range 1.7V to 5.5V 10 9 GND Ground pin 10 VLOGIC ISL23318 (10 LD UTQFN) TOP VIEW 1 9 GND SDA 2 8 VCC A0 3 7 RH A1 4 6 RW RL 5 SCL 2 FN7887.0 July 26, 2011 ISL23318 Ordering Information PART NUMBER (Note 5) PART MARKING RESISTANCE OPTION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL23318TFUZ (Notes 1, 3) 3318T 100 -40 to +125 10 Ld MSOP M10.118 ISL23318UFUZ (Notes 1, 3) 3318U 50 -40 to +125 10 Ld MSOP M10.118 ISL23318WFUZ (Notes 1, 3) 3318W 10 -40 to +125 10 Ld MSOP M10.118 ISL23318TFRUZ-T7A (Notes 2, 4) HH 100 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A ISL23318TFRUZ-TK (Notes 2, 4) HH 100 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A ISL23318UFRUZ-T7A (Notes 2, 4) HG 50 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A ISL23318UFRUZ-TK (Notes 2, 4) HG 50 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A ISL23318WFRUZ-T7A (Notes 2, 4) HF 10 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A ISL23318WFRUZ-TK (Notes 2, 4) HF 10 -40 to +125 10 Ld 2.1x1.6 UTQFN L10.2.1x1.6A NOTES: 1. Add "-TK" or "-T7A" suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23318. For more information on MSL please see techbrief TB363. 3 FN7887.0 July 26, 2011 ISL23318 Absolute Maximum Ratings Thermal Information Supply Voltage Range VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Voltage on Any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Wiper current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld MSOP Package (Notes 6, 7) . . . . . . . 170 70 10 Ld UTQFN Package (Notes 6, 7) . . . . . . 145 90 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For θJC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL RTOTAL PARAMETER RH to RL Resistance TEST CONDITIONS MIN (Note 20) RW UNITS 10 kΩ U option 50 kΩ T option VRH, VRL MAX (Note 20) W option RH to RL Resistance Tolerance End-to-End Temperature Coefficient TYP (Note 8) 100 -20 ±2 kΩ +20 % W option 175 U option 85 ppm/°C T option 70 ppm/°C 0 ppm/°C DCP Terminal Voltage VRH or VRL to GND VCC V Wiper Resistance RH - floating, VRL = 0V, force IW current to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V 70 200 Ω VCC = 1.7V 580 Ω 32 pF CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page 8 ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Digital Feed-Through from Bus to Wiper Wiper at middle point -65 dB Power Supply Reject Ratio -75 dB Feed Thru PSRR 4 Wiper output change if VCC change ±10%; wiper at middle point -0.4 <0.1 0.4 µA FN7887.0 July 26, 2011 ISL23318 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 13) Integral Non-linearity, Guaranteed Monotonic W, U, T options -0.5 ±0.15 +0.5 LSB (Note 9) DNL (Note 12) Differential Non-linearity, Guaranteed Monotonic W, U, T options -0.5 ±0.15 +0.5 LSB (Note 9) FSerror (Note 11) Full-scale Error W option -2.5 -1.5 0 LSB (Note 9) U, T option -1.0 -0.7 0 LSB (Note 9) W option 0 1.5 2.5 LSB (Note 9) U, T option 0 0.7 1.0 LSB (Note 9) ZSerror (Note 10) Zero-scale Error TCV Ratiometric Temperature Coefficient (Notes 14) fcutoff W option, Wiper Register set to 40 hex 8 ppm/°C U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C Large Signal Wiper Settling Time From code 0 to 7F hex 300 ns -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL (Note 18) Integral Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -1.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V Differential Non-linearity, Guaranteed Monotonic W option; VCC = 2.7V to 5.5V -0.5 -0.5 Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V -0.5 U, T option; VCC = 1.7V 5 ±0.15 ±0.15 0 1.8 +0.5 0.3 0.5 MI (Note 15) MI (Note 15) +0.5 MI (Note 15) MI (Note 15) 3.0 3.0 0 MI (Note 15) MI (Note 15) ±0.4 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +0.5 ±0.4 U, T option; VCC = 1.7V Roffset (Note 16) ±0.15 MI (Note 15) MI (Note 15) ±1.0 W option; VCC = 1.7V U, T option; VCC = 2.7V to 5.5V +1.0 ±3.0 U, T option; VCC = 1.7V RDNL (Note 17) ±0.5 MI (Note 15) MI (Note 15) 1 MI (Note 15) MI (Note 15) FN7887.0 July 26, 2011 ISL23318 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) SYMBOL TCR (Note 19) PARAMETER Resistance Temperature Coefficient TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS W option; Wiper register set between 19 hex and 7F hex 220 ppm/°C U option; Wiper register set between 19 hex and 7F hex 100 ppm/°C T option; Wiper register set between 19 hex and 7F hex 75 ppm/°C Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL ILOGIC ICC ILOGIC SB ICC SB PARAMETER VLOGIC Supply Current (Write/Read) VCC Supply Current (Write/Read) VLOGIC Standby Current VCC Standby Current MAX (Note 20) UNITS VLOGIC = 5.5V, VCC = 5.5V, fSCL = 400kHz (for I2C active read and write) 200 µA VLOGIC = 1.2V, VCC = 1.7V, fSCL = 400kHz (for I2C active read and write) 5 µA VLOGIC = 5.5V, VCC = 5.5V 18 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA VLOGIC = VCC = 5.5V, I2C interface in standby 1.3 µA VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby 0.4 µA VLOGIC = VCC = 5.5V, I2C interface in standby 1.5 µA 1 µA VLOGIC = VCC = 5.5V, I2C interface in standby 1.3 µA VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby 0.4 µA VLOGIC = VCC = 5.5V, I2C interface in standby 1.5 µA 1 µA 0.4 µA TEST CONDITIONS MIN (Note 20) TYP (Note 8) VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILOGIC SHDN VLOGIC Shutdown Current ICC SHDN VCC Shutdown Current VLOGIC = 1.2V, VCC = 1.7V, I2C interface in standby ILkgDig tDCP Leakage Current, at Pins A0, A1, SDA, SCL Voltage at pin from GND to VLOGIC Wiper Response Time tShdnRec DCP Recall Time from Shutdown Mode VCC, VLOGIC VCC ,VLOGIC Ramp Rate Ramp (Note 21) 6 -0.4 <0.1 SCL rising edge of the acknowledge bit after data byte to wiper new position 1.5 µs SCL rising edge of the acknowledge bit after ACR data byte to wiper recalled position and RH connection 1.5 µs Ramp monotonic at any level 0.01 50 V/ms FN7887.0 July 26, 2011 ISL23318 Serial Interface Specification SYMBOL For SCL, SDA, A0, A1 unless otherwise noted. PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V Hysteresis VOL SDA and SCL Input Buffer Hysteresis VLOGIC > 2V 0.05 x VLOGIC VLOGIC < 2V 0.1 x VLOGIC SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V V 0 IOL = 1.5mA, VLOGIC < 2V Cpin SDA, SCL Pin Capacitance fSCL SCL Frequency tsp Pulse Width Suppression Time at SDA and SCL Inputs tAA 0.4 V 0.2 x VLOGIC V 10 pF 400 kHz Any pulse narrower than the max spec is suppressed 50 ns SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window 900 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VLOGIC during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition 1300 ns tLOW Clock LOW Time Measured at the 30% of VLOGIC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VLOGIC crossing 600 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VLOGIC 600 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC 600 ns tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC 100 ns tHD:DAT Input Data Hold Time From SCL falling edge crossing 70% of VCC to SDA entering the 30% to 70% of VLOGIC window 0 ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC 600 ns tHD:STO STOP Condition Hold Time for Read From SDA rising edge to SCL or Write falling edge; both crossing 70% of VLOGIC 1300 ns 0 ns tDH Output Data Hold Time From SCL falling edge crossing 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL = 3mA, VLOGIC > 2V. IOL = 0.5mA, VLOGIC < 2V tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 7 20 + 0.1 x Cb 250 ns FN7887.0 July 26, 2011 ISL23318 Serial Interface Specification SYMBOL For SCL, SDA, A0, A1 unless otherwise noted. (Continued) PARAMETER TEST CONDITIONS MIN (Note 20) TYP (Note 8) MAX (Note 20) UNITS 20 + 0.1 x Cb 250 ns 10 400 pF tF SDA and SCL Fall Time From 70% to 30% of VLOGIC Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip tSU:A A1, A0 Set-up Time Before START condition 600 ns tHD:A A1, A0 Hold Time After STOP condition 600 ns NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)127 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127. 14. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 TC V = ------------------------------------------------------------------------------ × --------------------V ( RW i ( +25°C ) ) +165°C For i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage and Min( ) is the minimum value of the wiper voltage over the temperature range. 15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 19. 6 [ Max ( Ri ) – Min ( Ri ) ] 10 TC R = ------------------------------------------------------- × --------------------Ri ( +25°C ) +165°C For i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. DCP Macro Model RTOTAL RH CL CH CW 32pF RL 32pF 32pF RW 8 FN7887.0 July 26, 2011 ISL23318 Timing Diagrams SDA vs SCL Timing tHIGH tF SCL tLOW tsp tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) A0 and A1 Pin Timing STOP START SCL CLK 1 SDA tSU:A tHD:A A0, A1 0.4 0.04 0.2 0.02 DNL (LSB) DNL (LSB) Typical Performance Curves 0 -0.2 -0.4 0 -0.02 0 16 32 48 64 80 96 112 TAP POSITION (DECIMAL) FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V 9 128 -0.04 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves (Continued) 0.4 0.16 0.08 INL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 0 -0.08 0 16 32 48 64 80 96 112 -0.16 128 0 16 32 TAP POSITION (DECIMAL) 0.4 0.10 0.2 0.05 0 96 112 128 0 -0.10 0 16 32 48 64 80 96 112 128 0 16 32 TAP POSITION (DECIMAL) 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V 0.4 0.16 0.2 0.08 RINL (MI) RINL (MI) 80 -0.05 -0.2 0 -0.2 -0.4 64 FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V RDNL (MI) RDNL (MI) FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V -0.4 48 TAP POSITION (DECIMAL) 0 -0.08 0 16 32 48 64 80 96 112 TAP POSITION (DECIMAL) FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V 10 128 -0.16 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves (Continued) 60 50 WIPER RESISTANCE (Ω) 50 WIPER RESISTANCE (Ω) +25°C 40 30 20 -40°C 40 30 20 -40°C 10 10 0 +125°C +25°C +125°C 0 16 32 48 64 80 96 112 0 128 0 16 TAP POSITION (DECIMAL) 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V 140 30 120 25 TCv (ppm/°C) TCv (ppm/°C) 100 80 60 40 15 10 5 20 0 20 16 32 48 64 80 96 112 0 128 16 32 TAP POSITION (DECIMAL) 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION 350 100 300 75 TCr (ppm/°C) TCr (ppm/°C) 250 200 150 100 50 25 50 0 16 32 48 64 80 96 TAP POSITION (DECIMAL) FIGURE 15. 10k TCr vs TAP POSITION 11 112 128 0 16 32 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 16. 50k TCr vs TAP POSITION FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves (Continued) 150 20 140 TCr (ppm/°C) TCv (ppm/°C) 15 10 5 0 130 120 110 16 32 48 64 80 96 112 128 100 16 32 TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION 48 64 80 96 112 128 TAP POSITION (DECIMAL) FIGURE 18. 100k TCr vs TAP POSITION SCL CLOCK 1V/DIV RW PIN 10mV/DIV 20mV/DIV 5µs/DIV 1µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH 1V/DIV 1µs/DIV FIGURE 20. WIPER TRANSITION GLITCH 1V/DIV 0.1s/DIV WIPER VRH = VCC VRW SCL 9TH CLOCK OF THE DATA BYTE (ACK) FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME 12 FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE FN7887.0 July 26, 2011 ISL23318 Typical Performance Curves (Continued) 1.2 STANDBY CURRENT ICC (µA) CH1: 0.5V/DIV, 0.2µs/DIV RH PIN CH2: 0.2V/DIV, 0.2µs/DIV RW PIN RTOTAL = 10k -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP 1.0 0.8 VCC = 5.5V, VLOGIC = 5.5V 0.6 0.4 VCC = 1.7V, VLOGIC = 1.2V 0.2 0 -40 -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10k -3dB CUT OFF FREQUENCY Functional Pin Descriptions Potentiometers Pins RH AND RL The high (RH) and low (RL) terminals of the ISL23318 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. Bus Interface Pins FIGURE 24. STANDBY CURRENT vs TEMPERATURE VLOGIC This is an input pin that supplies internal level translator for serial bus operation from 1.2V to 5.5V. Principles of Operation The ISL23318 is an integrated circuit incorporating one DCP with its associated registers and an I2C serial interface providing direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. SERIAL DATA INPUT/OUTPUT (SDA) Voltage at any DCP pins, RH, RL or RW, should not exceed VCC level at any conditions during power-up and normal operation. The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. The VLOGIC pin needs to be connected to the I2C bus supply which allows reliable communication with the wide range of microcontrollers and independent of the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. SDA requires an external pull-up resistor, since it is an open drain input/output. DCP Description SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor, since a master is an open drain output. DEVICE ADDRESS (A1, A0) The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL23318. A maximum of four ISL23318 devices may occupy the I2C serial bus (see Table 3). 13 The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[7:0] = 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to 0111 1111b (127 decimal), the wiper moves FN7887.0 July 26, 2011 ISL23318 While the ISL23318 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the I2C serial interface as described in the following sections. Memory Description The ISL23318 contains two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). The memory map of ISL23318 is shown in Table 1. The Wiper Register (WR) at address 0 contains current wiper position. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. In shutdown mode, if there is a glitch on the power supply which causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. WIPER VOLTAGE, VRW (V) monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. POWER-UP MID SCALE = 80H USER PROGRAMMED AFTER SHDN SHDN ACTIVATED SHDN RELEASED WIPER RESTORE TO THE ORIGINAL POSITION SHDN MODE 0 TIME (s) FIGURE 26. SHUTDOWN MODE WIPER RESPONSE TABLE 1. MEMORY MAP ADDRESS (hex) VOLATILE REGISTER NAME DEFAULT SETTING (hex) 10 ACR 40 0 WR 40 TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 NAME/ VALUE 0 SHDN 0 0 0 0 0 0 I2C Serial Interface The ISL23318 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL23318 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. Shutdown Function The SHDN bit (ACR[6]) disables or enables shutdown mode for all DCP channels simultaneously. When this bit is 0, i.e., DCP is forced to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor as shown in Figure 25. Default value of the SHDN bit is 1 RH RW 2kΩ RL FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE In the shutdown mode, the RW terminal is shorted to the RL terminal with around 2kΩ resistance as shown in Figure 25. When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). 14 Protocol Conventions Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 27). On power-up of the ISL23318, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23318 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 27). A STOP condition at the end of a read operation or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 28). The ISL23318 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again FN7887.0 July 26, 2011 ISL23318 after successful receipt of an Address Byte. The ISL23318 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. TABLE 3. IDENTIFICATION BYTE FORMAT LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY 1 A valid Identification Byte contains 10100 as the five MSBs, and the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation and “0” for a Write operation (see Table 3). 0 1 0 0 A1 (MSB) A0 R/W (LSB) SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE S T A R T WRITE IDENTIFICATION BYTE ADDRESS BYTE 1 0 1 0 0 A1 A0 0 S T O P DATA BYTE 0 0 0 A C K A C K A C K FIGURE 29. BYTE WRITE SEQUENCE 15 FN7887.0 July 26, 2011 ISL23318 SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 ADDRESS BYTE 1 0 1 0 0 A1 A0 0 READ A C K S A T C O K P A C K 1 0 1 0 0 A1 A0 1 0 0 0 A C K SIGNALS FROM THE SLAVE S T A IDENTIFICATION R BYTE WITH T R/W = 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 30. READ SEQUENCE Write Operation Applications Information A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL23318 responds with an ACK. The data is transferred from I2C block to the corresponding register at the 9th clock of the data byte and device enters its standby state (see Figures 28 and 29). VLOGIC Requirements Read Operation A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 30). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL23318 responds with an ACK; then the ISL23318 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (see Figure 30). 16 It is recommended to keep VLOGIC powered all the time during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23318. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible. VCC Requirements and Placement It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., 7Eh to 7Fh, which have higher transient glitch. Note that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN7887.0 July 26, 2011 ISL23318 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 7/26/11 FN7887.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL23318 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7887.0 July 26, 2011 ISL23318 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L SEATING PLANE C -A0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - θ 5o 15o 5o 15o - α 0o 6o 0o 6o Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 18 FN7887.0 July 26, 2011 ISL23318 Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 8. PIN 1 INDEX AREA 2.10 A B PIN #1 ID 1 0.05 MIN. 1 8. 4 4X 0.20 MIN. 1.60 0.10 MIN. 10 5 0.80 10X 0.40 0.10 6 9 2X 6X 0.50 10 X 0.20 4 TOP VIEW 0.10 M C A B M C BOTTOM VIEW (10 X 0.20) SEE DETAIL "X" (0.05 MIN) PACKAGE OUTLINE 1 MAX. 0.55 0.10 C (10X 0.60) C (0.10 MIN.) (2.00) SEATING PLANE 0.08 C SIDE VIEW (0.80) (1.30) C 0 . 125 REF (6X 0.50 ) (2.50) 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 19 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Maximum package warpage is 0.05mm. 6. Maximum allowable burrs is 0.076mm in all directions. 7. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. 8. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7887.0 July 26, 2011