TI1 ISO7842 High-performance, 8000-vpk reinforced quad-channel digital isolator Datasheet

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ISO7842, ISO7842F
SLLSEJ0F – OCTOBER 2014 – REVISED APRIL 2016
ISO7842x High-Performance, 8000-VPK Reinforced Quad-Channel Digital Isolator
1 Features
3 Description
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•
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The ISO7842x device is a high-performance, quadchannel digital isolator with a 8000-VPK isolation
voltage. This device has reinforced isolation
certifications according to VDE, CSA, CQC, and TUV.
The isolator provides high electromagnetic immunity
and low emissions at low-power consumption, while
isolating CMOS or LVCMOS digital I/Os. Each
isolation channel has a logic input and output buffer
separated by a silicon-dioxide (SiO2) insulation
barrier.
1
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•
•
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Signaling Rate: Up to 100 Mbps
Wide Supply Range: 2.25 V to 5.5 V
2.25-V to 5.5-V Level Translation
Wide Temperature Range: –55°C to +125°C
Low-Power Consumption, Typical 1.7 mA per
Channel at 1 Mbps
Low Propagation Delay: 11 ns Typical
(5-V Supplies)
Industry leading CMTI (Min): ±100 kV/μs
Robust Electromagnetic Compatibility (EMC)
System-Level ESD, EFT, and Surge Immunity
Low Emissions
Isolation Barrier Life: >40 Years
Wide Body SOIC-16 Package and Extra-Wide
Body SOIC-16 Package Options
Safety and Regulatory Approvals:
– 8000-VPK Reinforced Isolation per DIN V VDE
V 0884-10 (VDE V 0884-10):2006-12
– 5.7-kVRMS Isolation for 1 Minute per UL 1577
– CSA Component Acceptance Notice 5A, IEC
60950-1 and IEC 60601-1 End Equipment
Standards
– CQC Certification per GB4943.1-2011
– TUV Certification per EN 61010-1 and EN
60950-1
– All DW Package Certifications Complete;
DWW Package Certifications Complete per
UL, VDE, TUV and Planned for CSA and CQC
2 Applications
•
•
•
•
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Industrial Automation
Motor Control
Power Supplies
Solar Inverters
Medical Equipment
Hybrid Electric Vehicles
This device comes with enable pins that can be used
to put the respective outputs in high impedance for
multi-master driving applications and to reduce power
consumption. The ISO7842 device has two forward
and two reverse-direction channels. If the input power
or signal is lost, the default output is high for the
ISO7842 device and low for the ISO7842F device.
See the Device Functional Modes section for further
details.
Used in conjunction with isolated power supplies, this
device helps prevent noise currents on a data bus or
other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
Through innovative chip design and layout
techniques, electromagnetic compatibility of the
ISO7842 device has been significantly enhanced to
ease system-level ESD, EFT, surge, and emissions
compliance.
The ISO7842 device is available in 16-pin SOIC
wide-body (DW) and extra-wide body (DWW)
packages.
Device Information(1)
PART NUMBER
ISO7842
ISO7842F
PACKAGE
BODY SIZE (NOM)
DW (16)
10.30 mm × 7.50 mm
DWW (16)
10.30 mm × 14.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCCI
Isolation
Capacitor
VCCO
INx
OUTx
ENx
GNDI
GNDO
VCCI and GNDI are supply and ground
connections respectively for the input
channels.
VCCO and GNDO are supply and ground
connections respectively for the output
channels.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISO7842, ISO7842F
SLLSEJ0F – OCTOBER 2014 – REVISED APRIL 2016
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
1
1
1
2
5
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Power Dissipation Characteristics ............................ 7
Electrical Characteristics–5-V Supply ....................... 8
Supply Current Characteristics–5-V Supply.............. 8
Electrical Characteristics—3.3-V Supply .................. 9
Supply Current Characteristics—3.3-V Supply ......... 9
Electrical Characteristics—2.5-V Supply .............. 10
Supply Current Characteristics—2.5-V Supply ..... 10
Switching Characteristics—5-V Supply................. 11
Switching Characteristics—3.3-V Supply.............. 11
Switching Characteristics—2.5-V Supply.............. 12
Typical Characteristics .......................................... 13
7
8
Parameter Measurement Information ................ 14
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
17
21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 25
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2016) to Revision F
Page
•
Changed the number of years for the isolation barrier life in the Features section .............................................................. 1
•
VDE certification is now complete ......................................................................................................................................... 1
•
Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical
characteristics tables .............................................................................................................................................................. 8
•
Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics tables 8
•
Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section ......................... 18
Changes from Revision D (December 2015) to Revision E
Page
•
Changed the Safety and Regulatory Approvals list of Features ............................................................................................ 1
•
Added Features "TUV Certification per EN 61010-1 and EN 60950-1" ................................................................................. 1
•
Changed text in the first paragraph of the Description From: "certifications according to VDE, CSA, and CQC". To:
"certifications according to VDE, CSA, CQC, and TUV." ...................................................................................................... 1
•
Added Note 1 to Table 3 ..................................................................................................................................................... 18
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Changed Table 4 .................................................................................................................................................................. 19
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Added TUV to the Regulatory Information section and Table 5. Deleted Note 1 in Table 5 .............................................. 19
•
Changed Figure 17 .............................................................................................................................................................. 21
Changes from Revision C (July 2015) to Revision D
Page
•
Added Features: DW Package Certifications Complete; DWW Certifications Planned ......................................................... 1
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Added text to the Description: and extra-wide body (DWW) packages. ............................................................................... 1
•
Added package: Extra wide SOIC, DWW (16) to the Device Information table..................................................................... 1
2
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•
Changed the MIN value of CMTI in Electrical Characteristics–5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted
the TYP value of 100 kV/μs.................................................................................................................................................... 8
•
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Electrical Characteristics–5-V Supply ............. 8
•
Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Electrical Characteristics–5-V Supply ...... 8
•
Changed the MIN value of CMTI in Electrical Characteristics—3.3-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs ....................................................................................................................................... 9
•
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Electrical Characteristics—3.3-V Supply......... 9
•
Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Electrical Characteristics—3.3-V Supply .. 9
•
Changed the MIN value of CMTI in Electrical Characteristics—2.5-V Supply, 5 V table From: 70 To: 100 kV/μs,
deleted the TYP value of 100 kV/μs ..................................................................................................................................... 10
•
Added the Supply Current - ISO7842DW and ISO7842FDW section to the Electrical Characteristics—2.5-V Supply....... 10
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Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Electrical Characteristics—2.5-V Supply 10
•
Added the 16-DWW Package to Table 2 ............................................................................................................................. 17
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Added the DWW package information to Table 3 ................................................................................................................ 18
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Added the DWW package information to Table 5 ................................................................................................................ 19
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Added text to the Application Information section: " isolation voltage per UL 1577." ......................................................... 22
Changes from Revision B (April 2015) to Revision C
Page
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Added device ISO7482F to the datasheet ............................................................................................................................. 1
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Changed the Description to include: " default output is 'high' for the ISO7842 device and 'low' for the ISO7842F device. .. 1
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Changed From: tPLH and tPHLat 5.5V To: tPLH and tPHL at 5.0 V ........................................................................................... 13
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Changed Figure 9................................................................................................................................................................. 15
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Changed Figure 15 , Added Figure 16 ................................................................................................................................. 20
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Added the Device I/O Schematics section .......................................................................................................................... 21
Changes from Revision A (November 2014) to Revision B
Page
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Changed the document title From: "Quad-Channel Digital Isolator" To: "Quad-Channel 2/2 Digital Isolator"....................... 1
•
Added Features 2.25 V to 5.5 V Level Translation ................................................................................................................ 1
•
Changed Features From: Wide Body SOIC-16 Package To: Wide Body and Extra-Wide Body SOIC-16 Package
Options .................................................................................................................................................................................. 1
•
Changed the Safety and Regulatory Approvals list of Features ............................................................................................ 1
•
VDE certification is now complete ......................................................................................................................................... 1
•
Changed the Simplified Schematic and added Notes 1 and 2............................................................................................... 1
•
Added the Power Dissipation Characteristics table................................................................................................................ 7
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Changed Figure 7 ................................................................................................................................................................ 14
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Changed Figure 8 ................................................................................................................................................................ 14
•
Changed From: VCC1 To: VCCI in Figure 9 ............................................................................................................................ 15
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Changed Figure 10............................................................................................................................................................... 15
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Changed Table 2 .................................................................................................................................................................. 17
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Changed the Test Condition of CTI of the table in Table 2 ................................................................................................. 17
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Changed the MIN value of CTI From" > 600 V To: 600 V .................................................................................................. 17
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Changed Table 3 title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To:
Insulation Characteristics...................................................................................................................................................... 18
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Changed Table 3 .................................................................................................................................................................. 18
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Changed the table in Regulatory Information....................................................................................................................... 19
•
Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Table 7 ..................................................................... 21
•
Changed the Application Information section ...................................................................................................................... 22
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•
Changed the Typical Application section ............................................................................................................................ 22
•
Added text and Figure 19 to the Detailed Design Procedure section ................................................................................. 23
Changes from Original (October 2014) to Revision A
Page
•
Changed Feature From: All Agencies Approvals Pending To: All Agencies Approvals Planned .......................................... 1
•
Changed statement in the Description From; "This device is certified to meet reinforced isolation requirements by
VDE and CSA." To: "This device is being reviewed for reinforced isolation certification by VDE and CSA." ....................... 1
•
Added Note: "This coupler..." to the High Voltage Feature Description section ................................................................. 17
•
Changed RIO MIN value From: 109 To: 1011 in the Table 2 table ........................................................................................ 17
•
Changed the first row of information in the Regulatory Information table ........................................................................... 19
4
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5 Pin Configuration and Functions
DW and DWW Packages
16-Pin SOIC
Top View
1
16 VCC2
GND1 2
15 GND2
INA
3
INB
4
14 OUTA
ISOLATION
VCC1
OUTC 5
OUTD 6
EN1
7
GND1 8
13 OUTB
12
INC
11
IND
10
EN2
9 GND2
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN1
7
I
Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in highimpedance state when EN1 is low.
EN2
10
I
Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in highimpedance state when EN2 is low.
GND1
GND2
INA
2
8
9
15
—
Ground connection for VCC1
—
Ground connection for VCC2
3
I
Input, channel A
INB
4
I
Input, channel B
INC
12
I
Input, channel C
IND
11
I
Input, channel D
OUTA
14
O
Output, channel A
OUTB
13
O
Output, channel B
OUTC
5
O
Output, channel C
OUTD
6
O
Output, channel D
VCC1
1
—
Power supply, VCC1
VCC2
16
—
Power supply, VCC2
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6 Specifications
6.1 Absolute Maximum Ratings
See
(1)
VCC1,
VCC2
Supply voltage (2)
Voltage
MAX
–0.5
6
–0.5
VCCX + 0.5
–0.5
VCCX + 0.5 (3)
–0.5
(3)
VCCX + 0.5
–15
Surge immunity
(1)
(2)
(3)
V
(3)
OUTx
Output current
Tstg
UNIT
INx
ENx
IO
MIN
Storage temperature
–65
V
15
mA
12.8
kV
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
Maximum voltage must not exceed 6 V
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±6000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VCC1,
VCC2
Supply voltage
2.25
VCCO
IOH
High-level output current
Low-level output current
(1)
=5V
(1)
MAX
5.5
–2
= 2.5 V
–1
4
VCCO (1) = 3.3 V
2
VCCO
V
mA
VCCO (1) = 5 V
(1)
UNIT
–4
VCCO (1) = 3.3 V
VCCO
IOL
NOM
= 2.5 V
mA
1
VIL
Low-level input voltage
0
0.3 × VCCI (1)
DR
Signaling rate
0
100
Mbps
TJ
Junction temperature (2)
–55
150
°C
TA
Ambient temperature
–55
125
°C
6
VCCI
(1)
High-level input voltage
(1)
(2)
0.7 × VCCI
(1)
VIH
25
V
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
To maintain the recommended operating conditions for TJ, see Thermal Information.
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6.4 Thermal Information
ISO7842
THERMAL METRIC (1)
DW (SOIC)
DWW (SOIC)
16 Pins
16 Pins
UNIT
RθJA
Junction-to-ambient thermal resistance
78.9
78.9
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
41.6
41.1
°C/W
RθJB
Junction-to-board thermal resistance
43.6
49.5
°C/W
ψJT
Junction-to-top characterization parameter
15.5
15.2
°C/W
ψJB
Junction-to-board characterization parameter
43.1
48.8
°C/W
N/A
N/A
°C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Dissipation Characteristics
VALUE
PD
Maximum power dissipation by ISO78420x
PD1
Maximum power dissipation by side-1 of
ISO78420x
PD2
Maximum power dissipation by side-2 of
ISO78420x
UNIT
200
VCC1 = VCC2 = 5.5 V, TJ = 150°C,
CL = 15 pF, input a 50 MHz 50% duty cycle
square wave
100
mW
100
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6.6 Electrical Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
VOH
High-level output voltage
IOH = –4 mA; see Figure 7
VOL
Low-level output voltage
IOL = 4 mA; see Figure 7
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
-10
CMTI
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 10
100
(1)
0.2
0.1 × VCCI
MAX
UNIT
V
0.4
(1)
V
V
10
μA
kV/μs
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.7 Supply Current Characteristics–5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.3
4.6
mA
10 Mbps
ICC1, ICC2
4.2
5.6
mA
100 Mbps
ICC1, ICC2
13.7
16.6
mA
EN1 = EN2 = 0V, VI = 0 V (ISO7842F),
VI = VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1)
(ISO7842F), VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.4
4.7
mA
10 Mbps
ICC1, ICC2
4.3
5.9
mA
100 Mbps
ICC1, ICC2
14
17.3
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0V, VI = 0 V (ISO7842F),
VI = VCCI (1) (ISO7842)
(1)
EN1 = EN2 = 0 V, VI = VCCI
(ISO7842F), VI = 0 V (ISO7842)
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW AND ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
8
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.8 Electrical Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –2 mA; see Figure 7
VOL
Low-level output voltage
IOL = 2 mA; see Figure 7
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
–10
μA
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 10
100
kV/μs
CMTI
(1)
0.2
V
0.4
V
10
μA
0.1 × VCCI (1)
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.9 Supply Current Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.3
4.5
mA
10 Mbps
ICC1, ICC2
4
5.2
mA
100 Mbps
ICC1, ICC2
10.8
12.9
mA
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1) (ISO7842F),
VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.4
4.7
mA
10 Mbps
ICC1, ICC2
4.1
5.5
mA
100 Mbps
ICC1, ICC2
11
13.6
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
EN1 = EN2 = 0 V, VI = VCCI
VI = 0 V (ISO7842)
(1)
(ISO7842F),
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW and ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.10 Electrical Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VCCO (1) – 0.4
VCCO (1) – 0.2
MAX
UNIT
VOH
High-level output voltage
IOH = –1 mA; see Figure 7
VOL
Low-level output voltage
IOL = 1 mA; see Figure 7
VI(HYS)
Input threshold voltage hysteresis
IIH
High-level input current
VIH = VCCI (1) at INx or ENx
IIL
Low-level input current
VIL = 0 V at INx or ENx
–10
μA
Common-mode transient immunity
VI = VCCI (1) or 0 V, VCM = 1500 V; see
Figure 10
100
kV/μs
CMTI
(1)
V
0.2
0.4
V
10
μA
0.1 × VCCI (1)
V
VCCI = Input-side VCC; VCCO = Output-side VCC.
6.11 Supply Current Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
SUPPLY
CURRENT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1, ICC2
1
1.5
mA
ICC1, ICC2
3.4
4.8
mA
ICC1, ICC2
2
2.7
mA
VI = VCCI (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.1
mA
1 Mbps
ICC1, ICC2
3.2
4.5
mA
10 Mbps
ICC1, ICC2
3.7
5.1
mA
100 Mbps
ICC1, ICC2
8.9
10.8
mA
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
ICC1, ICC2
1
1.5
mA
EN1 = EN2 = 0 V, VI = VCCI (1) (ISO7842F),
VI = 0 V (ISO7842)
ICC1, ICC2
3.4
4.8
mA
VI = 0 V (ISO7842F), VI = VCCI (1)
(ISO7842)
ICC1, ICC2
2
2.8
mA
VI = VCCI (1) (ISO7842F), VI = 0 V
(ISO7842)
ICC1, ICC2
4.4
6.3
mA
1 Mbps
ICC1, ICC2
3.3
4.6
mA
10 Mbps
ICC1, ICC2
3.8
5.3
mA
100 Mbps
ICC1, ICC2
9
11.5
mA
ISO7842DW AND ISO7842FDW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI
= VCCI (1) (ISO7842)
EN1 = EN2 = 0 V, VI = VCCI
VI = 0 V (ISO7842)
(1)
(ISO7842F),
VI = 0 V (ISO7842F), VI = VCCI
(ISO7842)
(1)
(1)
ISO7842DWW AND ISO7842FDWW
Disable
Supply current
DC signal
All channels switching with
square wave clock input;
CL = 15 pF
(1)
10
VCCI = Input-side VCC; VCCO = Output-side VCC.
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6.12 Switching Characteristics—5-V Supply
VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
11
16
ns
0.55
4.1
ns
2.5
ns
4.5
ns
1.7
3.9
ns
1.9
3.9
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
12
20
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
12
20
ns
10
20
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
10
20
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
Same-direction channels
See Figure 7
Enable propagation delay, high impedance-to-high
output for ISO7842F
tPZL
tfs
Default output delay time from input power loss
tie
(3)
See Figure 7
Enable propagation delay, high impedance-to-high
output for ISO7842
tPZH
(1)
(2)
TEST CONDITIONS
See Figure 8
Measured from the time VCC goes below 1.7 V. See
Figure 9
16
Time interval error
UNIT
2
0.90
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6.13 Switching Characteristics—3.3-V Supply
VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
6
10.8
16
ns
0.7
4.2
ns
2.2
ns
4.5
ns
0.8
3
ns
0.8
3
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
17
32
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
17
32
ns
17
32
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
17
32
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPZH
tPZL
tfs
tie
(1)
(2)
(3)
TEST CONDITIONS
See Figure 7
Same-direction channels
See Figure 7
Enable propagation delay, high impedance-to-high
output for ISO7842
Enable propagation delay, high impedance-to-high
output for ISO7842F
Default output delay time from input power loss
See Figure 8
Measured from the time VCC goes below 1.7 V.
See Figure 9
16
Time interval error
UNIT
2
– 1 PRBS data at 100 Mbps
0.91
ns
Also known as Pulse Skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.14 Switching Characteristics—2.5-V Supply
VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
7.5
11.7
17.5
ns
0.66
4.2
ns
2.2
ns
4.5
ns
1
3.5
ns
1.2
3.5
ns
tPHZ
Disable propagation delay, high-to-high impedance
output
22
45
ns
tPLZ
Disable propagation delay, low-to-high impedance
output
22
45
ns
18
45
ns
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842
2
2.5
μs
Enable propagation delay, high impedance-to-low
output for ISO7842F
18
45
ns
0.2
9
μs
tPLH, tPHL
Propagation delay time
PWD
Pulse width distortion (1) |tPHL – tPLH|
tsk(o)
Channel-to-channel output skew time (2)
tsk(pp)
Part-to-part skew time (3)
tr
Output signal rise time
tf
Output signal fall time
tPZH
tPZL
tfs
tie
(1)
(2)
(3)
12
TEST CONDITIONS
See Figure 7
Same-direction Channels
See Figure 7
Enable propagation delay, high impedance-to-high
output for ISO7842
Enable propagation delay, high impedance-to-high
output for ISO7842F
Default output delay time from input power loss
Time interval error
See Figure 8
Measured from the time VCC goes below 1.7 V.
See Figure 9
16
2
0.91
– 1 PRBS data at 100 Mbps
ns
Also known as pulse skew.
tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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6.15 Typical Characteristics
24
10
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5.0 V
ICC2 at 5.0 V
16
ICC1 at 2.5 V
ICC2 at 2.5 V
ICC1 at 3.3 V
ICC2 at 3.3 V
ICC1 at 5.0 V
ICC2 at 5.0 V
8
Supply Current (mA)
Supply Current (mA)
20
12
8
6
4
2
4
0
0
0
25
50
TA = 25°C
75
100
Data Rate (Mbps)
125
150
0
CL = 15 pF
75
100
Data Rate (Mbps)
125
150
D002
CL = No Load
Figure 1. Supply Current vs Data Rate (With 15-pF Load)
Figure 2. Supply Current vs Data Rate (With No Load)
6
1
5
Low-Level Output Voltage (V)
High-Level Output Voltage (V)
50
TA = 25°C
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
0.9
4
3
2
VCC at 2.5 V
VCC at 3.3 V
VCC at 5.0 V
1
0
-15
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-10
-5
High-Level Output Current (mA)
0
0
13
VCC1 Rising
VCC1 Falling
VCC2 Rising
VCC2 Falling
Propagation Delay Time (ns)
2.1
2.05
2
1.95
1.9
1.85
1.8
12
11
10
9
tPLH at 2.5 V
tPHL at 2.5 V
tPLH at 3.3 V
1.75
1.7
-50
D004
D001
Figure 4. Low-Level Output Voltage vs Low-Level Output
Current
2.25
2.15
15
TA = 25°C
Figure 3. High-Level Output Voltage vs High-level Output
Current
2.2
5
10
Low-Level Output Current (mA)
D003
TA = 25°C
Power Supply Under-Voltage Threshold (V)
25
D001
0
50
100
Free-Air Temperature (oC)
150
8
-60
-30
D005
Figure 5. Power Supply Undervoltage Threshold vs Free-Air
Temperature
0
30
60
Free-Air Temperature (oC)
tPHL at 3.3 V
tPLH at 5.0 V
tPHL at 5.0 V
90
120
D006
Figure 6. Propagation Delay Time vs Free-Air Temperature
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7 Parameter Measurement Information
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
VCCI
50
VI
OUT
50%
50%
0V
tPLH
tPHL
CL
See Note B
VO
VOH
90%
50%
VO
50%
10%
VOL
tf
tr
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A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 7. Switching Characteristics Test Circuit and Voltage Waveforms
VCCO
VCC
Isolation Barrier
IN
Input
Generator
(See Note A)
VI
Input
Generator
(See Note A)
VO
tPZL
0V
tPLZ
VOH
EN
0.5 V
VO
50%
VOL
50
OUT
VCC
VO
VCC / 2
VCC / 2
VI
0V
tPZH
EN
CL
See Note B
VI
VCC / 2
VCC / 2
VI
CL
See Note B
IN
3V
±1%
OUT
Isolation Barrier
0V
RL = 1 k
RL = 1 k
±1%
VOH
50%
VO
0.5 V
tPHZ
50
0V
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A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8. Enable/Disable Propagation Delay Time Test Circuit and Waveform
14
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Parameter Measurement Information (continued)
VI
VCC
VCC
Isolation Barrier
IN = 0 V (Devices without suffix F)
IN = VCC (Devices with suffix F)
IN
2.7 V
VI
OUT
0V
t fs
VO
fs high
VO
CL
VOH
50%
fs low V
OL
See Note A
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A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 9. Default Output Delay Time Test Circuit and Voltage Waveforms
VCCO
VCCI
S1
Isolation Barrier
C = 0.1 µF ±1%
IN
C = 0.1 µF ±1%
Pass-fail criteria:
The output must
remain stable.
OUT
+
EN
CL
See Note A
GNDI
+
VCM ±
VOH or VOL
±
GNDO
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A.
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 10. Common-Mode Transient Immunity Test Circuit
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8 Detailed Description
8.1 Overview
The ISO7842 device uses an ON-OFF Keying (OOK) modulation scheme to transmit the digital data across a
silicon-dioxide based isolation barrier. The transmitter sends a high-frequency carrier across the barrier to
represent one digital state and sends no signal to represent the other digital state. The receiver demodulates the
signal after advanced signal conditioning and produces the output through a buffer stage. If the EN pin is low
then the output goes to high impedance. The ISO7842 device also incorporates advanced circuit techniques to
maximize the CMTI performance and minimize the radiated emissions because of the high-frequency carrier and
IO buffer switching. The conceptual block diagram of a digital capacitive isolator, Figure 11, shows a functional
block diagram of a typical channel.
8.2 Functional Block Diagram
Transmitter
Receiver
EN
TX IN
OOK
Modulation
TX Signal
Conditioning
Oscillator
SiO2 based
Capacitive
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Emissions
Reduction
Techniques
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Figure 11. Conceptual Block Diagram of a Digital Capacitive Isolator
Figure 12 shows a conceptual detail of how the ON-OFF keying scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 12. On-Off Keying (OOK) Based Modulation Scheme
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8.3 Feature Description
Table 1 lists the device features.
Table 1. Device Features
PART
NUMBER
CHANNEL DIRECTION
2 Forward,
ISO7842
2 Reverse
ISO7842F
(1)
RATED ISOLATION
2 Forward,
2 Reverse
MAXIMUM DATA RATE
DEFAULT OUTPUT
5700 VRMS / 8000 VPK
(1)
100 Mbps
High
5700 VRMS / 8000 VPK
(1)
100 Mbps
Low
See Regulatory Information for detailed isolation ratings.
8.3.1 High Voltage Feature Description
NOTE
This coupler is suitable for 'safe electrical insulation' only within the safety ratings.
Compliance with the safety ratings shall be ensured by means of suitable protective
circuits.
Table 2. Package Insulation and Safety-Related Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
CLR
CPG
CTI
External clearance
External creepage
Comparative tracking index
TEST CONDITIONS
Shortest terminal-to-terminal distance
through air
Shortest terminal-to-terminal distance
across the package surface
MIN
16-DW
Package
8
16-DWW
Package
14.5
16-DW
Package
8
16-DWW
Package
14.5
TYP
MAX
UNIT
mm
mm
DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A
600
V
VIO = 500 V, TA = 25°C
12
10
Ω
VIO = 500 V, 100°C ≤ TA ≤ max
1011
Ω
RIO
Isolation resistance, input to
output (1)
CIO
Barrier capacitance, input to
output (1)
VIO = 0.4 × sin (2πft), f = 1 MHz
2
pF
CI
Input capacitance (2)
VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz, VCC = 5 V
2
pF
(1)
(2)
All pins on each side of the barrier tied together creating a two-terminal device.
Measured from input pin to ground.
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed-circuit board do not reduce this distance.
Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to
help increase these specifications.
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Table 3. Insulation Characteristics
PARAMETER
SPECIFICATION
TEST CONDITIONS
DW
DWW
UNIT
DTI
Distance through the insulation
Minimum internal gap (internal clearance)
>21
>21
μm
VIOWM
Maximum rated working isolation
voltage
Time dependent dielectric breakdown (TDDB) Test, see
Figure 13 and Figure 14
1500
2000
VRMS
2121
2828
VDC
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIOTM
Maximum rated transient isolation
voltage
VTEST = VIOTM
t = 60 sec (qualification)
t= 1 sec (100% production)
8000
8000
VPK
VIOSM
Maximum surge isolation voltage
for reinforced insulation
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (1) (qualification)
8000
8000
VPK
VIORM
Maximum rated repetitive peak
isolation voltage
2121
2828
VPK
Method a, After Input/Output safety test subgroup 2/3,
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
2545
3394
Method a, After environmental tests subgroup 1,
VPR = VIORM × 1.6, t = 10 s,
Partial Discharge < 5 pC
3394
4525
Method b1,
VPR = VIORM × 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC
3977
5303
VIO = 500 V at TS
>109
>109
Pollution degree
2
2
Climatic category
55/125/21
55/125/21
5700
5700
VPR
Input-to-output test voltage
RS
Isolation resistance
VPK
Ω
UL 1577
VISO
(1)
Maximum withstanding isolation
voltage
VRMS
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
1.E+11
1.E+10
87.5%
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+9
1.E+9
1.E+8
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
Safety Margin Zone: 2400 VRMS, 63 Years
Operating Zone: 2000 VRMS, 34 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
Time to Fail (s)
Time to Fail (s)
VTEST = VISO = 5700 VRMS, t = 60 sec (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 sec (100%
production)
87.5%
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+3
20%
1.E+2
1.E+2
1.E+1
500
1.E+1
400
20%
1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS)
TA upto 150°C
Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
Figure 13. Reinforced Isolation Capacitor Life Time
Projection for Devices in DW Package
18
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1400 2400 3400 4400 5400 6400 7400 8400 9400
Stress Voltage (VRMS)
TA upto 150°C
Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 14. Reinforced Isolation Capacitor Life Time
Projection for Devices in DWW Package
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Table 4. IEC 60664-1 Ratings Table
PARAMETER
TEST CONDITIONS
SPECIFICATION
Material group
Overvoltage category /
Installation classification
I
Rated mains voltage ≤ 600 VRMS
DW package
DWW package
I–IV
Rated mains voltage ≤ 1000 VRMS
I–III
Rated mains voltage ≤ 1000 VRMS
I–IV
8.3.1.1 Regulatory Information
Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV
and planned for CSA and CQC.
Table 5. Regulatory Information
VDE
Certified according to DIN
V VDE V 0884-10 (VDE V
0884-10):2006-12 and DIN
EN 60950-1 (VDE 0805
Teil 1):2011-01
CSA
UL
Approved under CSA
Component Acceptance
Notice 5A, IEC 60950-1 and
IEC 60601-1
Certified according to UL
1577 Component
Recognition Program
CQC
TUV
Certified according to GB
4943.1-2011
Reinforced insulation per CSA
60950-1-07+A1+A2 and IEC
60950-1 2nd Ed., 800 VRMS
Reinforced insulation
(DW package) and 1450 VRMS
Maximum transient
isolation voltage, 8000 VPK; (DWW package) max working
voltage (pollution degree 2,
Maximum repetitive peak
Single protection, 5700
isolation voltage, 2121 VPK material group I);
VRMS
(DW), 2828 VPK (DWW);
2 MOPP (Means of Patient
Maximum surge isolation
Protection) per CSA 60601voltage, 8000 VPK
1:14 and IEC 60601-1 Ed. 3.1,
250 VRMS (354 VPK) max
working voltage (DW package)
Reinforced Insulation,
Altitude ≤ 5000 m, Tropical
Climate, 250 VRMS
maximum working voltage
Certificate number:
40040142
Certificate number:
CQC15001121716
Master contract number:
220991
File number: E181974
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Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
working voltage of 600 VRMS (DW
package) and 1000 VRMS (DWW
package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS (DW package) and
1450 VRMS (DWW package)
Client ID number: 77311
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8.3.1.2 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier potentially leading to secondary system failures.
Table 6. Safety Limiting Values
PARAMETER
Safety input, output, or supply
current
IS
PS
Safety input, output, or total
power
TS
Maximum safety temperature
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
288
RθJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
440
RθJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C
576
RθJA = 78.9°C/W, TJ = 150°C, TA = 25°C
1584
mW
150
°C
mA
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
1800
700
1600
Safety Limiting Power (mW)
600
Safety Limiting Current (mA)
Power
VCC1 = VCC2 = 2.75 V
VCC1 = VCC2 = 3.6 V
VCC1 = VCC2 = 5.5 V
500
400
300
200
100
1200
1000
800
600
400
200
0
0
0
50
100
150
Ambient Temperature (qC)
200
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50
D014
Figure 15. Thermal Derating Curve for Safety Limiting
Current per VDE
20
1400
100
150
Ambient Temperature (qC)
200
D015
Figure 16. Thermal Derating Curve for Safety Limiting
Power per VDE
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8.4 Device Functional Modes
Table 7 lists the ISO7842 functional modes.
Table 7. Function Table (1)
VCCI
VCCO
PU
PU
X
(1)
(2)
(3)
PU
INPUT
(INx) (2)
OUTPUT
ENABLE
(ENx)
OUTPUT
(OUTx)
H
H or open
H
L
H or open
L
Open
H or open
Default
X
L
Z
PD
PU
X
H or open
Default
X
PD
X
X
Undetermined
COMMENTS
Normal Operation:
A channel output assumes the logic state of its input.
Default mode: When INx is open, the corresponding channel output goes to
its default logic state. Default= High for ISO7842 and Low for ISO7842F.
A low value of Output Enable causes the outputs to be high-impedance
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. Default= High for ISO7842 and
Low for ISO7842F.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of its input.
When VCCI transitions from powered-up to unpowered, channel output
assumes the selected default state.
When VCCO is unpowered, a channel output is undetermined (3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of its input
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level ; Z = High Impedance
A strongly driven input signal can weakly power the floating VCC through an internal protection diode and cause undetermined output.
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4.1 Device I/O Schematics
Input (Device Without Suffix F)
VCCI
VCCI
Input (Device With Suffix F)
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 MW
985 W
985 W
INx
INx
1.5 MW
Output
Enable
VCCO
VCCO
VCCO VCCO
VCCO
2 MW
1970 W
~20 W
OUTx
Enx
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Device I/O Schematics
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO7842 device is a high-performance, quad-channel digital isolator with a 5.7-kVRMS isolation voltage per
UL 1577. The device comes with enable pins on each side that can be used to put the respective outputs in high
impedance for multi-master driving applications and reduce power consumption. The ISO7842 device uses
single-ended CMOS-logic switching technology. The supply voltage range is from 2.25 V to 5.5 V for both
supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended
design structure, digital isolators do not conform to any specific interface standard and are only intended for
isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data
controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or
standard.
9.2 Typical Application
Figure 18 shows the typical isolated RS-232 interface implementation.
VIN
3.3 V
0.1 F
2
Vcc D2 3
1:2.1 MBR0520L
1
SN6501
10 F 0.1 F
GND D1
1
10 F
4, 5
MBR0520L
OU 5
T
LP2985-50
3
4
ON
BP
GND
2
10 nF
5 VISO
IN
3.3 F
Isolation
Barrier
0.1 F
0.1 F
0.1 F
16
1 F
0.1 F
1
4.7 k
2
7
DVcc
5
6
UCA0TXD
XOUT
XIN
4
EN1
VCC2
EN2
1
4.7 k
1 F
10
3
16
5
INA
GND1
2, 8
3
11
14
OUTA
ISO7842
12
OUTC
INC
4
13
OUTB
INB
6
11
OUTD
IND
15
UCA0RXD
12
MSP430F2132
P3.1
11
P3.0
DVss
VCC1
16
2
12
10
9
GND2
Vcc
VS±
VS+
C1+
C1±
C2+
TRS232
C2±
T1IN
T1OUT
R1OUT
R1IN
T2OUT
T2IN
R2IN
R2OUT
GND
6
1 F
4
5
14
13
7
8
1 F
TxD
RxD
RST
CST
15
9, 15
ISOGND
Copyright © 2016, Texas Instruments Incorporated
Figure 18. Isolated RS-232 Interface
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use the parameters shown in Table 8.
Table 8. Design Parameters
PARAMETER
VALUE
Supply voltage
2.25 to 5.5 V
Decoupling capacitor between VCC1 and GND1
0.1 µF
Decoupling capacitor from VCC2 and GND2
0.1 µF
9.2.2 Detailed Design Procedure
Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,
the ISO7842 device only requires two external bypass capacitors to operate.
VCC1
VCC2
0.1 µF
0.1 µF
VCC1
1
GND1
2
GND2
INA
INA
3
14 OUTA
OUTB
INB
INB
4
13 OUTB
OUTC
OUTC
OUTC
5
12
INC
INC
OUTD
OUTD
6
11
IND
IND
EN1
7
10
EN2
GND1
8
9
GND2
GND1
EN
GND1
16
VCC2
GND2
EN
GND2
ISO7842
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Typical ISO7842 Circuit Hook-Up
9.2.2.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO7842
device incorporates many chip-level design improvements for overall system robustness. Some of these
improvements include
• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
• Low-resistance connectivity of ESD cells to supply and ground pins.
• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
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9.2.3 Application Curve
The typical eye diagram of the ISO7842 device indicates low jitter and wide open eye at the maximum data rate
of 100 Mbps.
Figure 20. Eye Diagram at 100 Mbps PRBS, 5 V and 25°C
10 Power Supply Recommendations
To help ensure reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended
at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as
possible. If only a single primary-side power supply is available in an application, isolated power can be
generated for the secondary-side with the help of a transformer driver such as Texas InstrumentsSN6501. For
such applications, detailed power supply design and transformer selection recommendations are available in the
SN6501 data sheet (SLLSEA0).
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11 Layout
11.1 Layout Guidelines
A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 21). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to
the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the
power and ground plane of each power system can be placed closer together, thus increasing the high-frequency
bypass capacitance significantly.
For detailed layout recommendations, see the application note, Digital Isolator Design Guide (SLLA284).
11.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
11.2 Layout Example
High-speed traces
10 mils
Ground plane
40 mils
Keep this
space free
from planes,
traces, pads,
and vias
FR-4
0r ~ 4.5
Power plane
10 mils
Low-speed traces
Figure 21. Layout Example Schematic
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Digital Isolator Design Guide, SLLA284
• Isolation Glossary , SLLA353
• LP2985 150-mA Low-noise Low-dropout Regulator With Shutdown, SLVS522
• MSP430G2x32, MSP430G2x02 Mixed Signal Microcontroller, SLAS723
• SN6501 Transformer Driver for Isolated Power Supplies, SLLSEA0
• TRS232 Dual RS-232 Driver/Receiver With IEC61000-4-2 Protection, SLLS861
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ISO7842
Click here
Click here
Click here
Click here
Click here
ISO7842F
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A
16X
B
7.6
7.4
NOTE 4
2.65 MAX
B
0.38
TYP
0.25
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4221009/A 08/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-013, variation AA.
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EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
16X (1.65)
SEE
DETAILS
1
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/A 08/2013
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
9
8
9
8
(9.3)
(9.75)
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/A 08/2013
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
DWW0016A
SOIC - 2.65 mm max height
SCALE 1.000
PLASTIC SMALL OUTLINE
C
17.4
17.1
A
SEATING PLANE
0.1 C
PIN 1 ID AREA
14X 1.27
16
1
10.4
10.2
NOTE 3
2X
8.89
8
9
16X
14.1
13.9
NOTE 4
B
0.25
0.51
0.31
A B
(2.286)
C
2.65 MAX
0.28
TYP
0.22
SEE DETAIL A
(1.625)
0.25
GAGE PLANE
0.3
0.1
1.1
0.6
0 -8
DETAIL A
TYPICAL
4221501/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0,15 mm per side.
4. This dimension does not include interlead flash.
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EXAMPLE BOARD LAYOUT
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (2)
16X (1.875)
(14.25)
(14.5)
16X (0.6)
16X (0.6)
1
1
16
16
SYMM
SYMM
14X
(1.27)
9
8
SYMM
14X
(1.27)
9
8
SYMM
(16.375)
(16.25)
LAND PATTERN EXAMPLE
LAND PATTERN EXAMPLE
STANDARD
SCALE:3X
PCB CLEARANCE & CREEPAGE OPTIMIZED
SCALE:3X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221501/A 11/2014
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DWW0016A
SOIC - 2.65 mm max height
PLASTIC SMALL OUTLINE
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
(16.25)
SOLDER PASTE EXAMPLE
STANDARD
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
16X (1.875)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
(16.375)
SOLDER PASTE EXAMPLE
PCB CLEARANCE & CREEPAGE OPTIMIZED
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221501/A 11/2014
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
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19-Jun-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ISO7842DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842
ISO7842DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842
ISO7842DWW
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842
ISO7842DWWR
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842
ISO7842FDW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842F
ISO7842FDWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842F
ISO7842FDWW
ACTIVE
SOIC
DWW
16
45
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842F
ISO7842FDWWR
ACTIVE
SOIC
DWW
16
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ISO7842F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
19-Jun-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.75
10.7
2.7
12.0
16.0
Q1
ISO7842DWR
SOIC
DW
16
2000
330.0
16.4
ISO7842DWWR
SOIC
DWW
16
1000
330.0
24.4
18.0
10.0
3.0
20.0
24.0
Q1
ISO7842FDWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
ISO7842FDWWR
SOIC
DWW
16
1000
330.0
24.4
18.0
10.0
3.0
20.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ISO7842DWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7842DWWR
SOIC
DWW
16
1000
367.0
367.0
45.0
ISO7842FDWR
SOIC
DW
16
2000
367.0
367.0
38.0
ISO7842FDWWR
SOIC
DWW
16
1000
367.0
367.0
45.0
Pack Materials-Page 2
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