TI1 MSP430G2544IRHA40R Msp430g2x44 mixed signal microcontroller Datasheet

MSP430G2744
MSP430G2544
MSP430G2444
www.ti.com
SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
MSP430G2x44 Mixed Signal Microcontrollers
Check for Samples: MSP430G2744, MSP430G2544, MSP430G2444
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
•
•
•
Low Supply Voltage Range: 1.8 V to 3.6 V
Ultra-Low-Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode: 1 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wake Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies
– Internal Very-Low-Power Low-Frequency
(LF) Oscillator
– 32-kHz Crystal
– High-Frequency (HF) Crystal up to 16 MHz
– Resonator
– External Digital Clock Source
– External Resistor
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Three Capture/Compare
Registers
Universal Serial Communication Interface
(USCI)
– Enhanced UART Supports Auto-Baudrate
Detection (LIN)
– IrDA Encoder and Decoder
– Synchronous SPI
– I2C
10-Bit 200-ksps Analog-to-Digital Converter
(ADC) With Internal Reference, Sample-andHold, Autoscan, and Data Transfer Controller
Brownout Detector
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Bootstrap Loader (BSL)
On-Chip Emulation Module
•
•
•
•
Family Members
– MSP430G2444
– 8KB + 256B Flash Memory
– 512B RAM
– MSP430G2544
– 16KB + 256B Flash Memory
– 512B RAM
– MSP430G2744
– 32KB + 256B Flash Memory
– 1KB RAM
Table 1 Summarizes the Family Members
Package Options
– TSSOP: 38 Pin (DA)
– QFN: 40 Pin (RHA)
– DSBGA: 49 Pin (YFF)
– PDIP: 40 Pin (N) Available in Sampling
Quantities as PMS430G2744IN40
For Complete Module Descriptions, See the
MSP430x2xx Family User's Guide (SLAU144)
APPLICATIONS
•
•
Sensor Systems
Radio-Frequency Sensor Front End
DESCRIPTION
The Texas Instruments MSP430™ family of ultra-lowpower microcontrollers consists of several devices
featuring different sets of peripherals targeted for
various applications. The architecture, combined with
five low-power modes, is optimized to achieve
extended battery life in portable measurement
applications. The device features a powerful 16-bit
RISC CPU, 16-bit registers, and constant generators
that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows the device
to wake up from low-power modes to active mode in
less than 1 µs.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
MSP430G2744
MSP430G2544
MSP430G2444
SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
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The MSP430G2x44 series is an ultra-low-power mixed signal microcontroller with two built-in 16-bit timers, a
universal serial communication interface (USCI), 10-bit analog-to-digital converter (ADC) with integrated
reference and data transfer controller (DTC), and 32 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front
ends are another area of application.
Table 1. Available Options (1) (2)
Device
BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
Timer_B
ADC10
Channel
USCI_A0,
USCI_B0
Clock
1
1
32
1
TA3
TB3
12
1
HF, LF,
DCO,
VLO
MSP430G2744IRHA40
MSP430G2744IDA38
MSP430G2744IYFF
MSP430G2544IRHA40
MSP430G2544IDA38
1
1
16
512
TA3
TB3
12
HF, LF,
DCO,
VLO
1
MSP430G2544IYFF
MSP430G2444IRHA40
MSP430G2444IDA38
1
1
8
512
TA3
TB3
12
HF, LF,
DCO,
VLO
1
MSP430G2444IYFF
(1)
(2)
I/O
Package
Type
32
40-QFN
32
38-TSSOP
32
49-DSBGA
32
40-QFN
32
38-TSSOP
32
49-DSBGA
32
40-QFN
32
38-TSSOP
32
49-DSBGA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Functional Block Diagram
VCC
P1.x/P2.x
VSS
2x8
P3.x/P4.x
2x8
XOUT
XIN
Basic Clock
System+
ACLK
Flash
SMCLK
32kB
16kB
8kB
MCLK
16MHz
CPU
incl. 16
Registers
RAM
1kB
512B
512B
ADC10
10−Bit
Ports P1/P2
Ports P3/P4
2x8 I/O
Interrupt
capability,
pull−up/down
resistors
12
Channels,
Autoscan,
DTC
2x8 I/O
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
Timer_B3
JTAG
Interface
Brownout
Protection
Watchdog
WDT+
15/16−Bit
Spy−Bi Wire
Timer_A3
3 CC
Registers
3 CC
Registers,
Shadow
Reg
USCI_A0:
UART/LIN,
IrDA, SPI
USCI_B0:
SPI, I2C
RST/NMI
2
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Device Pinout, TSSOP (DA Package)
TEST/SBWTCK
1
38
P1.7/TA2/TDO/TDI
DVCC
2
37
P1.6/TA1/TDI
P2.5/ROSC
3
36
P1.5/TA0/TMS
DVSS
4
35
P1.4/SMCLK/TCK
XOUT/P2.7
5
34
P1.3/TA2
XIN/P2.6
6
33
P1.2/TA1
RST/NMI/SBWTDIO
7
32
P1.1/TA0
P2.0/ACLK/A0
8
31
P1.0/TACLK/ADC10CLK
P2.1/TAINCLK/SMCLK/A1
9
30
P2.4/TA2/A4/VREF+/VeREF+
P2.2/TA0/A2
10
29
P2.3/TA1/A3/VREF−/VeREF−
P3.0/UCB0STE/UCA0CLK/A5
11
28
P3.7/A7
P3.1/UCB0SIMO/UCB0SDA
12
27
P3.6/A6
P3.2/UCB0SOMI/UCB0SCL
13
26
P3.5/UCA0RXD/UCA0SOMI
P3.3/UCB0CLK/UCA0STE
14
25
P3.4/UCA0TXD/UCA0SIMO
AVSS
15
24
P4.7/TBCLK
AVCC
16
23
P4.6/TBOUTH/A15
P4.0/TB0
17
22
P4.5/TB2/A14
P4.1/TB1
18
21
P4.4/TB1/A13
P4.2/TB2
19
20
P4.3/TB0/A12
TEST/SBWTCK
1
40
P1.7/TA2/TDO/TDI
DVCC
2
39
P1.6/TA1/TDI
Device Pinout, PDIP (N Package)
DVCC
3
38
P1.5/TA0/TMS
P2.5/ROSC
4
37
P1.4/SMCLK/TCK
DVSS
5
36
P1.3/TA2
XOUT/P2.7
6
35
P1.2/TA1
XIN/P2.6
7
34
P1.1/TA0
DVSS
8
33
P1.0/TACLK/ADC10CLK
RST/NMI/SBWTDIO
9
32
P2.4/TA2/A4/VREF+/VeREF+
P2.0/ACLK/A0
10
31
P2.3/TA1/A3/VREF−/VeREF−
P2.1/TAINCLK/SMCLK/A1
11
30
P3.7/A7
P2.2/TA0/A2
12
29
P3.6/A6
P3.0/UCB0STE/UCA0CLK/A5
13
28
P3.5/UCA0RXD/UCA0SOMI
P3.1/UCB0SIMO/UCB0SDA
14
27
P3.4/UCA0TXD/UCA0SIMO
P3.2/UCB0SOMI/UCB0SCL
15
26
P4.7/TBCLK
P3.3/UCB0CLK/UCA0STE
16
25
P4.6/TBOUTH/A15
AVSS
17
24
P4.5/TB2/A14
AVCC
18
23
P4.4/TB1/A13
P4.0/TB0
19
22
P4.3/TB0/A12
P4.1/TB1
20
21
P4.2/TB2
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P1.2/TA1
P1.3/TA2
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
TEST/SBWTCK
DVCC
DVCC
P2.5/ROSC
Device Pinout, QFN (RHA Package)
39 38 37 36 35 34 33 32
DVSS
1
30
P1.1/TA0
XOUT/P2.7
2
29
P1.0/TACLK/ADC10CLK
XIN/P2.6
3
28
P2.4/TA2/A4/VREF+/VeREF+
DVSS
4
27
P2.3/TA1/A3/VREF−/VeREF−
RST/NMI/SBWTDIO
5
26
P3.7/A7
P2.0/ACLK/A0
6
25
P3.6/A6
P2.1/TAINCLK/SMCLK/A1
7
24
P3.5/UCA0RXD/UCA0SOMI
P2.2/TA0/A2
8
23
P3.4/UCA0TXD/UCA0SIMO
P3.0/UCB0STE/UCA0CLK/A5
9
22
P4.7/TBCLK
10
21
P4.6/TBOUTH/A15
P3.1/UCB0SIMO/UCB0SDA
P4.5/TB2/A14
P4.4/TB1/A13
P4.3/TB0/A12
P4.1/TB1
P4.2/TB2
P4.0/TB0
AVCC
AVSS
P3.3/UCB0CLK/UCA0STE
P3.2/UCB0SOMI/UCB0SCL
12 13 14 15 16 17 18 19
Device Pinout, DSBGA (YFF Package)
YFF PACKAGE
(TOP VIEW)
D
YFF PACKAGE
(BALL-SIDE VIEW)
G7
G6
G5
G4
G3
G2
G1
G1
G2
G3
G4
G5
G6
G7
P4.6
P3.4
P3.5
P3.7
P2.4
P1.1
P1.3
P1.3
P1.1
P2.4
P3.7
P3.5
P3.4
P4.6
F7
F6
F5
F4
F3
F2
F1
F1
F2
F3
F4
F5
F6
F7
P4.4
P4.5
P4.7
P3.6
P2.3
P1.0
P1.4
P1.4
P1.0
P2.3
P3.6
P4.7
P4.5
P4.4
E7
E6
E5
E4
E3
E2
E1
E1
E2
E3
E4
E5
E6
E7
P4.3
P4.2
DVCC
DVCC
P1.6
P1.2
P1.5
P1.5
P1.2
P1.6
DVCC
DVCC
P4.2
P4.3
D7
D6
D5
D4
D3
D2
D1
D1
D2
D3
D4
D5
D6
D7
P4.1
P4.0
AVCC
DVCC
DVCC
P1.7
TEST
TEST
P1.7
DVCC
DVCC
AVCC
P4.0
P4.1
C7
C6
C5
C4
C3
C2
C1
C1
C2
C3
C4
C5
C6
C7
AVCC
AVCC
AVSS
DVSS
DVSS
P2.5
DVCC
DVCC
P2.5
DVSS
DVSS
AVSS
AVCC
AVCC
B7
B6
B5
B4
B3
B2
B1
B1
B2
B3
B4
B5
B6
B7
AVSS
P3.3
P3.0
P2.1 RST/NMI DVSS
DVSS
DVSS
DVSS RST/NMI P2.1
P3.0
P3.3
AVSS
A7
A6
A5
A4
A3
A2
A1
A1
A2
A3
A4
A5
A6
A7
P3.2
P3.1
P2.2
P2.0
DVSS
P2.6
P2.7
P2.7
P2.6
DVSS
P2.0
P2.2
P3.1
P3.2
D
E
4
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Table 2. Terminal Functions
TERMINAL
NO.
NAME
I/O
YFF
DA
N
RHA
F2
31
33
29
DESCRIPTION
General-purpose digital I/O pin
P1.0/TACLK/ADC10CLK
I/O
Timer_A, clock signal TACLK input
ADC10, conversion clock
P1.1/TA0
G2
32
34
30
I/O
P1.2/TA1
E2
33
35
31
I/O
P1.3/TA2
G1
34
36
32
I/O
P1.4/SMCLK/TCK
F1
35
37
33
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: OUT0 output; BSL transmit
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
SMCLK signal output
Test Clock input for device programming and test
General-purpose digital I/O pin
P1.5/TA0/TMS
E1
36
38
34
I/O
Timer_A, compare: OUT0 output
Test Mode Select input for device programming and test
General-purpose digital I/O pin
P1.6/TA1/TDI/TCLK
E3
37
39
35
I/O
Timer_A, compare: OUT1 output
Test Data Input or Test Clock Input for programming and test
General-purpose digital I/O pin
P1.7/TA2/TDO/TDI
(1)
D2
38
40
36
I/O
Timer_A, compare: OUT2 output
Test Data Output or Test Data Input for programming and test
General-purpose digital I/O pin
P2.0/ACLK/A0
A4
8
10
6
I/O
ACLK output
ADC10, analog input A0
General-purpose digital I/O pin
P2.1/TAINCLK/
SMCLK/A1
B4
9
11
7
I/O
Timer_A, clock signal at INCLK, SMCLK signal output
ADC10, analog input A1
General-purpose digital I/O pin
P2.2/TA0/A2
A5
10
12
8
I/O
Timer_A, capture: CCI0B input; BSL receive, compare: OUT0 output
ADC10, analog input A2
General-purpose digital I/O pin
P2.3/TA1/A3/ VREF-/VeREF-
F3
29
31
27
I/O
Timer_A, capture CCI1B input, compare: OUT1 output
ADC10, analog input A3
Negative reference voltage output/input
General-purpose digital I/O pin
P2.4/TA2/A4/
VREF+/VeREF+
G3
30
32
28
I/O
Timer_A, compare: OUT2 output
ADC10, analog input A4
Positive reference voltage output/input
P2.5/ROSC
C2
3
4
40
I/O
XIN/P2.6
A2
6
7
3
I/O
(1)
General-purpose digital I/O pin
Input for external DCO resistor to define DCO frequency
Input terminal of crystal oscillator
General-purpose digital I/O pin
TDO or TDI is selected via JTAG instruction.
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
XOUT/P2.7
NO.
I/O
YFF
DA
N
RHA
A1
5
6
2
I/O
DESCRIPTION
Output terminal of crystal oscillator
General-purpose digital I/O pin (2)
General-purpose digital I/O pin
P3.0/UCB0STE/
UCA0CLK/A5
B5
11
13
9
I/O
USCI_B0 slave transmit enable
USCI_A0 clock input/output
ADC10, analog input A5
General-purpose digital I/O pin
P3.1/UCB0SIMO/
UCB0SDA
A6
12
14
10
I/O
USCI_B0 slave in, master out in SPI mode
USCI_B0 SDA I2C data in I2C mode
General-purpose digital I/O pin
P3.2/UCB0SOMI/
UCB0SCL
A7
13
15
11
I/O
USCI_B0 slave out, master in SPI mode
USCI_B0 SCL I2C clock in I2C mode
General-purpose digital I/O pin
P3.3/UCB0CLK/
UCA0STE
B6
14
16
12
I/O
USCI_B0 clock input/output
USCI_A0 slave transmit enable
General-purpose digital I/O pin
P3.4/UCA0TXD/
UCA0SIMO
G6
25
27
23
I/O
USCI_A0 transmit data output in UART mode
USCI_A0 slave in, master out in SPI mode
General-purpose digital I/O pin
P3.5/UCA0RXD/
UCA0SOMI
G5
26
28
24
I/O
USCI_A0 receive data input in UART mode
USCI_A0 slave out, master in SPI mode
P3.6/A6
F4
27
29
25
I/O
P3.7/A7
G4
28
30
26
I/O
P4.0/TB0
D6
17
19
15
I/O
P4.1/TB1
D7
18
20
16
I/O
P4.2/TB2
E6
19
21
17
I/O
General-purpose digital I/O pin
ADC10 analog input A6
General-purpose digital I/O pin
ADC10 analog input A7
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
P4.3/TB0/A12
E7
20
22
18
I/O
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12
General-purpose digital I/O pin
P4.4/TB1/A13
F7
21
23
19
I/O
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13
General-purpose digital I/O pin
P4.5/TB2/A14
F6
22
24
20
I/O
Timer_B, compare: OUT2 output
ADC10 analog input A14
General-purpose digital I/O pin
P4.6/TBOUTH/A15
G7
23
25
21
I/O
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15
(2)
6
If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to
this pad after reset.
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Table 2. Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
YFF
DA
N
RHA
P4.7/TBCLK
F5
24
26
22
I/O
RST/NMI/SBWTDIO
B3
7
9
5
I
TEST/SBWTCK
D1
1
1
37
I
DVCC
C1,
D3,
D4,
E4,
E5
2
2, 3
38, 39
Digital supply voltage
AVCC
C6,
C7,
D5
16
18
14
Analog supply voltage
DVSS
A3,
B1,
B2,
C3,
C4
4
5, 8
1, 4
Digital ground reference
AVSS
B7,
C5
15
17
13
Analog ground reference
QFN Pad
NA
NA
NA
Pad
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port 1. The device protection
fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
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NA
QFN package pad; connection to DVSS recommended.
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Development Tools Support
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools.
Hardware Features
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430
Architecture
4-Wire
JTAG
2-Wire
JTAG
Breakpoints
(N)
Range
Breakpoints
Clock
Control
State
Sequencer
Trace
Buffer
LPMx.5
Debugging
Support
MSP430
Yes
Yes
2
No
Yes
No
No
No
Recommended Hardware Options
Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also feature
header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the JTAG
programmer and debugger included. The following table shows the compatible target boards and the supported
packages.
Package
Target Board and Programmer Bundle
Target Board Only
38-pin TSSOP (DA)
MSP-FET430U38
MSP-TS430DA38
Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional
hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools
for details.
Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full
list of available tools at www.ti.com/msp430tools.
Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
Part Number
PC Port
MSP-GANG
Serial and USB
Features
Provider
Program up to eight devices at a time. Works with PC or standalone.
Texas Instruments
Recommended Software Options
Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).
MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices
delivered in a convenient package. MSP430Ware is available as a component of CCS or as a standalone
package.
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Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a
FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to
download binary files (.txt or .hex) files directly to the MSP430 Flash without the need for an IDE.
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you
can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430™ MCU devices and support tools. Each MSP430™ MCU commercial family member has one of three
prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of three
possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
PMS –Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZP) and temperature range (for example, T). Figure 1 provides a legend for reading the complete
device name for any family member.
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Part Number Decoder
MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
430 MCU Platform
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low Power Microcontroller Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel (7 inch)
R = Large Reel (11 inch)
No Markings = Tube or Tray
Optional: Additional Features *-EP = Enhanced Product (-40°C to 105°C)
*-HT = Extreme Temperature Parts (-55°C to 150°C)
Figure 1. Device Nomenclature
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Short-Form Description
CPU
The MSP430™ CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
Instruction Set
General-Purpose Register
R11
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 3 shows examples of the three types of
instruction formats; Table 4 shows the address
modes.
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-toregister operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant generator respectively. The remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
Table 3. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC → (TOS), R8 → PC
JNE
Jump-on-equal bit = 0
Relative jump, unconditional/conditional
Table 4. Address Mode Descriptions
ADDRESS MODE
D
(2)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
M(EDE) → M(TONI)
Absolute
✓
✓
MOV &MEM,&TCDAT
M(MEM) → M(TCDAT)
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2 → R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
(1)
(2)
S
(1)
OPERATION
S = source
D = destination
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Operating Modes
The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation.
An interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 (LPM0)
– CPU is disabled.
– ACLK and SMCLK remain active.
– MCLK is disabled.
• Low-power mode 1 (LPM1)
– CPU is disabled.
– ACLK and SMCLK remain active.
– MCLK is disabled.
– DCO dc-generator is disabled if DCO not used in active mode.
• Low-power mode 2 (LPM2)
– CPU is disabled.
– ACLK remains active.
– MCLK and SMCLK are disabled.
– DCO dc-generator remains enabled.
• Low-power mode 3 (LPM3)
– CPU is disabled.
– ACLK remains active.
– MCLK and SMCLK are disabled.
– DCO dc-generator is disabled.
• Low-power mode 4 (LPM4)
– CPU is disabled.
– ACLK, MCLK, and SMCLK are disabled.
– DCO dc-generator is disabled.
– Crystal oscillator is stopped.
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Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 5. Interrupt Vector Addresses
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (1)
PORIFG
RSTIFG
WDTIFG
KEYV (2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG (2) (3)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
Timer_B3
TBCCR0 CCIFG (4)
maskable
0FFFAh
29
Timer_B3
TBCCR1 and TBCCR2 CCIFGs,
TBIFG (2) (4)
maskable
0FFF8h
28
0FFF6h
27
Watchdog Timer
WDTIFG
maskable
0FFF4h
26
Timer_A3
maskable
0FFF2h
25
Timer_A3
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (2) (4)
maskable
0FFF0h
24
USCI_A0 or USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG (2)
maskable
0FFEEh
23
USCI_A0 or USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG (2)
maskable
0FFECh
22
ADC10
ADC10IFG (4)
maskable
0FFEAh
21
0FFE8h
20
(1)
(2)
(3)
(4)
(5)
(6)
TACCR0 CCIFG
(3)
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(2) (4)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7 (2) (4)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(5)
0FFDEh
15
(6)
0FFDCh to 0FFC0h
14 to 0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
Multiple source flags
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
Interrupt flags are located in the module.
This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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Special Function Registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw
rw-0, 1
rw-(0), (1)
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable 1
Address
7
6
00h
WDTIE
OFIE
NMIIE
ACCVIE
5
4
1
0
ACCVIE
NMIIE
3
2
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
Oscillator fault interrupt enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
Table 7. Interrupt Enable 2
Address
7
6
5
4
01h
UCA0RXIE
UCA0TXIE
UCB0RXIE
UCB0TXIE
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
USCI_A0 receive-interrupt enable
USCI_A0 transmit-interrupt enable
USCI_B0 receive-interrupt enable
USCI_B0 transmit-interrupt enable
Table 8. Interrupt Flag Register 1
Address
7
6
5
02h
WDTIFG
OFIFG
RSTIFG
PORIFG
NMIIFG
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
Power-on reset interrupt flag. Set on VCC power up.
Set via RST/NMI pin
Table 9. Interrupt Flag Register 2
Address
7
6
03h
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
14
5
4
3
2
1
0
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
USCI_A0 receive interrupt flag
USCI_A0 transmit interrupt flag
USCI_B0 receive interrupt flag
USCI_B0 transmit interrupt flag
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Memory Organization
Table 10. Memory Organization
MSP430G2444
MSP430G2544
MSP430G2744
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0FFFFh-0FFC0h
0FFFFh-0E000h
16KB Flash
0FFFFh-0FFC0h
0FFFFh-0C000h
32KB Flash
0FFFFh-0FFC0h
0FFFFh-08000h
Information memory
Size
Flash
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
256 Byte
010FFh-01000h
Boot memory
Size
ROM
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
1KB
0FFFh-0C00h
Size
512 Byte
03FFh-0200h
512 Byte
03FFh-0200h
1KB
05FFh-0200h
16-bit
8-bit
8-bit SFR
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
01FFh-0100h
0FFh-010h
0Fh-00h
RAM
Peripherals
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap
Loader User’s Guide (SLAU319).
Table 11. BSL Function Pins
BSL FUNCTION
DA PACKAGE PINS
RHA PACKAGE PINS
YFF PACKAGE PINS
Data transmit
32 - P1.1
30 - P1.1
G3 - P1.1
Data receive
10 - P2.2
8 - P2.2
A5 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).
Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and
a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low
system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in
less than 1 µs. The basic clock module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal verylow-power LF oscillator.
• Main clock (MCLK), the system clock used by the CPU.
• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
Table 12. DCO Calibration Data
(Provided From Factory in Flash Information Memory Segment A)
DCO FREQUENCY
1 MHz
8 MHz
12 MHz
16 MHz
CALIBRATION REGISTER
SIZE
ADDRESS
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and
power off.
Digital I/O
There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Each I/O has an individually programmable pullup or pulldown resistor.
Watchdog Timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 13. Timer_A3 Signal Connections
INPUT PIN NUMBER
DA
N
RHA
YFF
DEVICE
INPUT
SIGNAL
MODULE
MODULE
MODULE
INPUT
OUTPUT
BLOCK
NAME
SIGNAL
31 - P1.0
33 - P1.0
29 - P1.0
F2 - P1.0
TACLK
TACLK
ACLK
ACLK
Timer
NA
CCR0
TA0
OUTPUT PIN NUMBER
DA
N
RHA
YFF
SMCLK
SMCLK
9 - P2.1
11 - P2.1
7 - P2.1
B4 - P2.1
TAINCLK
INCLK
32 - P1.1
34 - P1.1
30 - P1.1
G2 - P1.1
TA0
CCI0A
32 - P1.1
34 - P1.1
30 - P1.1
G2 - P1.1
10 - P2.2
12 - P2.2
8 - P2.2
A5 - P2.2
TA0
CCI0B
10 - P2.2
12 - P2.2
8 - P2.2
A5 - P2.2
36 - P1.5
38 - P1.5
34 - P1.5
E1 - P1.5
33 - P1.2
35 - P1.2
31 - P1.2
E2 - P1.2
VSS
GND
VCC
VCC
33 - P1.2
35 - P1.2
31 - P1.2
E2 - P1.2
TA1
CCI1A
29 - P2.3
31 - P2.3
27 - P2.3
F3 - P2.3
TA1
CCI1B
29 - P2.3
31 - P2.3
27 - P2.3
F3 - P2.3
VSS
GND
37 - P1.6
39 - P1.6
35 - P1.6
E3 - P1.6
VCC
VCC
34 - P1.3
36 - P1.3
32 - P1.3
G1 - P1.3
34 - P1.3
36 - P1.3
32 - P1.3
G1 - P1.3
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CCR1
CCR2
TA1
TA2
CCI2A
ACLK
(internal)
TA2
CCI2B
30 - P2.4
32 - P2.4
28 - P2.4
G3 - P2.4
VSS
GND
38 - P1.7
40 - P1.7
36 - P1.7
D2 - P1.7
VCC
VCC
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Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 14. Timer_B3 Signal Connections
INPUT PIN NUMBER
DA
N
RHA
YFF
DEVICE
INPUT
SIGNAL
MODULE
MODULE
MODULE
INPUT
OUTPUT
BLOCK
NAME
SIGNAL
24 - P4.7
26 - P4.7
22 - P4.7
F5 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
24 - P4.7
26 - P4.7
22 - P4.7
F5 - P4.7
TBCLK
INCLK
17 - P4.0
19 - P4.0
15 - P4.0
D6 - P4.0
TB0
CCI0A
20 - P4.3
22 - P4.3
18 - P4.3
E7 - P4.3
TB0
CCI0B
VSS
GND
VCC
VCC
18 - P4.1
21 - P4.1
16 - P4.1
D7 - P4.1
TB1
CCI1A
21 - P4.4
23 - P4.4
19 - P4.4
F7 - P4.4
TB1
CCI1B
VSS
GND
VCC
VCC
19 - P4.2
21 - P4.2
17 - P4.2
E6 - P4.2
TB2
CCI2A
ACLK
(internal)
CCI2B
VSS
GND
VCC
VCC
Timer
NA
CCR0
TB0
CCR1
CCR2
TB1
TB2
OUTPUT PIN NUMBER
DA
N
RHA
YFF
17 - P4.0
19 - P4.0
15 - P4.0
D6 - P4.0
20 - P4.3
22 - P4.3
18 - P4.3
E7 - P4.3
18 - P4.1
20 - P4.1
16 - P4.1
D7 - P4.1
21 - P4.4
23 - P4.4
19 - P4.4
F7 - P4.4
19 - P4.2
21 - P4.2
17 - P4.2
E6 - P4.2
22 - P4.5
24 - P4.5
20 - P4.5
F6 - P4.5
Universal Serial Communications Interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART,
enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling allowing ADC samples to be converted and stored without any CPU intervention.
18
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Peripheral File Map
Table 15. Peripherals With Word Access
MODULE
ADC10
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
ADC10SA
1BCh
ADC memory
ADC10MEM
1B4h
ADC control register 1
ADC10CTL1
1B2h
ADC control register 0
ADC10CTL0
1B0h
ADC analog enable 0
ADC10AE0
04Ah
ADC data transfer start address
ADC analog enable 1
Timer_B
ADC10AE1
04Bh
ADC data transfer control register 1
ADC10DTC1
049h
ADC data transfer control register 0
ADC10DTC0
048h
Capture/compare register
TBCCR2
0196h
Capture/compare register
TBCCR1
0194h
Capture/compare register
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control
TBCCTL2
0186h
Capture/compare control
TBCCTL1
0184h
Capture/compare control
TBCCTL0
0182h
Timer_B control
Timer_A
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register
TACCR2
0176h
Capture/compare register
TACCR1
0174h
Capture/compare register
TACCR0
0172h
TAR
0170h
Capture/compare control
TACCTL2
0166h
Capture/compare control
TACCTL1
0164h
Capture/compare control
TACCTL0
0162h
TACTL
0160h
Timer_A register
Timer_A control
Timer_A interrupt vector
Flash Memory
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
FCTL1
0128h
WDTCTL
0120h
Flash control 1
Watchdog Timer+
Watchdog/timer control
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Table 16. Peripherals With Byte Access
MODULE
REGISTER NAME
USCI_B0
SHORT NAME
ADDRESS
OFFSET
USCI_B0 transmit buffer
UCB0TXBUF
06Fh
USCI_B0 receive buffer
UCB0RXBUF
06Eh
UCB0STAT
06Dh
UCB0BR1
06Bh
USCI_B0 bit rate control 0
UCB0BR0
06Ah
USCI_B0 control 1
UCB0CTL1
069h
USCI_B0 control 0
UCB0CTL0
068h
USCI_B0 I2C slave address
UCB0SA
011Ah
USCI_B0 I2C own address
UCB0OA
0118h
USCI_A0 transmit buffer
UCA0TXBUF
067h
USCI_A0 receive buffer
UCA0RXBUF
066h
USCI_A0 status
UCA0STAT
065h
USCI_A0 modulation control
UCA0MCTL
064h
USCI_A0 baud rate control 1
UCA0BR1
063h
USCI_A0 baud rate control 0
UCA0BR0
062h
USCI_A0 control 1
UCA0CTL1
061h
USCI_A0 control 0
UCA0CTL0
060h
USCI_B0 status
USCI_B0 bit rate control 1
USCI_A0
Basic Clock System+
Port P4
USCI_A0 IrDA receive control
UCA0IRRCTL
05Fh
USCI_A0 IrDA transmit control
UCA0IRTCTL
05Eh
USCI_A0 auto baud rate control
UCA0ABCTL
05Dh
Basic clock system control 3
BCSCTL3
053h
Basic clock system control 2
BCSCTL2
058h
Basic clock system control 1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P4 resistor enable
P4REN
011h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
P4IN
01Ch
Port P4 input
Port P3
Port P3 resistor enable
P3REN
010h
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
P3IN
018h
Port P3 input
Port P2
Port P2 resistor enable
P2REN
02Fh
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
Port P2 interrupt edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
P2IN
028h
Port P2 interrupt enable
Port P2 input
20
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Table 16. Peripherals With Byte Access (continued)
MODULE
Port P1
REGISTER NAME
SHORT NAME
ADDRESS
OFFSET
Port P1 resistor enable
P1REN
027h
Port P1 selection
P1SEL
026h
P1IE
025h
Port P1 interrupt edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
Port P1 interrupt enable
Special Function
P1OUT
021h
Port P1 input
P1IN
020h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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Absolute Maximum Ratings (1)
Voltage applied at VCC to VSS
Voltage applied to any pin
-0.3 V to 4.1 V
(2)
-0.3 V to VCC + 0.3 V
Diode current at any device terminal
Storage temperature, Tstg
(1)
±2 mA
(3)
Unprogrammed device
-55°C to 150°C
Programmed device
-55°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TEST pin when blowing the JTAG fuse.
Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
(2)
(3)
Recommended Operating Conditions (1) (2)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
VCC
Supply voltage
AVCC = DVCC = VCC
VSS
Supply voltage
AVSS = DVSS = VSS
TA
Operating free-air temperature
Processor frequency
(maximum MCLK frequency) (1) (2)
(see Figure 2)
fSYSTEM
(1)
(2)
NOM
MAX
UNIT
During program execution
1.8
3.6
V
During program and erase of
flash memory
2.2
3.6
V
0
V
-40
85
VCC = 1.8 V, Duty cycle = 50% ±10%
dc
4.15
VCC = 2.7 V, Duty cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V, Duty cycle = 50% ±10%
dc
16
°C
MHz
The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the
specified maximum frequency.
Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend :
System Frequency – MHz
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V 3.6 V
Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC
of 2.2 V.
Figure 2. Operating Area
22
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Active Mode Supply Current (into DVCC + AVCC) Excluding External Current (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IAM,1MHz
(1)
(2)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1 MHz,
fACLK = 32768 Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
Active mode (AM)
current (1 MHz)
VCC
MIN
TYP
2.2 V
270
3V
390
MAX
UNIT
µA
550
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Typical Characteristics - Active-Mode Supply Current (Into DVCC + AVCC)
ACTIVE-MODE CURRENT
vs
SUPPLY VOLTAGE
TA = 25°C
ACTIVE-MODE CURRENT
vs
DCO FREQUENCY
8.0
5.0
f DCO = 16 MHz
7.0
TA = 85 °C
6.0
Active Mode Current − mA
Active Mode Current − mA
4.0
f DCO = 12 MHz
5.0
4.0
f DCO = 8 MHz
3.0
2.0
TA = 25 °C
3.0
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
1.0
0.0
1.5
VCC = 2.2 V
f DCO = 1 MHz
2.0
2.5
3.0
3.5
VCC − Supply Voltage − V
Figure 3.
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4.0
0.0
0.0
4.0
8.0
12.0
16.0
f DCO − DCO Frequency − MHz
Figure 4.
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Low-Power-Mode Supply Currents (Into VCC ) Excluding External Current (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TA
VCC
Low-power mode 0
(LPM0) current (3)
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 0, OSCOFF = 0
25°C
ILPM2
Low-power mode 2
(LPM2) current (4)
fMCLK = fSMCLK = 0 MHz,
fDCO = 1 MHz,
fACLK = 32768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0,
SCG1 = 1, OSCOFF = 0
ILPM3,LFXT1
Low-power mode 3
(LPM3) current (4)
ILPM3,VLO
ILPM4
ILPM0,1MHz
(1)
(2)
(3)
(4)
(5)
24
TEST CONDITIONS
TYP
MAX
2.2 V
75
90
25°C
2.2 V
22
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 32768 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
25°C
2.2 V
1
2
µA
Low-power mode 3
current, (LPM3) (4)
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from internal LF oscillator
(VLO),
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 0
25°C
2.2 V
0.5
1
µA
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1,
SCG1 = 1, OSCOFF = 1
0.1
0.5
Low-power mode 4
(LPM4) current (5)
1.5
3
25°C
85°C
2.2 V
MIN
UNIT
µA
µA
µA
All inputs are tied to 0 V or VCC . Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance is chosen to closely match the required 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
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Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ - VIT- )
VCC
MIN
RPull
Pullup or pulldown resistor
CI
Input capacitance
VIN = VSS or VCC
MAX
0.45 VCC
0.75 VCC
1.35
2.25
3V
For pullup: VIN = VSS,
For pulldown: VIN = VCC
TYP
UNIT
V
0.25 VCC
0.55 VCC
3V
0.75
1.65
3V
0.3
1
V
3V
20
50
kΩ
35
V
5
pF
Leakage Current, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
TEST CONDITIONS
High-impedance leakage current
(1) (2)
VCC
MIN
TYP
3V
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
Outputs, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
VOH
High-level output voltage
IOH(max) = -6 mA
VOL
Low-level output voltage
IOL(max) = 6 mA (1)
(1)
VCC
MIN
TYP
MAX
UNIT
3V
VCC - 0.3
V
3V
VSS + 0.3
V
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop
specified.
Output Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fPx.y
Port output frequency (with load)
Px.y, CL = 20 pF,
RL = 1 kΩ against VCC/2 (1) (2)
fPort_CLK
Clock output frequency
Px.y, CL = 20 pF (2)
(1)
(2)
VCC
MIN
TYP
MAX
UNIT
3V
12
MHz
3V
16
MHz
Alternatively, a resistive divider with two 2-kΩ resistors between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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Typical Characteristics - Outputs
One output loaded at a time.
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
VCC = 2.2 V
P4.5
TA = 25°C
20.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P4.5
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
VOL − Low-Level Output V oltage − V
Figure 5.
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
1.5
2.0
2.5
3.0
3.5
0.0
VCC = 2.2 V
P4.5
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
VOH − High-Level Output Voltage − V
Figure 7.
26
1.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
−25.0
0.0
0.5
VOL − Low-Level Output V oltage − V
Figure 6.
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−20.0
TA = 25°C
40.0
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2.5
VCC = 3 V
P4.5
−10.0
−20.0
−30.0
−40.0
−50.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 8.
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POR and BOR (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
See Figure 9
dVCC /dt ≤ 3 V/s
0.7 ×
V(B_IT-)
V(B_IT-)
See Figure 9 through Figure 11
dVCC /dt ≤ 3 V/s
1.35
V
Vhys(B_IT-)
See Figure 9
dVCC /dt ≤ 3 V/s
140
mV
td(BOR)
See Figure 9
2000
µs
t(reset)
Pulse duration needed at RST/NMI pin to
accepted reset internally
(1)
(2)
2.2 V
2
V
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) +
Vhys(B_IT-) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-) . The default DCO settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 9. POR and BOR vs Supply Voltage
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Typical Characteristics - POR and BOR
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
1 ns
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR or BOR Signal
VCC
2
t pw
3V
VCC(drop) − V
VCC = 3 V
1.5
Typical Conditions
1
VCC(drop)
0.5
0
0.001
t f = tr
1
1000
tf
tr
t pw − Pulse Width − µs
t pw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
28
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DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
Supply voltage range
VCC
MIN
TYP
MAX
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
RSELx = 15
3.0
3.6
UNIT
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
3V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
3V
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
3V
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
3V
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
3V
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
3V
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
3V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
3V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
3V
1.6
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
3V
2.3
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
3V
3.4
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
3V
4.25
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
3V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
3V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
3V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO) /fDCO(RSEL,DCO)
3V
1.35
ratio
SDCO
Frequency step between tap
DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1) /fDCO(RSEL,DCO)
3V
1.08
ratio
Duty cycle
Measured at SMCLK
3V
50
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Calibrated DCO Frequencies, Tolerance
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
1-MHz tolerance over VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
30°C
1.8 V to 3.6 V
-3
±2
+3
%
1-MHz tolerance overall
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
1.8 V to 3.6 V
-6
±3
+6
%
8-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
8-MHz tolerance over VCC
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
30°C
2.2 V to 3.6 V
-3
±2
+3
%
8-MHz tolerance overall
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.2 V to 3.6 V
-6
±3
+6
%
12-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
12-MHz tolerance over VCC
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
30°C
2.7 V to 3.6 V
-3
±2
+3
%
12-MHz tolerance overall
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
2.7 V to 3.6 V
-6
±3
+6
%
16-MHz tolerance over
temperature (1)
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
0°C to 85°C
3V
-3
±0.5
+3
%
16-MHz tolerance over VCC
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
30°C
3.3 V to 3.6 V
-3
±2
+3
%
16-MHz tolerance overall
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
calibrated at 30°C and 3 V
-40°C to 85°C
3.3 V to 3.6 V
-6
±3
+6
%
(1)
30
This is the frequency change from the measured frequency at 30°C over temperature.
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Wake-Up From Lower-Power Modes (LPM3, LPM4)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tDCO,LPM3/4
DCO clock wake-up time
from LPM3 or LPM4 (1)
tCPU,LPM3/4
CPU wake-up time from
LPM3 or LPM4 (2)
(1)
(2)
VCC
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
MIN
3V
TYP
MAX
1.5
UNIT
µs
1 / fMCLK +
tClock,LPM3/4
The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, a port interrupt) to the first clock
edge observable externally on a clock pin (MCLK or SMCLK).
Parameter applicable only if DCOCLK is used for MCLK.
Typical Characteristics - DCO Clock Wake-Up Time From LPM3 or LPM4
CLOCK WAKE-UP TIME FROM LPM3
vs
DCO FREQUENCY
DCO Wake-Up Time − µs
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 12.
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DCO With External Resistor ROSC (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fDCO,ROSC
DCO output frequency with ROSC
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0,
TA = 25°C
DT
Temperature drift
DV
Drift with VCC
(1)
VCC
MIN
TYP
MAX
UNIT
2.2 V
1.8
3V
1.95
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
±0.1
%/°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V, 3 V
10
%/V
MHz
ROSC = 100 kΩ. Metal film resistor, type 0257, 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
Typical Characteristics - DCO With External Resistor ROSC
DCO FREQUENCY
vs
ROSC
VCC = 2.2 V, TA = 25°C
10.00
DCO Frequency − MHz
DCO Frequency − MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
100.00
1000.00
DCO FREQUENCY
vs
TEMPERATURE
VCC = 3 V
DCO FREQUENCY
vs
SUPPLY VOLTAGE
TA = 25°C
2.50
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
DCO Frequency − MHz
2.25
ROSC = 100k
2.00
DCO Frequency − MHz
RSELx = 4
ROSC − External Resistor − kW
Figure 14.
2.25
10000.00
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
ROSC = 1M
0.25
−25.0
0.0
25.0
50.0
TA − Temperature − °C
Figure 15.
32
0.10
ROSC − External Resistor − kW
Figure 13.
2.50
0.00
−50.0
1.00
0.01
10.00
10000.00
DCO FREQUENCY
vs
ROSC
VCC = 3 V, TA = 25°C
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75.0
ROSC = 1M
0.25
100.0
0.00
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 16.
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Crystal Oscillator LFXT1, Low-Frequency Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
OALF
Oscillation allowance for
LF crystals
CL,eff
fFault,LF
(1)
(2)
(3)
(4)
Integrated effective load
capacitance, LF mode (2)
XTS = 0, LFXT1Sx = 0 or 1
VCC
MIN
TYP
1.8 V to 3.6 V
1.8 V to 3.6 V
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32768 Hz, CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
kΩ
XTS = 0, XCAPx = 0
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle, LF mode
XTS = 0, Measured at P2.0/ACLK,
fLFXT1,LF = 32768 Hz
2.2 V
30
Oscillator fault frequency,
LF mode (3)
XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4)
2.2 V
10
50
pF
70
%
10000
Hz
To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift
dfVLO/dVCC
VLO frequency supply voltage drift
(1)
(2)
(1)
(2)
TA
VCC
MIN
TYP
MAX
-40°C to 85°C
3V
4
12
20
-40°C to 85°C
3V
25°C
1.8 V to 3.6 V
UNIT
kHz
0.5
%/°C
4
%/V
Calculated using the box method:
I version: [MAX(-40...85°C) - MIN(-40...85°C)]/MIN(-40...85°C)/[85°C - (-40°C)]
Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
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Crystal Oscillator LFXT1, High-Frequency Mode (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
XTS = 1, LFXT1Sx = 0
1.8 V to 3.6 V
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1
LFXT1 oscillator crystal frequency,
HF mode 2
XTS = 1, LFXT1Sx = 2
fLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
fLFXT1,HF1
fLFXT1,HF2
MAX
UNIT
0.4
1
MHz
1.8 V to 3.6 V
1
4
MHz
1.8 V to 3.6 V
2
10
2.2 V to 3.6 V
2
12
3 V to 3.6 V
fLFXT1,HF,logic
OAHF
CL,eff
LFXT1 oscillator logic-level squarewave input frequency, HF mode
Oscillation allowance for HF crystals
(see Figure 17 and Figure 18)
Integrated effective load capacitance,
HF mode (2)
Duty cycle, HF mode
fFault,HF
(1)
(2)
(3)
(4)
(5)
34
Oscillator fault frequency (4)
XTS = 1, LFXT1Sx = 3
TYP
2
16
1.8 V to 3.6 V
0.4
10
2.2 V to 3.6 V
0.4
12
3 V to 3.6 V
0.4
16
XTS = 1, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
2700
XTS = 1, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
800
XTS = 1, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
300
XTS = 1 (3)
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
XTS = 1,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
XTS = 1, LFXT1Sx = 3 (5)
50
pF
60
2.2 V
%
40
2.2 V
MHz
Ω
1
40
MHz
30
50
60
300
kHz
To improve EMI on the XT1 oscillator the following guidelines should be observed:
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, it is
recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should
always match the specification of the used crystal.
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
Measured with logic-level input frequency, but also applies to operation with crystals.
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Typical Characteristics - LFXT1 Oscillator in HF Mode (XTS = 1)
OSCILLATION ALLOWANCE
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
100000.00
800.0
OSCILLATOR SUPPLY CURRENT
vs
CRYSTAL FREQUENCY
CL,eff = 15 pF, TA = 25°C
LFXT1Sx = 3
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 1
LFXT1Sx = 2
XT Oscillator Supply Current − uA
Oscillation Allowance − Ohms
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
0.0
0.0
4.0
Crystal Frequency − MHz
Figure 17.
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 18.
Timer_A, Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
SMCLK, Duty cycle = 50% ± 10%
tTA,cap
Timer_A capture timing
TAx, TBx
VCC
MIN
TYP
MAX
fSYSTEM
3V
UNIT
MHz
20
ns
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baud rate in MBaud)
3V
2
tτ
UART receive deglitch time (1)
3V
50
(1)
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
MHz
100
600
ns
The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
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USCI (SPI Master Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 19 and Figure 20)
PARAMETER
TEST CONDITIONS
VCC
MIN
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
3V
75
tHD,MI
SOMI input data hold time
3V
0
tVALID,MO
SIMO output data valid time
(1)
SMCLK, duty cycle = 50% ± 10%
UCLK edge to SIMO valid,CL = 20 pF
3V
TYP
MAX
UNIT
fSYSTEM
MHz
ns
ns
20
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 19. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 1
36
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
USCI (SPI Slave Mode) (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Figure 21 and Figure 22)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
STE lead time, STE low to clock
3V
tSTE,LAG
STE lag time, Last clock to STE high
3V
tSTE,ACC
STE access time, STE low to SOMI data out
3V
50
ns
tSTE,DIS
STE disable time, STE high to SOMI high
impedance
3V
50
ns
tSU,SI
SIMO input data setup time
3V
15
ns
tHD,SI
SIMO input data hold time
3V
10
ns
tVALID,SO
(1)
UCLK edge to SOMI valid,
CL = 20 pF
SOMI output data valid time
50
UNIT
tSTE,LEAD
ns
10
3V
ns
50
75
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 21. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 22. SPI Slave Mode, CKPH = 1
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USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3V
0
tSU,DAT
Data setup time
3V
250
ns
tSU,STO
Setup time for STOP
3V
4
µs
tSP
Pulse duration of spikes suppressed by
input filter
3V
50
3V
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
0
4
3V
µs
0.6
4.7
3V
µs
0.6
ns
100
600
ns
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 23. I2C Mode Timing
38
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
10-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
TEST CONDITIONS
TA
VCC
MIN
Analog supply voltage range VSS = 0 V
All Ax terminals,
Analog inputs selected in
ADC10AE register
Analog input voltage
range (2)
VAx
IADC10
IREF+
ADC10 supply current
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0,
ADC10SHT0 = 1,
ADC10SHT1 = 0,
ADC10DIV = 0
(3)
Reference supply current,
reference buffer disabled (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
3V
25°C
3V
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
0.6
mA
0.25
25°C
3V
mA
0.25
IREFB,0
Reference buffer supply
current with
ADC10SR = 0 (4)
fADC10CLK = 5 MHz
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 0
25°C
3V
1.1
mA
IREFB,1
Reference buffer supply
current with
ADC10SR = 1 (4)
fADC10CLK = 5 MHz,
ADC10ON = 0, REFON = 1,
REF2_5V = 0, REFOUT = 1,
ADC10SR = 1
25°C
3V
0.5
mA
CI
Input capacitance
Only one terminal Ax selected at
a time
25°C
3V
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VCC
25°C
3V
(1)
(2)
(3)
(4)
27
1000
pF
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
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10-Bit ADC, Built-In Voltage Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
VCC,REF+
Positive built-in reference
analog supply voltage range
IVREF+ ≤ 1 mA, REF2_5V = 0
2.2
IVREF+ ≤ 1 mA, REF2_5V = 1
2.9
VREF+
Positive built-in reference
voltage
IVREF+ ≤ IVREF+max, REF2_5V = 0
3V
1.41
1.5
1.59
IVREF+ ≤ IVREF+max, REF2_5V = 1
3V
2.35
2.5
2.65
ILD,VREF+
Maximum VREF+ load
current
UNIT
V
V
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
3V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
±2
VREF+ load regulation
response time
IVREF+ = 100 µA to 900 µA,
VAx ≈ 0.5 x VREF+,
Error of conversion result ≤1 LSB,
ADC10SR = 0
3V
400
ns
CVREF+
Maximum capacitance at pin
VREF+
IVREF+ ≤ ±1 mA,
REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient (1)
IVREF+ = constant with
0 mA ≤ IVREF+ ≤ 1 mA
3V
±100
ppm/°C
tREFON
Settling time of internal
reference voltage
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 to 1
3.6 V
30
µs
tREFBURST
Settling time of reference
buffer to 99.9% VREF
IVREF+ = 0.5 mA,
REF2_5V = 1,
REFON = 1,
REFBURST = 1, ADC10SR = 0
3V
2
µs
VREF+ load regulation
(1)
40
mA
LSB
Calculated using the box method:
I temperature: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C))
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10-Bit ADC, External Reference (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
TEST CONDITIONS
Positive external reference input
voltage range (2)
1.4
3
0
1.2
V
1.4
VCC
V
Differential external reference input
voltage range
ΔVeREF = VeREF+ - VeREF-
VeREF+ > VeREF- (5)
(1)
(2)
(3)
(4)
(5)
UNIT
VeREF- ≤ VeREF+ ≤ VCC - 0.15 V,
SREF1 = 1, SREF0 = 1 (3)
ΔVeREF
Static input current into VeREF-
MAX
VCC
VeREF+ > VeREF-
IVeREF-
TYP
1.4
Negative external reference input
voltage range (4)
Static input current into VeREF+
MIN
VeREF+ > VeREF-,
SREF1 = 1, SREF0 = 0
VeREF-
IVeREF+
VCC
V
0 V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
3V
±1
0 V ≤ VeREF+ ≤ VCC - 0.15 V ≤ 3 V,
SREF1 = 1, SREF0 = 1 (3)
3V
0
0 V ≤ VeREF- ≤ VCC
3V
±1
µA
µA
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
Under this condition, the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply
current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
10-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC10SR = 0
fADC10CLK
ADC10 input clock
frequency
For specified performance of
ADC10 linearity parameters
fADC10OSC
ADC10 built-in oscillator
frequency
ADC10DIVx = 0, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
ADC10 built-in oscillator, ADC10SSELx = 0,
fADC10CLK = fADC10OSC
tCONVERT
Conversion time
tADC10ON
Turn on settling time of
the ADC (1)
(1)
ADC10SR = 1
VCC
MIN
TYP
MAX
0.45
6.3
0.45
1.5
2.2 V, 3 V
3.7
6.3
2.2 V, 3 V
2.06
3.51
2.2 V, 3 V
fADC10CLK from ACLK, MCLK or SMCLK,
ADC10SSELx ≠ 0
13 × ADC10DIVx ×
1 / fADC10CLK
100
UNIT
MHz
MHz
µs
ns
The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already
settled.
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10-Bit ADC, Linearity Parameters (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
SREFx = 010
3V
±1
LSB
ED
Differential linearity error
SREFx = 010
3V
±1
LSB
EO
Offset error
Source impedance RS < 100 Ω, SREFx = 010
3V
±1
LSB
EG
Gain error
SREFx = 010
3V
±1.1
±2
LSB
ET
Total unadjusted error
SREFx = 010
3V
±2
±6
LSB
TYP
MAX
UNIT
(1)
Using the integrated reference buffer (SREFx = 010) increases the gain, and offset and total unadjusted error.
10-Bit ADC, Temperature Sensor and Built-In VMID
(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISENSOR
TEST CONDITIONS
Temperature sensor supply
current (1)
TCSENSOR
VCC
3V
60
ADC10ON = 1, INCHx = 0Ah (2)
3V
3.55
tSENSOR(sample)
Sample time required if
channel 10 is selected (3)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
3V
IVMID
Current into divider at
channel 11
ADC10ON = 1, INCHx = 0Bh
3V
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID ≈ 0.5 × VCC
3V
tVMID(sample)
Sample time required if
channel 11 is selected (4)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
3V
(1)
(2)
(3)
(4)
42
MIN
REFON = 0, INCHx = 0Ah,
TA = 25°C
µA
mV/°C
30
µs
(3)
1.5
1220
µA
V
ns
The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal is
high).When REFON = 1, ISENSOR is included in IREF+.When REFON = 0, ISENSOR applies during conversion of the temperature sensor
input (INCH = 0Ah).
The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
No additional current is needed. The VMID is used during sampling.
The on time, tVMID(on), is included in the sampling time, tVMID(sample); no additional on time is needed.
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Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC (PGM/ERASE)
Program and erase supply voltage
2.2
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from VCC during program
2.2 V, 3.6 V
1
5
mA
IERASE
Supply current from VCC during erase
2.2 V, 3.6 V
1
7
mA
tCPT
Cumulative program time (1)
2.2 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
2.2 V, 3.6 V
20
ms
4
Program and erase endurance
5
10
10
cycles
tRetention
Data retention duration
TJ = 25°C
tWord
Word or byte program time
(2)
30
tFTG
tBlock,
Block program time for first byte or word
(2)
25
tFTG
tBlock, 1-63
Block program time for each additional byte or
word
(2)
18
tFTG
tBlock,
Block program end-sequence wait time
(2)
6
tFTG
tMass Erase
Mass erase time
(2)
10593
tFTG
tSeg
Segment erase time
(2)
4819
tFTG
(1)
(2)
0
End
Erase
100
years
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word write, individual byte write, and block write modes.
These values are hardwired into the flash controller's state machine (tFTG = 1/fFTG).
RAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
V(RAMh)
(1)
RAM retention supply voltage
(1)
TEST CONDITIONS
CPU halted
MIN
MAX
UNIT
1.6
V
This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
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JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V
0.025
15
µs
tSBW,En
Spy-Bi-Wire enable time
(TEST high to acceptance of first clock edge (1))
2.2 V
1
µs
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V
15
100
fTCK
TCK input frequency (2)
2.2 V
0
5
MHz
RInternal
Internal pulldown resistance on TEST
2.2 V
25
90
kΩ
(1)
(2)
60
µs
Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
(1)
44
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to
bypass mode.
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PORT SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.0/TACLK/ADC10CLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Table 17. Port P1 (P1.0 to P1.3) Pin Functions
PIN NAME (P1.x)
x
CONTROL BITS/SIGNALS
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
ADC10CLK
1
1
P1.1 (1) (I/O)
I: 0; O: 1
0
0
1
P1.0 (1)
P1.0/TACLK/ADC10CLK
P1.1/TA0
0
1
Timer_A3.TACLK
Timer_A3.CCI0A
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI1A
0
1
Timer_A3.TA1
1
1
P1.2 (1) (I/O)
P1.2/TA1
2
P1.3
P1.3/TA2
(1)
3
(1)
I: 0; O: 1
0
Timer_A3.CCI2A
(I/O)
0
1
Timer_A3.TA2
1
1
Default after reset (PUC, POR)
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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access
Features
Pad Logic
P1REN.x
P1DIR.x
0
P1OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
To JTAG
From JTAG
Table 18. Port P1 (P1.4 to P1.6) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.4 (2) (I/O)
P1.4/SMCLK/TCK
4
SMCLK
TCK
P1.5 (2) (I/O)
P1.5/TA0/TMS
5
Timer_A3.TA0
TMS
(1)
(2)
(3)
46
6
P1DIR.x
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer_A3.TA1
1
1
0
TDI/TCLK (3)
X
X
1
P1.6 (2) (I/O)
P1.6/TA1/TDI/TCLK
CONTROL BITS/SIGNALS (1)
X = Don't care
Default after reset (PUC, POR)
Function controlled by JTAG
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Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features
Pad Logic
P1REN.7
P1DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P1OUT.7
DVSS
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.7
EN
P1IN.7
EN
Module X IN
D
P1IE.7
P1IRQ.7
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1SEL.7
P1IES.7
To JTAG
From JTAG
From JTAG
From JTAG (TDO)
Table 19. Port P1 (P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.7
P1.7/TA2/TDO/TDI
(1)
(2)
(3)
7
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P1DIR.x
P1SEL.x
4-Wire JTAG
I: 0; O: 1
0
0
Timer_A3.TA2
1
1
0
TDO/TDI (3)
X
X
1
X = Don't care
Default after reset (PUC, POR)
Function controlled by JTAG
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Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
P2.0/ACLK/A0
P2.2/TA0/A2
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
EN
P2IRQ.x
Q
Set
P2IFG.x
Interrupt
Edge
Select
P2SEL.x
P2IES.x
Table 20. Port P2 (P2.0, P2.2) Pin Functions
Pin Name (P2.x)
x
y
FUNCTION
P2.0
P2.0/ACLK/A0
0
0
2
2
48
ADC10AE0.y
0
0
1
1
0
A0 (3)
X
X
1
I: 0; O: 1
0
0
Timer_A3.CCI0B
0
1
0
Timer_A3.TA0
1
1
0
X
X
1
A2
(1)
(2)
(3)
P2SEL.x
I: 0; O: 1
(2)
(I/O)
P2DIR.x
ACLK
P2.2
P2.2/TA0/A2
(2)
CONTROL BITS/SIGNALS (1)
(3)
(I/O)
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 1
ADC10AE0.1
P2REN.1
P2DIR.1
0
P2OUT.1
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P2.1/TAINCLK/SMCLK/A1
Bus
Keeper
P2SEL.1
EN
P2IN.1
EN
Module X IN
D
P2IE.1
EN
P2IRQ.1
Q
Set
P2IFG.1
Interrupt
Edge
Select
P2SEL.1
P2IES.1
Table 21. Port P2 (P2.1) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.1
P2.1/TAINCLK/
SMCLK/A1
1
1
(I/O)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.INCLK
0
1
0
SMCLK
1
1
0
(3)
X
X
1
A1
(1)
(2)
(3)
(2)
CONTROL BITS/SIGNALS (1)
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger
SREF2
VSS
0
To ADC 10 VR−
Pad Logic
1
To ADC 10
INCHx = 3
ADC10AE0.3
P2REN.3
P2DIR.3
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.3
DVSS
DVCC
P2.3/TA1/
A3/VREF−/VeREF−
Bus
Keeper
P2SEL.3
EN
P2IN.3
EN
Module X IN
D
P2IE.3
P2IRQ.3
EN
Q
P2IFG.3
P2SEL.3
P2IES.3
Set
Interrupt
Edge
Select
Table 22. Port P2 (P2.3) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.CCI1B
0
1
0
Timer_A3.TA1
1
1
0
A3/VREF-/VeREF- (3)
X
X
1
P2.3 (2) (I/O)
P2.3/TA1/A3/ VREF/VeREF-
(1)
(2)
(3)
50
3
3
CONTROL BITS/SIGNALS (1)
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger
Pad Logic
To /from ADC10
positive reference
To ADC 10
INCHx = 4
ADC10AE0.4
P2REN.4
P2DIR.4
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.4
DVSS
P2.4/TA2/
A4/VREF+/VeREF
Bus
Keeper
P2SEL.4
EN
P2IN.4
EN
Module X IN
D
P2IE.4
EN
P2IRQ.4
Q
Set
P2IFG.4
Interrupt
Edge
Select
P2SEL.4
P2IES.4
Table 23. Port P2 (P2.4) Pin Functions
PIN NAME (P2.x)
x
y
FUNCTION
P2.4
P2.4/TA2/A4/
VREF+/VeREF+
(1)
(2)
(3)
4
4
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
Timer_A3.TA2
1
1
0
A4/VREF+/VeREF+ (3)
X
X
1
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External ROSC for DCO
Pad Logic
To DCO
DCOR
P2REN.x
P2DIR.x
0
P2OUT.x
0
1
0
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
DVCC
P2.5/ROSC
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Table 24. Port P2 (P2.5) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.5
P2.5/ROSC
5
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P2DIR.x
P2SEL.x
DCOR
I: 0; O: 1
0
0
N/A (3)
0
1
0
DVSS
1
1
0
ROSC
X
X
1
(1)
(2)
(3)
X = Don't care
Default after reset (PUC, POR)
N/A = Not available or not applicable
52
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
P2.7/XOUT
LFXT1 off
0
LFXT1CLK
1
Pad Logic
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
DVCC
P2.6/XIN
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge
Select
Table 25. Port P2 (P2.6) Pin Functions
PIN NAME (P2.x)
P2.6/XIN
(1)
(2)
x
6
CONTROL BITS/SIGNALS (1)
FUNCTION
P2DIR.x
P2SEL.x
P2.6 (I/O)
I: 0; O: 1
0
(2)
X
1
XIN
X = Don't care
Default after reset (PUC, POR)
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Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output
BCSCTL3.LFXT1Sx = 11
LFXT1 Oscillator
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
P2.6/XIN
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
DVCC
P2.7/XOUT
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
P2SEL.7
P2IES.7
Set
Interrupt
Edge
Select
Table 26. Port P2 (P2.7) Pin Functions
PIN NAME (P2.x)
XOUT/P2.7
(1)
(2)
(3)
54
x
7
CONTROL BITS/SIGNALS (1)
FUNCTION
P2.7 (I/O)
XOUT
(2) (3)
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC, POR)
If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this
pin after reset.
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 5
ADC10AE0.5
P3REN.0
P3DIR.0
USCI Direction
Control
0
P3OUT.0
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK/A5
Bus
Keeper
P3SEL.0
EN
P3IN.0
EN
Module X IN
D
Table 27. Port P3 (P3.0) Pin Functions
PIN NAME (P1.x)
x
y
FUNCTION
P3.0
P3.0/UCB0STE/
UCA0CLK/A5
(1)
(2)
(3)
(4)
(5)
0
5
(2)
(I/O)
UCB0STE/UCA0CLK (3)
A5 (5)
(4)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
X
1
0
X
X
1
X = Don't care
Default after reset (PUC, POR)
The pin direction is controlled by the USCI module.
UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI_B0 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P3REN.x
P3DIR.x
USCI Direction
Control
0
P3OUT.x
0
Module X OUT
1
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Table 28. Port P3 (P3.1 to P3.5) Pin Functions
PIN NAME (P3.x)
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
(1)
(2)
(3)
(4)
56
x
1
2
3
4
5
CONTROL BITS/SIGNALS (1)
FUNCTION
P3.1 (2) (I/O)
UCB0SIMO/UCB0SDA
(3)
P3.2 (2) (I/O)
UCB0SOMI/UCB0SCL (3)
P3.3 (2) (I/O)
UCB0CLK/UCA0STE
(3) (4)
P3.4 (2) (I/O)
UCA0TXD/UCA0SIMO (3)
P3.5
(2)
(I/O)
UCA0RXD/UCA0SOMI (3)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
X = Don't care
Default after reset (PUC, POR)
The pin direction is controlled by the USCI module.
UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output, USCI_A0 is forced to
3-wire SPI mode even if 4-wire SPI mode is selected.
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = y
ADC10AE0.y
P3REN.x
P3DIR.x
0
P3OUT.x
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
DVSS
DVSS
P3.6/A6
P3.7/A7
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Table 29. Port P3 (P3.6, P3.7) Pin Functions
PIN NAME (P3.x)
P3.6/A6
P3.7/A7
(1)
(2)
(3)
x
6
7
y
6
7
FUNCTION
P3.6
(2)
(I/O)
A6/ (3)
P3.7 (2) (I/O)
A7 (3)
CONTROL BITS/SIGNALS (1)
P3DIR.x
P3SEL.x
ADC10AE0.y
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
P4REN.x
P4DIR.x
0
P4OUT.x
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 30. Port P4 (P4.0 to P4.2) Pin Functions
PIN NAME (P4.x)
x
P4.0
P4.0/TB0
0
CONTROL BITS/SIGNALS
FUNCTION
(1)
(I/O)
1
I: 0; O: 1
0
0
1
Timer_B3.TB0
1
1
I: 0; O: 1
0
Timer_B3.CCI1A
0
1
Timer_B3.TB1
1
1
I: 0; O: 1
0
Timer_B3.CCI2A
0
1
Timer_B3.TB2
1
1
P4.2 (1) (I/O)
P4.2/TB2
(1)
58
2
P4SEL.x
Timer_B3.CCI0A
P4.1 (1) (I/O)
P4.1/TB1
P4DIR.x
Default after reset (PUC, POR)
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
†
INCHx = 8+y
ADC10AE1.y
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.3/TB0/A12
P4.4/TB1/A13
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 31. Port P4 (P4.3 to P4.4) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.3
P4.3/TB0/A12
3
4
(2)
(1)
(2)
(3)
4
5
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
0
1
0
Timer_B3.TB0
1
1
0
(3)
P4.4 (2) (I/O)
P4.4/TB1/A13
P4DIR.x
Timer_B3.CCI0B
A12
(I/O)
CONTROL BITS/SIGNALS (1)
Timer_B3.CCI1B
X
X
1
I: 0; O: 1
0
0
0
1
0
Timer_B3.TB1
1
1
0
A13 (3)
X
X
1
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger
Timer_B Output Tristate Logic
P4.6/TBOUTH/A15
P4SEL.6
P4DIR.6
ADC10AE1.7
Pad Logic
To ADC 10
INCHx = 14
ADC10AE1.6
P4REN.5
P4DIR.5
0
P4OUT.5
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.5/TB3/A14
Bus
Keeper
P4SEL.5
EN
P4IN.5
EN
Module X IN
D
Table 32. Port P4 (P4.5) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.5
P4.5/TB3/A14
(1)
(2)
(3)
60
5
6
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
Timer_B3.TB2
1
1
0
A14 (3)
X
X
1
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger
Pad Logic
To ADC 10
INCHx = 15
ADC10AE1.7
P4REN.6
P4DIR.6
0
P4OUT.6
0
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
P4.6/TBOUTH/
A15
Bus
Keeper
P4SEL.6
EN
P4IN.6
EN
Module X IN
D
Table 33. Port P4 (P4.6) Pin Functions
PIN NAME (P4.x)
x
y
FUNCTION
P4.6
P4.6/TBOUTH/A15
(1)
(2)
(3)
6
7
(2)
(I/O)
CONTROL BITS/SIGNALS (1)
P4DIR.x
P4SEL.x
ADC10AE1.y
I: 0; O: 1
0
0
TBOUTH
0
1
0
DVSS
1
1
0
A15 (3)
X
X
1
X = Don't care
Default after reset (PUC, POR)
Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger
Pad Logic
DVSS
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.7/TBCLK
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Table 34. Port P4 (Pr.7) Pin Functions
PIN NAME (P4.x)
x
CONTROL BITS/SIGNALS
FUNCTION
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B3.TBCLK
0
1
DVSS
1
1
P4.7 (1) (I/O)
P4.7/TBCLK
(1)
62
7
Default after reset (PUC, POR)
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SLAS892B – MARCH 2013 – REVISED OCTOBER 2013
JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is
held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After
deactivation, the fuse check mode remains inactive until another POR occurs. After each POR, the fuse check
mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 24). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITF
ITEST
Figure 24. Fuse Check Mode Current
NOTE
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit
bootloader access key is used. Also, see the Bootstrap Loader section for more
information.
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REVISION HISTORY
Literature
Number
SLAS892
64
Summary
Production Data release
SLAS892A
Wake-Up From Lower-Power Modes (LPM3, LPM4), Removed MAX value from tDCO,LPM3/4.
SLAS892B
Device Pinout, DSBGA (YFF Package), Added ball-side view, changed top-side view, and removed package
dimensions from pinout (see the package mechanical data near the end of this data sheet for dimensions).
Added Development Tools Support and Device and Development Tool Nomenclature.
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PACKAGE OPTION ADDENDUM
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18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430G2444IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
M430G2444
MSP430G2444IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
M430G2444
MSP430G2444IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
M430
G2444
MSP430G2444IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
M430
G2444
MSP430G2444IYFFR
ACTIVE
DSBGA
YFF
49
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
M430G2444
MSP430G2444IYFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
M430G2444
MSP430G2544IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
M430G2544
MSP430G2544IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
M430G2544
MSP430G2544IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
M430
G2544
MSP430G2544IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
M430
G2544
MSP430G2544IYFFR
ACTIVE
DSBGA
YFF
49
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
M430G2544
MSP430G2544IYFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
M430G2544
MSP430G2744IDA38
ACTIVE
TSSOP
DA
38
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430G2744
MSP430G2744IDA38R
ACTIVE
TSSOP
DA
38
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
M430G2744
MSP430G2744IRHA40R
ACTIVE
VQFN
RHA
40
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
G2744
MSP430G2744IRHA40T
ACTIVE
VQFN
RHA
40
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430
G2744
MSP430G2744IYFFR
ACTIVE
DSBGA
YFF
49
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
M430G2744
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Oct-2013
Status
(1)
MSP430G2744IYFFT
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YFF
49
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
M430G2744
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
D: Max = 3.518 mm, Min =3.458 mm
E: Max = 3.36 mm, Min = 3.3 mm
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Texas Instruments:
MSP430G2744IRHA40R MSP430G2744IDA38R MSP430G2744IRHA40T MSP430G2744IYFFR
MSP430G2744IYFFT MSP430G2444IYFFR MSP430G2544IYFFT MSP430G2544IYFFR MSP430G2444IYFFT