Anpec APW8871 Ddr4 total power solution (vpp/vddq/vtt) synchronous dc/dc converter for nb/mb Datasheet

APW8871
DDR4 TOTAL POWER SOLUTION (VPP/VDDQ/VTT)
SYNCHRONOUS DC/DC CONVERTER for NB/MB
Features
•
Built in Fixed Valley Current Limit Protection
•
Built In Thermal Shutdown Function
High Input Voltages Range from 4.5V to 25V Input
•
Support Only 10µF MLCC for Stability on VTT LDO
Power
•
VTT and VTTREF Track at Half the VDDQ by internal
Provide 4 Independent Outputs for VPP, VDDQ, VTT LDO
and VTTREF LDO
VDDQ Converter
•
•
+0.75A LDO Section (VTT)
Provide 1.2V (DDR4) or Adjustable Output Voltage
divider
•
Max to 1.8V by SMBus Control
- +1% Accuracy over Temperature
•
•
Built In 0.7 5A Source/Sink Capability on VTT LDO
and 10mA Source/Sink Capability on VTTREF LDO
High Efficiency Performance up to 90%scale & Low
•
Independent Current Limit Protection
Shutdown Current <1uA
•
Thermal Shutdown Protection
Integrated High_Side N-Channe l MOSFET 20mΩ
•
4mmx4mm 26-pin package (TQFN-26)
•
Halogen and Lead Free Available (RoHS Compliant)
a nd Low_ Side N-Cha nne l MOSFET 10 m Ω @
VCC=5V
•
Integrated Bootstrap Forward P-CH MOSFET
•
Built in Internal Soft-Sta rt: 0.4 ms(typ.) and Soft-
General Description
The APW8871 integrates two synchronous buck PWM
controller and high/low side power MOSFETs to generate VPP and VDDQ, two sourcing and sinking LDO linear
regulator to generate VTT and VTTREF. It provides a complete power supply for DDR4 memory system. It offers
the lowest total solution cost in system where space is at
a premium.
Stop Functions for PWM Output
•
Built In Automatic PFM/PWM Mode Selection
•
Fixed 800kHz Switching Frequency
•
S3 and S5 Pins Control The Device in S0, S3 or S4/
S5 State
•
Built In PMAX Signal for Total Power Indicator
•
Power Good Monitoring
•
60% Under-Voltage Protection (UVP)
•
125% Over-Voltage Protection (OVP)
•
Built in Fixed Valley Current Limit Protection
•
The APW8871 provides excellent transient response
and accurate DC voltage output in PFM Mode. In Pulse
Frequency Mode (PFM), the APW8871 provides very
high efficiency over light to heavy loads with loadingmodulated switching frequencies.
The APW8871 has maximum power indicator function
in order to prevent over load condition. The device also
has single enable for VPP and VDDQ with JEDEC
sequence implemented. Moreover, the APW8871
integrates SMBus controller to program VDDQ output
voltage, VDDQ DAC voltage adjustment, VDDQ voltage
slew rate setting, and VDDQ PWM converter frequency.
Built In Thermal Shutdown Function
VPP Converter
•
Integrated High_Side P-Channel MOSFET 220mΩ
and Low_ Side N-Channe l MOSFET 2 00 mΩ @
VCC=5V
•
Excellent Reference Voltage = 0.6V
- +1% Load/Line Regulations over all TC range
•
Fixed 1MHz switching Frequency
•
Built in Internal Soft-Sta rt: 0.2 ms(typ.) and Soft-
The APW8871 is equipped with accurate current-limit,
output under-voltage, output over-voltage and over-temperature protections. A Power-On- Reset function monitors the voltage on VCC prevents wrong operation during
power on.
Stop Functions for PWM Output
•
60% Under-Voltage Protection (UVP)
•
125% Over-Voltage Protection (OVP)
ANP EC res erves the right to ma ke cha nges to imp rove relia bility or m anufac turab ility witho ut no tice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
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APW8871
General Description (cont.)
Applications
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 0.75A. It also incorporates current-limit
and thermal shutdown protection.
•
DDR3 and DDR4 Memory Power Supplies
•
NB/MB/Tablet
An internal resistor divider is used to provide a half voltage of VDDQ for VTTREF and VTT Voltage. The VTT output voltage is only requiring 10µF of ceramic output capacitance for stability and fast transient response. The
S3 and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
The APW8871 is available in 4mmx4mm 26-pin Thin QFN
package.
Simplified Application Circuit
VCC=5V
VPVCC =3~5.5V
VIN
+4.5V~25V
VTT
VDDQ/2
VPP PWM
Converter
Q1
DDR
LDO
L1
VDDQ PWM
Converter
VDDQ
Q3
L2
VPP
VCC
Q4
Q2
SMBUS Interface
SMC
S3
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S5
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APW8871
Ordering and Marking Information
APW 8871
Package Code
QB : TQFN4x4-26
Operating Ambient Temperature Range
o
I : -40 to 85 C
Handling Code
TR : Tape & Reel
TY : Tray
Lead Free Code
L : Lead Free Device Blank : Original Device
Lead Free Code
Handling Code
Temperature Range
Package Code
APW 8871 QB :
APW8871
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; w hich
are fully compliant w ith RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-fr ee (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by w eight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
w eight).
VTTREF
VTT
AGND
VTTSNS
S3
S5
POK
Pin Configuration
26 25 24 23 22 21 20
PMAX 1
19 VDDQSNS
FB2 2
18 VLDOIN
SMD 3
17 BOOT
PGND
SMC 4
16 PGND
VCC 5
15 LX1
LX1
VIN
VIN
LX1
9 10 11 12 13
VIN
8
VIN
7
LX2
14 LX1
LX2
PVCC 6
TQFN4x4-26 (Top View)
= Thermal Pad (Include LX1 and PGND)
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APW8871
Absolute Maximum Ratings (Note 1.2)
Symbol
VCC, VPVCC
VIN
Parameter
Rating
Unit
VCC /PVCC Supply Voltage (VCC/PVCC to AGND)
-0.3 ~ 7
V
VIN Supply Voltage (VIN to AGND)
-0.3 ~ 28
V
VBOOT
BOOT Supply Voltage (BOOT to LX1)
-0.3 ~ 7
V
VBOOT-GND
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
-5 ~ 35
-0.3 ~ 28
V
-5 ~ 9
-0.3 ~ 7
V
-0.3 ~ 7
V
-0.3 ~ 0.3
V
LX1 Voltage (LX1 to GND)
VLX1
<20ns pulse width
>20ns pulse width
LX2 Voltage (LX2 to GND)
VLX2
<20ns pulse width
>20ns pulse width
All Other Pins (FB2, S3, S5, VDDQSNS, SMD, SMC, POK,
VLDOIN, VTTSNS, VTT, and VTTREF to AGND Voltage)
PGND to AGND Voltage
Tj
Maximum Junction Temperature
TSTG
Storage Temperature
T SDR
Maximum Soldering Temperature, 10 Seconds
150
o
C
-65 ~ 150
o
C
260
o
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability
Note 2: The device is ESD sensitive. Handling precautions are recommended.
Thermal Characteristics(Note 3)
Symbol
Parameter
Value
θJA
Thermal Resistance -Junction to Ambient
40
θJC
Thermal Resistance -Junction to Case
12
Unit
°C/W
Note3: θJA and θJC are measured with the component mounted on a high effective the thermal conductivity test board in free air. The
exposed pad of package is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
Range
Unit
VCC
VCC Supply Voltage
Parameter
4.5 ~ 5.5
V
V IN
Converter Input Voltage
4.5 ~ 25
V
VPVCC
PVCC Supply Voltage
3 ~ 5.5
V
VVDDQ
VDDQ Output Voltage
1.0 ~ 1.7
V
V VPP
VPP Output Voltage
0.6 ~ 3.3
V
V VTT
LDO Output Voltage
0.5 ~ 0.9
V
IVPP
VPP Output Current
0 ~ 0.6
A
VDDQ Output Current
0 ~ 8.5
A
-0.75 ~ +0.75
A
0.5 ~ 4.7
µH
I VDDQ
IVTT
LDO Output Current
L1
VDDQ Output Inductor
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APW8871
Recommended Operating Conditions
Symbol
Parameter
VPP Output Inductor
L2
Range
Unit
2.2 ~ 4.7
µH
1~
µF
CVCC
VCC Capacitance
CVDDQ
VDDQ Output Capacitance
100 ~
µF
CVPP
VPP Output Capacitance
10 ~
µF
CVTT
VTT Output Capacitance
10 ~
µF
0.22 ~ 2.2
µF
CVTTREF
VTTREF Output Capacitance
TA
Ambient Temperature
-40 ~ 85
o
C
TJ
Junction Temperature
-40 ~ 125
o
C
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=19V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW8871
Unit
Min
Typ
Max
-
270
320
µA
-
245
295
µA
0.1
1
µA
SUPPLY CURRENT
I VCC
VCC Supply Current
TA = 25oC, VS3 = V S5 = 5V, no load
o
IVCCSTB
VCC Standby Current
IVCCSDN
VCC Shutdown C urrent
TA =25 C, V S3 = VS5 = 0V, no load
-
ILDOIN
LDOIN Supply Current
TA = 25oC, VS3 = V S5 = 5V, no load
0.3
0.6
1
mA
ILDOINSTB
LDOIN Standby Current
TA = 25 C, VS3 = 0V, VS5 = 5V, no load,
o
-
0.1
1
µA
o
-
0.1
1
µA
4.1
4.3
4.45
V
-
100
-
mV
-
0.6
-
V
-20
-
20
-30
-
30
I LDOINSDN
LDOIN Shutdown Current
TA = 25 C, VS3 = 0V, VS5 = 5V, no load
o
TA = 25 C, VS3 = V S5 = 0V, no load
POWER-ON-RESET
VCC POR Threshold
VCC Rising
VCC POR Hysteresis
VTT OUTPUT
VVTT
V VTT
VTT Output Voltage
VLDOIN = V VDDQ = 1.2V
VLDOIN = V VDDQ = 1.2V, V VDDQ/2 - VVTT,
IVTT = 0A
VTT Output Tolerance
VLDOIN = V VDDQ = 1.2V, V VDDQ/2 - VVTT,
IVTT = ±
0.75A
I LIM
Current-Limit
IVTTLK
VTT Leakage Current
I VTTSNSLK
I VTTDIS
Sourcing Current (VLDOIN =1.2V)
0.8
1
1.3
Sinking Current (VLDOIN =1.2V)
-0.8
-1
-1.3
-1.0
-
1.0
-1.00
0.01
1.00
µA
-
5
-
mA
VVTT = 1.25V, VS3 = 0V, VS5 = 5V,
o
TA = 25 C
VTTSNS Leakage Current
VVTT = 1.25V, T A = 25oC
VTT Discharge Current
VVTT = 0.5V, VS3 = VS5 = 0V, T A = 25oC
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A
µA
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APW8871
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=19V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
Test Conditions
APW8871
Unit
Min
Typ
Max
-
0.6
-
V
-12
-
+12
mV
VTTREF OUTPUT
V VTTREF
VTTREF Output Voltage
VTTREF Tolerance
V LDOIN = V VDDQ = 1.2V, VVDDQ/2
-10mA < IVTTREF < 10mA, VVDDQ/2 - VVTTREF
V LDOIN = V VDDQ = 1.2V
IVTTREF
VTTREF Source Current
V VTTREF = 0V
-10
-20
-40
mA
IVTTREF
VTTREF Sink Current
V VTTREF = 1.2V
10
20
40
mA
VTTREF Discharge Current
T A=25 C, S3=S5=0V, VTTREF=0.5V
o
-
2
-
mA
VDDQ Sense Voltage
VDDQ Initial Setting = 1.2V
-
1.2
-
V
VDDQ Regulation Voltage
Tolerance to SMBus Setting
T A=25 oC
-3
-
3
mV
VDDQSNS Input Current
V VDDQSNS=2V
-0.5
-
0.5
uA
VDDQSNS Discharge Current
V S3 = VS5 = 0V, V VDDQ = 0.5V, VDDQSNS to GND
MOSFET turns on
-
12
25
mA
LDOIN Discharge Current
V S3 = VS5 = 0V, V VDDQSNS = 0.5V, (Tracking)
-
700
-
mA
IVTTREFDIS
VDDQ OUTPUT
VVDDQ
IVDDQ
VDDQ PWM CONTROLLERS
FSW
Operating Frequency
V CC=4.5V~5.5V
720
800
880
kHz
TSS_VDDQ
Internal Soft Start Time
V VPP is High to VVDDQ Regulation
0.3
0.4
0.5
ms
T OFF (MIN)
Minimum off time
200
300
400
ns
T ON(MIN)
Minimum on time
80
110
140
ns
-5
0.5
5
mV
High-Side N-MOSFET
RON_HS_VDDQ Resistance
-
20
30
mΩ
Low-Side N-MOSFET
Resistance
-
10
15
mΩ
11
12
13
A
-
-5
-
A
120
125
130
%
Over all temperature and VCC
Zero-Crossing Threshold
VDDQ POWER MOSFET
RON_LS_VDDQ
VDDQ PROTECTIONS
VOCL
V NOCL
Current Limit Threshold
Negative Current Limit
Threshold
Sensing Valley Current
VDDQ OVP Trip Threshold
V VDDQ Rising
VDDQ OVP Debounce Delay
V VDDQ Rising, DV=10mV
VDDQ UVP Trip Threshold
V VDDQ Falling
VDDQ UVP Debounce
VDDQ UVP Enable Delay
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From S5=H to POK goes high
6
-
2
-
µs
55
60
65
%
-
2
-
µs
-
0.7
-
ms
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APW8871
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=19V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
Symbol
Parameter
APW8871
Test Conditions
Min
Typ
Max
Unit
VPP PWM CONTROLLER
VVREF_PP
IFB2
FSW
-
0.6
-
V
VFB2 =2V
-50
-
50
nA
VPP Reference Voltage
VFB2 Input Current
Over All Temperature Range
-0.5
-
0.5
%
Reference Voltage Accuracy
Load and Line Regulation,
IVPP< 0.6A, 3V < PVCC< 5.5V
-0.5
-
0.5
%
Operating Frequency
VCC=4.5V~5.5V
850
1000
1150
kHz
S5 is High to VVPP Regulation
T SS_VPP
Internal Soft Start Time
T OFF (MIN)
Minimum off time
0.1
0.2
0.3
ms
200
300
400
ns
T ON(MIN)
Minimum on time
80
110
140
ns
Zero-Crossing Threshold
-5
0.5
5
mV
LX2 Discharge Resistance
-
-
100
Ω
Over All Temperature and V CC
VS3 = VS5 = 0V
VPP POWER MOSFET
RON_HS_PP
High-Side P-MOSFET
Resistance
-
-
220
mΩ
RON_LS_PP
Low-Side N-MOSFET
Resistance
-
-
200
mΩ
Internal Design Spec.
2
3
5
ns
Sensing Valley Current
2.5
3
3.5
A
-
-0.6
-
A
120
125
130
%
TD
Dead Time
VPP PROTECTIONS
VOCL
Current Limit Threshold
V NOCL
Negative
Threshold
Current
Limit
VPP OVP Trip Threshold
VVPP Rising
VPP OVP Debounce Delay
VVPP Rising, DV=10mV
-
2
-
µs
55
60
65
%
VPP UVP Debounce
-
2
-
µs
VPP UVP Enable Delay
-
0.7
-
ms
87
90
93
%
120
125
130
%
VPP UVP Trip Threshold
VVPP Falling
POK
POK in from Lower (POK Goes High)
VPOK
POK Threshold
POK Out from Normal (POK Goes Low)
IPOK
POK Leakage Current
VPOK=5V
-
0.1
1.0
µA
POK Output Low Voltage
VCC=5V, IPOK_SINK =4mA
-
0.5
1
V
POK Enable Delay Time
S5 High to POK High
-
0.7
-
ms
POK Delay Time
Delay for POK Rise Up/ Fall Down
-
20
-
µs
-
0.15
0.25
V
-
0.2
0.5
µA
BOOTSTRAP DIODE
VF
Forward Voltage
IF
Reverse Leakage
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VVCC – VBOOT =5V, I F = 10mA, TA = 25 oC
o
VBOOT = 30V, VLX = 25V, VVCC=5V, TA = 25 C
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APW8871
Electrical Characteristics
Ref er to the typical applic ation cir cuits . These s pecif ications apply over V VCC=V BOO T =5V, V IN=19V and TA= -40 ~ 85oC, unless
otherw ise specified. Typical values are at TA=25oC.
APW8871
Symbol
Parameter
Test Conditions
Min
Typ
Max
1.6
-
-
Unit
LOGIC THRESHOLD
VIH
S3, S5 High Threshold Voltage
S3, S5 Rising
VIL
S3, S5 Low Threshold Voltage
S3, S5 Falling
-
-
0.6
V
Logic Input Leakage Current
VS3 = VS5 = 5V, T A =25 C
-1
-
1
µA
TJ Rising
-
150
-
o
C
-
o
C
I ILEAK
o
V
THERMAL SHUTDOWN
T SD
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
-
40
Note4 : Guaranteed by design.
SMBus Serial Control Port Operation
Timing characteristics for SMBus Interface signals over recommended operating conditions (unless otherw ise noted)
APW8871
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
Input High Voltage Threshold
1.6
-
-
V
Input Low Voltage Threshold
-
-
0.9
V
10
-
100
kHz
fSMC
Frequency, SMC
tHIGH
Pulse Duration, SMC High
4
-
50
tLOW
Pulse Duration, SMC Low
4.7
-
-
tR
Rise Time, SMC and SMD
-
-
1
µs
tF
Fall Time, SMC and SM D
-
-
300
ns
VCC=4.5V to 5.5V
µs
tSU_DAT
Data Setup Time
250
-
-
ns
tHD_DAT
Data Hold Time
300
-
-
ns
4.7
-
-
tBUF
Bus Free Time Between Stop
and Start Condition
tSU_STA
Setup Time for Start Condition
4.7
-
-
tHD_STA
Start Condition Hold Time
after Which First Clock Pulse
4
-
-
µs
Is Generated
tSU_STO
Setup Time for Stop Condition
4
-
-
µs
tTIMEOUT
SMBus Bus Release Timeout
25
-
35
ms
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APW8871
SMBus Serial Control Port Operation(cont.)
tLOW tR
SMC
VI
tF
H
VIL
tHIGH
tHD_STA
tHD_DAT
SMD
VI
tSU_DAT
tSU_STA
tSU_STO
H
VIL
tBUF
P
P
S
S
Figure1. SMC and SMD Timing
Pin Description
NO.
NAME
FUNCTION
1
PMAX
Open drain indicator. When total power is larger than setting values, then this pin will assert to PCH
or CPU.
2
FB2
VPP PWM output voltage feedback pin. This pin is connected the resistor divider to set the desired
output voltage.
3
SMD
Serial data. This pin must be connected to AGND if not used.
4
SMC
Serial clock. This pin must be connected to AGND if not used.
5
VCC
Filtered 5V power supply input for internal control circuitry.
6
PVCC
7, 8
LX2
VPP Junction point of the high-side MOSFET Source, output filter inductor and the low-side
MOSFET Drain for VPP PWM Converter.
9 ~12
VIN
VDDQ Power input stage pin. This pin supply voltage for internal high side power MOSFET.
13~15
LX1
Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET
Drain for VDDQ PWM Converter.
16
PGND
Power ground for internal low side power MOSFET source.
17
BOOT
Supply Input for the internal UGATE gate driver and an internal level-shift circuit. Connect to an
external capacitor and diode to create a boosted voltage suitable to drive an internal logic-level
N-channel MOSFET.
18
LDOIN
Supply voltage input for the VTT LDO.
19
VDDQSNS
20
VTTREF
21
VTT
22
VTTSNS
23
AGND
24
S5
S5 signal input.
25
S3
S3 signal input.
26
POK
VPP Power input stage pin. This pin supply voltage for internal high side power MOSFET.
Reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking
terminal for VDDQ discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is
connected to VCC or GND.
VTTREF buffered reference output.
Power output for the VTT LDO.
Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.
Signal ground for PWM controller and VTT LDO.
Power-okay output pin. POK is an open drain output used to Indicate the status of the output
voltage. When VDDQ/VPP output voltage is within the target range, it is in high state.
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APW8871
Typical Operating Characteristics
2
I C Setting VVDDQ=1.2V
VPP Reference Voltage
0.65
VPP Reference Voltage (V)
VDDQ Output Voltage (V)
1.30
1.25
1 .20
1.15
0.63
0.61
0.59
0.57
0.55
1 .10
-40
-20
20
0
40
60
80
100 120 140
-40
-20
Supply Current vs. Junction
Temperature
20
40
60
80
100 120 140
VCC Standby Current vs. Junction
Temperature
500
VCC Standby Current, (µA)
500
VCC Supply Current, (µA)
0
Junction Temperature, TJ (°C)
Junction Temperature, TJ (°C)
400
300
200
100
400
300
200
100
S3=0V, S5=5V
S3=S5=5V
0
0
-40
-20
0
20
40
60
80
100 120 140
-40
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-20
0
20
40
60
80
100
120 140
Junction Temperature, TJ (°C)
Junction Temperature, TJ (°C)
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APW8871
Operating Waveforms
S5=S3 Enable, No Load
S5=S3 Shutdown- No Load
4
4
3
3
2
2
1
1
CH1: VPOK (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVPP (2V/div)
CH4: VS5 (5V/div)
Time: 200µs/div
CH1: VPOK (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVPP (2V/div)
CH4: VS5 (5V/div)
Time: 200µs/div
S3 Shutdown è HZ Mode
S3 Enable
4
3
3
2
2
1
1
CH1: VVTT (500mV/div)
CH2: VLX1 (20V/div)
CH3: VVDDQ (1V/div)
CH4: VS 3 (5V/div)
Time: 20µs/div
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CH1: VVTT (500mV/div)
CH2: VVDDQ (1V/div)
CH3: VS3 (5V/div)
Time: 5ms/div
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APW8871
Operating Waveforms
VDDQ Load Transient,
IVDDQ = 0A->8A->0A
S5 Shutdown-Enable, Non-Zero VDDQ
4
3
3
2
2
1
1
CH1: VPOK (5V/div)
CH2: VVDDQ (1V/div)
CH3: VVPP (2V/div)
CH4: VS5 (5V/div)
Time: 200µs/div
CH1: IL1 (5A/div)
CH2: VVDDQ (AC,200mV/div)
CH3: VLX1 (20V/div)
Time: 50µs/div
VTT Source Load Transient,
IVTT = 0A->1A->0A
VTT Source Load Transient,
IVTT = 0A->1A->0A
4
4
3
3
2
2
1
1
CH1: IVTT (500mA/div)
CH2: VVTT (AC,100mV/div)
CH3: VLX1 (20V/div)
CH4: VVDDQ (1V/div)
Time: 100µs/div
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CH1: IVTT (500mA/div)
CH2: VVTT (AC,100mV/div)
CH3: VLX1 (20V/div)
CH4: VVDDQ (1V/div)
Time: 100µs/div
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APW8871
Operating Waveforms
VPP Load Transient,
IVPP = 0A->1A->0A
Short Circuit Test to VDDQ Terminal
3
3
2
2
1
1
CH1: IL1 (10Adiv)
CH2: VVDDQ (1V/div)
CH3: VVPP (2V/div)
Time: 50µs/div
CH1: IL2 (1A/div)
CH2: VVPP (AC,500mV/div)
CH3: VLX2 (5V/div)
Time: 20µs/div
Short Circuit Test to VPP Terminal
4
3
2
1
CH1: IL2 (2A/div)
CH2: VVTT (500mV/div)
CH3: VVDDQ (1V/div)
CH4: VVPP (2V/div)
Time: 200µs/div
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APW8871
Block Diagram
0.5 x VDDQSNS
VDDQSNS
VTTREF
VLDOIN
Thermal
Shutdown
S3
S3,S5 Control
Logic
S5
Current Limit
VTT
SMC
SMBus Interface
SMD
VTTSNS
PMAX
REFIN
80% of VDDQ
Current Limit
VDDQ DAC
Control
Discharge
Level
Sensing
POR
VCC
Soft
Start
VIN
VIN
Current
Limit
Error
Comparator
125% x REFIN
OV
VIN
BOOT
UV
60% x REFIN
LX1
LX1
TON
Generator
ZC
VDDQ
PWM
Signal
Controller
REFIN x 125%
VCC
VREF=0.6V
REFIN x 90%
FB2
Current Limit
Error
125% x VREF Comparator
OV
PVCC
PVCC
UV
60% x VREF
LX2
ZC
POK
TON
Generator
VPP
PWM
Signal
Controller
LX2
VCC
VREF x 125%
Delay
PGND
AGND
VREF x 90%
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APW8871
Typical Application Circuit
R POK
100K
R PMAX
100K
R VCC
5V
S5
2 .2
S3
VTTSNS
VIN
S5
S3
C VLDOIN
10 µF
(MLCC)
PMAX
POK
VLDOIN
CBOOT
0. 1µF
CIN
10uF x 2
(MLCC)
BOOT
VLDOIN
CVTT
10 µF
(MLCC)
VTTREF
VDDQ/2
L OUT1
1 µH
APW8871
VTT
LX1
VDDQ
1 .2V /8.5 A
CV CC
1µF
VTT
4.5 V~25 V
VCC
VTTREF
C IN
1 0µF
(MLCC)
L OUT2
1 .5 µH
FB2
A GND
PGND
SMD
SMC
C VT TREF
0. 22µF
C VDDQ
VDDQSNS
PVCC
LX 2
VPVCC
4.5 V ~5. 5V
100 µF(MLCC)
VPP
2 .5V /0.6A
CVPP
4 7K
100K
10µF(MLCC)
100 K
15 K
SMBus Power
DDR4 Total Power Solution Application Circuit
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APW8871
Function Description
The APW8871 integrates two synchronous buck PWM
controller and high/low side power MOSFETs to generate VPP and VDDQ, two sourcing and sinking LDO linear
regulator to generate VTT and VTTREF. It provides a complete power supply for DDR4 memory system in 26-pin
TQFN package. User defined output voltage is also possible and can be adjustable from 0.6V to 3.3V for VPP
terminal and SMBus 2 bits programmable 1.0V/1.1V/1.
2V/0V with maximum 500mV DAC dynamic adjustable.
Input voltage range of the VDDQ PWM converter is 4.5V to
25V and for VPP PWM converter is 3V to 5.5V. The converter runs an adaptive on-time PWM operation at highload condition and automatically reduces frequency to
keep excellent efficiency down to several mA.
The VTT LDO can source and sink up to 0.75A peak current with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
VTTREF within 20 mV at no load condition while 30 mV at
full load. The LDO input can be separated from VDDQ
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8871 is fully compatible to
JEDEC DDR4 specifications at S3/S5 sleep state (see
Table 1). When VPP, VDDQ and VTT are disabled, the
part has output tracking discharge function. The tracking
discharge mode discharges VDDQ and VTT outputs
through the internal LDO transistors and then VTT output
tracks half of VDDQ voltage during discharge. When VDDQ
voltage has been discharged to about 200mV, the internal discharge MOSFETs that are connected to VDDQ and
VTT are turned on. The current capability of these discharge MOSFETs are limited and discharge occurs more
slowly than the tracking discharge. Furthermore, the device discharges VPP Voltage by the internal resistor
through LX2 to PGND.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic co ntrols w hen the VCC voltag e is low . The
POR function continuall y monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set
hi gh. When the ris ing VCC voltage reaches the risi ng
POR voltage threshold (4.3Vtypical), the POR signal goes
high and the chip initiates soft-start operations. There is
alm ost no hyste resis to POR voltage thresho ld (ab out
100mV typical). When VCC vo ltage drop lower than 4.2V
(typical), the POR disables the chip.
Power Sequence and Soft- Start
Th e APW88 71 co nfo rm s to JEDEC D DR4 s equ en ce
specification. VPP must ramp at the same time or earlier
than VDD Q and VPP termi nal voltag e mus t equ al to or
higher than VDDQ at all time. APW8871 integrates digital
soft-start circuits to ramp up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. Th e slew rate of output voltag e is in ternally controlled to limit the inrush current through the output capacitors during soft-start process.
Constant-On-Time PWM Controller with Input FeedForward
The constant on-tim e contro l architecture is a pse udofixed frequency with i nput voltage feed-forward. This archite cture re lies on the outpu t filter capacito r’s effe ctive
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
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In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined so lely by a oneshot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switchin g frequency control circuit in the on -time generator bl ock. Th e swi tchi ng freq uen cy co ntro l circu it
senses th e switching freque ncy of the high-si de switch
and ke eps regula ting it at a constant frequency in PWM
mode. The design improves the frequency variation and
be more outstandin g than a co nventional cons tant ontime controller which has large switching frequency variation over inpu t voltage , output current an d tempera ture.
Bo th in PFM and PWM, th e o n-tim e g ene ra tor, w hi ch
sen ses in put voltage on VIN and PVCC pins, provi des
very fast on-time response to input line transients.
An othe r on e-sh ot se ts a m in im um off-ti me (typi ca l:
300ns). The on-time one-shot is triggered if the error comparator is high , the low-side switch curren t is below the
current-limi t thres hold, an d the mi nimum o ff-time oneshot has timed out.
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APW8871
Function Description (Cont.)
APW8871 has an independent counter for each output,
but the POK signal indicates only the status of VPP and
VDDQ and does not indicate VTT power good externally.
Power-Good Output (POK)
POK is an open-drain output and the POK comparator
continuously monitors the output voltage. POK is actively
held low in shutdown, and standby. When both PWM converters’ output voltages are greater than 90% of their target value, the internal open-drain device will be pulled
low. After 20µs debounce time, the POK goes high. When
one of the output voltages VPP/VDDQ outrun 125% of the
target voltage, POK signal will be pulled low with 20ms
debounce time.
Under Voltage Protection
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is bigger than current limit threshold value, the output voltage
will fall out of the required regulation range. The undervoltage continually monitors the setting output voltage
after both PWM operations to ensure startup. If a load
step is strong enough to pull the output voltage lower
than the under voltage threshold (60% of normal output
voltage), the internal UVP delay counter begins counting.
After 2µs debounce time, the device turns off both internal high-side and low-side MOSFETs with latched and
starts a soft-stop process to shut down the output
gradually. Toggling enable pin to low or recycling VCC
will clear the latch and bring the chip back to operation.
Power Sequence and Soft- Start (cont.)
The figure 2 shows VPP/VDDQ soft-start sequence. When
the S5 pin is pulled above the rising S5 threshold voltage,
the device initi ates a soft-start proces s to ramp up the
output voltage . In norma l ope ratio n, the VDDQ voltage
starts to rise up after VPP voltage has been established.
The VPP PWM converter soft-start interval is 0.2ms (max.);
VDDQ PWM converter s oft-start inte rval is 0.4ms (max.)
and independent of the switching frequency.
0.7ms
VCC
0.2ms
VVPP
S5
V VDDQ
0.4ms
VPOK
Figure 2. Soft-Start Sequence.
During soft-start stage before the POK pin is ready, the
under voltage protection is prohibited. The over voltage
and current limit protection functions are enabled. If the
output capacitor has residue voltage before startup, both
internal low-side and high-side MOSFETs are in off-state
until the internal individual digital soft start voltage equal
the VVPP/VVDDQ voltages. This will ensure the output voltage starts from its existing voltage level.
The VTT LDO part monitors the output current, both sourcing and sinking current, and limits the maximum output
current to prevent damages during current overload or
short circuit (shorted from VTT to GND or VLDOIN)
conditions.
The VTT LDO provides a soft-start function, using the
constant current to charge the output capacitor that gives
a rapid and linear output voltage rise. If the load current is
above the current limit start-up, the VTT cannot start
successfully.
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Over Voltage Protection (OVP)
The feedback voltage should increase over 125% of the
reference voltage due to the high-side MOSFET failure or
for other reasons, and the over voltage protection comparator designed with a 2µs noise filter will turn on the
internal low-side MOSFET. If the inductor current triggers
negative current limit, the device turns off Low-side
MOSFET for 300ns (typ.) and repeats the OVP function
action.This action actively pulls down the output voltage.
When the OVP occurs, the POK pin will pull down and
latch-off the converter. This OVP scheme only clamps the
voltage overshoot, and does not invert the output voltage
when otherwise activated with a continuously high output
from the internal low-side MOSFET driver. It’s a common
problem for OVP schemes with a latch. Once an overvoltage fault condition is set, toggling VCC power-on-reset signal can only reset it.
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APW8871
Function Description (Cont.)
S3, S5 Control
PWM Converter Current Limit
The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 3). The APW8871 uses the
internal low-side MOSFET’s R DS(ON) of the synchronous
rectifier as a current-sensing element. If the magnitude
of the current-sense signal at LX1/LX2 pin is above the
current limit threshold individual, the PWM is not allowed
to initiate a new cycle. The actual peak current is greater
than the current limit threshold by an amount equals to
the inductor ripple current. Therefore, the exact currentlimit characteristic and maximum load capability are the
functions of the sense resistance, inductor value, and
input voltage.
The PWM controller uses the internal low-side MOSFETs
on-resistance R DS(ON) to monitor the current for protection
against shortened outputs.
When the inductor valley current IVALLEY is bigger than device setting ICL, the current limit function is triggered and
internal LGATE turns on until current limit event released.
IVALLEY can be expressed as I OUT minus half of peak-topeak inductor current.
In the DDR4 memory ap plication, it is important to keep
VPP always higher than VD DQ and VDDQ always higher
than VTT/VTTREF including both start-up and shutdown.
Th e S3 an d S5 si gna ls contro l the VPP, VDDQ, VTT,
VTTREF states an d these pi ns should be connected to
SLP_S3 and SLP_S5 sig nals res pecti vely. The tab le1
shows the truth tabl e of the S3 an d S5 pins. Wh en both
S3 and S5 are above the logic threshold voltage, the VPP,
VDDQ, VTT and VTTREF are turned on at S0 state. When
S3 is low and S5 is high, the VPP, VDDQ and VTTREF are
kept on wh ile th e VTT voltag e is d isable d and left h igh
impedance in S3 state. When both S3 and S5 are low, the
VDDQ, VTT and VTTREF are turned off and discharged to
the gro und accord ing to th e trackin g dis charg e. When
VDDQ voltage is lower than 200mV (typical), the discharge
mode changes from tracking to non-trackin g and at the
same time, it se nds a s ignal to enab le VPP disch arge
during S4/S5 state.
Table1. The Truth Table of S3 and S5 pins
STATE S3
INDUCTOR CURRENT
IPEAK
I OUT
IVALLEY
0
VDDQ
VTTREF
VTT
S0
H
H
1
1
1
S3
L
H
1
1
0 (high-Z)
S4/5
L
L
0 (discharge) 0 (discharge) 0 (discharge)
VPP, VDDQ and VTT Discharge Control
APW8871 discharges VPP, VDDQ, VTTREF and VTT outputs du ring S3 and S5 are both low. First, when S3 and
S5 are lo w, APW8871 disch arges VDDQ outpu t through
the internal VTT regulator transistors and VTT output tracks
half of VDDQ voltage during this tracking discharge. Note
that VDDQ discharge current flows via
VLDOIN to VTTGND thus VLD OIN must be conn ected to
VDDQ output. After VDDQ is discharged down to 0.2V, the
in ternal LD O i s turn ed off and th e i nte rna l d ischarge
MOSFETs that are connected to VDDQ and VTT are turned
on. At the same time, APW8871 will send a signal to turn
on VPP di scharge device from LX2 to AGND. Therefore,
in this design rule, VPP voltage could be always guaranteed bigger than VDDQ voltage.
Time
Figure 3. Current Limit Algorithm
VTT Sink/Source Regulator
The output voltage at VTT pin tracks the reference voltage
applied at VTTREF pin. Two internal N-channel MOSFETs
controlled by sep arate h igh bandwidth error amplifiers
re gul ate the ou tpu t vol tag e b y sou rci ng cu rre nt from
VLDOIN pin or sinking current to GND pin. To prevent two
pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error
am plifiers . Th e VTT wi th fast resp onse fee dback lo op
keeps tracking to the VTTREF within +30 mV at all conditions including fast load transient.
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APW8871
Function Description (Cont.)
PMAX Indicator
PMAX is an o pen-drain output and s uppo rts the PMAX
sig nal for VDDQ PWM co nverter p ower indicator. If the
inductor valley current is bigger than 80% of current limit
thre shold an d counts four cycles con tinually, or the device tem perature is over 120oC, th e intern al open-drain
device wil l be turned on. Th e PMAX signal will go low to
in di ca te th at the PMAX co nd itio n h as h app en ed and
pas ses m essag e to the s yste m. Wh en in ducto r val ley
current is less than 80% of current limit threshold, or the
device temperature is under 120oC, the PMAX signal will
be pulled high immediately. Therefore, this indicator function is not latch up.
Thermal Shutdown
A the rmal shutdown circuit limits the jun ction tem perature of APW8871. When the junction temperature exceeds
+150oC, both PWM converters, VTTLDO and VTTREF are
shut off, allow ing the device to cool down. The regulator
regulates the output again through initiation of a new softstart cycl e after the juncti on temperature coo ls by 40oC ,
resul ting in a pulsed o utput du ring continuous th ermal
overload conditions. The thermal shutdown designed with
a 40oC hysteresis lowers the average junction temperature durin g continuous therm al overload conditions, extending life time of the device.
For normal operation , device powe r dissipation should
be e xterna lly li mited so tha t junction tempera tures will
not exceed +125oC.
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APW8871
The device slave address is defined as “00101010” (2AH) for APW8871.
Register
Address
Description
Read/Write
Power On Default
Value
01
VDDQ Switching Frequency setting
Read/Write
00h
02
VDDQ Initial Voltage setting
Read/Write
02h
03
VDDQ DAC Voltage adjustable
Read/Write
00h
VDDQ Voltage Slew Rate
Read/Write
00h
04
The below tables define the operation of each register bit. Default values are in bold text.
REGISTER Address:01h
Bit
Name
Data
Read/Write
[7:3]
Reserve
-
-
000
Read/Write
VDDQ FSW = 400KHz at PWM mode.
001
Read/Write
VDDQ FSW = 600KHz at PWM mode.
010
Read/Write
VDDQ FSW = 800KHz at PWM mode.
011
Read/Write
VDDQ FSW = 1000KHz at PWM mode.
100
Read/Write
VDDQ FSW = 1200KHz at PWM mode.
101
Read/Write
VDDQ FSW = 1400KHz at PWM mode.
[2:0]
VDDQ FSW
Description
No Used
REGISTER Address:02h
Read/Write
Description
Bit
Name
Data
[7:2]
Reserve
-
-
00
Read/Write
VDDQ Voltage = 1.0V.
01
Read/Write
VDDQ Voltage = 1.1V.
10
Read/Write
VDDQ Voltage = 1.2V.
11
Read/Write
VDDQ Voltage = 0V.
[1:0]
VDDQ Initial Voltage
No Used
REGISTER Address:03h
Read/Write
Description
Bit
Name
Data
[7:6]
Reserved
-
-
000000
Read/Write
VDAC Voltage = 0mV
000001
Read/Write
VDAC Voltage = 10mV
000010
Read/Write
VDAC Voltage = 20mV
000011
Read/Write
VDAC Voltage = 30mV
000100
Read/Write
VDAC Voltage = 40mV
000101
Read/Write
VDAC Voltage = 50mV
000110
Read/Write
VDAC Voltage = 60mV
[5:0]
VDDQ DAC
No Used
000111
Read/Write
VDAC Voltage = 70mV
001000
Read/Write
VDAC Voltage = 80mV
001001
Read/Write
VDAC Voltage = 90mV
001010
Read/Write
VDAC Voltage = 100mV
001011
Read/Write
VDAC Voltage = 110mV
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APW8871
REGISTER Address:03h
Bit
[5:0]
Name
VDDQ DAC
Data
Read/Write
Description
001100
Read/Write
VDAC Voltage = 120mV
001101
Read/Write
VDAC Voltage = 130mV
001110
Read/Write
VDAC Voltage = 140mV
001111
Read/Write
VDAC Voltage = 150mV
010000
Read/Write
VDAC Voltage = 160mV
010001
Read/Write
VDAC Voltage = 170mV
010010
Read/Write
VDAC Voltage = 180mV
010011
Read/Write
VDAC Voltage = 190mV
010100
Read/Write
VDAC Voltage = 200mV
010101
Read/Write
VDAC Voltage = 210mV
010110
Read/Write
VDAC Voltage = 220mV
010111
Read/Write
VDAC Voltage = 230mV
011000
Read/Write
VDAC Voltage = 240mV
011001
Read/Write
VDAC Voltage = 250mV
011010
Read/Write
VDAC Voltage = 260mV
011011
Read/Write
VDAC Voltage = 270mV
011100
Read/Write
VDAC Voltage = 280mV
011101
Read/Write
VDAC Voltage = 290mV
011110
Read/Write
VDAC Voltage = 300mV
011111
Read/Write
VDAC Voltage = 310mV
100000
Read/Write
VDAC Voltage = 320mV
100001
Read/Write
VDAC Voltage = 330mV
100010
Read/Write
VDAC Voltage = 340mV
100011
Read/Write
VDAC Voltage = 350mV
100100
Read/Write
VDAC Voltage = 360mV
100101
Read/Write
VDAC Voltage = 370mV
100110
Read/Write
VDAC Voltage = 380mV
100111
Read/Write
VDAC Voltage = 390mV
101000
Read/Write
VDAC Voltage = 400mV
101001
Read/Write
VDAC Voltage = 410mV
101010
Read/Write
VDAC Voltage = 420mV
101011
Read/Write
VDAC Voltage = 430mV
101100
Read/Write
VDAC Voltage = 440mV
101101
Read/Write
VDAC Voltage = 450mV
101110
Read/Write
VDAC Voltage = 460mV
101111
Read/Write
VDAC Voltage = 470mV
110000
Read/Write
VDAC Voltage = 480mV
110001
Read/Write
VDAC Voltage = 490mV
110010
Read/Write
VDAC Voltage = 500mV
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APW8871
REGISTER Address:03h
Bit
[5:0]
Name
VDDQ DAC
Data
Read/Write
Description
110011
Read/Write
Reserved
110100
Read/Write
Reserved
110101
Read/Write
Reserved
110110
Read/Write
Reserved
110111
Read/Write
Reserved
111000
Read/Write
Reserved
111001
Read/Write
Reserved
111010
Read/Write
Reserved
111011
Read/Write
Reserved
111100
Read/Write
Reserved
111101
Read/Write
Reserved
111110
Read/Write
Reserved
111111
Read/Write
IC Shutdown
REGISTER Address:04h
Bit
Name
Data
Read/Write
[7:2]
Reserve
-
-
No Used
00
Read/Write
10mV/µs
01
Read/Write
15mV/µs
10
Read/Write
20mV/µs
11
Read/Write
25mV/µs
[1:0]
VDDQ Slew Rate
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22
Description
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APW8871
Package Information
TQFN4x4-26
A
E
b
D
Pin 1
A1
A3 NX
k2
aaa C
E2
E1
e
Pin 1 Corner
k1 D2 k L
D1
S
Y
M
B
O
L
A
A1
TQFN4x4-26
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.031
0.05
0.000
0.002
0.00
A3
0.11 REF
b
0.15
0.25
0.004 REF
0.006
0.010
D
3.90
4.10
0.154
0.161
D1
0.90
1.10
0.035
0.043
0.024
D2
E
0.40
0.60
0.016
3.90
4.10
0.154
0.161
E1
1.85
2.05
0.073
0.081
E2
2.07
2.27
0.081
0.089
e
0.40 BSC
0.45
0.016 BSC
0.014
0.018
L
0.35
k
0.327
0.427
0.013
0.017
k1
0.317
0.417
0.012
0.016
k2
0.66
0.76
0.026
aaa
C opyright  ANPEC Electronics C orp.
Rev. A.1 - Sep., 2015
0.08
0.030
0.003
23
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APW8871
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN4x4-26
A
H
T1
C
d
D
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±
0.20
4.30±
0.20
1.30±0.20
4.0±0.10
8.0±
0.10
W
E1
12.0±
0.30 1.75±0.10
F
5.5±0.05
(mm)
Devices Per Unit
Package Type
TQFN4x4-26
Unit
Tape & Reel
C opyright  ANPEC Electronics C orp.
Rev. A.1 - Sep., 2015
Quantity
3000
24
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APW8871
Taping Direction Information
TQFN4x4-26
USER DIRECTION OF FEED
Classification Profile
C opyright  ANPEC Electronics C orp.
Rev. A.1 - Sep., 2015
25
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APW8871
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
20** seconds
30** seconds
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin )
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (T L)
Time at liquidous (tL)
Peak package body Temperature
(Tp )*
Time (t P)** within 5 °C of the specified
classification temperature (Tc)
Average ramp-down rate (T p to Tsmax)
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp ) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
C opyright  ANPEC Electronics C orp.
Rev. A.1 - Sep., 2015
26
Description
°
5 Sec, 245 C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150 °C
VHBM≧2KV
VMM ≧200V
10ms, 1 tr ≧100mA
www.anpec.com.tw
APW8871
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
C opyright  ANPEC Electronics C orp.
Rev. A.1 - Sep., 2015
27
www.anpec.com.tw