CY7C1386KV33
CY7C1387KV33
18-Mbit (512K × 36/1M × 18)
Pipelined DCD Sync SRAM
18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Features
Functional Description
■
Supports bus operation up to 200 MHz
■
Available speed grades are 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
Optimal for performance (double-cycle deselect)
■
Depth expansion without wait state
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 3 ns (for 200 MHz device)
■
Provides high performance 3-1-1-1 access rate
■
User selectable burst counter supporting interleaved or linear
burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
CY7C1386KV33 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1387KV33 available in JEDEC-standard Pb-free
100-pin TQFP
■
ZZ sleep mode option
The CY7C1386KV33/CY7C1387KV33 SRAM integrates
512K × 36/1M × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE1), depth expansion chip
enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and
ADV), write enables (BWX, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Configurations on page 5 and Truth Table on
page 9 for further details). Write cycles can be one to four bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing
system performance.
The CY7C1386KV33/CY7C1387KV33 operates from a +3.3 V
core power supply while all outputs operate with a +3.3 V or
+2.5 V supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
Selection Guide
Description
200 MHz
Maximum access time
Maximum operating current
Cypress Semiconductor Corporation
Document Number: 001-97893 Rev. *E
•
198 Champion Court
•
167 MHz
Unit
ns
3.0
3.4
× 18
158
143
× 36
178
163
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY7C1386KV33
CY7C1387KV33
Logic Block Diagram – CY7C1386KV33
A0,A1,A
ADDRESS
REGISTER
2 A[1:0]
MODE
ADV
CLK
BURST
Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
BW D
DQ D, DQP D
BYTE
WRITE REGISTER
DQ D, DQP D
BYTE
WRITE DRIVER
BW C
DQ c ,DQP C
BYTE
WRITE REGISTER
DQ c ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQP C
DQP D
E
DQ A, DQP A
BYTE
WRITE DRIVER
DQ A, DQP A
BYTE
WRITE REGISTER
ENABLE
REGISTER
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
CONTROL
Document Number: 001-97893 Rev. *E
Page 2 of 23
CY7C1386KV33
CY7C1387KV33
Logic Block Diagram – CY7C1387KV33
A0, A1, A
ADDRESS
REGISTER
2
MODE
ADV
CLK
A [1:0]
Q1
BURST
COUNTER AND
CLR
Q0
ADSC
ADSP
BW B
BW A
BWE
CE 1
CE 2
CE 3
DQ B , DQP B
BYTE
DQ B, DQP B
BYTE
WRITE REGISTER
DQ A, DQP A
BYTE
DQ A , DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQ s,
DQP A
DQP B
E
INPUT
REGISTERS
OE
SLEEP
CONTROL
Document Number: 001-97893 Rev. *E
Page 3 of 23
CY7C1386KV33
CY7C1387KV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
Truth Table for Read/Write ............................................ 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
Neutron Soft Error Immunity ......................................... 11
Electrical Characteristics ............................................... 11
Document Number: 001-97893 Rev. *E
Capacitance .................................................................... 13
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Page 4 of 23
CY7C1386KV33
CY7C1387KV33
Pin Configurations
NC
NC
NC
CY7C1387KV33
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1386KV33
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
A
A
A
A
A
A
A
A
A
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enable)
Document Number: 001-97893 Rev. *E
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
Page 5 of 23
CY7C1386KV33
CY7C1387KV33
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress inputs used to select one of the address locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
BWA, BWB,
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC, BWD Synchronous on the rising edge of CLK.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an
internal pull down.
DQs,
DQPX
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
I/O Ground
Ground for the I/O circuitry.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
Document Number: 001-97893 Rev. *E
Page 6 of 23
CY7C1386KV33
CY7C1387KV33
Pin Definitions (continued)
Name
I/O
Description
MODE
InputStatic
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull up.
NC
–
No Connects. Not internally connected to the die.
NC/(36M,
72M,
144M,
288M,
576M, 1G)
–
These pins are not connected. They are used for expansion up to 36M, 72M, 144M, 288M, 576M, and
1G densities.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1386KV33/CY7C1387KV33 supports secondary
cache in systems using either a linear or interleaved burst
sequence. The linear burst sequence is suited for processors
that use a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Synchronous chip selects CE1, CE2, CE3 and an asynchronous
output enable (OE) provide for easy bank selection and output
tristate control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals (GW,
BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH.
The address presented to the address inputs is stored into the
address advancement logic and the address register while being
presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and onto the data bus within tCO if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
Document Number: 001-97893 Rev. *E
The CY7C1386KV33/CY7C1387KV33 is a double cycle
deselect part. After the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output tristates
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BWX) and ADV inputs are ignored during this first
cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
HIGH, the write operation is controlled by BWE and BWX signals.
The CY7C1386KV33/CY7C1387KV33 provides byte write
capability that is described in the write cycle description table.
Asserting the byte write enable input (BWE) with the selected
byte write input, selectively writes to the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided to
simplify the write operations.
The CY7C1386KV33/CY7C1387KV33 is a common I/O device,
the output enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. This tristates the output drivers.
As a safety precaution, DQ are automatically tristated whenever
a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
combination of the write inputs (GW, BWE, and BWX) are
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
Page 7 of 23
CY7C1386KV33
CY7C1387KV33
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation remains
unaltered. A synchronous self timed write mechanism has been
provided to simplify the write operations.
deselected prior to entering the sleep mode. CEs, ADSP, and
ADSC must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
The CY7C1386KV33/CY7C1387KV33 is a common I/O device,
the output enable (OE) must be deasserted HIGH before
presenting data to the DQX inputs. This tristates the output
drivers. As a safety precaution, DQX are automatically tristated
whenever a write cycle is detected, regardless of the state of OE.
(MODE = Floating or VDD)
Interleaved Burst Address Table
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
Burst Sequences
01
00
11
10
The CY7C1386KV33/CY7C1387KV33 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence.The burst sequence is user
selectable through the MODE input.
10
11
00
01
11
10
01
00
Linear Burst Address Table
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
(MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ Active to sleep current
tRZZI
ZZ Inactive to exit sleep current
Document Number: 001-97893 Rev. *E
Min
Max
Unit
–
65
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
This parameter is sampled
0
–
ns
Page 8 of 23
CY7C1386KV33
CY7C1387KV33
Truth Table
The Truth Table for CY7C1386KV33 and CY7C1387KV33 follow. [1, 2, 3, 4, 5]
Operation
Add. Used CE1 CE2 CE3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = Do not care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-97893 Rev. *E
Page 9 of 23
CY7C1386KV33
CY7C1387KV33
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1386KV33 follows. [6, 7]
Function (CY7C1386KV33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Truth Table for Read/Write
The Truth Table for Read/Write for CY7C1387KV33 follows. [6, 7]
Function (CY7C1387KV33)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Notes
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid appropriate write is done based on which byte write is active.
Document Number: 001-97893 Rev. *E
Page 10 of 23
CY7C1386KV33
CY7C1387KV33
Maximum Ratings
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0 °C to +70 °C
3.3 V– 5% /
+10%
2.5 V – 5% to
VDD
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Neutron Soft Error Immunity
Parameter
LSBU
(Device
without
ECC)
Description
Max*
Unit
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
Logical
Multi-Bit
Upsets
25 °C
0
0.01
FIT/
Mb
Single Event
Latch up
85 °C
0
0.1
FIT/
Dev
LMBU
Latch-up current .................................................... > 200 mA
SEL
Test
Conditions Typ
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [8, 9]
Min
Max
Unit
VDD
Power Supply Voltage
–
3.135
3.6
V
VDDQ
I/O Supply Voltage
for 3.3 V I/O
3.135
VDD
V
for 2.5 V I/O
2.375
2.625
V
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
VOH
VOL
VIH
VIL
IX
Description
Output HIGH Voltage
Output LOW Voltage
[8]
Input HIGH Voltage
for 3.3 V I/O
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input Leakage Current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input Current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input = VSS
–5
–
A
Input = VDD
–
30
A
GND VI VDDQ, Output Disabled
–5
5
A
Input LOW Voltage
[8]
Input Current of ZZ
IOZ
Test Conditions
Output Leakage Current
Notes
8. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ <VDD.
Document Number: 001-97893 Rev. *E
Page 11 of 23
CY7C1386KV33
CY7C1387KV33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [8, 9]
IDD
ISB1
ISB2
ISB3
ISB4
Description
VDD Operating Supply
Automatic CE Power-down
Current – TTL Inputs
Test Conditions
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Min
Max
Unit
mA
5-ns cycle,
200 MHz
× 18
–
180
× 36
–
200
6-ns cycle,
167 MHz
× 18
–
158
× 36
–
178
5-ns cycle,
200 MHz
× 18
–
75
× 36
–
80
6-ns cycle,
167 MHz
× 18
–
75
× 36
–
80
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f=0
All speed
grades
× 18
–
65
× 36
–
70
Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
× 18
–
75
× 36
–
80
6-ns cycle,
167 MHz
× 18
–
75
× 36
–
80
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f=0
All speed
grades
× 18
–
65
× 36
–
70
Automatic CE Power-down
Current – TTL Inputs
Document Number: 001-97893 Rev. *E
mA
mA
mA
mA
Page 12 of 23
CY7C1386KV33
CY7C1387KV33
Capacitance
Parameter
100-pin TQFP
Package
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test With Still Air (0 m/s)
methods and procedures for
With Air Flow (1 m/s)
measuring thermal impedance, per
EIA/JESD51.
With Air Flow (3 m/s)
37.95
C/W
33.19
C/W
Description
Test Conditions
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
Input/Output capacitance
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
Thermal Resistance
Parameter
JA
Description
Thermal resistance
(junction to ambient)
JB
Thermal resistance
(junction to board)
JC
Thermal resistance
(junction to case)
--
30.44
C/W
24.07
C/W
8.36
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50
Z0 = 50
Document Number: 001-97893 Rev. *E
INCLUDING
JIG AND
SCOPE
1 ns
1 ns
(c)
ALL INPUT PULSES
VDDQ
GND
5 pF
R = 1538
(b)
90%
10%
90%
(b)
VT = 1.25 V
(a)
10%
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 13 of 23
CY7C1386KV33
CY7C1387KV33
Switching Characteristics
Over the Operating Range
Parameter [10, 11]
tPOWER
Description
VDD(typical) to the first access [12]
-200
-167
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.2
–
ns
tCL
Clock LOW
2.0
–
2.2
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.3
–
ns
1.3
–
1.3
–
ns
–
3.0
–
3.4
ns
–
3.0
–
3.4
ns
0
–
0
–
ns
–
3.0
–
3.4
ns
[13, 14, 15]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [13, 14, 15]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[13, 14, 15]
OE HIGH to output high Z
[13, 14, 15]
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.4
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.4
–
0.5
–
ns
Hold Times
Notes
10. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
11. Test conditions shown in (a) of Figure 2 on page 13 unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of Figure 2 on page 13. Transition is measured ±200 mV from steady-state voltage.
14. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high Z
prior to low Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document Number: 001-97893 Rev. *E
Page 14 of 23
CY7C1386KV33
CY7C1387KV33
Switching Waveforms
Figure 3. Read Cycle Timing [16]
tCYC
CLK
tCH
tCL
tADS tADH
ADSP
tADS
tADH
ADSC
tAS
ADDRESS
tAH
A1
A2
A3
Burst continued with
new base address
tWES tWEH
GW, BWE,BW
X
Deselect
cycle
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
Data Out (DQ)
High-Z
CLZ
t OEHZ
Q(A1)
tOEV
tCO
t OELZ
tDOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-97893 Rev. *E
Page 15 of 23
CY7C1386KV33
CY7C1387KV33
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [17, 18]
t CYC
CLK
tCH
tADS
tCL
tADH
ADSP
tADS
ADSC extends burst
tADH
tADS tADH
ADSC
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
tWES tWEH
BWE,
BWX
tWES tWEH
GW
tCES tCEH
CE
tADVS tADVH
ADV
ADV suspends burst
OE
t
t
DS DH
Data in (D)
High-Z
t
OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
Document Number: 001-97893 Rev. *E
Page 16 of 23
CY7C1386KV33
CY7C1387KV33
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [19, 20, 21]
tCYC
CLK
tCL
tCH
tADS
tADH
tAS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
D(A5)
D(A6)
tWES tWEH
BWE, BWX
tCES
tCEH
CE
ADV
OE
tDS
tCO
Data In (D)
tOELZ
High-Z
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A3)
Q(A2)
Q(A4)
BURST READ
Single WRITE
DON’T CARE
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
Document Number: 001-97893 Rev. *E
Page 17 of 23
CY7C1386KV33
CY7C1387KV33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [22, 23]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-97893 Rev. *E
Page 18 of 23
CY7C1386KV33
CY7C1387KV33
Ordering Information
The table below contains only the parts that are currently available. If you do not see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Ordering Code
CY7C1386KV33-167AXC
Package
Diagram
Part and Package Type
Operating
Range
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1387KV33-167AXC
200
CY7C1386KV33-200AXC
Ordering Code Definitions
CY
7
C 13XX K V33 - XXX XX X
X
Temperature range: X = C
C = Commercial = 0 °C to +70 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A
A = 100-pin TQFP
Speed Grade: XXX = 167 MHz or 200 MHz
V33 = 3.3 V VDD
Process Technology: K = 65 nm
Part Identifier: 13XX = 1386 or 1387
1386 = PL, 512Kb × 36 (18Mb)
1387 = PL, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-97893 Rev. *E
Page 19 of 23
CY7C1386KV33
CY7C1387KV33
Package Diagrams
Figure 10. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-97893 Rev. *E
Page 20 of 23
CY7C1386KV33
CY7C1387KV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
k
kilohm
I/O
Input/Output
MHz
megahertz
LMBU
Logical Multiple-Bit Upsets
µA
microampere
LSB
Least Significant Bit
µs
microsecond
LSBU
Logical Single-Bit Upsets
mA
milliampere
MSB
Most Significant Bit
OE
Output Enable
SEL
Single Event Latch-Up
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
Document Number: 001-97893 Rev. *E
Symbol
Unit of Measure
mV
millivolt
mm
millimeter
ms
millisecond
ns
nanosecond
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 21 of 23
CY7C1386KV33
CY7C1387KV33
Document History Page
Document Title: CY7C1386KV33/CY7C1387KV33, 18-Mbit (512K × 36/1M × 18) Pipelined DCD Sync SRAM
Document Number: 001-97893
Revision
ECN
Orig. of
Change
Submission
Date
*B
4983482
DEVM
10/23/2015
Changed status from Preliminary to Final.
*C
5086001
DEVM
01/14/2016
Post to external web.
*D
5333184
PRIT
07/01/2016
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU
parameter.
Updated to new template.
*E
6063404
CNX
02/08/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Document Number: 001-97893 Rev. *E
Description of Change
Page 22 of 23
CY7C1386KV33
CY7C1387KV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
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Wireless Connectivity
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© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-97893 Rev. *E
Revised February 8, 2018
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