LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 LP2987/LP2988 Micropower, 200 mA Ultra Low-Dropout Voltage Regulator with Programmable Power-On Reset Delay; Low Noise Version Available (LP2988) Check for Samples: LP2987, LP2988 FEATURES DESCRIPTION • • The LP2987/8 are fixed-output 200 mA precision LDO voltage regulators with power-ON reset delay which can be implemented using a single external capacitor. 1 2 • • • • • • • • • • Ultra Low Dropout Voltage Power-ON Reset Delay Requires Only One Component Bypass Pin for Reduced Output Noise (LP2988) Specified Continuous Output Current 200 mA Specified Peak Output Current > 250 mA SOIC-8 and VSSOP-8 Surface Mount Packages <2 μA Quiescent Current when Shutdown Low Ground Pin Current at All Loads 0.5% Output Voltage Accuracy (“A” Grade) Wide Supply Voltage Range (16V Max) Overtemperature/overcurrent Protection −40°C to +125°C Junction Temperature Range APPLICATIONS • • • Cellular Phone Palmtop/Laptop Computer Camcorder, Personal Stereo, Camera The LP2988 is specifically designed for noise-critical applications. A single external capacitor connected to the Bypass pin reduces regulator output noise. Using an optimized VIP (Vertically Integrated PNP) process, these regulators deliver superior performance: Dropout Voltage: 180 mV @ 200 mA load, and 1 mV @ 1 mA load (typical). Ground Pin Current: 1 mA @ 200 mA load, and 200 μA @ 10 mA load (typical). Sleep Mode: The LP2987/8 draws less than 2 μA quiescent current when shutdown pin is held low. Error Flag/Reset: The error flag goes low when the output drops approximately 5% below nominal. This pin also provides a power-ON reset signal if a capacitor is connected to the DELAY pin. Precision Output: Standard product versions of the LP2987 and LP2988 are available with output voltages of 5.0V, 3.8V, 3.3V, 3.2V, 3.0V, or 2.8V, with specified accuracy of 0.5% (“A” grade) and 1% (standard grade) at room temperature. Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com Connection Diagram (LP2987) Figure 1. Top View SOIC-8/VSSOP-8 Package Surface Mount Packages See Package Drawing Number D0008A/DGK0008A 8 DELAY 2 7 ERROR GROUND 3 6 SENSE INPUT 4 5 OUTPUT GROUND 1 N/C SHUTDOWN Figure 2. Top View 8-Lead WSON Surface Mount Package See Package Drawing Number NGN0008A Connection Diagram (LP2988) Figure 3. Top View SOIC-8/VSSOP-8 Package Surface Mount Packages See Package Drawing Number D0008A/DGK0008A BYPASS 1 8 SHUTDOWN DELAY 2 7 ERROR GROUND 3 6 SENSE INPUT 4 5 OUTPUT Figure 4. Top View 8-Lead WSON Surface Mount Package See Package Drawing Number NGN0008A 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Storage Temperature Range −65°C to +150°C Operating Junction Temperature Range −40°C to +125°C Lead Temperature (Soldering, 5 seconds) ESD Rating 260°C (3) 2 kV Power Dissipation (4) Internally Limited Input Supply Voltage (Survival) −0.3V to +16V Input Supply Voltage (Operating) 2.1V to +16V −0.3V to +16V Shutdown Pin −0.3V to +6V Sense Pin Output Voltage (Survival) (5) −0.3V to +16V IOUT (Survival) Short Circuit Protected Input-Output Voltage (Survival) (6) (1) (2) (3) (4) (5) (6) −0.3V to +16V Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The ESD rating of the Bypass pin is 500V (LP2988 only). The ESD rating of the VIN pin is 1kV and the Delay pin is ESD rated at 1.5kV. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal resistance, θJ−A, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: The value of θJ−A for the SOIC-8 (D) package is 160°C/W, and the VSSOP-8 (DGK) package is 200°C/W. The value θJ−A for the WSON (NGN) package is specifically dependent on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the WSON package, refer to Application Note AN-1187 (literature number SNOA401). Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. If used in a dual-supply system where the regulator load is returned to a negative supply, the LM2987/8 output must be diode-clamped to ground. The output PNP structure contains a diode between the VIN and VOUT terminals that is normally reverse-biased. Forcing the output above the input will turn on this diode and may induce a latch-up mode which can damage the part (see APPLICATION HINTS). ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V. Symbol ΔVO Parameter Conditions Typical Output Voltage Tolerance 0.1 mA < IL < 200 mA ΔVO/ΔVIN (1) Output Voltage Line Regulation VO(NOM) + 1V ≤ VIN ≤ 16V LM2987/8AI-X.X (1) LM2987/8I-X.X (1) Min Max Min Max −0.5 0.5 −1.0 1.0 −0.8 0.8 −1.6 1.6 −1.8 1.8 −2.8 2.8 0.007 0.014 0.014 0.032 0.032 Units %VNOM %/V Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 3 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V. Symbol VIN–VO Parameter Dropout Voltage (2) Conditions Typical IL = 100 µA 180 IL = 100 µA 100 IL = 75 mA 500 IL = 200 mA (1) Max LM2987/8I-X.X Min 2.0 90 IL = 200 mA Ground Pin Current Min 1 IL = 75 mA IGND LM2987/8AI-X.X 1 (1) Max Units 2.0 3.5 3.5 120 120 170 170 230 230 350 350 120 120 150 150 800 800 1400 1400 2.1 2.1 3.7 3.7 mA VS/D < 0.3V 0.05 Peak Output Current VOUT ≥ VO(NOM) − 5% 400 IO(MAX) Short Circuit Current RL = 0 (Steady State) en LP2987 Output Noise Voltage (RMS) BW = 300 Hz to 50 kHz, VOUT = 3.3V COUT = 10 µF LP2988 Output Noise Voltage (RMS) BW = 300 Hz to 50 kHz, VOUT = 3.3V COUT = 10 µF CBYPASS = .01 µF 20 ΔVOUT/ΔVIN Ripple Rejection f = 1 kHz, COUT = 10 µF CBYP = 0 (LP2988) 65 dB ΔVOUT/ΔT Output Voltage Temperature Coefficient 20 ppm/°C IDELAY Delay Pin Current Source 250 1.5 µA IO(PK) (3) 1.5 mV 250 µA mA 400 100 µV(RMS) (4) 2.2 1.6 2.8 1.6 2.8 1.4 3.0 1.4 3.0 µA SHUTDOWN INPUT VS/D IS/D (2) (3) (4) (5) 4 S/D Input Voltage (5) S/D Input Current VH = O/P ON 1.4 VL = O/P OFF 0.55 1.6 0.18 1.6 0.18 VS/D = 0 0 −1 −1 VS/D = 5V 5 15 15 V µA Dropout voltage is defined as the input to output differential at which the output voltage drops 100 mV below the value measured with a 1V differential. See TYPICAL PERFORMANCE CHARACTERISTICS curves. Temperature coefficient is defined as the maximum (worst-case) change divided by the total temperature range. To prevent mis-operation, the Shutdown input must be driven by a signal that swings above VH and below VL with a slew rate not less than 40 mV/µs (see APPLICATION HINTS). Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, IL = 1 mA, COUT = 4.7 µF, CIN = 2.2 µF, VS/D = 2V. Symbol Parameter Conditions Typical LM2987/8AI-X.X Min Max (1) LM2987/8I-X.X Min (1) Max Units ERROR COMPARATOR IOH VOL Output “HIGH” Leakage Output “LOW” Voltage VTHR (MAX) Upper Threshold Voltage VTHR (MIN) Lower Threshold Voltage HYST Hysteresis VOH = 16V VIN = VO(NOM) − 0.5V, IO(COMP) = 300 µA 0.01 150 −4.6 −6.6 1 1 2 2 220 220 350 350 −5.5 −3.5 −5.5 −3.5 −7.7 −2.5 −7.7 −2.5 −8.9 −4.9 −8.9 −4.9 −13.0 −3.3 −13.0 −3.3 µA mV %VOUT 2.0 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 5 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. 6 VOUT vs Temperature Dropout Voltage vs Temperature Figure 5. Figure 6. Dropout Voltage vs Load Current Dropout Characteristics Figure 7. Figure 8. Ground Pin Current vs Temperature and Load Ground Pin Current vs Load Current Figure 9. Figure 10. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. Input Current vs VIN Input Current vs VIN Figure 11. Figure 12. Load Transient Response Load Transient Response Figure 13. Figure 14. Line Transient Response Line Transient Response Figure 15. Figure 16. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 7 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. 8 Turn-On Waveform Turn-On Waveform Figure 17. Figure 18. Short Circuit Current Short Circuit Current Figure 19. Figure 20. Short Circuit Current vs Output Voltage Instantaneous Short Circuit Current vs Temperature Figure 21. Figure 22. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. DC Load Regulation Shutdown Pin Current vs Shutdown Pin Voltage Figure 23. Figure 24. Shutdown Voltage vs Temperature Input to Output Leakage vs Temperature Figure 25. Figure 26. Delay Pin Current vs VIN Delay Pin Current vs Delay Pin Voltage Figure 27. Figure 28. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 9 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. 10 Delay Sink Current vs Temperature Delay Sink Current vs Temperature Figure 29. Figure 30. Output Impedance vs Frequency Output Impedance vs Frequency Figure 31. Figure 32. Ripple Rejection (LP2987) Ripple Rejection (LP2988) Figure 33. Figure 34. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. Output Noise Density (LP2987) Output Noise Voltage (LP2988) Figure 35. Figure 36. Output Noise Density (LP2988) Output Noise Density (LP2988) Figure 37. Figure 38. Turn-On Time (LP2988) Turn-On Time (LP2988) Figure 39. Figure 40. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 11 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7 µF, CIN = 2.2 µF, S/D is tied to VIN, VIN = VO(NOM) + 1V, IL = 1 mA. Turn-On Time (LP2988) Figure 41. 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 BASIC APPLICATION CIRCUITS Figure 42. *Capacitance value shown is minimum required to assure stability, but may be increased without limit. Larger output capacitor provides improved dynamic response. **Shutdown must be actively terminated (see APPLICATION HINTS). Tie to INPUT (pin 4) if not used. Figure 43. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 13 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com APPLICATION HINTS WSON Package Devices The LP2987/LP2988 is offered in the 8 lead WSON surface mount package to allow for increased power dissipation compared to the SOIC-8 and the VSSOP-8. For details on thermal performance as well as mounting and soldering specifications, refer to Application Note AN-1187 (literature number SNOA401). EXTERNAL CAPACITORS As with any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. INPUT CAPACITOR: An input capacitor (≥ 2.2 µF) is required between the LP2987/8 input and ground (amount of capacitance may be increased without limit). This capacitor must be located a distance of not more than 0.5” from the input pin and returned to a clean analog ground. Any good quality ceramic or tantalum may be used for this capacitor. OUTPUT CAPACITOR: The output capacitor must meet the requirement for minimum amount of capacitance and also have an appropriate E.S.R. (equivalent series resistance) value. Curves are provided which show the allowable ESR range as a function of load current for 3V and 5V outputs. Figure 44. ESR Curves For 5V Output Figure 45. ESR Curves For 3V Output IMPORTANT: The output capacitor must maintain its ESR in the stable region over the full operating temperature range of the application to assure stability. The minimum required amount of output capacitance is 4.7 µF. Output capacitor size can be increased without limit. It is important to remember that capacitor tolerance and variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full operating temperature range. A good Tantalum capacitor will show very little variation with temperature, but a ceramic may not be as good (see next section). The output capacitor should be located not more than 0.5” from the output pin and returned to a clean analog ground. 14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 CAPACITOR CHARACTERISTICS TANTALUM: A solid tantalum capacitor is the best choice for the output capacitor on the LM2987/8. Available from many sources, their typical ESR is very close to the ideal value required on the output of many LDO regulators. Tantalums also have good temperature stability: a 4.7 µF was tested and showed only a 10% decline in capacitance as the temperature was decreased from +125°C to −40°C. The ESR increased only about 2:1 over the same range of temperature. However, it should be noted that the increasing ESR at lower temperatures present in all tantalums can cause oscillations when marginal quality capacitors are used (where the ESR of the capacitor is near the upper limit of the stability range at room temperature). CERAMIC: The ESR of ceramic capacitor can be low enough to cause an LDO regulator to oscillate: a 2.2 µF ceramic was measured and found to have an ESR of 15 mΩ. If a ceramic capacitor is to be used on the LP2987/8 output, a 1Ω resistor should be placed in series with the capacitor to provide a minimum ESR for the regulator. A disadvantage of ceramic capacitors is that their capacitance varies a lot with temperature: Large ceramic capacitors are typically manufactured with the Z5U temperature characteristic, which results in the capacitance dropping by 50% as the temperature goes from 25°C to 80°C. This means you have to buy a capacitor with twice the minimum COUT to assure stable operation up to 80°C. ALUMINUM: The large physical size of aluminum electrolytics makes them unsuitable for most applications. Their ESR characteristics are also not well suited to the requirements of LDO regulators. The ESR of a typical aluminum electrolytic is higher than a tantalum, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of 50X when going from 20°C to −40°C. Also, some aluminum electrolytics can not be used below −25°C because the electrolyte will freeze. POWER-ON RESET DELAY A power-on reset function can be easily implemented using the LP2987/8 by adding a single external capacitor to the Delay pin. The Error output provides the power-on reset signal when input power is applied to the regulator. The reset signal stays low for a pre-set time period after power is applied to the regulator, and then goes high (see Timing Diagram below). Figure 46. Timing Diagram for Power-Up The external capacitor cDLY sets the delay time (TDELAY). The value of capacitor required for a given time delay may be calculated using the formula: CDLY = TDELAY/(5.59 X 105) To simplify design, a plot is provided below which shows values of CDLY versus delay time. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 15 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com Figure 47. Plot of CDLY vs TDELAY DETAILS OF ERR/RESET CIRCUIT OPERATION: (Refer to LP2987/8 Equivalent Circuit). Figure 48. LP2987/8 Equivalent Circuit The output of comparator U2 is the ERR/RESET flag. Since it is an open-collector output, it requires the use of a pull-up resistor (RP). The 1.23V reference is tied to the inverting input of U2, which means that its output is controlled by the voltage applied to the non-inverting input. The output of U1 (also an open-collector) will force the non-inverting input of U2 to go low whenever the LP2987/8 regulated output drops about 5% below nominal. U1's inverting input is also held at 1.23V. The other input samples the regulated output through a resistive divider (RA and RB). When the regulated output is at nominal voltage, the voltage at the divider tap point will be 1.23V. If this voltage drops about 60 mV below 1.23V, the output of U1 will go low forcing the output of U2 low (which is the ERROR state). 16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 Power-ON reset delay occurs when a capacitor (shown as CDLY) is connected to the Delay pin. At turn-ON, this capacitor is initially fully discharged (which means the voltage at the Delay pin is 0V). The output of U1 keeps CDLY fully discharged (by sinking the 2.2 µA from the current source) until the regulator output voltage comes up to within about 5% of nominal. At this point, U1's output stops sinking current and the 2.2 µA starts charging up CDLY. When the voltage across CDLY reaches 1.23V, the output of U2 will go high (note that D1 limits the maximum voltage to about 2V). SELECTING CDLY: The maximum recommended value for this capacitor is 1 µF. The capacitor must not have excessively high leakage current, since it is being charged from a 2.2 µA current source. Aluminum electrolytics can not be used, but good-quality tantalum, ceremic, mica, or film types will work. SHUTDOWN INPUT OPERATION The LP2987/8 is shut off by driving the Shutdown input low, and turned on by pulling it high. If this feature is not to be used, the Shutdown input should be tied to VIN to keep the regulator output on at all times. To assure proper operation, the signal source used to drive the Shutdown input must be able to swing above and below the specified turn-on/turn-off voltage thresholds listed as VH and VL, respectively (see Electrical Characteristics). It is also important that the turn-on (and turn-off) voltage signals applied to the Shutdown input have a slew rate which is not less than 40 mV/µs. CAUTION The regulator output state can not be ensured if a slow-moving AC (or DC) signal is applied that is in the range between VH and VL. REVERSE INPUT-OUTPUT VOLTAGE The PNP power transistor used as the pass element in the LP2987/8 has an inherent diode connected between the regulator output and input. During normal operation (where the input voltage is higher than the output) this diode is reverse-biased. However, if the output is pulled above the input, this diode will turn ON and current will flow into the regulator output. In such cases, a parasitic SCR can latch which will allow a high current to flow into VIN (and out the ground pin), which can damage the part. In any application where the output may be pulled above the input, an external Schottky diode must be connected from VIN to VOUT (cathode on VIN, anode on VOUT), to limit the reverse voltage across the LP2987/8 to 0.3V (see Absolute Maximum Ratings). Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 17 LP2987, LP2988 SNVS004J – MARCH 1999 – REVISED APRIL 2013 www.ti.com BYPASS CAPACITOR (LP2988) The capacitor connected to the Bypass pin must have very low leakage. The current flowing out of the Bypass pin comes from the Bandgap reference, which is used to set the output voltage. Since the Bandgap circuit has only a few microamps flowing in it, loading effects due to leakage current will cause a change in the regulated output voltage. Curves are provided which show the effect of loading the Bypass pin on the regulated output voltage. Care must be taken to ensure that the capacitor selected for bypass will not have significant leakage current over the operating temperature range of the application. A high quality ceramic capacitor which uses either NPO or COG type dielectiric material will typically have very low leakage. Small surface-mount polypropolene or polycarbonate film capacitors also have extremely low leakage, but are slightly larger in size than ceramics. 18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 LP2987, LP2988 www.ti.com SNVS004J – MARCH 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision I (April 2013) to Revision J • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LP2987 LP2988 19 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP2987AILD-3.0/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L007A LP2987AILD-5.0/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L009A LP2987AILDX-5.0/NOPB ACTIVE WSON NGN 8 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L009A LP2987AIMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L44A LP2987AIMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987A IM5.0 LP2987ILD-3.3/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L008A B LP2987IM-3.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987I M3.0 LP2987IM-3.3/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987I M3.3 LP2987IM-5.0 NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2987I M5.0 LP2987IM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987I M5.0 LP2987IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L43B LP2987IMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L44B LP2987IMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L43B LP2987IMX-3.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987I M3.0 LP2987IMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2987I M5.0 LP2988AIM-5.0 NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 2988A IM5.0 LP2988AIM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2988A IM5.0 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 8-Oct-2015 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP2988AIMM-2.8/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L0IA LP2988AIMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L49A LP2988AIMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L50A LP2988AIMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L51A LP2988AIMX-3.3/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2988A IM3.3 LP2988ILD-3.8/NOPB ACTIVE WSON NGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 L083A B LP2988IM-5.0/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2988I M5.0 LP2988IMM-2.8/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L0IB LP2988IMM-3.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L49B LP2988IMM-3.3/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L50B LP2988IMM-5.0 NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 L51B LP2988IMM-5.0/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L51B LP2988IMMX-3.0/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L49B LP2988IMMX-3.3/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L50B LP2988IMX-5.0/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 2988I M5.0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2987AILD-3.0/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2987AILD-5.0/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2987AILDX-5.0/NOPB WSON NGN 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2987AIMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2987AIMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2987ILD-3.3/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2987IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2987IMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2987IMMX-3.3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2987IMX-3.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2987IMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2988AIMM-2.8/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988AIMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988AIMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988AIMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988AIMX-3.3/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LP2988ILD-3.8/NOPB WSON NGN 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LP2988IMM-2.8/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP2988IMM-3.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMM-3.3/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMM-5.0 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMM-5.0/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMMX-3.0/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMMX-3.3/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LP2988IMX-5.0/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2987AILD-3.0/NOPB WSON NGN 8 1000 213.0 191.0 55.0 LP2987AILD-5.0/NOPB WSON NGN 8 1000 213.0 191.0 55.0 LP2987AILDX-5.0/NOPB WSON NGN 8 4500 367.0 367.0 35.0 LP2987AIMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2987AIMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2987ILD-3.3/NOPB WSON NGN 8 1000 213.0 191.0 55.0 LP2987IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2987IMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2987IMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2987IMX-3.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2015 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP2987IMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2988AIMM-2.8/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988AIMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988AIMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988AIMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988AIMX-3.3/NOPB SOIC D 8 2500 367.0 367.0 35.0 LP2988ILD-3.8/NOPB WSON NGN 8 1000 213.0 191.0 55.0 LP2988IMM-2.8/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988IMM-3.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988IMM-3.3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988IMM-5.0 VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988IMM-5.0/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LP2988IMMX-3.0/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2988IMMX-3.3/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LP2988IMX-5.0/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 3 MECHANICAL DATA NGN0008A LDC08A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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