TI1 OPA2836QDGKRQ1 Very-low power, rail-to-rail out, negative-rail in, voltage-feedback operational amplifier Datasheet

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OPA2836-Q1
SBOS794 – DECEMBER 2016
OPA2836-Q1 Very-Low Power, Rail-to-Rail Out, Negative-Rail In, Voltage-Feedback
Operational Amplifier
1 Features
3 Description
•
•
The OPA2836-Q1 device is a dual-channel, ultra-low
power, rail-to-rail output, negative-rail input, voltagefeedback operational amplifier designed to operate
over a power-supply range of 2.5 V to 5.5 V (single
supply), or ±1.25 V to ±2.75 V (dual supply).
Consuming only 1 mA per channel with a unity-gain
bandwidth of 205 MHz, this amplifier sets an industryleading, power-to-performance ratio for rail-to-rail
amplifiers.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM Classification Level 2
– Device CDM Classification Level C6
Low Power:
– Supply Voltage: 2.5 V to 5.5 V
– Quiescent Current: 1 mA (Typ)
– Power-Down Mode: 0.5 µA Typ)
Bandwidth: 205 MHz
Slew Rate: 560 V/µs
Rise Time: 3 ns (2 VSTEP)
Settling Time (0.1%): 22 ns (2 VSTEP)
Overdrive Recovery Time: 60 ns
SNR: 0.00013% (–117.6 dBc) at 1 kHz (1 VRMS)
THD: 0.00003% (–130 dBc) at 1 kHz (1 VRMS)
HD2, HD3: –85 dBc, –105 dBc at 1 MHz (2 VPP)
Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz)
Input Offset Voltage: 65 µV (±400-µV Max)
CMRR: 116 dB
Output Current Drive: 50 mA
RRO: Rail-to-Rail Output
Input Voltage Range: –0.2 V to +3.9 V
(5-V Supply)
For battery-powered, portable applications where
power is a key importance, the low-power
consumption and high-frequency performance of the
OPA2836-Q1 offers designers performance-versuspower that is not attainable in other devices.
The OPA2836-Q1 is characterized for operation over
the extended industrial temperature range of –40°C
to +125°C.
Device Information(1)
PART NUMBER
OPA2836-Q1
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Harmonic Distortion vs Frequency
-40
VS = 2.7 V,
-50 G = 1,
VOUT = 1 Vpp,
-60 R = 0 W,
2 Applications
•
•
•
•
•
•
Low-Power Signal Conditioning
Audio ADC Input Buffers
Low-Power SAR and ΔΣ ADC Drivers
Portable Systems
Low-Power Systems
High-Density Systems
Harmonic Distortion - dBc
F
-70
RL = 1 kW
-80
-90
HD2
-100
-110
HD3
-120
-130
-140
10k
100k
1M
10M
f - Frequency - Hz
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2836-Q1
SBOS794 – DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
OPA2836-Q1 Related Devices ..............................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = 2.7 V........................
Electrical Characteristics: VS = 5 V...........................
Typical Characteristics ..............................................
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Applications ................................................ 34
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 39
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description ............................................ 21
8.1 Overview ................................................................. 21
8.2 Functional Block Diagrams ..................................... 21
8.3 Feature Description................................................. 21
Device Support ....................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
39
39
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
2
DATE
REVISION
NOTES
December 2016
*
Initial release.
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SBOS794 – DECEMBER 2016
5 OPA2836-Q1 Related Devices
BW (AV = 1)
(MHz)
SLEW RATE
(V/µs)
IQ (5 V)
(mA)
INPUT NOISE
(nV/√Hz)
RAIL-TO-RAIL IN/OUT
DUALS
OPA836
205
560
1
4.6
–VS/Out
OPA2836
OPA835
30
110
0.25
9.3
–VS/Out
OPA2835
OPA365
50
25
5
4.5
In/Out
OPA2365
THS4281
95
35
0.75
12.5
In/Out
—
LMH6618
140
45
1.25
10
In/Out
LMH6619
OPA830
310
600
3.9
9.5
–VS/Out
OPA2830
DEVICE
For a complete selection of TI high-speed amplifiers, visit www.ti.com.
6 Pin Configuration and Functions
DGK Package
8-Pin VSSOP
Top View
VOUT1
1
VIN1-
2
VIN1+
3
VS-
4
+
+
8
VS+
7
VOUT2
6
VIN2-
5
VIN2+
Pin Functions
NAME
PIN
I/O
VIN1+
3
Input
Amplifier 1 noninverting input
DESCRIPTION
VIN1–
2
Input
Amplifier 1 inverting input
VIN2+
5
Input
Amplifier 2 noninverting input
VIN2–
6
Input
Amplifier 2 inverting input
VOUT1
1
Output
Amplifier 1 output
VOUT2
7
Output
Amplifier 2 output
VS+
8
Power
Positive power supply input
VS–
4
Power
Negative power supply input
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
5.5
V
VS+ + 0.7
V
VS– to VS+
Supply voltage
VI
Input voltage
VID
Differential input voltage
1
V
II
Continuous input current
0.85
mA
IO
Continuous output current
60
mA
VS– – 0.7
Continuous power dissipation
TJ
Maximum junction temperature
TA
Operating free-air temperature
Tstg
Storage temperature
(1)
See Thermal Information
150
°C
–40
125
°C
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±6000
Charged-device model (CDM), per AEC Q100-011
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VS+
Single supply voltage
2.5
5
5.5
UNIT
V
TA
Ambient temperature
–40
25
125
°C
7.4 Thermal Information
OPA2836-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
177.7
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
69.3
°C/W
RθJB
Junction-to-board thermal resistance
98.8
°C/W
ψJT
Junction-to-top characterization parameter
11.7
°C/W
ψJB
Junction-to-board characterization parameter
97.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS794 – DECEMBER 2016
7.5 Electrical Characteristics: VS = 2.7 V
test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output
referenced to mid-supply, VIN_CM = mid-supply – 0.5 V; TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
VOUT = 100 mVPP, G = 1
200
VOUT = 100 mVPP, G = 2
100
VOUT = 100 mVPP, G = 5
26
VOUT = 100 mVPP, G = 10
11
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
110
MHz
C
Large-signal bandwidth
VOUT = 1 VPP, G = 2
60
MHz
C
Bandwidth for 0.1-dB flatness
VOUT = 1 VPP, G = 2
25
MHz
C
Slew rate, rise
VOUT = 1 VSTEP, G = 2
260
V/µs
C
Slew rate, fall
VOUT = 1 VSTEP, G = 2
240
V/µs
C
Rise time
VOUT = 1 VSTEP, G = 2
4
ns
C
Fall time
VOUT = 1 VSTEP, G = 2
4.5
ns
C
Settling time to 1%, rise
VOUT = 1 VSTEP, G = 2
15
ns
C
Settling time to 1%, fall
VOUT = 1 VSTEP, G = 2
15
ns
C
Settling time to 0.1%, rise
VOUT = 1 VSTEP, G = 2
30
ns
C
Settling time to 0.1%, fall
VOUT = 1 VSTEP, G = 2
25
ns
C
Settling time to 0.01%, rise
VOUT = 1 VSTEP, G = 2
50
ns
C
Settling time to 0.01%, fall
VOUT = 1 VSTEP, G = 2
45
ns
C
Overshoot
VOUT = 1 VSTEP, G = 2
5%
C
Undershoot
VOUT = 1 VSTEP, G = 2
3%
C
Small-signal bandwidth
Second-order harmonic distortion
Third-order harmonic distortion
f = 10 kHz, VIN_CM = mid-supply – 0.5 V
–133
f = 100 kHz, VIN_CM = mid-supply – 0.5 V
–120
f = 1 MHz, VIN_CM = mid-supply – 0.5 V
–84
f = 10 kHz, VIN_CM = mid-supply – 0.5 V
–137
f = 100 kHz, VIN_CM = mid-supply – 0.5 V
–130
f = 1 MHz, VIN_CM = mid-supply – 0.5 V
–105
C
MHz
C
C
C
C
dBc
C
C
C
dBc
C
C
Second-order intermodulation distortion
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V
–90
dBc
C
Third-order intermodulation distortion
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 1 VPP,
VIN_CM = mid-supply – 0.5 V
–90
dBc
C
Input voltage noise
f = 100 kHz
Voltage noise 1/f corner frequency
Input current noise
f = 1 MHz
Current noise 1/f corner frequency
4.6
nV/√Hz
C
215
Hz
C
0.75
pA/√Hz
C
31.7
kHz
C
Overdrive recovery time
Overdrive = 0.5 V
55
ns
C
Underdrive recovery time
Underdrive = 0.5 V
60
ns
C
Closed-loop output impedance
f = 100 kHz
0.02
Ω
C
Channel-to-channel crosstalk
f = 10 kHz
–120
dB
C
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
Input-referred offset voltage
Input offset voltage drift (2)
(1)
(2)
100
125
TA = 25°C
–400
±65
TA = –40°C to +85°C
–760
760
TA = –40°C to +125°C
–1060
1060
TA = –40°C to +85°C
TA = –40°C to +125°C
400
–6
±1
6
–6.6
±1.1
6.6
A
µV
B
B
µV/°C
B
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
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Electrical Characteristics: VS = 2.7 V (continued)
test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output
referenced to mid-supply, VIN_CM = mid-supply – 0.5 V; TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
TEST
LEVEL (1)
MIN
TYP
MAX
TA = 25°C
200
650
1000
TA = –40°C to +85°C
120
1500
TA = –40°C to +125°C
100
1800
TA = –40°C to +85°C
–1.9
±0.32
1.9
TA = –40°C to +125°C
–3.5
±0.37
2.1
TA = 25°C
–180
±30
180
TA = –40°C to +85°C
–215
±30
215
TA = –40°C to +125°C
–240
±30
240
TA = –40°C to +85°C
–575
±95
575
TA = –40°C to +125°C
–600
±100
600
TA = 25°C,
< 3-dB degradation in CMRR limit
–0.2
0
V
A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit
–0.2
0
V
B
DC PERFORMANCE (continued)
Input bias current (3)
Input bias current drift (2)
Input offset current
Input offset current drift (2)
A
nA
B
B
nA/°C
B
B
A
nA
B
B
pA/°C
B
B
INPUT
Common-mode input range, low
Common-mode input range, high
Input linear operating voltage range
TA = 25°C,
< 3-dB degradation in CMRR limit
1.5
1.6
V
A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit
1.5
1.6
V
B
–0.3 to
1.75
V
C
TA = 25°C,
< 6-dB degradation in THD
Common-mode rejection ratio
91
Input impedance common-mode
Input impedance differential mode
dB
A
200 || 1.2
114
kΩ || pF
C
200 || 1
kΩ || pF
C
OUTPUT
Output voltage, low
Output voltage, high
TA = 25°C, G = 5
0.15
0.2
V
A
TA = –40°C to +125°C, G = 5
0.15
0.2
V
B
A
TA = 25°C, G = 5
2.45
2.5
V
TA = –40°C to +125°C, G = 5
2.45
2.5
V
B
80
mV
C
Output saturation voltage, high
TA = 25°C, G = 5
Output saturation voltage, low
TA = 25°C, G = 5
Output current drive
40
mV
C
TA = 25°C
±40
±45
mA
A
TA = –40°C to +125°C
±40
±45
mA
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current per amplifier
2.5
TA = 25°C
0.7
TA = –40°C to +125°C
0.6
Power-supply rejection ratio (±PSRR)
(3)
6
91
0.95
108
5.5
V
B
1.15
mA
A
1.6
mA
B
dB
A
Current is considered positive out of the pin.
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7.6 Electrical Characteristics: VS = 5 V
test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 1 kΩ, G = 1 V/V, input and output
referenced to mid-supply; TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
Small-signal bandwidth
VOUT = 100 mVPP, G = 1
205
VOUT = 100 mVPP, G = 2
100
VOUT = 100 mVPP, G = 5
28
C
MHz
C
C
VOUT = 100 mVPP, G = 10
11.8
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
118
MHz
C
Large-signal bandwidth
VOUT = 2 VPP, G = 2
87
MHz
C
Bandwidth for 0.1-dB flatness
VOUT = 2 VPP, G = 2
29
MHz
C
Slew rate, rise
VOUT = 2-V step, G = 2
560
V/µs
C
Slew rate, fall
VOUT = 2-V step, G = 2
580
V/µs
C
Rise time
VOUT = 2-V step, G = 2
3
ns
C
Fall time
VOUT = 2-V Step, G = 2
3
ns
C
Settling time to 1%, rise
VOUT = 2-V step, G = 2
22
ns
C
Settling time to 1%, fall
VOUT = 2-V step, G = 2
22
ns
C
Settling time to 0.1%, rise
VOUT = 2-V step, G = 2
30
ns
C
Settling time to 0.1%, fall
VOUT = 2-V step, G = 2
30
ns
C
Settling time to 0.01%, rise
VOUT = 2-V step, G = 2
40
ns
C
Settling time to 0.01%, fall
VOUT = 2-V step, G = 2
45
ns
C
Overshoot
VOUT = 2-V step, G = 2
7.5%
C
Undershoot
VOUT = 2-V step, G = 2
5%
C
Second-order harmonic distortion
Third-order harmonic distortion
f = 10 kHz
–133
f = 100 kHz
–120
f = 1 MHz
–85
f = 10 kHz
–140
f = 100 kHz
–130
f = 1 MHz
–105
C
C
dBc
C
C
C
dBc
C
C
Second-order intermodulation distortion
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 2 VPP
–79
dBc
C
Third-order intermodulation distortion
f = 1 MHz, 200-kHz tone spacing,
VOUT envelope = 2 VPP
–91
dBc
C
Signal-to-noise ratio (SNR)
f = 1 kHz, VOUT = 1 VRMS,
22-kHz bandwidth
Total harmonic distortion (THD)
f = 1 kHz, VOUT = 1 VRMS
Input voltage noise
f = 100 KHz
0.00013%
dBc
0.00003%
f > 1 MHz
Current noise 1/f corner frequency
C
C
–130
Voltage noise 1/f corner frequency
Input current noise
C
–117.6
dBc
C
4.6
nV/√Hz
C
215
Hz
C
0.75
pA/√Hz
C
31.7
kHz
C
Overdrive recovery time
Overdrive = 0.5 V
55
ns
C
Underdrive recovery time
Underdrive = 0.5 V
60
ns
C
Closed-loop output impedance
f = 100 kHz
0.02
Ω
C
Channel-to-channel crosstalk
f = 10 kHz
–120
dB
C
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
TA = 25°C
Input-referred offset voltage
(1)
100
122
–400
±65
A
400
TA = –40°C to +85°C
–765
765
TA = –40°C to +125°C
–1080
1080
µV
B
B
Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
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Electrical Characteristics: VS = 5 V (continued)
test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 1 kΩ, G = 1 V/V, input and output
referenced to mid-supply; TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
DC PERFORMANCE (continued)
Input offset voltage drift (2)
Input bias current
(3)
Input bias current drift (2)
Input offset current
Input offset current drift (2)
TA = –40°C to +85°C
–6.1
±1
6.1
TA = –40°C to +125°C
–6.8
±1.1
6.8
TA = 25°C
200
650
1000
TA = –40°C to +85°C
120
1550
TA = –40°C to +125°C
100
1850
µV/°C
B
B
A
nA
B
B
TA = –40°C to +85°C
±0.34
±2
TA = –40°C to +125°C
±0.38
±3.8
TA = 25°C
±30
±180
TA = –40°C to +85°C
±30
±215
TA = –40°C to +125°C
±30
±250
TA = –40°C to +85°C
±100
±600
TA = –40°C to +125°C
±110
±660
TA = 25°C,
< 3-dB degradation in CMRR limit
–0.2
0
V
A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit
–0.2
0
V
B
nA/°C
B
B
A
nA
B
B
pA/°C
B
B
INPUT
Common-mode input range low
Common-mode input range high
Input linear operating voltage range
TA = 25°C,
< 3-dB degradation in CMRR limit
3.8
3.9
V
A
TA = –40°C to 125°C,
< 3-dB degradation in CMRR limit
3.8
3.9
V
B
–0.3 to
4.05
V
C
TA = 25°C,
< 6-dB degradation in THD
Common-mode rejection ratio
94
Input impedance common mode
Input impedance differential mode
dB
A
200 || 1.2
116
kΩ || pF
C
200 || 1
kΩ || pF
C
OUTPUT
Output voltage low
Output voltage high
TA = 25°C, G = 5
0.15
0.2
V
A
TA = –40°C to +125°C, G = 5
0.15
0.2
V
B
A
TA = 25°C, G = 5
4.75
4.8
V
TA = –40°C to +125°C, G = 5
4.75
4.8
V
B
100
mV
C
Output saturation voltage, high
TA = 25°C, G = 5
Output saturation voltage, low
TA = 25°C, G = 5
Output current drive
50
mV
C
TA = 25°C
±40
±50
mA
A
TA = –40°C to +125°C
±40
±50
mA
B
5.5
V
B
1.2
mA
A
1.7
mA
B
dB
A
POWER SUPPLY
Specified operating voltage
Quiescent operating current per amplifier
2.5
TA = 25°C
TA = –40°C to +125°C
Power-supply rejection ratio (±PSRR)
(2)
(3)
8
0.8
1.0
0.65
94
108
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
Current is considered positive out of the pin.
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SBOS794 – DECEMBER 2016
7.7 Typical Characteristics
7.7.1 Typical Characteristics: VS = 2.7 V
test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V, input and output
referenced to mid-supply, VIN_CM = mid-supply – 0.5 V; TA = 25°C (unless otherwise noted)
Table 1. Table of Graphs
FIGURE TITLE
FIGURE LOCATION
Small-Signal Frequency Response
Figure 1
Large-Signal Frequency Response
Figure 2
Noninverting Pulse Response
Figure 3
Inverting Pulse Response
Figure 4
Slew Rate vs Output Voltage Step
Figure 5
Output Overdrive Recovery
Figure 6
Harmonic Distortion vs Frequency
Figure 7
Harmonic Distortion vs Load Resistance
Figure 8
Harmonic Distortion vs Output Voltage
Figure 9
Harmonic Distortion vs Gain
Figure 10
Output Voltage Swing vs Load Resistance
Figure 11
Output Saturation Voltage vs Load Current
Figure 12
Output Impedance vs Frequency
Figure 13
Frequency Response With Capacitive Load
Figure 14
Series Output Resistor vs Capacitive Load
Figure 17
Input-Referred Noise vs Frequency
Figure 16
Open-Loop Gain vs Frequency
Figure 15
Common-Mode, Power-Supply Rejection Ratios vs Frequency
Figure 18
Crosstalk vs Frequency
Figure 19
Input Offset Voltage
Figure 22
Input Offset Voltage vs Free-Air Temperature
Figure 20
Input Offset Voltage Drift
Figure 46
Input Offset Current
Figure 23
Input Offset Current vs Free-Air Temperature
Figure 24
Input Offset Current Drift
Figure 25
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test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 V, VOUT = 1 VPP, RF = 0 Ω, RL = 2 kΩ, G = 1 V/V,
input and output referenced to mid-supply, VIN_CM = mid-supply – 0.5 V; TA = 25°C (unless otherwise noted)
21
21
VS = 2.7 V,
VOUT = 100 mVpp,
G = 10
18
RL = 1 kW
G=5
12
RL = 1 kW
15
9
6
G=2
3
G=5
12
Gain Magnitude - dB
Gain Magnitude - dB
15
VS = 2.7 V,
VOUT = 1 Vpp,
G = 10
18
9
6
G=2
3
G=1
0
0
G=1
-3
-3
G = -1
-6
-6
-9
100k
-9
100k
1M
10M
f - Frequency - Hz
100M
1G
G = -1
3
VS = 2.7 V,
G = 1,
RF = 0 W
VO - Output Voltage - V
1G
VOUT = 1.5 Vpp
1.5
RL = 1 kW
VOUT = 2 Vpp
2
1.5
1
VOUT = 0.5 Vpp
0.5
VOUT = 0.5 Vpp
1
0.5
0
0
0
500
t - Time - ns
0
1000
500
t - Time - ns
1000
Figure 4. Inverting Pulse Response
Figure 3. Noninverting Pulse Response
300
0.75
3.75
VS = 2.7 V,
G = 5,
RF = 1 kW,
VS = 2.7 V,
G = 2,
250 RF = 1 kW
RL = 1 kW
Falling
VI - Input Voltage - V
0.5
200
Rising
150
100
VIN
3.25
VOUT
2.75
RL = 1 kW
2.25
1.75
0.25
1.25
0.75
0.25
VO - Output Voltage - V
VO - Output Voltage - V
100M
VS = 2.7 V,
G = -1,
RF = 1 kW
2.5
2 RL = 1 kW
Slew Rate - V/ms
10M
f - Frequency - Hz
Figure 2. Large-Signal Frequency Response
Figure 1. Small-Signal Frequency Response
2.5
1M
0
-0.25
50
-0.75
0
0.5
0.6
0.7
0.8
Output Voltage Step -V
0.9
1
-0.25
0
Figure 5. Slew Rate vs Output Voltage Step
10
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500
1000
t - Time - ns
1500
-1.25
2000
Figure 6. Output Overdrive Recovery
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OPA2836-Q1
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SBOS794 – DECEMBER 2016
-40
-70
VS = 2.7 V,
-50 G = 1,
VOUT = 1 Vpp,
-60 R = 0 W,
-75
Harmonic Distortion - dBc
Harmonic Distortion - dBc
F
RL = 1 kW
-70
-80
-90
HD2
-100
-110
-80
HD2
-85
-90
-95
-100
HD3
-120
HD3
-105
-130
-140
10k
-110
100
f - Frequency - Hz
1k
RLOAD - Load Resistance - W
Figure 7. Harmonic Distortion vs Frequency
Figure 8. Harmonic Distortion vs Load Resistance
100k
10M
1M
-30
-40
-50
RL = 1 kW
VS = 2.7 V,
G = 1,
f = 1 MHz,
VOUT = 1 Vpp,
-65
-70
-60
-70
HD2
-80
-90
HD2
RL = 1 kW
-75
-80
-85
-90
-95
HD3
-100
-100
HD3
-105
-110
0
1
VO - Output Voltage - Vpp
-110
2
1
2
3
4
5
6
Gain - V/V
7
8
9
10
Figure 10. Harmonic Distortion vs Gain
Figure 9. Harmonic Distortion vs Output Voltage
1
3
VS = 2.7 V,
G = 5,
2.5 RF = 1 kW
VS = 2.7 V,
G = 5,
RF = 1 kW
VOUT = High
VSAT - Saturation Voltage - V
VO - Output Voltage - V
10k
-60
VS = 2.7 V,
G = 1,
f = 1 MHz,
RF = 0 W,
Harmonic Distortion - dBc
Harmonic Distortion - dBc
VS = 2.7 V,
G = 1,
f = 1 MHz,
RF = 0 W
VOUT = 1 Vpp
2
1.5
1
0.1
VOUT = High
VOUT = Low
0.01
0.5
VOUT = Low
0
10
100
1k
10k
0.001
0.1
RL - Load Resistance - W
Figure 11. Output Voltage Swing vs Load Resistance
1
10
IL - Load Current - mA
100
Figure 12. Output Saturation Voltage vs Load Current
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3
VS = 2.7 V,
G=1
100
VS = 2.7 V,
G = 1,
R F = 0W
CL = 10 pF
RO = 49.9 W
Gain Magnitude - dB
ZO - Output Impedance - W
RL = 1 kW,
CL = 22 pF
0
10
1
RO = 40.2 W
CL = 56 pF
RO = 24.9 W
CL = 100 pF
-3
RO = 16.9 W
CL = 220 pF
RO = 10 W
CL = 560 pF
-6
0.1
RO = 5 W
CL = 2.2 pF
0.01
10k
100k
1M
10M
f - Frequency - Hz
100M
1G
-45
100
-90
80
-135
60
-180
40
-225
20
-270
0
-315
1
10
100
1k
10k
100k
1G
10
1
-360
-405
1M
10M 100M
0.1
1G
1
Frequency (Hz)
10
100
C001
1K
10K
100K
Frequency (Hz)
1M
10M
VS = 2.7 V
VS = 2.7 V
Figure 16. Input-Referred Noise vs Frequency
Figure 15. Open-Loop Gain vs Frequency
100
0
VS = 2.7 V,
G = 1,
RF = 0 W,
VS = 2.7 V
PSRR
-10
RL = 1 kW
-20
CMRR/PSRR - dB
RO - Output Resistor - W
100M
Voltage Noise
Current Noise
VN, IN (nV/√Hz, pA/√Hz)
120
±40
10M
f - Frequency - Hz
100
Phase (ƒ)
0
Magnitude (dB)
140
Open Loop Gain Magnitude
Open Loop Gain Phase
1M
Figure 14. Frequency Response With Capacitive Load
Figure 13. Output Impedance vs Frequency
±20
RO = 0 W
-9
100k
10
CMRR
-30
-40
-50
-60
-70
1
1
10
100
CLOAD - Capacitive Load - pF
1000
Figure 17. Series Output Resistor vs Capacitive Load
12
-80
100k
1M
10M
f - Frequency - Hz
100M
Figure 18. Common-Mode, Power-Supply Rejection Ratios
vs Frequency
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SBOS794 – DECEMBER 2016
400
300
−80
200
VOS - Offset Voltage - mV
Crosstalk (dB)
−90
−100
−110
100
0
-100
−120
-200
−130
−140
-300
20
100
1k
10k
100k
Frequency (Hz)
1M
10M
-400
-40
100M
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
Figure 19. Crosstalk vs Frequency
Figure 20. Input Offset Voltage vs Free-Air Temperature
8
3000
2666
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
7
2500
6
2000
Count
Count
5
4
3
1507
1500
1268
1000
2
500
311
207
1
34 3 2 0 0 0 0 0 0
0 0 0 0 0 0 7 30
<694.3
>694.3
<624.87
<486.01
<555.44
<277.72
<347.15
<416.58
<138.86
<208.29
<0
<69.43
<-138.86
<-69.43
<-347.15
<-277.72
<-208.29
<-486.01
<-416.58
<-694.3
-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOS - Drift - mV/°C
<-624.87
<-555.44
0
0
IOS - Offset Current - nA
Figure 21. Input Offset Voltage Drift
Figure 22. Input Offset Voltage
1800
150
1687
1600
1532
100
IOS - Offset Current - nA
1400
1200
Count
964
1000
768
800
600
0
-50
365
400
-100
233
200
50
125
80
20 8 7 11 15 28 40
58 29 29
9 10 4 13
>36.6
<136.6
<122.94
<95.62
<109.28
<68.3
<81.96
<27.32
<40.98
<54.64
<-0
<13.66
<-27.32
<-13.66
<-68.3
<-54.64
<-40.98
<-95.62
<-81.96
<-136.6
<-122.94
<-109.28
0
-150
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
IOS - Offset Current - nA
Figure 23. Input Offset Current
Figure 24. Input Offset Current vs Free-Air Temperature
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14
12
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
Count
10
8
6
4
2
0
-400-350-300-250-200-150-100 -50 0 50 100 150 200 250 300 350 400
IOS - Drift - pA/°C
Figure 25. Input Offset Current Drift
14
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SBOS794 – DECEMBER 2016
7.7.2 Typical Characteristics: VS = 5 V
test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 1 kΩ, G = 1 V/V, input and output
referenced to mid-supply; TA = 25°C (unless otherwise noted)
Table 2. Table of Graphs
FIGURE TITLE
FIGURE LOCATION
Small-Signal Frequency Response
Figure 26
Large-Signal Frequency Response
Figure 27
Noninverting Pulse Response
Figure 28
Inverting Pulse Response
Figure 29
Slew Rate vs Output Voltage Step
Figure 30
Output Overdrive Recovery
Figure 31
Harmonic Distortion vs Frequency
Figure 32
Harmonic Distortion vs Load Resistance
Figure 33
Harmonic Distortion vs Output Voltage
Figure 34
Harmonic Distortion vs Gain
Figure 35
Output Voltage Swing vs Load Resistance
Figure 36
Output Saturation Voltage vs Load Current
Figure 37
Output Impedance vs Frequency
Figure 38
Frequency Response With Capacitive Load
Figure 39
Series Output Resistor vs Capacitive Load
Figure 42
Input-Referred Noise vs Frequency
Figure 40
Open-Loop Gain vs Frequency
Figure 41
Common-Mode, Power-Supply Rejection Ratios vs Frequency
Figure 43
Crosstalk vs Frequency
Figure 44
Input Offset Voltage
Figure 47
Input Offset Voltage vs Free-Air Temperature
Figure 45
Input Offset Voltage Drift
Figure 46
Input Offset Current
Figure 48
Input Offset Current vs Free-Air Temperature
Figure 49
Input Offset Current Drift
Figure 50
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test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOUT = 2 VPP, RF = 0 Ω, RL = 1 kΩ, G = 1 V/V, input
and output referenced to mid-supply; TA = 25°C (unless otherwise noted)
21
21
VS = 5 V,
VOUT = 100 mVpp,
G = 10
18
RL = 1 kW
15
G=2
3
0
G=5
12
Gain Magnitude - dB
Gain Magnitude - dB
9
6
RL = 1 kW
15
G=5
12
VS = 5 V,
VOUT = 2 Vpp,
G = 10
18
9
6
G=2
3
0
G=1
-3
-3
G=1
-6
-6
G = -1
G = -1
-9
100k
1M
10M
f - Frequency - Hz
100M
-9
100k
1G
Figure 26. Small-Signal Frequency Response
5
100M
1G
5
VS = 5 V,
4.5 G = 1,
RF = 1 kW
4 R = 1 kW
4
3
VO - Output Voltage - V
3.5
VOUT = 4 Vpp
L
VOUT = 4 Vpp
VS = 5 V,
G = 1,
RF = 0 W
2.5
RL = 1 kW
2
1.5
3.5
3
2.5
VOUT = 0.5 Vpp
2
1.5
1
1
0.5
0.5
VOUT = 0.5 Vpp
0
0
500
t - Time - ns
1000
0
Figure 28. Noninverting Pulse Response
1000
Figure 29. Inverting Pulse Response
1.25
700
600
500
t - Time - ns
VS = 5 V,
G = 2,
RF = 1 kW
RL = 1 kW
6.25
VS = 5 V,
G = 5,
1 RF = 1 kW,
RL = 1 kW
Falling
Rising
VIN
5.75
5.25
VOUT
4.75
4.25
VI - Input Voltage - V
500
400
300
0.75
3.75
3.25
2.75
0.5
2.25
1.75
0.25
1.25
200
0.75
0
0
0.25
0
100
-0.25
-0.25
1
2
Output Voltage Step -V
3
4
0
Figure 30. Slew Rate vs Output Voltage Step
16
VO - Output Voltage - V
0
Slew Rate - V/ms
10M
f - Frequency - Hz
Figure 27. Large-Signal Frequency Response
4.5
VO - Output Voltage - V
1M
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500
1000
t - Time - ns
1500
-0.75
-1.25
2000
Figure 31. Output Overdrive Recovery
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SBOS794 – DECEMBER 2016
-40
-70
VS = 5 V,
-50 G = 1,
VOUT = 2 Vpp,
-60 R = 0 W,
-80
-90
HD2
-100
-110
-80
Harmonic Distortion - dBc
Harmonic Distortion - dBc
F
RL = 1 kW
-70
VS = 5 V,
G = 1,
f = 1 MHz,
RF = 0 W
VOUT = 2 Vpp
-75
HD3
HD2
-85
-90
-95
-100
-120
HD3
-105
-130
-140
10k
1M
100k
-110
100
10M
1k
RLOAD - Load Resistance - W
f - Frequency - Hz
Figure 32. Harmonic Distortion vs Frequency
Figure 33. Harmonic Distortion vs Load Resistance
-60
-70
VS = 5 V,
G = 1,
f = 1 MHz,
RF = 0 W,
-80
VS = 5 V,
G = 1,
f = 1 MHz,
VOUT = 2 Vpp,
-65
-70
RL = 1 kW
Harmonic Distortion - dBc
-75
Harmonic Distortion - dBc
10k
HD2
-85
-90
-95
-100
HD3
RL = 1 kW
-75
HD2
-80
-85
-90
-95
HD3
-100
-105
-105
-110
0
1
2
VO - Output Voltage - Vpp
3
-110
4
1
Figure 34. Harmonic Distortion vs Output Voltage
5
3
4
5
6
Gain - V/V
7
8
9
10
Figure 35. Harmonic Distortion vs Gain
1
VS = 5 V,
G = 2,
RF = 1 kW
VS = 5 V,
G = 5,
RF = 1 kW
VOUT = High
VSAT - Saturation Voltage - V
4
VO - Output Voltage - V
2
3
2
1
VOUT = High
0.1
VOUT = Low
VOUT = Low
0
10
100
1k
10k
0.01
0.1
RL - Load Resistance - W
Figure 36. Output Voltage Swing vs Load Resistance
1
10
IL - Load Current - mA
100
Figure 37. Output Saturation Voltage vs Load Current
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3
VS = 5 V,
G=1
100
VS = 5 V,
G = 1,
RF = 0 W
CL = 10 pF
RO = 49.9 W
RL = 1 kW
CL = 2.2 pF
0
10
Gain Magnitude - dB
ZO - Output Impedance - W
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1
0.1
RO = 0 W
CL = 56 pF
RO = 24.9 W
CL = 100 pF
-3
RO = 16.9 W
CL = 220 pF
RO = 10 W
-6
CL = 560 pF
RO = 5 W
CL = 22 pF
RO = 40.2 W
-9
0.01
0.01
0.1
1
10
100
1000
1M
100k
10M
f - Frequency - Hz
f - Frequency - MHz
Figure 38. Output Impedance vs Frequency
-90
80
-135
60
-180
40
-225
20
-270
0
-315
±40
1
10
100
1k
10k
100k
Voltage Noise
Current Noise
VN, IN (nV/√Hz, pA/√Hz)
100
100
Phase (ƒ)
-45
Magnitude (dB)
0
120
Open Loop Gain Magnitude
Open Loop Gain Phase
10
1
-360
-405
1M
10M 100M
0.1
1G
Frequency (Hz)
1
10
100
C002
1K
10K
100K
Frequency (Hz)
1M
10M
VS = 5.0 V
VS = 5.0 V
Figure 41. Input-Referred Noise vs Frequency
Figure 40. Open-Loop Gain vs Frequency
0
100
VS = 5 V
VS = 5 V,
G = 1,
RF = 0 W,
PSRR
-10
RL = 1 kW
-20
CMRR/PSRR - dB
RO - Output Resistor - W
1G
Figure 39. Frequency Response With Capacitive Load
140
±20
100M
10
CMRR
-30
-40
-50
-60
-70
1
1
10
100
CLOAD - Capacitive Load - pF
1000
Figure 42. Series Output Resistor vs Capacitive Load
18
-80
100k
1M
10M
f - Frequency - Hz
100M
Figure 43. Common-Mode, Power-Supply Rejection Ratios
vs Frequency
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SBOS794 – DECEMBER 2016
400
300
−80
200
VOS - Offset Voltage - mV
Crosstalk (dB)
−90
−100
−110
100
0
-100
−120
-200
−130
−140
-300
20
100
1k
10k
100k
Frequency (Hz)
1M
10M
-400
-40
100M
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
Figure 44. Crosstalk vs Frequency
Figure 45. Input Offset Voltage vs Free-Air Temperature
3000
9
2707
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
8
2500
7
2000
Count
Count
6
5
1511
1500
1269
4
1000
3
2
500
289
193
0 0 0 0 0 0 7 25
1
31 1 2 0 0 0 0 0 0
>693
<485.1
<554.4
<623.7
<693
<277.2
<346.5
<415.8
<138.6
<207.9
<-69.3
<0
<69.3
<-138.6
<-277.2
<-207.9
<-415.8
<-346.5
<-554.4
<-485.1
<-693
-5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOS - Drift - mV/°C
<-623.7
0
0
VOS - Offset Voltage - mV
Figure 47. Input Offset Voltage
Figure 46. Input Offset Voltage Drift
150
1800
1641
1600
1525
100
IOS - Offset Current - nA
1400
Count
1200
947
1000
788
800
600
50
0
-50
369
400
261
-100
200
129
89
20 8 8 9 14 32 43
58 28 30
10 8 5 13
<136.5
>136.5
<109.2
<122.85
<81.9
<95.55
<68.25
<40.95
<54.6
<0
<13.65
<27.3
<-27.3
<-13.65
<-40.95
<-109.2
<-95.55
<-81.9
<-68.25
<-54.6
<-136.5
<-122.85
0
-150
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - °C
IOS - Offset Current - nA
Figure 48. Input Offset Current
Figure 49. Input Offset Current vs Free-Air Temperature
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12
10
0°C to 70°C
-40°C to 85°C
-40°C to 125°C
Count
8
6
4
2
0
-400-350-300-250-200-150-100 -50 0
50 100 150 200 250 300 350 400
IOS - Drift - pA/°C
Figure 50. Input Offset Current Drift
20
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8 Detailed Description
8.1 Overview
The OPA2836-Q1 bipolar input operational amplifier offers an excellent bandwidth of 205 MHz with ultra-low
THD of 0.00003% at 1 kHz. The OPA2836-Q1 can swing to within 200 mV of the supply rails when driving a
1-kΩ load. The input common-mode of the amplifier can swing to 200 mV below the negative supply rail. This
level of performance is achieved at 1 mA of quiescent current per amplifier channel.
8.2 Functional Block Diagrams
VSIG
VS+
VREF
VIN
RG
OPA2836-Q1
VOUT
GVSIG
VREF
VREF
VSRF
Copyright © 2016, Texas Instruments Incorporated
Figure 51. Noninverting Amplifier
VSIG
VREF
VS+
VREF
RG
OPA2836-Q1
VIN
VS-
VOUT
GVSIG
VREF
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Inverting Amplifier
8.3 Feature Description
8.3.1 Input Common-Mode Voltage Range
When the primary design goal is a linear amplifier with high CMRR, the input common-mode voltage range (VICR)
of the amplifier must not be violated.
The common-mode input range low and high specifications are based on CMRR. The specification limits are
chosen to ensure CMRR does not degrade more than 3 dB below the mid-supply limit if the input voltage is kept
within the specified range. The limits cover all process variations and most parts are better than specified. The
typical specifications are from 0.2 V below the negative rail to 1.1 V below the positive rail.
Given that the operational amplifier is in linear operation, the voltage difference between the input pins is very
small (ideally 0 V), and input common-mode voltage can be analyzed at either input pin with the other input pin
assumed to be at the same potential. The voltage at VIN+ is easy to evaluate. In the noninverting configuration,
Figure 51, the input signal VIN must not violate VICR. In the inverting configuration, Figure 52, the reference
voltage VREF must be within VICR.
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Feature Description (continued)
The input voltage limits have a fixed headroom to the power rails and track the power-supply voltages. For one
5-V supply, the linear input voltage range is –0.2 V to 3.9 V, and with a 2.7-V supply this range is –0.2 V to
1.6 V. The delta from each power-supply rail is the same in either case: –0.2 V and 1.1 V.
8.3.2 Output Voltage Range
The OPA2836-Q1 is a rail-to-rail output (RRO) operational amplifier. Rail-to-rail output typically means the output
voltage can swing to within a couple hundred millivolts of the supply rails. There are two different ways to specify
this: with the output still in linear operation and with the output saturated. Saturated output voltages are closer to
the power-supply rails than linear outputs, but the signal is not a linear representation of the input. Linear output
is a better representation of how well a device performs when used as a linear amplifier. Both saturation and
linear operation limits are affected by the current in the output, where higher currents lead to more loss in the
output transistors.
Data in the Electrical Characteristics tables list both linear and saturated output voltage specifications with a 1-kΩ
load. Figure 11 and Figure 36 illustrate saturated voltage-swing limits versus output load resistance, and
Figure 12 and Figure 37 illustrate the output saturation voltage versus load current. Given a light load, the output
voltage limits have a nearly constant headroom to the power rails and track the power-supply voltages. For
example, with a 2-kΩ load and a single 5-V supply, the linear output voltage range is 0.15 V to 4.8 V, and with a
2.7-V supply this range is 0.15 V to 2.5 V. The delta from each power-supply rail is the same in either case: 0.15
V and 0.2 V.
With devices such as the OPA2836-Q1 where the input range is lower than the output range, the input typically
limits the available signal swing only in the noninverting gain of 1. Signal swings in noninverting configurations in
gains greater than +1 and in inverting configurations in any gain are generally limited by the output voltage limits
of the operational amplifier.
8.3.3 Low-Power Applications and the Effects of Resistor Values on Bandwidth
The OPA2836-Q1 is designed for the nominal value of RF to be 1 kΩ in gains other than +1 V/V. This value of RF
= 1 kΩ gives excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. This
value also loads the amplifier. For example, in a gain of 2 with RF = RG = 1 kΩ, RG to ground, and VOUT = 4 V,
2 mA of current flows through the feedback path to ground. In s gain of +1, RG is open and no current flows to
ground. In low-power applications, reducing this current by increasing the gain-setting resistors values is
desirable. Using larger value gain resistors has two primary side effects (other than lower power) because of the
interaction with parasitic circuit capacitance:
• Lowers the bandwidth
• Lowers the phase margin
– Causes peaking in the frequency response
– Also causes overshoot and ringing in the pulse response
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Feature Description (continued)
Figure 53 shows the small-signal frequency response for a noninverting gain of 2 with RF and RG equal to 1 kΩ,
10 kΩ, and 100 kΩ. The test was done with RL = 1 kΩ. Lower values can reduce the peaking because of loading
effects of RL, but higher values do not have a significant effect.
24
Gain Magnitude - dB
VS = 5 V,
21 V
OUT = 100 mVpp,
18 G = 2,
RL = 1 kW
15
RF = 100 kW
12
RF = 10 kW
RF = 10 kW
CF = 1 pF
RF = 100 kW
CF = 1 pF
9
6
RF = 1 kW
3
0
-3
-6
-9
0
1
10
f - Frequency - MHz
100
1000
Figure 53. Frequency Response With Various Gain-Setting Resistor Values
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in the
frequency response is synonymous with overshoot and ringing in pulse response). Adding 1-pF capacitors in
parallel with RF helps compensate the phase margin and restores flat frequency response. Figure 54 shows the
test circuit used.
VIN
RG
VOUT
OPA2836-Q1
1 kW
RF
CF
Copyright © 2016, Texas Instruments Incorporated
Figure 54. G = 2 Test Circuit for Various Gain-Setting Resistor Values
8.3.4 Driving Capacitive Loads
The OPA2836-Q1 can drive up to a nominal capacitive load of 2.2 pF on the output with no special
consideration. When driving capacitive loads greater than this load, using a small resister (RO) in series with the
output as close to the device as possible is recommended. Without RO, the capacitance on the output interacts
with the output impedance of the amplifier causing phase shift in the loop gain of the amplifier that reduces the
phase margin. This scenario causes peaking in the frequency response and overshoot and ringing in the pulse
responses. Interaction with other parasitic elements can lead to instability or oscillation. Inserting RO isolates the
phase shift from the loop-gain path and restores the phase margin; however, the bandwidth is also limited.
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Feature Description (continued)
Figure 55 shows the test circuit and Figure 42 illustrates the recommended values of RO versus capacitive loads,
CL. See Figure 39 for frequency responses with various values.
RO
VIN
VOUT
OPA2836-Q1
CL
1 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 55. RO versus CL Test Circuit
8.4 Device Functional Modes
8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
To facilitate testing with common lab equipment, the OPA2836-Q1 EVM (see the OPA835DBV, OPA836DBV
EVM, SLOU314) is built to allow for split-supply operation. This configuration eases lab testing because the midpoint between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum
analyzers, and other lab equipment reference inputs and outputs to ground.
Figure 56 shows a simple noninverting configuration analogous to Figure 51 with a ±2.5-V supply and VREF equal
to ground. The input and output swing symmetrically around ground. Split-supply operation is preferred because
of the ease of use in systems where signals swing around ground, but two supply rails still must be generated.
+2.5 V
VSIG
RG
VOUT
OPA2836-Q1
Load
-2.5 V
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 56. Split-Supply Operation
24
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Device Functional Modes (continued)
8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
Many newer systems use a single power supply to improve efficiency and reduce the cost of the power supply.
The OPA2836-Q1 is designed for use with single-supply power operation and can be used with single-supply
power with no change in performance from split supply as long as the input and output are biased within the
linear operation of the device.
To change the circuit from split supply to single supply, level shift all voltages by half the difference between the
power-supply rails. For example, changing from a ±2.5-V split supply to a 5-V single supply is shown
conceptually in Figure 57.
5V
RG
VSIG
VOUT
OPA2836-Q1
Load
RF
2.5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 57. Single Supply Concept
A more practical circuit has a prior amplifier or another circuit to provide the bias voltage for the input with the
output providing the bias for the next stage.
Figure 58 shows a typical noninverting amplifier situation. With a 5-V single supply, a mid-supply reference
generator is needed to bias the negative side through RG. To cancel the voltage offset that is otherwise caused
by the input bias currents, R1 is chosen to be equal to RF in parallel with RG. For example, if a gain of 2 is
required and RF = 1 kΩ, select RG = 1 kΩ to set the gain and R1 = 499 Ω for bias current cancellation. The value
for C is dependent on the reference, but at least 0.1 µF is recommended to limit noise.
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RO
OPA2836-Q1
5V
2.5 V
REF
RG
VOUT
GVSIG
2.5 V
C
RF
Signal and bias to
next stage
Copyright © 2016, Texas Instruments Incorporated
Figure 58. Noninverting Single Supply With Reference
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Device Functional Modes (continued)
Figure 59 shows a similar noninverting single-supply scenario with the reference generator replaced by the
Thevenin equivalent using resistors and the positive supply. RG’ and RG” form a resistor divider from the 5-V
supply and are used to bias the negative side with the parallel sum equal to the equivalent RG to set the gain. To
cancel the voltage offset that is otherwise caused by the input bias currents, R1 is chosen to be equal to RF in
parallel with RG’ in parallel with RG” (R1= RF || RG’ || RG”). For example, if a gain of 2 is required and RF = 1 kΩ,
selecting RG’ = RG” = 2 kΩ gives an equivalent parallel sum of 1 kΩ, sets the gain to 2, and references the input
to mid supply (2.5 V). R1 is then set to 499 Ω for bias current cancellation, which can be lower cost compared to
Figure 59 but requires extra current in the resistor divider.
Signal and bias
from previous stage
VSIG
2.5 V
5V
R1
RO
RG’
5V
VOUT
OPA2836-Q1
GVSIG
2.5 V
RG”
Signal and bias to
next stage
RF
Copyright © 2016, Texas Instruments Incorporated
Figure 59. Noninverting Single Supply With Resistors
Figure 60 shows a typical inverting amplifier situation. With a 5-V single supply, a mid-supply reference generator
is needed to bias the positive side via R1. To cancel the voltage offset that is otherwise caused by the input bias
currents, R1 is chosen to be equal to RF in parallel with RG. For example, if a gain of –2 is required and RF = 1
kΩ, select RG = 499 Ω to set the gain and R1 = 332 Ω for bias-current cancellation. The value for C is dependent
on the reference, but at least 0.1 µF is recommended to limit noise into the operational amplifier.
5V
5V
R1
2.5 V
REF
RO
VOUT
OPA2836-Q1
C
GVSIG
2.5 V
RG
RF
VSIG
Signal and bias to
next stage
2.5 V
Signal and bias
from previous stage
Copyright © 2016, Texas Instruments Incorporated
Figure 60. Inverting Single Supply With Reference
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Device Functional Modes (continued)
Figure 61 shows a similar inverting single-supply scenario with the reference generator replaced by the Thevenin
equivalent using resistors and the positive supply. R1 and R2 form a resistor divider from the 5-V supply and are
used to bias the positive side. To cancel the voltage offset that is otherwise caused by the input bias currents,
set the parallel sum of R1 and R2 equal to the parallel sum of RF and RG. C must be added to limit coupling of
noise into the positive input. For example, if a gain of –2 is required and RF = 1 kΩ, select RG = 499 Ω to set the
gain. R1 = R2 = 665 Ω for mid-supply voltage bias and for operational amplifier input bias current cancellation. A
good value for C is 0.1 µF and can be a lower cost compared to Figure 61, but requires extra current in the
resistor divider.
5V
5V
R1
RO
R2
C
VOUT
OPA2836-Q1
GVSIG
2.5 V
RG
VSIG
RF
Signal and bias to
next stage
2.5 V
Signal and bias
from previous stage
Copyright © 2016, Texas Instruments Incorporated
Figure 61. Inverting Single Supply With Resistors
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Noninverting Amplifier
The OPA2836-Q1 can be used as a noninverting amplifier with a signal input to the noninverting input, VIN+ . A
basic block diagram of the circuit is illustrated in Figure 51.
If VIN = VREF + VSIG, then the output of the amplifier can be calculated according to Equation 1.
æ
RF ö
V
= VSIG ç 1 +
÷ + VREF
OUT
RG ø
è
(1)
RF
RG , and V
The signal gain of the circuit is set by
REF provides a reference around which the input and
output signals swing. Output signals are in-phase with the input signals.
G= 1 +
The OPA2836-Q1 is designed for the nominal value of RF to be 1 kΩ in gains other than +1. This value gives
excellent distortion performance, maximum bandwidth, best flatness, and best pulse response. RF = 1 kΩ must
be used as a default unless other design goals require changing to other values. All test circuits used to collect
data for this document have RF = 1 kΩ for all gains other than +1. Gain of +1 is a special case where RF is
shorted and RG is left open.
9.1.2 Inverting Amplifier
The OPA2836-Q1 can be used as an inverting amplifier with a signal input to the inverting input, VIN– , through
the gain setting resistor RG. A basic block diagram of the circuit is illustrated in Figure 52.
If VIN = VREF + VSIG, then the output of the amplifier may be calculated according to Equation 2.
æ -R
VOUT = VSIG ç F
è RG
ö
÷ + VREF
ø
(2)
G=
-RF
RG , and V
The signal gain of the circuit is set by:
REF provides a reference point around which the input
and output signals swing. Output signals are 180° out-of-phase with the input signals. The nominal value of RF
must be 1 kΩ for inverting gains.
9.1.3 Instrumentation Amplifier
Figure 62 is an instrumentation amplifier that combines the high input impedance of the differential-to-differential
amplifier circuit and the common-mode rejection of the differential-to-single-ended amplifier circuit. This circuit is
often used in applications where high input impedance is required (such as taps from a differential line or in
cases where the signal source has a high output impedance).
If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG– , then the output of the amplifier can be calculated according to
Equation 3.
VOUT =
28
(VIN+ - VIN- )
æ
2RF1 ö æ RF2 ö
´ ç1 +
÷ ç
÷ + VREF
RG1 ø è RG2 ø
è
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Application Information (continued)
æ
2R F1 ö æ R F2 ö
G = ç1 +
÷ ç
÷
R G 1 ø è R G2 ø
è
The signal gain of the circuit is set by
. VCM is rejected and VREF provides a level shift
around which the output signal swings. The single-ended output signal is in-phase with the differential input
signal.
VIN½ OPA2836-Q1
VSIG-
RF2
VCM
RF1
RG1
RG2
RG2
VSIG+
G[(VSIG+)-(VSIG-)]
RF2
VCM
VOUT
OPA2836-Q1
RF1
VREF
½ OPA2836-Q1
VREF
VIN+
Figure 62. Instrumentation Amplifier
Integrated solutions are available, but the OPA2836-Q1 provides a much lower-power, high-frequency solution.
For best CMRR performance, resistors must be matched. Given that CMRR ≈ the resistor tolerance, a 0.1%
tolerance provides apprximately 60-dB CMRR.
9.1.4 Attenuators
The noninverting circuit of Figure 51 has a minimum gain of 1. To implement attenuation, a resistor divider can
be placed in series with the positive input, and the amplifier can be set for a gain of 1 by shorting VOUT to VIN–
and removing RG. Because the operational amplifier input has high input impedance, the attenuation is set by the
resistor divider.
The inverting circuit of Figure 52 can be used as an attenuator by making RG larger than RF. The attenuation is
simply the resistor ratio. For example, a 10:1 attenuator can be implemented with RF = 1 kΩ and RG = 10 kΩ.
9.1.5 Single-Ended-to-Differential Amplifier
Figure 63 illustrates an amplifier circuit that is used to convert single-ended signals to differential and that
provides gain and level shifting. This circuit can be used for converting signals to differential in applications (such
as line drivers for Cat5 cabling or for driving differential-input SAR and ΔΣ ADCs).
With VIN = VREF + VSIG , the output of the amplifier can be calculated according to Equation 4.
RF
VOUT+ = G x VIN + VREF and VOUT- = -G x VIN + VREF Where: G = 1 +
RG
(4)
The differential-signal gain of the circuit is 2 × G, and VREF provides a reference around which the output signal
swings. The differential output signal is in-phase with the single-ended input signal.
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Application Information (continued)
G x V SIG
RO
VSIG
R1
VIN
VREF
VOUT+ VREF
½ OPA2836-Q1
2R
+
VREF
2R
VREF
+
RG
RF
-G x V SIG
RO
VOUT-
VREF
½ OPA2836-Q1
R
Copyright © 2016, Texas Instruments Incorporated
Figure 63. Single-Ended-to-Differential Amplifier
Line termination on the output can be accomplished with resistors RO. The differential input impedance of the
circuit is 2 × RO. For example, if a 100-Ω Cat5 cable is used with double termination, the amplifier is typically set
for a differential gain of 2 V/V (6 dB) with RF = 0 Ω (short), RG = open, 2R = 1 kΩ, R1 = 0 Ω, R = 499 Ω to
balance the input bias currents, and RO = 49.9 Ω for output line termination. This configuration is shown in
Figure 64.
For driving a differential-input ADC, the situation is similar but the output resistors (RO) are typically chosen along
with a capacitor across the ADC input for optimum filtering and settling-time performance.
VSIG
49.9 Ω
VSIG
VREF
VIN
RG
1 kΩ
½ OPA2836-Q1
+
VOUT+ VREF
RF
1 kΩ
VREF
-VSIG
49.9 Ω
VOUT-
VREF
½ OPA2836-Q1
+
499 Ω
Copyright © 2016, Texas Instruments Incorporated
Figure 64. Cat5 Line Driver With Gain = 2 V/V (6 dB)
9.1.6 Differential-to-Signal-Ended Amplifier
Figure 65 illustrates a differential amplifier that converts differential signals to single-ended and provides gain (or
attenuation) and level shifting. This circuit can be used in applications such as a line receiver for converting a
differential signal from a Cat5 cable to single ended.
If VIN+ = VCM + VSIG+ and VIN– = VCM + VSIG–, then the output of the amplifier can be calculated according to
Equation 5.
æR ö
VOUT = (VIN+ - VIN - ) ´ ç F ÷ + VREF
è RG ø
(5)
G=
RF
RG . V is rejected, and V
The signal gain of the circuit is set by
CM
REF provides a level shift around which
the output signal swings. The single-ended output signal is in-phase with the differential input signal.
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Application Information (continued)
VSIG-
RF
VCM
RG
VIN-
RG
VIN+
VOUT
OPA2836-Q1
G[(VSIG+)-(VSIG-)]
VSIG+
RF
VCM
VREF
VREF
Copyright © 2016, Texas Instruments Incorporated
Figure 65. Differential to Single Ended Amplifier
Line termination can be accomplished with a resistor shunt across the input. The differential input impedance of
the circuit is the resistor value in parallel with the amplifier circuit. For low-gain and low-line impedance, the
resistor value to add is approximately the impedance of the line. For example, if a 100-Ω Cat5 cable is used with
a gain of 1 amplifier and RF = RG = 1 kΩ, adding a 100-Ω shunt across the input gives a differential impedance of
98 Ω that is adequate for most applications.
For best CMRR performance, resistors must be matched. A rule of thumb is CMRR ≈ the resistor tolerance; so a
0.1% tolerance provides approximately 60-dB CMRR.
9.1.7 Differential-to-Differential Amplifier
Figure 66 shows a differential amplifier that is used to amplify differential signals. This circuit has high input
impedance and is often used in differential line driver applications where the signal source is a high-impedance
driver (for example, a differential DAC) that must drive a line.
If VIN± = VCM + VSIG± , then the output of the amplifier can be calculated according to Equation 6.
æ
2RF ö
V
= VIN ± ´ ç 1 +
÷ + VCM
OUT ±
RG ø
è
G= 1 +
(6)
2RF
RG , and V passes with unity gain. The amplifier in essence
The signal gain of the circuit is set by
CM
combines two noninverting amplifiers into one differential amplifier with the RG resistor shared, which makes RG
effectively half the value when calculating the gain. The output signals are in-phase with the input signals.
VIN½ OPA2836-Q1
VSIG-
VOUTGVSIGVCM
VCM
RF
RG
RF
VSIG+
GVSIG+
VCM
VCM
½ OPA2836-Q1
VOUT+
VIN+
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Figure 66. Differential to Differential Amplifier
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Application Information (continued)
9.1.8 Pulse Application With Single-Supply
For pulsed applications, where the signal is at ground and pulses to some positive or negative voltage, the circuit
bias-voltage considerations are different than with a signal that swings symmetrical about a reference point.
Figure 67 shows a pulsed situation where the signal is at ground (0 V) and pulses to a positive value.
Signal and bias
from previous stage
VSIG
0V
5V
R1
RO
VOUT
OPA2836-Q1
GVSIG
RG
0V
RF
Signal and bias to
next stage
Copyright © 2016, Texas Instruments Incorporated
Figure 67. Noninverting Single Supply With Pulse
If the input signal pulses negatively from ground, an inverting amplifier is more appropriate, as shown in
Figure 68. A key consideration in both noninverting and inverting cases is that the input and output voltages are
kept within the limits of the amplifier; because the VICR of the OPA2836-Q1 includes the negative supply rail, the
OPA2836-Q1 lends itself to this application.
5V
R1
OPA2836-Q1
RO
VOUT
GVSIG
RG
Signal and bias
from previous stage
0V
VSIG
0V
RF
Signal and bias to
next stage
Copyright © 2016, Texas Instruments Incorporated
Figure 68. Inverting Single Supply With Pulse
9.1.9 ADC Driver Performance
The OPA2836-Q1 provides excellent performance when driving high-performance, delta-sigma (ΔΣ), and
successive approximation register (SAR) ADCs in low-power audio and industrial applications.
To show achievable performance, the OPA2836-Q1 is tested as the drive amplifier for the ADS8326. The
ADS8326 is a 16-bit, micro power, SAR ADC with pseudo-differential inputs and sample rates up to 250 kSPS.
The ADS8326 offers excellent noise and distortion performance in a small 8-pin SOIC or VSSOP (MSOP)
package. Low power and small size make the ADS8326 and OPA2836-Q1 devices an ideal solution for portable
and battery-operated systems, for remote data-acquisition modules, simultaneous multichannel systems, and
isolated data acquisition.
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Application Information (continued)
The circuit shown in Figure 69 is used to test the performance. Figure 70 is the FFT plot showing the spectral
performance with a 10-kHz input frequency, and Table 3 shows the tabulated ac analysis results.
2.7 V
VSIG
VSIG
0V
2.7V
2k
1k
1.35 V
5V
VS+
VIN
2.5 V
100
+In VDD REF
ADS 8326
-In
OPA2836-Q1
2k
2.2 nF
VS-
1k
1k
Copyright © 2016, Texas Instruments Incorporated
Figure 69. OPA2836-Q1 and ADS8326 Test Circuit
0
-20
AIN - dBc
-40
-60
-80
-100
-120
-140
0
20
40
60
80
f - Frequency - Hz
100
120
Figure 70. ADS8326 and OPA2836-Q1 10-kHz FFT
Table 3. AC Analysis
TONE (kHz)
SIGNAL (dBFS)
SNR (dBc)
THD (dBc)
SINAD (dBc)
SFDR (dBc)
10
–0.85
83.3
–86.6
81.65
88.9
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9.2 Typical Applications
9.2.1 Audio-Frequency Performance
The OPA2836-Q1 provides excellent audio performance with very low quiescent power. To show performance in
the audio band, a 2700 series audio analyzer from Audio Precision is used to test THD+N and FFT at 1-VRMS
output voltage.
Figure 71 shows the test circuit used for the audio-frequency performance application.
+2.5 V
VIN
From AP
VOUT
To AP
100 pF OPA2836-Q1
10 W
-2.5 V
Copyright © 2016, Texas Instruments Incorporated
The 100-pF capacitor to ground on the input helped to decouple noise pick up in the lab and improved noise
performance.
Figure 71. OPA2836-Q1 Audio Precision Analyzer Test Circuit
9.2.1.1 Design Requirements
Design a low distortion, single-ended input to single-ended output audio amplifier using the OPA2836-Q1. The
2700 series audio analyzer from Audio Precision is used as the signal source and also as the measurement
system.
Table 4. Design Requirements
CONFIGURATION
INPUT
EXCITATION
PERFORMANCE
TARGET
RLoad
OPA2836-Q1 unity-gain configuration
1-kHz tone frequency
> 110 dBc SFDR
300 Ω and
100 kΩ
9.2.1.2 Detailed Design Procedure
The OPA2836-Q1 is tested in this application in a unity-gain buffer configuration. A buffer configuration is chosen
because this configuration maximizes the loop gain of the amplifier configuration. At higher closed-loop gains, the
loop gain of the circuit reduces, resulting in degraded harmonic distortion. The relationship between distortion
and closed-loop gain at a fixed input frequency is illustrated in Figure 35 in the Typical Characteristics section.
The test was performed under varying output load conditions using a resistive load of 300 Ω and 100 kΩ.
Figure 33 illustrates the distortion performance of the amplifier versus output resistive load. Output loading,
output swing, and closed-loop gain play a key role in determining the distortion performance of the amplifier.
NOTE
The 100-pF capacitor to ground on the input helped to decouple noise pickup in the lab
and improved noise performance.
The Audio Precision was configured as a single-ended output in this application circuit. In applications where a
differential output is available, the OPA2836-Q1 device can be configured as a differential-to-single-ended
amplifier; see Figure 65. Power-supply bypassing is critical in order to reject noise from the power supplies. A
2.2-μF power-supply decoupling capacitor must be placed within 2 inches of the device and can be shared with
other operational amplifiers on the same board. A 0.1-μF power supply decoupling capacitor must be placed as
close to the power supply pins as possible, preferably within 0.1 inch. For split supply, a capacitor is required for
both supplies. A 0.1-µF capacitor placed directly between the supplies is also beneficial for improving system
noise performance. If the output load is very heavy, in the order of 16 Ω to 32 Ω, performance of the amplifier
can begin to degrade. In order to drive such heavy loads, both channels of the OPA2836-Q1 device can be
paralleled with the outputs isolated with 1-Ω resistors to reduce the loading effects.
34
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9.2.1.3 Application Curves
A 10-Ω series resistor can be inserted between the capacitor and the noninverting pin to isolate the capacitance.
Figure 72 shows the THD+N performance with 100-kΩ and 300-Ω loads, with A-weighting and with no weighting.
Both loads show similar performance. With no weighting, the THD+N performance is dominated by the noise;
whereas, A-weighting provides filtering that improves the noise.
Figure 73 and Figure 74 show FFT outputs with a 1-kHz tone and 100-kΩ and 300-Ω loads. To show relative
performance of the device versus the test set, one channel has the OPA2836-Q1 in-line between generator
output and analyzer input and the other channel is in Gen Mon loopback mode that internally connects the signal
generator to the analyzer input. With a 100-kΩ load, Figure 73, the curves are basically indistinguishable from
each other except for noise, meaning that the OPA2836-Q1 cannot be directly measured. With a 300-Ω load,
Figure 74, the main difference between the curves is that the OPA2836-Q1 shows slightly higher even-order
harmonics, but odd-order harmonics are masked by the test-set performance.
0
VS = 5 V,
VOUT = 1 VRMS,
G = 1,
RF = 0 W,
BW = 80 kHz
-95
-100
No weighting
RL = 300 W,
VS = 5 V,
VOUT = 1 VRMS,
G = 1,
RF = 0 W
-10
-20
-30
-40
FFT - dBV
THD+N - Total Harmonic Distortion + Noise - dBv
-90
RL = 100 kW
-105
-50
-60
-70
-80
-110
A-weighting
RL = 300 W,
-90
-100
RL = 100 kW
Gen Mon - 100k
-110
-115
-120
RL = 100k
-130
-120
10
-140
100
1k
f - Frequency - Hz
10k
100k
Figure 72. OPA2836-Q1 1 VRMS, 20-Hz to 80-kHz THD+N
0
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
Figure 73. OPA2836-Q1 and AP Gen Mon 10-kHz FFT Plot;
VOUT = 1 VRMS, RL = 100 kΩ
0
VS = 5 V,
VOUT = 1 VRMS,
G = 1,
RF = 0 W
-10
-20
-30
-40
FFT - dBV
-50
-60
-70
-80
-90
Gen Mon - 300
-100
-110
RL = 300
-120
-130
-140
0
2k
4k
6k
8k
10k
12k
f - Frequency - Hz
14
16k
18k
20k
Figure 74. OPA2836-Q1 and AP Gen Mon 10-kHz FFT Plot;
VOUT = 1 VRMS, RL = 300 Ω
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9.2.2 Active Filters
The OPA2836-Q1 can be used to design active filters. Figure 75 and Figure 76 show MFB and Sallen-Key
circuits designed using the WEBENCH® filter designer to implement second-order low-pass Butterworth filter
circuits. Figure 77 shows the frequency response.
1.24 kW
330 pF
1.24 kW
2.80 kW
OPA2386-Q1
2.2 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 75. MFB 100-kHz Second Order Low-Pass Butterworth Filter Circuit
2.2 nF
562 W
6.19 kW
330 pF
OPA2836-Q1
Copyright © 2016, Texas Instruments Incorporated
Figure 76. Sallen-Key 100-kHz Second Order Low-Pass Butterworth Filter Circuit
VS = 5 V,
VOUT = 100 mVpp
Gain Magnitude - dB
0
MFB
-10
-20
Sallen-Key
-30
-40
1k
10k
100k
1M
f - Frequency - Hz
Figure 77. MFB and Sallen-Key Second Order Low-Pass Butterworth Filter Response
MFB and Sallen-Key filter circuits offer similar performance. The main difference is the MFB uses an inverting
amplifier in the pass-band and the Sallen-Key uses an noninverting amplifier. The primary advantage for each is
the Sallen-Key in unity gain has no resistor gain-error term, and thus no sensitivity to gain error, whereas the
MFB has inherently better attenuation properties beyond the bandwidth of the operational amplifier.
36
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10 Power Supply Recommendations
The OPA2836-Q1 is principally intended to work in a supply range of 2.7 V to 5 V. Supply voltage tolerances are
supported with the specified operating range of 2.5 V (7% on a 2.7-V supply) and 5.5 V (10% on a 5-V supply).
Good power-supply bypassing is required. Minimize the distance (< 0.1 inch) from the power-supply pins to highfrequency, 0.1-μF decoupling capacitors. Often a larger capacitor (2.2 µF, typical) is used along with a highfrequency, 0.1-µF supply decoupling capacitor at the device supply pins. For single-supply operation, only the
positive supply has these capacitors. When a split supply is used, use these capacitors for each supply to
ground. If necessary, place the larger capacitors somewhat farther from the device and share these capacitors
among several devices in the same area of the PCB. Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling capacitors. An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) improves second-harmonic distortion performance.
11 Layout
11.1 Layout Guidelines
The OPA835DBV, OPA836DBV EVM (SLOU314) must be used as a reference when designing the circuit board.
Follow the EVM layout of the external components near to the amplifier, ground plane construction, and power
routing as closely as possible. General guidelines are:
1. Signal routing must be direct and as short as possible into an out of the operational amplifier.
2. The feedback path must be short and direct avoiding vias if possible especially with G = +1.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. A series output resistor is recommended to be placed as near to the output pin as possible. See Figure 17
for recommended values given expected capacitive load of design.
5. A 2.2-µF power-supply decoupling capacitor must be placed within 2 inches of the device and can be shared
with other operational amplifiers. For spit supply, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as near to the power supply pins as possible.
Preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
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11.2 Layout Example
Figure 78. Top Layer
Figure 79. Bottom Layer
38
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
WEBENCH® filter designer
12.1.2 Related Documentation
For related documentation see the following:
• OPA835DBV, OPA836DBV EVM (SLOU314)
• ADS8326 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling Analog-to-Digital Converter (SBAS343)
12.2 Related Links
Table 5 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA2836-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
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7-Dec-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
OPA2836QDGKRQ1
PREVIEW
Package Type Package Pins Package
Drawing
Qty
VSSOP
DGK
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
2836Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2016
OTHER QUALIFIED VERSIONS OF OPA2836-Q1 :
• Catalog: OPA2836
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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