TI OPA1688 Soundplus 36-v, single-supply, 10-mhz, rail-to-rail output operational amplifier Datasheet

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OPA168x
SoundPlus 36-V, Single-Supply, 10-MHz, Rail-to-Rail Output Operational Amplifiers
1 Features
•
•
•
•
•
•
•
•
•
•
•
•
•
THD+N, 50 mW, 32 Ω, 1 kHz, –109 dB
Wide Supply Range:
– 4.5 V to 36 V, ±2.25 V to ±18 V
Low Offset Voltage: ±0.25 mV
Low Offset Drift: ±0.5 µV/°C
Gain Bandwidth: 10 MHz
Low Input Bias Current: ±10 pA
Low Quiescent Current: 1.6 mA per Amplifier
Low Noise: 8 nV/√Hz
EMI- and RFI-Filtered Inputs
Input Range Includes Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
High Common-Mode Rejection: 120 dB
Industry-Standard Packages:
– SOIC-8 and SOIC-14
microPackages:
– Dual in WSON-8, Quad in VQFN-16
Unlike most op amps that are specified at only one
supply voltage, the OPA168x family is specified from
4.5 V to 36 V. Input signals beyond the supply rails
do not cause phase reversal. The input can operate
100 mV below the negative rail and within 2 V of the
top rail during normal operation. Note that these
devices can operate with full rail-to-rail input 100 mV
beyond the top rail, but with reduced performance
within 2 V of the top rail.
The OPA168x series of op amps are specified from
–40°C to 85°C.
2 Applications
•
•
•
•
•
•
•
•
The OPA1688 and OPA1689 are a family of
SoundPlus™
36-V,
single-supply,
low-noise
operational amplifiers capable of operating on
supplies ranging from 4.5 V (±2.25 V) to 36 V
(±18 V). This latest addition of high-voltage audio
operational amplifiers, in conjunction with the
OPA16xx devices provide a family of bandwidth,
noise, and power options to meet the needs of a wide
variety of applications. The OPA168x are available in
micropackages, and offer low offset, drift, and
quiescent current. These devices also offer wide
bandwidth, fast slew rate, and high output current
drive capability. The dual and quad versions all have
identical specifications for maximum design flexibility.
Headphone Driver
Analog and Digital Mixers
Audio Effects Processors
Transducer Amplifiers
Musical Instruments
A/V Receivers
DVD and Blu-Ray™ Players
Car Audio Systems
Device Information(1)
PART NUMBER
OPA1688
OPA1689(2)
++
VAC
ROUT
Audio DAC
R3
768
5V
R4
750
C2
47pF
OPA1688
Headphone
Output
Total Harmonic Distortion + Noise (%)
-5 V
+
VDC
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
VQFN (16)
3.50 mm × 3.50 mm
1
R2
750
VAC
WSON (8)
Superior THD Performance
(f = 1 kHz, BW = 80 kHz, VS = ±5 V)
C1
47pF
ROUT
BODY SIZE (NOM)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Product-preview device.
Headphone Amplifier Circuit Configuration
R1
768
PACKAGE
SOIC (8)
-40
0.1
-60
Inverting
0.01
-80
Noninverting
0.001
16-
Load
32-
Load
1280.0001
0.001
-100
Load
Total Harmonic Distortion + Noise (dB)
•
•
1
3 Description
-120
0.01
0.1
Amplitude (VRMS)
1
10
C004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
OPA1688, OPA1689
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Device Family Comparison Table ........................
Pin Configuration and Functions .........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
9
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 21
1
1
1
2
3
3
3
5
10 Applications and Implementation...................... 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 28
12.1 Layout Guidelines ................................................. 28
12.2 Layout Example .................................................... 29
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: OPA1688 ................................ 6
Thermal Information: OPA1689 ................................ 6
Electrical Characteristics........................................... 7
Typical Characteristics: Table of Graphs .................. 9
Typical Characteristics ............................................ 10
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Detailed Description ............................................ 18
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
31
31
31
14 Mechanical, Packaging, and Orderable
Information ........................................................... 31
9.1 Overview ................................................................. 18
9.2 Functional Block Diagram ....................................... 18
4 Revision History
2
DATE
REVISION
NOTES
September 2015
*
Initial release.
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5 Device Comparison Table
(1)
DEVICE (1)
PACKAGE
OPA1688 (dual)
SOIC-8, WSON-8
OPA1689 (quad)
SOIC-14, VQFN-16
The OPA1688 SOIC-8 and WSON-8 packages are production data. The OPA1689 SOIC-14 and VQFN-16 packages are product
preview.
6 Device Family Comparison Table
DEVICE
QUIESCENT CURRENT
(IQ)
GAIN BANDWIDTH PRODUCT
(GBP)
VOLTAGE NOISE DENSITY
(en)
OPA168x
1650 µA
10 MHz
8 nV/√Hz
OPA165x
2000 µA
18 MHz
4.5 nV/√Hz
OPA166x
1500 µA
22 MHz
3.3 nV/√Hz
7 Pin Configuration and Functions
D Package: OPA1688
SOIC-8
Top View
OUT A
1
8
DRG Package: OPA1688
WSON-8
Top View
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
+IN A 1
A
V+ 2
V- 3
-IN A
7
OUT A
6
OUT B
5
-IN B
B
+IN B 4
D Package: OPA1689
SOIC-14
Top View
V+
4
11
V-
+IN A
1
+IN B
5
10
+IN C
V+
2
-IN B
6
9
-IN C
NC
3
OUT B
7
OUT C
+IN B
13 -IN D
+IN D
A
D
B
C
4
8
12
-IN C
3
14 OUT D
+IN A
7
-IN D
OUT C
13
15 OUT A
2
6
-IN A
OUT B
OUT D
5
14
-IN B
1
16 -IN A
RVA Package: OPA1689
VQFN-16
Top View
OUT A
8
8
12
+IN D
11
V-
10
NC
9
+IN C
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Pin Functions: OPA1688
PIN
OPA1688
D (SOIC)
DRG
(WSON)
I/O
+IN A
3
1
I
Noninverting input, channel A
+IN B
5
4
I
Noninverting input, channel B
–IN A
2
8
I
Inverting input, channel A
–IN B
6
5
I
Inverting input, channel B
OUT A
1
7
O
Output, channel A
OUT B
7
6
O
Output, channel B
V+
8
2
—
Positive (highest) power supply
V–
4
3
—
Negative (lowest) power supply
NAME
DESCRIPTION
Pin Functions: OPA1689
PIN
OPA1689
NAME
D
RVA
I/O
+IN A
3
1
I
Noninverting input, channel A
DESCRIPTION
+IN B
5
4
I
Noninverting input, channel B
+IN C
10
9
I
Noninverting input, channel C
+IN D
12
12
I
Noninverting input, channel D
–IN A
2
16
I
Inverting input, channel A
–IN B
6
5
I
Inverting input, channel B
–IN C
9
8
I
Inverting input, channel C
–IN D
13
13
I
Inverting input, channel D
OUT A
1
15
O
Output, channel A
OUT B
7
6
O
Output, channel B
OUT C
8
7
O
Output, channel C
OUT D
14
14
O
Output, channel D
V+
4
2
—
Positive (highest) power supply
V–
11
11
—
Negative (lowest) power supply
NC
—
3, 10
—
No connection
4
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VS
Signal input pins
Common-mode
Voltage (2)
(V–) – 0.5
MAX
UNIT
±20 (40, single supply)
V
(V+) + 0.5
V
Differential (3)
Current
Output short circuit (4)
–55
Junction temperature
Storage, Tstg
(1)
(2)
(3)
(4)
V
±10
mA
Continuous
Temperature range
Temperature
±0.5
–65
150
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Transient conditions that exceed these voltage ratings should be current limited to 10 mA or less.
See the Electrical Overstress section for more information.
Short-circuit to ground, one amplifier per package.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
85
°C
Specified temperature
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8.4 Thermal Information: OPA1688
OPA1688
THERMAL METRIC (1)
D (SOIC)
DRG (WSON)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
116.1
63.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.8
63.5
°C/W
RθJB
Junction-to-board thermal resistance
56.6
36.5
°C/W
ψJT
Junction-to-top characterization parameter
22.5
1.4
°C/W
ψJB
Junction-to-board characterization parameter
56.1
36.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
6.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
8.5 Thermal Information: OPA1689
OPA1689
THERMAL METRIC
(1)
D (SOIC)
RVA (VQFN)
14 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
82.7
TBD
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.3
TBD
°C/W
RθJB
Junction-to-board thermal resistance
37.3
TBD
°C/W
ψJT
Junction-to-top characterization parameter
8.9
TBD
°C/W
ψJB
Junction-to-board characterization parameter
37
TBD
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
TBD
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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8.6 Electrical Characteristics
At TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.00005%
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 2 kΩ
–126
G = 1, f = 1 kHz, VO = 3.5 VRMS , RL = 600 Ω
THD+N
Total harmonic distortion
+ noise
dB
0.000051%
–126
dB
0.000153%
G = 1, f = 1 kHz, PO = 10 mW, RL = 128 Ω
–116
dB
0.000357%
G = 1, f = 1 kHz, PO = 10 mW, RL = 32 Ω
–109
dB
0.000616%
G = 1, f = 1 kHz, PO = 10 mW, RL = 16 Ω
–104
dB
FREQUENCY RESPONSE
GBP
Gain bandwidth product
G=1
10
SR
Slew rate
G=1
8
V/µs
Full-power bandwidth (1)
VO = 1 VPP
1.3
MHz
Overload recovery time
VIN × gain > VS
200
ns
Channel separation
(dual)
f = 1 kHz
–120
dB
Settling time
To 0.1%, VS = ±18 V, G = 1, 10-V step
3
µs
Input voltage noise
f = 0.1 Hz to 10 Hz
2.5
en
Input voltage noise
density (2)
f = 100 Hz
14
in
Input current noise
density
tS
MHz
NOISE
En
f = 1 kHz
8
f = 1 kHz
1.8
µVPP
nV/√Hz
fA/√Hz
OFFSET VOLTAGE
TA = 25°C
±0.25
±1.5
VOS
Input offset voltage
dVOS/dT
VOS over temperature (2)
TA = –40°C to 85°C
±0.5
±2
µV/°C
PSRR
Power-supply rejection
ratio
TA = –40°C to 85°C
±1
±2.5
µV/V
Channel separation, dc
At dc
0.1
TA = 25°C
±10
TA = –40°C to 85°C
mV
±1.6
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
TA = –40°C to 85°C
TA = 25°C
±3
TA = –40°C to 85°C
±20
pA
±1.5
nA
±7
pA
±250
pA
(V+) – 2 V
V
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
range (3)
CMRR
Common-mode rejection
ratio
(V–) – 0.1 V
VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to 85°C
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to 85°C
90
104
104
120
dB
INPUT IMPEDANCE
(1)
(2)
(3)
Differential
100 || 7
MΩ || pF
Common-mode
6 || 1.5
1012Ω || pF
Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
Specified by design and characterization.
Common-mode range can extend to the top rail with reduced performance.
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Electrical Characteristics (continued)
At TA = 25°C, VS = ±2.25 V to ±18 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
108
130
MAX
UNIT
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 0.35 V < VO < (V+) – 0.35 V, RL = 10 kΩ,
TA = –40°C to 85°C
dB
(V–) + 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ,
TA = –40°C to 85°C
118
OUTPUT
IL = ±1 mA
VO
Voltage output swing
from rail
ZO
Open-loop output
impedance
ISC
Short-circuit current
CLOAD
Capacitive load drive
(V–) + 0.1 V
(V+) – 0.1 V
VS = 36 V, RL = 10 kΩ
70
90
VS = 36 V, RL = 2 kΩ
330
400
f = 1 MHz, IO = 0 A
mV
60
Ω
±75
mA
See the Typical Characteristics
pF
POWER SUPPLY
VS
Specified voltage range
IQ
Quiescent current per
amplifier
4.5
IO = 0 A
36
1.6
IO = 0 A, TA = –40°C to 85°C
1.8
2
V
mA
TEMPERATURE RANGE
8
Specified range
–40
85
°C
Operating range
–55
125
°C
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8.7 Typical Characteristics: Table of Graphs
Table 1. List of Typical Characteristics
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature (VS = ±18 V)
Figure 3
Offset Voltage vs Common-Mode Voltage (VS = ±18 V)
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 5
Offset Voltage vs Power Supply
Figure 6
Input Bias Current vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10
CMRR vs Temperature
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
Figure 14
THD+N Ratio vs Frequency
Figure 15
THD+N vs Output Amplitude
Figure 16
THD+N vs Frequency
Figure 17
THD+N vs Amplitude
Figure 18
Quiescent Current vs Temperature
Figure 19
Quiescent Current vs Supply Voltage
Figure 20
Open-Loop Gain and Phase vs Frequency
Figure 21
Closed-Loop Gain vs Frequency
Figure 22
Open-Loop Gain vs Temperature
Figure 23
Open-Loop Output Impedance vs Frequency
Figure 24
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 25, Figure 26
Positive Overload Recovery
Figure 27, Figure 28
Negative Overload Recovery
Figure 29, Figure 30
Small-Signal Step Response (10 mV, G = –1)
Figure 31
Small-Signal Step Response (10 mV, G = 1)
Figure 32
Small-Signal Step Response (100 mV, G = –1)
Figure 33
Small-Signal Step Response (100 mV, G = 1)
Figure 34
Large-Signal Step Response (10 V, G = –1)
Figure 35
Large-Signal Step Response (10 V, G = 1)
Figure 36
Large-Signal Settling Time (10-V Positive Step)
Figure 37
Large-Signal Settling Time (10-V Negative Step)
Figure 38
No Phase Reversal
Figure 39
Short-Circuit Current vs Temperature
Figure 40
Maximum Output Voltage vs Frequency
Figure 41
EMIRR vs Frequency
Figure 42
Channel Separation vs Frequency
Figure 43
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8.8 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1
0.9
0.8
0.7
0.6
0.5
0.4
5
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
-0.8
5
10
0.3
10
15
0.2
15
20
0.1
20
0
Percentage of Amplifiers (%)
25
-1
Percentage of Amplifiers (%)
25
Offset Voltage Drift (µV/ƒC)
Offset Voltage (mV)
C013
C013
Distribution taken from 5185 amplifiers
Distribution taken from 47 amplifiers,
temperature = –40°C to 125°C
Figure 2. Offset Voltage Drift Production Distribution
Figure 1. Offset Voltage Production Distribution
250
225
200
150
150
100
VCM = -18.1 V
75
VOS ( V)
50
VOS ( V)
VCM = 16 V
0
±50
0
±75
±100
±150
±150
±200
±250
±75
±50
±25
±225
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±10
0
±5
5
10
15
VCM (V)
5 typical units shown, VS = ±18 V
20
C001
5 typical units shown, VS = ±18 V
Figure 3. Offset Voltage vs Temperature
(VS = ±18 V)
Figure 4. Offset Voltage vs Common-Mode Voltage
(VS = ±18 V)
500
20
400
10
Vs = ± 2.25 V
300
0
200
VOS ( V)
VOS (mV)
±15
C001
-10
-20
100
0
±100
±200
-30
±300
-40
±400
±500
-50
14
15
16
17
VCM (V)
18
5 typical units shown, VS = ±18 V
Figure 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
10
0
2
4
6
8
10
12
14
16
VSUPPLY (V)
C001
18
C001
5 typical units shown, VS = ±2.25 V to ±18 V
Figure 6. Offset Voltage vs Power Supply
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
8000
12
Input Bias Current (pA)
Input Bias Current (pA)
IB+
IB Ios
IbP
10
8
6
IbN
4
2
0
5500
3000
500
Ios
±2
±2000
±4
-18
-13.5
-9
-4.5
0
4.5
9
13.5
VCM (V)
±50
18
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
C001
TA = 25°C
Figure 8. Input Bias Current vs Temperature
140
25°C
125°C
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
Figure 7. Input Bias Current vs Common-Mode Voltage
(V+) +1
(V+)
(V+) -1
(V+) -2
(V+) -3
(V+) -4
(V+) -5
(V-) +5
(V-) +4
(V-) +3
(V-) +2
(V-) +1
(V-)
(V-) -1
±40°C
85°C
85°C
125°C
±40°C
25°C
CMRR
120
PSRR+
100
80
PSRR-
60
40
20
0
0
10
20
30
40
50
60
70
80
90
Output Current (mA)
100
1
100
1k
10k
100k
Frequency (Hz)
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
1M
C006
Figure 10. CMRR and PSRR vs Frequency
(Referred-to-Input)
30
10
20
VS = ± 2.25 V, -
9 ” 9CM ”
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
10
C011
9
10
0
VS = “18 V, -
9 ” 9CM ”
9
±10
8
6
4
2
0
±2
±75
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
±75
±50
Figure 11. CMRR vs Temperature
±25
0
25
50
75
100
125
Temperature (ƒC)
C001
150
C001
Figure 12. PSRR vs Temperature
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
500 nV/div
9ROWDJH 1RLVH 'HQVLW\ Q9 ¥+]
1000
100
10
1
Time (1 s/div)
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C001
C002
Peak-to-peak noise = 1.70 µVPP
G = +1 V/V, 600G = -1 V/V, 10-k
0.001
G = -1 V/V, 2-k
G = -1 V/V, 600-
-80
Load
Load
Load
Load
-100
Load
Load
0.0001
-120
0.00001
1.
100
1k
10k
Frequency (Hz)
0.1
0.01
-120
-140
0.1
Output Amplitude (VRMS)
C008
-100
0.001
-120
-40
0.1
-60
Inverting
0.01
-80
Noninverting
0.001
Load
32-
Load
-100
Load
-120
0.01
0.1
1
Amplitude (VRMS)
C003
POUT = 10 mW, BW = 80 kHz, VS = ±5 V
16-
1280.0001
0.001
10000
Frequency (Hz)
1
Total Harmonic Distortion + Noise (%)
-80
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
G = -1, 16- Load
G = -1, 32- Load
G = -1, 128- Load
G = +1, 16- Load
G = +1, 32- Load
G = +1, 128- Load
0.0001
10
C004
f = 1 kHz, BW = 80 kHz, VS = ±5 V
Figure 17. THD+N vs Frequency
12
10
Figure 16. THD+N vs Output Amplitude
-60
1000
1
f = 1 kHz, BW = 80 kHz
Figure 15. THD+N Ratio vs Frequency
100
-80
0.0001
C007
0.1
10
-60
-100
VOUT = 3.5 VRMS, BW = 50 kHz
0.01
-40
0.001
0.00001
0.01
-140
10
G = +1 V/V, 10-k Load
G = +1 V/V, 2-k Load
G = -1 V/V, 10-k Load
G = -1 V/V, 2-k Load
G = -1 V/V, 600- Load
G = +1 V/V, 600- Load
Total Harmonic Distortion + Noise (dB)
G = +1 V/V, 2-k
Total Harmonic Distortion + Noise (dB)
G = +1 V/V, 10-k
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
0.01
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
Total Harmonic Distortion + Noise (dB)
Figure 13. 0.1-Hz to 10-Hz Noise
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Figure 18. THD+N vs Amplitude
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
2
2
1.9
1.8
1.8
1.7
IQ (mA)
IQ (mA)
Vs = ± 18 V
1.6
Vs = ± 2.25 V
1.4
1.6
1.5
1.4
1.3
1.2
1.2
1.1
1
1
±75
±50
±25
0
25
50
75
100
125
0
150
Temperature (ƒC)
8
12
16
20
24
28
32
36
Supply Voltage (V)
Figure 19. Quiescent Current vs Temperature
C001
Figure 20. Quiescent Current vs Supply Voltage
180
140
25
20
120
100
15
135
Open-loop Gain
Phase
60
90
40
Gain (dB)
10
80
Phase (º)
Gain (dB)
4
C001
5
0
-5
20
45
-10
0
G = +1
G = -10
G = -1
-15
±20
1
10
100
1k
10k
100k
1M
0
10M
-20
1000
Frequency (Hz)
10k
100k
1M
10M
Frequency (Hz)
C004
C003
CLOAD = 15 pF
Figure 21. Open-Loop Gain and Phase vs Frequency
Figure 22. Closed-Loop Gain vs Frequency
2
1000
1.5
100
Vs = 4.5 V
ZO ( )
AOL (µV/V)
1
0.5
10
Vs = 36 V
0
1
-0.5
-1
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
C001
100M
C016
RL = 10 kΩ
Figure 23. Open-Loop Gain vs Temperature
Figure 24. Open-Loop Output Impedance vs Frequency
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
50
60
40
40
Overshoot (%)
Overshoot (%)
50
30
20
ROUT = 0
10
100
200
300
400
Capacitive Load (pF)
ROUT= 0
ROUT
25
RO
==25
ROUT
= 50
RO
= 50
0
20
10
ROUT
= 25
RO
= 25
0
30
RO
==50
ROUT
50
0
500
0
100
200
300
400
Capacitive Load (pF)
C013
G = –1
500
C013
G=1
Figure 25. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 26. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
5 V/div
5V/div
VOUT
VOUT
VIN
VIN
Time (1 s/div)
Time (1 s/div)
C009
C011
Figure 27. Positive Overload Recovery
Figure 28. Positive Overload Recovery (Zoomed In)
VIN
5 V/div
5 V/div
VIN
VOUT
VOUT
Time (1 s/div)
Time (1 s/div)
C010
Figure 29. Negative Overload Recovery
14
C010
Figure 30. Negative Overload Recovery (Zoomed In)
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Typical Characteristics (continued)
2 mV/div
2 mV/div
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
Time (200 ns/div)
Time (200 ns/div)
C006
C014
RL = 1 kΩ, CL = 10 pF
CL = 10 pF
Figure 32. Small-Signal Step Response (10 mV, G = 1)
20 mV/div
20 mV/div
Figure 31. Small-Signal Step Response (10 mV, G = –1)
Time (200 ns/div)
Time (200 ns/div)
C006
C014
RL = 1 kΩ, CL = 10 pF
CL = 10 pF
Figure 34. Small-Signal Step Response (100 mV, G = 1)
2 V/div
2 V/div
Figure 33. Small-Signal Step Response (100 mV, G = –1)
Time (500 ns/div)
Time (500 ns/div)
C005
C014
RL = 1 kΩ, CL = 10 pF
CL = 10 pF
Figure 35. Large-Signal Step Response (10 V, G = –1)
Figure 36. Large-Signal Step Response (10 V, G = 1)
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
20
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
20
15
10
5
0
-5
-10
-15
-20
15
10
5
0
±5
±10
±15
±20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time ( s)
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time ( s)
C034
G = 1, CL = 10 pF, 0.1% settling = ±10 mV
C030
G = 1, CL = 10 pF, 0.1% settling = ±10 mV
Figure 37. Large-Signal Settling Time (10-V Positive Step)
Figure 38. Large-Signal Settling Time (10-V Negative Step)
100
VOUT
75
ISC (mA)
5 V/div
ISC, Sink “ 18 V
50
ISC, Source ± 18 V
25
VIN
0
Time (200 s/div)
±75
±50
Figure 39. No Phase Reversal
0
25
50
75
100
125
150
C001
Figure 40. Short-Circuit Current vs Temperature
160
30
VS = ±15 V
140
Maximum output voltage without
slew-rate induced distortion.
25
120
20
EMIRR (dB)
Output Voltage (VPP)
±25
Temperature (ƒC)
C011
15
VS = ±5 V
10
80
60
40
VS = ±2.25 V
5
100
20
0
0
10k
100k
1M
Frequency (Hz)
10M
10M
100M
1G
Frequency (Hz)
C033
10G
C017
PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V
Figure 41. Maximum Output Voltage vs Frequency
16
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Figure 42. EMIRR vs Frequency
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
0
Channel Separation (dB)
±20
±40
±60
±80
±100
±120
±140
±160
100
1k
10k
100k
1M
Frequency (Hz)
10M
C027
Figure 43. Channel Separation vs Frequency
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9 Detailed Description
9.1 Overview
The OPA168x family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1.5 µV/°C (max) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
The Functional Block Diagram section shows the simplified diagram of the OPA168x design. The design
topology is a highly-optimized, three-stage amplifier with an active-feedforward gain stage.
9.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
2nd Stage
Output
Stage
OUT
-IN
NCH
Input Stage
18
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9.3 Feature Description
9.3.1 EMI Rejection
The OPA168x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPA168x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 44 shows the results of this testing on the OPA168x. Table 2 shows the EMIRR IN+ values for the
OPA168x at particular frequencies commonly encountered in real-world applications. Applications listed in
Table 2 can be centered on or operated near the particular frequency shown. Detailed information can also be
found in application report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
160
140
EMIRR (dB)
120
100
80
60
40
20
0
10M
100M
1G
Frequency (Hz)
10G
C017
PRF = –10 dBm, VSUPPLY = ±18 V, VCM = 0 V
Figure 44. EMIRR Testing
Table 2. OPAx168x EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, and ultrahigh
frequency (UHF) applications
47.6 dB
900 MHz
Global system for mobile communications (GSM) applications, radio
communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, and
UHF applications
58.5 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, and Lband (1 GHz to 2 GHz)
68 dB
®
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal communications,
industrial, scientific and medical (ISM) radio band, amateur radio and satellite, and
S-band (2 GHz to 4 GHz)
69.2 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, and S-band
82.9 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile communication,
space and satellite operation, and C-band (4 GHz to 8 GHz)
114 dB
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9.3.2 Phase-Reversal Protection
The OPA168x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA168x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 45.
5 V/div
VOUT
VIN
Time (200 s/div)
C011
Figure 45. No Phase Reversal
9.3.3 Capacitive Load and Stability
The dynamic characteristics of the OPA168x are optimized for commonly-used operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
may lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT = 50 Ω) in series with the
output. Figure 46 and Figure 47 show graphs of small-signal overshoot versus capacitive load for several values
of ROUT; see application bulletin SBOA015 (AB-028), Feedback Plots Define Op Amp AC Performance, available
for download from www.ti.com, for details of analysis techniques and application circuits.
50
60
40
40
Overshoot (%)
Overshoot (%)
50
30
20
ROUT = 0
10
100
200
300
Capacitive Load (pF)
400
ROUT= 0
ROUT
25
RO
==25
ROUT
= 50
RO
= 50
0
20
10
ROUT
= 25
RO
= 25
0
30
RO
==50
ROUT
50
0
500
0
G = –1
200
300
400
500
C013
G=1
Figure 46. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
20
100
Capacitive Load (pF)
C013
Figure 47. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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9.4 Device Functional Modes
9.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPA168x series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 3.
Table 3. Typical Performance Range (VS = ±18 V)
PARAMETER
MIN
Input common-mode voltage
TYP
(V+) – 2
Offset voltage
MAX
(V+) + 0.1
UNIT
V
5
mV
Offset voltage vs temperature (TA = –40°C to 85°C)
10
µV/°C
Common-mode rejection
70
dB
Open-loop gain
60
dB
4
MHz
Gain bandwidth product (GBP)
Slew rate
Noise at f = 1 kHz
4
V/µs
22
nV/√Hz
9.4.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful.
Figure 48 illustrates the ESD circuits contained in the OPA168x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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TVS
+
±
RF
+VS
R1
IN±
250 Ÿ
RS
IN+
250 Ÿ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 48. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption
device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA168x but below
the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (Figure 48), the ESD protection components are intended
to remain inactive and do not become involved in the application circuit operation. However, circumstances may
arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there
is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs
through steering-diode paths and rarely involves the absorption device.
Figure 48 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
22
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Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (+VS or –VS) are at 0 V. Again, this question depends on the supply characteristic when at
0 V, or at a level below the input-signal amplitude. If the supplies appear as high impedance, then the input
source supplies the operational amplifier current through the current-steering diodes. This state is not a normal
bias condition; most likely, the amplifier will not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external zener diodes to the
supply pins; see Figure 48. Select the zener voltage so that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The OPA168x input pins are protected from excessive differential voltage with back-to-back diodes; see
Figure 48. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1
circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the input signal current. This input series resistor degrades the low-noise
performance of the OPA168x. Figure 48 illustrates an example configuration that implements a current-limiting
feedback resistor.
9.4.3 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from the saturated state to
the linear state. The output devices of the op amp enter the saturation region when the output voltage exceeds
the rated operating voltage, either resulting from the high input voltage or the high gain. After the device enters
the saturation region, the charge carriers in the output devices need time to return back to the normal state. After
the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. Thus,
the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew
time. The overload recovery time for the OPA168x is approximately 200 ns.
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10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The OPA168x family of amplifiers is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to 85°C. Parameters that can exhibit significant variance with regard to operating
voltage or temperature are presented in the Typical Characteristics.
10.2 Typical Application
This application example highlights only a few of the circuits where the OPA168x can be used.
C1
47pF
ROUT
R1
768
R2
750
-5 V
VAC
+
VDC
++
VAC
ROUT
Audio DAC
R3
768
OPA1688
Headphone
Output
5V
R4
750
C2
47pF
Figure 49. Headphone Amplifier Circuit Configuration for Audio DACs that Output a Differential Voltage
(Single Channel Shown)
10.2.1 Design Requirements
The design requirements are:
•
•
•
•
24
Supply voltage: 10 V (±5 V)
Headphone loads: 16 Ω to 600 Ω
THD+N: > 100 dB (1-kHz fundamental, 1 VRMS in 32 Ω, 22.4-kHz measurement bandwidth)
Output power (before clipping): 50 mW into 32 Ω
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Typical Application (continued)
10.2.2 Detailed Design Procedure
The OPA168x family offers an excellent combination of specifications for headphone amplifier circuits (such as
low noise, low distortion, capacitive load stability, and relatively high output current). Furthermore, the low-power
supply current and small package options make the OPA1688 an exceptionally good choice for headphone
amplifiers in portable devices. A common headphone amplifier circuit for audio digital-to-analog converters
(DACs) with differential voltage outputs is illustrated in Figure 49. This circuit converts the differential voltage
output of the DAC to a single-ended, ground-referenced signal and provides the additional current necessary for
low-impedance headphones. For R2 = R4 and R1 = R3, the output voltage of the circuit is given by Equation 1:
R2
VOUT = 2 u VAC
R 1 + R OUT
where
•
•
ROUT is the output impedance of the DAC and
2 × VAC is the unloaded differential output voltage
(1)
The output voltage required for headphones depends on the headphone impedance as well as the headphone
efficiency. Both values can be provided by the headphone manufacturer, with headphone efficiency usually given
as a sound pressure level (SPL) produced with 1 mW of input power and denoted by the Greek letter η. The SPL
at other input power levels can be calculated from the efficiency specification using Equation 2:
§ P
·
SPL (dB) K 10 log ¨ IN ¸
1
mW
©
¹
(2)
Note that at extremely high power levels, the accuracy of this calculation decreases as a result of secondary
effects in the headphone drivers. Figure 50 allows the SPL produced by a pair of headphones of a known
sensitivity to be estimated for a given input power.
10000
1000
90-dB SPL
95-dB SPL
100-dB SPL
105-dB SPL
110-dB SPL
115-dB SPL
120-dB SPL
Power (mW)
100
10
1
0.1
0.01
90
95
100
105
110
115
Headphone Efficiency (dB/mW)
C001
Figure 50. SPLs Produced for Various Headphone Efficiencies and Input Power Levels
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Typical Application (continued)
For example, a pair of headphones with a 95-dB/mW sensitivity given a 3-mW input signal produces a 100-dB
SPL. If these headphones have a nominal impedance of 32 Ω, then the voltage and current from the headphone
amplifier is as described in Equation 3 and Equation 4, respectively:
V
I
PIN u RHP
PIN
RHP
3 mW u 32 :
3 mW
32 :
310 mVRMS
(3)
9.68 mARMS
(4)
Headphones can present a capacitive load at high frequencies that can destabilize the headphone amplifier
circuit. Many headphone amplifiers use a resistor in series with the output to maintain stability; however this
solution also compromises audio quality. The OPA168x family is able to maintain stability into large capacitive
loads; therefore, a series output resistor is not necessary in the headphone amplifier circuit. TINA-TI™
simulations illustrate that the circuit in Figure 49 has a phase margin of approximately 50 degrees with a 400-pF
load connected directly to the amplifier output.
10.2.3 Application Curves
The headphone amplifier circuit in Figure 49 is tested with three common headphone impedances: 16 Ω, 32 Ω,
and 600 Ω. The total harmonic distortion and noise (THD+N) for increasing output voltages is given in Figure 51.
This measurement is performed with a 1-kHz input signal and a measurement bandwidth of 22.4 kHz. The
maximum output power and THD+N before clipping are given in Table 4. The maximum output power into lowimpedance headphones is limited by the output current capabilities of the amplifier. For high-impedance
headphones (600 Ω), the output voltage capabilities of the amplifier are the limiting factor. The circuit in Figure 49
is tested using ±5-V supplies that are common in many portable systems. However, using higher supply voltages
increases the output power into 600-Ω headphones.
Total Harmonic Distortion + Noise (dB)
0
-20
-40
-60
-80
-100
-120
0.001
0.01
0.1
1
10
Amplitude (VRMS)
C002
Figure 51. THD+N for Increasing Output Voltages Into Three Load Impedances
(Input Signal = 1 kHz, Measurement Bandwidth = 22.4 kHz)
26
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Typical Application (continued)
Table 4. Maximum Output Power and THD+N Before Clipping for Different Load Impedances
LOAD IMPEDANCE (Ω)
MAXIMUM OUTPUT POWER BEFORE
CLIPPING (mW)
THD+N AT MAXIMUM OUTPUT POWER
(dB)
16
32
–104.1
32
50
–109.5
600
16
–117.8
Figure 52, Figure 53, and Figure 54 further illustrate the exceptional performance of the OPA1688 as a
headphone amplifier.
Figure 52 shows the THD+N over frequency for a 500-mVRMS output signal into the same three load impedances
previously tested.
0
0
±20
±20
±40
Amplitude (dBc)
Total Harmonic Distortion + Noise (dB)
Figure 53 and Figure 54 show the output spectrum of the OPA1688 at low (1 mW) and high (50 mW) output
power levels into a 32-Ω load. The distortion harmonics in both cases are approximately 120 dB below the
fundamental.
±40
±60
±80
±60
±80
±100
±120
±100
±140
±120
±160
10
100
1000
10000
Frequency (Hz)
0
5000
10000
15000
Frequency (Hz)
C003
Figure 52. THD+N Measured over Frequency (90-kHz
Measurement Bandwidth) for a 500-mVRMS Output Level
20000
C001
Figure 53. Output Spectrum of a
1-mW, 1-kHz Tone into a 32-Ω Load
(The third harmonic is dominant at a level of –117.6 dB
relative to the fundamental.)
0
±20
Amplitude (dBc)
±40
±60
±80
±100
±120
±140
±160
0
5000
10000
15000
Frequency (Hz)
20000
C001
Figure 54. Output Spectrum of a 50-mW, 1-kHz Tone Into a
32-Ω Load, Immediately Below the Onset of Clipping
(The highest harmonic is the second harmonic at
–119 dB below the fundamental.)
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11 Power Supply Recommendations
The OPA168x is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
12 Layout
12.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed
information, see SLOA089, Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 55, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
28
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12.2 Layout Example
RIN
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
NC
NC
±IN
V+
+IN
OUT
V±
NC
RG
GND
VIN
GND
RIN
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 55. Operational Amplifier Board Layout for a Noninverting Configuration
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
13.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
13.2 Documentation Support
13.2.1 Related Documentation
SBOA015 (AB-028) — Feedback Plots Define Op Amp AC Performance
SBOA128 — EMI Rejection Ratio of Operational Amplifiers
SLOA089 — Circuit Board Layout Techniques
SLOD006 — Op Amps for Everyone
TIPD128 — Capacitive Load Drive Solution using an Isolation Resistor
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA1688
Click here
Click here
Click here
Click here
Click here
OPA1689
Click here
Click here
Click here
Click here
Click here
13.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
30
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13.5 Trademarks
E2E is a trademark of Texas Instruments.
SoundPlus is a trademark of Texas Instruments, Inc.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Blu-Ray is a trademark of Blu-ray Disc Association (BDA).
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA1688ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1688A
OPA1688IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
O1688A
OPA1688IDRGR
ACTIVE
SON
DRG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP1688
OPA1688IDRGT
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OP1688
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA1688IDRGR
SON
DRG
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
OPA1688IDRGT
SON
DRG
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA1688IDRGR
SON
DRG
8
3000
367.0
367.0
35.0
OPA1688IDRGT
SON
DRG
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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