TI1 CDC3RL02BYFPR Low phase-noise two-channel clock fan-out buffer Datasheet

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CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer
1 Features
3 Description
•
The CDC3RL02 is a two-channel clock fan-out buffer
and is ideal for use in portable end-equipment, such
as mobile phones, that require clock buffering with
minimal additive phase noise and fan-out capabilities.
It buffers a single master clock, such as a
temperature compensated crystal oscillator (TCXO)
to multiple peripherals. The device has two clock
request inputs (CLK_REQ1 and CLK_REQ2), each of
which enable a single clock output.
1
•
•
•
•
•
Low Additive Noise:
– –149 dBc/Hz at 10-kHz Offset Phase Noise
– 0.37 ps (RMS) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1- to 5-ns Rise/Fall Time for 10-pF to 50-pF
Loads)
Adaptive Output Stage Controls Reflection
Regulated 1.8-V Externally Available I/O Supply
Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP
(0.8 mm × 1.6 mm)
ESD Performance Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model
(JESD22-C101-A Level III)
2 Applications
•
•
•
•
•
•
Cellular Phones
Global Positioning Systems (GPS)
Wireless LAN
FM Radio
WiMAX
W-BT
The CDC3RL02 has an integrated Low-Drop-Out
(LDO) voltage regulator which accepts input voltages
from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This
1.8-V supply is externally available to provide
regulated power to peripheral devices such as a
TCXO.
Simplified Block Diagram
VBATT
GND
VLDO
LDO
VCC
The CDC3RL02 accepts square or sine waves at the
master clock input (MCLK_IN), eliminating the need
for an AC coupling capacitor. The smallest
acceptable sine wave is a 0.3-V signal (peak-topeak). CDC3RL02 has been designed to offer
minimal channel-to-channel skew, additive output
jitter, and additive phase noise. The adaptive clock
output buffers offer controlled slew-rate over a wide
capacitive loading range which minimizes EMI
emissions, maintains signal integrity, and minimizes
ringing caused by signal reflections on the clock
distribution lines.
The CDC3RL02 is offered in a 0.4-mm pitch waferlevel chip-scale (WCSP) package (0.8 mm × 1.6 mm)
and is optimized for very low standby current
consumption.
Device Information(1)
CLK_OUT1
EN
CLK_REQ1
PART NUMBER
CDC3RL02
MCLK_IN
VCC
CLK_OUT2
EN
CLK_REQ2
PACKAGE
DSBGA (8)
BODY SIZE (NOM)
0.80 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Switch/
Decoder
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2015) to Revision C
•
Added the Device Comparison Table .................................................................................................................................... 3
Changes from Revision A (September 2015) to Revision B
•
2
Page
Added Thermal Information table, Overview, Feature Description section, Power Supply Recommendations section,
and Layout section ................................................................................................................................................................. 1
Changes from Original (November 2009) to Revision A
•
Page
Page
Formatted document to new standards. ................................................................................................................................. 1
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5 Device Comparison Table
TA
(1)
(2)
PACKAGE
(1)
ORDERABLE PART NUMBER
BACKSIDE
COATING (2)
-40 C to 85 C
YFP
CDC3RL02BYFPR
Yes
-40 C to 85 C
YFP
CDC3RL02YFPR
No
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
CSP (DSBGA) devices manufactured with backside coating have an increased resistance to cracking due to the increased physical
strength of the package. Devices with backside coating are highly encouraged for new designs.
6 Pin Configuration and Functions
YFP Package
8-Pin DSBGA
Top View
1
2
A
A1
A2
B
B1
B2
C
C1
C2
D
D1
D2
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VBATT
A1
I
Input to internal LDO
CLK_OUT1
A2
O
Clock output 1
VLDO
B1
O
1.8 V I/O supply for CDC3RL02 and external TCXO
CLK_REQ1
B2
I
Clock request from peripheral 2
MCLK_IN
C1
I
Master clock input
CLK_REQ2
C2
I
Clock request from peripheral 1
GND
D1
–
Ground
CLK_OUT2
D2
O
Clock output 2
YFP Package Pin Assignments
A
1
2
VBATT
CLK_OUT1
B
VLDO
CLK_REQ1
C
MCLK_LIN
CLK_REQ2
D
GND
CLK_OUT2
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted.
VBATT
(1)
MIN
MAX
UNIT
–0.3
7
V
CLK_REQ_1/2, MCLK_IN
–0.3
VBATT + 0.3
VLDO, CLK_OUT_1/2 (2)
–0.3
VBATT + 0.3
Voltage range (2)
Voltage range (3)
V
IIK
Input clamp current at VBATT,
CLK_REQ_1/2, and MCLK_IN
VI < 0
–50
mA
IO
Continuous output current
CLK_OUT1/2
±20
mA
±50
mA
Continuous current through GND, VBATT, VLDO
TJ
Operating virtual junction temperature
–40
150
°C
TA
Operating ambient temperature range
–40
85
°C
Tstg
Storage temperature range
–55
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
All voltage values are with respect to network ground pin.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine Model
(1)
(2)
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
See
(1)
MIN
MAX
2.3
5.5
V
0
1.89
V
0
1.8
V
1.3
1.89
V
0.5
V
VBATT
Input voltage to internal LDO
VI
Input voltage
MCLK_IN, CLK_REQ1/2
VO
Output voltage
CLK_OUT1/2
VIH
High-level input voltage
CLK_REQ1/2
VIL
Low-level input voltage
CLK_REQ1/2
0
IOH
High-level output current, DC current
IOL
Low-level output current, DC current
(1)
4
–8
UNIT
mA
8
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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7.4 Thermal Information
CDC3RL02
THERMAL METRIC (1)
YFP (TSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
1.3
°C/W
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
4.5
°C/W
ψJB
Junction-to-board characterization parameter
18.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.71
1.8
1.89
V
LDO
VOUT
LDO output voltage
CLDO
External load capacitance
IOUT(SC)
Short circuit output current
RL = 0 Ω
IOUT(PK)
Peak output current
VBATT = 2.3 V, VLDO = VOUT – 5%
PSR
Power supply rejection
VBATT = 2.3 V, IOUT = 2 mA,
tsu
LDO startup time
IOUT = 50 mA
1
μF
10
100
mA
100
fIN= 217 Hz and 1 kHz
60
fIN= 3.25 MHz
40
VBATT = 2.3 V , CLDO = 1 μF,
CLK_REQ_n to VLDO = 1.71 V
mA
dB
0.2
ms
VBATT = 5.5 V , CLDO = 10 μF,
CLK_REQ_n to VLDO = 1.71 V
1
POWER CONSUMPTION
ISB
Standby current
Device in standby (all VCLK_REQ_n = 0 V)
0.2
1
μA
ICCS
Static current consumption
Device active but not switching
0.4
1
mA
IOB
Output buffer average current
fIN = 26 MHz, CLOAD = 50 pF
4.2
CPD
Output power dissipation
capacitance
fIN = 26 MHz
mA
44
pF
1
μA
MCLK_IN INPUT
II
MCLK_IN, CLK_REQ_1/2 leakage
current
VI = VLDO or GND
CI
MCLK_IN capacitance
fIN = 26 MHz
4.75
pF
RI
MCLK_IN impedance
fIN = 26 MHz
6
kΩ
fIN
MCLK_IN frequency range
10
26
52
MHz
MCLK_IN LVCMOS SOURCE
1-kHz offset
–140
10-kHz offset
–149
100-kHz offset
–153
Additive phase noise
fIN = 26 MHz, tr/tf ≤ 1 ns
1-MHz offset
–148
Additive jitter
fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz
0.37
tDL
MCLK_IN to CLK_OUT_n
propagation delay
DCL
Output duty cycle
dBc/Hz
ps (rms)
11
fIN = 26 MHz, DCIN = 50%
45%
50%
ns
55%
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MCLK_IN SINUSOIDAL SOURCE
VMA
Input amplitude
0.3
fIN = 26 MHz, VMA = 1.8 VPP
Additive phase noise
fIN = 26 MHz, VMA = 0.8 VPP
Additive jitter
tDS
MCLK_IN to CLK_OUT_1/2
propagation delay
DCs
Output duty cycle
1.8
1-kHz offset
–141
10-kHz offset
–149
100-kHz offset
–152
1-MHz offset
–148
1-kHz offset
–139
10-kHz offset
–146
100-kHz offset
–150
1-MHz offset
–146
fIN = 26 MHz, VMA = 1.8 VPP, BW = 10–5 MHz
dBc/Hz
0.41
ps (RMS)
12
fIN = 26 MHz, VMA > 1.8 VPP
45%
50%
V
ns
55%
CLK_OUT_N OUTPUTS
tr
20% to 80% rise time
CL = 10 pF to 50 pF
1
5.2
ns
tf
20% to 80% fall time
CL = 10 pF to 50 pF
1
5.2
ns
tsk
Channel-to-channel skew
CL = 10 pF to 50 pF (CL1 = CL2)
–0.5
0.5
ns
IOH = –100 μA, reference to VLDO
–0.1
VOH
High-level output voltage
VOL
Low-level output voltage
6
IOH = –8 mA
V
1.2
IOL = 20 μA
0.2
IOL = 8 mA
0.55
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7.6 Typical Characteristics
-90
3.54
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.52
3.51
-110
3.50
3.49
-120
3.48
Square Wave 1.8 V 1 µF
ICC (mA)
Additive Phase Noise (dBc/Hz)
-100
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.53
-130
Sine Wave 0.8 Vpp 1 µF
-140
TA = 85°C
3.47
3.46
3.45
TA = 25°C
3.44
3.43
-150
3.42
3.41
Sine Wave 1.8 Vpp 1 µF
-160
TA = -40°C
3.40
3.39
-170
1.E+01
3.38
1.E+02 1.E+03
1.E+04
1.E+05 1.E+06
0.3
1.E+07
0.6
Offset Frequency (Hz)
Figure 1. Additive Phase Noise vs Offset Frequency
3.50
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
TA = -40°C
1.5
1.8
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
3.49
3.48
TA = 25°C
TA = 85°C
3.47
TA = 85°C
6
3.46
3.45
5
ICC (mA)
Supply Current (mA)
1.2
Figure 2. Supply Current vs Input Amplitude
8
7
0.9
Input Am plitude (Vpp)
4
3
3.44
TA = 25°C
3.43
3.42
3.41
TA = -40°C
3.40
2
3.39
3.38
1
3.37
0
3.36
0
10
20
30
40
50
60
70
2.3
2.7
3.1
Frequency (MHz)
180
160
4.3
4.7
5.1
5.5
Figure 4. Supply Current vs Supply Voltage
0
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
-10
-20
5.5 V
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
-30
140
3.3 V
-40
PSRR (dB)
120
ISB (nA)
3.9
V BATT (V)
Figure 3. Supply Current vs Input Frequency
200
3.5
2.3 V
100
80
-50
-60
-70
60
-80
40
-90
20
-100
0
-40
-15
10
35
60
85
-110
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Tem perature (°C)
Figure 5. Standby Current vs Temperature
Figure 6. Power Supply Rejection vs Input Frequency
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Typical Characteristics (continued)
2.4
5.0
VBATT = 3.3 V CVLDO = 1 µF
CBATT = 0.1 µF COUT = 30 pF
2.2
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
4.5
2.0
1.8
4.0
1.6
3.5
TA = 25°C
TA = -40°C
Time (ns)
1.4
Voltage (V)
TA = 85°C
1.2
1.0
0.8
3.0
2.5
2.0
0.6
1.5
0.4
1.0
0.2
0.0
0.5
-0.2
MCLK_IN
CLK_OUT1
0.0
-0.4
0
10
20
30
40
50 60
Tim e (ns)
70
80
90
0
100
10
VBATT = 3.3 V
CVLDO = 1 µF
CBATT = 0.1 µF
COUT = 30 pF
4.5
4.0
30
40
50
60
70
CLOAD (pF)
Figure 7. Sine-Wave Input vs Square-Wave Output
5.0
20
Figure 8. Rise Time vs Load
MCLK_IN
0.5 V/div
CLK_OUT1
0.5 V/div
CLK_OUT2
10 mV/div
TA = 85°C
TA = 25°C
Time (ns)
3.5
TA = -40°C
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
60
70
0
20
40
60
CLOAD (pF)
Figure 9. Fall Time vs Load
8
80
100
120
140
160
180
200
Time (ns)
Figure 10. Digital Cross-Talk Scope Shot
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8 Detailed Description
8.1 Overview
The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as
mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a
single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The
device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.
The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an
AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has been
designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive
clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI
emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution
lines.
The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3
V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide regulated power to
peripheral devices such as a TCXO.
8.2 Functional Block Diagram
VBATT
VLDO
LDO
VCC
GND
CLK_OUT1
EN
CLK_REQ1
VCC
MCLK_IN
CLK_OUT2
EN
CLK_REQ2
Switch/
Decoder
8.3 Feature Description
8.3.1 Low Additive Noise
The CDC3RL02 features –149 dBc/Hz at 10 kHz offset phase noise and 0.37 ps (RMS) of output jitter, to make
sure that the buffered signals are clean.
8.3.2 Regulated 1.8-V Externally Available I/O Supply
The CDC3RL02 allows users to connect to the output of the internal LDO, for providing power to other ICs. For
more information, refer to LDO.
8.3.3 Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
Using the ultra-small YFP package, the CDC3RL02 is very small and allows it to be placed on a board with
minimum work.
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8.4 Device Functional Modes
Table 1 is the function table for CDC3RL02.
Table 1. Function Table
INPUTS
10
OUTPUTS
CLK_REQ1
CLK_REQ2
MCLK_IN
CLK_OUT1
CLK_OUT2
L
L
X
L
L
CLK
L
H
CLK
L
H
L
CLK
CLK
L
H
H
CLK
CLK
CLK
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Clock Squarer
Figure 11 shows the input stage of the CDC3RL02. The input signal at MCLK_IN can be a square wave or sine
wave. CMCLK is an internal AC coupling capacitor that allows a direct connection from the TCXO to the
CDC3RL02 without an external capacitor.
MCLK _IN
CMCLK
Figure 11. Input Stage with Internal AC Coupling Capacitor
Any external component added in the series path of the clock signal will potentially add phase noise and jitter.
The error source associated with the internal decoupling capacitor is included in the specification of the
CDC3RL02. The recommended clock frequency band of the CDC3RL02 is 10 MHz to 52 MHz for specified
functionality. All performance metrics are specified at 26 MHz. The lowest acceptable sinusoidal signal amplitude
is 0.8 VPP for specified performance. Amplitudes as low as 0.3 VPP are acceptable but with reduced phase-noise
and jitter performance.
9.1.2 Output Stage
Each output drives 1.8-V LVCMOS levels. Adaptive output buffers limit the rise/fall time of the output to within 1
ns to 5 ns with load capacitance between 10 pF and 50 pF. Fast slew rates introduce EMI into the system. Each
output buffer limits EMI by keeping the rise/fall time above 1 ns. Slow rise/fall times can induce additive phase
noise and duty cycle errors in the load device. The output buffer limits these errors by keeping the rise/fall time
below 5 ns. In addition, the output stage dynamically alters impedance based on the instantaneous voltage level
of the output. This dynamic change limits reflections keeping the output signal monotonic during transitions. Each
output is active low when not requested to avoid false clocking of the load device.
9.1.3 LDO
A low noise 1.8-V LDO is integrated to provide the I/O supply for the output buffers. The LDO output is externally
available to power a clock source such as a TCXO. A clean supply is provided to the clock buffers and the clock
source for optimum phase noise performance. The input range of the LDO allows the device to be powered
directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,
the device enters a low power shutdown mode consuming less than 1 μA from the battery. The LDO requires an
output decoupling capacitor in the range of 1 μF to 10 μF for compensation and high frequency PSR. This
capacitor must stay within the specified range over the entire operating temperature range. An input bypass
capacitor of 1 μF or larger is recommended.
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9.2 Typical Application
The CDC3RL02 is ideal for use in mobile applications as shown in Figure 12. In this example, a single low noise
TCXO system clock source is buffered to drive a mobile GPS receiver and WLAN transceiver. Each peripheral
independently requests an active clock by asserting a single clock request line (CLK_REQ_1 or CLK_REQ_2).
When both clock request lines are inactive, the CDC3RL02 enters a low current shutdown mode. In this mode,
the LDO output, CLK_OUT_1, and CLK_OUT_2 are pulled to GND and the TCXO will be unpowered.
VLDO
VBATT
LDO
2.2 µF
1 µF
Li
GPS
CLK_REQ_1
TCXO REQ
CLK_OUT_1
MCLK_IN
TCXO CLK
CLK_REQ_2
TCXO REQ
CLK_OUT_2
TCXO CLK
TCXO
CDC3RL02
WLAN
GND
Figure 12. Mobile Application
When either peripheral requests the clock, the CDC3RL02 will enable the LDO and power the TCXO. The TCXO
output (square wave, sine wave, or clipped sine wave) is converted to a square wave and buffered to the
requested output.
9.2.1 Design Requirements
For the typical application, the user must know the following parameters.
Table 2. Design Parameters
PARAMETER
DESCRIPTION
VBATT
Input voltage from battery or power supply
EXAMPLE VALUE
3.7 V
MCLK_IN
Input frequency from a TCXO
26 MHz
9.2.2 Detailed Design Procedure
The designer must make sure that all parameters are within the ranges specified in Recommended Operating
Conditions.
Each device which receives a clock output from the CDC3RL02 should have the CLK request pin connected to
the appropriate CLK_REQ pin on the CDC3RL02. This will enable the output buffer when a device requests the
clock signal.
It is possible to have a control the outputs of the clock by using a GPIO from a controller to control the CLK_REQ
pins.
If one of the outputs is unused, then tie the CLK_REQ and CLK_OUT pins to ground. If the clock will always be
required, and the user wishes, it is acceptable to tie the CLK_REQ pin to a 1.8 V source (such as VLDO).
12
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CDC3RL02
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SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
9.2.3 Application Curves
2.4
VBATT = 3.3 V CVLDO = 1 µF
CBATT = 0.1 µF COUT = 30 pF
2.2
2.0
1.8
1.6
Voltage (V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
MCLK_IN
CLK_OUT1
-0.4
0
10
20
30
40
50 60
Tim e (ns)
70
80
90
100
Figure 13. Sine Wave Input vs Output
10 Power Supply Recommendations
General power supply recommendations are to be considered for the CDC3RL02. These include:
• Decoupling capacitors placed close to the VBATT pin of typical values (1 μF)
• VBATT be within the recommended voltage range
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the VBATT
pin
• Short trace-lengths should be used to avoid excessive loading
• For improved performance on the clock output lines, use a ground trace on the sides of the clock trace to
minimize crosstalk and EMI
11.2 Layout Example
CLK_OUT1
0402 Decoupling
Cap
VBATT
A1
VLDO
CLK_REQ1
MCLK_IN
CLK_REQ2
GND
= Via to GND Plane
CLK_OUT2
= GND Trace
Figure 14. Example Layout for YFP Package
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Product Folder Links: CDC3RL02
13
CDC3RL02
SCHS371C – NOVEMBER 2009 – REVISED JANUARY 2016
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12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDC3RL02BYFPR
ACTIVE
DSBGA
YFP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
4LN
CDC3RL02YFPR
ACTIVE
DSBGA
YFP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(4L2 ~ 4LN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jan-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
CDC3RL02BYFPR
DSBGA
YFP
8
3000
178.0
9.2
CDC3RL02YFPR
DSBGA
YFP
8
3000
178.0
9.2
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
0.9
1.75
0.6
4.0
8.0
Q1
0.9
1.75
0.6
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDC3RL02BYFPR
DSBGA
YFP
8
3000
220.0
220.0
35.0
CDC3RL02YFPR
DSBGA
YFP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
D: Max = 1.59 mm, Min = 1.53 mm
E: Max = 0.79 mm, Min = 0.73 mm
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