Practical Aspects of Using PowerMOS Transistors to Drive Inductive Loads Application Note Introduction Title N75 ) ubct ractil pect of ing werOS an tors ive duce ads) utho ) eyords nter- Many of the more recent applications of PowerMOS transistors, particularly low voltage devices, have been as solenoid drivers. In this type of application the device is simply used as a switch to turn the current through a solenoid, relay or other inductive load on and off (Figure 1). Since the dissipation is low, a very small or no heat sink will be required. This note will cover the application of the rating and characteristics of PowerMOS transistors to that type of application and illustrate the process of selecting a suitable transistor. Defining the Problem The circuit used in most solenoid switch applications is very simple. It simply consists of an inductor and resistance in series with the drain and a gate drive circuit (Figure 2). Analyzing this circuit can lead to some simplifications that will speed design efforts. There are three circuit states that we should analyze. The simplest state is when the PowerMOS transistor is “off”, when the gate and source are at the same potential. Under this condition the dissipation in the device is simply the leakage current times the supply voltage VCC. Usually this is negligible. The second state we should consider is when the gate drive is “on”. The PowerMOS transistor can best be represented as a series resistor. The current through that resistor is: V CC I T = --------------------------------R L + r DS(ON) (EQ. 1.1) The dissipation (PT) in the PowerMOS transistor while the device is “on” is: 2 orpoion, minctor reor () OC FO fark P T = ( I T ) × r DS(ON) (EQ. 1.2) If we make the simplifying assumption that RL >> rDS(ON) this is: V CC 2 P T = ------------ × r DS(ON) RL (EQ. 1.3) where rDS(ON) is the worst case resistance of the PowerMOS transistor at its operating junction temperature. PowerMOS October 1999 AN-7517 transistors all exhibit an increase in rDS(ON) with temperature. Usually this is given in the form of a curve of rDS(ON) vs temperature on the datasheet. The worst case rDS(ON) at any elevated junction temperature is determined as follows. First, using the rDS(ON) vs temperature curve for the device, obtain the multiplicative factor at the expected operating junction temperature. Finally multiply the maximum 25oC rDS(ON) rating by the previously determined factor. The third state we should consider is when the switch transitions from “on” to “off” or vice versa. In many solenoid switch applications the major dissipation occurs while the PowerMOS transistor is “on”, but turn on and turn off also dissipate power in the transistor. The switching speed of most PowerMOS transistors is so fast that turn on losses are usually very small. An exception is when the drive current available is very very small. Usually this does not occur in the real world. For example the Fairchild RFP70N06 PowerMOS transistor requires a maximum of 115nC of gate charge to transition from “off” to fully “on”. For a gate drive which supplies 1.0mA this would mean that the transition would take less than 115µs. This will make a negligible change in the junction temperature of the PowerMOS transistor. Turn-off subjects the PowerMOS transistor to Unclamped Inductive Switching. Modern PowerMOS transistors can withstand this type of stress and give clear ratings in their datasheets to let customers calculate whether or not they are operating within the devices’ capability. The energy dissipated in the PowerMOS transistor each time the current is interrupted is: L × I T × V DSS 1- E T = ------------------------------------ × 1 – K × In 1 + -- RL K (EQ. 1.4) See Fairchild Application Note AN-7514. Where: V BRK – V CC K = --------------------------------IT × RL Please note that the VBRK used here is the rated breakdown voltage, since that is worst case, rather than the 1.3 x rated breakdown voltage used in Application Note AN-7514. L L RL + VGS RG 0V FIGURE 1. TYPICAL INDUCTIVE SWITCHING CIRCUIT ©2002 Fairchild Semiconductor Corporation + VDD VGS - RG VDD - 0V FIGURE 2. SOLENOID SWITCHING APPLICATION CIRCUIT Application Note 7517 Rev. A2 Application Note 7517 The power dissipated in the device due to UIS will be directly proportional to the number of times the interruption could occur per second. If a human provides the interruptions, 5 times per second would probably be sufficient. IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V – V L BRK CC (EQ. 1.5) All of the losses in the PowerMOS transistor summed, multiplied by the total thermal resistance (junction to case, case to heat sink and heatsink to ambient) gives the rise in junction temperature above the ambient. From that temperature the operating rDS(ON) can be determined and the calculations iterated. Sometimes several iterations are required. Capability at 4.0A, 175oC is 0.9ms. Example 1 (Unit is not suitable for this application!) The following example assumes a set of operating conditions and computes the suitability of various Fairchild PowerMOS devices to operate under those assumed conditions. C. Try RFP45N06 The assumed circuit conditions are: Check to be sure UIS stress is within RFP45N06 capability. L = 50mH, VCC = 16V, RL = 4Ω, IERC PSD1-2U Heat sink. In addition, the following assumed: operational conditions are Rep Rate = 5 pulses/s, TA = 125oC, charged current level ≈ 4A. Sufficient time was allotted for the inductor to charge; we chose ten time constants (125ms). The inductor also had to discharge to less than 1% of the charged current level between pulses, and finally; 10ms of deadtime were allotted between pulses. Please note: the number of significant figures in all intermediate calculation values were truncated to aid readability. Check UIS capability and verify junction temperature is less than 175oC. 0.05 4×4 t AV = ----------- × In ------------------------------------- + 1 4 1.3 × 100 – 16 t AV = 1.64ms Assume TJ = 175oC. IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V – V L BRK CC (EQ. 1.5) 0.05 4×4 t AV = ----------- × In ---------------------------------- + 1 4 1.3 × 60 – 16 t AV = 2.9ms Capability at 4.0A, 175oC is 3.2ms. OK for UIS. Check to see if TJ ≤ 175oC. r DS(ON) = 2.1 × 0.028 (See Figure 7, RFP45N06 datasheet.) r DS(ON) = 0.059 Ω A. Try RFP3055 Dissipation during conduction: Assume TJ = 175oC. 2 Check to be sure UIS stress is within RFP3055 capability. IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V BRK – V CC L (EQ. 1.5) V CC P T = ------------ × r DS(ON) RL (EQ. 1.3) 16.0 2 P T = ----------- × 0.059 4 (Reference AN-7514.) 0.05 4×4 t AV = ----------- × In ---------------------------------- + 1 4 1.3 × 60 – 16 t AV = 2.9ms Capability at 4.0A, 175oC is 0.04ms. P T = 0.941W Dissipation due to UIS: L × I T × V DSS 1- E T = ------------------------------------ × 1 – K × In 1 + -- RL K (EQ. 1.4) (Unit is not suitable for this application!) B. Try RFP22N10 Assume TJ = 175oC. Check to be sure UIS stress is within RFP22N10 capability. ©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2 Application Note 7517 Where Check to see if TJ ≤ 175oC. V DSS – V CC K = --------------------------------IT × RL r DS(ON) = 2.1 × 0.022 (See Figure 7, RFP50N06 datasheet.) r DS(ON) = 0.046 Ω 60 – 16K = -----------------4×4 Dissipation during conduction: V CC 2 P T = ------------ × r DS(ON) RL K = 2.75 0.05 × 4 × 60 E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ] 4 (EQ. 1.3) 16.0 2 P T = ----------- × 0.046 4 E T = 0.441J Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6) P T = 0.739W Dissipation due to UIS: P T = 0.441 × 5 = 2.206W L × I T × V DSS 1 E T = ------------------------------------ × 1 – K × In 1 + ---- RL K P TOTAL = 0.941 + 2.206 = 3.147W θ JA = θ JC + θ CHS + θ HS (EQ. 1.7) o (EQ. 1.4) Where V DSS – V CC K = --------------------------------IT × RL θ JC = 1.14 C ⁄ W (See page 2, RFP45N06 datasheet). o θ CHS = 1.0 C ⁄ W (estimated) 60 – 16 K = ------------------4×4 o θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.) K = 2.75 o θ JA = 16.54 C ⁄ W ∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) 0.05 × 4 × 60 E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ] 4 E T = 0.441J o ∆ TJUNCTION = 3.147 × 16.54 = 52.05 C ∆ TJUNCTION = 125 + 52.1 = 177.1 C Dissipation due to UIS = ET x Rep Rate: (Unit is not suitable for this application!) P T = 0.441 × 5 = 2.206W But we could use a lower thermal resistance heat sink and make it work. P TOTAL = 0.739 + 2.206 = 2.945W C. Try RFP50N06 θ JA = θ JC + θ CHS + θ HS o Assume TJ = 175oC. (EQ. 1.7) o θ JC = 1.14 C ⁄ W (See page 2, RFP50N06 datasheet.) Check to be sure UIS stress is within RFP50N06 capability. IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V L BRK – V CC (EQ. 1.6) (EQ. 1.5) o θ CHS = 1.0 C ⁄ W (estimated) o θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.) o 0.05 4×4 t AV = ----------- × In ---------------------------------- + 1 4 1.3 × 60 – 16 t AV = 2.9ms Capability at 4.0A, 175oC is 3.2ms. OK for UIS. θ JA = 16.54 C ⁄ W ∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) o ∆ TJUNCTION = 2.945 × 16.54 = 48.7 C o ∆ TJUNCTION = 125 + 48.7 = 173.7 C OK for both UIS and TJ . ©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2 Application Note 7517 D. Try RFP70N03 P T = 0.500 × 5 = 2.500W Assume TJ = 175oC. Check to be sure UIS stress is within RFP70N03 capability. P TOTAL = 0.256 + 2.500 = 2.756W IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V – V L BRK CC θ JA = θ JC + θ CHS + θ HS (EQ. 1.5) o θ JC = 1.0 C ⁄ W (See page 2, RFP70N03 datasheet.) 0.05 4×4 t AV = ----------- × In ---------------------------------- + 1 4 1.3 × 30 – 16 o θ CHS = 1.0 C ⁄ W (estimated) t AV = 6.6ms o θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.) Capability at 4.0A, 175oC is 24ms. OK for UIS. o θ JA = 16.4 C ⁄ W Check to see if TJ ≤ 175oC. r DS(ON) = 1.6 × 0.010 (See Figure 7, RFP70N03 datasheet.) o o OK for both UIS and TJ . (EQ. 1.3) E. Try RFP70N06 Assume TJ = 175oC. 2 16.0 P T = ----------- × 0.016 4 Check to be sure UIS stress is within RFP70N06 capability. P T = 0.256W IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V – V L BRK CC Dissipation due to UIS: (EQ. 1.4) Where (EQ. 1.5) 0.05 4×4 t AV = ----------- × In ---------------------------------- + 1 4 1.3 × 60 – 16 t AV = 2.9ms V DSS – V CC K = --------------------------------IT × RL Capability at 4.0A, 175oC is 9.0ms. OK for UIS. Check to see if TJ ≤ 175oC. 30 – 16K = -----------------4×4 r DS(ON) = 2.1 × 0.014 (See Figure 7, RFP70N06 datasheet.) K = 0.875 r DS(ON) = 0.0294 Ω 0.05 × 4 × 30 E T = ---------------------------------- × [ 1 – 0.875 × In ( 2.143 ) ] 4 Dissipation during conduction: V CC 2 P T = ------------ × r DS(ON) RL E T = 0.500J Dissipation due to UIS = ET x Rep Rate: (EQ. 1.8) ∆ TJUNCTION = 125 + 45.2 = 170.2 C Dissipation during conduction: L × I T × V DSS 1- E T = ------------------------------------ × 1 – K × In 1 + -- RL K ∆ TJUNCTION = θ JA × P TOTAL ∆ TJUNCTION = 2.756 × 16.4 = 45.2 C r DS(ON) = 0.016 Ω V CC 2 P T = ------------ × r DS(ON) RL (EQ. 1.7) (EQ. 1.3) (EQ. 1.6) 2 16.0 P T = ----------- × 0.0294 4 P T = 0.470W ©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2 Application Note 7517 Dissipation due to UIS: The assumed conditions are: L × I T × V DSS 1 E T = ------------------------------------ × 1 – K × In 1 + ---- RL K (EQ. 1.4) Where L = 10mH, VCC = 24V, RL = 24Ω, rep rate = 5/s, No Heat sink, ambient = +125oC, I ≈ 1A, Check UIS capability and verify junction temperature is less than +175oC. A. Try RFD3055 V DSS – V CC K = --------------------------------IT × RL Assume TJ = 175oC. Check to capability. 60 – 16K = -----------------4×4 be sure UIS stress K = 2.75 IT × RL L t AV = ------- × In ------------------------------------------------ + 1 R 1.3 × V – V L BRK CC 0.05 × 4 × 60 E T = ---------------------------------- × [ 1 – 2.75 × In ( 1.36 ) ] 4 0.01 1 × 24 t AV = ----------- × In ---------------------------------- + 1 24 1.3 × 60 – 24 E T = 0.441J t AV = 0.172ms Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6) within RFP3055 (EQ. 1.5) Capability at 1.0A, +175oC is 0.6ms. Unit is OK for UIS. P T = 0.441 × 5 = 2.206W Check to see if TJ ≤ +175oC. r DS(ON) = 2.1 × 0.150 (See Figure 7, RFD3055 datasheet.) P TOTAL = 0.470 + 2.206 = 2.676W (EQ. 1.7) θ JA = θ JC + θ CHS + θ HS r DS(ON) = 0.315 Ω Dissipation during conduction: o θ JC = 1.14 C ⁄ W (See page 2, RFP50N06 datasheet.) V CC 2 P T = ------------ × r DS(ON) RL o θ CHS = 1.0 C ⁄ W (estimated) (EQ. 1.3) 24.0 2 P T = ----------- × 0.315 24 o θ HS = 14.4 C ⁄ W (IERC short form catalog dated 8/93.) o θ JA = 16.54 C ⁄ W P T = 0.315W ∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) o ∆ TJUNCTION = 2.676 × 16.54 = 44.3 C o ∆ TJUNCTION = 125 + 44.3 = 169.3 C OK for both UIS and TJ . Conclusion This leaves us with the result that the smallest device that will safely handle a 4A switch application under these ground rules is a 50A rated device. Example 2 The following example assumes a set of operating conditions and computes the suitability of various Fairchild PowerMOS devices to operate under those assumed conditions. ©2002 Fairchild Semiconductor Corporation is Dissipation due to UIS: L × I T × V DSS 1- E T = ------------------------------------ × 1 – K × In 1 + -- RL K (EQ. 1.4) Where V DSS – V CC K = --------------------------------IT × RL 60 – 24 K = -----------------1 × 24 K = 1.5 0.01 × 1 × 60 E T = ---------------------------------- × [ 1 – 1.5 × In ( 1.667 ) ] 24 E T = 5.84mJ Application Note 7517 Rev. A2 Application Note 7517 Dissipation due to UIS = ET x Rep Rate: (EQ. 1.6) P T = 0.00584 × 5 = 0.029W P TOTAL = 0.315 + 0.029 = 0.344W θ JA = θ JC + θ CA (EQ. 1.7) o θ JC = 2.8 C ⁄ W (See page 2, RFD3055 datasheet.) on resistance and thermal resistance to conduction dissipation and operating temperature. The supply voltage, load resistance and junction and ambient temperatures are defined and therefore constant. The on resistance multiplied by the thermal resistance must be less than or equal to this constant. The equation to calculate the dissipation (PT) in the PowerMOS transistor while the device is “on” assuming that RL >> rDS(ON) was given on Page 1 as: 2 V CC P T = ------------ × r DS(ON) RL o θ CA = 100 C ⁄ W (See page 2, RFD3055 datasheet.) (EQ. 1.3) Substituting terms in the equation: o θ JA = 102.8 C ⁄ W ∆ TJUNCTION = θ JA × P TOTAL (EQ. 1.8) o ∆ TJUNCTION = 102.8 × 0.344 = 35.4 C TJ – TA V CC 2 ------------------- = ------------ × r DS(ON) R θ JA RL Where ∆ TJUNCTION = 125 + 35.4 = 160.4 C TJ – TA P T = ------------------R θ JA OK for both UIS and Tj . and rearranging as follows: Conclusion RL r DS(ON) × R θ JA ≤ ------------ × T J – T A V CC o (EQ. 2.1) (EQ. 2.2) 2 (EQ. 2.3) It is not necessary to use a larger device to switch this current. provides the equation for device selection. Example 3 A. Try the RFP3055 Example 1 concludes we need a device with an on resistance of less than 50mΩ and a 30A continuous current rating at +125oC case temperature. This seems to be a bit of overkill, since the application has a peak current of 4A. The possibility of a more cost-effective alternative should be investigated. A circuit configuration using a smaller MOSFET and a commutating diode will be examined to determine if that is a better solution. RL 2 r DS(ON) × R θ JA ≤ ------------ × T J – T A V CC The assumed circuit conditions are: L = 50mH, VCC = 16V, RL = 4Ω, IERC PSD1-2U Heat sink. In addition, the following assumed: operational conditions are Rep Rate = 5pulses/s, ambient temperature = +125oC, charged current level ≈ 4A. Sufficient time was allotted for the inductor to charge; we chose ten time constants (125ms). The inductor also had to discharge to less than 1% of the charged current level between pulses, and finally; 10ms of deadtime were allotted between pulses. The selection process can be divided into two parts; MOSFET and diode, as each will perform different functions. The MOSFET will function as a switch, the diode as a discharge path for the inductor. (EQ. 2.3) o o o 4Ω 2 0.315 Ω × 18.2 C ⁄ W ≤ ----------- × 175 C – 125 C 16V o o 5.733 Ω C ⁄ W > 3.125 Ω C ⁄ W The on resistance thermal resistance product is greater than the constant. (This unit is not suitable!) B. Try the RFD16N05 RL 2 r DS(ON) × R θ JA ≤ ------------ × T J – T A V CC (EQ. 2.3) o o o 4Ω 2 0.999 Ω × 17.5 C ⁄ W ≤ ----------- × 175 C – 125 C 16V o o 1.733 Ω C ⁄ W < 3.125 Ω C ⁄ W This unit is capable of dissipating the conduction losses! Since the MOSFET is only a switch in this configuration, we need only be concerned with the conduction dissipation when selecting the proper device. Equation 2.3 provides a basis for determining the MOSFET using the relationship of ©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2 Application Note 7517 With a suitable MOSFET selected a diode is next. discharge time could be no greater than: The energy dissipated by the diode due to one UIS pulse is calculated as follows: t ≤ Pulse Width (1 pulse) – ( Charge Time + 10ms ) L E = I0 × V D × ---- × k R t ≤ 200ms – ( 125ms + 10ms ) (EQ. 2.4) Where t ≤ 65ms I0 = the current level at the time the MOSFET was turned off VD = the voltage across the diode ( In ( 1 ⁄ ( 1 + s ) ) ) k = 1 + ---------------------------------------s If parasitic inductances and resistances are negligible; a useful approximation of the discharge time can be calculated as follows: L t = ------- × In ( 1 + s ) RL I0 × R s = -------------VD 0.05mH t = --------------------- × In ( 1 + 36.4 ) 4Ω 50mH E = 4A × 0.84V × ---------------- × 0.843 4Ω t = 45.3ms E = 35.4mJ The total power dissipation due to the 5 UIS pulses is calculated; using the calculated value, determine a thermal resistance necessary to dissipate the power. The thermal resistance of the device, interface and heat sink must be less than or equal to the calculated value. P T = E × 5 pulses/s (EQ. 1.5) P T = 177mW T JMAX – T A R θ JA = ------------------------------PT o o 175 C – 125 C R θ JA = ----------------------------------------0.177W o R θ JA ≤ 282 C ⁄ W C. Try the RURD410 (EQ. 1.7) R θ JA = R θ JC + R θ CHS + R θ HS o o o R θ JA = 5.0 C ⁄ W + 1.0 C ⁄ W + 14.4 C ⁄ W o R θ JA = 20.4 C ⁄ W The discharge time is less than the allowable 65ms. This approach will work. The inductor would discharge to less than 1% of the initial current level between each pulse. Conclusion A properly selected MOSFET, capable of withstanding operation in the avalanche mode was the best choice of the solutions examined for this application. The MOSFET operating as a switch dissipates little power while “on” and provides a means of discharging the inductor between pulses; making it functionally compatible for the application. Finally and equally important; the avalanche rated MOSFET is also the most economical choice of the solutions evaluated. The selected MOSFET diode combination is also functionally compatible for this application. The combination selected in this example is more expensive than the stand alone MOSFET. However, the thermal resistance calculated for the diode suggests a smaller less expensive diode could be substituted. The cost reduction from the substitution of a less expensive diode may make the combination a more attractive solution. The examination of more economical diodes is left to the reader. In this application; functionality, economics and a defined set of operating conditions were the constraints to the eventual solution. Rather than reach a rigid conclusion; the Application note intended to illustrate a methodology to determine the best solution for a set of design constraints. The RURD410, interface and heat sink junction to ambient thermal resistance are less than the requirement. This unit is suitable. The next consideration is to determine the time necessary for the inductor to fully discharge. Earlier we established the conditions for discharge. The current level must decay to 1% of its initial value, the discharge time to the 1% current level must be no greater than the pulse width of one pulse minus the sum of the charge time and 10ms. In this illustration the ©2002 Fairchild Semiconductor Corporation Application Note 7517 Rev. A2 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H5