SCAS576C − JULY 1996 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D NOT RECOMMENDED FOR NEW DESIGNS this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input No External RC Network Required Operates at 3.3-V VCC Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package PW PACKAGE (TOP VIEW) AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN description The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3-V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDC509 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0:4) 2Y (0:3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996 − 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($ (#"! " !%$""! %$ )$ $! $*! !#$! !(( +, (#" %"$!!- ($! $"$!!', "'#($ $!- '' %$$! POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCAS576C − JULY 1996 − REVISED DECEMBER 2004 functional block diagram 1G 11 3 4 5 8 9 2G 20 24 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ PLL FBIN AVCC 13 23 AVAILABLE OPTIONS PACKAGE 2 1Y1 1Y2 1Y3 1Y4 14 21 CLK 1Y0 TA SMALL OUTLINE (PW) 0°C to 70°C CDC509PWR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 16 12 2Y0 2Y1 2Y2 2Y3 FBOUT SCAS576C − JULY 1996 − REVISED DECEMBER 2004 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDC509 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 1G 11 I Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same frequency as CLK. 2G 14 I Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. 1Y(0:4) 3, 4, 5, 8, 9 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. 2Y(0:3) 16, 17, 20 21 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 15, 22 Power Power supply 6, 7, 18, 19 Ground Ground absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCAS576C − JULY 1996 − REVISED DECEMBER 2004 recommended operating conditions (see Note 4) MIN MAX 3.6 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage IOH IOL High-level output current 0 Low-level output current TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 0 V V 0.8 Input voltage UNIT V VCC −20 mA V 20 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II ICC‡ ∆ICC Ci Co TEST CONDITIONS VCC II = −18 mA IOH = −100 µA MIN TYP† 3V MIN to MAX IOH = −20 mA IOL = 100 µA 3V IO = 0, Outptus high or low Other inputs at VCC or GND UNIT −1.2 V VCC−0.2 2.4 V MIN to MAX 0.2 3V 0.55 IOL = 20 mA VI = VCC or GND VI = VCC or GND, One input at VCC − 0.6 V, MAX V 3.6 V ±5 µA 3.6 V 10 µA 3.3 V to 3.6 V 500 µA VI = VCC or GND VO = VCC or GND 3.3 V 4 pF 3.3 V 6 pF † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ For ICC of AVCC, see Figure 5. timing requirements over recommended ranges of supply voltage and operating free-air temperature fclock Clock frequency Input clock duty cycle Stabilization time§ MIN MAX UNIT 25 125 MHz 40% 60% 1 ms § Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS576C − JULY 1996 − REVISED DECEMBER 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Note 5 and Figures 1 and 2)† FROM (INPUT) TO (OUTPUT) tphase error, reference (see Figure 3) 66 MHz < CLKIN↑ < 100 MHz FBIN↑ tphase error, − jitter, (see Note 6) CLKIN↑ = 100 MHz FBIN↑ Any Y or FBOUT Any Y or FBOUT F(clkin > 66 MHz) Any Y or FBOUT F(clkin ≤ 66 MHz) Any Y or FBOUT F(clkin > 66 MHz) Any Y or FBOUT PARAMETER tsk(o)‡ Jitter(pk-pk) Duty cycle, reference (see Figure 4) tr tf VCC = 3.3 V ± 0.165 V MIN TYP 220 VCC = 3.3 V ± 0.3 V MAX MIN TYP UNIT MAX 100...480 ps 340 ps 480 200 ps −100 100 ps 45% 55% 43% 57% Any Y or FBOUT 1.1 1.5 0.7 1.6 ns Any Y or FBOUT 0.8 1.3 0.5 1.5 ns † This parameters are not production tested. ‡ The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 6. Phase error does not include jitter. The total phase error is 120 ps to 580 ps for the 5% VCC range. PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 W Output 30 pF 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCAS576C − JULY 1996 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS576C − JULY 1996 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS PHASE ERROR vs CLOCK FREQUENCY OUTPUT DUTY CYCLE vs CLOCK FREQUENCY 1.2 1 57% VDD = 3.3 V TA = 25°C 55% Output Duty Cycle 53% 0.6 0.4 0.2 51% 49% 47% 0 45% 45 55 65 75 85 95 43% 30 105 115 125 135 50 fclk − Clock Frequency − MHz 70 90 110 130 fclk − Clock Frequency − MHz Figure 3 Figure 4 ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 9 VDD = 3.3 V TA = 25°C 8 Analog Supply Current − mA Phase Error − ns 0.8 −0.2 35 VDD = 3.3 V CL = 30 pF 7 6 5 4 3 2 1 0 25 35 45 55 65 75 85 95 105 115 125 fclk − Clock Frequency − MHz Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDC509PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK509 CDC509PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CK509 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC509PWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC509PWR TSSOP PW 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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