Renesas M37641M8M8-XXXFP Single-chip 8-bit cmos microcomputer Datasheet

7641 Group
REJ03B0191-0400
Rev.4.00
Aug 28, 2006
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7641 group is the 8-bit microcomputer based on the 7600 series
core (740 family core compatible) technology.
The 7641 group is designed for PC peripheral devices, including the
USB, DMAC, Serial I/O, UART, Timer, Master CPU bus interface and
so on.
FEATURES
<Microcomputer mode)
●Basic machine-language instructions ....................................... 71
●Minimum instruction execution time ..................................... 83 ns
(at 24 MHz oscillation frequency)
●Memory size
ROM ............................................................................. 32 Kbytes
RAM ................................................................................ 1 Kbytes
●Programmable input/output ports ............................................. 66
●Software pull-up resistors .................................................. Built-in
●Interrupts ................................................... 24 sources, 24 vectors
(external 5 including Key input, internal 18, software 1)
●USB function control unit
Transceiver ............................... Full-Speed USB2.0 specification
●Timers ..................................................... 16-bit ✕ 2 (Timers X, Y)
8-bit ✕ 3 (Timers 1, 2, 3)
●Serial Interface
Serial I/O ......................................................................... 8-bit ✕ 1
UART .............................................................................. 8-bit ✕ 2
●DMAC .......................................................................... 2 channels
●Master CPU bus interface ................................................. 2 bytes
●Special count source generator ...................................... 8-bit ✕ 1
●Clock generating circuit ..................................................... Built-in
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V
●Operating temperature range .................................... –20 to 70°C
●Packages
FP ................................................ PRQP0080GB-A (80-pin QFP)
HP ............................................... PLQP0080KB-A (80-pin LQFP)
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<Flash memory mode>
●Power source voltage
At 24 MHz oscillation frequency, φ = 12 MHz ......... 4.15 to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz ........... 3.00 to 3.60 V
●Program/Erase voltage
.................................. VCC = 4.50 V to 5.25 V, or 3.00 V to 3.60 V
.................................................................. VPP = 4.50 V to 5.25 V
At 24 MHz oscillation frequency, φ = 6 MHz (See Table 25.)
●Memory size
Flash ROM .................................................................... 32 Kbytes
RAM ............................................................................. 2.5 Kbytes
●Flash memory mode ....................................................... 3 modes
Parallel I/O mode
Standard serial I/O mode
CPU rewrite mode
●Programming method ....................... Programming in unit of byte
●Erasing method
Batch erasing
Block erasing
●Program/Erase control by software command
●Command number ................................................... 6 commands
●Number of times for programming/erasing ............................. 100
●ROM code protection
Available in parallel I/O mode and standard serial I/O mode
●Operating temperature range (at programming/erasing) ..............
...................................................................... Normal temperature
APPLICATION
Audio, musical instrument, printer, scanner, modem, other PC peripheral devices
■Notes
The flash memory version cannot be used for application embedded in the MCU card.
7641 Group
P74/OBF1
P73/IBF1/HLDA
P72/S1
P71/HOLD
P70/SOF
USB D+
USB DExt.Cap
VSS
VCC
P67/DQ7
P66/DQ6
P65/DQ5
P64/DQ4
P63/DQ3
P62/DQ2
47
46
45
44
43
42
41
50
49
48
51
59
58
57
56
55
54
53
52
60
62
61
64
63
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
P00/AB0
P01/AB1
P02/AB2
P03/AB3
P04/AB4
P05/AB5
P06/AB6
P07/AB7
P10/AB8
P11/AB9
P12/AB10
P13/AB11
P14/AB12
P15/AB13
P16/AB14
P17/AB15
PIN CONFIGURATION (TOP VIEW)
65
66
40
39
67
68
69
70
71
38
37
36
35
34
33
M37641M8-XXXFP
M37641F8FP
72
73
74
75
76
32
31
30
29
28
27
77
78
79
26
25
24
23
22
20
21
19
18
15
16
17
XOUT
VCC
AVCC
LPF
AVSS
P44/CNTR1
P43/CNTR0
P42/INT1
P41/INT0
P40/EDMA
13
14
12
10
11
5
6
7
8
9
2
3
4
P61/DQ1
P60/DQ0
P57/W/(R/W)
P56/R(E)
P55/A0
P54/S0
P53/IBF0
P52/OBF0
CNVSS/VPP
RESET
P51/TOUT/XCOUT
P50/XCIN
VSS
XIN
1
80
P30/RDY
P31
P32
P33/DMAOUT
P34/φ OUT
P35/SYNCOUT
P36/WR
P37/RD
P80/UTXD2/SRDY
P81/URXD2/SCLK
P82/CTS2/SRXD
P83/RTS2/STXD
P84/UTXD1
P85/URXD1
P86/CTS1
P87/RTS1
Package type : PRQP0080GB-A (80P6N-A)
41
47
46
45
44
43
42
50
49
48
51
54
53
52
61
40
62
39
38
37
36
63
64
65
66
35
34
67
68
33
32
31
M37641M8-XXXHP
M37641F8HP
69
70
71
72
73
74
30
29
28
27
26
25
24
75
76
77
78
79
23
22
80
20
19
17
18
15
16
13
14
12
10
11
8
9
6
7
5
P57/W/(R/W)
P56/R(E)
P55/A0
P54/S0
P53/IBF0
P52/OBF0
CNVSS/VPP
RESET
P51/TOUT/XCOUT
P50/XCIN
VSS
XIN
XOUT
VCC
AVCC
LPF
AVSS
P44/CNTR1
P43/CNTR0
P42/INT1
2
3
4
21
1
P21/DB1
P20/DB0
P74/OBF1
P73/IBF1/HLDA
P72/S1
P71/HOLD
P70/SOF
USB D+
USB DExt.Cap
VSS
VCC
P67/DQ7
P66/DQ6
P65/DQ5
P64/DQ4
P63/DQ3
P62/DQ2
P61/DQ1
P60/DQ0
59
58
57
56
55
60
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
P00/AB0
P01/AB1
P02/AB2
P03/AB3
P04/AB4
P05/AB5
P06/AB6
P07/AB7
P10/AB8
P11/AB9
P12/AB10
P13/AB11
P14/AB12
P15/AB13
Fig. 1 M37641M8-XXXFP, M37641F8FP pin configuration
Package type : PLQP0080KB-A (80P6Q-A)
Fig. 2 M37641M8-XXXHP, M37641F8HP pin configuration
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 2 of 135
P16/AB14
P17/AB15
P30/RDY
P31
P32
P33/DMAOUT
P34/φ OUT
P35/SYNCOUT
P36/WR
P37/RD
P80/UTXD2/SRDY
P81/URXD2/SCLK
P82/CTS2/SRXD
P83/RTS2/STXD
P84/UTXD1
P85/URXD1
P86/CTS1
P87/RTS1
P40/EDMA
P41/INT0
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REJ03B0191-0400
15
Fig. 3 Functional block diagram
page 3 of 135
UART1 (8)
Reset
XCIN
φ
65 66 67 68 69
I/O port P7
25 26 27 28 29 30 31 32
I/O port P8
S1, IBF1
OBF1
Serial I/O (8)
P6(8)
17
10
I/O port P6
2
DQ0 to
DQ7
3
4
6
7
8 11 12
I/O port P5
5
74
VCC
P5(8)
16
VCC
W(R/W)
R(E),A0
S0,IBF0
OBF0
Master CPU bus
interface
RAM
AVcc
RESET
Reset input
75 76 77 78 79 80 1
SOF
19
D+ D-
70 71
USB
18
LPF AVSS
ROM
P7(5)
3
6
[φ OUT]
P8(8)
UART2 (8)
XCOUT
Clock generating circuit
14
Main clock Main clock
input
output
XOUT
XIN
FUNCTIONAL BLOCK DIAGRAM (Package: PRQP0080GB-A)
XCIN
TOUT
13
VSS
P4(5)
72
I/O port P4
34
I/O port P2
57 58 59 60 61 62 63 64
I/O port P3
40
I/O port P0
49 50 51 52 53 54 55 56
41 42 43 44 45 46 47 48
I/O port P1
P0(8)
P1(8)
Timer 3 (8)
Timer 2 (8)
Timer Y (16)
Timer X (16)
68
Timer 1 (8)
66
[HLDA] [HOLD]
Key input
33 34 35 36 37 38 39 40
35
P2(8)
[DMAOUT]
DMA
33
P3(8)
INT1,
INT0
TOUT
PS
PCL
S
Y
X
A
24
[EDMA] [RD] [WR] [SYNCOUT] [RDY]
CNTR1, CNTR0
C P U
PCH
9
Ext.Cap CNVSS
20 21 22 23 24
73
VSS
7641 Group
7641 Group
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Function
Name
VCC, VSS
Power source
CNVss/VPP
CNVss
AVss/AVcc
Analog power
supply
Reset input
Clock input
Clock output
Function except a port function
• Apply 4.15 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the Vcc pin. Apply 0 V to the
Vss pin.
• This controls the MCU operating mode. Connect this pin to Vss. If connecting this pin to Vcc, the
internal ROM is inhibited. In the flash memory version this pin functions as a VPP power supply input pin.
• These pins are the power supply inputs for analog circuitry.
LPF
Ext. Cap.
LPF
3.3 V line power
supply
USB D+
USB D+
• Reset input pin for active “L.”
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• Loop filter for the frequency synthesizer.
• It is a capacitor connection pin for built-in DC-DC converter. At Vcc=5 V, use built-in DC-DC converter
by permitting a USB line driver and connect a capacitor. Refer to "Notes on use" for details. Built-in DCDC converter cannot be used at Vcc = 3.3 V. Supply 3.3V power supply to this pin from the externals.
• USB D+ voltage signal port. Connect a 27 to 33 Ω (recommended) resistor in series.
USB D-
USB D-
• USB D- voltage signal port. Connect a 27 to 33 Ω (recommended) resistor in series.
RESET
XIN
XOUT
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• When connecting an external memory, these function as the address bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• When connecting an external memory, these function as the address bus.
P00/AB0–
P07/AB7
P10/AB8–
P17/AB15
I/O port P0
P20/DB0–
P27/DB7
I/O port P1
P30/RDY,
I/O port P2
P31, P32,
I/O port P3
P33/DMAOUT,
P34/φ OUT,
P35/SYNCOUT,
P36/WR,
P37/RD
P40/EDMA,
(See Remarks.)
P41/INT0,
P42/INT1,
P43/CNTR0,
P44/CNTR1
P50/XCIN,
P51/TOUT/
XCOUT,
P52/OBF0,
P53/IBF0,
P54/S0,
P55/A0,
P56/R(E),
P57/W(R/W)
I/O port P4
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
• 8-bit I/O port.
• CMOS compatible input level or VIHL input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the data bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the control bus.
• Key-on wake-up interrupt input pin
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When connecting an external memory, these function as
the control bus.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When enabling the Master CPU bus interface function,
CMOS or TTL input level can be selected as an input.
• External memory control pin
• External interrupt pin
page 4 of 135
• External memory control pin
• Timer X, Timer Y pin
• Sub-clock generating input pin
• Timers 1, 2 pulse output pins
• Sub-clock generating output pin
• Master CPU bus interface pin
7641 Group
Table 2 Pin description (2)
Pin
Function
Name
P60/DQ0–
P67/DQ7
I/O port P5
P70/SOF,
P71/HOLD,
P72/S1,
P73/IBF1/
HLDA,
P74/OBF1
P80/UTXD2/
SRDY,
P81/URXD2/
SCLK,
P82/CTS2/
SRXD,
P83/RTS2/
STXD,
P84/UTXD1,
P85/URXD1,
P86/CTS1,
P87/RTS1
I/O port P6
I/O port P7
I/O port P8
Function except a port function
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• When enabling the bus interface function, CMOS or TTL
input level can be selected as its input.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• Master CPU bus interface pin
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O direction register allows each pin to be individually programmed as either input or output.
• Serial I/O pin
• UART2 pin
• USB function pin
• Master CPU bus interface pin
• UART1 pin
Remarks
•DMAOUT pin
If externally detecting the timing of DMA execution, use the signal from this pin. It is “H” level during DMA transferring. This signal is valid in the memory expansion
and microprocessor modes.
•SYNCOUT pin
If externally detecting the timing of OP code fetch, use the signal from this pin. This signal is valid in the memory expansion and microprocessor modes.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 5 of 135
7641 Group
PART NUMBERING
Product
M37641
M 8
–
XXX
FP
Package type
FP: PRQP0080GB-A package
HP: PLQP0080KB-A package
ROM number
Omitted in Flash memory version.
–: Standard
Omitted in Flash memory version.
ROM size/ Flash memory size
8: 32768 bytes
The first 128 bytes and the last 4 bytes of ROM
are reserved areas; they cannot be used.
In the flash memory version, these areas can be used for program
and erase.
Memory type
M: Mask ROM version
F: Flash memory version
RAM size
M37641M8 : 1024 bytes
M37641F8 : 2560 bytes
Fig. 4 Part numbering
Rev.4.00 Aug 28, 2006
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page 6 of 135
7641 Group
GROUP EXPANSION
Packages
Mitsubishi plans to expand the 7641 group as follows.
PRQP0080GB-A ......................... 0.8 mm-pitch plastic molded QFP
PLQP0080KB-A ........................ 0.5 mm-pitch plastic molded LQFP
Memory Type
Supports for mask ROM and flash memory versions.
Memory Size
ROM size ......................................................................... 32 Kbytes
RAM size ........................................................... 1024 to 2560 bytes
Memory Expansion Plan
ROM size (bytes)
ROM
external
60 K
48 K
M37641M8
32 K
M37641F8
28 K
24 K
20 K
16 K
12 K
8K
384
512
640
768
896 1024 1152 1280 1408 1536 2048 3072 4032
RAM size (bytes)
Fig. 5 Memory expansion plan
Currently planning products are listed below.
Table 3 Support products
Product name
M37641M8-XXXFP
M37641M8-XXXHP
M37641F8FP
M37641F8HP
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
As of Aug. 2006
ROM size (bytes)
ROM size for User in ( )
32768 (32636)
RAM size
(bytes)
1024
32768
2560
page 7 of 135
Package
PRQP0080GB-A
PLQP0080KB-A
PRQP0080GB-A
PLQP0080KB-A
Remarks
Mask ROM version
Flash memory version
7641 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
[Stack Pointer (S)]
The 7641 group uses the standard 7600 series instruction set. Refer
to the 7600 Series Software Manual for details on the instruction set.
The 7600 series has an upward compatible instruction set, of which
instruction execution cycles are shortened, for 740 series.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b8 b7
PCH
Stack pointer
b0
Program counter
PCL
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 7600 series CPU register structure
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7641 Group
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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page 9 of 135
7641 Group
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can
be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow
(V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags
are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
C flag
Z flag
I flag
D flag
B flag
SEC
CLC
–
–
SEI
CLI
SED
CLD
–
–
page 10 of 135
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
7641 Group
[CPU Mode Registers A, B (CPUMA, CPUMB)] 000016, 000116
The CPU mode register contains the stack page select bit and the
CPU operating mode select bit and so on.
The CPU mode registers are allocated at address 000016, 000116.
b7
■ Notes
Do not use the microprocessor mode in the flash memory version.
b0
CPU mode register A (address 000016)
CPMA
1
Processor mode bits
b1b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Microprocessor mode (Note 1)
1 1: Not available
Stack page select bit
0: Page 0
1: Page 1
Fix to “1”.
Sub-clock (XCIN-XCOUT) control bit
0: Stopped
1: Oscillating
Main clock (XIN-XOUT) control bit
0: Oscillating
1: Stopped
Internal system clock select bit (Note 2)
0: External clock (XIN-XOUT or XCIN-XCOUT)
1: fSYN
External clock select bit
0: XIN-XOUT
1: XCIN-XCOUT
Notes 1: This is not available in the flash memory version.
2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected
between f(XIN) or f(XIN)/2 by CCR7.
The internal clock φ is the internal system clock divided by 2.
b7
1 0
b0
CPU mode register B (address 000116)
CPMB
Slow memory wait select bits
b1b0
0 0: No wait
0 1: One-time wait
1 0: Two-time wait
1 1: Three-time wait
Slow memory wait mode select bits
b3b2
0 0: Software wait
0 1: Not available
1 0: RDY wait
1 1: Software wait plus RDY input anytime wait
Expanded data memory access bit
0: EDMA output disabled
1: EDMA output enabled
HOLD function enable bit
0: HOLD function disabled
1: HOLD function enabled
Resereved bit (“0” at read/write)
Fix to “1”.
Fig. 8 Structure of CPU mode register
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7641 Group
MEMORY
Special Function Register (SFR) Area
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
Zero Page
RAM
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Special Page
ROM
Access to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 4 bytes of ROM are reserved for
device testing and the rest is user area for storing programs. In the
flash memory version, program and erase can be performed in the
reserved area.
Refer to page 74 for the memory map of memory expansion and
microprocessor modes.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
M37641M8
1024
046F16
M37641F8
2560
0A6F16
SFR area
007016
RAM
Zero page
010016
XXXX16
Reserved area (Note 1)
100016
Not used
800016
Reserved ROM area
(128 bytes)
808016
ROM
SIZE: 32768 bytes
FF0016
FFC916
FFCA16
(Note 2)
SFR area
Interrupt vector area
FFFC16
FFFF16
Reserved ROM area
Notes 1: Reserved area in M37641F8.
2: SFR area in M37641F 8.
Fig. 9 Memory map diagram
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Special page
7641 Group
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
CPU mode register A (CPUA)
CPU mode register B (CPUB)
Interrupt request register A (IREQA)
Interrupt request register B (IREQB)
Interrupt request register C (IREQC)
Interrupt control register A (ICONA)
Interrupt control register B (ICONB)
Interrupt control register C (ICONC)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port control register (PTC)
Interrupt polarity select register (IPOL)
Port P2 pull-up control register (PUP2)
USB control register (USBC)
Port P6 (P6)
Port P6 direction register (P6D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Resereved (Note 1)
Clock control register (CCR)
Timer XL (TXL)
Timer XH (TXH)
Timer YL (TYL)
Timer YH (TYH)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Serial I/O shift register (SIOSHT)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Special count source generator 1 (SCSG1)
Special count source generator 2 (SCSG2)
Special count source mode register (SCSGM)
UART1 mode register (U1MOD)
UART1 baud rate generator (U1BRG)
UART1 status register (U1STS)
UART1 control register (U1CON)
UART1 transmit/receive buffer register 1 (U1TRB1)
UART1 transmit/receive buffer register 2 (U1TRB2)
UART1 RTS control register (U1RTSC)
Resereved (Note 1)
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
UART2 mode register (U2MOD)
UART2 baud rate generator (U2BRG)
UART2 status register (U2STS)
UART2 control register (U2CON)
UART2 transmit/receive buffer register 1 (U2TRB1)
UART2 transmit/receive buffer register 2 (U2TRB2)
UART2 RTS control register (U2RTSC)
DMAC index and status register (DMAIS)
DMAC channel x mode register 1 (DMAx1)
DMAC channel x mode register 2 (DMAx2)
DMAC channel x source register Low (DMAxSL)
DMAC channel x source register High (DMAxSH)
DMAC channel x destination register Low (DMAxDL)
DMAC channel x destination register High (DMAxDH)
DMAC channel x transfer count register Low (DMAxCL)
DMAC channel x transfer count register High (DMAxCH)
Data bus buffer register 0 (DBB0)
Data bus buffer status register 0 (DBBS0)
Data bus buffer control register 0 (DBBC0)
Resereved (Note 1)
Data bus buffer register 1 (DBB1)
Data bus buffer status register 1 (DBBS1)
Data bus buffer control register 1 (DBBC1)
Resereved (Note 1)
USB address register (USBA)
USB power management register (USBPM)
USB interrupt status register 1 (USBIS1)
USB interrupt status register 2 (USBIS2)
USB interrupt enable register 1 (USBIE1)
USB interrupt enable register 2 (USBIE2)
USB frame number register Low (USBSOFL)
USB frame number register High (USBSOFH)
USB endpoint index register (USBINDEX)
USB endpoint x IN control register (IN_CSR)
USB endpoint x OUT control register (OUT_CSR)
USB
USB
USB
USB
endpoint x IN max. packet size register (IN_MAXP)
endpoint x OUT max. packet size register (OUT_MAXP)
endpoint x OUT write count register Low (WRT_CNTL)
endpoint x OUT write count register High (WRT_CNTH)
USB endpoint FIFO mode register (USBFIFOMR)
USB endpoint 0 FIFO (USBFIFO0)
USB endpoint 1 FIFO (USBFIFO1)
USB endpoint 2 FIFO (USBFIFO2)
USB endpoint 3 FIFO (USBFIFO3)
USB endpoint 4 FIFO (USBFIFO4)
Resereved (Note 1)
Resereved (Note 1)
Resereved (Note 1)
Resereved (Note 1)
Resereved (Note 1)
Flash memory control register (FMCR) (Note 2)
Resereved (Note 1)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register 1 (FSM1)
Frequency synthesizer multiply register 2 (FSM2)
Frequency synthesizer divide register (FSD)
FFC916 ROM code protect control register (ROMCP) (Note 3)
Notes 1: Do not write any data to this addresses, because these areas are reserved.
2: This area is reserved in the mask ROM version.
3: This area is on the ROM in the mask ROM version.
Fig. 10 Memory map of special function register (SFR)
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7641 Group
I/O PORTS
b7
Direction Registers
b0
Port control register (address 001016)
PTC
The I/O ports P0–P8 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Port P0 to P3 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P4 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P5 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P6 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P7 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P8 slew rate control bit (Note 1)
0: Disabled
1: Enabled
Port P2 input level select bit
0: Reduced VIHL level input (Note 2)
1: CMOS level input
Master CPU bus input level select bit
0: CMOS level input
1: TTLlevel input
Slew Rate Control
By setting bits 0 to 5 of the port control register (address 001016) to
“1”, slew rate control is enabled. VIHL or CMOS level can be used as
a port P2 input level; CMOS or TTL level can be used as an input
level of master CPU bus interface.
Pull-up Control
By setting the port P2 pull-up control register (address 001216), pullup of each pin of port P2 can be controlled with a program.
However, the contents of port P2 pull-up control register do not affect
ports programmed as the output ports but as the input ports.
b7
b0
Port P2 pull-up control register
(address 001216) PUP2
Port P20 pull-up control bit
0: Disabled
1: Enabled
Port P21 pull-up control bit
0: Disabled
1: Enabled
Port P22 pull-up control bit
0: Disabled
1: Enabled
Port P23 pull-up control bit
0: Disabled
1: Enabled
Port P24 pull-up control bit
0: Disabled
1: Enabled
Port P25 pull-up control bit
0: Disabled
1: Enabled
Port P26 pull-up control bit
0: Disabled
1: Enabled
Port P27 pull-up control bit
0: Disabled
1: Enabled
Notes 1: The slew rate function can reduce di/dt by modifying an internal
buffer structure.
2: The characteristics of VIHL level is basically the same as that of
TTL level. But, its switching center point is a little higher than
TTL’s. Refer to section “Recommended operating conditions”.
Fig. 11 Structure of port control and port P2 pull-up control
registers
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7641 Group
Table 6 List of I/O port function
Pin
P00/AB0–
P07/AB7
P10/AB8–
P17/AB15
P20/DB0–
P27/DB7
Name
Port P0
Port P2
CMOS input level/VIHL
input level
CMOS 3-state output
P30/RDY–
P37/RD
P40/EDMA,
Port P3
CMOS input level
CMOS 3-state output
Input/Output
Input/Output,
individual bits
I/O format
CMOS input level
CMOS 3-state output
Port P1
Non-port function
Lower address
output
Higher address
output
Data bus I/O
Control signal I/O
Port P4
P41/INT0,
Control signal I/O
External interrupt
P42/INT1,
P43/CNTR0,
P44/CNTR1
Related SFRs
CPU mode register A
Port control register
Ref. No.
(1)
CPU mode register A
Port control register
Port P2 pull-up control
register
CPU mode register A
CPU mode register B
Port control register
CPU mode register A
CPU mode register B
Port control register
Timer X mode register
Timer Y mode register
(2)
(1)
(3)
(4)
(5)
Interrupt polarity select register
P50/XCIN,
P51/TOUT/
XCOUT
Port P5
P52/OBF0,
P53/IBF0,
P54/S0,
P55/A0,
P56/R(E),
P57/W(R/W)
P60/DQ0–
P67/DQ7
Port P6
P70/SOF,
Port P7
P71/HOLD,
P72/S1,
P73/IBF1/
HLDA,
P74/OBF1
P80/UTXD2/
SRDY,
P81/URXD2/
SCLK,
P82/CTS2/
SRXD,
P83/RTS2/
STXD,
P84/UTXD1,
P85/URXD1,
P86/CTS1,
P87/RTS1
Port P8
CMOS input level
CMOS 3-state output
Timer 1, Timer 2
output pin
Sub-clock generating input pin
CMOS input level
CMOS 3-state output
CMOS input level/TTL
input level in Master
CPU bus inferface
function
Master CPU bus
interface I/O pin
CMOS input level/TTL
input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level/TTL
input level in Master
CPU bus inferface
function
CMOS input level
CMOS 3-state output
Master CPU bus
interface I/O pin
USB function output
pin
Control signal I/O
Master CPU bus
interface I/O pin
Serial I/O I/O pin
UART2 I/O pin
UART1 I/O pin
CPU mode register A
Port control register
Clock control register
Timer 123 mode register
Data bus buffer control
register 0
Port control register
Data bus buffer control
register 0
Port control register
USB control register
Port control register
Data bus buffer control
register 1
Port control register
CPU mode register B
UART1, 2 control registers
Serial I/O control register 1
Serial I/O control register 2
Port control register
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
Notes 1: For details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable
sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a rush current will flow from VCC to VSS through the input-stage gate.
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7641 Group
(1) Ports P0, P1, P3
(2) Port P2
Direction
register
Data bus
P2 pull-up
Direction
register
Port latch
Data bus
Port latch
Key interrupt input
(3) Port P40
(4) Ports P41, P42
Direction
register
Expanded data
memory access bit
Direction
register
Data bus
Data bus
Port latch
Port latch
INT0, INT1 interrupt input
EDMA signal
(5) Ports P43, P44
(6) Port P50
Sub-clock (XCIN-XCOUT) stop bit
Timer count enabled
Pulse output mode selected
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
Timers X, Y output
CNTR0, CNTR1 input
Fig. 12 Port block diagram (1)
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XCIN input
7641 Group
(7) Port P51
(8) Port P52
XCOUT oscillation drive disable bit
Sub-clock (XCIN-XCOUT) stop bit
OBF0 output enable bit
TOUT output control bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Timer 1, 2 output
XCOUT output
OBF0 output
(10) Ports P54 to P57
(9) Port P53
Master CPU bus
interface enable bit
IBF0 output enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Master CPU bus
functions input ✻
IBF0 output
(11) Port P6
(12) Port P70
Write to Master CPU bus interface
USB SOF port select bit
S0
S1
Read from Master CPU bus interface
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
DBBOUT0
A0
DBBS0
S0
Read from Master CPU bus
interface
S1
✻: Ports P54 to P57 functions
DBBOUT1
A1
DBBS1
S0
Write to Master CPU
bus interface
S1
DBBIN0
DBBIN1
Fig. 13 Port block diagram (2)
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SOF signal
page 17 of 135
Pin name
P54
P55
P56
P57
Functions
S0
A0
R(E)
W(R/W)
7641 Group
(13) Port P71
(14) Port P72
Data bus buffer function select bit
HOLD function enable bit
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Data bus buffer
function select bit
HOLD function
enable bit
S1
HOLD
(15) Port P73
(16) Port P74
OBF1 output enable bit
Data bus buffer function select bit
IBF1 output enable bit
Data bus buffer function
HOLD function
select bit
enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
OBF1 output
IBF1 output
HLDA
(17) Port P80
(18) Port P81
SRDY output select bit
(UART2) Transmit enable bit
(Serial I/O) Internal synchronous clock select bits
Serial I/O port select bit
(UART2) Receive enable bit
SPI mode select bit
(UART2) Receive enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
(Serial I/O) Internal
synchronous clock
select bits
SRDY output
Serial I/O clock output
(UART2) UTXD2 output
SPI mode select bit
Control for SPI
compatible mode
(UART2) Receive enable bit
(UART2) URXD2 input
Serial I/O clock input
Fig. 14 Port block diagram (3)
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7641 Group
(19) Port P82
(20) Port P83
Transmit completed signal
Serial I/O port select bit
(Serial I/O) SRXD input enable bit
(UART2) CTS function enable bit
STXD output channel
control bit
Direction
register
(UART2) RTS function enable bit
Direction
register
P
Poorrtt llaattcchh
Data bus
Data bus
Port latch
(UART2) CTS function enable bit
(UART2) CTS2 input
(Serial I/O) STXD output
(Serial I/O) SRXD input
(UART2) RTS2 input
(21) Port P84
(22) Port P85
(UART1) Transmit enable bit
(UART1) Receive enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
(UART1) URXD1 input
(UART1) UTXD1 output
(23) Port P86
(24) Port P87
(UART1) RTS function enable bit
(UART1) CTS function enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
(UART1) CTS1 input
Fig. 15 Port block diagram (4)
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Port latch
(UART1) RTS1 output
7641 Group
INTERRUPTS
Interrupt Operation
There are twenty-four interrupt sources: five externals, eighteen
internals, and one software.
When an interrupt request occurs, the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The Interrupt Disable Flag is set and the corresponding interrupt request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an Interrupt Request Bit and an Interrupt Enable Bit, and is controlled by the
Interrupt Disable Flag (I). An interrupt occurs if the corresponding
Interrupt Request and Enable Bits are “1” and the Interrupt Disable
Flag is “0”.
Interrupt Enable Bits can be set or cleared by software. Interrupt Request Bits can be cleared by software, but cannot be set by software.
Additionally, an active edge of INT1 and INT2 can be selected by
using the interrupt edge select register (address 001116); an active
edge of CNTR0 can be done by using the timer X mode register
(address 002716); an active edge of CNTR1 can be done by using
the timer Y mode register (address 002816).
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I Flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occur at the
same time, the interrupt with the highest priority is accepted first.
■Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt polarity select register (address 001116)
Timer X mode register (address 002716)
Timer Y mode register (address 002816)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
➀Set the corresponding Interrupt Enable Bit to “0” (disabled).
➁Set the Interrupt Edge Select Bit (Active Edge Switch Bit).
➂Set the corresponding Interrupt Request Bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding Interrupt Enable Bit to “1” (enabled).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Fig. 16 Interrupt control
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Interrupt request
7641 Group
Table 7 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Source Priority
High
Low
Reset (Note 3)
1
FFFB16
FFFA16
USB function
2
FFF916
FFF816
USB SOF
3
FFF716
FFF616
INT0
4
FFF516
FFF416
Interrupt Request
Generating Conditions
INT1
5
FFF316
FFF216
DMAC0
DMAC1
UART1 receive
buffer full
UART1 transmit
UART1
summing error
UART2 receive
buffer full
UART2 transmit
UART2
summing error
Timer X
Timer Y
Timer 1
Timer 2
Timer 3
CNTR0
6
7
8
FFF116
FFEF16
FFED16
FFF016
FFEE16
FFEC16
At reset
(Note 2)
At reception of SOF packet
At detection of either rising or falling edge of
INT0 intput
At detection of either rising or falling edge of
INT1 input
At completion of DMAC0 transfer
At completion of DMAC1 transfer
At completion of UART1 reception
9
10
FFEB16
FFE916
FFEA16
FFE816
At completion of UART1 transmission
At detection of UART1 summing error
11
FFE716
FFE616
At completion of UART2 reception
12
13
FFE516
FFE316
FFE416
FFE216
At completion of UART2 transmission
At detection of UART2 summing error
14
15
16
17
18
19
FFE116
FFDF16
FFDD16
FFDB16
FFD916
FFD716
FFE016
FFDE16
FFDC16
FFDA16
FFD816
FFD616
CNTR1
20
FFD516
FFD416
Serial I/O
21
FFD316
FFD216
Input buffer full
Output buffer
empty
Key input (Keyon wake-up)
BRK instruction
22
23
FFD116
FFCF16
FFD016
FFCE16
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At completion of serial I/O transmission/reception
At writing to input data bus buffer
At reading from output data bus buffer
24
FFCD16
FFCC16
At falling of port P2 input logical level AND
25
FFCB16
FFCA16
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: USB function interrupt occurs owing to an interrupt request of the endpoint x (x = 0 to 4) IN, endpoint x OUT, overrun/underrun, USB reset or suspend/
resume.
3: Reset functions in the same way as an interrupt with the highest priority.
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7641 Group
b7
b0
b7
b0
Interrupt request register A (address 000216)
IREQA
Interrupt request register B address (address 000316)
IREQB
USB function interrupt request bit
USB SOF interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
DMAC0 interrupt request bit
DMAC1 interrupt request bit
UART1 receive buffer full interrupt request bit
UART1 transmit interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
UART1 summing error interrupt request bit
UART2 receive buffer full interrupt request bit
UART2 transmit interrupt request bit
UART2 summing error interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b0
Interrupt request register C (address 000416)
IREQC
0
Interrupt control register A (address 000516)
ICONA
USB function interrupt enable bit
USB SOF interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit
DMAC0 interrupt enable bit
DMAC1 interrupt enable bit
UART1 receive buffer full interrupt enable bit
UART1 transmit interrupt enable bit
Timer 3 interrupt request bit
CNT R0 interrupt request bit
CNT R1 interrupt request bit
Serial I/O interrupt request bit
Input buffer full interrupt request bit
Output buffer empty interrupt request bit
Key input interrupt request bit
Reserved bit (“0” at read/write)
0 : Interrupts disabled
1 : Interrupts enabled
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
Interrupt control register B (address 000616)
ICONB
0
UART1 summing error interrupt enable bit
UART2 receive buffer full interrupt enable bit
UART2 transmit interrupt enable bit
UART2 summing error interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
b7
0 0 0 0 0 0
b0
Interrupt polarity select register (address
001116 )
IPOL
INT0 interrupt edge select bit
0 : Falling edge active
INT1 interrupt edge select bit
Reserved bits (“0” at read/write) 1 : Rising edge active
Fig. 17 Structure of interrupt-related registers
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b0
Interrupt control register C (address 000716)
ICONC
Timer 3 interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Serial I/O interrupt enable bit
Input buffer full interrupt enable bit
Output buffer empty interrupt enable bit
Key input interrupt enable bit
Reserved bit (“0” at read/write)
0 : Interrupts disabled
1 : Interrupts enabled
7641 Group
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by applying “L” level to any
pin of port P2 that have been set to input mode. In other words, it is
generated when AND of input level goes from “1” to “0”. An example
of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as
an active-low key matrix which inputs to ports P20–P24.
Port PXx
“L” level output
P27 output
P26 output
P25 output
P24 input
P23 input
P22 input
P21 input
P20 input
Port P2 pull-up control register
Bit 7 = “0”
Port P27
direction register = “1”
✻
✻✻
Port P27
latch
Falling edge
detector
Key input interrupt request
Port P2 pull-up control register
Bit 6 = “0”
Port P26
direction register = “1”
✻
✻✻
Port P26
latch
Falling edge
detector
Port P2 pull-up control register
Bit 5 = “0”
Port P25
direction register = “1”
✻
✻✻
Port P25
latch
Falling edge
detector
Port P2 pull-up control register
Bit 4 = “0”
Port P24
direction register = “0”
✻
✻✻
Port P24
latch
Falling edge
detector
Port P2 pull-up control register
Bit 3 = “0”
Port P23
direction register = “0”
✻
✻✻
Port P23
latch
Falling edge
detector
Port P2
Input reading circuit
Port P2 pull-up control register
Bit 2 = “0”
Port P22
direction register = “0”
✻
✻✻
Port P22
latch
Falling edge
detector
Port P2 pull-up control register
Bit 1 = “0”
Port P21
direction register = “0”
✻
✻✻
Port P21
latch
Falling edge
detector
Port P2 pull-up control register
Bit 0 = “0”
Port P20
direction register = “0”
✻
✻✻
Port P20
latch
Falling edge
detector
✻ P-channel transistor for pull-up
✻✻ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
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7641 Group
TIMERS
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 7641 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”
or “000016”, an underflow occurs at the next count pulse and the
corresponding timer latch is reloaded into the timer and the count
is continued. When a timer underflows, the interrupt request bit
corresponding to that timer is set to “1”.
SCSGCLK
Timer X internal clock
select bit
φ/8
φ / 16
φ / 32
φ / 64
Timer X count source
select bits
Timer X count
stop bit
“00”
“01”
CNTR0 active edge
switch bit “0”
P43/CNTR0
“11”
Timer X (high) latch (8)
Timer X (low) (8)
Timer X (high) (8)
Timer X interrupt
request
Timer X
operating “10”
mode bits
“1”
CNTR0 active edge
switch bit “0”
Q
“1”
P54 direction register
CNTR0 interrupt
request
Pulse output mode
T
Pulse width HL continuously
measurement mode
Q
Rising edge detection
P43 latch
Pulse output mode
Falling edge detection
Pulse width HL
continuously measurement,
Period measurement modes
φ/8
φ / 16
φ / 32
φ / 64
P44/CNTR1
Timer X write control bit
Timer X (low) latch (8)
CNTR1 active
edge switch bit
“0”
“1”
Timer Y count
stop bit
“00”
“01”
“11”
Timer Y (low) latch (8)
Timer Y (low) high (8)
Timer Y (low) (8)
Timer Y (high) (8)
“10”
Timer Y
operating mode
bits
Timer mode,
TYOUT output enabled
“0”
CNTR1 active
edge switch bit
Timer mode,
TYOUT output enabled
Timer 1 count
source select bit
“0”
φ/8
f(XCIN) / 2
“1”
“1”
S
Q
T
Timer Y write
control bit
Timer Y
operating mode
bits
Q
Timer Y interrupt
request
“11”
CNTR1 interrupt
request
“00”
“01”
“10”
Timer 1 interrupt
request
Timer 1 count
stop bit
Timers 1, 2 write control
Timers 1, 2 write control
bit
bit
Timer 2 latch (8)
“0”
Timer 1 latch (8)
Timer 1 (8)
Timer 2 (8)
Timer 2 count
source select bit
“1”
Timer 2 interrupt
request
φ
TOUT output control bit
TOUT output active “0”
edge switch bit
Q
T
“1”
Q
“0”
TOUT source
select bit
Timer 3 (8)
φ/8
P51/TOUT/XCOUT
“1”
TOUT output control bit
TOUT output
control bit
“0”
Q
TOUT output active
edge switch bit
“1”
Fig. 19 Timer block diagram
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T
Q
Timer 3 latch (8)
Timer 3 count
source select bit
Timer 3 interrupt
request
7641 Group
Timer X
■ Notes
Timer X is a 16-bit timer that can be selected in one of four modes.
The timer X’s internal clock and count source can be selected and
a write control is possible by using the timer X mode register.
In all modes the count operation can halt by setting the Timer X
Count Stop Bit to “1”. Additionally, each timer underflow sets the
Interrupt Request Bit to “1”.
● Timer X Write Control
If the Timer X Write Control Bit is “1”, when the value is written in
the address of timer X, the value is loaded only in the latch. The
value in the latch is loaded in timer X after timer X underflows.
If the Timer X Write Control Bit is “0”, when the value is written in
the address of timer X, the value is loaded in the timer X and the
latch at the same time.
When the value is to be written in latch only, unexpected value
may be set in the high-order timer if the writing in high-order latch
and the underflow of timer X are performed at the same timing.
(1) Timer Mode
The timer counts the SCSGCLK (Special Count Source Generator) or one of the internal clock φ divided by 8, 16, 32, 64.
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode.
When the CNTR0 Active Edge Switch Bit is “0”, the CNTR 0 pin
starts pulses output beginning at “H”; when this bit is “1”, the
CNTR0 pin starts pulses output beginning at “L”.
When using a timer in this mode, set the port P43 direction register to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
When the CNTR0 Active Edge Switch Bit is “0”, the rising edge is
counted; when this bit is “1”, the falling edge is counted.
When using a timer in this mode, set the port P43 direction register to input mode.
● CNTR0 Interrupt Active Edge Selection
The CNTR 0 interrupt active edge depends on the selection of
CNTR0 Active Edge Switch Bit.
b7
b0
Timer X mode register (address 002716)
TXM
Timer X write control bit
0: Write value in latch and counter
1: Write value in latch only
Timer X count source select bits
b2b1
0 0: φ / 8
0 1: φ / 16
1 0: φ / 32
1 1: φ / 64
Timer X internal clock select bit
0: φ / n (n = 8, 16, 32, 64)
1: SCSGCLK (Special Count Source Generator)
Timer X operating mode bits
b5b4
(4) Pulse Width Measurement Mode
When the CNTR0 Active Edge Switch Bit is “0”, the timer counts
while the input signal of CNTR0 pin is at “H”; when it is “1”, the
timer counts while the input signal of CNTR0 pin is at “L”.
The timer counts the SCSGCLK or one of the internal clock φ divided by 8, 16, 32, 64 as its count source.
When using a timer in this mode, set the port P43 direction register to input mode.
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge switch bit
0: Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for interrupt
1: Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for interrupt
Timer X count stop bit
0: Count start
1: Count stop
Fig. 20 Structure of timer X mode register
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7641 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts one of the internal clock φ divided by 8, 16, 32,
64.
● TYOUT Output Function
In the timer mode, a signal of which polarity is inverted each time
the timer underflows is output from the CNTR1 pin. This is enabled
by setting the Timer Y Output Control Bit to “1”.
When the CNTR1 Active Edge Switch Bit is “0”, the CNTR 1 pin
starts pulses output beginning at “H”; when this bit is “1”, the
CNTR1 pin starts pulses output beginning at “L”.
When using a timer in this mode, set the port P44 direction register to output mode.
(2) Period Measurement Mode
CNTR1 interrupt request is generated at a rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Except for the aforementioned operation, the operation in period
measurement mode is the same as in timer mode. (The TY OUT
output function is not usable.)
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR 1 pin input signal is found by
CNTR1 interrupt.
When the CNTR1 Active Edge Switch Bit is “0”, the falling edge is
detected; when this bit is “1”, the rising edge is detected.
When using a timer in this mode, set the port P44 direction register to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. (The TYOUT output function is not usable.)
When the CNTR1 Active Edge Switch Bit is “0”, the rising edge is
counted; when this bit is “1”, the falling edge is counted.
When using a timer in this mode, set the port P44 direction register to input mode.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
When using a timer in this mode, set the port P44 direction register to input mode.
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■ Notes
● Timer Y Write Control
If the Timer Y Write Control Bit is “1”, when the value is written in
the address of timer Y, the value is loaded only in the latch. The
value in the latch is loaded in timer Y after timer Y underflows.
If the Timer Y Write Control Bit is “0”, when the value is written in
the address of timer Y, the value is loaded in the timer Y and the
latch at the same time.
When the value is to be written in latch only, unexpected value
may be set in the high-order timer if the writing in high-order latch
and the underflow of timer Y are performed at the same timing.
● CNTR1 Interrupt Active Edge Selection
The CNTR 1 interrupt active edge depends on the selection of
CNTR1 Active Edge Switch Bit.
However, in pulse width HL continuously measurement mode,
CNTR 1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 Active Edge Switch Bit.
b7
b0
Timer Y mode register (address 002816)
TYM
Timer Y write control bit
0: Write value in latch and counter
1: Write value in latch only
Timer Y output control bit
0: TYOUT output disabled
1: TYOUT output enabled
Timer Y count source select bits
b3b2
0 0: φ / 8
0 1: φ / 16
1 0: φ / 32
1 1: φ / 64
Timer Y operating mode bits
b5b4
0 0: Timer mode
0 1: Period measurement mode
1 0: Event counter mode
1 1: Pulse width HL continuously measurement mode
CNTR1 active edge switch bit
0: Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for interrupt
Start from “H” output for TYOUT signal
1: Count at falling edge in event counter mode
Measure the rising edge to rising edge
period in period measurement mode
Rising edge active for interrupt
Start from “L” output for TYOUT signal
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 21 Structure of timer Y mode register
7641 Group
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register.
● Timers 1, 2 Write Control
When the Timers 1, 2 Write Control Bit is “1” and the values are
written in the address of timers 1 and 2, the values are loaded only
in their latches. The values in the latches are loaded in timers 1
and 2 after timers 1 and 2 underflow.
When the Timers 1, 2 Write Control Bit is “0” and the values are
written in the address of timers 1 and 2, the values are loaded in
the timers 1 and 2 and their latches at the same time.
● Timers 1, 2 Output Control
A signal of which polarity is inverted each time the timer selected
by the TOUT Factor Select Bit underflows is output from the TOUT
pin. This is enabled by setting the TOUT Output Control Bit to “1”.
When the TOUT Output Active Edge Switch Bit is “0”, the TOUT pin
starts pulses output beginning at “H”; when this bit is “1”, the TOUT
pin starts pulses output beginning at “L”.
When using a timer in this mode, set the port P51 direction register to output mode.
b0
Timer 123 mode register (address 002916)
T123M
TOUT factor select bit
0: Timer 1 output
1: Timer 2 output
Timer 1 count stop bit
0: Count start
1: Count stop
Timer 1 count source select bit
0:φ/8
1 : f(XCIN) / 2
Timer 2 count source select bit
0 : Timer 1 output
1:φ
Timer 3 count source select bit
0 : Timer 1 output
1:φ/8
TOUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
TOUT output control bit
0: TOUT output disabled
1: TOUT output enabled
Timers 1, 2 write control bit
0: Write value in latch and counter
1: Write value in latch only
Fig. 22 Structure of timer 123 mode register
■ Notes
● Timer 1 to Timer 3
Switching of the count sources of timers 1 to 3 does not affect the
values of reload latches. However, that may make count operation
started. Therefore, write values again in the order of timers 1, 2
and then timer 3 after their count sources have been switched.
● Timers 1, 2 Write Control
When the value is to be written in latch only, unexpected value
may be set in the timer if the writing in the latch and the timer underflow are performed at the same timing.
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b7
page 27 of 135
7641 Group
SERIAL INTERFACE
Serial I/O
b7
b0
Serial I/O control register 1 (address 002B16)
SIOCON1
The serial I/O can be used only for clock synchronous serial I/O.
The transmitter and the receiver must use the same clock. If the
internal clock is used, transfer is started by a write signal to the
serial I/O shift register.
Internal synchronous clock select bits (Note 1)
b2b1b0
0 0 0: Internal clock divided by 2
0 0 1: Internal clock divided by 4
0 1 0: Internal clock divided by 8
0 1 1: Internal clock divided by 16
1 0 0: Internal clock divided by 32
1 0 1: Internal clock divided by 64
1 1 0: Internal clock divided by 128
1 1 1: Internal clock divided by 256
Serial I/O port select bit
0: I/O port
1: STXD, SCLK signal output
SRDY output select bit
0: I/O port
1: SRDY signal output
Transfer direction select bit
0: LSB first
1: MSB first
Synchronous clock select bit
0: External clock
1: Internal clock
STXD output channel control bit
0: CMOS output
1: N-channel open drain output
[Serial I/O Control Register 1 (SIOCON1)] 002B16
[Serial I/O Control Register 2 (SIOCON2)] 002C16
Each of the serial I/O control registers 1 and 2 contains eight bits
which control various serial I/O functions.
b7
0 0 0
b0
Serial I/O control register 2 (address 002C16)
SIOCON2
SPI mode select bit
0: Normal serial I/O mode
1: SPI compatible mode (Note 2)
Serial I/O internal clock select bit
0: φ
1: SCSGCLK
SRXD input enable bit
0: SRXD input disabed
1: SRXD input enabed
Clock polarity select bit (CPoL)
0: SCLK starting at “L”
1: SCLK starting at “H”
Clock phase select bit (CPha)
0: Serial transfer starting at falling edge of SRDY
1: Serial transfer starting afer a half cycle of SCLK
passed at falling edge of SRDY
Reserved bits (“0” at read/write)
Notes 1: The source of serial I/O internal synchronous clock can be selected by bit 1 of
serial I/O control register 2.
2 : To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”.
Fig. 23 Structure of serial I/O control registers 1, 2
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7641 Group
1/2
SCSGCLK
1/4
φ
Divider
Serial I/O internal
“1” clock select bit
“0 ”
Data bus
1/8
1/16
1/32
1/64
1/128
Synchronous
clock select bit
“1 ”
1/256
“0”
“0”
P80 latch
P80/UTXD2/SRDY
“1”
SRDY output select bit
“0 ”
Internal synchronous
clock selection bits
External clock
Synchronization
circuit
P81 latch
P81/URXD2/SCLK
Serial I/O counter (3)
“1”
Serial I/O port select bit
“0”
P83/RTS2/STXD
P82/CTS2/SRXD
P83 latch
“1” Serial I/O port select bit
“1 ”
Serial I/O shift register (8)
“0 ”
SRXD input enable bit
Fig. 24 Block diagram of serial I/O
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SPI mode select bit
page 29 of 135
Serial I/O
interrupt request
7641 Group
●Serial I/O Normal Operation
The serial I/O counter is set to “7” by writing operation to the serial
I/O shift register (address 002A16). When the SRDY Output Select
bit is “1”, the SRDY pin goes “L” after that writing. On the negative
edge of the transfer clock the SRDY pin returns “H” and the data
of the first bit is transmitted from the STXD pin. The remaining
data are done from the STXD pin bit by bit on each falling edge of
the transfer clock.
Additionally, the data is latched from the SRXD pin on each rising
edge of the transfer clock and then the contents of the serial I/O
shift register are shifted by one bit.
When the internal system clock is selected as the transfer clock,
the followings occur at counting eight transfer clocks:
•The serial I/O counter reaches “0”
•The transfer clock halts at “H”
•The serial I/O interrupt request bit is set to “1”
•The STXD pin goes a high-impedance state after an 8-bit transfer
is completed.
When the external clock is selected as the transfer clock, the followings occur at counting eight transfer clocks:
•The serial I/O counter reaches “0”
•The serial I/O interrupt request bit is set to “1”
In this case, the transfer clock needs to be controlled by the external source because the transfer clock does not halt. Additionally,
the STXD pin does not go a high-impedance state after an 8-bit
transfer is completed.
Figure 25 shows serial I/O timing.
●Normal mode timing (LSB first)
Synchronizing clock
Transfer clock
Serial I/O shift
register write signal
SRDY signal
(Note)
D0
Serial I/O output STXD
D1
D2
D3
D4
D5
D6
D7
Serial I/O input SRXD
Interrupt request bit is set to “1”.
Note: When the internal clock is selected as the transfer clock, the STXD pin goes to a high-impedance state after transfer completion.
●SPI compatible mode timing
SRDY signal
Synchronizing clock
SCLK (CPoL = 1, CPha =1 )
SCLK (CPoL = 0, CPha = 1)
SCLK (CPoL = 1, CPha = 0)
SCLK (CPoL = 0, CPha = 0)
STXD/SRXD
First
Fig. 25 Serial I/O timing
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Last
7641 Group
●SPI Compatible Mode Operation
Setting the SPI Mode Select Bit (bit 0 of SIOCON2) puts the serial
I/O in SPI compatible mode. The Synchronous Clock Select Bit
(bit 6 of SIOCON1) determines whether the serial I/O is an SPI
master or slave. When the external clock is selected (“0”), the serial I/O is in slave mode; When the internal clock is selected (“1”),
the serial I/O is in master mode.
In SPI compatible mode the SRXD pin functions as a MISO (Master In/Slave Out) pin and the STXD pin functions as a MOSI
(Master Out/Slave In) pin.
In slave mode the transmit data is output from the MISO pin and
the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal input pin from an external.
In master mode the transmit data is output from the MOSI pin and
the receive data is input from the MISO pin. The SRDY pin functions as the chip-select signal output pin to an external.
• Slave Mode Operation
In slave mode of SPI compatible mode 4 types of clock polarity
and clock phase can be usable by bits 3 and 4 of serial I/O control
register 2.
If the SRDY pin is held “H”, the shift clock is inhibited, the serial I/
O counter is set to “7”. If the SRDY pin is held “L”, then the shift
clock will start.
Make sure during transfer to maintain the SRDY input at “L” and
not to write data to the serial I/O counter.
Figure 25 shows the serial I/O timing.
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7641 Group
UART1, UART2
The UART consists of two channels: UART1 and UART2. Each
has a dedicated timer provided to generate transfer clocks and operates independently. Both UART1 and UART2 have the same
functions.
Twelve serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
The transfer speed (baud rate) is expression as follows:
Transfer speed (baud rate) = fi / {(n + 1) ✕ 16 }
n: The contents of UARTx (x = 1, 2) baud rate generator
fi: Using UART clock prescaling select bits, select any one of φ, φ/
8, φ/32, φ/256, SCSGCLK, SCSGCLK/8, SCSGCLK/32 and
SCSGCLK/256
Data bus
Addresses 003516
Addresses 003D16
003416
003C16
Address 003016
Address 003816
Receive buffer full flag (RBF)
Receive buffer full interrupt request (UxRBF)
Receive summing error interrupt request (UxES)
UARTx mode register
Receive buffer register 1
OER
Receive buffer register 2
UART character length select bits
P85/URXD1
Receive shift register 1
ST
7 bits
P81/URXD2/SCLK
Receive shift register 2
detector
8 bits
9 bits
P87/RTS1
P83/RTS2/STXD
φ
SCSGCLK
P86/CTS1
P82/CTS2/SRXD
RTS control register
UART clock
Prescaler
select bit
1/1
1/8
1/32
1/256
PER FER
Address 003316
Address003B16
UARTx control register
SPdetector
Clock control circuit
Addresses 003616
Frequency
Addresses 003E16
Addresses 003116 division ratio
Addresses 003916 1/(n+1)
Baud rate generator
1/16
ST/SP/PA generator
UART clock
prescaling select bits
Transmit shift register 1
Transmit shift register 2
P84/UTXD1
P80/UTXD2/SRDY
Character length select bit
Transmit buffer register 1
Transmit buffer register 2
Addresses 003516
Addresses 003D16
003416
003C16
Data bus
Fig. 26 UARTx (x = 1, 2) block diagram
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Transmit comple flag
(TCM)
Transmit interrupt source select bit
Transmit interrupt
request (UxTX)
Transmit buffer empty
UART status register flag (TBE)
Address 003216
Address 003A16
7641 Group
●UART Transmit Operation
Transmission starts when the Transmit Enable Bit is “1” and the
Transmit Buffer Empty Flag is “0”. Additionally, when CTS function
enabled, the CTSx pin must be “L” to be started. The data in which
Start Bit and Stop Bit or Parity Bit are also added is transmitted
from the low-order byte sequentially. When using 9-bit character
length, set the data into the UARTx transmit buffer register 2
(high-order byte) first before the UARTx transmit buffer register 1
(low-order byte).
Once the transmission starts, the Transmit Enable Bit, the Transmit Buffer Empty Flag and the CTSx pin state (when this is
enabled) could not be checked until the transmission in progress
has ended.
Transmission requires the following setup:
(1) Define a baud rate by setting a value n (n = 0 to 255) into
UARTx baud rate generator (addresses 003116, 003916).
(2) Set the Transmit Initialization Bit (bit 2 of UxCON) to “1”. This
will set the UARTx status register to “0316”.
(3) Select the interrupt source with the Transmit Interrupt Source
Select Bit (bit 4 of UxCON).
(4) Configure the data format and clock selection by setting the
UARTx mode register.
(5) Set the CTS Function Enable Bit (bit 5 of UxCON) if CTS function will be used.
(6) Set the Transmit Enable Bit (bit 0 of UxCON) to “1”.
●UART Receive Operation
Reception is enabled when the Receive Enable Bit is “1”. Detection of the start bit makes transfer clocks generated and the data
reception starts in the LSB first.
When using 9-bit character length, read the received data from the
UARTx receive buffer register 2 (high-order byte) first before the
UARTx receive buffer register 1 (low-order byte).
Reception requires the following setup:
(1) Define a baud rate by setting a value n (n = 0 to 255) into
UARTx baud rate generator (addresses 003116, 003916).
(2) Set the Receive Initialization Bit (bit 3 of UxCON) to “1”.
(3) Configure the data format and clock selection by setting the
UARTx mode register.
(4) Set the RTS Function Enable Bit (bit 5 of UxCON) if RTS function will be used.
(5) Set the Receive Enable Bit (bit 1 of UxCON) to “1”.
●CTS (Clear-to-Send) Function
As a transmitter, the UART can be configured to recognize the
Clear-to-Send (CTSx) input as a handshaking signal. This is enabled by setting the CTS Function Enable Bit (bit 5 of UxCON) to
“1”. If CTS function is enabled, even when transmission is enabled
and the UARTx transmit buffer register is filled with the data, the
transmission never starts; but it will start when inputting “L” to the
CTSx pin.
Figures 27 and 28 show the UARTx transmit timings.
If updating a value of UARTx baud rate generator while the data is
being transmitted, be sure to disable the transmission before updating. If the former data remains in the UARTx transmit buffer
registers 1 and 2 at retransmission, an undefined data might be
output.
Transfer clock
Tranmit enable bit
Data set into UARTx transmit buffer register 1
Transmit buffer
empty flag
Data transferring from UARTx
transmit buffer register 1 to Transmit shift register 1
CTSx pin
(P86/CTS1, P82/CTS2/SRXD)
UTXD output (P84/UTXD1,
P80/UTXD2/SRDY)
Halt due to CTS = “H”
ST
D0
D1
D2
D3 D4
D5 D6
Transmit complete flag
This timing applying to the conditions:
•Character length = 8 bits
•Parity enabled
•1 stop bit
Fig. 27 UARTx transmit timing (CTS function enabled)
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
Halt due to Tranmit
enable bit = “0”
page 33 of 135
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
7641 Group
●RTS (Request-to-Send) Function
As a receiver, the UART can be configured to generate the Request-to-Send (RTSx) handshaking signal. This is enabled by
setting the RTS Function Enable Bit (bit 6 of UxCON) to “1”.
When reception is enabled, that is the Receive Enable Bit is “1”,
the RTSx pin goes “L” to inform a transmitter that reception is possible. The RTSx pin goes “H” at reception starting and does “L” at
receiving of the last bit.
The delay time from the reception of the last stop bit to the assertion of RTSx is selectable using the RTS Assertion Delay Count
Select Bits.
When the Receive Enable Bit is set to “0” or the Receive initialization bit is set to “1”, the RTSx pin goes “H”. Even when the
Receive Enable Bit is set to “1”, the RTSx pin goes “H” if detecting
an invalid start bit.
Figure 29 shows the UARTx receive timing.
Transfer clock
Tranmit enable bit
Data set into UARTx transmit buffer register 1
Transmit buffer
empty flag
Data transferring from UARTx transmit
buffer register 1 to Transmit shift register 1
UTXD output (P84/UTXD1,
P80/UTXD2/SRDY)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
Transmit complete flag
This timing applies to the conditions:
•Character length = 8 bits
•Parity enabled
•1 stop bit
Fig. 28 UARTx transmit timing (CTS function disbled)
BRGx (x = 1, 2)
count source
Receive enable bit
URXD (P85/URXD1,
P81/URXD2/SCLK)
ST
Transfer clock generated at falling edge
of start bit and receive started
D0
D1
D7
SP
Receive data latched
Transfer clock
Data transferring from UARTx receive register
1 to Receive buffer register 1 (Note)
Receive buffer
empty flag
RTSx pin (P87/RTS1,
P83/RTS2/STXD)
Note: When no RTS assertion delay, the RTSx pin goes “L”.
The RTS assertion delay counts are selected by bits 4 to 7 of UARTx RTS control register.
This timing applies to the conditions:
•Character length = 8 bits
•Parity enabled
•1 stop bit
Fig. 29 UARTx transmit timing (RTS function enabled)
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 34 of 135
P
SP
ST
D0
D1
7641 Group
●UART Address Mode
The UART address mode is intended for use to communicate between the specified MCUs in a multi-MCU environment. The
UART address mode can be used in either an 8-bit or 9-bit character length. An address is identified by the MSB of the incoming
data being “1”. The bit is “0” for non-address data.
When the MSB of the incoming data is “0” in the UART address
mode, the Receive Buffer Full Flag is set to “1”, but the Receive
Buffer Full Interrupt Request Bit is not set to “1”. When the MSB of
the incoming data is “1”, normal receive operation is performed. In
the UART address mode an overrun error is not detected for reception of the 2nd and onward bytes. An occurrence of framing
error or parity error sets the Summing Error Interrupt Request Bit
to “1” and the data is not received independent of its MSB contents.
Usage of UART address mode is explained as follows:
(1) Set the UART Address Mode Enable Bit to “1”.
(2) Sends the address data of a slave MCU first from a host MCU
to all slave MCUs. The MSB of address data must be “1” and
the remaining 7 bits specify the address.
(3) The all slave MCUs automatically check for the received data
whether its stop bit is valid or not, and whether the parity error
occurs or not (when the parity enabled). If these errors occur,
the Framing Error Flag or Parity Error Flag and the Summing
Error Flag are set to “1”. Then, the Summing Error Interrupt
Request Bit is also set to “1”.
(4) When received data has no error, the all slave MCUs must
judge whether the address of the received address data
matches with their own addresses by a program. After the
MSB being “1” is received, the UART Address Mode Enable
Bit is automatically set to “0” (disabled).
(5) The UART Address Mode Enable Bit of the slave MCUs which
have be judged that the address does not match with them
must be set to “1” (enabled) again by a program to disable reception of the following data.
(6) Transmit the data of which MSB is “0” from the host MCU. The
slave MCUs disabling the UART address mode receive the
data, and their Receive Buffer Full Flags and the Receive
Buffer Full Interrupt Request Bits are set to “1”. For the other
slave MCUs enabling the UART address mode, their Receive
Buffer Full Flag are set to “1”, but their Receive Buffer Full Interrupt Request Bits are not set to “1”.
(7) An overrun error cannot be detected after the first data has
been received in UART Address Mode. Accordingly, even if
the slave MCUs does not read the received data and the next
data has been received, an overrun error does not occur.
Thus, a communication between a host MCU and the specified
MCU can be realized.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 35 of 135
[UARTx (x = 1, 2) Mode Register (UxMOD)] 003016, 003816
The UART x mode register consists of 8 bits which set a transfer
data format and an used clock.
[UARTx (x = 1, 2) Baud Rate Generator (UxBRG)] 0031 16 ,
003916
The UARTx baud rate generator determines the baud rate for
transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
The reset cannot affect the contents of baud rate generator.
[UARTx (x = 1, 2) Status Register (UxSTS)] 003216, 003A16
The read-only UARTx status register consists of seven flags (bits
0 to 6) which indicate the UART operating status and various errors.
When the UART address mode is enabled , the setting and clearing conditions of each flag differ from the following explanations.
These differences are explained in section “UART Address
Mode”.
•Transmit complete flag (TCM)
In the case where no data is contained in the transmit buffer register, the Transmit Complete Flag (TCM) is set to “1” when the last
bit in the transmit shift register is transmitted.
The TCM flag is also set to “1” at reset or initialization by setting
the Transmit Initialization Bit (bit 2 of UxCON). It is set to “0” when
transmission starts, and it is kept during the transmission.
•Transmit buffer empty flag (TBE)
The Transmit Buffer Empty Flag (TBE) is set to “1” when the contents of the transmit buffer register are loaded into the transmit
shift register. The TBE flag is also set “1” at the hardware reset or
initialization by setting the Transmit Initialization Bit. It is set to “0”
when a write operation is performed to the low-order byte of the
transmit buffer register.
•Receive buffer full flag (RBF)
The Receive Buffer Full Flag (RBF) is set to “1” when the last stop
bit of the data is received. The RBF flag is set to “0” when the loworder byte of the receive buffer register is read, at the hardware
reset or initialization by setting the Transmit Initialization Bit.
7641 Group
●Receive Errors
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the Receive Buffer Full Flag is set to “1”. The all error
flags PER, FER, OER and SER are cleared to “0” when the
UARTx status register is read, at the hardware reset or initialization by setting the Transmit Initialization Bit.
The Summing Error Flag (SER) is set to “1” when any one of the
PER, FER and OER is set to “1”.
The Parity Error Flag (PER) is set to “1” when the sum total of 1s
of received data and the parity does not correspond with the selection with the Parity Select Bit (PMD). It is enabled only if the
Parity Enable Bit (bit 5 of UxMOD) is set to “1”.
The Framing Error Flag (FER) is set to “1” when the number of
stop bit of the received data does not correspond with the selection with the Stop Bit Length Select Bit (STB).
The Overrun Flag Flag (OER) is set to “1” if the previous data in
the low-order byte of the receive buffer register 1 (addresses
003416, 003C16) is not read before the current receive operation is
completed. It is also set “1” if any one of error flags is “1” for the
previous data and the current receive operation is completed. Be
sure to read UARTx status register to clear the error flags before
the next reception has been completed.
[UARTx (x = 1, 2) Control Register (UxCON)] 003316, 003B16
The UARTx control register consists of eight control bits for the
UARTx function. This register can enable the CTS, RTS and
UART address mode.
If the Transmit Enable Bit (TEN) is set to “0” (disabled) while a
data is being transmitted, the transmitting operation will stop after
the data has been transmitted. If the Receive Enable Bit (REN) is
set to “0” (diabled) while a data is being received, the receiving
operation will stop after the data has been received.
When setting the Transmit Initialization Bit (TIN) to “1”, the TEN bit
is set to “0” and the UARTx status register will be set to “0316” after the data has been transmitted. To retransmit, set the TEN to “1”
and set a data to the transmit buffer register again. The TIN bit will
be cleared to “0” one cycle later after the TIN bit has been set to
“1”.
Setting the Receive Initialization Bit (RIN) to “1” sets all of the
REN, RBF and the receive error flags (PER, FER, OER, SER) to
“0”. The RIN bit will be cleared to “0” one cycle later after the RIN
bit has been set to “1”.
When CTS or RTS function is disabled, pins CTS 1 and CTS2 or
RTS1 and RTS2 can be used as ordinary I/O ports, correspondingly.
[UARTx Transmit/Receive Buffer Registers 1, 2 (UxTRB1/
UxTRB2)] 003416, 003516, 003C16, 003D16
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of received data is invalid. If a
character bit length is 7 or 8 bits, the received contents of UxTRB2
are also invalid. If a character bit length is 9 bits, the received
high-order 7 bits of UxTRB2 are “0”.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 36 of 135
[UARTx (x = 1, 2) RTS Control Register (UxRTS)] 0036 16 ,
003E16
The delay time from the reception of the last stop bit to the assertion of RTSx is selectable using the RTS Assertion Delay Count
Select Bits. If the stop bit is detected before RTS assertion delay
time has expired, the RTSx pin is kept “H”. The RTS assertion delay count starts after the last data reception is completed.
Setting the RIN bit to “1” resets the UxRTS. After setting the RIN
bit to “1”, set this UxRTS.
7641 Group
b7
b0
b7
b0
UARTx mode register (addresses 003016, 003816)
UxMOD
UARTx control register (addresses 003316, 003B16)
UxCON
UART clock select bit (CLK)
Transmit enable bit (TEN)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (REN)
0: Receive disabled
1: Receive enabled
Transmit initialization bit (TIN)
0: No action.
1: Initializing
Receive initialization bit (RIN)
0: No action.
1: Initializing
Transmit interrupt source select bit (TIS)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
CTS function enable bit (CTS_SEL)
0: CTS function disabled
1: CTS function enabled
RTS function enable bit (RTS_SEL)
0: RTS function disabled
1: RTS function enabled
UART address mode enable bit (AME)
0: Address mode disabled
1: Address mode enabled
0: φ
1: SCSGCLK
UART clock prescaling select bits (PS)
b2b1
0 0: UART clock divided by 1
0 1: UART clock divided by 8
1 0: UART clock divided by 32
1 1: UART clock divided by 256
Stop bit length select bit (STB)
0: 1 stop bit
1: 2 stop bits
Parity select bit (PMD)
0: Even parity
1: Odd parity
Parity enable bit (PEN)
0: Parity checking disabled
1: Parity checking enabled
UART character length select bit
b7b6
0 0: 7 bits
0 1: 8 bits
1 0: 9 bits
1 1: Not available
b7
b0
b7
UARTx status register (addresses 003216, 003A16)
UxSTS
Transmit complete flag (TCM)
0: Transmit shift in progress
1: Transmit shift completed
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Parity error flag (PER)
0: No error
1: Parity error
Framing error flag (FER)
0: No error
1: Framing error
Overrun error flag (OER)
0: No error
1: Overrun error
Summing error flag (SER)
0: (FER) U (OER) U (SER) = 0
1: (FER) U (OER) U (SER) = 1
Reserved bits (“0” at read/write)
Fig. 30 Structure of UART related registers
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 37 of 135
b0
0 0 0 0 UARTx RTS control register (addresses 003616, 003E16)
UxRTSC
Reserved bits (“0” at read/write)
RTS assertion delay count select bits
b7 b6 b5 b4
0 0 0 0 : No delay; Assertion immediately
0 0 0 1 : 8-bit term assertion at “H”
0 0 1 0 : 16-bit term assertion at “H”
0 0 1 1 : 24-bit term assertion at “H”
0 1 0 0 : 32-bit term assertion at “H”
0 1 0 1 : 40-bit term assertion at “H”
0 1 1 0 : 48-bit term assertion at “H”
0 1 1 1 : 56-bit term assertion at “H”
1 0 0 0 : 64-bit term assertion at “H”
1 0 0 1 : 72-bit term assertion at “H”
1 0 1 0 : 80-bit term assertion at “H”
1 0 1 1 : 88-bit term assertion at “H”
1 1 0 0 : 96-bit term assertion at “H”
1 1 0 1 : 104-bit term assertion at “H”
1 1 1 0 : 112-bit term assertion at “H”
1 1 1 1 : 120-bit term assertion at “H”
7641 Group
DMAC
The 7641 group is equipped with 2 channels of DMAC (direct
memory access controller) which enable high speed data transfer
from a memory to a memory without use of the CPU.
The DMAC initiates the data transfer with an interrupt factor specified by the DMAC channel x (x = 0, 1) hardware transfer request
source bit (DxHR), or with a software trigger.
The DxTMS [DMA Channel x (x = 0, 1) Transfer Mode Selection
Bit] selects one of two transfer modes; cycle steal mode or burst
transfer mode. In the cycle steal mode, the DMAC transfers one
byte of data for each request. In the burst transfer mode, the
DMAC transfers the number of bytes data specified by the transfer
count register for each request. The count register is a 16-bit
counter; the maximum number of data is 65,536 bytes per one request.
Figure 31 shows the DMA control block diagram and Figure 32
shows the structure of DMAC related registers.
Interrupt:
UART1 receive, UART1 transmit,
Serial I/O, INT0, Timer Y, CNTR1
Signal:
OBE0, IBF0 (data),
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP (endpoint) 3 receive/transmit
EP1OUT FIFO data existing
[DMAC Index and Status Register] DMAIS
The DMAC Index and Status Register consists of various control
bits for the DMAC and its status flags.
The DMA Channel Index Bit (DCI) selects which channel ( 0 or 1)
will be accessed, since the mode registers, source registers, destination registers and transfer count register of both DMAC
channels share the same SFR addresses, respectively.
[DMAC Channel x (x = 0, 1) Mode Registers 1, 2] DMAxM1,
DMAxM2
The 16 bits of DMAC Channel x Mode Registers 1 and 2 control
each operation of DMAC channels 0 and 1.
When the DMAC Channel x (x = 0, 1) Write Bit (DxDWC) is “0”,
data is simultaneously written into each latch and register of the
Source Registers, Destination Register, and Transfer Count Registers. When this bit is “1”, data is written only into their latches.
When data is read from each register, it must be read from the
higher bytes first, then the lower bytes. When writing data, write to
the lower bytes first, then the higher bytes.
DMAC channel X
Case of DMAC
channel 0
Address bus
Channel X timing
generator
Interrupt:
UART2 receive, UART2 transmit,
INT1, Timer 1, Timer X, CNTR0
Signal:
OBE1, IBF1 (data),
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP (endpoint) 4 receive/transmit
EP1OUT FIFO data existing
Case of DMAC
channel 1
DxTMS
DTSC
DxUF
DxCEN
DxCRR
DxUMIE
DxSWT
DxHRS3
DxHRS2
DxHRS1
DxHRS0
DxDAUE
Mode 1
register
Mode 2
register
Channel X transfer
source register
DxSRCE
DxSRID
DxRLD
DRLDD
DxDWC
Channel X transfer
source latch
15
0
Channel X transfer
destination register
Data bus
Temporary register
Index status register
Data bus
Fig. 31 DMACx (x = 0, 1) block diagram
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 38 of 135
Interrupt
generator
DxDWC
Channel X transfer
destination latch
15
0
Interrupt disable flag (I flag)
DxUF
DxSFI
Channel X transfer count register
DxDRCE
DxDRID
DxRLD
DRLDD
DxDWC
Channel X transfer count latch
15
0
DMACx
interrupt request
7641 Group
b7
b0
b7
b0
DMAC index and status register (address 003F16)
DMAIS
DMAC channel x mode register 1 (address 004016)
DMAxM1
DMAC channel x source register increment/decrement
selection bit (DxSRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x source register increment/decrement enable
bit (DxSRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x destination register increment/decrement
selection bit (DxDRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x destination register increment/decrement
enable bit (DxDRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x data write control bit (DxDWC)
0: Writing data in reload latches and registers
1: Writing data in reload latches only
DMAC channel x disable after count register underflow
enable bit (DxDAUE)
0: Channel x enabled after count register underflow
1: Channel x disabled after count register underflow
DMAC channel x register reload bit (DxRLD)
0: Not reloaded (Bit is always read as “0”)
1: Source, destination, and transfer count registers contents
of channel x to be reloaded
DMAC channel x transfer mode selection bit (DxTMS)
0: Cycle steal transfer mode
1: Burst transfer mode
DMAC channel 0 count register underflow flag (D0UF)
0: No underflow
1: Underflow generated
DMAC channel 0 suspend flag (D0SFI)
0: Not suspended
1: Suspended
DMAC channel 1 count register underflow flag (D1UF)
0: No underflow
1: Underflow generated
DMAC channel 1 suspend flag (D1SFI)
0: Not suspended
1: Suspended
DMAC transfer suspend control bit (DTSC)
0: Suspending only burst transfers during interrupt
process
1: Suspending both burst and cycle steal transfers
during interrupt process
DMAC register reload disable bit (DRLDD)
0: Enabling reload of source and destination registers
of both channels
1: Disabling reload of source and destination registers
of both channels
Reserved bit (“0” at read/write)
Channel index bit (DCI)
0: Channel 0 accessible
1: Channel 1 accessible
b7
b0
b7
b0
DMAC channel 0 mode register 2 (address 004116)
DMA0M2
DMAC channel 1 mode register 2 (address 004116)
DMA1M2
DMAC channel 0 hardware transfer request source bits
(D0HR)
DMAC channel 1 hardware transfer request source bits
(D1HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART1 receive interrupt
0 0 1 0: UART1 transmit interrupt
0 0 1 1: Timer Y interrupt
0 1 0 0: INT0 interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: USB endpoint 3 IN_PKT_RDY signal
(falling edge active)
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: USB endpoint 3 OUT_PKT_RDY signal
(rising edge active)
1 1 0 0: Master CPU bus interface OBE0 signal
(rising edge active)
1 1 0 1: Master CPU bus interface IBF0 signal, data
(rising edge active)
1 1 1 0: Serial I/O trasmit/receive interrupt
1 1 1 1: CNTR1 interrupt
DMAC channel 0 software transfer trigger (D0SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (Note 1)
DMAC channel 0 USB and master CPU bus interface enable
bit (D0UMIE)
0: Disabled
1: Enabled
DMAC channel 0 transfer initiation source capture register
reset bit (D0CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 0 capture register by writing “1” (Note 1)
DMAC channel 0 enable bit (D0CEN)
0: Channel 0 disabled
1: Channel 0 enabled (Note 2)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART2 receive interrupt
0 0 1 0: UART2 transmit interrupt
0 0 1 1: Timer X interrupt
0 1 0 0: INT1 interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: USB endpoint 4 IN_PKT_RDY signal
(falling edge active)
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: USB endpoint 4 OUT_PKT_RDY signal
(rising edge active)
1 1 0 0: Master CPU bus interface OBE1 signal
(rising edge active)
1 1 0 1: Master CPU bus interface IBF1 signal, data
(rising edge active)
1 1 1 0: Timer 1 trasmit/receive interrupt
1 1 1 1: CNTR0 interrupt
DMAC channel 1 software transfer trigger (D1SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (Note 1)
DMAC channel 1 USB and master CPU bus interface enable
bit (D1UMIE)
0: Disabled
1: Enabled
DMAC channel 1 transfer initiation source capture register
reset bit (D1CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 1 capture register by writing “1” (Note 1)
DMAC channel 1 enable bit (D1CEN)
0: Channel 0 disabled
1: Channel 0 enabled (Note 2)
Notes 1: This bit is automatically cleared to “0” after writing “1”.
2: When setting this bit to “1”, simultaneously set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of DMAxM2) to “1”.
Fig. 32 Structure of DMACx related register
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page 39 of 135
7641 Group
(1) Cycle Steal Transfer Mode
When the DMAC Channel x (x = 0, 1) Transfer Mode Selection Bit
(DxTMS) is set to “0”, the respective DMAC Channel x operates in
the cycle steal transfer mode.
When a request of the specified transfer factor is generated, the
selected channel transfers one byte of data from the address indicated by the Source Register into the address indicated by the
Destination Register.
There are two kinds of DMA transfer triggers supported: hardware
transfer factor and software trigger. Hardware transfer factors can
be selected by the DMACx (x = 0, 1) Hardware Transfer Request
Factor Bit (DxHR). To only use the Interrupt Request Bit, the interrupt can be disabled by setting its Interrupt Enable Bit of Interrupt
Control Register to “0”.
The DMA transfer request as a software trigger can be generated
by setting the DMA Channel x (x = 0, 1) Software Transfer Trigger
Bit (DxSWT) to “1”.
The Source Registers and Transfer Destination Registers can be
either decreased or increased by 1 after transfer completion by
setting bits 0 to 3 in the DMAC Channel x (x = 0, 1) Mode Register. When the Transfer Count Register underflows, the Source
Registers and Destination Registers are reloaded from their
latches if the DMAC Register Reload Disable Bit (DRLDD) is “0”.
The Transfer Count Register value is reloaded after an underflow
regardless of DRLDD setting. At the same time, the DMAC Interrupt Request Bit and the DMA Channel x (x = 0, 1) Count Register
Underflow Flag are set to “1”.
The DMAC Channel x Disable After Count Register Underflow Enable Bit (DxDAUE) is “1”, the DMAC Channel x Enable Bit
(DxCEN) goes to “0” at an under flows of Transfer Count Register.
By setting the DMAC Channel x (x = 0, 1) Register Reload Bit
(DxRLD) to “1”, the Source Registers, Destination Registers, and
Transfer Count Registers can be updated to the values in their respective latches.
When one signal among USB endpoint signals is selected as the
hardware transfer request factor, and DMAC Channel x (x = 0, 1)
USB and Master CPU Bus Interface Enable Bit (DxUMIE) is “1”;
transfer between the USB FIFO and the master CPU bus interface
input/output buffer can be performed effectively. This transfer
function is only valid in the cycle steal mode. To validate this function, the DMAC Channel x (x = 0, 1) USB and the Master CPU Bus
Interface Enable Bit (bit 5 of DxTR) must be set to “1”. The following shows an example of a transfer using this function.
Packet Transfer from USB FIFO to Master
CPU Bus Interface Buffer
When the USB OUT_PKT_RDY is selected as the hardware transfer request factor; if the USB OUT_PKT_RDY is “1” and the
master CPU bus interface output buffer is empty, the transfer request is generated and the transfer is initiated. The
OUT_PKT_RDY retains “1” and a transfer request is generated
each time the output buffer empties until all the data in the corresponding endpoint FIFO has been transferred.
The transfer ends when the last byte in the USB receive packet is
transferred and the OUT_PKT_RDY flag goes to “0” (in the case
of AUTO_CLR bit = “1”).
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Byte Transfer from USB FIFO to Master CPU
Bus Interface Buffer
When the USB Endpoint 1 OUT_FIFO_NOT_EMPTY is selected
as a hardware transfer request factor, if there is data in the USB
Endpoint 1 FIFO and the master CPU bus interface output buffer
is empty; a transfer request is generated and the transfer is initiated. The transfer is performed by unit of one byte.
Transfer from Master CPU Bus Interface
Buffer to USB FIFO
When the USB Endpoint X (X = 1 to 4) IN_PKT_RDY
(IN_PKT_RDY = “0”) is selected as a hardware transfer request
factor, if there is data in the master CPU bus interface output
buffer and the data in the USB FIFO is within the specified packet
size, a transfer request is generated.
The DMA transfer is terminated when a command (A0 = “1”) is input to the master CPU bus interface input buffer.
The timing chart for a cycle steal transfer caused by a hardwarerelated transfer request and a software trigger are shown in Figure
33 and 34, respectively.
7641 Group
φ OUT
SYNCOUT
RD
WR
LDA $zz
Address
PC
Data
DMAOUT
(Port P33)
Transfer request
source (“L” active)
Transfer request source
sampling
Reset of transfer request
source sampling
PC + 1
A5
STA $zz
ADL1, 00
ADL1
DMA transfer
DMA
source add.
PC + 2
Data
DMA destination add.
DMA
data
85
Next instruction
STA $zz (last 2 cycles)
PC + 3
DMA
data
ADL2, 00
ADL2
PC + 4
Data
Op code 3
Fig. 33 Timing chart for cycle steal transfer caused by hardware-related transfer request
φ OUT
SYNCOUT
RD
WR
1 cycle
1 cycle
1 cycle
instruction instruction instruction
LDM #$90, $41
Address
Data
DMAOUT
(Port P33)
Transfer request
source (“L” active)
Transfer request source
sampling
Reset of transfer request
source sampling
PC
PC + 1
3C
18
PC + 2
42, 00
41
PC + 3
90
PC + 4
Op code 2
PC + 5
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DMA
source add.
Op code 3 Op code 4
Fig. 34 Timing chart for cycle steal transfer caused by software trigger transfer request
Next instruction
DMA transfer
DMA destination add.
DMA
data
PC + 6
DMA
data
Op code 6
7641 Group
(2) Burst Transfer Mode
When an interrupt request occurs during any DMA operation, the
transfer operation is suspended and the interrupt process routine
is initiated. During the interrupt operation, the DMAC automatically
sets the corresponding DMAC Channel x (x = 0, 1) Suspend Flag
(DxSFI) to “1”. As soon as the CPU completes the interrupt operation, the DMAC clears the flag to “0” and resumes the original
operation from the point where it was suspended.
The suspended transfer due to the interrupt can also be resumed
during its interrupt process routine by writing “1” to the DMAC
Channel x (x = 0,1) Enable Bit (DxCEN).
When the DMAC Channel x Transfer Mode Selection Bit (DxTMS)
is set to “1”, the respective DMAC channel operates in the burst
transfer mode.
In the burst transfer mode, the DMAC continually transfers the
number of bytes of data specified by the Transfer Count Register
for one transfer request. Other than this, the burst transfer mode
operation is the same as the cycle steal mode operation.
Priority
The DMAC places a higher priority on Channel-0 transfer requests
than on Channel-1 transfer requests.
If a Channel-0 transfer request occurs during a Channel-1 burst
transfer operation, the DMAC completes the next transfer source
and destination read/write operation first, and then starts the
Channel-0 transfer operation. As soon as the Channel-0 transfer is
completed, the DMAC resumes the Channel-1 transfer operation.
The timing charts for a burst transfer caused by a hardware-related transfer request are shown in Figure 35.
φ OUT
SYNCOUT
RD
WR
STA $zz
(First cycle)
LDA $zz
Address
Data
DMAOUT
(Port P33)
Transfer request
source (“L” active)
Transfer request source
sampling
Reset of transfer request
source sampling
PC
PC + 1
A5
ADL1, 00
ADL1
DMA source
add. 1
PC + 2
Data
85
DMA destination add. 1
DMA
data 1
Fig. 35 Timing chart for burst transfer caused by hardware-related transfer request
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STA $zz
(Second cycle)
DMA transfer
DMA source
add. 2
DMA
data 1
DMA destination add. 2
DMA
data 2
PC + 3
DMA
data 2
ADL2
7641 Group
USB FUNCTION
The 7641 Group MCU is equipped with a USB Function Control
Unit (USB FCU). This USB FCU allows the MCU to communicate
with a host PC using a minimum amount of the MCU power. This
built-in USB FCU complies with Full-Speed USB2.0 specification
that supports four transfer types: Control Transfer, Isochronous
Transfer, Interrupt Transfer, and Bulk Transfer. This built-in USB
FCU performs the data transfer error detection and transfer retry
operation by hardware. The default transfer mode of the USB FCU
is bulk transfer mode at reset. The user must set the USB FCU for
the required transfer mode by software.
Figure 36 shows the USB FCU (USB Function Control Unit) block
diagram. The USB FCU consists of the SIE (Serial Interface Engine) performing the USB data transfer, GFI (Generic Function
Interface) performing USB protocol handing, SIU (Serial Engine
Interface Unit) performing a received address and endpoint decoding, MCI (Microcontroller Interface) handling the MCU
interface or performing address decoding and synchronization of
control signals, and the USB transceiver.
The USB FCU has five endpoints (Endpoint 0 to Endpoint 4). The
EPINDEX bit selects one of these five endpoints for the USB FCU
to use. Each endpoint has IN (transmit) FIFO and OUT (receive)
FIFO. To use the USB FCU, the USB enable bit (USBC7) must be
set to “1”. There are two USB related interrupts supported for this
MCU: USB Function Interrupt and USB SOF Interrupt.
Serial Engine
Interface Unit
(SIU)
Microcontroller
Interface Unit
(MCI)
Serial Interface
Engine (SIE)
Generic
Function
Interface
(GFI)
FIFOs
Fig. 36 USB FCU (USB Function Control Unit) block
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Transceiver
CPU
USBD+
USBD-
7641 Group
USB Transmission
Endpoint 0 to Endpoint 4 have IN (transmit) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: Mode 0: 512-byte
Mode 1: 1024-byte
Mode 2: 0-byte
Mode 3: 2048-byte
Mode 4: 768-byte
Mode 5: 880-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
Endpoint 3: 16-byte
Endpoint 4: 16-byte
When Endpoint 1 or Endpoint 2 is used for data transmit, the IN
FIFO size can be selected. Endpoint 1 and Endpoint 2 have programmable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes
for Endpoint 2. Each mode can be selected by the USB endpoint
FIFO mode selection register (address 005F16).
When writing data to the USB Endpoint-x FIFO (addresses 006016
to 006416 ) in the SFR area, the internal write pointer for the IN
FIFO is automatically increased by 1. When the AUTO_SET bit is
“1” and if the stored data reaches to the max. packet value set in
USB Endpoint x IN max. packet size register (address 005B16),
the USB FCU sets the IN_PKT_RDY bit to “1”. When the
AUTO_SET bit is “0”, the IN_PKT_RDY bit will not be automatically set to “1”; it must be set to “1” by software. (The AUTO_SET
bit function is not applicable to Endpoint 0.)
The USB FCU transmits the data when it receives the next IN token. The IN_PKT_RDY bit automatically goes to “0” when the data
transfer is complete.
●Isochronous transfer
Endpoints 1 to 4 can be used in isochronous transfer mode. When
using isochronous transfer mode, the ISO/TOGGLE_INIT bit must
be set to “1”. When ISO_UPDATE = “1” and the corresponding
endpoint’s ISO/TOGGLE_INIT bit = “1”, the USB FCU delays the
rise of the IN_PKT_RDY bit until the next SOF signal transmission. In this way, the USB FCU can synchronize a transmit data to
the SOF signal.
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●Interrupt transfer mode
Endpoints 1 to 4 can be used in interrupt transfer mode. During a
regular interrupt transfer, an interrupt transaction is similar to the
bulk transfer. Therefore, there is no special setting required. When
IN-endpoint is used for a rate feedback interrupt transfer, INTPT
bit of the IN_CSR register must be set to “1”. The following steps
show how to configure the IN-endpoint for the rate feedback interrupt transfer.
1. Set a value which is larger than 1/2 of the USB Endpoint-x FIFO
size to the USB Endpoint x IN max. package size register.
2. Set INTPT bit to “1”.
3. Flush the old data in the FIFO.
4. Store transmission data to the IN FIFO and set the
IN_PKT_RDY bit to “1”.
5. Repeat steps 3 and 4.
In a real application, the function-side always has transfer data
when the function sends an endpoint in a rate feedback interrupt.
Accordingly, the USB FCU never returns a NAK against the host
IN token for the rate feedback interrupt. The USB FCU always
transmits data in the FIFO in response to an IN token, regardless
of IN_PKT_RDY. However, this premises that there is always an
ACK response from Host PC after the 7641 Group has transmitted
data to IN token.
When MAXP size ≤ (a half of IN FIFO size), the IN FIFO can store
two packets (called double buffer). At this time, the IN FIFO status can be checked by monitoring the IN_PKT_RDY bit and the
TX_NOT_EPT flag. The TX_NOT_EPT flag is a read-only flag
which shows the FIFO state. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 0, IN FIFO is empty. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 1, IN FIFO has one packet.
In double buffer mode, as long as the IN FIFO is not filled with
double packets, IN_PKT_RDY will not be set to “1”, even if it is set
to “1” by software, but TX_NOT_EPT flag will be set to “1”. In
single buffer mode, if MAXP > (a half of IN FIFO), this condition
never occurs.
When IN_PKT_RDY = “1” and TX_NOT_EPT = “1”, IN FIFO holds
two packets in double buffer mode and one packet in single
packet mode. In single packet mode, when the IN_PKT_RDY bit is
set to “1” by software, the TX_NOT_EPT flag is set to “1” as well.
During double buffer mode, if you want to load two packets sequentially, you must set the IN_PKT_RDY bit to “1” each time a
packet is loaded.
7641 Group
USB Reception
TOGGLE Initialization
Endpoint 0 to Endpoint 4 have OUT (receive) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: Mode 0: 800-byte
Mode 1: 1024-byte
Mode 2: 2048-byte
Mode 3: 0-byte
Mode 4: 1280-byte
Mode 5: 1168-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
Endpoint 3: 16-byte
Endpoint 4: 16-byte
In order to initialize the data toggle sequence bit of the endpoint,
in other words, resetting the next data packet to DATA0; set the
ISO/TOGGLE_INT bit to “1” and then clear back to “0”.
When Endpoint 1 or Endpoint 2 is used for data receive, the OUT
FIFO size can be selected. Endpoint 1 and Endpoint 2 have programmable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes
for Endpoint 2. Each mode can be selected by the USB endpoint
FIFO mode selection register (address 005F16).
Data transmitted from the host-PC is stored in Endpoint x FIFO
(006016 to 006416). Every time the data is stored in the FIFO, the
internal OUT FIFO write pointer is increased by 1. When one complete data packet is stored, the OUT_PKT_RDY flag is set to “1”
and the number of received data packets is stored in USB Endpoint x OUT write count registers (Low and High). When the
AUTO_CLR bit is “1” and the received data is read out from the
OUT FIFO, the OUT_PKT_RDY flag is cleared to “0”. When the
AUTO_CLR bit is “1”, the OUT_PKT_RDY flag will not be cleared
automatically by the FIFO read; it must be cleared by software.
(The AUTO-CLR bit function is not applicable in Endpoint 0.)
When MAXP size ≤ (a half of OUT FIFO size), the OUT_FIFO can
receive 2 packets (double buffer). At this time, the OUT_ FIFO status can be checked by the OUT_PKT_RDY flag. When the FIFO
holds two packets and one packet is read from the FIFO, the
OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag
returns from “0” to “1” in one φ cycle after the read-out). During
double buffer mode, the USB Endpoint x OUT write count registers (Low and High) holds the number of previously received
packets. This count register is updated after reading out one of
packets in the OUT FIFO and clearing the OUT_PKT_RDY flag to
“0”.
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7641 Group
USB Interrupts
Suspend/Resume Functions
The USB FCU has two interrupts, USB Function Interrupt and
USB SOF (Start Of Frame) Interrupt.
If no bus activity is detected on the D+/D- line for at least 3 ms, the
USB suspend signal detect flag (SUSPEND) of the USB power
control register (address 005116) and the USB suspend signal interrupt status flag of USB interrupt status register 2 are set to “1”
and the suspend interrupt request occurs. The following procedure
must be executed after pushing the internal registers (A, X, Y ) to
memories during the suspend interrupt process routine.
●USB Function Interrupt (USBF-INT)
The USBF-INT is usable for the USB data flow control and power
management. The USBF-INT request occurs at data transmit/receive completion, overrun/underrun, reset, or receiving suspend/
resume signal. To enable this interrupt, the USB function interrupt
enable bit in the interrupt control register A (address 000516) and
the respective bit in the USB interrupt enable registers 1 and 2
(addresses 0005416 and 0005516) must be set to “1”. When setting bit 7 in USB interrupt enable register 2 to “1”, the suspend
interrupt and the resume interrupt are enabled.
Endpoint x (x = 0 to 4) IN interrupt request occurs when the USB
Endpoint x IN interrupt status flag (INTST 0, 2, 4, 6, 8) of USB interrupt status registers 1 and 2 (addresses 005216 and 005316) is
“1”. The USB Endpoint x IN interrupt status flag is set to “1” when
the respective endpoint IN_PKT_RDY bit is “1”.
Endpoint x (x = 0 to 4) OUT interrupt request occurs when the
USB endpoint x OUT interrupt status flag (INTST3, 5, 7, 9) in USB
interrupt status registers 1 and 2 is set to “1”. The USB Endpoint x
OUT interrupt status flag is set to “1” when the respective endpoint
OUT_PKT_RDY flag is “1”.
The overrun/underrun interrupt request occurs when the USB
overrun/underrun interrupt status flag (INTST12) in USB interrupt
status register 2 is set to “1”. This flag is set to “1” when the FIFO
data overruns or underruns in isochronous transfer mode.
The USB reset interrupt request occurs when the USB reset interrupt status flag (INTST13) in USB interrupt status register 2 is set
to “1”. This flag is set when the SE0 is detected on the D+/D- line
for at least 2.5 µs. When this situation happens, all USB internal
registers (addresses 005016 to 005F16), except this flag, are initialized to the default state at reset. The USB reset interrupt is
always enabled.
The suspend/resume interrupt request occurs when either the
USB resume signal interrupt status flag (INTST14) or the USB
suspend signal interrupt status flag (INTST15) in USB interrupt
status register 2 is set to “1”.
The bits in both interrupt status registers 1 and 2 can be cleared
by writing “1” to each bit.
●USB SOF interrupt
The USB SOF interrupt is usable in isochronous transfers. This interrupt request occurs when an SOF packet is received. To enable
a USB SOF interrupt, set the USB SOF interrupt enable bit of interrupt control register A to “1”.
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(1) Clear all bits of USB interrupt status register 1 (address
005216) and USB interrupt status register 2 (address 005316)
to “0”.
(2) Set the USB clock enable bit to “0”. (After disabling the USB
clock, do not write to any of the USB internal registers (addresses 005016 to 006416), except for the USB control register
(address 001316), clock control register (address 001F16), and
frequency synthesizer control register (address 006C16).
(3) Set the frequency synthesizer enable bit to “0”.
(4) Set the USB line driver current control bit to “1”. (Always keep
the USB line driver current control bit set to “0” during USB
function operations. When operating at Vcc = 3.3 V, this bit
does not need to be set.)
(5) Keep total drive current at 500 µA or less.
(6) Disable the timer 1 interrupt.
(7) Disable the timer 2 interrupt. (Disable all the other external interrupts.)
(8) Set the timer 1 interrupt request bit to “0”.
(9) Set the timer 2 interrupt request bit to “0”.
(10) Set the interrupt disable flag (I) to “0”.
(11) Execute the STP instruction.
At this point, the MCU will be in stop mode (suspend mode). Before executing the STP instruction, make sure to set the USB
function interrupt request bit (bit 0 at address 000216) to “0” and
the USB function interrupt enable bit (bit 0 at address 000516) to
“1”.
7641 Group
The USB suspend detect signal flag goes to “0” when the USB resume signal detect flag (RESUME) is set to “1”. During suspend
mode, if the clock operation is started up with a process (remote
wake-up) other than the resume interrupt process (for example;
reset or timer), make sure to clear the USB suspend detect signal
flag to “0” when you set the USB remote wake-up bit to “1”. When
the USB FCU is in suspend mode and detects a non-idle signal on
the D+/D- line, the USB resume detect flag and the USB resume
signal interrupt status flag both go to “1” and a resume interrupt
request occurs. At this point, pull the internal registers (A, X, Y) in
this interrupt process routine. Take the following procedure in the
USB resume interrupt process.
(1) Set the USB line driver current control bit to “0”. (When operating at Vcc = 3.3 V, this bit does not need to be set.)
(2) Set the frequency synthesizer enable bit to “1” and set a 2 ms
to 5 ms wait.
(3) Check the frequency synthesizer lock status bit. If “0”, it must
be checked again after a 0.1 ms wait.
(4) Enable the USB clock.
b7
Set the USB resume signal interrupt status flag to “0” after the
wake-up sequence process. The USB resume detect flag goes to
“0” at the same time. When the clock operation is started up with
a remote wake-up, set the USB remote wake-up bit to “1” after the
wake-up sequence process. (keep it set to “1” for a minimum of 10
ms and maximum of 15 ms). By doing this, the MCU will send a
resume signal to the host CPU and let it know that the suspend
state has been released.
After that, set the USB remote wake-up bit and the USB suspend
detection flag to “0”, because the USB suspend detection flag is
not automatically cleared to “0” with a remote wake-up.
[USB Control Register] USBC
When using the USB function, the USB enable bit must be set to
“1”. The USB line driver supply bit must be set to “0” (DC-DC converter is disabled) when operating at Vcc = 3.3V. In this condition,
the setting of the USB line driver current control bit has no effect
on USB operations.
When the USB artificial SOF enable bit is set to “1”, the MCU
judges that a SOF packet is received within 250 ns from a frame
starting if an SOF packet is destroyed owing to some cause.
b0
0 USB control register (address 001316)
USBC
Reserved bit (“0” at read/write)
USB default state selection bit (USBC1)
0: In default state after power-on/reset
1: In default state after USB reset signal received
USB artificial SOF enable bit (USBC2)
0: Artificial SOF disabled
1: Artificial SOF enabled
USB line driver current control bit (USBC3)
0: High current mode
1: Low current mode
USB line driver supply enable bit (USBC4) (Note 1)
0: Line driver disabled
1: Line driver enabled
USB clock enable bit (USBC5)
0: 48 MHz clock to the USB block disabled
1: 48 MHz clock to the USB block enabled
USB SOF port select bit (USBC6)
0: SOF output disabled
1: SOF output enabled
USB enable bit (USBC7)
0: USB block disabled (Note 2)
1: USB block enabled
Notes 1: When using the MCU in Vcc = 3.3 V, set this bit to “0” and disable the built-in DC-DC converter
2: Setting this bit to 0” causes the contents of all USB registers to have the values at reset.
Fig. 37 Structure of USB control register
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7641 Group
[USB Address Register] USBA
The USB address register maintains the USB function control unit
address assigned by the host computer. When receiving the
SET_ADDRESS, keep it in this register. The values of this register
are “0” when the device is not yet configured. The values of this
register are also set to “0” when the USB block is disabled (bit 7 of
USB control register is set to “0”). In addition, no matter what
value is written to this register, it will have no effect on the set
value.
b7
b0
USB address register (address 005016)
USBA
0
Programmable function address (FUNAD0 to 6))
This register maintains the 7-bit USB function control unit address
assigned by the host CPU.
Reserved bit (“0” at read/write)
Fig. 38 Structure of USB address register
[USB Power Management Register] USBPM
The USB power management register is used for power management in the USB FCU. This register needs to be set only when
using the remote wake-up to resume the MCU from suspend
mode.
b7
b0
0 0 0 0 0
USB power management register (address 005116)
USBPM
USB suspend detection flag (SUSPEND) (Read only)
0: No USB suspend detected
1: USB suspend detected
USB resume detection flag (RESUME) (Read only)
0: No USB resume signa detected
1: USB resume signal detected
USB remote wake-up bit (WAKEUP)
0: End of remote resume signal
1: Transmitting of remote resume signal (only when SUSPEND = “1”)
Reserved bit (“0” at read/write)
Fig. 39 Structure of USB power management register
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7641 Group
[USB Interrupt Status Registers 1 and 2] USBIS1, USBIS2
The USB interrupt status registers are used to indicate the condition that caused a USB function interrupt to be generated. Each
status flag and bit can be cleared to “0” by writing “1” to the corresponding bit. Make sure to write to/read from the USB interrupt
status register 1 first and then USB interrupt status register 2.
When an IN token is received during an isochronous transfer, and
b7
the IN FIFO is empty, an underrun error occurs and INTST12 and
IN_CSR2 are set to “1”. When an OUT token is received and the
OUT FIFO is full, an overrun error occurs and INTST12 and
OUT_CSR2 are set to “1”. Underruns and overruns are not detected by the CPU in bulk transfers and normal interrupt transfers,
however in this case, the MCU will send a NAK signal to the host
CPU.
b0
0
USB interrupt status register 1 (address 005216)
USBIS1
USB endpoint 0 interrupt status flag (INTST0)
0: Except the following conditions
1: Set at any one of the following conditions:
• A packet data of endpoint 0 is successfully received
• A packet data of endpoint 0 is successfully sent
• DATA_END bit of endpoint 0 is cleared to “0”
• FORCE_STALL bit of endpoint 0 is set to “1”
• SETUP_END bit of endpoint 0 is set to “1”.
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt status flag (INTST2)
0: Except the following conditions
1: Set at which of the following conditions:
• A packet data of endpoint 1 is successfully sent
• UNDER_RUN bit of endpoint 1 is set to “1”.
USB endpoint 1 OUT interrupt status flag (INTST3)
0: Except the following conditions
1: Set at any one of the following conditions:
• A packet data of endpoint 1 is successfully received
• OVER_RUN bit of endpoint 1 is set to “1”
• FORCE_STALL bit of endpoint 1 is set to “1”.
USB endpoint 2 IN interrupt status flag (INTST4)
0: Except the following conditions
1: Set at which of the following conditions:
• A packet data of endpoint 2 is successfully sent
• UNDER_RUN bit of endpoint 2 is set to “1”.
USB endpoint 2 OUT interrupt status flag (INTST5)
0: Except the following conditions
1: Set at any one of the following conditions:
• A packet data of endpoint 2 is successfully received
• OVER_RUN bit of endpoint 2 is set to “1”
• FORCE_STALL bit of endpoint 2 is set to “1”.
USB endpoint 3 IN interrupt status flag (INTST6)
0: Except the following conditions
1: Set at which of the following conditions:
• A packet data of endpoint 3 is successfully sent
• UNDER_RUN bit of endpoint 3 is set to “1”.
USB endpoint 3 OUT interrupt status flag (INTST7)
0: Except the following conditions
1: Set at any one of the following conditions:
• A packet data of endpoint 3 is successfully received
• OVER_RUN bit of endpoint 3 is set to “1”
• FORCE_STALL bit of endpoint 3 is set to “1”.
Fig. 40 Structure of USB interrupt status register 1
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7641 Group
b7
b0
0 0
USB interrupt status register 2 (address 005316)
USBIS2
USB endpoint 4 IN interrupt status flag (INTST8)
0: Except the following conditions
1: Set at which of the following conditions:
• A packet data of endpoint 4 is successfully sent
• UNDER_RUN bit of endpoint 4 is set to “1”.
USB endpoint 4 OUT interrupt status flag (INTST9)
0: Except the following conditions
1: Set at any one of the following conditions:
• A packet data of endpoint 4 is successfully received
• OVER_RUN bit of endpoint 4 is set to “1”
• FORCE_STALL bit of endpoint 4 is set to “1”.
Reserved bit (“0” at read/write)
USB overrun/underrun interrupt status flag (INTST12)
0: Except the following condition
1: Set at an occurrence of overrun/underrun (for isochronous data transfer)
USB reset interrupt status flag (INTST13)
0: Except the following condition
1: Set at receiving of USB reset signal
USB resume signal interrupt status flag (INTST14)
0: Except the following condition
1: Set at receiving of resume signal
USB suspend signal interrupt status flag (INTST15)
0: Except the following condition
1: Set at receiving of suspend signal
Fig. 41 Structure of USB interrupt status register 2
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7641 Group
[USB Interrupt Enable Registers 1 and 2] USBIE1, USBIE2
The USB interrupt enable registers are used to enable the USB
b7
function interrupt. Upon reset, all USB interrupts except the USB
suspend and USB resume interrupts are enabled.
b0
USB interrupt enable register 1 (address 005416)
USBIE1
0
USB endpoint 0 interrupt enable bit (INTEN0)
0: Disabled
1: Enabled
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt enable bit (INTEN2)
0: Disabled
1: Enabled
USB endpoint 1 OUT interrupt enable bit (INTEN3)
0: Disabled
1: Enabled
USB endpoint 2 IN interrupt enable bit (INTEN4)
0: Disabled
1: Enabled
USB endpoint 2 OUT interrupt enable bit (INTEN5)
0: Disabled
1: Enabled
USB endpoint 3 IN interrupt enable bit (INTEN6)
0: Disabled
1: Enabled
USB endpoint 3 OUT interrupt enable bit (INTEN7)
0: Disabled
1: Enabled
Fig. 42 Structure of USB interrupt enable register 1
b7
b0
0 1
0 0
USB interrupt enable register 2 (address 005516)
USBIE2
USB endpoint 4 IN interrupt enable bit (INTEN8)
0: Disabled
1: Enabled
USB endpoint 4 OUT interrupt enable bit (INTEN9)
0: Disabled
1: Enabled
Reserved bit (“0” at read/write)
USB overrun/underrun interrupt enable bit (INTEN12)
0: Disabled
1: Enabled
Reserved bit (“1” at read/write)
Reserved bit (“0” at read/write)
USB suspend/resume interrupt enable bit (INTEN15)
0: Disabled
1: Enabled
Fig. 43 Structure of USB interrupt enable register 2
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7641 Group
[USB Frame Number Registers Low and High ]
USBSOFL, USBFOFH
These 11-bit registers contain the frame number of the SOF token
received from the host computer. These are read-only registers.
b7
[USB Endpoint Index Register] USBINDEX
This register specifies the accessible endpoint. It serves as an index to endpoint-specific USB Endpoint x IN Control Register, USB
Endpoint x OUT Control Register, USB Endpoint x IN Max. Packet
Size Register, USB Endpoint x OUT Max. Packet Size Register,
USB Endpoint x OUT Write Count Register, and USB FIFO Mode
Selection Register (x = 0 to 4).
b0
USB frame number register Low (address 005616)
USBSOFL
Low-order 8 bits of SOF token
b7
b0
USB frame number register High (address 005716)
USBSOFH
High-order 3 bits of SOF token
Reserved bit (“0” at read)
Fig. 44 Structure of USB frame number registers
b7
b0
0 0 0
USB endpoint index register (address 005816)
USBINDEX
Endpoint index bit (EPINDEX)
b2b1b0
0 0 0: Endpoint 0
0 0 1: Endpoint 1
0 1 0: Endpoint 2
0 1 1: Endpoint 3
1 0 0: Endpoint 4
1 0 1: Not used
1 1 0: Not used
1 1 1: Not used
Reserved bit (“0” at read/write)
AUTO_FLUSH bit (AUTO_FL)
0: Auto FIFO flush disabled
1: Auto FIFO flush enabled
ISO_UPDATE bit (ISO_UPD)
0: ISO_UPDATE disabled
1: ISO_UPDATE enabled
Fig. 45 Structure of USB frame number registers
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7641 Group
[USB Endpoint 0 IN Control Register ] IN_CSR
This register contains the control and status information of the
endpoint 0. This USB FCU sets the OUT_PKT_RDY flag to “1”
upon having received a data packet in the OUT FIFO. When reading its one data packet from the OUT FIFO, be sure to set this flag
to “0”.
After a SETUP token is received, the MCU is in the “decode wait
state” until the OUT_PKT_RDY flag is cleared. If the
OUT_PKT_RDY flag is not cleared (indicating that the host request has not been successfully decoded), the USB FCU keep
returning a NAK to the host for all IN/OUT tokens.
Set the IN_PKT_RDY bit to “1” after the data packet has been
written to the IN FIFO. If this bit is set to “1” even though nothing
has been written to the IN FIFO, a “0” length data (NULL packet)
is sent to the host. The SEND_STALL bit is for sending a STALL to
the host if an unsupported request is received by the USB FCU.
This bit must be set to “1”. When the OUT_PKT_RDY flag is set to
“0” for request reception, the USB FCU transmits a STALL signal
b7
to the Host CPU. Perform the following three processes simultaneously:
• Set SEND_STALL bit to “1”
• Set DATA_END bit to “1”
• Set OUT_PKT_RDY flag to “0” by setting SERVICED_OUT
_PKT_RDY bit to “1”.
Note that if “0” is written to the SEND_STALL bit before the
CLEAR_FEATURE (endpoint STALL) request has been received,
the next STALL will not be generated.
The DATA_END bit informs the USB FCU of the completion of the
process indicated in the SETUP packet. Set this bit to “1” when
the process requested in the SETUP packet is completed. (Control Read Transfer: set this bit after writing all of the requested
data to the FIFO; Control Write Transfer: set this bit to “1” after
reading all of the requested data from the FIFO.) When this bit is
“1”, the host request is ignored and a STALL is returned. After the
status phase process is completed, the USB FCU automatically
clears it to “0”.
b0
USB endpoint 0 IN control register (address 005916)
IN_CSR
OUT_PKT_RDY flag (IN0CSR0)
0: Except the following condition (Cleared to “0” by writing “1” into
SERVICED_OUT_PKT_RDY bit)
1: End of a data packet reception
IN_PKT_RDY bit (IN0CSR1)
0: End of a data packet transmission
1: Write “1” at completion of writing a data packet into IN FIFO.
SEND_STALL bit (IN0CSR2)
0: Except the following condition
1: Transmitting STALL handshake signal
DATA_END bit (IN0CSR3)
0: Except the following condition (Cleared to “0” after completion of
status phase)
1: Write “1” at completion of writing or reading the last data packet
to/from FIFO.
FORCE_STALL flag (IN0CSR4)
0: Except the following condition
1: Protocol error detected
SETUP_END flag (IN0CSR5) (Note )
0: Except the following condition (Cleared to “0” by writing “1” into
SERVICED_SETUP_END bit)
1: Control transfer ends before the specific length of data is
transferred during the data phase.
SERVICED_OUT_PKT_RDY bit (IN0CSR6)
Writing “1” to this bit clears OUT_PKT_RDY flag to “0”.
SERVICED_SETUP_END bit (IN0CSR7)
Writing “1” to this bit clears SETUP_END flag to “0”.
Note: If this bit is set to “0”, stop accessing the FIFO to serve the previous setup transaction.
Fig. 46 Structure of USB endpoint 0 IN control register
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7641 Group
[USB Endpoint x (x = 1 to 4) IN Control Register] IN_CSR
This register contains the control and status information of the respective IN Endpoints 1 to 4.
Set the IN_PKT_RDY bit to “1” after the data packet has been
written to the IN FIFO. This bit is cleared to “0” when the data
transfer is completed. In a bulk IN transfer, this bit is cleared when
an ACK signal is received from the host. If an ACK signal is not received, this bit (and the TX_NOT_EMPTY bit) remains as “1”. This
same data packet is sent after the next IN token is received. The
FLUSH bit is for flushing the data in the IN FIFO.
b7
b0
USB endpoint x IN control register (address 005916)
IN_CSR
INT_PKT_RDY bit (INXCSR0)
0: End of a data packet transmission (Note 1)
1: Write “1” at completion of writing a data packet into IN FIFO.
(Note 3)
UNDER_RUN flag (INXCSR1) (In isochronous data transfer)
0: No FIFO underrun (Note 2)
1: FIFO underrun occurred (Note 1) (USB overrun/underrun interrupt
status flag is set to “0”.)
SEND_STALL bit (INXCSR2) (Note 2)
0: Except the following condition
1: Transmitting STALL handshake signal
ISO/TOGGLE_INIT bit (INXCSR3) (Note 2)
0: Except the following condition
1: Initializing to endpoint used for isochronous transfer;
Initializing the data toggle sequence bit
INTPT bit (INXCSR4) (Note 2)
0: Except the following condition
1: Initializing to endpoint used for interrupt transfer, rate feedback
TX_NOT_EPT flag (INXCSR5) (Note 1)
0: Empty in IN FIFO
1: Full in IN FIFO
FLUSH bit (INXCSR6)
0: Except the following condition (Note 1)
1: Flush FIFO. (Note 2)
AUTO_SET bit (INXCSR7) (Note 2)
0: AUTO_SET disabled
1: AUTO_SET enabled (Note 4)
Notes 1: This bit is automatically set to “1” or cleared to “0”.
2: The user must program to “1” or “0”.
3: When AUTO_SET bit is “0”, the user must set to “1”. When AUTO_SET bit is “1”, this
bit is automatically set to “1”.
4: To use the AUTO_SET function for an IN transfer when the AUTO_SET bit is set to
“1”, set the FIFO to single buffer mode.
Fig. 47 Structure of USB endpoint x (x = 1 to 4) IN control register
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7641 Group
[USB Endpoint x (x = 1 to 4) OUT Control Register] OUT_CSR
This register contains the information and status of the respective
OUT endpoints 1 to 4. In the endpoint 0, all bits are reserved and
cannot be used (they will all be read out as “0”). The USB FCU
sets the OUT_PKT_RDY flag to “1” after a data packet has been
received into the OUT FIFO. After reading the data packet in the
OUT FIFO, clear this flag to “0”. However, if there is still data in the
OUT FIFO, the flag cannot be cleared even by writing “0” by software.
b7
b0
USB endpoint x OUT control register (address 005A16)
OUT_CSR
OUT_PKT_RDY flag (OUTXCSR0)
0: Except the following condition (Note 3)
1: End of a data packet reception (Note 2)
OVER RUN flag (OUTXCSR1) (In isochronous data transfer)
0: No FIFO overrun (Note 2)
1: FIFO overrun occurred (Note 1)
SEND_STALL bit (OUTXCSR2) (Note 2)
0: Except the following condition
1: Transmitting STALL handshake signal
ISO/TOGGLE_INIT bit (OUTXCSR3) (Note 2)
0: Except the following condition
1: Initializing to endpoint used for isochronous transfer;
Enabling reception of DATA0 and DATA1 as PID (Initializing the
toggle)
FORCE_STALL flag (OUTXCSR4)
0: Except the following condition (Note 2)
1: Protocol error detected (Note 1)
DATA_ERR flag (OUTXCSR5)
0: Except the following condition (Note 2)
1: CRC or bit stuffing error detected in transferring isochronous data
(Note 1)
FLUSH bit (OUTXCSR6)
0: Except the following condition (Note 1)
1: Flush FIFO. (Note 2)
AUTO_CLR bit (OUTXCSR7) (Note 2)
0: AUTO_CLR disabled
1: AUTO_CLR enabled
Notes 1: This bit is automatically set to “1” or cleared to “0”.
2: The user must program to “1” or “0”.
3: When AUTO_CLR bit is “0”, the user must clear to “0”. When AUTO_CLR bit is “1”, this
bit is automatically cleared to “0”.
Fig. 48 Structure of USB endpoint x (x = 1 to 4) OUT control register
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7641 Group
[USB Endpoint x (x = 0 to 4) IN Max. Packet Size Register]
IN_MAXP
This register specifies the maximum packet size (MAXP) of an
endpoint x IN packet. The value set for endpoint 1 is the number
of transmitted bytes divided by 8, and the value set for endpoints
0, 2, 3, and 4 is the actual number of transmitted bytes. The CPU
can change these values using the SET_DESCRIPTOR command.
The initial value for endpoints 0, 2, 3 and 4 is 8, and the initial
value for endpoint 1 is 1.
b7
[USB Endpoint x (x = 0 to 4) OUT Max. Packet Size Register]
OUT_MAXP
This register specifies the maximum packet size (MAXP) of an
Endpoint x OUT packet. The value set for endpoint 1 is the number of received bytes divided by 8, and the value set for endpoints
0, 2, 3, and 4 is the actual number of received bytes. The CPU
can change these values using the SET_DESCRIPTOR command.
The initial value for endpoints 0, 2, 3, and 4 is 8, and the initial
value for endpoint 1 is 1. When using the endpoint 0, both USB
endpoint x IN max. packet size register (IN _MAXP) and USB endpoint x OUT max. packet size register (OUT_MAXP) are set to the
same value. Changing one register’s value effectively changes the
value of the other register as well.
b0
USB endpoint x IN max. packet size register (address 005B16)
IN_MAXP
The maximum packet size (MAXP) of endpoint x IN is contained.
MAXP = n for endpoints 0, 2, 3, 4
MAXP = n ✕ 8 for endpoint 1
“n” is a written value into this register.
Fig. 49 Structure of USB endpoint x IN max. packet size register
b7
b0
USB endpoint x OUT max. packet size register (address 005C16)
OUT_MAXP
The maximum packet size (MAXP) of endpoint x OUT is contained.
MAXP = n for endpoints 0, 2, 3, 4
MAXP = n ✕ 8 for endpoint 1
“n” is a written value into this register.
Fig. 50 Structure of USB endpoint x OUT max. packet size register
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7641 Group
[USB endpoint x (x = 0 to 4) OUT Write Count Registers (Low
and High)] WRT_CNTRL, WRT_CNTH
These registers contain the number of bytes in the endpoint x
OUT FIFO. These are read-only registers. These two registers
must be read after the USB FCU has received a packet of data
b7
from the host. When reading these registers, the lower byte must
be read first, then the higher byte.
When the OUT FIF0 is in double buffer mode, the CPU first reads
the received number of bytes of the former data packet. The next
CPU read can obtain that of the new data packet.
b0
USB endpoint x OUT write count register Low (address 005D16)
WRT_CNTL
Low-order 8 bits of the number of bytes in endpoint x OUT FIFO
b7
b0
USB endpoint x OUT write count register High (address 005E16)
WRT_CNTH
High-order 2 bits of the number of bytes in endpoint x OUT FIFO
Not used (“0” at read)
Fig. 51 Structure of USB endpoint x (x = 0 to 4) OUT write count registers
[USB Endpoint x (x = 0 to 4) FIFO Register] USBFIFOx
These registers are the USB IN (transmit) and OUT (receive) FIFO
data registers. Write data to the corresponding register, and read
data from the corresponding register.
When the maximum packet size is equal to or less than half the
FIFO size, these registers function in double buffer mode and can
hold two packets of data. When the IN_PKT_RDY bit is “0” and
b7
the TX_NOT_EMPTY bit is “1”, these bits indicate that one packet
of data is stored in the IN FIFO. When the OUT FIFO is in double
buffer mode, the OUT_PKT_RDY flag remains as “1” after the first
packet of data is read out (it actually goes to “0” and returns to “1”
after one φ cycle).
b0
USB endpoint x FIFO register
(addresses 006016, 006116, 006216, 006316, 006416,)
USBFIFOx
Endpoint x IN/OUT FIFO
Fig. 52 Structure of USB endpoint x (x = 0 to 4) FIFO register
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7641 Group
[USB Endpoint FIFO Mode Selection Register] USBFIFOMR
This register determines IN/OUT FIFO size mode for endpoint 1 or
endpoint 2. This register is invalid when using endpoint 0, 3, or 4.
b7
b0
USB endpoint FIFO mode register (address 005F16)
USBFIFOMR
0 0 0 0
FIFO size selection bit (Note)
For endpoint 1
b3b2b1b0
0 0 0: IN 512-byte, OUT 800-byte
0 0 1: IN 1024-byte, OUT 1024-byte
X 0 1 0: IN 0-byte, OUT 2048-byte
X 0 1 1: IN 2048-byte, OUT 0-byte
X 1 0 0: IN 768-byte, OUT 1280-byte
X 1 0 1: IN 880-byte, OUT 1168-byte
X
X
For endpoint 2
0 X X X : IN 32-byte, OUT 32-byte
1 X X X : IN 128-byte, OUT 128-byte
Reserved bit (“0” at read/write)
Note: The value set into “x” is invalid.
Fig. 53 Structure of USB endpoint FIFO mode register
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7641 Group
MASTER CPU BUS INTERFACE
The 7641 group internally has a 2-byte bus interface which control
signals from the host CPU side can operate (slave mode).
This bus interface allows the 7641 group to be directly connected
with a R/W type of CPU bus or a RD and WR separated type of
CPU bus. Figure 56 shows the block diagram of master CPU bus
interface function.
The data bus buffer function I/O pins (P52 – P57 , P6, P72–P74 )
also function as the normal I/O ports. When the Master CPU Bus
Interface Enable bit of Data Bus Buffer Control Register (bit 6 of
address 004A16) is “0”, these pins become the normal I/O ports.
When it is “1”, these pins become the master CPU bus interface
function pins.
Additionally, when using the master CPU bus interface function,
set port P6 to input mode by setting “0016” into its port direction
register (address 001516).
The selection of either the single data bus buffer mode, which
uses 1 byte: data bus buffer 0 only, or the double data bus buffer
mode, which uses 2 bytes: data bus buffer 0 and data bus buffer
1, is performed by the Data Bus Buffer Function Select Bit of Data
Bus Buffer Control Register 1 (bit 7 of address 004E16). Port P72
becomes S1 input pin in the double data bus buffer mode.
When data is written from the host CPU side, an input buffer full
interrupt occurs. When data is read from the host CPU, an output
buffer empty interrupt occurs. The 7641 group shares two input
buffer full interrupt requests and two output buffer empty interrupt
requests as shown in Figure 54, respectively.
The 7641 group can also operate the master CPU bus interface
connecting with the Built-in DMAC. This could transfer a large
amount of data fast.
An input signal level of data bus buffer function input pins can be
selected between a CMOS level and a TTL level. Set it using the
Master CPU Bus Input Level Select Bit of Port Control Register
(address 001016)
.
Input buffer
full flag 0 IBF0
Rising edge
detection circuit
One-shot pulse
generating circuit
Input buffer
full flag 1 IBF1
Rising edge
detection circuit
One-shot pulse
generating circuit
Output buffer
full flag 0
OBF0
Output buffer
full flag 1
OBF1
OBE0
OBE1
Rising edge
detection circuit
Rising edge
detection circuit
Input buffer full interrupt
request signal IBF
One-shot pulse
generating circuit
One-shot pulse
generating circuit
Output buffer empty interrupt
request signal OBE
IBF0
IBF1
IBF
Interrupt request is set at this rising edge
OBF0
(OBE0)
OBF1
(OBE1)
OBE
Interrupt request is set at this rising edge
Fig. 54 Interrupt request circuit of data bus buffer
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7641 Group
b7
b0
b7
Data bus buffer status register 0 (address 004916)
DBBS0
b0
Data bus buffer control register 0 (address 004A16)
DBBC0
0
Output buffer full flag (OBF0)
0: Buffer empty
1: Buffer full
Input buffer full flag (IBF0)
0: Buffer empty
1: Buffer full
User definable flag (U2)
This flag can be defined by user freely.
A0 flag (A00)
This flag indicates the condition of A0 status when
the IBF0 flag is set.
User definable flag (U4–U7)
This flag can be defined by user freely.
b7
b0
OBF0 output enable bit
0: P52 functions as I/O port.
1: P52 functions as OBF0 output pin.
IBF0 output enable bit
0: P53 functions as I/O port.
1: P53 functions as IBF0 output pin.
IBF0 interrupt select bit
0: Occurrence due to data write (A0 = “0”) or
command write (A0 = “1”)
1: Occurrence due to command write (A0 = “1”)
Output buffer 0 empty interrupt disable bit
0: Enabled
1: Disabled
Input buffer 0 full interrupt disable bit
0: Enabled
1: Disabled
Reserved bit (“0” at read/write)
Master CPU bus interface enable bit
0: P54 to P57, P60 to P67 function as I/O ports.
1: P54 to P57, P60 to P67 function as master CPU
bus interface function pins.
Bus interface type select bit
0: RD, WR separate type bus
1: R/W type bus
b7
Data bus buffer status register 1 (address 004D16)
DBBS1
Output buffer full flag (OBF1)
0: Buffer empty
1: Buffer full
Input buffer full flag (IBF1)
0: Buffer empty
1: Buffer full
User definable flag (U2)
This flag can be defined by user freely.
A0 flag (A01)
This flag indicates the condition of A0 status when
the IBF1 flag is set.
User definable flag (U4–U7)
This flag can be defined by user freely.
Fig. 55 Structure of master CPU bus interface related registers
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b0
0 0
Data bus buffer control register 1 (address 004E16)
DBBC1
OBF1 output enable bit
0: P74 functions as I/O port.
1: P74 functions as OBF1 output pin.
IBF1 output enable bit
0: P73 functions as port I/O pin.
1: P73 functions as IBF1 output pin.
IBF1 interrupt select bit
0: Occurrence due to data write (A0 = “0”) or
command write (A0 = “1”)
1: Occurrence due to command write (A0 = “1”)
Output buffer 1 empty interrupt disable bit
0: Enabled
1: Disabled
Input buffer 1 full interrupt disable bit
0: Enabled
1: Disabled
Reserved bit (“0” at read/write)
Data bus buffer function select bit
0 : Single data bus buffer mode
(P72 functions as I/O port.)
1 : Double data bus buffer mode
(P72 functions as S1 input pin.)
7641 Group
Data bus buffer control register 1 b7
(address 004E16)
b6
b5
b4 b3
b2
b1 b0
A01
U2
IBF1 OBF1
U2
IBF0 OBF0
P74/OBF1
P73/IBF1
P55/A0
P72/S1
P56/R
P57/W
U7
P60/DQ0
U6
U5
Output data bus buffer
register 1
(address 004C16)
P61/DQ1
P62/DQ2
DBBSTS1
Input data bus buffer
register 1
(address 004C16)
RD
D B B1
RD
DBB0
Input data bus buffer
register 0
P65/DQ5
DBBSTS0
WR
(address 004816)
Internal data bus
P64/DQ4
WR
System bus
P63/DQ3
U4
P66/DQ6
Output data bus buffer
register 0
P67/DQ7
(address 004816)
U7
U6
U5
U4
A00
P57/W
P56/R
P54/S0
P55/A0
P53/IBF0
P52/OBF0
Data bus buffer control register 0 b7
(address 004A16)
Fig. 56 Master CPU bus interface block diagram
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b6
b5
b4
b3
b2
b1
b0
7641 Group
[Data Bus Buffer Status Register 0, 1 (DBBS0, DBBS1)]
004916, 004D16
The data bus buffer status registers 0, 1 consist of eight bits each.
Bits 0, 1, and 3 are read-only bits and indicate the status of the
data bus buffer. Bits 2, 4, 5, 6, and 7 are user definable flags
which can be programed, and can be read/written. The host CPU
can only read this register when the A0 pin is set to “H”.
•Bit 0: Output buffer full flag OBF0, OBF1
When writing data to the output data bus buffer, this flag is set to
“1”. When reading the output data bus buffer from the host CPU,
this flag is cleared to “0”.
•Bit 1: Input buffer full flag IBF0, IBF1
When writing data from the host CPU to the input data bus
buffer, this flag is set to “1”. When reading the input data bus
buffer from the slave CPU side, this flag is are cleared to “0”.
•Bit 3: A0 flag A00, A01
When writing data from the host CPU to the input data bus
buffer, the level of the A0 pin is latched.
[Input Data Bus Buffer Registers 0, 1 (DBBIN 0 , DBBIN 1 )]
004816, 004C16
Data on the data bus is latched to DBBIN0 or DBBIN1 by writing
request from the host CPU. Data of DBBINs can be read from the
Data Bus Buffer Registers (address 0048 16 or 004C16) on the
SFR area.
[Output Data Bus Buffer Registers 0, 1 (DBBOUT 0 ,
DBBOUT1)] 004816, 004C16
When writing data to the Data Bus Buffer Registers (address
004816 or 004C16) on the SFR area, data is set to DBBOUT0 or
DBBOUT1. Data of DBBOUTs is output onto the data bus by performing the reading request from the host CPU when the A0 pin is
set to “L”.
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7641 Group
Table 8 Function description of control I/O pins of master CPU bus interface
Name
OBF0
output
enable
bit
IBF0
output
enable
bit
OBF1
output
enable
bit
IBF1
output
enable
bit
Input/
Output
P52/OBF0
OBF0
1
0
0
0
Output
Status output signal.
OBF0 signal is output.
P53/IBF0
IBF0
0
1
0
0
Output
Status output signal.
IBF0 signal is output.
P54/S0
S0
—
—
—
—
Input
Chip select input.
This is used for selecting the data bus buffer, which is
selected at “L” level.
P55/A0
A0
—
—
—
—
Input
Address input.
This is used for selecting DBBSTS and DBBOUT
when the host CPU reads.
This is used for distinguishing command from data
when the host CPU writes.
P56/R (E)
R (E)
—
—
—
—
Input
This is a timing signal for reading data from the data
bus buffer to the host CPU.
P57/W (R/W)
W (R/W)
—
—
—
—
Input
This is a timing signal for writing data to the data bus
buffer by the host CPU.
P72/S1
S1
—
—
—
—
Input
Chip select input.
This is used for selecting the data bus buffer, which is
selected at “L” level.
P73/IBF1/HLDA
IBF1
0
0
0
1
Output
Status output signal.
IBF1 signal is output.
P74/OBF1
OBF1
0
0
1
0
Output
Status output signal.
OBF1 signal is output.
Pin
Rev.4.00 Aug 28, 2006
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Functions
7641 Group
COUNT SOURCE GENERATOR
The 7641 Group has a built-in special count source generator,
SCSG. This generator consists of two 8-bit timers: SCSG1 and
SCSG2. The output of the special count source generator can be
used as a clock source for the timer X, serial I/O and two UARTs.
The SCSG output is Clock SCSGCLK. The frequency is calculated
as follows:
SCSGCLK = φ ✕ {n1 / (n1+1)} ✕ {1 / (n2+1)}
n1: value set to SCSG1
n2: value set to SCSG2
SCSG Operation
Timers SCSG1 and SCSG2 are both down count timers. When the
count reaches “0”, an underflow occurs at the next count source
rising edge and the contents of the corresponding timer latch are
loaded to the timer. The division ratio of each SCSG-x timer is
given by 1 / (n+1), where “n” is the value set to the SCSG-x timer.
The output of Timer SCSG1 is ANDed with the original clock (φ) to
make a count source for Timer SCSG2.
If the SCSG1 Count Stop Bit (SCSGM1) is set to “1”, or Timer
SCSG1 is set to “0”, the SCSG1 count stops. When this happens,
the count source for Timer SCSG2 becomes φ.
Data Write Control
When the SCSG1 Data Write Control Bit or SCSG2 Data Write
Control Bit is set to “0”, and data is written to the SCSG-x timer;
the data is written to the corresponding latch and timer at the
same time. When that bit is set to “1”, the data is only written to
the latch.
SCSG1 data write control bit
SCSG1 count stop bit
SCSGCLK output control bit
SCSG1 Timer Reload Latch
φ
SCSG1 Timer (8)
SCSG1 count stop bit
SCSG1 count stop bit
SCSG2 data write control bit
SCSGCLK output control bit
SCSG2 Timer Reload Latch
SCSG2 Timer (8)
SCSGCLK output control bit
SCSGCLK
Fig. 57 Special count source generator block diagram
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7641 Group
b7
b0
Special count source mode register (address 002F16)
SCSGM
0 0 0 0
SCSG1 data write control bit
0: Writing data into both Timer latch and Timer simultaneously
1: Writing data into only Timer latch
SCSG1 count stop bit
0: Count start
1: Count stop
SCSG2 data write control bit
0: Writing data into both Timer latch and Timer simultaneously
1: Writing data into only Timer latch
SCSGCLK output control bit
0: SCSGCLK output disabled (SCSG1 and SCSG2 counts stop)
1: SCSGCLK output enabled
Reserved bits (“0” at read/write)
Fig. 58 Structure of special count source generator mode register
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REJ03B0191-0400
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7641 Group
FREQUENCY SYNTHESIZER (PLL)
The frequency synthesizer generates the 48 MHz clock required
by fUSB and fSYN, which are multiples of the external input reference f(XIN). Figure 59 shows the block diagram for the frequency
synthesizer circuit.
The Frequency Synthesizer Input Bit selects either f(X IN ) or
f(XCIN) as an input clock fIN for the frequency synthesizer.
The Frequency Synthesizer Multiply Register 2 (FSM2: address
006E16) divides fIN to generate fPIN, where
fPIN = fIN / 2(n + 1), n: value set to FSM2.
When the value of Frequency Synthesizer Multiply Register 2 is
set to 255, the division is not performed and fPIN will equal fIN.
[Frequency Synthesizer Control Register] FSC
Setting the Frequency Synthesizer Enable Bit (FSE) to “1” enables
the frequency synthesizer. When the Frequency Synthesizer Lock
Status Bit (LS) is “1” in the frequency synthesizer enabled, this indicates that fSYN and fVCO have correct frequencies.
■Notes
Make sure to connect a low-pulse filter to the LPF pin when using
the frequency synthesizer. In addition, please refer to “Programming Notes: Frequency Synthesizer” when recovering from a
Hardware Reset.
fVCO is generated according to the contents of Frequency Synthesizer Multiply Register 1 (FSM1: address 006D16), where
fVCO = fPIN ✕ {2(n + 1)}, n: value set to FSM1.
Set the value of FSM1 so that the value of fVCO is 48 MHz.
fSYN is generated according to the contents of the Frequency Synthesizer Divide Register (FSD: address 006F16), where
fSYN = fVCO / 2(m + 1), m: value set to FSD.
When the value of the Frequency Synthesizer Divide Register is
set to 255, the division is not performed and fSYN becomes invalid.
fVCO
Prescaler
fPIN
Frequency Divider
fSYN
Frequency
Multiplier
fUSB
Frequency
synthesizer lock
status bit
fIN
FSM2
FSM1
(address 006E16)
FSC
(address 006D16)
Data Bus
Fig. 59 Frequency synthesizer block diagram
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REJ03B0191-0400
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FSD
(address 006C16)
(address 006F16)
7641 Group
b7
b0
0
0 0
Frequency synthesizer control register (address 006C16)
FSC
Frequency synthesizer enable bit (FSE)
0: Disabled
1: Enabled
Fix to “00”.
Frequency synthesizer input bit (FIN)
0: f(XIN)
1: f(XCIN)
Reserved bit (“0” at read/write)
LPF current control (CHG1, CHG0) (Note)
b6b5
0 0: Not available
0 1: Low current
1 0: Intermediate current (recommended)
1 1: High current
Frequency synthesizer lock status bit
0: Unlocked
1: Locked
Note: Bits 6 and 5 are set to (bit 6, bit 5) = (1, 1) at reset.
When using the frequency synthesizer, we recommend to set to (bit 6, bit 5)
= (1, 0) after locking the frequency synthesizer.
Fig. 60 Structure of frequency synthesizer control register
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7641 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 20 cycles or more of φ. Then the RESET pin is returned to
an “H” level, and reset is released. They must be performed when
the power source voltages are between 3.00 V and 3.60 V or 4.15
V and 5.25 V.
After the reset is completed, the program starts from the address
contained in address FFFA 16 (high-order byte) and address
FFFB16 (low-order byte).
After oscillation has restarted, the timers 1 and 2 secures waiting
time for the internal clock φ oscillation stabilized automatically by
setting the timer 1 to “FF 16” and timer 2 to “01 16”. The internal
clock φ retains “H” level until Timer 2’s underflow and it cannot be
supplied until the underflow.
The pins state during reset are follows:
•When CNVss = “H”
: Outputting
Ports P0, P1, P33 to P37
Pins other than above mentioned ports : Inputting
•When CNVss = “L”
All pins
: Inputting.
Poweron
VCC
RESET
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc = 3.00 or 4.15 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 61 Reset circuit example
φ
RESET
Internal
reset
Address
?
?
?
?
FFFB
FFFA
ADH,L
Reset address from
the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 512 clock cycles
Notes: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 62 Reset sequence
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7641 Group
Address Register contents
Address Register contents
(1)
CPU mode register A (CPUA)
000016 0 0 0 0 1 1 0 0
(48) UART1 status register (U1STS)
003216 0 0 0 0 0 0 1 1
(2)
CPU mode register B (CPUB)
000116 1 0 0 0 0 0 1 1
(49) UART1 control register (U1CON)
003316
(3)
Interrupt request register A (IREQA)
000216
0016
(50) UART1 RTS control register (U1RTSC)
003616 1 0 0 0 0 0 0 0
(4)
Interrupt request register B (IREQB)
000316
0016
(51) UART2 mode register (U2MOD)
003816
(5)
Interrupt request register C (IREQC)
000416
0016
(52) UART2 status register (U2STS)
003A16 0 0 0 0 0 0 1 1
(6)
Interrupt control register A (ICONA)
000516
0016
(53) UART2 control register (U2CON)
003B16
(7)
Interrupt control register B (ICONB)
000616
0016
(54) UART2 RTS control register (U2RTSC)
003E16 1 0 0 0 0 0 0 0
(8)
Interrupt control register C (ICONC)
000716
0016
(55) DMAC index and status register (DMAIS)
003F16
0016
(9)
Port P0 (P0)
000816
0016
(56) DMAC channel x mode register 1 (DMAx1)
004016
0016
(10) Port P0 direction register (P0D)
000916
0016
(57) DMAC channel x mode register 2 (DMAx2)
004116
0016
(11) Port P1 (P1)
000A16
0016
(58) DMAC channel x source register Low (DMAxSL)
004216
0016
(12) Port P1 direction register (P1D)
000B16
0016
(59) DMAC channel x source register High (DMAxSH)
004316
0016
(13) Port P2 (P2)
000C16
0016
(60) DMAC channel x destination register Low (DMAxDL)
004416
0016
(14) Port P2 direction register (P2D)
000D16
0016
(61) DMAC channel x destination register High (DMAxDH)
004516
0016
(15) Port P3 (P3)
000E16
0016
(62) DMAC channel x transfer count register Low (DMAxCL) 004616
0016
(16) Port P3 direction register (P3D)
000F16
0016
(63) DMAC channel x transfer count register High (DMAxCH) 004716
0016
(17) Port control register (PTC)
001016
0016
(64) Data bus buffer register 0 (DBB0)
004816
0016
(18) Interrupt polarity select register (IPOL)
001116
0016
(65) Data bus buffer status register 0 (DBBS0)
004916
0016
(19) Port P2 pull-up control register (PUP2)
001216
0016
(66) Data bus buffer control register 0 (DBBC0)
004A16
0016
(20) USB control register (USBC)
001316
0016
(67) Data bus buffer register 1 (DBB1)
004C16
0016
(21) Port P6 (P6)
001416
0016
(68) Data bus buffer status register 1 (DBBS1)
004D16
0016
(22) Port P6 direction register (P6D)
001516
0016
(69) Data bus buffer control register 1 (DBBC1)
004E16
0016
(23) Port P5 (P5)
001616
0016
(70) USB address register (USBA)
005016
0016
(24) Port P5 direction register (P5D)
001716
0016
(71) USB power management register (USBPM) 005116
0016
(25) Port P4 (P4)
001816
0016
(72) USB interrupt status register 1 (USBIS1)
005216
0016
(26) Port P4 direction register (P4D)
001916
0016
(73) USB interrupt status register 2 (USBIS2)
005316
0016
(27) Port P7 (P7)
001A16
0016
(74) USB interrupt enable register 1 (USBIE1)
005416
FF16
(28) Port P7 direction register (P7D)
001B16
0016
(75) USB interrupt enable register 2 (USBIE2)
005516 0 0 1 1 0 0 1 1
(29) Port P8 (P8)
001C16
0016
(76) USB frame number register Low (USBSOFL)
005616
0016
(30) Port P8 direction register (P8D)
001D16
0016
(77) USB frame number register High (USBSOFH)
005716
0016
(31) Clock control register (CCR)
001F16
0016
(78) USB endpoint index register (USBINDEX)
005816
0016
(32) Timer XL (TXL)
002016
FF16
(79) USB endpoint x IN control register (IN_CSR) 005916
0016
(33) Timer XH (TXH)
002116
FF16
(80) USB endpoint x OUT control register (OUT_CSR)
0016
(34) Timer YL (TYL)
002216
FF16
(81) USB endpoint x IN max. packet size register (IN_MAXP) 005B16 0 0 0 0 1 0 0 0
(35) Timer YH (TYH)
002316
FF16
(82) USB endpoint x OUT max. packet size register (OUT_MAXP) 005C16 0 0 0 0 1 0 0 0
(36) Timer 1 (T1)
002416
FF16
(83) USB endpoint x OUT write count register Low (WRT_CNTL)
(37) Timer 2 (T2)
002516 0 0 0 0 0 0 0 1
(38) Timer 3 (T3)
002616
(39) Timer X mode register (TXM)
005A16
0016
0016
0016
(Note 1)
(Note 1)
005D16
0016
(84) USB endpoint x OUT write count register High (WRT_CNTH) 005E16
0016
FF16
(85) USB endpoint FIFO mode register (USBFIFOMR)
005F16
0016
002716
0016
(86) Flash memory control register (FMCR)
006A16 0 0 0 0 0 0 0 1
(40) Timer Y mode register (TYM)
002816
0016
(87) Frequency synthesizer control register (FSC)
006C16 0 1 1 0 0 0 0 0
(41) Timer 123 mode register (T123M)
002916
0016
(88) Frequency synthesizer multiply register 1 (FSM1)
006D16
FF16
(42) Serial I/O control register 1 (SIOCON1)
002B16 0 1 0 0 0 0 0 0
(89) Frequency synthesizer multiply register 2 (FSM2)
006E16
FF16
(43) Serial I/O control register 2 (SIOCON2)
002C16 0 0 0 1 1 0 0 0
(90) Frequency synthesizer divide register (FSM2)
006F16
FF16
FFC916
(Note 3)
(44) Special count source generator 1 (SCSG1) 002D16
FF16
(91) ROM code protect control register (ROMCP)
(45) Special count source generator 2 (SCSG2) 002E16
FF16
(92) Processor status register
(46) Special count source mode register (SCSGM) 002F16
0016
(93) Program counter
(47) UART1 mode register (U1MOD)
0016
FF16
(Note 3)
003016
(PS)
(PCH)
FFFB16 contents
(PCL)
FFFA16 contents
X : Not fixed
Notes 1: When using the endpoint 1, this contents are “0116”.
2: Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
3: The flash memory control register and the ROM code protect control register exists in the flash memory version only.
Fig. 63 Internal status at reset
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✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
7641 Group
CLOCK GENERATING CIRCUIT
The 7641 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. (An external feed-back resistor may be
needed depending on conditions.) However, an external feed-back
resistor is needed between XCIN and XCOUT.
When using an external clock, input the clocks to the XIN or XCIN
pin and leave the XOUT or XCOUT pin open.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
The internal system clock can be selected among f SYN, f(XIN),
f(XIN)/2, and f(XCIN). The internal clock φ is half the frequency of
internal system clock.
(1) fSYN clock
This is made by the frequency synthesizer. f(XIN) or f(XCIN) can be
selected as its input clock. See also section “FREQUENCY SYNTHESIZER”.
XCIN
XCOUT
XIN
XOUT
Rd (Note)
Rf
Rd
CCIN
CCOUT
CI N
COUT
Notes : Insert a damping resistor if required.
The resistance will vary depending on the oscillator
and the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added
external to the chip though a feedback resistor
exists on-chip, insert a feedback resistor between
XIN and XOUT following the instruction.
Fig. 64 Ceramic resonator or quartz-crystal oscillator external circuit
(2) f(XIN) clock
The frequency of internal system clock is the frequency of XIN pin.
(3) f(XIN)/2 clock
The frequency of internal system clock is half the frequency of XIN
pin.
(4) f(XCIN) clock
XCIN
The frequency of internal system clock is the frequency of XCIN
pin.
XIN
Open
External oscillation
circuit
External oscillation
circuit
VCC
VSS
VCC
VSS
Fig. 65 External clock input circuit
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 70 of 135
XOUT
Open
■Note
If you switch the oscillation between XIN - XOUT and XCIN - XCOUT,
stabilize both XIN and XCIN oscillations. The sufficient time is required for the XCIN oscillation to stabilize, especially immediately
after power on and at returning from the stop mode.
XCOUT
7641 Group
(5) Low power dissipation mode
(2) Wait mode
• The low power dissipation operation can be realized by stopping
the main clock XIN when using f(X CIN) as the internal system
clock. To stop the main clock, set the Main Clock (X IN-X OUT)
Stop Bit of the CPU mode register A to “1”.
• The low power dissipation operation can be realized by disabling
the reversed amplifier when inputting external clocks to the XIN
pin or XCIN pin. To disable the reversed amplifier, set the XCOUT
Oscillation Drive Disable Bit (CCR5) or XOUT Oscillation Drive
Disable Bit (CCR6) of the clock control register to “1”.
If the WIT instruction is executed, the internal clock φ stops at “H”
level, but the oscillator does not stop. The internal clock φ restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the internal clock φ is restarted.
Set the Interrupt Enable Bit to be used to release the wait mode to
enabled (“1”) and the Interrupt Disable Flag (I) to “0”.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal clock φ stops at “H”
level, and XIN and XCIN oscillators stop. Then the timer 1 is set to
“FF16” and the internal clock φ divided by 8 is automatically selected as its count source. Additionally, the timer 2 is set to “0116”
and the timer 1’s output is automatically selected as its count
source.
Set the Timer 1 and Timer 2 Interrupt Enable Bits to disabled (“0”)
before executing the STP instruction. When using an external interrupt to release the stop mode, set the Interrupt Enable Bit to be
used to enabled (“1”) and the Interrupt Disable Flag (I) to “0”.
Oscillator restarts at reset or when an external interrupt including
USB resume interrupts is received, but the internal clock φ remains at “H” until the timer 2 underflows. The internal clock φ is
supplied for the first time when the timer 2 underflows. Therefore
make sure not to set the Timer 1 Interrupt Request Bit and Timer
2 Interrupt Request Bit to “1” before the STP instruction stops the
oscillator.
b7
b0
0 0 0 0 0
Clock control register (address 001F16)
CCR
Reserved bits (“0” at read/write)
Fix to “0”.
XCOUT oscillation drive disable bit (CCR5)
0: XCOUT oscillation drive is enabled.
(When XCIN oscillation is enabled.)
1: XCOUT oscillation drive is disabled.
XOUT oscillation drive disable bit (CCR6)
0: XOUT oscillation drive is enabled.
(When XIN oscillation is enabled.)
1: XOUT oscillation drive is disabled.
XIN divider select bit (CCR7)
Valid when CPMA6, CPMA7 = “00”
0: f(XIN)/2 is used for the system clock.
1: f(XIN) is used for the system clock.
Fig. 66 Structure of clock control register
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7641 Group
P1HATRSTB
D Q
PIN1
T
R
D Q
T R
PIN2
P2LATRSTB
D Q
PIN1
T
R
P2+
D Q
R Q
T R
S
D Q
RESET
T
PIN1
D Q
RESET
P2+
T
STP instruction
P2LATRSTB
P2 peripheral
P1 peripheral
Oscillator count-down
timer 1 to 2
R Q
D Q
S
T
P2 peripheral
R Q
STP
instruction
STP instruction
S
P1 peripheral
P1HATRSTB
R Q
Interrupt request
Interrupt disable
flag l
PIN2
WI T
instruction
S
D Q
P2 out
T
P1 out
S
S Q
Internal
clock φ
R
P2LATRSTB
RESET
Delay
STP instruction
P2
D Q
R QB
P2+
OSCSTP
T
XOSCSTP
P1
Main clock (XIN-XOUT) stop bit
P1HATRSTB
XCOSCSTP
XOD
Sub-clock (XCIN-XCOUT)
stop bit
PIN1, PIN2
XDOSCSTP
XCOD
Slow memory wait
select bit
Slow memory wait
mode select bit
XCDOSCSTP
Slow memory
wait
P1+, P2+
RDY
XIN drive select bit
External clock select bit
f(XIN)
LPF
f(XCIN)
1/2
fEXT
LPF
XOSCSTP
Frequency synthesizer
input bit
XCOSCSTP
Internal system clock
select bit
fIN
Main clock (XIN-XOUT)
stop bit
Frequency
synthesizer
Sub-clock (XCIN-XCOUT)
stop bit
Frequency synthesizer LPF
enable bit
XIN
XOUT
XCIN
Fig. 67 Clock generating circuit block diagram
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XCOUT
1/2
fSYN
USB 48 MHz
clock output
7641 Group
Reset
φ = f(XIN/4) (Note 3)
(Note 2)
STOP
φ = f(XIN/4) (Note 3)
FSC0
“0”←→“1”
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock oscillating, (Note 4)
CPMA = 0C, FSC = 41
φ = f(PLL)/2
CPMA6
“0”←→“1”
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock oscillating,
CPMA = 4C, FSC = 41
WAIT
CPMA4
“1”←→“0”
WAIT
XIN clock oscillating,
XCIN clock stopped,
Frequency synthesizer
clock stopped,
CPMA = 0C, FSC = 60
φ = f(XIN/4) (Note 3)
(Note 2)
STOP
FSC0
“0”←→“1”
φ = f(XIN/4) (Note 3)
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating, (Note 4)
CPMA = 1C, FSC = 41
CPMA6
“0”←→“1”
φ = f(PLL)/2
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = 5C, FSC = 41
WAIT
CPMA7
“1”←→“0”
WAIT
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = 1C, FSC = 60
φ = f(XCIN/2)
(Note 2)
WAIT
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = 9C, FSC = 60
(Note 5)
φ = f(XCIN/2)
(Note 2)
STOP
WAIT
FSC0
“0”←→“1”
φ = f(XCIN/2)
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating, (Note 4)
CPMA = 9C, FSC = 41
CPMA6
“0”←→“1”
φ = f(PLL)/2
XIN clock oscillating,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = DC, FSC = 41
WAIT
CPMA5
“1”←→“0”
STOP
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock stopped,
CPMA = BC, FSC = 68
FSC0
“0”←→“1”
φ = f(XCIN/2)
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating, (Note 4)
CPMA = BC, FSC = 49
CPMA6
“0”←→“1”
φ = f(PLL)/2
XIN clock stopped,
XCIN clock oscillating,
Frequency synthesizer
clock oscillating,
CPMA = FC, FSC = 49
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : In Stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequency
synthesizer stops. Set the system clock and disable the frequency synthesizer before execution of the STP instruction.
3 : φ = f(XIN)/2 can be also used by setting the XIN divider select bit (CCR7) to “1”. Then this diagram also applies to that case.
4 : The frequency synthesizer’s input can be selected between XIN input and XCIN input regardless of the system clock. This diagram
assumes the frequency synthesizer’s input to be the system clock. Enable the oscillator to be used for the frequency synthesizer’s input
before enabling the frequency synthesizer.
5 : Select the XCIN input as the frequency synthesizer’s input by setting the frequency synthesizer input bit (FSC3) to “1” before stopping XIN
oscillation.
Remarks : This diagram assumes that:
•Stack page is page 1
•In single-chip mode
(Depending on the CPU mode register A)
•φ expresses the internal clock.
Fig. 68 State transitions of clock
Rev.4.00 Aug 28, 2006
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page 73 of 135
WAIT
7641 Group
PROCESSOR MODE
Single-chip mode, memory expansion mode, and microprocessor
mode which is only in the mask ROM version can be selected by
using the Processor Mode Bits of CPU mode register A (bits 0 and
1 of address 000016). In the memory expansion mode and microprocessor mode, a memory can be expanded externally via ports
P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins.
The port direction registers corresponding to those ports become
external memory areas.
Table 9 Port functions in memory expansion mode and
microprocessor mode
Port Name
Port P0
Port P1
Port P2
Port P3
Port P4
Function
Outputs low-order 8 bits of address.
Outputs high-order 8 bits of address.
Operates as I/O pins for data D7 to D0 (including
instruction code).
P30 is the RDY input pin.
P31 and P32 function only as output pins
P33 is the DMAOUT output pin.
P34 is the φOUT output pin.
P35 is the SYNCOUT output pin.
P36 is the WR output pin, and P37 is the RD output pin.
P40 is the EDMA pin.
(1) Single-chip mode
Select this mode by resetting the MCU with CNVSS connected to
VSS.
(2) Memory expansion mode
Select this mode by setting the Processor Mode Bits (b1, b0) to
“01” in software with CNVSS connected to VSS. This mode enables
external memory expansion while maintaining the validity of the internal ROM.
(3) Microprocessor mode
Select this mode by resetting the MCU with CNVSS connected to
VCC, or by setting the Processor Mode Bits (b1, b0) to “10” in software with CNVSS connected to VSS. In the microprocessor mode,
the internal ROM is no longer valid and an external memory must
be used.
Do not set this mode in the flash memory version.
M37641M8
000016
000816
001016
000016
SFR area
000816
001016
SFR area
007016
SFR area
SFR area
007016
Internal RAM
047016
Internal RAM
047016
800016
Internal ROM
FFFF16
FFFF16
Memory expansion mode Microprocessor mode
The shaded areas are external areas.
M37641F8
000016
SFR area
000816
001016
SFR area
007016
Internal RAM
0A7016
100016
Reserved area
800016
Internal ROM
FFFF16
Memory expansion mode
The shaded areas are external areas.
Fig. 69 Memory maps in processor modes other than singlechip mode
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7641 Group
b7
b0
CPU mode register A (address 000016)
CPMA
1
Processor mode bits
b1b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Microprocessor mode (Note 1)
1 1: Not available
Stack page select bit
0: Page 0
1: Page 1
Fix to “1”.
Sub-clock (XCIN-XCOUT) control bit
0: Stopped
1: Oscillating
Main clock (XIN-XOUT) control bit
0: Oscillating
1: Stopped
Internal system clock select bit (Note 2)
0: External clock (XIN-XOUT or XCIN-XCOUT)
1: fSYN
External clock select bit
0: XIN-XOUT
1: XCIN-XCOUT
Notes 1: This is not available in the flash memory version.
2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected
between f(XIN) or f(XIN)/2 by CCR7.
The internal clock φ is the internal system clock divided by 2.
Fig. 70 Structure of CPU mode register A
b7
1 0
b0
CPU mode register B (address 000116)
CPMB
Slow memory wait select bits
b1b0
0 0: No wait
0 1: One-time wait
1 0: Two-time wait
1 1: Three-time wait
Slow memory wait mode select bits
b3b2
0 0: Software wait
0 1: Not available
1 0: RDY wait
1 1: Software wait plus RDY input anytime wait
Expanded data memory access bit
0: EDMA output disabled
1: EDMA output enabled
HOLD function enable bit
0: HOLD function disabled
1: HOLD function enabled
Resereved bit (“0” at read/write)
Fix to “1”.
Fig. 71 Structure of CPU mode register B
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7641 Group
Slow Memory Wait
(2) RDY wait
The 7641 Group is equipped with the slow memory wait function
(Software wait, RDY wait, and Extended RDY wait: software wait
plus RDY input anytime wait) for easier interfacing with external
devices that have long access times. The slow memory wait function can be enabled in the memory expansion mode and
microprocessor mode. The appropriate wait mode is selected by
setting bits 0 to 3 of CPU mode register B (address 000116). This
function can extend the read cycle or write cycle only for access to
an external memory. However, this wait function cannot be enabled for access to addresses 000816 to 000F16.
RDY Wait is selected by setting “10” to the Slow Memory Wait
Mode Select Bits of CPU mode register B (address 000116). When
a fixed time of “L” is input to the RDY pin at the beginning of a
read/write cycle (before φ cycle falls), the MCU goes to the RDY
state. The read/write cycle can then be extended by one to three φ
cycles. The number of φ cycles to be added can be selected by
the Slow Memory Wait Bits.
(1) Software wait
The software wait is selected by setting “00” to the Slow Memory
Wait Mode Select Bits of CPU mode register B (address 000116).
Read/write cycles (“L” width of RD pin/WR pin) can be extended
by one to three φ cycles. The number of cycles to be extended can
be selected with the Slow Memory Wait Select Bits. When the
software wait function is selected, the RDY pin status becomes invalid.
(3) Software wait + Extended RDY wait
Extended RDY Wait is selected by setting “11” to the Slow
Memory Wait Mode Select Bits of CPU mode register B (address
000116). The read/write cycle can be extended when a fixed time
of “L” is input to the RDY pin at the beginning of a read/write cycle
(before φ cycle falls). The RDY pin state is checked continually at
each fall of φ cycle until the RDY pin goes to “H”. When “H” is input to the RDY pin, the wait is released within 1, 2, or 3 φ cycles
(as selected with the Slow Memory Wait Bits).
XIN
φ OUT
ADOUT
RD
WR
No wait
1-cycle software wait
CPMB = 0016
2-cycle software wait
CPMB = 0116
3-cycle software wait
CPMB = 0316
CPMB = 0216
Note: This diagram assumes φ = XIN/2.
Fig. 72 Software wait timing diagram
XIN
φ OUT
ADOUT
RD
WR
tsu
tsu
tsu
tsu
tsu
tsu
RDY
No wait
1-cycle RDY wait
CPMB = 0816
CPMB = 0916
Note: This diagram assumes φ = XIN/2.
Fig. 73 RDY wait timing diagram
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REJ03B0191-0400
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2-cycle RDY wait
CPMB = 0A16
3-cycle RDY wait
CPMB = 0B16
7641 Group
XIN
φOUT
ADOUT
RD
WR
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
RDY
No wait
1-cycle extended RDY wait
2-cycle extended RDY wait
CPMB = 0D16
CPMB = 0E16
CPMB = 0C16
XIN
φOUT
ADOUT
RD
WR
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
RDY
2-cycle extended RDY wait
CPMB = 0E16
3-cycle extended RDY wait
CPMB = 0F16
Note: This diagram assumes φ = XIN/2.
Fig. 74 Extended RDY wait (software wait plus RDY input anytime wait) timing diagram
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REJ03B0191-0400
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tsu
tsu
7641 Group
HOLD Function
Expanded Data Memory Access
The HOLD function is used for systems that consist of external circuits that access MCU buses without use of the CPU (Central
Processing Unit). The HOLD function is used to generate the timing in which the MCU will relinquish the bus from the CPU to the
external circuits. To use the HOLD function, set the HOLD function
Enable Bit of CPU mode register B (address 000116) to “1”. This
function can be used with both the HOLD pin and the HLDA pin.
The HOLD signal is a signal from an external circuit requesting the
MCU to relinquish use of the bus. When “L” level is input, the MCU
goes to the HOLD state and remains so while the pin is at “L”. The
oscillator does not stop oscillating during the HOLD state, therefore allowing the internal peripheral functions to operate during
this time.
When the MCU relinquishes use of the bus, “L” level is output from
the HLDA pin. The MCU makes ports P0 and P1 (address buses)
and port P2 (data bus) tri-state outputs and holds port P37 (RD
pin) and port P36 (WR pin) “H” level. Port P34 (φ OUT pin) continues to oscillate. This function is not valid when the MCU is using
the IBF1 function with the HLDA pin.
In Expanded Data Memory Access Mode, the MCU can access a
data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y)
instruction and the STA ($zz), Y (indirect Y) instruction.
To use this mode, set the Expanded Data Memory Access Bit of
CPU mode register B (address 000116) to “1”. In this case, port
P40 (EDMA pin) goes “L” level during the read/write cycle of the
LDA or STA instruction.
The determination of which bank to access is done by using an I/
O port to represent expanded addresses exceeding address bus
AB15. For example, when accessing 4 banks, use two I/O ports to
represent address buses AB16 and AB17.
XIN
φ OUT
RD, W R
ADDROUT
DATAIN/OUT
tsu(HOLD-φ)
th(φ-HOLD)
HOLD
HLDA
td(φ-HLDAL)
Note: This diagram assumes φ = XIN/2.
Fig. 75 Hold function timing diagram
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td(φ-HLDAH)
7641 Group
φ
SYNCOUT
RD
WR
Address
PC
Data
BAL, 00
PC +1
BAL
Op code
ADL + Y,
ADH
BAL+1, 00
ADL
ADH
ADL + Y,
ADH + C
Invalid
PC + 2
Data
Next
Op code
EDMA
Fig. 76 STA ($ zz), Y instruction sequence when EDMA enabled
φ
SYNCOUT
RD
WR
Address
PC
Data
PC +1
Op code
BAL, 00
BAL
ADL + Y,
ADH
BAL+1, 00
ADL
ADH
ADL + Y,
ADH + C
Invalid
PC + 2
Data
Next
Op code
EDMA
Fig. 77 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “0”
φ
SYNCOUT
RD
WR
Address
Data
PC
PC +1
Op code
BAL, 00
BAL
BAL+1, 00
ADL
ADH
ADL + Y,
ADH
ADL + Y,
ADH + C
Invalid
Data
EDMA
Fig. 78 LDA ($ zz), Y instruction sequence when EDMA enabled and T flag = “1”
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X, 00
Invalid
PC + 2
Data
Next
Op code
7641 Group
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 10 Absolute maximum ratings
Parameter
Symbol
Power source voltage
VCC
Analog power source voltage AVcc, Ext.Cap
AVCC
Input voltage
P00–P07, P10–P17, P20–P27,
VI
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
Input voltage
RESET, XIN, XCIN
VI
Input voltage
CNVSS
Mask ROM version
VI
Flash memory version
Input voltage
USB D+, USB D–
VI
Output voltage P00–P07, P10–P17, P20–P27,
VO
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87,
XOUT, XCOUT, LPF
Output
voltage
USB
D+, USB D–, Ext. Cap
VO
Power
dissipation
(Note)
Pd
Operating temperature
Topr
Storage temperature
Tstg
Conditions
All voltages are based on
Vss. Output transistors
are cut off.
Ta = 25°C
Ratings
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VCC+0.3
Unit
V
V
V
–0.3 to VCC+0.3
–0.3 to Vcc + 0.3
–0.3 to 6.5
–0.5 to 3.8
–0.3 to VCC+0.3
V
V
V
V
V
–0.5 to 3.8
750
–20 to 70
–40 to 125
V
mW
°C
°C
Note: The maximum power dissipation depends on the MCU’s power dissipation and the specific heat consumption of the package.
Rev.4.00 Aug 28, 2006
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page 80 of 135
7641 Group
Recommended Operating Conditions
In Vcc = 5 V
Table 11 Recommended operating conditions (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Min.
Typ.
Max.
VCC
Power source voltage
4.15
5.0
5.25
AVcc
Analog reference voltage
4.15
5.0
VCC
VSS
Power source voltage
0
AVSS
Analog reference voltage
0
VIH
“H” input voltage
P00–P07, P10–P17, P20–P27,
VCC
0.8VCC
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
VIH
“H” input voltage (Selecting VIHL level input) P20–P27
VCC
0.5VCC
VIH
“H” input voltage (Selecting TTL level input for MBI input)
VCC
2.0
P54–P57, P60–P67, P72
0.8VCC
VCC
VIH
“H” input voltage
RESET, XIN, XCIN, CNVss
2.0
3.8
VIH
“H” input voltage
USB D+, USB D–
0
0.2VCC
VIL
“L” input voltage
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
VIL
“L” input voltage (Selecting VIHL level input) P20–P27
0.16VCC
0
VIL
“L” input voltage (Selecting TTL level input for MBI input)
0.8
0
P54–P57, P60–P67, P72
0.2VCC
0
VIL
“L” input voltage
RESET, XIN, XCIN, CNVss
0.8
VIL
“L” input voltage
USB D+, USB D–
–80
ΣIOH(peak) “H” total peak output current
P00–P07, P10–P17, P20–P27,
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
80
ΣIOL(peak) “L” total peak output current
P00–P07, P10–P17, P20–P27,
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
ΣIOH(avg) “H” total average output current P00–P07, P10–P17, P20–P27,
–40
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
40
ΣIOL(avg)
“L” total average output current P00–P07, P10–P17, P20–P27,
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOH(peak)
“H” peak output current
P00–P07, P10–P17, P20–P27,
–10
(Note 2)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOL(peak)
“L” peak output current
P00–P07, P10–P17, P20–P27,
10
(Note 2)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOH(avg)
“H” average output current
P00–P07, P10–P17, P20–P27,
–5.0
(Note 3)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOL(avg)
“L” average output current
P00–P07, P10–P17, P20–P27,
5.0
(Note 3)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
f(CNTR0) Timer X input frequency (Note 4)
5.0
f(CNTR1) Timer Y input frequency (Note 4)
5.0
f(XIN)
Main clock input frequency (Notes 4, 5)
24
1
f(XCIN)
Sub-clock input frequency (Notes 4, 6)
50/5.0
32.768
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REJ03B0191-0400
page 81 of 135
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
kHz/MHz
7641 Group
Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average
value measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: The duty of oscillation frequency is 50 %.
5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However,
make sure to set φ to 12 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible.
6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an
external clock having 5 MHz frequency (max.) from the XCIN pin.
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7641 Group
Electrical Characteristics
In Vcc = 5 V
Table 12 Electrical characteristics (1) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
VOH
VOH
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“H” output voltage
USB D+, USB D-
VOL
“L” output voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
VOL
“L” output voltage
USB D+, USB D-
VT+–VT-
Hysteresis
CNTR0, CNTR1, INT0, INT1, RDY, HOLD,
P20–P27
Hysteresis
URXD1, URXD2 (SCLK), CTS2 (SRXD),
SRDY, CTS1
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“H” input current RESET, CNVSS
“H” input current XIN
“H” input current XCIN
“L” input current
P00–P07, P10–P17, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“L” input current RESET
“L” input current CNVSS
“L” input current XIN
“L” input current XCIN
“L” input current P20–P27
VT+–VT-
VT+–VTIIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
IIL
VRAM
Rev.4.00 Aug 28, 2006
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Test conditions
IOH = –10 mA
USB+, and USB- pins
pull-down via a resistor
of 15 kΩ ± 5 %
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 kΩ ± 5 %
IOL = 10 mA
Min.
VCC–2.0
Limits
Typ.
Max.
V
2.8
USB+, and USB- pins
pull-down via a resistor
of 15 kΩ ± 5 %
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 kΩ ± 5 %
3.6
V
2.0
V
0.3
V
0.5
V
0.5
V
5.0
V
µA
5.0
20
5.0
–5.0
µA
µA
µA
µA
–9.0
–5.0
–20
–20
–5.0
–5.0
µA
µA
µA
µA
µA
–65
–140
µA
5.25
V
0.5
VI = VCC
9.0
VI = VSS
VI = VSS
Pull-ups “off”
VCC = 5.0 V, VI = VSS
Pull-ups “on”
When clock is stopped
–30
2.0
Unit
7641 Group
In Vcc = 5 V
Table 13 Electrical characteristics (2) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
ICC
Parameter
Power source current
(Output transistor is
isolated.)
Test conditions
Min.
Normal mode (Note 1)
f(XIN) = 24 MHz, φ = 12 MHz
USB operating
Frequency synthesizer ON
Wait mode (Note 2)
f(XIN) = 24 MHz, φ = 12 MHz
USB block enabled, USB clock
stopped, Frequency synthesizer ON
Wait mode (Note 3)
f(XCIN) = 32 kHz, φ = 16 kHz
USB block disabled
Frequency synthesizer OFF
USB transceiver DC-DC converter OFF
Stop mode
USB transceiver DC-DC converter ON
Low current mode (USBC3 = “1”)
Stop mode
USB transceiver DC-DC converter OFF
Ta = 25 °C
Stop mode
USB transceiver DC-DC converter OFF
Ta = 70 °C
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
USB operating with USB transceiver DC-DC converter enabled
Operating functions: Frequency synthesizer, CPU, two UARTs, DMAC, Timers and Count source generator
Disabled functions: Master CPU bus interface and Serial I/O
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled
Operating functions: Frequency synthesizer, Timers and Count source generator
Disabled functions: CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O
3: Operating in single-chip mode with Wait mode
XIN - XOUT oscillator stopped
Clock input from XCIN pin (XCOUT oscillator stopped)
USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled
Operating functions: Timers and Count source generator
Disabled functions: Frequency synthesizer, CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O
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Limits
Typ.
40
Max.
90
5.0
11
mA
10
µA
250
µA
1.0
µA
10
µA
100
Unit
mA
7641 Group
Timing Requirements
In Vcc = 5 V
Table 14 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(INT)
tWH(INT)
tWL(INT)
tC(CNTRI)
tWH(CNTRI)
tWL(CNTRI)
td(φ -TOUT)
td(φ -CNTR0)
tC(CNTRE0)
tWH(CNTRE0)
tWL(CNTRE0)
td(φ -CNTR1)
tC(CNTRE1)
tWH(CNTRE1)
tWL(CNTRE1)
tC(SCLKE)
tWH(SCLKE)
tWL(SCLKE)
tsu(SRXD-SCLKE)
th(SCLKE-SRXD)
td(SCLKE-STXD)
tv(SCLKE-SRDY)
tc(SCLKI)
tWH(SCLKI)
tWL(SCLKI)
tsu(SRXD-SCLKI)
th(SCLKI-SRXD)
td(SCLKI-STXD)
Parameter
Reset input “L” pulse width
Main clock input cycle time (Note)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
INT0, INT1 input cycle time
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
Timer TOUT delay time
Timer CNTR0 delay time (Pulse output mode)
Timer CNTR0 input cycle time (Event counter mode)
Timer CNTR0 input “H” pulse width (Event counter mode)
Timer CNTR0 input “L” pulse width (Event counter mode)
Timer CNTR1 delay time (Pulse output mode)
Timer CNTR1 input cycle time (Event counter mode)
Timer CNTR1 input “H” pulse width (Event counter mode)
Timer CNTR1 input “L” pulse width (Event counter mode)
Serial I/O external clock input cycle time
Serial I/O external clock input “H” pulse width
Serial I/O external clock input “L” pulse width
Serial I/O input setup time (external clock)
Serial I/O input hold time (external clock)
Serial I/O output delay time (external clock)
Serial I/O SRDY valid time (external clock)
Serial I/O internal clock output cycle time
Serial I/O internal clock output “H” pulse width
Serial I/O internal clock output “L” pulse width
Serial I/O input setup time (internal clock)
Serial I/O input hold time (internal clock)
Serial I/O output delay time (internal clock)
Min.
2
41.66
0.4•tc(XIN)
0.4•tc(XIN)
200
0.4•tc(XCIN)
0.4•tc(XCIN)
200
90
90
200
80
80
Limits
Typ.
Max.
15
15
200
0.4•tc(CNTRE0)
0.4•tc(CNTRE0)
15
200
0.4•tc(CNTRE1)
0.4•tc(CNTRE1)
400
190
180
15
10
25
26
166.66
0.5•tc(SCLKI) – 5
0.5•tc(SCLKI) – 5
20
5
5
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: Make sure not to exceed 12 MHz of φ, in other words, tc(φ) ≥ 83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of
tc(XIN) < 41.66 ns.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 85 of 135
7641 Group
In Vcc = 5 V
Table 15 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tsu(S-R)
tsu(S-W)
th(R-S)
th(W-S)
tsu(A-R)
tsu(A-W)
th(R-A)
th(W-A)
tw(R)
tw(W)
tsu(D-W)
th(W-D)
ta(R-D)
tv(R-D)
tv(R-OBF)
td(W-IBF)
Parameter
S0, S1 setup time for read
S0, S1 setup time for write
S0, S1 hold time for read
S0, S1 hold time for write
A0 setup time for read
A0 setup time for write
A0 hold time for read
A0 hold time for write
Read pulse width
Write pulse width
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after read
IBF output transmission time after write
Min.
0
0
0
0
10
10
0
0
50
50
25
0
Limits
Typ.
Max.
40
10
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
In Vcc = 5 V
Table 16 Master CPU bus interface (MBI; R/W type) (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tsu(S-E)
th(E-S)
tsu(A-E)
th(E-A)
tsu(RW-E)
th(E-RW)
tw(E)
tw(E-E)
tsu(D-E)
th(E-D)
ta(E-D)
tv(E-D)
tv(E-OBF)
td(E-IBF)
Parameter
S0, S1 setup time
S0, S1 hold time
A0 setup time
A0 hold time
R/W setup time
R/W hold time
Enable pulse width
Enable pulse interval
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after E inactive
IBF output transmission time after E inactive
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 86 of 135
Min.
0
0
10
0
10
10
50
50
25
0
Limits
Typ.
Max.
40
10
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7641 Group
In Vcc = 5 V
Table 17 Timing requirements and switching characteristics in memory expansion and microprocessor modes
(Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tC(φ)
tWH(φ)
tWL(φ)
td(φ -AH)
tv(φ -AH)
td(φ -AL)
tv(φ -AL)
td(φ -WR)
tv(φ -WR)
td(φ -RD)
tv(φ -RD)
td(φ -SYNC)
tv(φ -SYNC)
td(φ -DMA)
tv(φ -DMA)
tsu(RDY- φ)
th(φ -RDY)
tsu(HOLD- φ)
th(φ -HOLD)
td(φ -HLDAL)
td(φ -HLDAH)
tsu(DB- φ)
th(φ -DB)
td(φ -DB)
tV(φ -DB)
td(φ -EDMA)
tv(φ -EDMA)
tWL(WR) (Note 2)
tWL(RD) (Note 2)
td(AH-WR)
td(AL-WR)
tv(WR-AH)
tv(WR-AL)
td(AH-RD)
td(AL-RD)
tv(RD-AH)
tv(RD-AL)
tsu(RDY-WR)
th(WR-RDY)
tsu(RDY-RD)
th(RD-RDY)
tsu(DB-RD)
th(RD-DB)
td(WR-DB)
tv(WR-DB)
tv(WR-EDMA)
tv(RD-EDMA)
tr(D+), tr(D-)
tf(D+), tf(D-)
Parameter
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AB15–AB8 delay time
AB15–AB8 valid time
AB7–AB0 delay time
AB7–AB0 valid time
WR delay time
WR valid time
RD delay time
RD valid time
SYNCOUT delay time
SYNCOUT valid time
DMAOUT delay time
DMAOUT valid time
RDY setup time
RDY hold time
HOLD setup time
HOLD hold time
HOLD “L” delay time
HOLD “H” delay time
Data bus setup time
Data bus hold time
Data bus delay time
Data bus valid time (Note 1)
EDMA delay time
EDMA valid time
WR pulse width
RD pulse width
AB15–AB8 valid time before WR
AB7–AB0 valid time before WR
AB15–AB8 valid time after WR
AB7–AB0 valid time after WR
AB15–AB8 valid time before RD
AB7–AB0 valid time before RD
AB15–AB8 valid time after RD
AB7–AB0 valid time after RD
RDY setup time before WR
RDY hold time after WR
RDY setup time before RD
RDY hold time after RD
Data bus setup time before RD
Data bus hold time after RD
Data bus delay time before WR
Data bus valid time after WR (Note 1)
EDMA delay time after WR
EDMA valid time after RD
USB output rise time, CL = 50 pF
USB output fall time, CL = 50 pF
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 87 of 135
Min.
83.33
0.5•tc(φ) – 5
0.5•tc(φ) – 5
Limits
Typ.
Max.
31
5
33
5
6
3
6
3
6
4
25
5
21
0
21
0
25
25
7
0
22
13
9
4
0.5•tc(φ) – 5
0.5•tc(φ) – 5
0.5•tc(φ) – 28
0.5•tc(φ) – 30
0
0
0.5•tc(φ) – 28
0.5•tc(φ) – 30
0
0
27
0
27
0
13
0
20
10
2
2
4
4
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7641 Group
Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF
2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number)
twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number)
For example, two software waits, PHI = 12 MHz operating
twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns
Recommended Operating Conditions
In Vcc = 3 V
Table 18 Recommended operating conditions (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Min.
Max.
Typ.
VCC
Power source voltage
3.0
3.6
3.3
AVcc
Analog reference voltage
3.0
VCC
3.3
VSS
Power source voltage
0
AVSS
Analog reference voltage
0
Ext. Cap. DC-DC converter voltage
3.6
3.0
3.3
VIH
“H” input voltage
P00–P07, P10–P17, P20–P27,
0.8VCC
VCC
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
VIH
“H” input voltage (Selecting VIHL level input) P20–P27
VCC
0.5VCC
VIH
“H” input voltage
RESET, XIN, XCIN, CNVss
VCC
0.8VCC
VIH
“H” input voltage
USB D+, USB D–
2.0
VIL
“L” input voltage
P00–P07, P10–P17, P20–P27,
0.2VCC
0
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
VIL
“L” input voltage (Selecting VIHL level input) P20–P27
0
0.16VCC
VIL
“L” input voltage
RESET, XIN, XCIN, CNVss
0
0.2VCC
VIL
“L” input voltage
USB D+, USB D–
0.8
ΣIOH(peak) “H” total peak output current
P00–P07, P10–P17, P20–P27,
–80
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
ΣIOL(peak) “L” total peak output current
P00–P07, P10–P17, P20–P27,
80
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
ΣIOH(avg) “H” total average output current P00–P07, P10–P17, P20–P27,
–40
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
ΣIOL(avg)
“L” total average output current P00–P07, P10–P17, P20–P27,
40
(Note 1)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOH(peak)
“H” peak output current
P00–P07, P10–P17, P20–P27,
–10
(Note 2)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOL(peak)
“L” peak output current
P00–P07, P10–P17, P20–P27,
10
(Note 2)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
IOH(avg)
“H” average output current
P00–P07, P10–P17, P20–P27,
–5.0
(Note 3)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
5.0
IOL(avg)
“L” average output current
P00–P07, P10–P17, P20–P27,
(Note 3)
P30–P37, P40–P44, P50–P57,
P60–P67, P70–P74, P80–P87
f(CNTR0) Timer X input frequency (Note 4)
5.0
f(CNTR1) Timer Y input frequency (Note 4)
5.0
f(XIN)
Main clock input frequency (Notes 4, 5)
24
1
f(XCIN)
Sub-clock input frequency (Notes 4, 6)
50/5.0
32.768
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 88 of 135
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
kHz/MHz
7641 Group
Notes 1: The total peak output current is the peak value of the peak currents flowing through all the applicable ports. The total average output current is the average
value measured over 100 ms flowing through all the applicable ports.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: The duty of oscillation frequency is 50 %.
5: Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins. Its maximum oscillation frequency must be 24 MHz. However,
make sure to set φ to 6 MHz or slower. More faster clocks are required as the f(XIN) when using the frequency synthesizer as possible.
6: Connect a ceramic resonator or a quartz-crystal oscillator between the XCIN and XCOUT pins. Its maximum oscillation frequency must be 50 kHz. Input an
external clock having 5 MHz (max.) frequency from the XCIN pin.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 89 of 135
7641 Group
Electrical Characteristics
In Vcc = 3 V
Table 19 Electrical characteristics (1) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
VOH
VOH
VOL
VOL
VT+–VT-
VT+–VT-
VT+–VTIIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IIL
IIL
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“H” output voltage
USB D+, USB D-
“L” output voltage
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“L” output voltage
USB D+, USB D-
Hysteresis
CNTR0, CNTR1, INT0, INT1, RDY, HOLD,
P20–P27
Hysteresis
URXD1, URXD2 (SCLK), CTS2 (SRXD),
SRDY, CTS1
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“H” input current RESET, CNVSS
“H” input current XIN
“H” input current XCIN
“L” input current
P00–P07, P10–P17, P30–P37,
P40–P44, P50–P57, P60–P67, P70–P74,
P80–P87
“L” input current RESET
“L” input current CNVSS
“L” input current XIN
“L” input current XCIN
“L” input current P20–P27
VRAM
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 90 of 135
Test conditions
IOH = –1 mA
Min.
VCC–1.0
USB+, and USB- pins
pull-down via a resistor
of 15 kΩ ± 5 %
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 kΩ ± 5 %
IOL = 1 mA
2.8
USB+, and USB- pins
pull-down via a resistor
of 15 kΩ ± 5 %
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 kΩ ± 5 %
0
Limits
Typ.
Max.
Unit
V
3.6
V
1.0
V
0.3
V
0.3
V
0.3
V
VI = VCC
5.0
V
µA
VI = VSS
5.0
20
5.0
–5.0
µA
µA
µA
µA
–9.0
–5.0
–20
–20
–5.0
–5.0
µA
µA
µA
µA
µA
–20
–50
µA
0.3
9.0
VI = VSS
Pull-ups “off”
VCC = 3.0 V, VI = VSS
Pull-ups “on”
When clock is stopped
–10
2.0
V
7641 Group
In Vcc = 3 V
Table 20 Electrical characteristics (2) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Min.
Typ.
Normal mode (Note 1)
ICC
Power source current
25
f(XIN) = 24 MHz, φ = 6 MHz
(Output transistor is
USB operating
isolated.)
Frequency synthesizer ON
Wait mode (Note 2)
2.5
f(XIN) = 24 MHz, φ = 6 MHz
USB block enabled, USB clock
stopped, Frequency synthesizer ON
Wait mode (Note 3)
f(XCIN) = 32 kHz, φ = 16 kHz
USB block disabled
Frequency synthesizer OFF
USB transceiver DC-DC converter OFF
Stop mode
USB transceiver DC-DC converter OFF
Ta = 25 °C
Stop mode
USB transceiver DC-DC converter OFF
Ta = 70 °C
<Test conditions>
Notes 1: Operating in single-chip mode
Clock input from XIN pin (XOUT oscillator stopped)
USB operating with USB transceiver DC-DC converter enabled
Operating functions: Frequency synthesizer, CPU, two UARTs, DMAC, Timers and Count source generator
Disabled functions: Master CPU bus interface and Serial I/O
2: Operating in single-chip mode with Wait mode
Clock input from XIN pin (XOUT oscillator stopped)
USB suspended due to USB clock stopped with USB transceiver DC-DC converter enabled
Operating functions: Frequency synthesizer, Timers and Count source generator
Disabled functions: CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O
3: Operating in single-chip mode with Wait mode
XIN - XOUT oscillator stopped
Clock input from XCIN pin (XCOUT oscillator stopped)
USB stopped, USB clock stopped and USB transceiver DC-DC converter disabled
Operating functions: Timers and Count source generator
Disabled functions: Frequency synthesizer, CPU, two UARTs, DMAC, Master CPU bus interface and Serial I/O
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 91 of 135
Max.
45
Unit
mA
6
mA
6
µA
1.0
µA
10
µA
7641 Group
Timing Requirements
In Vcc = 3 V
Table 21 Timing requirements (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(INT)
tWH(INT)
tWL(INT)
tC(CNTRI)
tWH(CNTRI)
tWL(CNTRI)
td(φ -TOUT)
td(φ -CNTR0)
tC(CNTRE0)
tWH(CNTRE0)
tWL(CNTRE0)
td(φ -CNTR1)
tC(CNTRE1)
tWH(CNTRE1)
tWL(CNTRE1)
tC(SCLKE)
tWH(SCLKE)
tWL(SCLKE)
tsu(SRXD-SCLKE)
th(SCLKE-SRXD)
td(SCLKE-STXD)
tv(SCLKE-SRDY)
tc(SCLKI)
tWH(SCLKI)
tWL(SCLKI)
tsu(SRXD-SCLKI)
th(SCLKI-SRXD)
td(SCLKI-STXD)
Parameter
Reset input “L” pulse width
Main clock input cycle time (Note)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
INT0, INT1 input cycle time
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
Timer TOUT delay time
Timer CNTR0 delay time (Pulse output mode)
Timer CNTR0 input cycle time (Event counter mode)
Timer CNTR0 input “H” pulse width (Event counter mode)
Timer CNTR0 input “L” pulse width (Event counter mode)
Timer CNTR1 delay time (Pulse output mode)
Timer CNTR1 input cycle time (Event counter mode)
Timer CNTR1 input “H” pulse width (Event counter mode)
Timer CNTR1 input “L” pulse width (Event counter mode)
Serial I/O external clock input cycle time
Serial I/O external clock input “H” pulse width
Serial I/O external clock input “L” pulse width
Serial I/O input setup time (external clock)
Serial I/O input hold time (external clock)
Serial I/O output delay time (external clock)
Serial I/O SRDY valid time (external clock)
Serial I/O internal clock output cycle time
Serial I/O internal clock output “H” pulse width
Serial I/O internal clock output “L” pulse width
Serial I/O input setup time (internal clock)
Serial I/O input hold time (internal clock)
Serial I/O output delay time (internal clock)
Note: Make sure not to exceed 6 MHz of φ, in other words, tc(φ) ≥ 166.66 ns).
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 92 of 135
Min.
2
41.66
0.4•tc(XIN)
0.4•tc(XIN)
200
0.4•tc(XCIN)
0.4•tc(XCIN)
250
110
110
250
110
110
Limits
Typ.
Max.
17
16
250
0.4•tc(CNTRE0)
0.4•tc(CNTRE0)
15
250
0.4•tc(CNTRE1)
0.4•tc(CNTRE1)
450
220
190
20
15
34
35
300
0.5•tc(SCLKI) – 5
0.5•tc(SCLKI) – 5
20
5
5
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7641 Group
In Vcc = 3 V
Table 22 Master CPU bus interface (MBI; RD, WR separate type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tsu(S-R)
tsu(S-W)
th(R-S)
th(W-S)
tsu(A-R)
tsu(A-W)
th(R-A)
th(W-A)
tw(R)
tw(W)
tsu(D-W)
th(W-D)
ta(R-D)
tv(R-D)
tv(R-OBF)
td(W-IBF)
Parameter
S0, S1 setup time for read
S0, S1 setup time for write
S0, S1 hold time for read
S0, S1 hold time for write
A0 setup time for read
A0 setup time for write
A0 hold time for read
A0 hold time for write
Read pulse width
Write pulse width
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after read
IBF output transmission time after write
Min.
0
0
0
0
10
10
0
0
80
80
35
0
Limits
Typ.
Max.
65
10
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
In Vcc = 3 V
Table 23 Master CPU bus interface (MBI; R/W type) (Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tsu(S-E)
th(E-S)
tsu(A-E)
th(E-A)
tsu(RW-E)
th(E-RW)
tw(E)
tw(E-E)
tsu(D-E)
th(E-D)
ta(E-D)
tv(E-D)
tv(E-OBF)
td(E-IBF)
Parameter
S0, S1 setup time
S0, S1 hold time
A0 setup time
A0 hold time
R/W setup time
R/W hold time
Enable pulse width
Enable pulse interval
Data input setup time before write
Data input hold time after write
Data output enable time after read
Data output disable time after read
OBF output transmission time after E inactive
IBF output transmission time after E inactive
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Min.
0
0
10
0
10
10
80
80
35
0
Limits
Typ.
Max.
65
10
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7641 Group
In Vcc = 3 V
Table 24 Timing requirements and switching characteristics in memory expansion and microprocessor modes
(Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Symbol
tC(φ)
tWH(φ)
tWL(φ)
td(φ -AH)
tv(φ -AH)
td(φ -AL)
tv(φ -AL)
td(φ -WR)
tv(φ -WR)
td(φ -RD)
tv(φ -RD)
td(φ -SYNC)
tv(φ -SYNC)
td(φ -DMA)
tv(φ -DMA)
tsu(RDY- φ)
th(φ -RDY)
tsu(HOLD- φ)
th(φ -HOLD)
td(φ -HLDAL)
td(φ -HLDAH)
tsu(DB- φ)
th(φ -DB)
td(φ -DB)
tV(φ -DB)
td(φ -EDMA)
tv(φ -EDMA)
tWL(WR) (Note 2)
tWL(RD) (Note 2)
td(AH-WR)
td(AL-WR)
tv(WR-AH)
tv(WR-AL)
td(AH-RD)
td(AL-RD)
tv(RD-AH)
tv(RD-AL)
tsu(RDY-WR)
th(WR-RDY)
tsu(RDY-RD)
th(RD-RDY)
tsu(DB-RD)
th(RD-DB)
td(WR-DB)
tv(WR-DB)
tv(WR-EDMA)
tv(RD-EDMA)
tr(D+), tr(D-)
tf(D+), tf(D-)
Parameter
φ clock cycle time
φ clock “H” pulse width
φ clock “L” pulse width
AB15–AB8 delay time
AB15–AB8 valid time
AB7–AB0 delay time
AB7–AB0 valid time
WR delay time
WR valid time
RD delay time
RD valid time
SYNCOUT delay time
SYNCOUT valid time
DMAOUT delay time
DMAOUT valid time
RDY setup time
RDY hold time
HOLD setup time
HOLD hold time
HOLD “L” delay time
HOLD “H” delay time
Data bus setup time
Data bus hold time
Data bus delay time
Data bus valid time (Note 1)
EDMA delay time
EDMA valid time
WR pulse width
RD pulse width
AB15–AB8 valid time before WR
AB7–AB0 valid time before WR
AB15–AB8 valid time after WR
AB7–AB0 valid time after WR
AB15–AB8 valid time before RD
AB7–AB0 valid time before RD
AB15–AB8 valid time after RD
AB7–AB0 valid time after RD
RDY setup time before WR
RDY hold time after WR
RDY setup time before RD
RDY hold time after RD
Data bus setup time before RD
Data bus hold time after RD
Data bus delay time after WR
Data bus valid time after WR (Note 1)
EDMA delay time after WR
EDMA valid time after RD
USB output rise time, CL = 50 pF
USB output fall time, CL = 50 pF
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Min.
166.66
0.5•tc(φ) – 5
0.5•tc(φ) – 5
Limits
Typ.
Max.
45
7
47
7
8
4
8
3
11
4
26
9
35
0
21
0
30
30
9
0
30
15
12
8
0.5•tc(φ) – 6
0.5•tc(φ) – 6
0.5•tc(φ) – 33
0.5•tc(φ) – 35
0
0
0.5•tc(φ) – 33
0.5•tc(φ) – 35
0
0
45
0
45
0
18
0
28
12
3
3
4
4
20
20
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7641 Group
Notes 1: Test conditions: IOHL = ± 5mA, CL = 50 pF
2: twL(RD) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number)
twL(WR) = ((n + 0.5) • tc(PHI)) – 5 ns (n = wait number)
For example, two software waits, PHI = 12 MHz operating
twL(RD) = 2.5 • tc(PHI) – 5 ns = 203.33 ns
Measurement output pin
1 kΩ
100
pF
Measurement output pin
CMOS output
Fig. 79 Circuit for measuring output switching characteristics (1)
100 pF
N-channel open-drain output (Note)
Note: This diagram applies when bit 7 of the serial I/O control
register 1 is “1”.
Fig. 80 Circuit for measuring output switching characteristics (2)
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7641 Group
● Timing diagram
[Interrupt]
tC(CNTRI)
tWH(CNTRI)
CNTR0, CNTR1
tWL(CNTRI)
0.8VCC
0.2VCC
tC(INT)
tWL(INT)
tWH(INT)
INT0, INT1
0.8VCC
0.2VCC
[Input]
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
XCIN
0.8VCC
0.2VCC
[Timer]
φ
0.5VCC
td(φ – TOUT)
TOUT
0.5VCC
td(φ – CNTR0,1)
CNTR0, CNTR1
0.5VCC
tC(CNTRE0,1)
tWH(CNTRE0,1)
CNTR0, CNTR1
Fig. 81 Timing diagram (1)
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0.8VCC
tWL(CNTRE0,1)
0.2VCC
7641 Group
● Timing diagram
[Serial I/O]
tC(SCLKE,I)
tWL(SCLKE, I)
SCLK
tWH(SCLKE,I)
0.8VCC
0.2VCC
tsu(SRXD – SCLKE, I)
th(SCLKE, I – SRXD)
0.8VCC
0.2VCC
SRXD
td(SCLKE, I – STXD)
0.5VCC
STXD
tv(SCLKE – SRDY)
0.8VCC
SRDY
Fig. 82 Timing diagram (2)
tr(D+)
tr(D-)
tf(D+)
tf(D-)
USBD+,
USBD-
0.1VOH
Fig. 83 Timing diagram (3)
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0.9VOH
7641 Group
● Timing diagram
[Master CPU bus interface: R/W separate mode]
<Read>
tsu(A-R)
A0
th(R-A)
0.8VCC(2.0V)
0.2VCC(0.8V)
tsu(S-R)
S0, S1
th(R-S)
0.2VCC(0.8V)
tw(R)
0.8VCC(2.0V)
0.2VCC(0.8V)
R
0.8VCC
0.2VCC
0.8VCC
0.2VCC
DQ0 to DQ7
ta(R-D)
tv(R-D)
tv(R-OBF)
OBF
0.2VCC
<Write>
tsu(A-W)
A0
th(W-A)
0.8VCC(2.0V)
0.2VCC(0.8V)
tsu(S-W)
S0, S1
th(W-S)
0.2VCC(0.8V)
tw(W)
W
0.8VCC(2.0V)
0.2VCC(0.8V)
tsu(D-W)
DQ0 to DQ7
0.8VCC
0.2VCC
th(W-D)
0.8VCC
0.2VCC
td(W-IBF)
IBF
0.2VCC
Note: This timing applies in the case of the master bus input level select bit
(PTC7) = “1” (TTL level input)
Fig. 84 Timing diagram (4)
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7641 Group
● Timing diagram
[Master CPU bus interface: R/W mode]
tw(E-E)
E
tw(E)
0.8VCC(2.0V)
0.2VCC(0.8V)
0.2VCC(0.8V)
<Read>
tsu(A-E)
A0
R/W
th(E-A)
0.8VCC(2.0V)
0.2VCC(0.8V)
tsu(S-E)
S0, S1
DQ0 to DQ7
th(E-S)
0.2VCC(0.8V)
0.8VCC
0.2VCC
0.8VCC
0.2VCC
ta(E-D)
<Write>
tv(E-D)
tsu(D-E)
DQ0 to DQ7
0.8VCC
0.2VCC
0.8VCC
0.2VCC
th(E-D)
tv(E-OBF)
td(E-IBF)
OBF, IBF
0.2VCC
Note: This timing applies in the case of the master bus input level select bit
(PTC7) = “1” (TTL level input)
Fig. 85 Timing diagram (5)
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7641 Group
tC(φ)
tWH(φ)
φ
tWL(φ)
0.5VCC
tv(φ-AH)
td(φ-AH)
AB15 to AB8
0.5VCC
td(φ-AL)
AB7 to AB0
tv(φ-AL)
0.5VCC
tv(φ-SYNC)
td(φ-SYNC)
0.5VCC
SYNCOUT
tv(φ-WR)
tv(φ-RD)
td(φ-WR)
td(φ-RD)
0.5VCC
RD,WR
tv(φ-DMA)
td(φ-DMA)
DMAOUT
n cycles of φ
0.5VCC
tsu(RDY-φ)
RDY
th(φ-RDY)
0.8VCC
0.2VCC
tsu(HOLD-φ) th(φ-HOLD)
HOLD
(at entering)
0.8VCC
0.2VCC
td(φ-HLDAL)
0.5VCC
HLDA
tsu(HOLD-φ) th(φ-HOLD)
HOLD
(at releasing)
0.8VCC
0.2VCC
td(φ-HLDAH)
0.5VCC
HLDA
tsu(DB-φ)
<CPU read>
0.8VCC
0.2VCC
DB0 to DB7
td(φ-DB)
<CPU write>
DB0 to DB7
EDMA
page 100 of 135
tv(φ-DB)
0.5VCC
td(φ-EDMA)
tv(φ-EDMA)
0.5VCC
0.5VCC
Fig. 86 Timing diagram (6); Memory expansion and microprocessor modes
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th(φ-DB)
7641 Group
tWL(RD)
tWL(WR)
0.5VCC
RD,WR
td(AH-RD)
td(AH-WR)
tv(RD-AH)
tv(WR-AH)
0.5VCC
AB15 to AB8
td(AL-RD)
td(AL-WR)
tv(RD-AL)
tv(WR-AL)
0.5VCC
AB7 to AB0
tsu(RDY-WR) th(WR-RDY)
tsu(RDY-RD)
th(RD-RDY)
0.8VCC
0.2VCC
RDY
tSU(DB-RD)
<CPU read>
th(RD-DB)
0.8VCC
0.2VCC
DB0 to DB7
td(WR-DB)
<CPUwrite>
DB0 to DB7
tv(WR-DB)
0.5VCC
tv(WR-EDMA)
tv(RD-EDMA)
0.5VCC
EDMA
Fig. 87 Timing diagram (7); Memory expansion and microprocessor modes
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7641 Group
FLASH MEMORY MODE
Summary
The M37641F8FP/HP (flash memory version) has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 5 V, and 2 power sources
when VPP is 5 V and VCC is 3.3 V in the CPU rewrite and standard
serial I/O modes.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Table 25 lists the summary of the M37641F8 (flash memory version).
This flash memory version has some blocks on the flash memory
as shown in Figure 88 and each block can be erased. The flash
memory is divided into User ROM area and Boot ROM area.
In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O
mode.
Table 25 Summary of M37641F8 (flash memory version)
Item
Power source voltage (For Program/Erase)
VPP voltage (For Program/Erase)
Flash memory mode
Specifications
Vcc = 3.00 – 3.60 V, 4.50 – 5.25 V (f(XIN) = 24 MHz, φ = 6 MHz) (Note 1)
VPP = 4.50 – 5.25 V
3 modes; Flash memory can be manipulated as follows:
(1) CPU rewrite mode: Manipulated by the Central Processing Unit (CPU)
(2) Parallel I/O mode: Manipulated using an external programmer (Note 2)
(3) Standard serial I/O mode: Manipulated using an external programmer (Note 2).
Erase block division
User ROM area
Boot ROM area
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
ROM code protection
See Figure 79.
1 block (4 Kbytes) (Note 3)
Byte program
Batch erasing/Block erasing
Program/Erase control by software command
6 commands
100 times
Available in parallel I/O mode and standard serial I/O mode
Notes 1: After programming/erasing at Vcc = 3.0 to 3.6 V, the MCU can operate only at Vcc = 3.0 to 3.6 V.
After programming/erasing at Vcc = 4.5 to 5.25 V or programming/erasing with the exclusive external equipment flash programmer, the MCU can
operate at both Vcc = 3.0 to 3.6 V and 4.15 to 5.25 V.
2: In the parallel I/O mode or the standard serial I/O mode, use the exclusive external equipment flash programmer which supports the 7641 Group
(flash memory version).
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be
rewritten in only parallel I/O mode.
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7641 Group
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Processing Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure 88
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area to be
executed before it can be executed.
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.)
See Figure 88 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNV SS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P36 (CE) pin high,
the P81 (SCLK) pin high, the CNVSS pin high, the CPU starts operating using the control program in the Boot ROM area. This mode
is called the “Boot” mode.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
Parallel I/O mode
User ROM area
800016
C00016
E00016
FFFF16
Block 2 : 16 Kbytes
Block 1 : 8 Kbytes
Block 0 : 8 Kbytes
Boot ROM area
F00016
FFFF16
BSEL = “L”
4 Kbytes
BSEL = “H”
CPU rewrite mode, standard serial I/O mode
User ROM area
800016
C00016
E00016
FFFF16
Block 2 : 16 Kbytes
Block 1 : 8 Kbytes
Block 0 : 8 Kbytes
User area / Boot area select bit = “0”
Boot ROM area
F00016
FFFF16
4 Kbytes
User area / Boot area select bit = “1”
Notes 1: The Boot ROM area can be rewritten in only parallel I/O mode. (Access to any other
areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 88 Block diagram of built-in flash memory
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7641 Group
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip, memory expansion
or Boot mode. The only User ROM area can be rewritten in CPU
rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory by executing software commands. This
rewrite control program must be transferred to a memory such as
the internal RAM before it can be executed.
The MCU enters CPU rewrite mode by applying 4.50 V to 5.25 V
to the CNVSS pin and setting “1” to the CPU Rewrite Mode Select
Bit (bit 1 of address 006A16). Software commands are accepted
once the mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 89 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
b7
CPU becomes unable to access the internal flash memory directly.
Therefore, use the control program in a memory other than internal flash memory for write to bit 1. To set this bit to “1”, it is
necessary to write “0” and then write “1” in succession. The bit can
be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” automatically. Reprogramming of this bit must be in a memory other
than internal flash memory.
Figure 90 shows a flowchart for setting/releasing CPU rewrite
mode.
b0
Flash memory control register (address 006A16)
FMCR
RY/BY status flag
0: Busy (being programmed or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area / Boot ROM area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (Indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig. 89 Structure of flash memory control register
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7641 Group
Start
Single-chip mode, Memory expansion mode or
Boot mode
Set CPU mode registers A, B (Note 2)
Transfer CPU rewrite mode control program to
memory other than internal flash memory
Jump to control program transferred in memory
other than internal flash memory
(Subsequent operations are executed by control
program in this memory)
Setting
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Released
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode or memory expansion mode, supply
4.5 V to 5.25 V to the CNVss pin until checking the CPU rewrite mode entry flag.
2: Set the main clock as follows depending on the XIN divider select bit of clock control
register (bit 7 of address 001F16):
When XIN divider select bit = “0” (φ = f(XIN)/4), the main clock is 24 MHz or less
When XIN divider select bit = “1” (φ = f(XIN)/2), the main clock is 12 MHz or less.
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 90 CPU rewrite mode set/release flowchart
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7641 Group
Notes on CPU Rewrite Mode
The below notes applies when rewriting the flash memory in CPU
rewrite mode.
●Operation speed
During CPU rewrite mode, set the internal clock φ to 6 MHz or less
using the XIN Divider Select Bit (bit 7 of address 001F16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Reset
Reset is always valid. When CNVSS is “H” at reset release, the
program starts from the address stored in addresses FFFA16 and
FFFB16 of the boot ROM area in order that CPU may start in boot
mode.
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7641 Group
Software Commands (CPU Rewrite Mode)
Table 26 lists the software commands.
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
●Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified address are read out at the data bus (DB0 to DB7).
The read array mode is retained intact until another command is
written.
register mode is entered automatically and the contents of the status register is read at the data bus (DB 0 to DB 7 ). The status
register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains active until the next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status register bit 7.
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
Start
●Read Status Register Command (7016)
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status register are read out at the data bus (DB0 to DB7 ) by a read in the
second bus cycle.
The status register is explained in the next section.
Write 4016
Write Write address
Write data
Status register
read
●Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
or
RY/BY = 1 ?
●Program Command (4016)
Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data programming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
NO
YES
NO
SR4 = 0 ?
Program
error
YES
Program
completed
Fig. 91 Program flowchart
Table 26 List of software commands (CPU rewrite mode)
Command
Cycle number
Mode
Read array
1
Write
Read status register
2
Clear status register
First bus cycle
Data
Address (DB0 to DB7)
X
Second bus cycle
Data
Mode
Address
(DB0 to DB7)
(Note 4)
FF16
Write
X
7016
1
Write
X
5016
Program
2
Write
X
4016
Write
WA (Note 2)
WD (Note 2)
Erase all blocks
2
Write
X
2016
Write
X
2016
Block erase
2
Write
X
2016
Write
(Note 3)
D016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
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REJ03B0191-0400
page 107 of 135
Read
X
BA
SRD (Note 1)
7641 Group
●Erase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Whether the erase all blocks command is terminated can be con____
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(DB0 to DB7). The status register bit 7 (SR7) is set to “0” at the
same time the erase operation starts and is returned to “1” upon
completion of the erase operation. In this case, the read status
register mode remains active until another command is written.
____
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7
(SR7).
After the erase all blocks end, erase results can be checked by
reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
●Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the blobk address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is written.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register bit 7.
After the block erase ends, erase results can be checked by reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 108 of 135
Start
Write 2016
Write
2016/D016
Block address
2016:Erase all blocks command
D016:Block erase command
Status register
read
SR7 = 1 ?
or
RY/BY = 1 ?
NO
YES
SR5 = 0 ?
YES
Erase completed
Fig. 92 Erase flowchart
NO
Erase error
7641 Group
Status Register (SRD)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 27 shows the status register. Each bit in this register is explained below.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status register command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 27 Definition of each bit in status register (SRD)
Symbol
Status name
SR7 (bit7)
Sequencer status
SR6 (bit6)
SR5 (bit5)
Reserved
Erase status
SR4 (bit4)
SR3 (bit3)
Program status
Reserved
SR2 (bit2)
SR1 (bit1)
Reserved
Reserved
SR0 (bit0)
Reserved
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REJ03B0191-0400
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Definition
“1”
“0”
Ready
-
Busy
-
Terminated in error
Terminated in error
Terminated normally
Terminated normally
-
-
-
-
7641 Group
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 93 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the read aray, the program, erase
all blocks, and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 93 Full status check flowchart and remedial procedure for errors
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REJ03B0191-0400
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7641 Group
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode.
●ROM Code Protect Function (in Pararell I/O Mode)
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFC916 ) in parallel I/O
mode. Figure 94 shows the ROM code protect control (address
FFC916). (This address exists in the User ROM area.)
If one or both of the pair of ROM Code Protect Bits is set to “0”,
b7
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Protect Reset Bits.
b0
1 1 ROM code protect control (address FFC916) (Note 1)
ROMCP
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 4)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: This area is on the ROM in the mask ROM version.
2: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
Fig. 94 Structure of ROM code protect control
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
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7641 Group
ID Code Check Function (in Standard serial
I/O mode)
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFC216 to FFC816. Write a program
which has had the ID code preset at these addresses to the flash
memory.
Address
FFC216
ID1
FFC316
ID2
FFC416
ID3
FFC516
ID4
FFC616
ID5
FFC716
ID6
FFC816
ID7
FFC916
ROM code protect control
Interrupt vector area
Fig. 95 ID code store addresses
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7641 Group
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input software command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the exclusive external equipment flash programmer which supports the
7641 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 88 can be rewritten. Both areas of flash memory can be operated on
in the same way.
Program and block erase operations can be performed in the user ROM
area. The user ROM area and its block is shown in Figure 88.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial I/O
mode control program stored in it when shipped from the Mitsubishi
factory. Therefore, using the device in standard serial I/O mode, you
do not need to write to the boot ROM area.
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REJ03B0191-0400
page 113 of 135
7641 Group
(3) Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires the exclusive external
equipment (flash programmer).
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the P36 (CE) pin
and “H” to the P81 (SCLK) pin and “H” to the CNVSS pin (apply 4.5
V to 5.25 V to Vpp from an external source), and releasing the reset operation. (In the ordinary microcomputer mode, set CNVss
pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Mitsubishi. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. Figures 96 and 97
show the pin connections for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK, SRXD, STXD and SRDY (BUSY). The SCLK pin is the
transfer clock input pin through which an external transfer clock is
input. The STXD pin is for CMOS output. The SRDY (BUSY) pin
outputs “L” level when ready for reception and “H” level when reception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 88 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 114 of 135
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(flash programer, etc.) using 4-wire clock-synchronized serial I/O.
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK pin, and are then input to the MCU via the SRXD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the STXD pin.
The STXD pin is for CMOS output. Transfer is in 8-bit units with
LSB first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY (BUSY) pin is “H” level. Accordingly,
always start the next transfer after the SRDY (BUSY) pin is “L”
level.
Also, data and status registers in a memory can be read after inputting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
7641 Group
Table 28 Description of pin function (Standard Serial I/O Mode)
Pin name
Signal name
I/O
Function
VCC,VSS
Power supply input
Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to
the VCC pin. Apply 0 V to the Vss pin.
CNVSS
CNVSS
I
This controls the MCU operating mode. Connect this pin to VPP (= 4.50 V –
5.25 V
RESET
Reset input
I
To reset, input “L” level for 20 cycles or longer clocks of φ.
X IN
Clock input
XOUT
Clock output
AVCC, AVSS
Analog power supply input
LPF
LPF
Ext.Cap
3.3 V line power supply input
USB D+
USB D+
I/O
USB D+ signal port. When this pin is not used, input “H” level.
USB D-
USB D-
I/O
USB D- signal port. When this pin is not used, input “L” level.
P00 to P07
I/O port P0
I/O
P10 to P17
I/O port P1
I/O
When these ports are not used, input “L” or “H” level, or leave them open in
output mode.
P20 to P27
I/O port P2
I/O
P30 to P35, P37 I/O port P3
I/O
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When inputting an externally derived clock, input it from XIN and leave
XOUT open.
Apply 4.50 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to
the AVCC pin. Apply 0 V to the AVss pin.
O
Loop filter for the frequency synthesizer. When this pin is not used, leave
this open.
I
Power supply input pin for 3.3 V USB line driver. When this pin is not used,
input “H” level.
P36
CE input
P40 to P44
I/O port P4
I/O
P50 to P57
I/O port P5
I/O
P60 to P67
I/O port P6
I/O
P70 to P74
I/O port P7
I/O
P80
BUSY output
O
This is a BUSY output pin.
P81
SCLK input
I
This is a serial clock input pin.
P 82
SRXD input
I
This is a serial data input pin.
P83
STXDoutput
O
This is a serial data output pin.
P84 to P87
I/O port P8
I/O
When these ports are not used, input “L” or “H” level, or leave them open in
output mode.
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I
page 115 of 135
Input “H” level.
When these ports are not used, input “L” or “H” level, or leave them open in
output mode.
41
43
42
47
46
45
44
50
49
48
57
56
55
54
53
52
51
65
40
66
67
68
39
38
37
36
35
34
69
70
71
72
33
32
M37641F8FP
73
74
31
75
76
77
78
30
29
28
27
26
79
80
P30/RDY
P31
P32
P33/DMAOUT
P34/φOUT
P35/SYNCOUT
P36/WR
P37/RD
P80/UTXD2/SRDY
P81/URXD2/SCLK
P82/CTS2/SRXD
P83/RTS2/STXD
P84/UTXD1
P85/URXD1
P86/CTS1
P87/RTS1
CE
BUSY
SCLK
SRXD
STXD
24
21
22
23
19
20
18
17
15
16
12
13
14
8
9
10
11
7
5
6
3
4
25
1
2
P74/OBF1
P73/IBF1/HLDA
P72/S1
P71/HOLD
P70/SOF
USB D+
USB DExt.Cap
VSS
VCC
P67/DQ7
P66/DQ6
P65/DQ5
P64/DQ4
P63/DQ3
P62/DQ2
60
59
58
64
63
62
61
P20/DB0{DB0}
P21/DB1{DB1}
P22/DB2{DB2}
P23/DB3{DB3}
P24/DB4{DB4}
P25/DB5{DB5}
P26/DB6{DB6}
P27/DB7{DB7}
P00/AB0{AB0}
P01/AB1{AB1}
P02/AB2{AB2}
P03/AB3{AB3}
P04/AB4{AB4}
P05/AB5{AB5}
P06/AB6{AB6}
P07/AB7{AB7}
P10/AB8{AB8}
P11/AB9{AB9}
P12/AB10{AB10}
P13/AB11{AB11}
P14/AB12{AB12}
P15/AB13{AB13}
P16/AB14{AB14}
P17/AB15{AB15}
7641 Group
P61/DQ1
P60/DQ0
P57/W/(R/W)
P56/R(E)
P55/A0
P54/S0
P53/IBF0
P52/OBF0
CNVSS
RESET
P51/TOUT/XCOUT
P50/XCIN
VSS
XIN
XOUT
VCC
AVCC
LPF
AVSS
P44/CNTR1
P43/CNTR0
P42/INT1
P41/INT0
P40/EDMA
VSS
Mode setup method
Signal
Value
4.5 to 5.25 V
CNVSS
VCC (Note)
SCLK
VSS → VCC
RESET
VCC
CE
Note: It is necessary to apply Vcc only when reset is released.
RESET
VPP
Connect to oscillator circuit.
Package outline: PRQP0080GB-A
Fig. 96 Pin connection diagram in standard serial I/O mode (1)
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REJ03B0191-0400
page 116 of 135
VCC
41
44
43
42
47
46
45
51
50
49
48
61
40
62
39
38
37
63
64
65
36
35
66
34
33
32
67
68
69
M37641F8HP
70
71
31
30
29
28
72
73
27
26
25
24
23
74
75
76
77
78
79
22
21
Mode setup method
Signal
Value
4.5 to 5.25 V
CNVSS
VCC (Note)
SCLK
VP P
Connect to oscillator circuit.
VSS → VCC
VCC
RESET
RESET
CE
Note: It is necessary to apply Vcc only when reset is released.
Fig. 97 Pin connection diagram in standard serial I/O mode (2)
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CE
BUSY
SCLK
SRXD
STXD
19
20
18
14
15
16
17
8
9
10
11
12
13
P16/AB14{AD14}
P17/AB15{AD15}
P30/RDY
P31
P32
P33/DMAOUT
P34/φOUT
P35/SYNCOUT
P36/WR
P37/RD
P80/UTXD2/SRDY
P81/URXD2/SCLK
P82/CTS2/SRXD
P83/RTS2/STXD
P84/UTXD1
P85/URXD1
P86/CTS1
P87/RTS1
P40/EDMA
P41/INT0
P57/W/(R/W)
P56/R(E)
P55/A0
P54/S0
P53/IBF0
P52/OBF0
CNVSS
RESET
P51/TOUT/XCOUT
P50/XCIN
VSS
XIN
XOUT
VCC
AVCC
LPF
AVSS
P44/CNTR1
P43/CNTR0
P42/INT1
5
6
7
80
1
2
3
4
P21/DB1
P20/DB0
P74/OBF1
P73/IBF1/HLDA
P72/S1
P71/HOLD
P70/SOF
USB D+
USB DExt.Cap
VSS
VCC
P67/DQ7
P66/DQ6
P65/DQ5
P64/DQ4
P63/DQ3
P62/DQ2
P61/DQ1
P60/DQ0
59
58
57
56
55
54
53
52
60
P22/DB2{DB2}
P23/DB3{DB3}
P24/DB4{DB4}
P25/DB5{DB5}
P26/DB6{DB6}
P27/DB7{DB7}
P00/AB0{AB0}
P01/AB1{AB1}
P02/AB2{AB2}
P03/AB3{AB3}
P04/AB4{AB4}
P05/AB5{AB5}
P06/AB6{AB6}
P07/AB7{AB7}
P10/AB8{AB8}
P11/AB9{AB9}
P12/AB10{AB10}
P13/AB11{AB11}
P14/AB12{AB12}
P15/AB13{AB13}
7641 Group
Package outline: PLQP0080KB-A
VSS
VCC
7641 Group
Software Commands (Standard Serial I/O
Mode)
commands via the SRXD pin. Software commands are explained
here below.
Table 29 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
Table 29 Software commands (Standard serial I/O mode)
Control command
1
Page read
2
Page program
3
Block erase
4
Erase all blocks
5
Read status register
6
Clear status register
7
ID code check
1st byte
transfer
2nd byte
3rd byte
4th byte
5th byte
6th byte
.....
When ID is
not verified
FF16
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
Not
acceptable
4116
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
Data
output to
259th byte
Data input
to 259th
byte
2016
Address
(middle)
Address
(high)
D016
A716
D016
7016
SRD
output
Not
acceptable
Not
acceptable
SRD1
output
Acceptable
5016
F516
FA16
8
Download function
9
Version data output function
10
Boot ROM area output
function
FB16
FC16
Not
acceptable
Not
acceptable
Address
(low)
Size
(low)
Address
(middle)
Size
(high)
Address
(high)
Checksum
ID size
ID1
Data
input
To
required
number
of times
Version
data
output
Address
(middle)
Version
data
output
Address
(high)
Version
data
output
Data
output
Version
data
output
Data
output
Version
data
output
Data
output
To ID7
Acceptable
Not
acceptable
Version
data output
to 9th byte
Data
output to
259th byte
Acceptable
Not
acceptable
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment
(programmer) to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted for the products of which boot ROM area is totally blank.
4: Address low is AB0 to AB7; Address middle is AB8 to AB15; Address high is AB16 to AB23.
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7641 Group
●Page Read Command
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, data (DB0 to DB7) for the page (256
bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
SCLK
SRXD
FF16
AB8 to AB16 to
AB15
AB23
STXD
data0
SRDY (BUSY)
Fig. 98 Timing for page read
●Read Status Register Command
This command reads status information. When the “70 16” command code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
SCLK
SRXD
STXD
SRDY (BUSY)
Fig. 99 Timing for reading status register
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7016
SRD
output
SRD1
output
data255
7641 Group
●Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when
the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY
(BUSY) signal changes from “H” to “L” level.
SCLK
SRXD
5016
STXD
SRDY (BUSY)
Fig. 100 Timing for clear status register
●Page Program Command
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, as write data (DB0 to DB7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the SRDY
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
SCLK
SRXD
4116 AB8 to AB16 to data0
AB15 AB23
STXD
SRDY (BUSY)
Fig. 101 Timing for page program
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data255
7641 Group
●Block Erase Command
This command erases the contents of the specifided block. Execute the block erase command as explained here following.
(1) Transfer the “2016” command code with the 1st byte.
(2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd
and 3rd bytes respectively.
(3) Transfer the verify command code “D0 16” with the 4th byte.
With the verify command code, the erase operation will start
for the specifided block in the flash memory. Set the addresses
AB8 to AB23 to the maximum address of the specified block.
When block erasing ends, the SRDY (BUSY) signal changes from
“H” to “L” level. The result of the erase operation can be known by
reading the status register.
For more information, see the section on the status register.
SCLK
SRXD
2016
AB8 to
AB15
AB16 to
AB23
D016
STXD
SRDY(BUSY)
Fig. 102 Timing for block erasing
●Erase All Blocks Command
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D0 16” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
When erase all blocks end, the SRDY (BUSY) signal changes
from “H” to “L” level. The result of the erase operation can be
known by reading the status register.
SCLK
SRXD
STXD
SRDY (BUSY)
Fig. 103 Timing for erase all blocks
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A716
D016
7641 Group
●Download Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
SCLK
SRXD
FA16
STXD
SRDY (BUSY)
Fig. 104 Timing for download
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Data size Data size
(low)
(high)
Check
su m
Program
data
Program
data
7641 Group
●Version Information Output Command
This command outputs the version information of the control program stored in the Boot ROM area. Execute the version
information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward.
This data is composed of 8 ASCII code characters.
SCLK
SRXD
FB16
STXD
‘V’
‘E’
‘R’
‘X’
SRDY (BUSY)
Fig. 105 Timing for version information output
●Boot ROM Area Output Command
This command reads the control program stored in the Boot ROM
area in page (256 bytes) unit. Execute the Boot ROM area output
command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses AB8 to AB15 and AB16 to AB23 with the 2nd
and 3rd bytes respectively.
(3) From the 4th byte onward, data (DB0 to DB7) for the page (256
bytes) specified with addresses AB8 to AB23 will be output sequentially from the smallest address first synchronized with the
fall of the clock.
SCLK
SRXD
STXD
SRDY(BUSY)
Fig. 106 Timing for Boot ROM area output
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FC16
A B 8 to
A B 15
AB 1 6 to
A B 23
data0
data255
7641 Group
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses AB0 to AB7, AB8 to AB15 and AB16 to AB23
(“0016”) of the 1st byte of the ID code with the 2nd and 3rd respectively.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
●ID Code Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
SCLK
SRXD
F516
C216
FF16
0016
ID size
STXD
SRDY (BUSY)
Fig. 107 Timing for ID check
●ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFC216 to FFC816. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFC216
ID1
FFC316
ID2
FFC416
ID3
FFC516
ID4
FFC616
ID5
FFC716
ID6
FFC816
ID7
FFC916
ROM code protect control
Interrupt vector area
Fig. 108 ID code storage addresses
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ID1
ID7
7641 Group
●Status Register (SRD)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (70 16 ). Also, the status register is
cleared by writing the clear status register command (5016).
Table 30 lists the definition of each status register bit. After releasing the reset, the status register becomes “8016”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the the
flash memory.
After power-on and recover from deep power down mode, the sequencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation. If a program error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 30 Definition of each bit of status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
Ready
Busy
Reserved
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
SR3 (bit3)
Program status
Reserved
Terminated in error
-
Terminated normally
-
SR2 (bit2)
SR1 (bit1)
Reserved
Reserved
-
-
SR0 (bit0)
Reserved
-
-
SR7 (bit7)
Sequencer status
SR6 (bit6)
SR5 (bit5)
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7641 Group
●Status Register 1 (SRD1)
The status register 1 indicates the status of serial communications, results from ID checks and results from check sum
comparisons. It can be read after the status register (SRD) by writing the read status register command (7016). Also, status register
1 is cleared by writing the clear status register command (5016).
Table 31 lists the definition of each status register 1 bit. This register becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download function.
•ID code check completed bits (SR11 and SR10)
These flags indicate the result of ID code checks. Some commands cannot be accepted without an ID code check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the received data is discarded and the MCU returns to the command
wait state.
Table 31 Definition of each bit of status register 1 (SRD1)
SRD1 bits
SR15 (bit7)
SR14 (bit6)
Boot update completed bit
Reserved
SR13 (bit5)
SR12 (bit4)
Reserved
Checksum match bit
SR11 (bit3)
SR10 (bit2)
ID code check completed bits
SR9 (bit1)
SR8 (bit0)
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Definition
Status name
Data reception time out
Reserved
page 126 of 135
“1”
“0”
Update completed
-
Not Update
-
Match
00
01
Not verified
Verification mismatch
10
11
Reserved
Verified
Time out
-
Mismatch
Normal operation
-
7641 Group
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 109 shows a flowchart of the full status check and explains how to remedy errors
which occur.
Read status register
SR4 = 1 and
SR5 = 1 ?
YES
Command
sequence error
NO
SR5 = 0 ?
NO
Erase error
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
YES
SR4 = 0 ?
NO
Program error
Should a program error occur, the block in error
cannot be used.
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the page read, program, erase all
blocks, and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 109 Full status check flowchart and remedial procedure for errors
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7641 Group
Example Circuit Application for Standard
Serial I/O Mode
Figure 110 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
Clock input
SCLK
BUSY output
SRDY (BUSY)
Data input
SRXD
Data output
STXD
VPP power
source input
CNVss
P36/WR (CE)
M37641F8
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the Vpp power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.25 V.
Fig. 110 Example circuit application for standard serial I/O mode
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7641 Group
NOTES ON PROGRAMMING
Processor Status Register
•The contents of the processor status register (PS) after a reset
are undefined, except for the interrupt disable flag (I) which is “1”.
After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
•To reference the contents of the processor status register (PS),
execute the PHP instruction once then read the contents of
(S+1). If necessary, execute the PLP instruction to return the PS
to its original status.
A NOP instruction must be executed after every PLP instruction.
•A SEI instruction must be executed before every PLP instruction.
A NOP instruction must be executed before every CLI instruction.
BRK Instruction
It can be detected that the BRK instruction interrupt event or the
least priority interrupt event by referring the stored B flag state.
Refer to the stored B flag state in the interrupt routine.
Ports
•When the data register (port latch) of an I/O port is modified with
the bit managing instruction (SEB, CLB instructions) the value of
the unspecified bit may be changed.
•In standby state (the stop mode by executing the STP instruction,
and the wait mode by executing the WIT instruction) for lowpower dissipation, do not make input levels of an I/O port
“undefined”, especially for I/O ports of the P-channel and the Nchannel open-drain.
Pull-up (connect the port to Vcc) or pull-down (connect the port to
Vss) these ports through a resistor.
When determining a resistance value, note the following points:
(1) External circuit
(2) Variation of output levels during the ordinary operation
When using built-in pull-up or pull-down resistor, note on varied
current values.
(1) When setting as an input port : Fix its input level
(2) When setting as an output port : Prevent current from flowing
out to external
Decimal Calculations
Serial I/O
When decimal mode is selected, the values of the V flags are invalid.
The carry flag (C) is set to “1” if a carry is generated as a result of
the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag
must be initialized to “0” before each calculation. To check for a
borrow, the C flag must be initialized to “1” before each calculation.
Do not write to the serial I/O shift register during a transfer when in
SPI compatible mode.
UART
•The all error flags PER, FER, OER and SER are cleared to “0”
when the UARTx status register is read, at the hardware reset or
initialization by setting the Transmit Initialization Bit. These flags
are also cleared to “0” by execution of bit test instructions such as
BBC and BCS.
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Timers
•If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
•P51/XCOUT/TOUT pin cannot function as an I/O port when XCIN XCOUT is oscillating. When XCIN - XCOUT oscillation is not used or
XCOUT oscillation drive is disabled, this pin can function as the
TOUT output pin of the timer 1 or 2.
When using the TOUT output function and f(XCIN) divided by 2 is
used as the timer 1 count source (bit 2 of T123M = “1”), disable
XCOUT oscillation drive (bit 5 of CCR = “1”).
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•The transmission interrupt request bit is set and the interrupt request is generated by setting the transmit enable bit to “1” even
when selecting timing that either of the following flags is set to “1”
as timing where the transmission interrupt is generated:
(1) Transmit buffer empty flag is set to “1”
(2) Transmit complete flag is set to “1”.
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as the following sequence:
(1) Transmit enable bit is set to “1”
(2) Transmit interrupt request bit is set to “0”
(3) Transmit interrupt enable bit is set to “1”.
•Do not update a value of UARTx baud rate generator in the condition of transmission enabled or reception enabled. Disable
transmission and reception before updating the value. If the
former data remains in the UARTx transmit buffer registers 1 and
2 when transmission is enabled, an undefined data might be output.
•The receive buffer full interrupt request is not generated if receive
errors are detected at receiving.
7641 Group
•If a character bit length is 7 bits, bit 7 of the UARTx transmit/receive buffer register 1 and bits 0 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are invalid at receiving.
If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are invalid at receiving.
If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/
receive buffer register 2 are ignored at transmitting; they are “0”
at receiving.
•The IN_PKT_RDY Bit can be set by software even when using
the AUTO_SET function.
•When writing to USB-related registers, set the USB Clock Enable
Bit to “1”, then perform the write after four φ cycle waits.
•When using the MCU at Vcc = 3.3V, set the USB Line Driver Supply Enable Bit to “0” (line driver disable). Note that setting the
USB Line Driver Current Control Bit (USBC3) doesn’t affect the
USB operation.
•Read one packet data from the OUT FIFO before clearing the
OUT_PKT_RDY Flag. If the OUT_PKT_RDY Flag is cleared
while one packet data is being read, the internal read pointer cannot operate normally.
USB
•When the USB Reset Interrupt Status Flag is kept at “1”, all other
flags in the USB internal registers (addresses 005016 to 005F16)
will return to their reset status. However, the following registers
are not affected by the USB reset: USB control register (address
0013 16 ), Frequency synthesizer control register (address
006C16), Clock control register (address 001F16), and USB endpoint-x FIFO register (addresses 006016 to 006416).
•When not using the USB function, set the USB Line Driver Supply
Enable Bit of the USB control register (address 001316) to “1” for
power supply to the internal circuits (at Vcc = 5V).
•When using an isochronous transfer, set the FLUSH Bit (bit 6 of
address 005916 and bit 6 of address 005A16) as follows:
IN FIFO: use AUTO_FLUSH Bit (bit 6 of address 005816)
OUT FIFO: when OUT_PKT_RDY Bit is “1”, set FLUSH Bit to “1”
•When the USB SOF Port Select Bit is “1”, the reference pulse of
83.3 ns (φ = 12 MHz) is output from the P70 /SOF pin and synchronized with the SOF packet.
•Use the AUTO_FLUSH Bit (bit 6 of address 005816 ) in double
buffer mode.
•Use the transfer instructions such as LDA and STA to set the registers: USB interrupt status registers 1, 2 (addresses 005216,
005316); USB endpoint 0 IN control register (address 0059 16 );
USB endpoint x IN control register (address 005916); USB endpoint x OUT control register (address 005A16). Do not use the
read-modify-write instructions such as the SEB or the CLB instruction.
When writing to bits shown by Table 32 using the transfer instruction such as LDA or STA, a value which never affect its bit state
is required. Take the following sequence to change these bits
contents:
(1) Store the register contents onto a variable or a data register.
(2) Change the target bit on the variable or the data register. Simultaneously mask the bit so that its bit state cannot be
changed. (See to Table 39.)
(3) Write the value from the variable or the data register to the
register using the transfer instruction such as LDA or STA.
•To use the AUTO_SET function for an IN transfer when the
AUTO_SET bit is set to 1, set the FIFO to single buffer mode.
Table 32 Bits of which state might be changed owing to software write
Bit name
Register name
IN_PKT_RDY (b1)
USB endpoint 0 IN control register
DATA_END (b3)
FORCE_STALL (b4)
USB endpoint x (x = 1 to 4) IN control register
IN_PKT_RDY (b0)
UNDER_RUN (b1)
USB endpoint x (x = 1 to 4) OUT control register
OUT_PKT_RDY (b0)
OVER_RUN (b1)
FORCE_STALL (b4)
DATA_ERR (b5)
Value not affecting state (Note)
“0”
“0”
“1”
“0”
“1”
“1”
“1”
“1”
“1”
Note: Writing this value will not change the bit state, because this value cannot be written to the bit by software.
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7641 Group
Frequency Synthesizer
•The frequency synthesizer and DC-DC converter must be set up
as follows when recovering from a Hardware Reset:
(1) Enable the frequency synthesizer after setting the frequency
synthesizer related registers (addresses 006C16 to 006F16).
Then wait for 2 ms.
(2) Check the Frequency Synthesizer Lock Status Bit. If “0”, wait
for 0.1 ms and then recheck.
(3) When using the USB built-in DC-DC converter, set the USB
Line Driver Supply Enable Bit of the USB control register to
“1”. This setting must be done 2 ms or more after the setup
described in step (1). The USB Line Driver Current Control Bit
must be set to “0” at this time. (When Vcc = 3.3V, the setting
explained in this step is not necessary.)
(4) After waiting for (C + 1) ms so that the external capacitance
pin (Ext. Cap. pin) can reach approximately 3.3 V, set the
USB Clock Enable Bit to “1”. At this time, “C” equals the capacitance (µ F) of the capacitor connected to the Ext. Cap.
pin. For example, if 2.2 µF and 0.1 µF capacitors are connected to the Ext. Cap. in parallel, the required wait will be
(2.3 + 1) ms.
(5) After enabling the USB clock, wait for 4 or more φ cycles, and
then set the USB Enable Bit to “1”.
•Bits 6 and 5 of the frequency synthesizer control register (address 006C16) are initialized to “11” after reset release. Make
sure to set bits 6 and 5 to “10” after the Frequency Synthesizer
Lock Status Bit goes to “1”.
•When setting the DMAC channel x enable bit (bit 7 of address
004116) to “1”, be sure simultaneously to set the DMAC channel x
transfer initiation source capture register reset bit (bit 6 of address 004116) to “1”. If this is not performed, an incorrect data will
be transferred at the same time when the DMAC is enabled.
Memory Expansion Mode & Microprocessor
Mode
•In both memory expansion mode and microprocessor mode, use
the LDM instruction or STA instruction to write to port P3 (address
000E16). When using the Read-Modify-Write instruction (SEB instruction, CLB instruction) you will need to map a memory that
the CPU can read from and write to.
•In the memory expansion mode, if the internal and external
memory areas overlap, the internal memory becomes the valid
memory for the overlapping area. When the CPU performs a read
or a write operation on this overlapped area, the following things
happen:
(1) Read
The CPU reads out the data in the internal memory instead of
in the external memory. Note that, since the CPU will output a
proper read signal, address signal, etc., the memory data at
the respective address will appear on the external data bus.
(2) Write
The CPU writes data to both the internal and external memories.
•The wait function is serviceable at accessing an external memory.
•When using the frequency synthesized clock function, we recommend using the fastest frequency possible of f(XIN) or f(XCIN) as
an input clock for the PLL. Owing to the PLL mechanism, the PLL
controls the speed of multiplied clocks from the source clock. As
a result, when the source clock input is lower, the generated clock
becomes less stable. This is because more multipliers are
needed and the speed control is very rough. Higher source clock
input generates a stabler clock, as less multipliers are needed
and the speed control is more accurate. However, if the input
clock frequency is relatively high, the PLL clock generator can
quickly lock-up the output clock to the source and make the output clock very stable.
•Set the value of frequency synthesizer multiply register 2 (FSM2)
so that the fPIN is 1 MHZ or higher.
DMA
•In the memory expansion mode and microprocessor mode, the
DMAOUT pin outputs “H” during a DMA transfer.
•Do not access the DMAC-related registers by using a DMAC
transfer. The destination address data and the source address
data will collide in the DMAC internal bus.
•When using the USB FIFO as the DMA transfer source, make
sure that, if you use the AUTO_SET function, short packet data
does not get mixed in with the transfer data.
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Stop Mode
•When the STP instruction is executed, bit 7 of the clock control
register (address 001F16) goes to “0”. To return from stop mode,
reset CCR7 to “1”.
•When using fSYN (set Internal System Clock Select Bit (CPMA6)
to “1”) as the internal system clock, switch CPMA6 to “0” before
executing the STP instruction. Reset CPMA6 after the system returns from Stop Mode and the frequency synthesizer has
stabilized.
CPMA6 does not need to be switched to “0” when using the WIT
instruction.
•When the STP instruction is being executed, all bits except bit 4
of the timer 123 mode register (address 002916) are initialized to
“0”. It is not necessary to set T123M1 (Timer 1 Count Stop Bit) to
“0” before executing the STP instruction. After returning from Stop
Mode, reset the timer 1 (address 0024 16 ), timer 2 (address
002516), and the timer 123 mode register (address 002916).
7641 Group
USAGE NOTES
Oscillator Connection Notice
AVss and AVcc Pin Treatment Notice (Noise
Elimination)
The built-in feedback register (1 MΩ) and the dumping resistor
(400 Ω) is internally connected between pins XIN and XOUT.
An insulation connector (Ferrite Beads) must be connected between AVss and Vss pins and between AVcc and Vcc pins.
Power Source Voltage
U S B Tr a n s c e i v e r Tr e a t m e n t ( N o i s e
Elimination)
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Power Supply Pins Treatment Notice
Please connect 0.1 µF and 4.7 µF capacitors in parallel between
pins Vcc and Vss, and pins AVss and AVcc.
These capacitors must be connected as close as possible between the DC supply and GND pins, and also the analog supply
pin and corresponding GND pin.
Wiring patterns for these supply and GND pins must be wider than
other signal patterns.
These filter capacitors should not be placed near the LPF pins as
they will cause noise problems
•The Full-Speed USB2.0 specification requires a driver -impedance 28 to 44 Ω. (Refer to Clause 7.1.1.1 Full-speed (12 Mb/s)
Driver Characteristics in the USB specification.) In order to meet
the USB specification impedance requirements, connect a resistor (27 Ω to 33 Ω recommended) in series to the USB D+ pin and
the USB D- pin.
In addition, in order to reduce the ringing and control the falling/
rising timing of USB D+/D- and a crossover point, connect a capacitor between the USB D+/D- pins and the Vss pin if necessary.
The values and structure of those peripheral elements depend on
the impedance characteristics and the layout of the printed circuit
board. Accordingly, evaluate your system and observe waveforms
before actual use and decide use of elements and the values of
resistors and capacitors.
•Connect a capacitor between the Ext. Cap. pin and the Vss pin.
The capacitor should have a 2.2 µF capacitor (Tantalum capacitor) and a 0.1 µF capacitor (ceramic capacitor) connected in
parallel. Figure 112 for the proper positions of the peripheral components.
R e s e t P i n Tr e a t m e n t N o t i c e ( N o i s e
Elimination)
Please note the following two issues for this capacitor connection.
(1) Capacitor wiring pattern must be as short as possible (within
20 mm).
(2) The user must perform an application level operation test.
FSE
LS
USBC5
DC-DC converter
enable
enable
USBC4
USB Clock
(48 MHz)
USB FCU
enable
USB
transceiver
current
mode
USBC3
Note 1
Ext. Cap.
0.1 µF
lock
1.5 kΩ
Frequency Synthesizer
enable
D+
enable
USBC7
DUSBC7
Note 2
Notes 1: In Vcc = 3.3 V, connect to Vcc. In Vcc =5 V, do not connect the external DC-DC
converter to the Ext. Cap pin.
2: The resistors values depend on the layout of the printed circuit board.
LPF Pin Treatment Notice
All passive components must be located as close as possible to
the LPF pin.
LPF pin
680 pF
1 kΩ
0.1 µF
AVSS pin
Fig. 111 Passive components near LPF pin
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
XIN
2.2 µF
If the reset input signal rises very slowly, we recommend attaching
a capacitor, such as a 1000 pF ceramic capacitor with excellent
high frequency characteristics, between the RESET pin and the
Vss pin.
page 132 of 135
Fig.112 Peripheral circuit
•In Vcc = 3.3 V operation, connect the Ext. Cap. pin directly to the
Vcc pin in order to supply power to the USB transceiver. In addition, you will need to disable the DC-DC converter in this
operation (set bit 4 of the USB control register to “0”.) If you are
using the bus powered supply in Vcc = 3.3 V operation, the DCDC converter must be placed outside the MCU.
•In Vcc = 5 V operation, do not connect the external DC-DC converter to the Ext. Cap. pin. Use the built-in DC-DC converter by
enabling the USB line driver.
•Make sure the USB D+/D- lines do not cross any other wires.
Keep a large GND area to protect the USB lines. Also, make sure
you use a USB specification compliant connecter for the connection.
7641 Group
USB Communication
In applications requiring high-reliability, we recommend providing
the system with protective measures such as USB function initialization by software or USB reset by the host to prevent USB
communication from being terminated unexpectedly, for example
due to external causes such as noise.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program periodically to increase the reliability of program.
• At the termination of unused pins, perform wiring at the shortest
possible distance (20 mm or less) from microcomputer pins.
Clock Input/Output Pin Wiring (Noise
Elimination)
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MCUs
(1) Make the wiring for the input/output pins as short as possible.
(2) Make the wiring across the grounding lead of the capacitor
which is connected to an oscillator and the Vss pin of the MCU
as short as possible (within 20 mm)
(3) Make sure to isolate the oscillation Vss pattern from other patterns for oscillation circuit-use only.
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
Flash Memory version MCUs due to the difference in the manufacturing processes.
When manufacturing an application system with the Flash
Memory version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
Oscillator Wiring (Noise Elimination)
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines, including USB signal lines, where a current larger than the tolerance of current value flows. When a large
current flows through those signal lines, strong noise occurs because of mutual inductance.
(2) Installing oscillator away from signal lines where potential
levels change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also, do
not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
Terminate Unused Pins
(1) Output ports : Open
(2) Input ports :
Connect each pin to Vcc or Vss through each resistor of 1 kΩ to
10 kΩ.
Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. As for pins whose potential affects
to operation modes such as pins CNVss, INT or others, select the
Vcc pin or the Vss pin according to their operation mode.
(3) I/O ports :
• Set the I/O ports for the input mode and connect them to Vcc or
Vss through each resistor of 1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up or pull-down resistor can also use this resistor. Set the I/O ports for the output
mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the
initial status remains until the mode of the ports is switched over
to the output mode by the program after reset. Thus, the potential
at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the
system, thoroughly perform system evaluation on the user side.
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 133 of 135
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
For the mask ROM confirmation and the mark specifications, refer
to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com).
7641 Group
PACKAGE OUTLINE
PRQP0080GB-A
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
PRQP0080GB-A
Previous Code
80P6N-A
MASS[Typ.]
1.6g
HD
*1
D
64
41
65
HE
*
*2"
*
INCLUDE TRIM OFFSET.
ZE
*2
E
NOTE)
1.
Dimension in Millimeters
80
Symbol
25
1
ZD
24
D
E
A2
c
Index mark
D
F
A
A2
HE
A
A1
bp
c
*3
y
bp
L
A1
e
Detail F
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 134 of 135
y
ZD
ZE
L
Min Nom Max
19.8
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
0.1 0.2
0
0.3 0.35
0.13 0.15 0.2
0°
10°
0.65 0.8
0.10
0.8
1.0
0.4 0.6 0.8
7641 Group
PLQP0080KB-A
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
MASS[Typ.]
0.5g
HD
*1
D
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
0
2.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
E
*2
HE
c1
1
Reference
Symbol
Terminal cross section
ZE
D
E
A
HD
E
20
A1
F
c
A1
A
A2
p
L
L1
Detail F
Rev.4.00 Aug 28, 2006
REJ03B0191-0400
page 135 of 135
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
REVISION HISTORY
Rev.
7641 GROUP DATA SHEET
Date
Description
Summary
Page
1.0
04/06/2001
First edition
2.0
05/17/2001 Page 1
Page 104
Page 105
Page 145
3.0
12/27/2001 Page 1
Page 4
Page 6
Page 11
Page 22
Page 31
Page 38
Page 39
Page 42
3.1
3/26/2002 Page 1
4.0
8/28/2006 All pages Package names “80P6N-A” → “PRQP0080GB-A” revised
Package names “80P6Q-A” → “PLQP0080KB-A” revised
All pages “USB std. spec. ver.1.1” → “Full-Speed USB2.0 specification”
38
DMAC; “(DxCEN)” → “(DxHR)”
Notes 2 are added.
Fig.89 is revised: Explanation of bits 5 to 7 and Notes.
Fig.90 is revised: Explanation of flow chart.
“USB Transceiver Treatment” Line 9 is revised: “between the USB D+ pin and
USB D- pin, or” is deleted.
Page 146 URL of Mitsubishi MCU Technical Information Homepage is revised:
http://www.infomicom.maec.co.jp
Operating temperature range is added.
Table 1 is revised: Ext. Cap. function’s explanation is revised.
Fig.4 is revised: “A-” is eliminated.
Fig.8 is revised: Bit 4 explanation of CPMA is revised.
Fig.17 is revised: The symbol of Interrupt control register C is corrected.
The pin name SRD is corrected to SRDY.
Fig.31 is revised: Serial I/O as interrupt is eliminated.
Fig.32 is revised: Bit 5 explanation of DMAxM1 is revised.
The flag name in section Priority is corrected to the DMAC Channel x (x =0, 1)
Suspend Flag (DxSFI).
Page 44 The explanation of section “Interrupt transfer mode” is revised.
Page 45 Some explanations of section “USB Reception” is eliminated.
Page 46 The all USB internal registers addresses in section USB Function Interrupt is corrected to “005F16”.
Page 53 The explanation of section “IN_CSR” is revised.
Page 55 Fig.48 is revised: Bits 0 and 3 name of OUT_CSR is corrected.
Page 75 Fig.70 is revised: Bit 4 explanation of CPMA is revised.
Page 80 Table 10 is revised: AVcc and Ext. Cap. as a parameter is added.
Page 88 Table 18 is revised: Ext. Cap. limits are added.
Page 91 Table 20 is revised: Test conditions to be determined are eliminated.
Page 94 Table 24 is revised: The parameter of td(WR-DB) is revised.
Pages 102 The explanation of section “FLASH MEMORY MODE” is revised.
to 128
Page 130 The all USB internal registers addresses in section USB Function Interrupt is corrected to “005F16”.
The explanation of IN_PKT_RDY is revised.
Page 131 The explanation of section “DMA” is revised.
Page 132 The explanation of section “USB Transceiver Treatment” is added: In Vcc = 5 V.
Power source voltage and Program/Erase voltage of Flash memory mode in FEATURES are updated.
Page 7
Fig. 5 is revised: “M37641F8” is in Mass-production status.
Page 102 Table 25 is revised.
Page 115 Table 28 is revised.
Page 133 One usage note is added: Electric Characteristic Differences Between Mask ROM
and Flash Memory Version MCUs
(1/2)
REVISION HISTORY
Rev.
7641 GROUP DATA SHEET
Date
Description
Summary
Page
4.0
8/28/2006
54
70
129
130
132
133
134
Fig. 47 “4: To use the AUTO_SET function .... to single buffer mode.” added
CLOCK GENERATING CIRCUIT; “No external resistor is needed .... resistor
exists on-chip.” → “No external resistor is needed .... depending on conditions.)
Fig. 64; Pulled up added, NOTE added
UART; “•Do not update .... data might be output.” added
USB; “•Use the AUTO_FLUSH Bit .... buffer mode.”,
“•To use the AUTO_SET function .... to single buffer mode.” added
Oscillator Connection Notice; “The built-in feedback register (400 ) .... pins X IN
and XOUT.” → “The built-in feedback register (1 M ) .... pins X IN and XOUT.”
Power Source Voltage added
USB Communication added
“For the mask ROM confirmation .... http://www.infomicom.maec.co.jp/indexe.htm”
→ “For the mask ROM confirmation .... (http://www.renesas.com).”
Package outline revised
(2/2)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
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Tel: <852> 2265-6688, Fax: <852> 2730-6071
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Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0