MCP3201
2.7V 12-Bit A/D Converter with SPI Serial Interface
Features
Description
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The Microchip Technology Inc. MCP3201 device is a
successive approximation 12-bit Analog-to-Digital
(A/D) Converter with on-board sample and hold
circuitry. The device provides a single pseudo-differential input. Differential Nonlinearity (DNL) is specified at
±1 LSB, and Integral Nonlinearity (INL) is offered in
±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C)
versions. Communication with the device is done using
a simple serial interface compatible with the SPI
protocol. The device is capable of sample rates of up to
100 ksps at a clock rate of 1.6 MHz. The MCP3201
device operates over a broad voltage range (2.7V 5.5V). Low-current design permits operation with
typical standby and active currents of only 500 nA and
300 µA, respectively. The device is offered in 8-pin
MSOP, PDIP, TSSOP and 150 mil SOIC packages.
12-bit resolution
±1 LSB max DNL
±1 LSB max INL (MCP3201-B)
±2 LSB max INL (MCP3201-C)
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100 ksps maximum sampling rate at VDD = 5V
50 ksps maximum sampling rate at VDD = 2.7V
Low power CMOS technology
500 nA typical standby current, 2 µA maximum
400 µA maximum active current at 5V
Industrial temp range: -40°C to +85°C
8-pin MSOP, PDIP, SOIC and TSSOP packages
Package Types
Applications
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
MSOP, PDIP, SOIC, TSSOP
Functional Block Diagram
VDD
VREF
VSS
VREF
1
IN+
2
IN–
3
VSS
4
MCP3201
•
•
•
•
8
VDD
7
CLK
6
DOUT
5
CS/SHDN
DAC
Comparator
IN+
IN-
12-Bit SAR
Sample
and
Hold
Control Logic
CS/SHDN
© 2008 Microchip Technology Inc.
CLK
Shift
Register
DOUT
DS21290E-page 1
MCP3201
NOTES:
DS21290E-page 2
© 2008 Microchip Technology Inc.
MCP3201
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings†
†Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
VDD...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................ -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
ESD protection on all pins (HBM) .................................> 4 kV
ELECTRICAL CHARACTERISTICS
Electrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
tCONV
—
—
12
clock
cycles
Conditions
Conversion Rate:
Conversion Time
Analog Input Sample Time
tSAMPLE
Throughput Rate
fSAMPLE
—
—
Integral Nonlinearity
INL
—
—
Differential Nonlinearity
DNL
1.5
clock
cycles
100
50
ksps
ksps
VDD = VREF = 5V
VDD = VREF = 2.7V
±0.75
±1
±1
±2
LSB
LSB
MCP3201-B
MCP3201-C
—
±0.5
±1
LSB
No missing codes over
temperature
Offset Error
—
±1.25
±3
LSB
Gain Error
—
±1.25
±5
LSB
THD
—
-82
—
dB
VIN = 0.1V to 4.9V@1 kHz
Signal to Noise and Distortion
(SINAD)
SINAD
—
72
—
dB
VIN = 0.1V to 4.9V@1 kHz
Spurious Free Dynamic Range
SFDR
—
86
—
dB
VIN = 0.1V to 4.9V@1 kHz
DC Accuracy:
Resolution
12
bits
Dynamic Performance:
Total Harmonic Distortion
Reference Input:
Voltage Range
0.25
—
VDD
V
Note 2
Current Drain
—
—
100
.001
150
3
µA
µA
CS = VDD = 5V
—
VREF+IN-
V
VSS+100
mV
µA
Analog Inputs:
Input Voltage Range (IN+)
IN+
IN-
Input Voltage Range (IN-)
IN-
VSS-100
Leakage Current
—
0.001
±1
Switch Resistance
RSS
—
1K
—
W
See Figure 4-1
Sample Capacitor
CSAMPLE
—
20
—
pF
See Figure 4-1
High Level Input Voltage
VIH
0.7 VDD
—
—
V
Low Level Input Voltage
VIL
—
—
0.3 VDD
V
Digital Input/Output:
Data Coding Format
Note 1:
2:
3:
Straight Binary
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to VREF level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.
© 2008 Microchip Technology Inc.
DS21290E-page 3
MCP3201
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter
Sym
Min
Typ
High Level Output Voltage
VOH
4.1
—
—
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
—
—
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
—
10
µA
VIN = VSS or VDD
Output Leakage Current
ILO
-10
—
10
µA
VOUT = VSS or VDD
CIN, COUT
—
—
10
pF
VDD = 5.0V (Note 1)
TA = +25°C, f = 1 MHz
fCLK
—
—
—
—
1.6
0.8
MHz
MHz
Clock High Time
tHI
312
—
—
ns
Clock Low Time
tLO
312
—
—
ns
tSUCS
100
—
—
ns
CLK Fall To Output Data Valid
tDO
—
—
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
—
—
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
CS Disable Time
Pin Capacitance
(all inputs/outputs)
Max
Units
Conditions
Timing Parameters:
Clock Frequency
CS Fall To First Rising CLK Edge
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
tCSH
625
—
—
ns
DOUT Rise Time
tR
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
DOUT Fall Time
tF
—
—
100
ns
See Test Circuits, Figure 1-2
(Note 1)
Operating Voltage
VDD
2.7
—
5.5
V
Operating Current
IDD
—
—
300
210
400
—
µA
µA
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
—
0.5
2
µA
CS = VDD = 5.0V
Power Requirements:
Note 1:
2:
3:
This parameter is established by characterization and not 100% tested.
See graph that relates linearity performance to VREF level.
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+85
°C
Operating Temperature Range
TA
-40
—
+85
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 8L-MSOP
θJA
—
211
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
—
89.5
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 8L-TSSOP
θJA
—
139
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS21290E-page 4
© 2008 Microchip Technology Inc.
MCP3201
tCSH
CS
tSUCS
tHI
tLO
CLK
tEN
HI-Z
DOUT
FIGURE 1-1:
tDO
NULL BIT
tR
tDIS
tF
HI-Z
LSB
MSB OUT
Serial Timing.
Load circuit for tDIS and tEN
Load circuit for tR, tF, tDO
1.4V
Test Point
VDD
3 kΩ
Test Point
DOUT
3 kΩ
DOUT
30 pF
CL = 30 pF
Voltage Waveforms for tR, tF
VOH
VOL
DOUT
tF
tR
tDIS Waveform 2
VDD/2
tEN Waveform
tDIS Waveform 1
VSS
Voltage Waveforms for tEN
CS
1
CLK
2
3
4
B9
DOUT
tEN
Voltage Waveforms for tDO
Voltage Waveforms for tDIS
CS
CLK
tDO
DOUT
VIH
DOUT
Waveform 1*
90%
tDIS
DOUT
Waveform 2†
10%
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled
by the output control.
† Waveform 2 is for an output with internal conditions such that the output is low, unless disabled
by the output control.
FIGURE 1-2:
Test Circuits.
© 2008 Microchip Technology Inc.
DS21290E-page 5
MCP3201
NOTES:
DS21290E-page 6
© 2008 Microchip Technology Inc.
MCP3201
2.0
TYPICAL PERFORMANCE CHARACTERISTICS
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
2.0
Positive INL
INL (LSB)
1.0
Negative INL
Positive INL
0.5
0.0
-0.5
Negative INL
-1.0
-1.5
-2.0
0
25
50
75
100
Sample Rate (ksps)
FIGURE 2-1:
vs. Sample Rate.
125
150
Integral Nonlinearity (INL)
0
2.0
1.5
1.5
40
60
Sample Rate (ksps)
0.0
Negative INL
100
Positive INL
0.5
0.0
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
Negative INL
-2.0
0
1
2
3
4
5
0.0
0.5
1.0
VREF (V)
FIGURE 2-2:
vs. VREF.
Integral Nonlinearity (INL)
0.8
0.6
0.4
INL (LSB)
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536 2048
2560 3072
3584 4096
Digital Code
FIGURE 2-3:
Integral Nonlinearity (INL)
vs. Code (Representative Part).
© 2008 Microchip Technology Inc.
1.5
VREF (V)
2.0
2.5
3.0
FIGURE 2-5:
Integral Nonlinearity (INL)
vs. VREF (VDD = 2.7V).
1.0
INL (LSB)
80
VDD = 2.7V
FSAMPLE = 50 ksps
1.0
Positive INL
0.5
-0.5
20
FIGURE 2-4:
Integral Nonlinearity (INL)
vs. Sample Rate (VDD = 2.7V).
2.0
1.0
INL (LSB)
VDD = VREF = 2.7V
1.5
INL (LSB)
INL (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
FIGURE 2-6:
Integral Nonlinearity (INL)
vs. Code (Representative Part, VDD = 2.7V).
DS21290E-page 7
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
1.0
1.0
0.6
0.6
0.4
0.4
0.2
0.0
Negative INL
-0.2
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
0.8
Positive INL
INL (LSB)
INL (LSB)
0.8
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
Negative INL
-1.0
-1.0
-50
-25
0
25
50
75
-50
100
-25
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
Integral Nonlinearity (INL)
25
50
75
100
FIGURE 2-10:
Integral Nonlinearity (INL)
vs. Temperature (VDD = 2.7V).
2.0
VDD = VREF = 2.7V
1.5
1.0
Positive DNL
DNL (LSB)
DNL (LSB)
FIGURE 2-7:
vs. Temperature.
0
Temperature (°C)
Temperature (°C)
Negative DNL
Positive DNL
0.5
0.0
-0.5
Negative DNL
-1.0
-1.5
-2.0
0
25
50
75
100
Sample Rate (ksps)
125
150
0
FIGURE 2-8:
Differential Nonlinearity
(DNL) vs. Sample Rate.
20
40
60
Sample Rate (ksps)
80
100
FIGURE 2-11:
Differential Nonlinearity
(DNL) vs. Sample Rate (VDD = 2.7V).
3.0
3.0
2.0
2.0
VDD = 2.7V
FSAMPLE = 50 ksps
Positive DNL
1.0
DNL (LSB)
DNL (LSB)
Positive INL
Positive DNL
0.0
Negative DNL
-1.0
1.0
0.0
-1.0
Negative DNL
-2.0
-3.0
-2.0
0
1
2
3
4
VREF (V)
FIGURE 2-9:
(DNL) vs. VREF.
DS21290E-page 8
Differential Nonlinearity
5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VREF(V)
FIGURE 2-12:
Differential Nonlinearity
(DNL) vs. VREF (VDD = 2.7V).
© 2008 Microchip Technology Inc.
MCP3201
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
DNL (LSB)
DNL (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
FIGURE 2-16:
Differential Nonlinearity
(DNL) vs. Code (Representative Part,
VDD = 2.7V).
Positive DNL
DNL (LSB)
DNL (LSB)
FIGURE 2-13:
Differential Nonlinearity
(DNL) vs. Code (Representative Part).
Negative DNL
-50
-25
0
25
50
Temperature (°C)
75
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VDD = 2.7V
FSAMPLE = 50ksps
Positive DNL
Negative DNL
-50
100
FIGURE 2-14:
Differential Nonlinearity
(DNL) vs. Temperature.
-25
0
25
50
Temperature (°C)
75
100
FIGURE 2-17:
Differential Nonlinearity
(DNL) vs. Temperature (VDD = 2.7V).
20
5
18
Offset Error (LSB)
4
Gain Error (LSB)
1.0
VDD = VREF = 2.7V
0.8 F
SAMPLE = 50 ksps
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
VDD = 2.7V
3
FSAMPLE = 50 ksps
2
1
0
VDD = 5V
-1
FSAMPLE = 100 ksps
-2
16
V DD = 5V
14
FSAMPLE = 100 ksps
12
10
8
V DD = 2.7V
6
FSAMPLE = 50ksps
4
2
0
0
1
2
3
4
5
0
VREF(V)
FIGURE 2-15:
Gain Error vs. VREF.
© 2008 Microchip Technology Inc.
1
2
3
4
5
VREF (V)
FIGURE 2-18:
Offset Error vs. VREF.
DS21290E-page 9
MCP3201
Offset Error (LSB)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
VDD = VREF = 5V
FSAMPLE = 100 ksps
-50
-25
FIGURE 2-19:
0
25
50
Temperature (°C)
75
Gain Error vs. Temperature.
100
90
80
70
60
50
40
30
20
10
0
SNR (dB)
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
10
Input Frequency (kHz)
-25
100
90
80
70
60
50
40
30
20
10
0
0
25
50
Temperature (°C)
75
100
Offset Error vs.
VDD = VREF = 5V
FSAMPLE = 100 ksps
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
1
10
Input Frequency (kHz)
100
FIGURE 2-23:
Signal-to-Noise and
Distortion (SINAD) vs. Input Frequency.
80
VDD = VREF = 5V
FSAMPLE = 100 ksps
70
SINAD (dB)
THD (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
FIGURE 2-22:
Temperature.
100
FIGURE 2-20:
Signal-to-Noise Ratio (SNR)
vs. Input Frequency.
VDD = VREF = 5V
FSAMPLE = 100 ksps
-50
VDD = VREF = 5V
FSAMPLE = 100 ksps
1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
100
SINAD (dB)
Gain Error (LSB)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
60
50
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
40
30
20
10
VDD = VREF = 5V, FSAMPLE = 100 ksps
0
1
10
Input Frequency (kHz)
100
FIGURE 2-21:
Total Harmonic Distortion
(THD) vs. Input Frequency.
DS21290E-page 10
-40
-35
-30
-25
-20
-15
-10
Input Signal Level (dB)
-5
0
FIGURE 2-24:
Signal-to-Noise and
Distortion (SINAD) vs. Input Signal Level.
© 2008 Microchip Technology Inc.
MCP3201
12.0
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
9.75
9.50
9.25
9.00
V DD = 5V
11.5
FSAMPLE = 100 ksps
11.0
VDD = VREF = 5V
FSAMPLE =100 ksps
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
ENOB (rms)
ENOB (rms)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
10.5
10.0
9.5
9.0
VDD = 2.7V
8.5
FSAMPLE = 50 ksps
8.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
VREF (V)
Effective Number of Bits
SFDR (dB)
VDD = VREF = 5V, FSAMPLE = 100 ksps
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
1
10
Input Frequency (kHz)
10000
20000
30000
Frequency (Hz)
40000
50000
Amplitude (dB)
FIGURE 2-27:
Frequency Spectrum of
10 kHz input (Representative Part).
© 2008 Microchip Technology Inc.
-20
-30
-40
-50
-60
-70
-80
1
10
100
1000
10000
Ripple Frequency (kHz)
VDD = VREF = 5V
FSAMPLE = 100 ksps
FINPUT = 9.985kHz
4096 points
0
0
-10
100
FIGURE 2-26:
Spurious Free Dynamic
Range (SFDR) vs. Input Frequency.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
FIGURE 2-28:
Effective Number of Bits
(ENOB) vs. Input Frequency.
Power Supply Rejection (dB)
100
90
80
70
60
50
40
30
20
10
0
Input Frequency (kHz)
FIGURE 2-29:
Power Supply Rejection
(PSR) vs. Ripple Frequency.
Amplitude (dB)
FIGURE 2-25:
(ENOB) vs. VREF.
100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
VDD = VREF = 2.7V
FSAMPLE = 50 ksps
FINPUT = 998.76 Hz
4096 points
0
5000
10000
15000
Frequency (Hz)
20000
25000
FIGURE 2-30:
Frequency Spectrum of
1 kHz input (Representative Part, VDD = 2.7V).
DS21290E-page 11
MCP3201
500
450
400
350
300
250
200
150
100
50
0
100
90
80
70
60
50
40
30
20
10
0
VREF = VDD
All points at FCLK = 1.6 MHz, except
at VREF = VDD = 2.5V, FCLK = 800 kHz
VREF = VDD
All points at FCLK = 1.6 MHz, except
at VREF = VDD = 2.5V, FCLK = 800 kHz
IREF (µA)
IDD (µA)
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
VDD (V)
FIGURE 2-31:
FIGURE 2-34:
IDD vs. VDD.
90
350
5.5
6.0
IREF vs. VDD.
VDD = V REF = 5V
80
VDD = VREF = 5V
70
IREF (µA)
300
IDD (µA)
5.0
100
400
250
200
VDD = VREF = 2.7V
150
60
50
40
VDD = VREF = 2.7V
30
100
20
50
10
0
0
10
100
1000
10
10000
100
Clock Frequency (kHz)
FIGURE 2-32:
IDD vs. Clock Frequency.
FIGURE 2-35:
VDD = VREF = 5V
FCLK = 1.6 MHz
350
300
IREF (µA)
250
200
VDD = VREF = 2.7V
FCLK = 800 kHz
150
100
50
0
-50
-25
FIGURE 2-33:
DS21290E-page 12
0
25
50
Temperature (°C)
1000
10000
Clock Frequency (kHz)
400
IDD (µA)
4.0
4.5
VDD (V)
75
IDD vs. Temperature.
100
100
90
80
70
60
50
40
30
20
10
0
IREF vs. Clock Frequency.
VDD = VREF = 5V
FCLK = 1.6 MHz
VDD = VREF = 2.7V
FCLK = 800 kHz
-50
-25
FIGURE 2-36:
0
25
50
Temperature (°C)
75
100
IREF vs. Temperature.
© 2008 Microchip Technology Inc.
MCP3201
Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE, TA = +25°C.
70
Analog Input Leakage (nA)
80
VREF = CS = VDD
IDDS (pA)
60
50
40
30
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 2-37:
IDDS vs. VDD.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VDD = VREF = 5V
FCLK = 1.6 MHz
-50
-25
0
25
50
Temperature (°C)
75
100
FIGURE 2-39:
Analog Input Leakage
Current vs. Temperature.
100.00
VDD = VREF = CS = 5V
I DDS (nA)
10.00
1.00
0.10
0.01
-50
FIGURE 2-38:
-25
0
25
50
Temperature (°C)
75
100
IDDS vs. Temperature.
© 2008 Microchip Technology Inc.
DS21290E-page 13
MCP3201
NOTES:
DS21290E-page 14
© 2008 Microchip Technology Inc.
MCP3201
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PIN FUNCTION TABLE
MCP3201
MSOP, PDIP, SOIC,
TSSOP
Symbol
1
VREF
2
IN+
Positive Analog Input
3
IN-
Negative Analog Input
4
VSS
Ground
5
CS/SHDN
6
DOUT
Serial Data Out
7
CLK
Serial Clock
8
VDD
+2.7V to 5.5V Power Supply
3.1
Positive Analog Input (IN+)
Positive analog input. This input can vary from IN- to
VREF + IN-.
3.2
Negative Analog Input (IN-)
Negative analog input. This input can vary ±100 mV
from VSS.
3.3
Chip Select/Shutdown (CS/SHDN)
The CS/SHDN pin is used to initiate communication
with the device when pulled low and will end a
conversion and put the device in low power standby
when pulled high. The CS/SHDN pin must be pulled
high between conversions.
© 2008 Microchip Technology Inc.
Description
Reference Voltage Input
Chip Select/Shutdown Input
3.4
Serial Clock (CLK)
The SPI clock pin is used to initiate a conversion and to
clock out each bit of the conversion as it takes place.
See Section 6.2 “Maintaining Minimum Clock
Speed” for constraints on clock speed.
3.5
Serial Data Output (DOUT)
The SPI serial data output pin is used to shift out the
results of the A/D conversion. Data will always change
on the falling edge of each clock as the conversion
takes place.
DS21290E-page 15
MCP3201
NOTES:
DS21290E-page 16
© 2008 Microchip Technology Inc.
MCP3201
4.0
DEVICE OPERATION
4.2
Reference Input
The MCP3201 A/D Converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the first rising edge of the
serial clock after CS has been pulled low. Following this
sample time, the input switch of the converter opens
and the device uses the collected charge on the
internal sample and hold capacitor to produce a serial
12-bit digital output code. Conversion rates of 100 ksps
are possible on the MCP3201 device. See Section 6.2
“Maintaining Minimum Clock Speed” for information
on minimum clock rates. Communication with the
device is done using a 3-wire SPI-compatible interface.
The reference input (VREF) determines the analog input
voltage range and the LSB size, as shown below.
4.1
EQUATION 4-2:
Analog Inputs
The MCP3201 device provides a single pseudo-differential input. The IN+ input can range from IN- to VREF
(VREF + IN-). The IN- input is limited to ±100 mV from
the VSS rail. The IN- input can be used to cancel small
signal common-mode noise which is present on both
the IN+ and IN- inputs.
For the A/D Converter to meet specification, the charge
holding capacitor (CSAMPLE) must be given enough
time to acquire a 12-bit accurate voltage level during
the 1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(RS) adds to the internal sampling switch (RSS)
impedance, directly affecting the time that is required to
charge the capacitor (CSAMPLE). Consequently, a
larger source impedance increases the offset, gain,
and integral linearity errors of the conversion.
EQUATION 4-1:
V REF
LSB Size = -----------4096
As the reference input is reduced, the LSB size is
reduced accordingly. The theoretical digital output code
produced by the A/D Converter is a function of the
analog input signal and the reference input as shown
below.
4096*V IN
Digital Output Code = ----------------------V REF
Where:
VIN
=
Analog Input Voltage = V(IN+) - V(IN-)
VREF
=
Reference Voltage
When using an external voltage reference device, the
system designer should always refer to the
manufacturer’s recommendations for circuit layout.
Any instability in the operation of the reference device
will have a direct effect on the operation of the
A/D Converter.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational
amplifier such as the MCP601, which has a closed loop
output impedance of tens of ohms. The adverse affects
of higher source impedances are shown in Figure 4-2.
If the voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[VREF + (IN-)] - 1 LSB}, then the
output code will be FFFh. If the voltage level at IN- is
more than 1 LSB below VSS, then the voltage level at
the IN+ input will have to go below VSS to see the 000h
output code. Conversely, if IN- is more than 1 LSB
above VSS, then the FFFh code will not be seen unless
the IN+ input level goes above VREF level.
© 2008 Microchip Technology Inc.
DS21290E-page 17
MCP3201
VDD
RSS
VT = 0.6V
CHx
CPIN
7 pF
VA
Sampling
Switch
VT = 0.6V
SS
ILEAKAGE
±1 nA
RS = 1 kΩ
CSAMPLE
= DAC capacitance
= 20 pF
VSS
LEGEND
VA
RSS
CHx
CPIN
VT
ILEAKAGE
SS
RS
CSAMPLE
=
=
=
=
=
=
=
=
=
FIGURE 4-1:
Signal Source
Source Impedance
Input Channel Pad
Input Pin Capacitance
Threshold Voltage
Leakage Current At The Pin
Due To Various Junctions
Sampling Switch
Sampling Switch Resistor
Sample/hold Capacitance
Analog Input Model.
Clock Frequency (MHz)
1.8
1.6
VDD = VREF = 5V
1.4
1.2
1.0
0.8
0.6
VDD = VREF = 2.7V
0.4
0.2
0.0
100
1000
10000
Input Resistance (Ohms)
FIGURE 4-2:
Maximum Clock Frequency
vs. Input Resistance (RS) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.
DS21290E-page 18
© 2008 Microchip Technology Inc.
MCP3201
5.0
SERIAL COMMUNICATIONS
Communication with the device is done using a
standard SPI-compatible serial interface. Initiating
communication with the MCP3201 device begins with
the CS going low. If the device was powered up with the
CS pin low, it must be brought high and back low to
initiate communication. The device will begin to sample
the analog input on the first rising edge after CS goes
low. The sample period will end in the falling edge of the
second clock, at which time the device will output a low
null bit. The next 12 clocks will output the result of the
conversion with MSB first, as shown in Figure 5-1. Data
is always output from the device on the falling edge of
the clock. If all 12 data bits have been transmitted and
the device continues to receive clocks while the CS is
held low, the device will output the conversion result
LSB first, as shown in Figure 5-2. If more clocks are
provided to the device while CS is still low (after the
LSB first data has been transmitted), the device will
clock out zeros indefinitely.
tCYC
TCSH
CS
POWER
DOWN
TSUCS
CLK
TSAMPLE
HI-Z
DOUT
tDATA**
tCONV
NULL B11 B10 B9
BIT
B8
B7
B6
B5
B4
B3
B2
B1 B0*
HI-Z
NULL B11 B10 B9
BIT
B8
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed
by zeros indefinitely. See Figure 5-2 below.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-1:
Communication with MCP3201 device using MSB first Format.
tCYC
tCSH
CS
tSUCS
POWER DOWN
CLK
tSAMPLE
DOUT
HI-Z
tCONV
tDATA**
NULL B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11*
BIT
HI-Z
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.
** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high-impedance
node, leaving the CLK running to clock out the LSB-first data or zeros.
FIGURE 5-2:
Communication with MCP3201 device using LSB first Format.
© 2008 Microchip Technology Inc.
DS21290E-page 19
MCP3201
NOTES:
DS21290E-page 20
© 2008 Microchip Technology Inc.
MCP3201
6.0
APPLICATIONS INFORMATION
6.1
Using the MCP3201 Device with
Microcontroller SPI Ports
been sent to the device, the microcontroller’s receive
buffer will contain two unknown bits (the output is at
high-impedance for the first two clocks), the null bit and
the highest order five bits of the conversion. After the
second eight clocks have been sent to the device, the
MCU receive register will contain the lowest-order
seven bits and the B1 bit repeated as the A/D
Converter has begun to shift out LSB first data with the
extra clock. Typical procedure would then call for the
lower-order byte of data to be shifted right by one bit to
remove the extra B1 bit. The B7 bit is then transferred
from the high-order byte to the lower-order byte, and
then the higher-order byte is shifted one bit to the right
as well. Easier manipulation of the converted data can
be obtained by using this method.
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 device can be
interfaced to a microcontroller with a standard SPI port.
Since the MCP3201 always clocks data out on the
falling edge of clock, the MCU SPI port must be
configured to match this operation. SPI Mode 0,0
(clock idles low) and SPI Mode 1,1 (clock idles high)
are both compatible with the MCP3201. Figure 6-1
depicts the operation shown in SPI Mode 0,0, which
requires that the CLK from the microcontroller idles in
the ‘low’ state. As shown in the diagram, the MSB is
clocked out of the A/D Converter on the falling edge of
the third clock pulse. After the first eight clocks have
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
CS
MCU latches data from A/D
Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data is clocked out of A/D
Converter on falling edges
DOUT
HI-Z
NULL B11 B10
BIT
B9
B7
B8
B6
B4
B5
B3
B2
B1
B0
B1 B2
HI-Z
LSB first data begins
to come out
?
?
B11 B10 B9
0
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-1:
B5
B6
B4
B3
B2
B1
B1
B0
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D
Converter on rising edges of SCLK
CLK
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
Data is clocked out of A/D
Converter on falling edges
DOUT
HI-Z
NULL B11 B10 B9
BIT
B8
B7
B6
B5
B4 B3
B2
B1
B0
B1
HI-Z
LSB first data begins
to come out
?
?
0
B11 B10 B9
B8
B7
Data stored into MCU receive register
after transmission of first 8 bits
FIGURE 6-2:
B6
B5
B4
B3
B2
B1
B0
B1
Data stored into MCU receive register
after transmission of second 8 bits
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
© 2008 Microchip Technology Inc.
DS21290E-page 21
MCP3201
6.2
Maintaining Minimum Clock Speed
When the MCP3201 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst case condition), the part will maintain
proper charge on the sample capacitor for at least
1.2 ms after the sample period has ended. This means
that the time between the end of the sample period and
the time that all 12 data bits have been clocked out
must not exceed 1.2 ms (effective clock frequency of
10 kHz). Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D Converter does not require a
constant clock speed or duty cycle, as long as all timing
specifications are met.
6.3
Buffering/Filtering the Analog
Inputs
VDD
10 µF
4.096V
Reference
0.1 µF
10 µF
MCP1541
CL
VREF
IN+
1 µF
MCP3201
VIN
R1
C1
MCP601
IN-
+
R2
-
C2
R3
R4
FIGURE 6-3:
The MCP601 Operational
Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by
the MCP3201 device.
If the signal source for the A/D Converter is not a low
impedance source, it will have to be buffered
or inaccurate conversion results may occur.
See Figure 4-2. It is also recommended that a filter be
used to eliminate any signals that may be aliased back
into the conversion results. This is illustrated in
Figure 6-3 where an op amp is used to drive the analog
input of the MCP3201 device. This amplifier provides a
low impedance source for the converter input and a
low-pass filter, which eliminates unwanted highfrequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab® software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see the application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
DS21290E-page 22
© 2008 Microchip Technology Inc.
MCP3201
6.4
Layout Considerations
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor should
always be used with this device and should be placed
as close as possible to the device pin. A bypass
capacitor value of 1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board and no traces should run
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing VDD connections to
devices in a “star” configuration can also reduce noise
by eliminating current return paths and associated
errors. See Figure 6-4. For more information on layout
tips when using A/D Converter, refer to AN688 “Layout
Tips for 12-Bit A/D Converter Applications”.
VDD
Connection
Device 4
Device 1
Device 3
Device 2
FIGURE 6-4:
VDD traces arranged in a
‘Star’ configuration in order to reduce errors
caused by current return paths.
© 2008 Microchip Technology Inc.
DS21290E-page 23
MCP3201
NOTES:
DS21290E-page 24
© 2008 Microchip Technology Inc.
MCP3201
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
Example:
8-Lead MSOP
XXXXXX
3201CI
YWWNNN
820256
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
3201-B
3
I/P e^^256
0820
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
Example:
XXXX
201C
YYWW
I820
NNN
256
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Example:
3201-BI
SN e3 0820
256
8-Lead TSSOP
*
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS21290E-page 25
MCP3201
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© 2008 Microchip Technology Inc.
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© 2008 Microchip Technology Inc.
DS21290E-page 29
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© 2008 Microchip Technology Inc.
MCP3201
APPENDIX A:
REVISION HISTORY
Revision E (November 2008)
The following is the list of modifications:
1.
2.
Updated Section 7.0 “Packaging Information”
Updated Section “Product Identification
System”.
Revision D (January 2007)
The following is the list of modifications:
1.
This revision includes updates to the packaging
diagrams.
diagrams.Revision C (August 2001)
The following is the list of modifications:
1.
This revision includes undocumented changes.
Revision B (August 1999)
The following is the list of modifications:
1.
This revision includes undocumented changes.
Revision A (September 1998)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS21290E-page 31
MCP3201
NOTES:
DS21290E-page 32
© 2008 Microchip Technology Inc.
MCP3201
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
X
/XX
Device
Grade
Temperature
Range
Package
Device
MCP3201:
MCP3201T:
12-Bit A/D Converter w/SPI Interface
12-Bit A/D Converter w/SPI Interface
(Tape and Reel)
Grade
B:
C:
= ± LSB max INL (MSOP and TSSOP not available)
= ± LSB max INL
Temperature Range
I
= -40°C to+85°C(Industrial)
Package
MS
P
SN
ST
=
=
=
=
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
© 2008 Microchip Technology Inc.
Examples:
a)
MCP3201-BI/P:
B Grade,
Industrial Temperature,
8LD PDIP package.
b)
MCP3201-BI/SN:
B Grade,
Industrial Temperature,
8LD SOIC package.
c)
MCP3201-CI/P:
C Grade,
Industrial Temperature,
8LD PDIP package.
d)
MCP3201-CI/MS:
C Grade,
Industrial Temperature,
8LD MSOP package.
e)
MCP3201-CI/SN:
C Grade,
Industrial Temperature,
8LD SOIC package.
f)
MCP3201-CI/ST:
C Grade,
Industrial Temperature,
8LD TSSOP package.
g)
MCP3201T-BI/SN: Tape and Reel,B Grade,
Industrial Temperature,
8LD SOIC package.
h)
MCP3201T-CI/MS: Tape and Reel, C Grade,
Industrial Temperature,
8LD MSOP package.
i)
MCP3201T-CI/SN: Tape and Reel, C Grade,
Industrial Temperature,
8LD SOIC package.
j)
MCP3201T-CI/ST: Tape and Reel, C Grade,
Industrial Temperature,
8LD TSSOP package.
DS21290E-page 33
MCP3201
NOTES:
DS21290E-page 34
© 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC, SmartShunt and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS21290E-page 35
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS21290E-page 36
© 2008 Microchip Technology Inc.