Mitsubishi M37516M6 Single-chip 8-bit cmos microcomputer Datasheet

MITSUBISHI ELECTRIC CORPORATION
SPEC.NAME
Customer's
Std.Spec
Prepared by
H.Yamazoe
Checked by
Y.Hayashi
Approved by
M.Abe
DATE
31 May '99
R
E
V
INTEGRATED CIRCUIT
1.
Type No.
M37516M6-XXXHP
2.
Function
Single chip 8-bit microcomputer
3.
Application
Office automation,Household products etc.
4.
Outline
4.1 Name
4.2
48P6D / 48P6Q (48pin 0.5mm pitch Plastic-molded LQFP)
Drawing No.
5.
Circuit
Drawing No.
6.
Pin Configuration
7.
Related Documents
M37516M6-XXXHP
See Page 2
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DESCRIPTION
●Clock generating circuit ..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In high-speed mode .................................................. 2.7 to 5.5 V
(at 4 MHz oscillation frequency)
In middle-speed mode ............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode .......................................................... 34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode .............................................................. 60uW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range .................................... –20 to 85 C
The M37516M6-XXXHP is the 8-bit microcomputer based on the
740 family core technology.
The M37516M6-XXXHP is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, A-D converter, and I2C-bus interface.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time ................................... 0.5us
(at 8 MHz oscillation frequency)
●Memory size
ROM ............................................................................. 24 Kbytes
RAM .............................................................................. 640 bytes
●Programmable input/output ports ............................................ 40
●Interrupts ................................................. 17 sources, 16 vectors
●Timers ............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●Multi-master I2C-bus interface (option) ....................... 1 channel
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 8 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
P07
P10(LED0)
P11(LED1)
25
P06
27
P05
29
28
26
P03/SRDY2
P04
31
30
P01/SOUT2
P02/SCLK2
33
P00/SIN2
34
32
P36/AN6
P37/AN7
36
35
PIN CONFIGURATION (TOP VIEW)
P35/AN5
37
24
P12(LED2)
P34/AN4
38
23
P13(LED3)
P33/AN3
39
22
P14(LED4)
P32/AN2
40
21
P15(LED5)
P31/AN1
41
20
P16(LED6)
P30/AN0
42
VCC
43
M37516M6-XXXHP
19
P17(LED7)
18
VSS
10
11
12
P23/SCL1
CNVSS
P24/SDA2/RXD
P22/SDA1
8
9
P25/SCL2/TXD
P21/XCIN
6
13
7
48
P27/CNTR0/SRDY1
P26/SCLK
P45
4
P20 /XCOUT
5
RESET
14
P41/INT0
15
47
P40/CNTR1
46
P46
3
P47
P42/INT1
XIN
1
XOUT
16
2
17
45
P44/INT3/PWM
44
P43/INT2/SCMP2
VREF
AVSS
Package type : 48P6D-A / 48P6Q-A (48-pin plastic-molded LQFP)
Fig. 1 M37516M6-XXXHP pin configuration
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M37516M6-XXXHP
Sub-clock Sub-clock
input
output
XCIN XCOUT
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
AVSS
VREF
44 45
A-D
converter
(10)
PWM
(8)
Reset
Clock generating circuit
17
Main-clock
output
XOUT
Watchdog
timer
16
Main-clock
input
XIN
I/O port P4
46 47 48 1 2 3 4 5
P4(8)
RAM
FUNCTIONAL BLOCK DIAGRAM
INT0–
INT3
P3(8)
PC H
I/O port P3
35 36 37 38 39 40 41 42
ROM
18
VSS
SI/O1(8)
C P U
43
VCC
PS
I2 C
PC L
S
Y
X
A
15
RESET
CNTR0
Reset input
P2(8)
CNTR1
I/O port P2
XCOUT
XCIN
Prescaler Y(8)
Prescaler X(8)
Prescaler 12(8)
6 7 8 9 10 11 13 14
12
CNVSS
I/O port P1
19 20 21 22 23 24 25 26
P1(8)
P0(8)
I/O port P0
27 28 29 30 31 32 33 34
Timer Y( 8 )
Timer X( 8 )
Timer 2( 8 )
Timer 1( 8 )
SI/O2(8)
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
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PIN DESCRIPTION
Table 1 Pin description
Pin
VCC, VSS
Power source
CNVSS
CNVSS input
RESET
Reset input
XIN
Clock input
XOUT
Clock output
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
I/O port P0
P10–P17
I/O port P1
P20/XCOUT
P21/XCIN
P22/SDA1
P23/SCL1
P24/SDA2/RxD
P25/SCL2/TxD
Functions
Name
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
• Serial I/O2 function pins
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Sub-clock generating circuit I/O
pins (connect a resonator)
• I2C-BUS interface function pins
•CMOS compatible input level.
•P22 to P25 can be switched between CMOS compatible input level or SMBUS input level in the I2C-BUS
interface function.
• I2C-BUS interface function pin/
Serial I/O1 function pins
P26/SCLK
•P20, P21, P24 to P27: CMOS3-state output structure.
P27/CNTR0/
SRDY1
•P24, P25 : N-channel open-drain structure in the I2CBUS interface function.
•P22, P23: N-channel open-drain structure.
• Serial I/O1 function pin
• Serial I/O1 function pin/
Timer X function pin
P30/AN0–
P37/AN7
I/O port P2
•8-bit CMOS I/O port with the same function as port P0.
I/O port P3
•CMOS 3-state output structure.
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
• A-D converter input pin
•CMOS compatible input level.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
I/O port P4
• Timer Y function pin
• Interrupt input pins
• Interrupt input pins
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P44/INT3/PWM
P45–P47
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FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The M37516M6-XXXHP uses the standard 740 Family instruction
set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details
on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “1” when read)
(Do not write “0” to this bit.)
Port X C switch bit
0 : I/O port function (stop oscillating)
1 : X CIN–XCOUT oscillating function
Main clock (X IN–XOUT ) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X IN)/2 (high-speed mode)
0 1 : φ = f(X IN)/8 (middle-speed mode)
1 0 : φ = f(X CIN)/2 (low-speed mode)
1 1 : Not available
Fig. 3 Structure of CPU mode register
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MEMORY
Special Function Register (SFR) Area
Zero Page
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
000016
SFR area
Zero page
004016
010016
RAM
640 bytes
023F16
Reserved area
044016
Not used
A00016
Reserved ROM area
(128 bytes)
A08016
ROM
24 Kbytes
FF0016
FFDC16
Interrupt vector area
FFFE16
FFFF16
Special page
Reserved ROM area
Fig. 4 Memory map diagram
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000016
Port P0 (P0)
002016
Prescaler 12 (PRE12)
000116
Port P0 direction register (P0D)
002116
Timer 1 (T1)
000216
Port P1 (P1)
002216
Timer 2 (T2)
000316
Port P1 direction register (P1D)
002316
Timer XY mode register (TM)
000416
Port P2 (P2)
002416
Prescaler X (PREX)
000516
Port P2 direction register (P2D)
002516
Timer X (TX)
000616
Port P3 (P3)
002616
Prescaler Y (PREY)
000716
Port P3 direction register (P3D)
002716
Timer Y (TY)
000816
Port P4 (P4)
002816
Timer count source selection register (TCSS)
000916
Port P4 direction register (P4D)
002916
000A16
002A16
000B16
002B16
I2C data shift register (S0)
000C16
002C16
I2C address register (S0D)
000D16
002D16
I2C status register (S1)
000E16
002E16
I2C control register (S1D)
000F16
002F16
I2C clock control register (S2)
001016
003016
I2C start/stop condition control register (S2D)
001116
003116
001216
003216
001316
003316
003416
A-D control register (ADCON)
001516
Serial I/O2 control register1 (SIO2CON1)
003516
A-D conversion low-order register (ADL)
001616
Serial I/O2 control register2 (SIO2CON2)
003616
A-D conversion high-order register (ADH)
001716
Serial I/O2 register (SIO2)
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O1 status register (SIOSTS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIOCON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
PWM control register (PWMCON)
003D16
Interrupt request register 2 (IREQ2)
001E16
PWM prescaler (PREPWM)
003E16
Interrupt control register 1 (ICON1)
001F16
PWM register (PWM)
003F16
Interrupt control register 2 (ICON2)
001416
Fig. 5 Memory map of special function register (SFR)
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I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input
port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 2 I/O port function
Pin
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
Name
Input/Output
Ref.No.
(1)
(2)
(3)
(4)
Serial I/O2 control
register
(5)
Port P1
P22/SDA1
P23/SCL1
Port P2
P24/SDA2/RxD
P25/SCL2/TxD
Input/output,
individual
bits
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I2C-BUS interface
function)
N-channel open-drain
output
CMOS compatible
input level
CMOS/SMBUS input
level (when selecting
I2C-BUS interface
function)
CMOS 3-state output
N-channel open-drain
output (when
selecting I2C-BUS
interface function)
P26/SCLK
Sub-clock generating
circuit
CPU mode register
(6)
(7)
I2C-BUS interface function I/O
I2C control register
(8)
(9)
I2C-BUS interface function I/O
Serial I/O1 function I/O
I2C control register
Serial I/O1 control
register
(10)
(11)
Serial I/O1 function I/O
Serial I/O1 control
register
(12)
(13)
Timer X function I/O
Serial I/O1 control
register
Timer XY mode register
A-D conversion input
A-D control register
(14)
Timer Y function I/O
Timer XY mode register
(15)
External interrupt input
Interrupt edge selection
register
(16)
Serial I/O1 function I/O
P27/CNTR0/SRDY1
Port P3
P40/CNTR1
CMOS compatible
input level
CMOS 3-state output
P41/INT0
P42/INT1
P43/INT2/SCMP2
Related SFRs
CMOS compatible
input level
CMOS 3-state output
P20/XCOUT
P21/XCIN
P30/AN0—
P37/AN7
Non-Port Function
Serial I/O2 function I/O
Port P0
P04–P07
P10–P17
I/O Structure
Port P4
P44/INT3/PWM
External interrupt input
SCMP2 output
External interrupt input
PWM output
Interrupt edge selection
register
Serial I/O2 control
register
Interrupt edge selection
register
PWM control register
(18)
(5)
P45—P47
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(2) Port P01
(1) Port P00
P01/SOUT2 P-channel output disable bit
Direction
register
Data bus
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(4) Port P03
(3) Port P02
SRDY2 output enable bit
P02/SCLK2 P-channel output disable bit
Direction
register
Serial I/O2 synchronous clock selection bit
Serial I/O2 port selection bit
Direction
register
Data bus
Data bus
Port latch
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 External clock input
(5) Port P04-P07, P1, P45-P47
(6) Port P20
Port XC switch bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
Oscillator
Port P21
Port XC switch bit
(7) Port P21
(8) Port P22
I 2 C-BUS interface enable bit
SDA/SCL pin selection bit
Port XC switch bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Sub-clock generating circuit input
SDA output
SDA input
Fig. 6 Port block diagram (1)
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(10) Port P24
(9) Port P23
I2C-BUS interface enable bit
SDA/SCL pin selection bit
I2C-BUS interface enable bit
SDA/SCL pin selection bit
Serial I/O1 enable bit
Receive enable bit
Direction
register
Data bus
Direction
register
Port latch
Data bus
Port latch
SCL output
SCL input
SDA input
SDA output
Serial I/O1 input
(12) Port P26
(11) Port P25
P-channel output disable bit
Serial I/O1 enable bit
Serial I/O1 clock selection bit
Serial I/O1 enable bit
Transmit enable bit
bus interface enable bit
SDA/SCL pin selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
I2C
Direction
register
Data bus
Direction
register
Data bus
Port latch
SCL input
Serial I/O1 output
Port latch
Serial I/O1 clock output
External clock input
SCL output
(13) Port P27
(14) Port P30–P37
Direction
register
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Data bus
Port latch
Direction
register
Data bus
Port latch
A-D converter input
Analog input pin selection bit
Pulse output mode
Serial ready output
CNTR0 interrupt
input
Timer output
(16) Port P41, P42
(15) Port P40
Direction
register
Data bus
Direction
register
Port latch
Data bus
Pulse output mode
Port latch
Interrupt input
Timer output
CNTR1 interrupt input
Fig. 7 Port block diagram (2)
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(17) Port P43
(18) Port P44
Serial I/O2 I/O comparison
signal control bit
PWM output enable bit
Direction
register
Direction
register
Data bus
Data bus
Port latch
Port latch
PWM output
Serial I/O2 I/O comparison
signal output
Interrupt input
Interrupt input
Fig. 8 Port block diagram (3)
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INTERRUPTS
■Notes
Interrupts occur by 17 sources among 17 sources: seven external,
nine internal, and one software.
When the active edge of an external interrupt (INT0 –INT3 , SCL/
SDA, CNTR0, CNTR1) is set, the corresponding interrupt request
bit may also be set. Therefore, take the following sequence:
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
1. Disable the interrupt
2. Change the interrupt edge selection register
(SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the
timer XY mode register for CNTR0 and CNTR1)
3. Clear the interrupt request bit to “0”
4. Accept the interrupt.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
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Table 3 Interrupt vector addresses and priority
Interrupt Source
Reset (Note 2)
Priority
1
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
Interrupt Request
Generating Conditions
Remarks
At reset
Non-maskable
External interrupt
(active edge selectable)
INT0
2
FFFB16
FFFA16
At detection of either rising or
falling edge of INT0 input
SCL, SDA
3
FFF916
FFF816
At detection of either rising or
falling edge of SCL or SDA input
External interrupt
(active edge selectable)
INT1
4
FFF716
FFF616
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
INT2
5
FFF516
FFF416
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3 / Serial I/O2
6
FFF316
FFF216
At detection of either rising or
falling edge of INT3 input
External interrupt
(active edge selectable)
I 2C
Timer X
Timer Y
Timer 1
7
8
FFF116
FFF016
At completion of data transfer
FFEF16
9
FFED16
10
11
FFEB16
FFE916
FFEE16
FFEC16
FFEA16
FFE816
At timer X underflow
At timer Y underflow
At timer 1 underflow
Serial I/O1
reception
12
FFE716
FFE616
At completion of serial I/O1 data
reception
Valid when serial I/O is selected
Serial I/O1
Transmission
13
FFE516
FFE416
At completion of serial I/O1
transfer shift or when transmission buffer is empty
Valid when serial I/O is selected
CNTR0
14
FFE316
FFE216
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
15
FFE116
FFE016
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
A-D converter
BRK instruction
16
FFDF16
FFDE16
At completion of A-D conversion
17
FFDD16
FFDC16
At BRK instruction execution
Timer 2
STP release timer underflow
At timer 2 underflow
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
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Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 9 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
Serial I/O2 / INT3 interrupt source bit
0 : Falling edge active
1 : Rising edge active
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
b7
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
INT0 interrupt request bit
SCL/SDA interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
INT3 / Serial I/O2 interrupt request bit
I2C interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
b0 Interrupt control register 2
(ICON2 : address 003F16)
INT0 interrupt enable bit
SCL/SDA interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 / Serial I/O2 interrupt enable bit
I2C interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 10 Structure of interrupt-related registers (1)
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
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TIMERS
Timer 1 and Timer 2
The M37516M6-XXXHP has four timers: timer X, timer Y, timer 1,
and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
b0
b7
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 11 Structure of timer XY mode register
b7
b0
Timer count source selection register
(TCSS : address 002816)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN)
Not used (returns “0” when read)
Fig. 12 Structure of timer count source selection register
M37516M6-XXXHP
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
■Note
When switching the count source by the timer 12, X and Y count
source bit, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
15/54
Data bus
f(XIN)/16
f(XIN)/2
Prescaler X latch (8)
Timer X latch (8)
Pulse width
Timer X count source selection bit measurement Timer mode
Pulse output mode
mode
Prescaler X (8)
CNTR0 active
edge selection
“0”
bit
P27/CNTR0
Event
counter
mode
“1”
Timer X count stop bit
To CNTR0 interrupt
request bit
CNTR0 active
edge selection “1”
bit
“0”
Q
Toggle flip-flop T
Q
R
Timer X latch write pulse
Pulse output mode
Port P27
latch
Port P27
direction register
To timer X interrupt
request bit
Timer X (8)
Pulse output mode
Data bus
Prescaler Y latch (8)
f(XIN)/16
f(XIN)/2
Timer Y count source selection bit
Pulse width
measurement mode
Timer mode
Pulse output mode
Prescaler Y (8)
CNTR1 active
edge selection
bit
“0”
P40/CNTR1
Event
counter
mode
“1”
Port P40
direction register
To timer Y interrupt
request bit
Timer Y (8)
Timer Y count stop bit
To CNTR1 interrupt
request bit
CNTR1 active
edge selection “1”
bit
Q
Toggle flip-flop T
Q
Port P40
latch
Timer Y latch (8)
“0”
R
Timer Y latch write pulse
Pulse output mode
Pulse output mode
Data bus
Prescaler 12 latch (8)
f(XIN)/16
f(XCIN)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 2 latch (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt
request bit
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 13 Block diagram of timer X, timer Y, timer 1, and timer 2
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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SERIAL I/O1
(1) Clock Synchronous Serial I/O Mode
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P24/RXD
Address 001A16
Shift clock
Clock control circuit
P26/SCLK
XIN
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
1/4
Address 001C16
BRG count source selection bit
1/4
P27/SRDY1
F/F
Clock control circuit
Falling-edge detector
Shift clock
P25/TXD
Transmit shift register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 14 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 15 Operation of clock synchronous serial I/O1 function
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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(2) Asynchronous Serial I/O (UART) Mode
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
Data bus
Address 001816
OE
P24/RXD
Serial I/O1 control register Address 001A16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
SP detector
Clock control circuit
UART control register
Address 001B16
Serial I/O1 synchronous clock selection bit
P26/SCLK1
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P25/TXD
Transmit shift register
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Character length selection bit
Address 001816
Data bus
Fig.16 Block diagram of UART serial I/O1
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
18/54
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1
ST
D0
Receive buffer read
signal
SP
D1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 17 Operation of UART serial I/O1 function
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
M37516M6-XXXHP
Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■Note
When using the serial I/O1, clear the I2C-BUS interface enable bit
to “0” or the SCL/SDA pin selection bit to “0”.
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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b7
b0
b7
Serial I/O1 status register
(SIOSTS : address 001916)
b0
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
b0
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
b7
Serial I/O1 control register
(SIOCON : address 001A16)
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P24 to P27 operate as serial I/O1 pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 18 Structure of serial I/O1 control registers
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
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●Serial I/O2
The serial I/O2 can be operated only as the clock synchronous
type. As a synchronous clock for serial transfer, either internal clock
or external clock can be selected by the serial I/O2 synchronous
clock selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits
selecting 6 types of clock by the internal synchronous clock selection bit (b2, b1, b0) of serial I/O2 control register 1.
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by
the P01/S OUT2, P02/S CLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is
not set to "1" automatically.
When the external clock has been selected, the contents of the
serial I/O2 register is continuously sifted while transfer clocks are
input. Accordingly, control the clock externally. Note that the SOUT2
pin does not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control
register 2 to "1" when SCLK2 is "H" after completion of data transfer.
After the next data transfer is started (the transfer clock falls), bit 7
of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is
put into the active state.
Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored
in the serial I/O2 register becomes a fractional number of bits close
to MSB if the transfer direction selection bit of serial I/O2 control
register 1 is LSB first, or a fractional number of bits close to LSB if
the said bit is MSB first. For the remaining bits, the previously received data is shifted.
At transmit operation using the clock synchronous serial I/O, the
SCMP2 signal can be output by comparing the state of the transmit
pin SOUT2 with the state of the receive pin SIN2 in synchronization
with a rise of the transfer clock. If the output level of the SOUT2 pin is
equal to the input level to the SIN2 pin, "L" is output from the SCMP2
pin. If not, "H" is output. At this time, an INT2 interrupt request can
also be generated. Select a valid edge by bit 2 of the interrupt edge
selection register (address 003A16).
b7
b0
Serial I/O2 control register 1
(SIO2CON1 : address 001516)
Internal synchronous clock selection bit
b2 b1 b0
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
SRDY2 output enable bit
0: P03 pin is normal I/O pin
1: P03 pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616)
Optional transfer bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
Serial I/O2 I/O comparison signal control bit
0: P43 I/O
1: SCMP2 output
SOUT2 pin control bit (P01)
0: Output active
1: Output high-impedance
Fig. 19 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2
The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 19.
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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Internal synchronous
clock selection bit
1/8
XCIN
1/16
"10"
Divider
Main clock division ratio
selection bits (Note)
"00"
"01"
XIN
Data bus
1/32
1/64
1/128
1/256
P03 latch
Serial I/O2 synchronous
clock selection bit
"0"
SRDY2
"1"
SRDY2 output enable bit
"1"
Synchronous circuit
SCLK2
P03/SRDY2
"0"
External clock
P02 latch
Optional transfer bits (3)
"0"
P02/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
"1"
Serial I/O2 port selection bit
P01 latch
"0"
P01/SOUT2
"1"
Serial I/O2 port selection bit
Serial I/O2 register (8)
P00/SIN2
P43 latch
"0"
D
P43/SCMP2/INT2
Q
"1"
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 20 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
Serial I/O2 output SOUT2
D0
D1
.
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SCOUT2 pin has high impedance after transfer completion.
Fig. 21 Timing chart of Serial I/O2
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GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 22 SCMP2 output operation
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
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MULTI-MASTER I2C-BUS INTERFACE
Table 4 Multi-master I2C-BUS interface functions
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial
communications.
Figure 23 shows a block diagram of the multi-master I2C-BUS interface and Table 4 lists the multi-master I 2 C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I 2C address
register, the I 2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I 2 C-BUS interface, set 1 MHz or
more to .
Item
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
System clock
= f(XIN)/2 (high-speed mode)
= f(XIN)/8 (middle-speed mode)
Note: Mitsubishi Electric Corporation assumes no responsibility for infringement of any third-party’s rights or originating in the use of the
connection control function between the I2C-BUS interface and the
ports SCL1, SCL2, SDA1 and SDA2 with the bit 6 of I2C control register (002E16).
I2C address register
b7
b0
Interrupt
generating
circuit
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
S0D
Interrupt request signal
(IICIRQ)
Address comparator
Serial data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b0
b7
2
I C data shift register
b7
b0
S0
MS
SIS SIP SSC4SSC3 SSC2 SSC1 SSC0
S2D
AL
circuit
TRX BB PIN
AL AAS AD0 LRB
T
I2C status register
S1
I2C start/stop condition
control register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
S2
I2C clock control register
Clock division
I2C clock control register
S1D
b0
b7
TISS TSEL 10BIT
SAD
ALS
ES0 BC2 BC1 BC0
S1D I 2 C control register
System clock (f)
Bit counter
Fig. 23 Block diagram of multi-master I2C-BUS interface
✽ : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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[I2C Data Shift Register (S0)] 002B16
The I2C data shift register (S0 : address 002B16) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of
the I2C control register is “1”. The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and
the MST bit of the I2C status register (address 002D16) are “1,” the
SCL is output by a write instruction to the I2C data shift register.
Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value.
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RWB
I2C address register
(S0D: address 002C 16)
Read/write bit
Slave address
Fig. 24 Structure of I2C address register
[I2C Address Register (S0D)] 002C16
The I 2C address register (address 002C 16) consists of a 7-bit
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is detected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RWB) of the I2C address register.
The RWB bit is cleared to “0” automatically when the stop condition is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address
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I2 C
Note: Do not write data into the
clock control register during transfer. If
data is written during transfer, the I 2C clock generator is reset, so
that data cannot be transferred normally.
M37516M6-XXXHP
I2C clock control register
(S2 : address 002F16)
SCL frequency control bits
Refer to Table 5.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Fig. 25 Structure of I2C clock control register
Table 5 Set values of I 2 C clock control register and SCL
frequency
Setting value of
CCR4–CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
SCL frequency
(at φ = 4 MHz, unit : kHz)
Standard clock High-speed clock
mode
mode
0
0
0
0
Setting disabled
Setting disabled
0
0
0
0
1
Setting disabled
Setting disabled
0
0
0
1
0
Setting disabled
Setting disabled
0
0
0
1
1
– (Note 2)
333
0
0
1
0
0
– (Note 2)
250
0
0
1
0
1
100
400 (Note 3)
0
0
1
1
0
83.3
166
…
0
…
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an acknowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to “1,” the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the SDA at
the occurrence of an ACK clock (makes SDA “H”) and receives the
ACK bit generated by the data receiving device.
ACK
b0
ACK FAST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
…
✽ACK clock: Clock for acknowledgment
b7
…
The I2C clock control register (address 002F16) is used to set ACK
control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 5.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I2C bus standard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) and 2 division clock.
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is automatically made “H” (ACK is not returned).
…
[I2C Clock Control Register (S2)] 002F16
500/CCR value
(Note 3)
1
1
1
0
1
17.2
1000/CCR value
(Note 3)
34.5
1
1
1
1
0
16.6
33.3
1
1
1
1
1
16.1
32.3
Notes 1: Duty of SCL clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates
from –4 to +2 machine cycles in the standard clock mode, and
fluctuates from –2 to +2 machine cycles in the high-speed clock
mode. In the case of negative fluctuation, the frequency does not
increase because “L” duration is extended instead of “H” duration
reduction.
These are value when SCL clock synchronization by the synchronous function is not performed. CCR value is the decimal
notation value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ✕ CCR value) Standard clock mode
φ/(4 ✕ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by
setting the SCL frequency control bits CCR4 to CCR0.
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[I2C Control Register (S1D)] 002E16
The I2C control register (address 002E16) controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. The I2C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of address 002F 16)) have been transferred, and
BC0 to BC2 are returned to “0002”.
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C-BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ES0 = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I2C
status register at address 002D16 ).
• Writing data to the I2C data shift register (address 002B16) is disabled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
when a general call (refer to “I 2C Status Register,” bit 1) is received, transfer processing can be performed. When this bit is set
to “1,” the free data format is selected, so that slave addresses are
not recognized.
•Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit
is set to “0,” the 7-bit addressing format is selected. In this case,
only the high-order 7 bits (slave address) of the I2C address register (address 002C16) are compared with address data. When this
bit is set to “1,” the 10-bit addressing format is selected, and all
the bits of the I 2C address register are compared with address
data.
•Bit 6: SDA/SCL pin selection bit
This bit selects the input/output pins of SCL and SDA of the multimaster I2C-BUS interface.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the
multi-master I2C-BUS interface.
TSEL
SCL1/P23
SCL
SCL2/TxD/P25
Multi-master
I2C-BUS interface
TSEL
TSEL
SDA1/P22
SDA
SDA2/RxD/P24
TSEL
Fig. 26 SDA/SCL pin selection bit
b7
10 BIT
TISS TSEL SAD
b0
ALS ES0 BC2 BC1 BC0
I2C control register
(S1D : address 002E16)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I2C-BUS interface
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
SDA/SCL pin selection bit
0 : Connect to ports P22, P23
1 : Connect to ports P24, P25
I2C-BUS interface pin input
level selection bit
0 : CMOS input
1 : SMBUS input
Fig. 27 Structure of I2C control register
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[I2C Status Register (S1)] 002D16
The I2C status register (address 002D16) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I2C data shift register
(address 002B16).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call: The master transmits the general call address “0016 ” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 002C16).
• A general call is received.
➁ In the slave receive mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I2C address register (8 bits consisting of slave address and RWB bit), the first
bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I 2C
data shift register (address 002B16) when ES0 is set to “1” or
reset.
•Bit 3: Arbitration lost✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When arbitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and address data transmitted by another master device.
•Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 29 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I2 C data shift register (address 002B16). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address agreement or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I2C start/stop condition
control register (address 003016). When the ES0 bit of the I 2C
control register (address 002E16) is “0” or reset, the BB flag is set
to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Generating Method” described later.
✽Arbitration lost :The status in which communication as a master is disabled.
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•Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condition
are generated. Additionally, the clocks required for data communication are generated on the SCL.
This bit is set to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transfer when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START condition duplication preventing function (Note).
• At reset
Note: START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after confirming that the BB flag is “0” in the procedure of a START condition
occurrence. However, when a START condition by another master
device occurs and the BB flag is set to “1” immediately after the contents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
b7
b0
MST TRX BB PIN AL AAS AD0 LRB
I2C status register
(S1 : address 002D 16)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
SCL pin low hold bit
0 : SCL pin low hold
1 : SCL pin low release
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bits and flags can be read out, but cannot
be written.
Write “0” to these bits at writing.
Fig. 28 Structure of I2C status register
SCL
PIN
IICIRQ
Fig. 29 Interrupt request signal generating timing
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START Condition Generating Method
START/STOP Condition Detecting Operation
When writing “1” to the MST, TRX, and BB bits of the I 2C status
register (address 002D16) at the same time after writing the slave
address to the I2 C data shift register (address 002B16) with the
condition in which the ES0 bit of the I2C control register (address
002E16) is “1” and the BB flag is “0”, a START condition occurs.
After that, the bit counter becomes “000 2” and an SCL for 1 byte is
output. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 30, the START condition generating timing diagram, and
Table 6, the START condition generating timing table.
The START/STOP condition detection operations are shown in
Figures 32, 33, and Table 8. The START/STOP condition is set by
the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL release time, setup time, and hold time (see Table 8).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 8, the BB flag set/
reset time.
AAA
AAA
I2C status register
write signal
SCL
Setup
time
SDA
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “IICIRQ” occurs to the CPU.
Fig. 30 START condition generating timing diagram
Table 6 START condition generating timing table
Standard clock mode High-speed clock mode
Item
2.5 us (10 cycles)
5.0 us (20 cycles)
Setup time
2.5 us (10 cycles)
5.0 us (20 cycles)
Hold time
Note: Absolute time at
= 4 MHz. The value in parentheses denotes the
number of cycles.
SCL
SDA
I 2C
When the ES0 bit of the
control register (address 002E16) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I2C status register (address 002D16) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 31, the STOP condition generating timing
diagram, and Table 7, the STOP condition generating timing table.
SCL
SDA
Setup
time
AAA
AAA
Hold time
Hold time
BB flag
set
time
AAA
AAA
AAA
AAA
Fig. 32 START condition detecting timing diagram
SCL release time
SCL
BB flag
Setup
time
Hold time
BB flag
reset
time
Fig. 33 STOP condition detecting timing diagram
Table 8 START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
SCL release time
Setup time
Hold time
I2C status register
write signal
Setup
time
BB flag
SDA
STOP Condition Generating Method
AAAA
AAA
SCL release time
Hold time
BB flag set/
reset time
SCC value + 1 cycle (6.25 us)
4 cycles (1.0 us)
SCC value + 1 cycle < 4.0 us (3.125 us)
2 cycles (1.0 us)
2
SCC value + 1 cycle < 4.0 us (3.125 us) 2 cycles (0.5 us)
2
SCC value –1 + 2 cycles (3.375 us) 3.5 cycles (0.875 us)
2
Note: Unit : Cycle number of system clock
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at = 4 MHz.
Fig. 31 STOP condition generating timing diagram
Table 7 STOP condition generating timing table
Standard clock mode
High-speed clock mode
Item
5.0 us (20 cycles)
3.0 us (12 cycles)
Setup time
4.5 us (18 cycles)
2.5 us (10 cycles)
Hold time
Note: Absolute time at
= 4 MHz. The value in parentheses denotes the
number of cycles.
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[I2C START/STOP Condition Control Register
(S2D)] 003016
The I2C START/STOP condition control register (address 003016)
controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bit (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 8.
Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Refer to Table 9, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or
SDA pin interrupt pin.
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I 2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2 C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
M37516M6-XXXHP
Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
➀ 7-bit addressing format
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
the I 2C control register (address 002E16) to “0.” The first 7-bit
address data transmitted from the master is compared with the
high-order 7-bit slave address stored in the I2C address register
(address 002C16). At the time of this comparison, address comparison of the RWB bit of the I2 C address register (address
002C 16) is not performed. For the data transmission format
when the 7-bit addressing format is selected, refer to Figure 35,
(1) and (2).
➁ 10-bit addressing format
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
the I 2C control register (address 002E 16) to “1.” An address
comparison is performed between the first-byte address data
transmitted from the master and the 8-bit slave address stored
in the I2C address register (address 002C16). At the time of this
comparison, an address comparison between the RWB bit of
the I 2C address register (address 002C 16) and the R/W bit
which is the last bit of the address data transmitted from the
master is made. In the 10-bit addressing mode, the RWB bit
which is the last bit of the address data not only specifies the
direction of communication for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
the AAS bit of the I2C status register (address 002D16) is set to
“1.” After the second-byte address data is stored into the I 2C
data shift register (address 002B16), perform an address comparison between the second-byte data and the slave address
by software. When the address data of the 2 bytes agree with
the slave address, set the RWB bit of the I2C address register
(address 002C16) to “1” by software. This processing can make
the 7-bit slave address and R/W data agree, which are received after a RESTART condition is detected, with the value of
the I2C address register (address 002C16). For the data transmission format when the 10-bit addressing format is selected,
refer to Figure 35, (3) and (4).
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b7
b0
SIS
SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C START/STOP condition
control register
(S2D : address 003016)
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin selection bit
0 : SDA valid
1 : SCL valid
Reserved
Do not write “1” to this bit.
Fig. 34 Structure of I2C START/STOP condition control register
Table 9 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
Main clock
divide ratio
System
clock φ
(MHz)
8
2
4
8
8
1
4
2
2
2
2
1
START/STOP
condition
control register
SCL release time
(µs)
Setup time
(µs)
Hold time
(µs)
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
3.375 µs (13.5 cycles)
3.125 µs (12.5 cycles)
2.5 µs (2.5 cycles)
3.25 µs (6.5 cycles)
2.75 µs (5.5 cycles)
2.5 µs (2.5 cycles)
Note: Do not set “000002” or an odd number to the START/STOP condition set bit (SSC4 to SSC0).
S
Slave address R/W
7 bits
A
“0”
Data
A
1 to 8 bits
Data
A/A
P
A
P
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave address R/W
7 bits
A
“1”
Data
A
1 to 8 bits
Data
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
7 bits
A
“0”
Slave address
2nd bytes
A
Data
1 to 8 bits
8 bits
A
Data
A/A
P
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd bytes
A
Sr
Slave address
R/W
1st 7 bits
“1”
7 bits
“0”
8 bits
7 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
A
Data
1 to 8 bits
A
Data
A
P
1 to 8 bits
: Master to slave
: Slave to master
Fig. 35 Address data communication format
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Example of Master Transmission
Example of Slave Reception
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
(1) Set a slave address in the high-order 7 bits of the I2C address
register (address 002C16) and “0” into the RWB bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting “85 16”
in the I2C clock control register (address 002F16).
(3) Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
(1) Set a slave address in the high-order 7 bits of the I2C address
register (address 002C16) and “0” in the RWB bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting
“2516” in the I2C clock control register (address 002F16).
(3) Set “0016” in the I2C status register (address 002D16) so that
transmission/reception mode can become initializing condition.
(4) Set a communication enable status by setting “0816” in the I2C
control register (address 002E16).
(5) When a START condition is received, an address comparison
is performed.
(6) •When all transmitted addresses are “0” (general call):
AD0 of the I2C status register (address 002D16 ) is set to “1”
and an interrupt request signal occurs.
• When the transmitted addresses agree with the address set
in (1):
ASS of the I2C status register (address 002D16) is set to “1”
and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 002D16) are set to “0” and no interrupt
request signal occurs.
(7) Set dummy data in the I2C data shift register (address
002B16).
(8) When receiving control data of more than 1 byte, repeat step
(7).
(9) When a STOP condition is detected, the communication ends.
(4) Set a communication enable status by setting “0816” in the I2C
control register (address 002E16).
(5) Confirm the bus free condition by the BB flag of the I2C status
register (address 002D16).
(6) Set the address data of the destination of transmission in the
high-order 7 bits of the I2C data shift register (address 002B16)
and set “0” in the least significant bit.
(7) Set “F016” in the I2C status register (address 002D16) to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occur.
(8) Set transmit data in the I 2 C data shift register (address
002B16). At this time, an SCL and an ACK clock automatically
occur.
(9) When transmitting control data of more than 1 byte, repeat
step (8).
(10) Set “D016” in the I2C status register (address 002D16) to generate a STOP condition if ACK is not returned from slave
reception side or transmission ends.
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■Precautions when using multi-master I2C-BUS
interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I2C-BUS interface are described below.
• I2C data shift register (S0: address 002B16)
When executing the read-modify-write instruction for this register during transfer, data may become a value not intended.
• I2C address register (S0D: address 002C16)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
• I2C status register (S1: address 002D16)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
• I2C control register (S1D: address 002E16)
When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
• I2C clock control register (S2: address 002F16)
The read-modify-write instruction can be executed for this register.
• I 2 C START/STOP condition control register (S2D: address
003016)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 5.
::
LDA —
(Taking out of slave address value)
SEI
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI
(Interrupt enabled)
::
BUSBUSY:
CLI
(Interrupt enabled)
::
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the generating procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0.”
::
LDM #$00, S1
(Select slave receive mode)
LDA —
(Taking out of slave address value)
SEI
(Interrupt disabled)
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of RESTART condition generating)
CLI
(Interrupt enabled)
::
2. Select the slave receive mode when the PIN bit is “0.” Do not
write “1” to the PIN bit. Neither “0” nor “1” is specified for the
writing to the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
3. The SCL pin is released by writing the slave address value to
the I2C data shift register.
4. Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
2. Use “Branch on Bit Set” of “BBS 5, $002D, –” for the BB flag
confirming and branch process.
3. Use “STA $2B, STX $2B” or “STY $2B” of the zero page addressing instruction for writing the slave address value to the
I2C data shift register.
4. Execute the branch instruction of above 2 and the store instruction of above 3 continuously shown the above procedure
example.
5. Disable interrupts during the following three process steps:
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PULSE WIDTH MODULATION (PWM)
The M37516M6-XXXHP has a PWM function with an 8-bit resolution, based on a signal that is the clock input X IN or that clock
input divided by 2.
Data Setting
The PWM output pin also functions as port P44. Set the PWM period by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ✕ (n+1) / f(XIN)
= 31.875 ✕ (n+1) us
(when f(XIN) = 8 MHz, count source is f(XIN) )
Output pulse “H” term = PWM period ✕ m / 255
= 0.125 ✕ (n+1) ✕ m us
(when f(XIN) = 8 MHz, count source is f(XIN))
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
31.875 ✕ m ✕ (n+1)
255
us
PWM output
T = [31.875 ✕ (n+1)] us
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz,
count source is f(XIN))
Fig. 36 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
PWM prescaler
PWM register
Count source
selection bit
“0”
XIN
1/2
Port P44
“1”
Port P44 latch
PWM enable bit
Fig. 37 Block diagram of PWM function
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b7
b0
PWM control register
(PWMCON : address 001D 16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN)
1: f(XIN)/2
Not used (return “0” when read)
Fig. 38 Structure of PWM control register
A
B
B = C
T2
T
C
PWM output
T
PWM register
write signal
T
T2
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 39 PWM output timing when PWM register or PWM prescaler is changed
■Note
The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin.
The length of this "L" level output is as follows:
n+1
2 • f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
n+1
f(XIN)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
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A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b0
b7
AD control register
(ADCON : address 003416)
Analog input pin selection bits
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion
b2 b1 b0
0
0
0
0
1
1
1
1
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
0
0
1
1
0
0
1
1
0: P30/AN0
1: P31/AN1
0: P32/AN2
1: P33/AN3
0: P34/AN4
1: P35/AN5
0: P36/AN6
1: P37/AN7
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Comparison Voltage Generator
Not used (returns “0” when read)
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024 and outputs the divided voltages.
Fig. 40 Structure of AD control register
Channel Selector
10-bit reading
(Read address 003616 before 003516)
The channel selector selects one of ports P30/AN0 to P37/AN7 and
inputs the voltage to the comparator.
b7
Comparator and Control Circuit
(Address 003616)
b0
b9 b8
b0
b7
b7 b6 b5 b4 b3 b2 b1 b0
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(X IN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
(Address 003516)
Note : The high-order 6 bits of address 003616 become “0”
at reading.
8-bit reading (Read only address 003516)
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 41 Structure of A-D conversion registers
Data bus
AD control register
(Address 003416)
b7
b0
3
A-D interrupt request
A-D control circuit
Channel selector
P30/AN0
P31/AN1
P32/AN2
P33/AN3
P34/AN4
P35/AN5
P36/AN6
P37/AN7
Comparator
A-D conversion high-order register (Address 003616)
A-D conversion low-order register (Address 003516)
10
Resistor ladder
VREF AVSS
Fig. 42 Block diagram of A-D converter
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WATCHDOG TIMER
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 0039 16) may be
started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after resetting.
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L is set to “FF16.”
“FF16” is set when
watchdog timer
control register is
written to.
XCIN
XIN
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“10”
Main clock division
ratio selection bits
(Note)
Data bus
Watchdog timer L (8)
1/16
“1”
“00”
“01”
Watchdog timer H (8)
Watchdog timer H count
source selection bit
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 43 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 0039 16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 44 Structure of Watchdog timer control register
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RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L"
level for 2 µs or more. Then the RESET pin is returned to an "H"
level (the power source voltage must be between 2.7 V and 5.5 V,
and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in
address FFFD16 (high-order byte) and address FFFC16 (low-order
byte). Make sure that the reset input voltage is less than 0.54 V for
VCC of 2.7 V.
Poweron
RESET
Power source
voltage
0V
VCC
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 45 Reset circuit example
XIN
φ
RESET
RESETOUT
?
?
Address
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
?
Data
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles
Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except X IN and RESET are internals.
Fig. 46 Reset sequence
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Address Register contents
(1)
Port P0 direction register (P0D)
000116
0016
(2)
Port P1 direction register (P1D)
000316
0016
(3)
Port P2 direction register (P2D)
000516
0016
(4)
Port P3 direction register (P3D)
000716
0016
(5)
Port P4 direction register (P4D)
000916
0016
(6)
Serial I/O status register (SIOSTS)
001916 1 0 0 0 0 0 0 0
(7)
Serial I/O control register (SIOCON)
001A16
(8)
UART control register (UARTCON)
001B16 1 1 1 0 0 0 0 0
(9)
PWM control register (PWMCON)
001D16
0016
(10) Prescaler 12 (PRE12)
002016
FF16
(11) Timer 1 (T1)
002116
0116
(12) Timer 2 (T2)
002216
0016
(13) Timer XY mode register (TM)
002316
0016
(14) Prescaler X (PREX)
002416
FF16
(15) Timer X (TX)
002516
FF16
(16) Prescaler Y (PREY)
002616
FF16
(17) Timer Y (TY)
002716
FF16
(18) Timer count source select register
002816
0016
(19) I2C address register (S0D)
002C16
0016
(20) I2C status register (S1)
002D16 0 0 0 1 0 0 0 X
(21) I2C control register (S1D)
002E16
0016
(22) I2C clock control register (S2)
002F16
0016
(23) I2C start/stop condition control register (S2D)
003016 0 0 0 X X X X X
(24) AD control register (ADCON)
003416 0 0 0 1 0 0 0 0
(25) MISRG
003816
(26) Watchdog timer control register (WDTCON)
003916 0 0 1 1 1 1 1 1
(27) Interrupt edge selection register (INTEDGE)
003A16
(28) CPU mode register (CPUM)
003B16 0 1 0 0 1 0 0 0
(29) Interrupt request register 1 (IREQ1)
003C16
0016
(30) Interrupt request register 2 (IREQ2)
003D16
0016
(31) Interrupt control register 1 (ICON1)
003E16
0016
(32) Interrupt control register 2 (ICON2)
003F16
0016
(33) Processor status register
(34) Program counter
Note : X indicates Not fixed .
0016
0016
0016
(PS) X X X X X 1 X X
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
Fig. 47 Internal status at reset
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CLOCK GENERATING CIRCUIT
be generated.
The M37516M6-XXXHP has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between
XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values.
No external resistor is needed between X IN and X OUT since a
feed-back resistor exists on-chip. However, an external feed-back
resistor is needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After reset, this mode is selected.
(2) High-speed mode
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before executing of the STP or WIT instruction.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruction.
The internal clock φ is half the frequency of XIN.
■Note
(3) Low-speed mode
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
The internal clock φ is half the frequency of XCIN.
■Note
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3•f(XCIN).
XCIN
XCOUT
Rf
XIN
XOUT
Rd
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
CCIN
M37516M6-XXXHP
CIN
COUT
Fig. 48 Ceramic resonator circuit
Oscillation Control
(1) Stop mode
XCIN
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1.
Either X IN or X CIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is received, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
CCOUT
XCOUT
Rf
XIN
XOUT
Open
Rd
External oscillation
circuit
CCIN
CCOUT
Vcc
Vss
Fig. 49 External clock input circuit
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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b7
Middle-speed mode automatic switch set bit
b0
By setting the middle-speed mode automatic switch set bit to “1”
while operating in the low-speed mode, XIN oscillation automatically starts and the mode is automatically switched to the
middle-speed mode when defecting a rising/falling edge of the
SCL or SDA pin. The middle-speed automatic switch wait time set
bit can select the switch timing from the low-speed to the middlespeed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5
machine cycles in the low-speed mode. Select it according to oscillation start characteristics of used XIN oscillator.
The middle-speed mode automatic switch start bit is used to automatically make to X IN oscillation start and switch to the
middle-speed mode by setting this bit to “1” while operating in the
low-speed mode.
MISRG
(MISRG : address 0038 16)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01 16 ” to Timer 1,
“FF 16 ” to Prescaler 12
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Fig. 50 Structure of MISRG
XCOUT
XCIN
“0”
“1”
Port XC
switch bit
XOUT
XIN
Main clock division ratio
selection bits (Note)
Low-speed mode
1/2
1/4
Prescaler 12
1/2
High-speed or
middle-speed
mode
FF16
Timer 1
0116
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Q
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Note 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
2: When the oscillation stabilizing time set after STP instruction released bit is “0”.
Fig. 51 System clock generating circuit block diagram (Single-chip mode)
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
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Reset
CM4
“1”
4
Middle-speed mode
(f( )=1 MHz)
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
”
“0
“0”
CM
“0 4
”
CM
“1 6
“1
”
”
”
“0
CM ”
“1 6
CM ”
“1
“0”
“0
”
CM6
“1”
High-speed mode
(f( )=4 MHz)
“0”
CM
“0 7
”
CM
“1
“1 6
”
”
“0
”
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
“0”
“0”
CM7=0
CM6=1
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(f( )=4 MHz)
CM7=0
CM6=0
CM5=0(8 MHz oscillating)
CM4=0(32 kHz stopped)
CM4
“1”
CM6
“1”
CM7
“1”
Middle-speed mode
(f( )=1 MHz)
Low-speed mode
(f( )=16 kHz)
b7
CM5
“1”
“0”
CM7=1
CM6=0
CM5=0(8 MHz oscillating)
CM4=1(32 kHz oscillating)
Low-speed mode
(f( )=16 kHz)
CM7=1
CM6=0
CM5=1(8 MHz stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0 0:
= f(XIN)/2 ( High-speed mode)
0 1:
= f(XIN)/8 (Middle-speed mode)
1 0:
= f(XCIN)/2 (Low-speed mode)
1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 16ms occurs in low-speed mode if Timer 12 count source selection bit is "0".
(2) After the clock is restarted, a delay of approximately 250ms occurs in low-speed mode if Timer 12 count source selection bit is "1".
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. f indicates the internal clock.
Fig. 52 State transitions of system clock
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
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NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 500 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt
request register, execute at least one instruction before performing a BBC or BBS instruction.
The instruction execution time is obtained by multiplying the frequency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
NOTES ON USAGE
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (V SS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF 0.1µF is recommended.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1.”
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmission is completed.
When an external clock is used as synchronous clock in serial I/
O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H.”
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
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ELECTRICAL CHARACTERISTICS
Table 11 Absolute maximum ratings
Symbol
VCC
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P37, P40–P47,
VREF
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P37, P40–P47,
XOUT
Output voltage P22, P23
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based on VSS.
Output transistors are cut off.
Ratings
–0.3 to 6.5
Unit
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to VCC +0.3
V
V
V
–0.3 to VCC +0.3
V
–0.3 to 5.8
300
–20 to 85
–40 to 125
V
mW
°C
°C
Ta = 25 °C
Table 12 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Power source voltage (At 8 MHz)
Power source voltage (At 4 MHz)
Power source voltage
A-D convert reference voltage
Analog power source voltage
Analog input voltage
AN0–AN7
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47
“H” input voltage (when I2C-BUS input level is selected)
SDA1, SCL1
“H” input voltage (when I2C-BUS input level is selected)
SDA2, SCL2
“H” input voltage (when SMBUS input level is selected)
SDA1, SCL1
“H” input voltage (when SMBUS input level is selected)
SDA2, SCL2
“H” input voltage
RESET, XIN, CNVSS
VCC
VSS
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIH
VIL
“L” input voltage
VIL
VIL
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47
“L” input voltage (when I2C-BUS input level is selected)
SDA1, SDA2, SCL1, SCL2
“L” input voltage (when SMBUS input level is selected)
SDA1, SDA2, SCL1, SCL2
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
P00–P07, P10–P17, P30–P37 (Note)
P20, P21, P24–P27, P40–P47 (Note)
P00–P07, P30–P37 (Note)
P10–P17 (Note)
P20–P27,P40–P47 (Note)
P00–P07, P10–P17, P30–P37 (Note)
P20, P21, P24–P27, P40–P47 (Note)
P00–P07, P30–P37 (Note)
P10–P17 (Note)
P20–P27,P40–P47 (Note)
Min.
4.0
2.7
Limits
Typ.
5.0
5.0
0
Max.
5.5
5.5
Unit
V
AVSS
0.8VCC
VCC
VCC
V
V
V
V
V
0.7VCC
5.8
V
0.7VCC
VCC
V
1.4
5.8
V
1.4
VCC
V
0.8VCC
0
VCC
0.2VCC
V
0
0.3VCC
V
0
0.6
V
0
0.2VCC
0.16VCC
V
V
–80
–80
80
80
80
–40
–40
40
40
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2.0
VCC
0
0
V
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
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45/54
Table 13 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
f(XIN)
Parameter
Min.
Limits
Typ.
“H” peak output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P37,
P40–P47 (Note 1)
“L” peak output current
P00–P07, P20–P27, P30–P37, P40–P47 (Note 1)
“L” peak output current
P10–P17 (Note 1)
“H” average output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P37,
P40–P47 (Note 2)
“L” average output current
P00–P07, P20–P27, P30–P37, P40–P47 (Note 2)
“L” peak output current
P10–P17 (Note 2)
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
Max.
Unit
–10
mA
10
mA
20
mA
–5
mA
5
mA
15
8
mA
MHz
4
kHz
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46/54
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
Table 14 Electrical characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
“H” output voltage
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P37, P40–P47
(Note)
“L” output voltage
P00–P07, P20–P27, P30–P37,
P40–P47
VOH
VOL
“L” output voltage
P10–P17
VOL
IOH = –10 mA
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
Min.
Typ.
Unit
Max.
VCC–2.0
V
VCC–1.0
V
2.0
V
1.0
V
2.0
V
1.0
V
VT+–VT–
Hysteresis
CNTR0, CNTR1, INT0–INT3
0.4
V
VT+–VT–
Hysteresis
RxD, SCLK
0.5
V
0.5
V
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
VRAM
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P37, P40–P47
“H” input current RESET, CNVSS
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27
P30–P37, P40–P47
“L” input current RESET,CNVSS
“L” input current XIN
RAM hold voltage
5.0
µA
5.0
µA
µA
VI = VSS
–5.0
µA
VI = VSS
VI = VSS
When clock stopped
–5.0
µA
µA
V
VI = VCC
VI = VCC
VI = VCC
4
–4
5.5
2.0
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
M37516M6-XXXHP
GNOK-M37516M6-XXXHP-50
(MSETSU 2)
PA
GE
47/54
Table 15 Electrical characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source current
Test conditions
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is
executed
f(XIN) = 8 MHz
All oscillation stopped
(in STP state)
Output transistors “off”
M37516M6-XXXHP
Ta = 25 °C
Min.
Typ.
Max.
6.8
13
mA
1.6
mA
60
200
µA
20
40
µA
20
55
µA
5.0
10.0
µA
4.0
7.0
mA
1.5
mA
800
µA
0.1
1.0
µA
10
µA
Ta = 85 °C
GNOK-M37516M6-XXXHP-50
Unit
(MSETSU 2)
PA
GE
48/54
Table 16 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Symbol
Parameter
–
–
tCONV
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
RLADDER
IVREF
Ladder resistor
Reference power source input current
II(AD)
A-D port input current
M37516M6-XXXHP
Test conditions
Limits
Min.
High-speed mode,
middle-speed mode
Low-speed mode
VREF “on” VREF = 5.0 V
VREF “off”
50
Typ.
bit
LSB
tc(φ)
200
5
5.0
µs
kΩ
µA
µA
µA
40
35
150
0.5
GNOK-M37516M6-XXXHP-50
Unit
Max.
10
±4
61
(MSETSU 2)
PA
GE
49/54
TIMING REQUIREMENTS
Table 17 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Limits
Min.
2
125
50
50
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 18 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Limits
Min.
2
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
M37516M6-XXXHP
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(MSETSU 2)
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Table 19 Switching characteristics 1
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Test conditions
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Limits
Min.
Typ.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140
–30
30
30
Fig. 53
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
10
10
30
30
30
Notes 1: For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 20 Switching characteristics 2
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Symbol
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tr (CMOS)
tf (CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Test conditions
Limits
Min.
Typ.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
Unit
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
350
–30
50
50
Fig. 53
tC(SCLK2)/2–240
tC(SCLK2)/2–240
400
0
20
20
50
50
50
Notes 1: For tWH(SCLK1), tWL(SCLK1), when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
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Measurement output pin
100pF
CMOS output
Fig. 53 Circuit for measuring output switching characteristics
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tC(CNTR)
tWH(CNTR)
CNTR0
CNTR1
tWL(CNTR)
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0 to INT3
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
SCLK1
SCLK2
tf
0.2VCC
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
tr
0.8VCC
0.2VCC
tsu(RxD-SCLK1),
tsu(SIN2-SCLK2)
RXD
SIN2
th(SCLK1-RxD),
th(SCLK2-SIN2)
0.8VCC
0.2VCC
td(SCLK1-TXD),
td(SCLK2-SOUT2)
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
TXD
SOUT2
Fig. 54 Timing diagram
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MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Table 21 Multi-master I2C-BUS bus line characteristics
Standard clock mode High-speed clock mode
Symbol
Parameter
Min.
Max.
Max.
Unit
tBUF
Bus free time
4.7
Min.
1.3
tHD;STA
Hold time for START condition
4.0
0.6
µs
tLOW
Hold time for SCL clock = “0”
4.7
1.3
µs
tR
Rising time of both SCL and SDA signals
1000
20+0.1Cb
µs
300
ns
0.9
µs
tHD;DAT
Data hold time
tHIGH
Hold time for SCL clock = “1”
tF
Falling time of both SCL and SDA signals
tSU;DAT
Data setup time
250
100
ns
tSU;STA
Setup time for repeated START condition
4.7
0.6
µs
tSU;STO
Setup time for STOP condition
4.0
0.6
µs
0
0
4.0
0.6
300
µs
20+0.1Cb
300
ns
Note: Cb = total capacitance of 1 bus line
SDA
tHD:STA
tBUF
tLOW
SCL
P
tR
tF
Sr
S
tHD:STA
tsu:STO
tHD:DAT
tHIGH
tsu:DAT
P
tsu:STA
S : START condition
Sr : RESTART condition
P : STOP condition
Fig. 55 Timing diagram of multi-master I2C-BUS
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(MSETSU 2)
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