Cypress CY7C4022KV13-933FCXC 72-mbit qdrâ ¢-iv xp sram Datasheet

CY7C4022KV13/CY7C4042KV13
72-Mbit QDR™-IV XP SRAM
72-Mbit QDR™-IV XP SRAM
Features
■
Configurations
72-Mbit density (4M × 18, 2M × 36)
[1]
CY7C4022KV13 – 4M × 18
■
Total Random Transaction Rate
of 2132 MT/s
■
Maximum operating frequency of 1066 MHz
■
Read latency of 8.0 clock cycles and Write Latency of 5.0 clock
cycles
■
8 bank architecture enables one access per bank per cycle
■
Two-word burst on all accesses
■
Dual independent bi-directional data ports
❐ Double data rate (DDR) data ports
❐ Supports concurrent read/write transactions on both ports
■
Single address port used to control both data ports
❐ DDR address signaling
■
Single data rate (SDR) control signaling
■
High-speed transceiver logic (HSTL) and stub series
terminated logic (SSTL) compatible signaling (JESD8-16A
compliant)
❐ I/O VDDQ = 1.2 V ± 50 mV or 1.25 V ± 50 mV
CY7C4042KV13 – 2M × 36
Functional Description
The QDR™-IV XP (Xtreme Performance) SRAM is a
high-performance memory device that has been optimized to
maximize the number of random transactions per second by the
use of two independent bi-directional data ports.
These ports are equipped with DDR interfaces and designated
as port A and port B respectively. Accesses to these two data
ports are concurrent and independent of each other. Access to
each port is through a common address bus running at DDR. The
control signals are running at SDR and determine if a read or
write should be performed.
There are three types of differential clocks:
■
(CK, CK#) for address and command clocking
■
(DKA, DKA#, DKB, DKB#) for data input clocking
■
(QKA, QKA#, QKB, QKB#) for data output clocking
■
Pseudo open drain (POD) signaling (JESD8-24 compliant)
❐ I/O VDDQ = 1.1 V ± 50 mV or 1.2 V ± 50 mV
Addresses for port A are latched on the rising edge of the input
clock (CK), and addresses for port B are latched on the falling
edge of the input clock (CK).
■
Core voltage
❐ VDD = 1.3 V ± 40 mV
■
On-die termination (ODT)
❐ Programmable for clock, address/command and data inputs
This QDR-IV XP SRAM is internally partitioned into eight internal
banks. Each bank can be accessed once for every clock cycle
enabling the SRAM to operate at high frequencies.
■
Internal self calibration of output impedance through ZQ pin
■
Bus inversion to reduce switching noise and power
❐ Programmable on/off for address and data
■
Address bus parity error protection
■
Training sequence for per-bit deskew
■
On-chip error correction code (ECC) to reduce soft error rate
(SER)
■
JTAG 1149.1 test access port (JESD8-26 compliant)
❐ 1.3-V LVCMOS signaling
■
Available in 361-ball FCBGA Pb-free package (21 × 21 mm)
The QDR-IV XP SRAM device is offered in a two-word burst
option and is available in × 18 and × 36 bus width configurations.
For an × 18 bus width configuration, there are 22 address bits,
and for an × 36 bus width configuration, there are 21 address bits
respectively.
An on-chip ECC circuitry detects and corrects all single-bit
memory errors, including those induced by soft error events such
as cosmic rays, alpha particles, etc. The resulting SER of these
devices is expected to be less than 0.01 FITs/Mb, a
four-order-of-magnitude improvement over previous generation
SRAMs.
For a complete list of related resources, click here.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
× 18
× 36
QDR-IV
2132 (MT/s)
1066
4100
4500
QDR-IV
1866 (MT/s)
933
3400
4000
Unit
MHz
mA
Note
1. Random Transaction Rate (RTR) is defined as the number of fully random memory accesses (reads or writes) that can be performed on the memory. RTR is measured
in million transactions per second.
Cypress Semiconductor Corporation
Document Number: 001-79552 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2017
CY7C4022KV13/CY7C4042KV13
Logic Block Diagram – CY7C4022KV13
Document Number: 001-79552 Rev. *O
Page 2 of 46
CY7C4022KV13/CY7C4042KV13
Logic Block Diagram – CY7C4042KV13
Document Number: 001-79552 Rev. *O
Page 3 of 46
CY7C4022KV13/CY7C4042KV13
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Clocking ....................................................................... 9
Command Cycles ........................................................ 9
Read and Write Data Cycles ....................................... 9
Banking Operation ....................................................... 9
Address and Data Bus Inversion ................................. 9
Address Parity ........................................................... 10
Port Enable ................................................................ 10
On-Die Termination (ODT) Operation ....................... 10
JTAG Operation ........................................................ 10
Power Up and Reset ................................................. 10
Operation Modes ....................................................... 11
Deskew Training Sequence ...................................... 12
I/O Signaling Standards ............................................ 12
Initialization ................................................................ 13
Configuration Registers ............................................. 14
Configuration Registers Description .......................... 15
Configuration Register Definitions ............................. 15
I/O Type and Port Enable Bit Definitions ................... 17
ODT Termination Bit Definitions ................................ 18
Drive Strength Bit Definitions .................................... 19
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 20
Test Access Port ....................................................... 20
TAP Registers ........................................................... 20
TAP Instruction Set ................................................... 20
TAP Controller State Diagram ....................................... 22
TAP Controller Block Diagram ...................................... 23
TAP Electrical Characteristics ...................................... 24
Document Number: 001-79552 Rev. *O
TAP AC Switching Characteristics ............................... 24
TAP Timing Diagram ...................................................... 25
Identification Register Definitions ................................ 26
Scan Register Sizes ....................................................... 26
Instruction Codes ........................................................... 26
Boundary Scan Order .................................................... 27
Maximum Ratings ........................................................... 30
Operating Range ............................................................. 30
Neutron Soft Error Immunity ......................................... 30
Electrical Characteristics ............................................... 30
Capacitance .................................................................... 32
Thermal Resistance ........................................................ 32
AC Test Load and Waveform ......................................... 32
Switching Characteristics .............................................. 33
Switching Waveforms .................................................... 35
Ordering Information ...................................................... 42
Ordering Code Definitions ......................................... 42
Package Diagram ............................................................ 43
Acronyms ........................................................................ 44
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Document History Page ................................................. 45
Sales, Solutions, and Legal Information ...................... 46
Worldwide Sales and Design Support ....................... 46
Products .................................................................... 46
PSoC® Solutions ...................................................... 46
Cypress Developer Community ................................. 46
Technical Support ..................................................... 46
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CY7C4022KV13/CY7C4042KV13
Pin Configurations
Figure 1. 361-ball FCBGA Pinout
CY7C4022KV13 (4M × 18)
Document Number: 001-79552 Rev. *O
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CY7C4022KV13/CY7C4042KV13
Pin Configurations (continued)
Figure 2. 361-ball FCBGA Pinout
CY7C4042KV13 (2M × 36)
Document Number: 001-79552 Rev. *O
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CY7C4022KV13/CY7C4042KV13
Pin Definitions
Pin Name
I/Os
Pin Description
Input Clock
Address/Command Input Clock. CK and CK# are differential clock inputs. All control and address
input signals are sampled on both the rising and falling edges of CK. The rising edge of CK samples
the control and address inputs for port A, while the falling edge of CK samples the control and address
inputs for port B. CK# is 180 degrees out of phase with CK.
A[x:0]
Input
Address Inputs. Sampled on the rising edge of both CK and CK# clocks during active read and write
operations. These address inputs are used for read and write operations on both ports. The lower
three address pins (A0, A1, and A2) select the bank that will be accessed. These address inputs are
also known as bank address pins.
For (× 36) data width - Address inputs A[19:0] are used and A[24:20] are reserved.
For (× 18) data width - Address inputs A[20:0] are used and A[24:21] are reserved.
The reserved address inputs are No Connects and may be tied high, tied low, or left floating.
AP
Input
Address Parity Input. Used to provide even parity across the address pins.
For (× 36) data width - AP covers address inputs A[20:0]
For (× 18) data width - AP covers address inputs A[21:0]
PE#
Output
AINV
Input
Address Inversion Pin for Address and Address Parity Inputs.
For (× 36) data width - AINV covers address inputs A[20:0] and the address parity input (AP).
For (× 18) data width - AINV covers address inputs A[21:0] and the address parity input (AP).
DKA[1:0],
DKA#[1:0],
DKB[1:0],
DKB#[1:0]
Input
Data Input Clock.
DKA[0]/DKA#[0] controls the DQA[17:0] inputs for × 36 configuration and DQA[8:0] inputs for × 18
configuration respectively
DKA[1]/DKA#[1] controls the DQA[35:18] inputs for × 36 configuration and DQA[17:9] inputs for × 18
configuration respectively
DKB[0]/DKB#[0] controls the DQB[17:0] inputs for × 36 configuration and DQB[8:0] inputs for × 18
configuration respectively
DKB[1]/DKB#[1] controls the DQB[35:18] inputs for × 36 configuration and DQB[17:9] inputs for × 18
configuration respectively
QKA[1:0],
QKA#[1:0],
QKB[1:0],
QKB#[1:0]
Output
Data Output Clock.
QKA[0]/QKA#[0] controls the DQA[17:0] outputs for ×36 configuration and DQA[8:0] outputs for × 18
configuration respectively
QKA[1]/QKA#[1] controls the DQA[35:18] outputs for × 36 configuration and DQA[17:9] outputs for
× 18 configuration respectively
QKB[0]/QKB#[0] controls the DQB[17:0] outputs for × 36 configuration and DQB[8:0] outputs for × 18
configuration respectively
QKB[1]/QKB#[1] controls the DQB[35:18] outputs for × 36 configuration and DQB[17:9] outputs for
× 18 configuration respectively
DQA[x:0],
DQB[x:0]
Input/Output
Data Input/Output.Bidirectional data bus.
For (× 36) data width  DQA[35:0]; DQB[35:0]
For (× 18) data width  DQA[17:0]; DQB[17:0]
DINVA[1:0],
DINVB[1:0]
Input/Output
Data Inversion Pin for DQ Data Bus.
DINVA[0] covers DQA[17:0] for × 36 configuration and DQA[8:0] for × 18 configuration respectively
DINVA[1] covers DQA[35:18] for × 36 configuration and DQA[17:9] for × 18 configuration respectively
DINVB[0] covers DQB[17:0] for × 36 configuration and DQB[8:0] for × 18 configuration respectively
DINVB[1] covers DQB[35:18] for × 36 configuration and DQB[17:9] for × 18 configuration respectively
LDA#, LDB#
Input
Synchronous Load Input.LDA# is sampled on the rising edge of the CK clock, while LDB# is sampled
on the falling edge of CK clock. LDA# enables commands for data port A, and LDB# enables
commands for data port B. LDx# enables the commands when LDx# is LOW and disables the
commands when LDx# is HIGH. When the command is disabled, new commands are ignored, but
internal operations continue.
CK, CK#
Address Parity Error Flag. Asserted LOW when address parity error is detected. Once asserted,
PE# will remain LOW until cleared by a Configuration Register command.
Document Number: 001-79552 Rev. *O
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CY7C4022KV13/CY7C4042KV13
Pin Definitions (continued)
Pin Name
I/Os
Pin Description
Input
Synchronous Read/Write Input. RWA# input is sampled on the rising edge of the CK clock, while
RWB# is sampled on the falling edge of the CK clock. The RWA# input is used in conjunction with the
LDA# input to select a Read or Write Operation. Similarly, the RWB# input is used in conjunction with
the LDB# input to select a read or write operation.
Output
Output Data Valid Indicator. The QVLD pin indicates valid output data. QVLD is edge aligned with
QKx and QKx#.
ZQ/ZT
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance.
CFG#
Input
Configuration bit. This pin is used to configure different mode registers.
RST#
Input
Active Low Asynchronous RST. This pin is active when RST# is LOW and inactive when RST# is
HIGH. The RST# pin has an internal pull down resistor.
LBK0#,
LBK1#
Input
Loopback mode for control and address/command/clock deskewing.
TMS
Input
Test Mode Select Input pin for JTAG. This pin may be left unconnected if the JTAG function is not
used in the circuit.
TDI
Input
Test Data Input pin for JTAG. This pin may be left unconnected if the JTAG function is not used in
the circuit.
TCK
Input
Test Clock Input pin for JTAG. This pin must be tied to VSS if the JTAG function is not used in the
circuit.
TDO
Output
Test Data Output pin for JTAG. This pin may be left unconnected if the JTAG function is not used in
the circuit.
TRST#
Input
Test Reset Input pin for JTAG. This pin must be tied to VDD if the JTAG function is not used in the
system. TRST# input is applicable only in JTAG mode.
DNU
N/A
Do Not Use. Do Not Use pins.
VREF
Reference
VDD
Power
Power Supply Inputs to the Core of the Device.
VDDQ
Power
Power Supply Inputs for the Outputs of the Device.
VSS
Ground
Ground for the Device.
RWA#,
RWB#
QVLDA[1:0],
QVLDB[1:0]
Reference Voltage Input. Static input used to set the reference level for inputs, outputs, and AC
measurement points.
Document Number: 001-79552 Rev. *O
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CY7C4022KV13/CY7C4042KV13
Functional Overview
The QDR-IV XP SRAM is a two-word burst synchronous SRAM
equipped with dual independent bidirectional data ports. The
following sections describe the operation of QDR-IV XP SRAM.
Clocking
There are three groups of clock signals: CK/CK#, DKx/DKx#,
and QKx/QKx#, where x can be A or B, referring to the respective
ports.
The CK/CK# clock is associated with the address and control
pins: A[24:0], LDA#, LDB#, RWA#, RWB#. The CK/CK#
transitions are centered with respect to the address and control
signal transitions.
The DKx/DKx# clocks are associated with write data. The
DKx/DKx# clocks are used as source-centered clocks for the
DDR DQx and DINVx pins, when acting as inputs for the write
data.
The QKx/QKx# clocks are associated with read data. The
QKx/QKx# clocks are used as source-synchronous clocks for
the double data rate DQx and DINVx pins, when acting as
outputs for the read data.
Command Cycles
The QDR-IV XP SRAM read and write commands are driven by
the control inputs (LDA#, LDB#, RWA#, and RWB#) and the
Address Bus.
The port A control inputs (LDA# and RWA#) are sampled at the
rising edge of the input clock. The port B control inputs (LDB#
and RWB#) are sampled at the falling edge of the input clock.
For port A:
When LDA# = 0 and RWA# = 1, a read operation is initiated.
When LDA# = 0 and RWA# = 0, a write operation is initiated.
The address is sampled on the rising edge of the input clock.
For port B:
When LDB# = 0 and RWB# = 1, a read operation is initiated.
When LDB# = 0 and RWB# = 0, a write operation is initiated.
The address is sampled on the falling edge of the input clock.
Read and Write Data Cycles
Read data is supplied to the DQA pins exactly eight clock cycles
from the rising edge of the CK signal corresponding to the cycle
where the read command was initiated. QVLDA is asserted
one-half clock cycle prior to the first data word driven on the bus.
It is de asserted one-half cycle prior to the last data word driven
on the bus. Data outputs are tri stated in the clock following the
last data word.
Read data is supplied to the DQB pins exactly eight clock cycles
from the falling edge of the CK signal corresponding to the cycle
that the read command was initiated. QVLDB is asserted
one-half clock cycle prior to the first data word driven on the bus.
It is de-asserted one-half cycle prior to the last data word driven
on the bus. Data outputs are tristated in the clock following the
last data word.
Document Number: 001-79552 Rev. *O
Write data is supplied to the DQA pins exactly five clock cycles
from the rising edge of the CK signal corresponding to the cycle
that the write command was initiated.
Write data is supplied to the DQB pins exactly five clock cycles
from the falling edge of the CK signal corresponding to the cycle
that the write command was initiated.
Banking Operation
The QDR-IV XP SRAM is designed with 8 internal banks. The
lower three address pins (A0, A1, and A2) select the bank that
will be accessed. These address inputs are also known as bank
address pins.
Bank Access Rules
1. On the rising edge of the input clock, any bank address may
be accessed. This is the address associated with port A.
2. On the falling edge of the input clock, any other bank
address may be accessed. This is the address associated
with port B.
3. If port A did not issue a command on the rising edge of the
input clock, then port B may access any bank address on the
falling edge of the input clock.
4. From the rising edge of the input clock cycle to the next
rising edge of the input clock, there is no address
restriction. Port A may access any bank at any time.
To clarify, the banking restriction only applies in a single clock
cycle. Since the port A address is sampled on the rising edge of
the input clock, there are no restrictions with port A access.
Because the port B address is sampled on the falling edge of the
input clock, port B has the restriction that it must use a different
bank than port A.
Banking Violations
1. Accesses for port A cannot cause a banking violation, only
accesses to port B can.
2. If port B tries to access the same bank as port A, then the port
B access to the memory array is ignored. The port A access
will still occur normally.
3. If the requested cycle on port B was a write, then there will be
no external indication that a banking violation occurred.
4. If the requested cycle on port B was a read, then there will be
no QVLDB signal generated. Outputs will remain tristated.
Address and Data Bus Inversion
To reduce simultaneous switching noise and I/O current, QDR-IV
XP SRAM provides the ability to invert all address and data pins.
The AINV pin indicates whether the address bus- A[24:0], and
the address parity bit, AP, is inverted. The address bus and parity
bit are considered one group. The function of the AINV is
controlled by the memory controller. However, the following rules
should be used in the system design.
■
For a × 36 configuration part, 20 address pins plus 1 parity bit
are used for 21 signals in the address group.If the number of
0’s in the address group is >11, AINV is set to 1 by the controller.
As a result, no more than 11 pins may switch in the same
direction during each bit time.
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CY7C4022KV13/CY7C4042KV13
■
For a × 18 data width part, 21 address pins plus 1 parity bit are
used for 22 signals in the address group. If the number of 0’s
in the address group is > 12, AINV is set to 1 by the controller.
As a result, no more than 12 pins may switch in the same
direction during each bit time.
The DINVA and DINVB pins indicate whether the corresponding
DQA and DQB pins are inverted.
■
■
For a × 36 data width part, the data bus for each port is split
into groups of 18 pins. Each 18-pin data group is guaranteed
to be driving less than or equal to 10 pins low on any given
cycle. If the number of 0’s in the data group is >10, DINV is set
to 1.As a result, no more than 10 pins may switch in the same
direction during each bit time.
For a × 18 data width part, the data bus for each port is split
into groups of 9 pins. Each 9 pin data group is guaranteed to
be driving less than or equal to five pins low on any given cycle.
If the number of 0’s in the data group is >5, DINV is set to 1 As
a result, no more than five pins may switch in the same direction
during each bit time.
AINV, DINVA[1:0], DINVB[1:0] are all active high. When set to 1,
the corresponding bus is inverted. If the data inversion feature is
programmed to be OFF, then the DINVA/DINVB output bits will
always be driven to 0.
These functions are programmable through the configuration
registers and can be enabled or disabled for the address bus and
the data bus independently.
During configuration register read and write cycles, the address
inversion input is ignored and the data inversion output is always
driven to 0 when the register read data is driven on the data bus.
Specifically, the register read data is driven on DQA[7:0] and the
DINVA[0] bit is driven to 0. All other DQA/DQB data bits and
DINVA/DINVB bits are tristated. In addition, the address parity
input (AP) is ignored.
Address Parity
The QDR-IV XP SRAM provides an address parity feature to
provide integrity on the address bus. Two pins are provided to
support this function: AP and PE#.
The AP pin is used to provide an even parity across the address
pins. The value of AP is set so that the total number of 1’s
(including the AP bit) is even. The AP pin is a DDR input.
Internally, when an address parity error is detected, the access
to the memory array is ignored if it was a write cycle. A read
access continues normally even if an address parity error is
detected.
Externally, the PE# pin is used to indicate that an address parity
error has occurred. This pin is Active Low and is set to 0 within
RL cycles after the address parity error is detected. It remains
asserted until the error is cleared through the configuration
registers.
The address parity function is optional and can be enabled or
disabled in the configuration registers.
During configuration register read and write cycles, the address
parity input is ignored. Parity is not checked during these cycles.
Document Number: 001-79552 Rev. *O
Note The memory controller should generate address parity
based on the address bus first. Address inversion is done later
on the address bus and address parity bit.
Port Enable
The QDR-IV XP SRAM has two independent bidirectional data
ports. However, some system designers may either choose to
use only one port, or use one port as read-only and one port as
write-only.
If a port is used in a uni-directional mode, disable the data clocks
(DKx/DKx# or QKx/QKx#) to reduce EMI effects in the system.
In addition, disable the corresponding control input (RWx#).
Port B may be programmed to be entirely disabled. If port B is
not used, then the following must happen:
■
The data clocks (DKB/DKB# and QKB/QKB#) and the control
inputs (LDB# and RWB#) must be disabled.
■
All data bus signals must be tristated. This includes DQB,
DINVB and QVLDB.
■
All input signals related to port B can be left floating or tied to
either 1 or 0 without any adverse effects on the port A operation.
■
When port B is not used. All output signals related to port B are
inactive.
A configuration register option is provided to specify if one of the
ports is not used or is operating in a unidirectional mode.
On-Die Termination (ODT) Operation
When enabled, the ODT circuits for the chip will be enabled
during all NOP and write cycles. The ODT is temporary disabled
only during read cycles because the read data is driven out.
Specifically, ODT is disabled one-half clock cycle before the first
beat of the read data is driven on the data bus and remains
disabled during the entire read operation. ODT is enabled again
one-half clock cycle after the last beat of read data is driven on
the data bus.
JTAG Operation
The JTAG interface uses five signals: TRST#, TCK, TMS, TDI,
and TDO. For normal JTAG operation, the use of TRST# is not
optional for this device.
While in the JTAG mode, the following conditions are true:
■
ODT for all pins is disabled.
If the JTAG function is not used in the system, then the TRST#
pin must be tied to VDD and the TCK input must be driven low
or tied to VSS. TMS, TDI, and TDO may be left floating.
Power Up and Reset
The QDR-IV XP SRAM has specific power up and reset
requirements to guarantee reliable operation.
Power-Up Sequence
■
Apply VDD before VDDQ.
■
Apply VDDQ before VREF or at the same time as VREF.
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CY7C4022KV13/CY7C4042KV13
Reset Sequence
Operation Modes
Refer to the Reset timing diagram (Figure 16 on page 41).
The QDR-IV XP has three unique modes of operation:
1. Configuration
2. Loopback
3. Memory Access
1. As the power comes up, all inputs may be in an undefined
state except RST# and TRST#, which must be LOW during
tPWR.
2. The first signal that should be driven to the device is the input
clock (CK/CK#), which may be unstable for the duration of
tPWR.
3. After the input clock has stabilized, all the control inputs
should be driven to a valid value as follows:
a. RST# = 0
b. CFG# = 1
c. LBK0# = 1
d. LBK1# = 1
e. LDA# = 1
f. LDB# = 1
4. Reset should remain asserted, while all other control inputs
de-asserted, for a minimum time of 200 µs (tRSS).
5. At the rising edge of reset, the address bits A[13:0] are
sampled to load in the ODT values and Port Enable values.
After reset, internal operations in the device may start. This
may include operations such as PLL initialization, resetting
and internal registers.
6. However, all external control signals must remain de-asserted
for a minimum time of 400000 clocks (tRSH). During this time
all other signals (data and address busses) should be driven
to a valid level. All inputs to the device should be driven to a
valid level.
7. After this, the device is in normal operating mode and ready
to respond to control inputs.
Typically, after a reset sequence, the system starts to perform a
training sequence, involving the steps outlined in the following
section.
However, RST# may be asserted at anytime by the system, and
the system may wish to initiate normal read/write operations after
a reset sequence without going through another training
sequence. The chip should be able to accept normal read/write
operations immediately following tRSH after the de-assertion of
RST#.
PLL Reset Operation
The configuration registers contain a bit to reset the PLL.
Operating the QDR-IV XP device without the PLL enabled is not
supported–timing characteristics are not guaranteed when the
PLL is disabled. However, this bit is intended to allow the system
to reset the PLL locking circuitry.
Resetting the PLL is accomplished by first programming the PLL
Reset bit to 1 to disable the PLL, and then programming the bit
to 0 to enable the PLL. After these steps, the PLL will re-lock to
the input clock. A wait time of tPLL is required.
These modes are defined by the level of the control signals
CFG#, LBK0#, LBK1#, LDA#, LDB#.
It is intended that these operations are mutually exclusive. In
other words, one operation mode cannot be performed
simultaneously with another operation mode.
There is no priority given for inadvertently asserting the control
signals at the wrong time. The internal chip behavior is not
defined for improper control signal assertion. The system
must strictly adhere to proper mode transitions as defined in the
following section for proper, device operation.
Configuration
A Configuration operation mode is entered when the CFG#
signal is asserted. Memory Access or Loopback operations
should not be performed for a minimum of 32 clocks prior to
entering this mode.
While in this mode, the control signals LDB#, LBK0# and LBK1#
must not be asserted. However, LDA# is used to perform the
actual Register Read and Write operations.
Memory Access or Loopback operations should not be
performed for a minimum of 32 clocks after exiting this mode.
Loopback
A Loopback operation mode is entered when the LBK0# and/or
LBK1# signals are asserted. Memory Access or Configuration
operations should NOT be performed for a minimum of 32 clocks
prior to entering this mode.
Just after entering this mode, an additional 32 clocks are
required before the part is ready to accept toggling valid inputs
for training.
While in this mode, LDA# and LDB# may be toggled for training.
Memory Access or Configuration operations should NOT be
performed for a minimum of 32 clocks after exiting this mode.
Data inversion is not used during the Loopback mode. Even if
the configuration register has this feature enabled, it is
temporarily ignored during the Loopback mode.
Memory Access
If the control signals CFG#, LBK0#, and LBK1# are not asserted,
then the device is in the memory access mode. This mode is the
normal operating mode of the device.
While in this mode, a memory access cycle is performed when
the LDA# and/or LDB# signals are asserted. The control signals
CFG#, LBK0# and LBK1# must NOT be asserted when
performing a memory access cycle.
A memory access should not be performed for a minimum of 32
clocks prior to leaving this mode.
Document Number: 001-79552 Rev. *O
Page 11 of 46
CY7C4022KV13/CY7C4042KV13
Deskew Training Sequence
The QDR-IV XP SRAM provides support that allows a memory
controller to deskew signals for a high speed operation. The
memory controller provides the deskew function, if deskew is
desired. During the deskew operation the QDR-IV XP SRAM
operates in the Loopback mode.
Refer to Loopback Timing Diagram (Figure 15 on page 40)
Deskew is achieved in three steps
1. Control/address deskew
2. Read data deskew
3. Write data deskew
Control/Address Deskew
Assert LBK0# to 0 and/or LBK1# to 0
The following 39 signals are looped back:
The Write Training Enable bit has no effect on the read data
cycles.
After the data pattern is written into the memory, standard read
commands permit the system to deskew with respect to the
QK/QK# data output clocks the following signals:
DQA, DINVA, QVLDA, DQB, DINVB, QVLDB
Write Data Deskew
Write data deskew is performed using write commands to the
memory followed by read commands.
The deskewed read data path is used to determine whether or
not the write data was received correctly by the device.
This permits the system to deskew with respect to the DK/DK#
input data clocks the following signals:
DQA, DINVA, DQB, DINVB
■
DKA0, DKA0#, DKA1, DKA1#
I/O Signaling Standards
■
DKB0, DKB0#, DKB1, DKB1#
Several I/O signaling standards are supported by the QDR-IV XP
SRAM, which are programmable by the user. They are:
■
LDA#, RWA#, LDB#, RWB#
■
A[24:0], AINV, AP
The clock inputs DKA0, DKA0#, DKA1#, DKB0, DKB0#, DKB1,
and DKB1# are free running clock inputs and should be
continuously running during the training sequence. In addition, a
wait time of tPLL is needed.
Refer to Table 1 on page 14 for the loopback signal mapping.
For each pin that is looped back, the input pin is sampled on both
the rising and falling edges using the input clock (CK/CK#).
The value output on the rising edge of the output clock
(QKA/QKA#) will be the value that was sampled on the rising
edge of the input clock.
The value output on the falling edge of the output clock
(QKA/QKA#) will be the inverted value that was sampled on the
falling edge of the input clock.
The delay from the input pins to the DQA outputs is tLBL, which
is 16 clocks.
Read Data Deskew
■
1.2 V and 1.25 V HSTL/SSTL
■
1.1 V and 1.2 V POD
The I/O Signaling Standard is programmed on the rising edge of
reset by sampling the address bus inputs. Once programmed,
the value cannot be changed. Only the rising edge of another
reset can change the value.
All Address, Control, and Data I/O signals – with the exception
of six pins (listed as LVCMOS in the LVCMOS Signaling section)
– will program to comply with HSTL/SSTL, or POD compliant.
HSTL/SSTL Signaling
HSTL/SSTL is supported at the VDDQ voltages of 1.2 V and
1.25 V nominal.
The ODT termination values can be set to:
■
40, 60, or, 120 ohms with a 220-ohm reference resistor
■
50 or 100 ohms with a 180-ohm reference resistor.
The drive strength can be programmed to:
At this time, the address, control, and data input clocks are
already deskewed.
■
40 or 60 ohms with a 220-ohm reference resistor
■
50 ohms with a 180-ohm reference resistor
Read data deskew requires a training pattern to be written into
the memory using data held at constant values.
A reference resistor of 180 ohms or 220 ohms is supported with
HSTL/SSTL signaling.
Complex data patterns such as the following may be written into
the memory using the non-deskewed DQA and/or DQB signals
and the write training enable bit.
POD Signaling
POD is supported at VDDQ voltages of 1.1 V and 1.2 V nominal.
Write training enable set to 1:
During Write Data Cycles:
The First Data Beat (First Data Burst) is sampled from the data
bus.
The Second Data Beat (Second Data Burst) is the inverted
sample from the data bus.
The ODT termination values can be set to:
Write training enable set to 0:
During Write Data Cycles:
Both First and Second Data Beats are sampled from the data
bus, which is the normal operation.
■
50 ohms with a 180-ohm reference resistor
■
40 or 60 ohms with a 220-ohm reference resistor
Document Number: 001-79552 Rev. *O
■
50 or 100 ohms with a 180-ohm reference resistor
■
60 or 120 ohms with a 220-ohm reference resistor
The drive strength can be programmed to:
A reference resistor of 180 ohms or 220 ohms is supported with
POD signaling.
Page 12 of 46
CY7C4022KV13/CY7C4042KV13
LVCMOS Signaling
The following flowchart illustrates the initialization procedure:
Six I/O signals are permanently set to use LVCMOS signaling at
a voltage of 1.3 V nominal. These signals are referenced to the
core voltage supply, VDD. They are:
Figure 3. Flowchart illustrating initialization procedure
RST#, TRST#, TCK, TMS, TDI, and TDO
All the five JTAG signals as well as the main reset input are 1.3 V
LVCMOS.
In addition, ODT is disabled at all times on these LVCMOS
signals.
Initialization
The QDR-IV XP SRAM must be initialized before it can operate
in normal functional mode. Initialization uses four special pins:
- RST# pin to reset the device
- CFG# pin to program the Configuration Registers
- LBK0# and LBK1# pins for the Loopback function
Power on
Apply power to the chip as described in Power-Up Sequence.
Reset Chip
Apply reset to the QDR-IV XP SRAM as described in Reset
Sequence.
Configure the Impedance
Assert Config (CFG# = 0) and program the impedance control
register.
Wait for the PLL to Lock
Since the input impedance is updated, allow the PLL time (tPLL)
to lock to the input clock.
Document Number: 001-79552 Rev. *O
Page 13 of 46
CY7C4022KV13/CY7C4042KV13
Configure Training Options
At this time, the address and data inversion options need to be
programmed. In addition, the write training function needs to be
enabled.
Assert Config (CFG# = 0) and program:
■
Write Training (Turn On)
■
Address Inversion Enable
■
Data Inversion Enable
Table 1. Loopback Signal Mapping
Input Pin
Input Pin
Input Pin
Output Pin
LBK0# = 0
LBK1# = 0
LBK0# = 0
LBK1# = 1
LBK0# = 1
LBK1# = 0
A0
A13
DKA0
DQA0
A1
A14
DKA0#
DQA1
A2
A15
DKA1
DQA2
Control/Address Deskew
A3
A16
DKA1#
DQA3
Control and address deskew can now be performed by the
memory controller.
A4
A17
LDA#
DQA4
A5
A18
RWA#
DQA5
Read Data Deskew
A6
A19
DKB0
DQA6
After control and address deskew, the read data path is
deskewed as described in Deskew Training Sequence.
A7
A20
DKB0#
DQA7
A8
A21
DKB1
DQA8
Write Data Deskew
A9
A22
DKB1#
DQA9
Write data path is deskewed following the read data path
deskew.
A10
A23
LDB#
DQA10
A11
A24
RWB#
DQA11
Configure Runtime Options
A12
AINV
AP
DQA12
After the training is complete, disable the write training function.
Finally, enable the address parity option at this time.
Assert Config (CFG# = 0) and program:
■
Write Training (Turn off)
■
Parity Enable
Normal Operation
If the system detects a need to deskew again, the process must
start again from the Configure Training Options step.The
following table defines the loopback mapping:
Configuration Registers
The QDR-IV XP SRAM contains internal registers that are
programmed by the system using a special configuration cycle.
These registers are used to enable and control several options
as described in this section. All registers are 8-bits wide. The
write operation is performed using only the address pins to
define the register address and register write data. For a read
operation, the register read data is provided on the data port A
output pins. Refer to Figure 14 on page 39 for programming
details.
During the rising edge of RST#, the address pins A[13:0] are
sampled. The value sampled becomes the reset value of certain
bits in the registers defined below. This is used to set termination,
impedance, and port configuration values immediately upon
reset. These values can be overwritten later through a register
write operation.
When a parity error occurs, the complete address of the first
error is recorded in registers 4, 5, 6, and 7 along with the port A/B
error bit. The port A/B error bit will indicate from which port the
address parity error came – 0 for port A and 1 for port B. This
information will remain latched until cleared by writing a 1 to the
address parity error clear bit in register 3.
Two counters are used to indicate if multiple address parity errors
occurred. The port A error count is a running count of the number
of parity errors on port A addresses, and similarly the port B error
count is a running count of the number of parity errors on port B
addresses. They will each independently count to a maximum
value of 3 and then stop counting. These counters are free
running, and they are both reset by writing a 1 to the address
parity error clear bit in register 3.
Document Number: 001-79552 Rev. *O
Page 14 of 46
CY7C4022KV13/CY7C4042KV13
Configuration Registers Description
Table 2. Configuration Register Table
Register Address
0
1
2
3
4
5
6
7
Description
Termination Control Register
Impedance Control Register
Option Control Register
Function Control Register
Address Parity Status Register 0
Address Parity Status Register 1
Address Parity Status Register 2
Address Parity Status Register 3
Configuration Register Definitions
Table 3. Address 0: Termination Control Register (Read/Write)
Function
ODT Global
ODT/ZQ
Enable
Auto Update
Address /
Command
Input Group
IU[2]
Address /
Command
Input Group
IU[1]
Address /
Clock Input Clock Input Clock Input
Command Group KU[2] Group KU[1] Group KU[0]
Input Group
IU[0]
Bit Location
7
6
5
4
3
2
1
0
Reset Value
A7
A6
A5
A4
A3
A2
A1
A0
Note: ODT/ZQ Auto Update needs to be turned on if ODT/ZQ configuration is changed
Table 4. Address 1: Impedance Control Register (Read/Write)
Function
Pull Down
Pull Down
Pull Up
Pull Up
Group PD[1] Group PD[0] Group PU[1] Group PU[0]
Unused
Data Input
Data Input
Group QU[2] Group QU[1]
Data Input
Group QU[0]
Bit Location
7
6
5
4
3
2
1
0
Reset Value
1
0
1
0
0
A10
A9
A8
Table 5. Address 2: Option Control Register (Read/Write Bits 7-3) (Read-Only Bits 2-0) [2]
Function
Write Train
Enable
Data Inv
Enable
Address Inv
Address
Enable
Parity Enable
Bit Location
7
6
5
Reset Value
0
0
0
PLL Reset
I/O Type
Port
Enable[1]
Port Enable[0]
4
3
2
1
0
0
0
A13
A12
A11
Table 6. Address 3: Function Control Register (Write Only)
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Address Parity
Error Clear
Bit Location
7
6
5
4
3
2
1
0
Reset Value
0
0
0
0
0
0
0
0
Function
Note
2. The Bits 2–0 are read only and can be changed only on the rising edge of reset
Document Number: 001-79552 Rev. *O
Page 15 of 46
CY7C4022KV13/CY7C4042KV13
Table 7. Address 4: Address Parity Status Register 0 (Read Only)
Function
Port B Error Count
(1:0)
Port A Error Count
(1:0)
Port A/B Error
AINV Bit
Unused
Unused
Bit Location
7:6
5:4
3
2
1
0
Reset Value
00
00
0
0
0
0
Table 8. Address 5: Address Parity Status Register 1 (Read Only)
Function
Address (23:16)
Bit Location
7:0
Reset Value
00000000
Note: Unused address locations will be read as 0
Table 9. Address 6: Address Parity Status Register 2 (Read Only)
Function
Address (15:8)
Bit Location
7:0
Reset Value
00000000
Table 10. Address 7: Address Parity Status Register 3 (Read Only)
Function
Address (7:0)
Bit Location
7:0
Reset Value
00000000
Document Number: 001-79552 Rev. *O
Page 16 of 46
CY7C4022KV13/CY7C4042KV13
I/O Type and Port Enable Bit Definitions
Table 11. I/O Type Bit Definition specified in Address 2: Option Control Register
I/O Type
Function
0
HSTL/SSTL
1
POD
Table 12. Port Enable Bit Definition specified in Address 2: Option Control Register
Port Enable
[1:0]
Function
Port B
Mode
Port A
Mode
Port B
Clocks and
Controls
Port A
Clocks and
Controls
0
0
Fixed Port Mode
Write Only
Read Only
DKB - On
QKB - Off
LDB# - On
RWB# - Off
DKA - Off
QKA - On
LDA# - On
RWA# - Off
0
1
Only Port A
Enable
Disabled
Enabled
DKB - Off
QKB - Off
LDB# - Off
RWB# - Off
DKA - On
QKA - On
LDA# - On
RWA# - On
1
0
Not supported
Disabled
Disabled
DKB - Off
QKB - Off
LDB# - Off
RWB# - Off
DKA - Off
QKA - Off
LDA# - Off
RWA# - Off
1
1
Both Ports
Enabled
Enabled
Enabled
DKB - On
QKB - On
LDB# - On
RWB# - On
DKA - On
QKA - On
LDA# - On
RWA# - On
Document Number: 001-79552 Rev. *O
Page 17 of 46
CY7C4022KV13/CY7C4042KV13
ODT Termination Bit Definitions
Table 13. Clock Input Group Bit Definition specified in Address 0: Termination Control Register
ODT
Global
Enable
0
1
1
1
1
1
1
1
1
Divisor Termination Value HSTL/SSTL Mode
Value
ZT 180 ohm
ZT 220 ohm
KU[2:0]
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
–
–
8.33%
12.50%
16.67%
25%
50%
-
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
40 ohm
60 ohm
120 ohm
Not supported
Not supported
Termination Value POD Mode
ZT 180 ohm
ZT 220 ohm
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
Not supported
60 ohm
120 ohm
Not supported
Not supported
Note: Termination values are accurate to ±15%
ZQ tolerance is 1%
Table 14. Address/Command Input Group Bit Definition specified in Address 0: Termination Control Register
ODT
Global
Enable
0
1
1
1
1
1
1
1
1
Divisor Termination Value HSTL/SSTL Mode
Value
ZT 180 ohm
ZT 220 ohm
IU[2:0]
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
–
–
8.33%
12.50%
16.67%
25%
50%
–
–
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
40 ohm
60 ohm
120 ohm
Not supported
Not supported
Termination Value POD Mode
ZT 180 ohm
ZT 220 ohm
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
Not supported
60 ohm
120 ohm
Not supported
Not supported
Note: Termination values are accurate to ±15%
ZQ tolerance is 1%
Table 15. Data Input Group Bit Definition specified in Address 1: Impedance Control Register
ODT
Global
Enable
0
1
1
1
1
1
1
1
1
Divisor Termination Value HSTL/SSTL Mode
Value
ZT 180 ohm
ZT 220 ohm
QU[2:0]
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
–
–
8.33%
12.50%
16.67%
25%
50%
–
–
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
40 ohm
60 ohm
120 ohm
Not supported
Not supported
Termination Value POD Mode
ZT 180 ohm
ZT 220 ohm
OFF
OFF
Not supported
Not supported
Not supported
50 ohm
100 ohm
Not supported
Not supported
OFF
OFF
Not supported
Not supported
Not supported
60 ohm
120 ohm
Not supported
Not supported
Note: Termination values are accurate to ±15%
ZQ tolerance is 1%
Document Number: 001-79552 Rev. *O
Page 18 of 46
CY7C4022KV13/CY7C4042KV13
Drive Strength Bit Definitions
Table 16. Pull-Up Driver Bit Definition specified in Address 1: Impedance Control Register
Divisor
Value
PU[1:0]
Impedance Value HSTL/SSTL Mode
Impedance Value POD Mode
ZT 180 ohm
ZT 220 ohm
ZT 180 ohm
ZT 220 ohm
0
0
14.17%
Not supported
Not supported
Not supported
Not supported
0
1
16.67%
Not supported
40 ohm
Not supported
40 ohm
1
0
25%
50 ohm
60 ohm
50 ohm
60 ohm
1
1
–
Not supported
Not supported
Not supported
Not supported
Note: Termination values are accurate to ±15%
ZQ tolerance is 1%
Table 17. Pull-Down Driver Bit Definition
Divisor
Value
PD[1:0]
Impedance Value HSTL/SSTL Mode
Impedance Value POD Mode
ZT 180 ohm
ZT 220 ohm
ZT 180 ohm
ZT 220 ohm
0
0
14.17%
Not supported
Not supported
Not supported
Not supported
0
1
16.67%
Not supported
40 ohm
Not supported
40 ohm
1
0
25%
50 ohm
60 ohm
50 ohm
60 ohm
1
1
–
Not supported
Not supported
Not supported
Not supported
Note: Termination values are accurate to ±15%
ZQ tolerance is 1%
Document Number: 001-79552 Rev. *O
Page 19 of 46
CY7C4022KV13/CY7C4042KV13
IEEE 1149.1 Serial Boundary Scan (JTAG)
Instruction Register
QDR-IV XP SRAMs incorporate a serial boundary scan test
access port (TAP) in the FCBGA package. This part is fully
compliant with IEEE Standard #1149.1-2001. In the JTAG mode
the ODT feature for all pins is disabled.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in Figure 5 on page 23. Upon power up,
the instruction register is loaded with the IDCODE instruction. It
is also loaded with the IDCODE instruction if the controller is
placed in a RST state, as described in the previous section.
If the JTAG function is not used in the circuit, then TCK inputs
must be driven low or tied to VSS. TRST#, TMS, TDI, and TDO
may be left floating. An internal Pull-Up resistor is implemented
on the TRST#, TMS, and TDI inputs to ensure that these inputs
are HIGH during tPWR.
Test Access Port
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Test Mode Select (TMS)
Boundary Scan Register
Test Clock (TCK)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see Figure 4 on page 22. TDI is
internally pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most significant bit
(MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 26).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Test Reset (TRST#)
The TRST# input pin is used to reset the TAP controller.
Alternatively, a reset may be performed by forcing TMS HIGH
(VDD) for five rising edges of TCK.
This reset does not affect the operation of the SRAM and can be
performed while the SRAM is operating. At power up, the TAP is
reset internally to ensure that TDO comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-79552 Rev. *O
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 27 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 26.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 26. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 20 of 46
CY7C4022KV13/CY7C4042KV13
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-RST state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state. Both Port A and Port B are enabled once this
command has been executed.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
Remember that the TAP controller clock can only operate at a
frequency up to 20 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output undergoes a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state. Both Port A and Port B are
enabled after this command is executed.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has output enable control bits
located at Bit #49 and Bit #50. Bit# 49 enables the output pins
for DQB and Bit#50 enables DQA and PE# pins.
When these scan cells, called the “extest output bus tristate,” are
latched into the preload register during the Update-DR state in
the TAP controller, they directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
These bits can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, these bits directly controls the
output Q-bus pins. Note that these bits are pre-set LOW to
disable the output when the device is powered up, and also when
the TAP controller is in the Test-Logic-RST state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
Document Number: 001-79552 Rev. *O
Page 21 of 46
CY7C4022KV13/CY7C4042KV13
TAP Controller State Diagram
Figure 4. TAP Controller State Diagram [2]
1
TEST-LOGIC
RST
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
3. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-79552 Rev. *O
Page 22 of 46
CY7C4022KV13/CY7C4042KV13
TAP Controller Block Diagram
Figure 5. TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
135
.
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TRST#
Document Number: 001-79552 Rev. *O
Page 23 of 46
CY7C4022KV13/CY7C4042KV13
TAP Electrical Characteristics
Over the Operating Range
Min
Max
Unit
VOH
Parameter
LVCMOS High Level Output
Voltage
Description
IOH = 100µA
Test Conditions
VDD × 0.8
–
V
VOL
LVCMOS Low Level Output
Voltage
IOL = 100 µA
–
VDD × 0.2
V
VIH
LVCMOS High Level Input
Voltage (DC)
VDD × 0.7
VDD + 0.2
V
VIL
LVCMOS Low Level Input
Voltage (DC)
–0.2
VDD × 0.3
V
IX
LVCMOS Input Leakage Current
–
10
A
IOZ
LVCMOS Output Leakage
Current
–
10
A
Min
Max
Unit
50
–
ns
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Description
tTCYC
TCK clock cycle time
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH
20
–
ns
tTL
TCK clock LOW
20
–
ns
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
Setup Times
Hold Times
Output Times
Note: tCS and tCH refer to setup and hold time requirements of latching data from the boundary scan register.
Document Number: 001-79552 Rev. *O
Page 24 of 46
CY7C4022KV13/CY7C4042KV13
TAP Timing Diagram
Figure 6. TAP Timing Diagram
Document Number: 001-79552 Rev. *O
Page 25 of 46
CY7C4022KV13/CY7C4042KV13
Identification Register Definitions
Value
Instruction Field
CY7C4022KV13
Revision Number (31:29)
Description
CY7C4042KV13
000
000
Cypress Device ID (28:12)
11011010101010100
11011010101100100
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
136
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-79552 Rev. *O
Page 26 of 46
CY7C4022KV13/CY7C4042KV13
Boundary Scan Order
Bit
Bump
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
12A
13B
14A
15B
16A
18B
17C
16C
14C
12C
12D
13D
15D
17D
18E
15F
16F
17F
18G
16G
17H
15H
16J
18J
18K
18L
16L
15M
17M
18N
16N
15P
16P
17P
18R
17T
15T
13T
12T
12U
14U
16U
17U
18V
15V
Document Number: 001-79552 Rev. *O
CY7C4042KV13
× 36 Device
DQA<26>
DQA<19>
DQA<25>
DQA<35>
DQA<23>
DQA<31>
QVLDA<1>
QKA<1>
DQA<20>
DQA<18>
DINVA<1>
DQA<22>
DQA<21>
QKA#<1>
DQA<32>
DQA<24>
DKA<1>
DKA#<1>
DQA<33>
DQA<34>
DQA<27>
DQA<28>
DQA<30>
DQA<29>
RST#
DQB<29>
DQB<30>
DQB<28>
DQB<27>
DQB<33>
DQB<34>
DQB<24>
DKB<1>
DKB#<1>
DQB<32>
QKB#<1>
DQB<21>
DQB<22>
DINVB<1>
DQB<18>
DQB<20>
QKB<1>
QVLDB<1>
DQB<31>
DQB<35>
CY7C4022KV13
× 18 Device
DQA<17>
DQA<10>
DQA<16>
NC
DQA<14>
NC
QVLDA<1>
QKA<1>
DQA<11>
DQA<9>
DINVA<1>
DQA<13>
DQA<12>
QKA#<1>
NC
DQA<15>
DKA<1>
DKA#<1>
NC
NC
NC
NC
NC
NC
RST#
NC
NC
NC
NC
NC
NC
DQB<15>
DKB<1>
DKB#<1>
NC
QKB#<1>
DQB<12>
DQB<13>
DINVB<1>
DQB<9>
DQB<11>
QKB<1>
QVLDB<1>
NC
NC
Page 27 of 46
CY7C4022KV13/CY7C4042KV13
Boundary Scan Order (continued)
Bit
Bump
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
13V
12W
14W
16W
Document Number: 001-79552 Rev. *O
10V
8P
7N
9N
10P
10N
11N
12P
13N
13L
12M
11L
10L
10M
9L
8M
7L
7J
9J
10K
10J
11J
13J
12H
10H
8H
7G
9G
10G
11G
13G
12F
10F
8F
10D
10B
10A
8A
7B
6A
5B
CY7C4042KV13
× 36 Device
DQB<19>
DQB<26>
DQB<25>
DQB<23>
Internal_DQB
Internal_DQA
PE#
A<15>
A<9>
NC/1152M
AP
A<2>
NC/2304M
A<16>
A<10>
A<8>
A<12>
A<18>
RWB#
AINV
A<17>
A<11>
A<7>
A<5>
A<19>
CK#
CK
NC/144M
A<6>
LDB#
RWA#
LDA#
A<3>
NC/288M
A<1>
NC/576M
A<4>
A<14>
A<0>
A<13>
CFG#
LBK#<1>
LBK#<0>
DQA<8>
DQA<1>
DQA<7>
DQA<17>
CY7C4022KV13
× 18 Device
DQB<10>
DQB<17>
DQB<16>
DQB<14>
Internal_DQB
Internal_DQA
PE#
A<15>
A<9>
NC/576M
AP
A<2>
NC/1152M
A<16>
A<10>
A<8>
A<12>
A<18>
RWB#
AINV
A<17>
A<11>
A<7>
A<5>
A<19>
CK#
CK
A<20>
A<6>
LDB#
RWA#
LDA#
A<3>
NC/144M
A<1>
NC/288M
A<4>
A<14>
A<0>
A<13>
CFG#
LBK#<1>
LBK#<0>
DQA<8>
DQA<1>
DQA<7>
NC
Page 28 of 46
CY7C4022KV13/CY7C4042KV13
Boundary Scan Order (continued)
Bit
Bump
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
4A
2B
3C
4C
6C
8C
8D
7D
5D
3D
2E
3F
4F
5F
4G
2G
3H
5H
4J
2J
2L
4L
5M
3M
2N
4N
5P
4P
3P
2R
3T
5T
7T
8T
8U
6U
4U
3U
2V
5V
7V
8W
6W
4W
Document Number: 001-79552 Rev. *O
CY7C4042KV13
× 36 Device
DQA<5>
DQA<13>
QVLDA<0>
QKA<0>
DQA<2>
DQA<0>
DINVA<0>
DQA<4>
DQA<3>
QKA#<0>
DQA<14>
DKA#<0>
DKA<0>
DQA<6>
DQA<16>
DQA<15>
DQA<9>
DQA<10>
DQA<12>
DQA<11>
DQB<11>
DQB<12>
DQB<10>
DQB<9>
DQB<15>
DQB<16>
DQB<6>
DKB<0>
DKB#<0>
DQB<14>
QKB#<0>
DQB<3>
DQB<4>
DINVB<0>
DQB<0>
DQB<2>
QKB<0>
QVLDB<0>
DQB<13>
DQB<17>
DQB<1>
DQB<8>
DQB<7>
DQB<5>
CY7C4022KV13
× 18 Device
DQA<5>
NC
QVLDA<0>
QKA<0>
DQA<2>
DQA<0>
DINVA<0>
DQA<4>
DQA<3>
QKA#<0>
NC
DKA#<0>
DKA<0>
DQA<6>
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQB<6>
DKB<0>
DKB#<0>
NC
QKB#<0>
DQB<3>
DQB<4>
DINVB<0>
DQB<0>
DQB<2>
QKB<0>
QVLDB<0>
NC
NC
DQB<1>
DQB<8>
DQB<7>
DQB<5>
Page 29 of 46
CY7C4022KV13/CY7C4042KV13
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Operating Range
Range
Ambient
Temperature (TA)
VDD
VDDQ
0 °C to +70 °C
1.3V ±
40 mV
1.2 V ± 50 mV
Storage temperature ................................ –65 °C to +150 °C
Commercial
Ambient temperature
with Power Applied .................................. –55 °C to +125 °C
Industrial
Maximum Junction Temperature ............................... 125 °C
Neutron Soft Error Immunity
Supply Voltage on
VDD Relative to GND .................................–0.3 V to +1.35 V
Supply Voltage on
VDDQ Relative to GND ...............................–0.3 V to +1.35 V
Parameter
Static Discharge Voltage
(MIL-STD-883, M. 3015) ......................................... > 2001V
Latch up current ..................................................... > 200 mA
Description
1.1 V ± 50 mV
Test
Conditions Typ
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
0
0.01
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
Single event
latch-up
85 °C
0
0.1
FIT/
Dev
DC Input Voltage .......................................–0.3 V to +1.35 V
Current into Outputs (LOW) ........................................ 20 mA
–40 °C to +85 °C
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure
Rates – AN54908.
Electrical Characteristics
Over the Operating Range
Parameter
Description
POD Signaling Mode
VDD[4]
Core supply voltage (1.3 V ± 40 mV)
VDDQ [4]
POD I/O supply voltage (1.1 V ± 50 mV)
POD I/O supply voltage (1.2 V ± 50 mV)
[4,
5]
VREF
POD reference voltage
VOL(DC) [4]
POD low level output voltage (DC)
VIH(DC) [4, 6]
POD high level input voltage (DC)
[4,
6]
VIL(DC)
POD low level input voltage
VIH(AC) [4, 7]
POD high level input voltage (DC)
[4,
7]
VIL(AC)
POD low level input voltage
VMP(DC)
POD differential Input Mid-Point Voltage; Pin and Pin#
VID(DC)
POD differential Input Differential Voltage (DC); Pin and Pin#
VID(AC)
POD differential Input Differential Voltage (AC); Pin and Pin#
VIN
POD single-ended Input Voltage; Pin and Pin#
VINS
POD single-ended Input Voltage Slew Rate; Pin and Pin#
VIX(AC)
POD differential Input Crossing Point Voltage (AC); Pin and
Pin#
Min
Typ
Max
Unit
1.26
1.05
1.15
VDDQ × 0.69
–
VREF + 0.08
–0.15
VREF + 0.15
–
VREF – 0.08
0.16
0.30
0.27
3
VREF – 0.08
1.3
1.1
1.2
VDDQ × 0.7
–
–
–
–
–
–
–
–
–
–
–
1.34
1.15
1.25
VDDQ × 0.71
0.5
VDDQ + 0.15
VREF – 0.08
–
VREF – 0.15
VREF + 0.08
–
–
VDDQ + 0.15
–
VREF + 0.08
V
V
V
V
V
V
V
V
V
V
V
V
V
V/ns
V
Notes
4. All voltages referenced to VSS (GND).
5. Peak to Peak AC noise on VREF must not exceed +/–2% VDDQ(DC).
6. VIH/VIL(DC) are specified with ODT disabled.
7. VIH/VIL(AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.
Document Number: 001-79552 Rev. *O
Page 30 of 46
CY7C4022KV13/CY7C4042KV13
Electrical Characteristics (continued)
Over the Operating Range
Parameter
IX [8]
IOZ [8]
IDD[9, 10]
Description
POD input leakage current
POD output leakage current
VDD operating supply (1066 MHz, × 18)
VDD operating supply (1066 MHz, × 36)
VDD operating supply (933 MHz, × 18)
VDD operating supply (933 MHz, × 36)
HSTL/SSTL Signaling Mode
VDD[11]
Core supply voltage (1.3 V ± 40 mV)
VDDQ [11]
I/O supply voltage (1.2 V ± 50 mV)
VREF(DC) [11, 12]
VREF(AC) [11, 12]
VIH(DC) [11, 13]
VIL(DC) [11, 13]
VIH(AC) [11, 14]
VIL(AC) [11, 14]
VOH(DC) [11]
VOL(DC) [11]
VIX
VDIF(AC)
VDIF(DC)
VDIF(CM)
VOX
VOUT(AC)
VOUT(DC)
IX [8]
IOZ [8]
IDD[9, 10]
I/O supply voltage (1.25 V ± 50 mV)
HSTL/SSTL reference voltage (DC)
HSTL/SSTL reference voltage (AC)
HSTL/SSTL high level input voltage (DC)
HSTL/SSTL low level input voltage (DC)
HSTL/SSTL high level input voltage (AC)
HSTL/SSTL low level input voltage (AC)
HSTL/SSTL high level output voltage (DC) –
IOH = –0.25 × VDDQ/ROH
HSTL/SSTL low level output voltage (DC) –
IOL = 0.25 × VDDQ/ROL
HSTL/SSTL input Voltage Cross point
HSTL/SSTL AC Input Differential Voltage
HSTL/SSTL DC Input Differential Voltage
HSTL/SSTL DC Common Mode Input
HSTL/SSTL Output voltage cross point
HSTL/SSTL AC Output Voltage
HSTL/SSTL DC Output Voltage
HSTL/SSTL input leakage current
HSTL/SSTL output leakage current
VDD operating supply (1066 MHz, × 18)
VDD operating supply (1066 MHz, × 36)
VDD operating supply (933 MHz, × 18)
VDD operating supply (933 MHz, × 36)
Min
Typ
Max
Unit
–
–
–
–
–
–
–
–
2800
3920
2520
3520
200
200
4100
4500
3400
4000
µA
µA
mA
mA
mA
mA
1.26
1.15
1.3
1.2
1.34
1.25
V
V
1.3
VDDQ × 0.52
VDDQ × 0.53
VDDQ + 0.15
VREF – 0.08
VDDQ + 0.24
VREF – 0.15
–
V
V
V
V
V
V
V
V
VDDQ × 0.25 VDDQ × 0.288
V
1.2
1.25
VDDQ × 0.48 VDDQ × 0.5
VDDQ × 0.47 VDDQ × 0.5
VREF + 0.8
–
–0.15
–
VREF + 0.15
–
–0.24
–
VDDQ × 0.712 VDDQ × 0.75
–
–
0.30
0.16
VDDQ × 0.4
–
–0.24
–0.15
–
–
–
–
–
–
VDDQ × 0.5
–
–
VDDQ × 0.5
VDDQ × 0.5
–
–
–
–
2800
3920
2520
3520
–
VDDQ + 0.48
VDDQ + 0.30
VDDQ × 0.6
–
VDDQ + 0.24
VDDQ + 0.15
200
200
4100
4500
3400
4000
V
V
V
V
V
V
V
µA
µA
mA
mA
mA
mA
Notes
8. Output driver into High Z with ODT disabled.
9. The operation current is calculated with 50% read cycle and 50% write cycle.
10. Typical operation current specifications are tested at 1.3V VDD.
11. All voltages referenced to VSS (GND).
12. Peak to Peak AC noise on VREF must not exceed +/–2% VDDQ(DC).
13. VIH/VIL(DC) are specified with ODT disabled.
14. VIH/VIL(AC) is a test condition specified to guarantee at which the receiver must meet its timing specifications with ODT enabled.
Document Number: 001-79552 Rev. *O
Page 31 of 46
CY7C4022KV13/CY7C4042KV13
Capacitance
Table 18. Capacitance
Parameter [15]
Description
CIN
Input capacitance
CO
Output capacitance
Test Conditions
Max
Unit
4
pF
4
pF
Test Conditions
361-ball FCBGA
Package
Unit
Test conditions follow standard With Still Air (0 m/s)
test methods and procedures for
With Air Flow (1 m/s)
measuring thermal impedance, in
accordance with EIA/JESD51.
With Air Flow (3 m/s)
12.00
°C/W
10.57
°C/W
9.09
°C/W
TA = 25 C, f = 1 MHz, VDD = 1.3 V, VDDQ = 1.25 V
Thermal Resistance
Table 19. Thermal Resistance
Parameter [15]
JA
Description
Thermal resistance
(junction to ambient)
JB
Thermal resistance
(junction to board)
3.03
°C/W
JC
Thermal resistance
(junction to case)
0.029
°C/W
AC Test Load and Waveform
Figure 7. AC Test Load and Waveform
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-79552 Rev. *O
Page 32 of 46
CY7C4022KV13/CY7C4042KV13
Switching Characteristics
Over the Operating Range [16, 17, 18, 19, 20, 21, 22, 23]
Cypress
Parameter
Description
1066 MHz
933 MHz
Min
Max
Min
Max
Unit
tCK
CK, DKx, QKx clock Period
0.938
3.333
1.071
3.333
ns
tCKL
CK, DKx LOW time
0.45*
–
0.45*
–
tCK
tCKH
CK, DKx HIGH time
tJIT(per)
Clock Period Jitter
tJIT(cc)
Cycle-to-cycle Jitter
tAS
A to CK setup
tAH
CK to A hold
tASH
CK to A setup-hold window
tCS
tCH
0.45*
–
0.45*
–
tCK
–0.055
0.055
–0.060
0.060
ns
–
0.110
–
0.120
ns
0.125
–
0.135
–
ns
0.125
–
0.135
–
ns
0.170
–
0.180
–
ns
LDx#, RWx# to CK setup
0.150
–
0.180
–
ns
CK to LDx#, RWx# hold
0.150
–
0.180
–
ns
tCSH
CK to LDx#, RWx# setup-hold window
0.170
–
0.180
–
ns
tCKDK
CK to DKx skew
–0.15
0.15
–0.172
0.172
ns
tIS
DQx, DINVx to DKx setup
0.125
–
0.135
–
ns
tIH
DKx to DQx, DINVx hold
0.125
–
0.135
–
ns
tISH0
DKx[0] to DQx[17:0], DINVx[0] (× 36) or
DKx[0] to DQx[8:0], DINVx[0] (× 18) setup-hold window
0.150
–
0.180
–
ns
tISH1
DKx[1] to DQx[35:18], DINVx[1] (× 36) or
DKx[1] to DQx[17:9], DINVx[1] (× 18) setup-hold window
0.150
–
0.180
–
ns
tRise (se)
Single ended Output Signal Rise Time 20%–80%
2
6
2
6
V/ns
tFall (se)
Single ended Output Signal Fall Time 20%–80%
2
6
2
6
V/ns
tRise (diff)
Differential Output Signal Rise Time 20%–80%
3
10
3
10
V/ns
tFall (diff)
Differential Output Signal Fall Time 20%–80%
3
10
3
10
V/ns
tQKL
QKx LOW time
0.45*
–
0.45*
–
tCK
tQKH
QKx HIGH time
0.45*
–
0.45*
–
tCK
tCKQK
CK to QKx skew
–0.225
0.225
–0.257
0.257
ns
tQKQ0
QKx[0] to DQx[17:0], DINVx[0] (× 36) or
QKx[0] to DQx[8:0], DINVx[0] (× 18)
–
0.075
–
0.085
ns
tQH0
QKx[0] to DQx[17:0], DINVx[0] (× 36) or
QKx[0] to DQx[8:0], DINVx[0] (× 18)
0.40*
–
0.40*
–
tCK
tQKQ1
QKx[1] to DQx[35:18], DINVx[1] (× 36) or
QKx[1] to DQx[17:9], DINVx[1] (× 18)
–
0.075
–
0.085
ns
tQH1
QKx[1] to DQx[35:18], DINVx[1] (× 36) or
QKx[1] to DQx[17:9], DINVx[1] (× 18)
0.40*
–
0.40*
–
tCK
Notes
16. x refers to Port A and Port B. For example, DQx refers to DQA and DQB.
17. Input hold timing assumes rising edge slew rate of 4 V/ns measured from VIL/VIH (DC) to VREF.
18. Input setup timing assumes falling edge slew rate of 4 V/ns measured from VREF to VIL/VIH (AC).
19. All output timing assumes the load shown in Figure 8.
20. Setup/hold window, tASH, tCSH, tISH are used for pin to pin timing budgeting and cannot be directly applied without performing de-skew training.
21. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
22. Frequency drift is not allowed.
23. tQKL, tQKH, tQKQ, tQKQX, tASH, tCSH and tISH are guaranteed by design.
Document Number: 001-79552 Rev. *O
Page 33 of 46
CY7C4022KV13/CY7C4042KV13
Switching Characteristics (continued)
Over the Operating Range [16, 17, 18, 19, 20, 21, 22, 23]
Cypress
Parameter
Description
1066 MHz
933 MHz
Min
Max
Min
Max
Unit
tQKQV0
QKx[0] to QVLDx
–
0.112
–
0.128
ns
tQVH0
QKx[0] to QVLDx
0.85*
–
0.85*
–
tCK
tQKQV1
QKx[1] to QVLDx
–
0.112
–
0.128
ns
tQVH1
QKx[1] to QVLDx
0.85*
–
0.85*
–
tCK
tPWR
VDD (Typical) to the first access
200
–
200
–
ms
tRSS
RST# pulse width
200
–
200
–
µs
tRSH
RST# deasserted to first active command
400000*
–
400000*
–
tCK
tRDS
A to RST# setup
500*
–
500*
–
tCK
tRDH
A to RST# hold
500*
–
500*
–
tCK
tTSS
TRST# pulse width
200
–
200
–
µs
tTSH
TRST# deasserted to first JTAG command
200
–
200
–
µs
tPLL
Time for PLL to stabilize after being reset
–
100
–
100
µs
tLBL
Loopback Latency
16*
16*
16*
16*
tCK
tCD
Loopback Output Delay
–
5
–
5
ns
tCFGS
Active mode to Configuration mode
32*
–
32*
–
tCK
tCFGH
Configuration mode to Active mode Register Access
without ODT or PLL programming updates
32*
–
32*
–
tCK
tCFGH
Configuration mode to Active mode Register Access with
ODT programming updates
4096*
–
4096*
–
tCK
tCFGH
Configuration mode to Active mode Register Access with
PLL programming updates
100
–
100
–
µs
tCFGD
Configuration command to Configuration command
80*
–
80*
–
tCK
tCLDS
CFG# assertion to LDA# assertion
32*
–
32*
–
tCK
tCLDH
LDA# deassertion to CFG# deassertion
32*
–
32*
–
tCK
tCFGA
CFG# assertion to Address assertion
16*
–
16*
–
tCK
tCLDW
LDA# pulse width for Configuration command
16*
–
16*
–
tCK
tCRDL
LDA# assertion to Read Data Latency
–
32*
–
32*
tCK
tCRDH
CFG# deassertion to Read Data Hold
0*
32*
0*
32*
tCK
tDQVLD
DQAx to QVLDA<0> in Configuration mode
-2
2
–2
2
tCK
Document Number: 001-79552 Rev. *O
Page 34 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms
Figure 8. Rise and Fall Time Definitions for Output Signals
Nominal Rise-Fall Time Definition for Single-Ended Output Signals
Nominal Rise-Fall Time Definition for Differential Output Signals
Document Number: 001-79552 Rev. *O
Page 35 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 9. Input and Output Timing Waveforms
Address and Command Input Timing
Data Input Timing
Data Output Timing
Document Number: 001-79552 Rev. *O
Page 36 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 10. Waveforms for 8.0 Cycle Read Latency (Read to Write Timing Waveform)
Figure 11. Waveforms for 8.0 Cycle Read Latency (Write to Read Timing Waveform)
Document Number: 001-79552 Rev. *O
Page 37 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 12. Configuration Write Timing Waveform
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
Figure 13. Configuration Read Timing Waveform
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
Document Number: 001-79552 Rev. *O
Page 38 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 14. Configuration Write and Read Timing Waveform
(a) Configuration Multiple Cycle - Write followed by Read Operation
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
(b) Configuration Multiple Cycle - Back to Back Read Operation
Note: DQA[x:8] and DQB data bus is a don’t care in Configuration Mode
Note: It is recommended to keep CFG# asserted during the configuration write or read operation
Document Number: 001-79552 Rev. *O
Page 39 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 15. Loopback TIming
Document Number: 001-79552 Rev. *O
Page 40 of 46
CY7C4022KV13/CY7C4042KV13
Switching Waveforms (continued)
Figure 16. Reset TImings
Document Number: 001-79552 Rev. *O
Page 41 of 46
CY7C4022KV13/CY7C4042KV13
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page
at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
1066
Package
Diagram
Ordering Code
CY7C4022KV13-106FCXC
Package Type
Operating
Range
001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free
Commercial
001-70319 361-ball FCBGA (21 × 21 × 2.515 mm) Pb-free
Commercial
CY7C4042KV13-106FCXC
933
CY7C4022KV13-933FCXC
CY7C4042KV13-933FCXC
CY7C4022KV13-933FCXI
Industrial
Ordering Code Definitions
CY
7
C
40x2
K
V13 - XXX
FC
X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: 361-ball Flip Chip BGA
Speed Grade: 106 = 1066 MHz or 933 = 933 MHz
VDD = 1.3 V
Die Revision: K = 65nm
Part Identifier: 4022 or 4042
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-79552 Rev. *O
Page 42 of 46
CY7C4022KV13/CY7C4042KV13
Package Diagram
Figure 17. 361-ball FCBGA (21 × 21 × 2.515 mm) FR0AA Package Outline, 001-70319
001-70319 *D
Document Number: 001-79552 Rev. *O
Page 43 of 46
CY7C4022KV13/CY7C4042KV13
Acronyms
Document Conventions
Table 20. Acronyms used in this document
Acronym
Description
Units of Measure
Table 21. Units of Measure
DDR
Double Data Rate
RTR
Random Transaction Rate
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
EMI
Electromagnetic Interference
µA
microampere
FCBGA
Flip-Chip Ball Grid Array
µs
microsecond
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
JTAG
Joint Test Action Group
ms
millisecond
LMBU
Logical Multiple Bit Upset
mV
millivolt
LSB
Least Significant Bit
ns
nanosecond
LSBU
Logical Single Bit Upset

ohm
MSB
Most Significant Bit
%
percent
ODT
On-Die Termination
pF
picofarad
PLL
Phase Locked Loop
V
volt
QDR
Quad Data Rate
W
watt
SDR
Single Data Rate
SEL
Single Event Latch-up
SER
Soft Error Rate
SRAM
Static Random Access Memory
TAP
Test Access Port
TCK
Test Clock
TDI
Test Data-In
TDO
Test Data-Out
TMS
Test Mode Select
Document Number: 001-79552 Rev. *O
Symbol
Unit of Measure
Page 44 of 46
CY7C4022KV13/CY7C4042KV13
Document History Page
Document Title: CY7C4022KV13/CY7C4042KV13, 72-Mbit QDR™-IV XP SRAM
Document Number: 001-79552
Rev.
ECN
Submission
Date
Orig. of
Change
*G
4283232
03/25/2014
PRIT
Post to web.
*H
4414677
06/20/2014
PRIT
Updated AC Test Load and Waveform:
Updated Figure 7 (Changed value of RQ resistor from 200  to 180 ).
Description of Change
Updated Switching Characteristics:
Added tASH, tCSH, tISH parameters and their details.
Updated Note 20 and 23.
Completing Sunset Review.
*I
4504029
09/16/2014
PRIT
Updated Switching Characteristics:
Updated Note 23.
Updated Package Diagram:
spec 001-70319 – Changed revision from *C to *D.
*J
4575129
11/20/2014
PRIT
Updated Functional Description:
Added “For a complete list of related resources, click here.” at the end.
*K
4710842
04/02/2015
PRIT
Updated Operating Range:
Replaced “Case Temperature (TC)” with “Ambient Temperature (TA)” in column
heading.
*L
4951480
10/07/2015
PRIT
Updated Logic Block Diagram – CY7C4042KV13.
Updated Switching Characteristics:
Changed maximum value of tCK parameter from 1.875 ns to 3.333 ns for
1066 MHz speed bin.
Changed maximum value of tCK parameter from 2.143 ns to 3.333 ns for
933 MHz speed bin.
Removed Errata.
Updated to new template.
*M
5157690
03/01/2016
PRIT
Added Industrial Temperature Range related information in all instances across
the document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*N
5381153
07/29/2016
PRIT
Updated Switching Characteristics:
Added tCFGA parameter and its details.
Updated Switching Waveforms:
Updated Figure 12, Figure 13, and Figure 14.
*O
5843004
08/03/2017
AJU
Updated to new template.
Completing Sunset Review.
Added Errata.
Document Number: 001-79552 Rev. *O
Page 45 of 46
CY7C4022KV13/CY7C4042KV13
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
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the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-79552 Rev. *O
Revised August 3, 2017
Page 46 of 46