CMX994/CMX994A/CMX994E Direct Conversion Receivers CML Microcircuits COMMUNICATION SEMICONDUCTORS CMX994 / CMX994A (lower power consumption) / CMX994E (enhanced performance) D/994_994A_994E/1 September 2015 DATASHEET Provisional Features Applications Direct conversion receiver family with PowerTrade™ flexible power vs. performance modes CMX994 - Standard and low power modes CMX994A - Standard and additional low power modes CMX994E - Enhanced, standard and low power modes Rx single conversion to zero IF, near-zero IF or low IF; zero IF eliminates image responses Very high mixer IIP2 for practical zero IF receiver 100MHz to 1000MHz I/Q demodulator (CMX994A/E) 100MHz to 940MHz I/Q demodulator (CMX994) Extended operation down to 50MHz LNA with gain control Precise filtering with 1:2:4 bandwidth select control Mixer Bandwidth up to 20MHz Local Oscillator LO synthesiser VCO negative resistance amplifier Rx LO divide by 2, 4 or 6 modes Tx LO Output with divide by 1, 2, 4, or 6 modes 3.0V – 3.6V Low power Operation Small size 40-pin VQFN Package Analogue/digital multi-mode radio Software Defined Radio (SDR) Data telemetry modems Satellite communications Constant envelope and linear modulation Rx function compatible with CMX998 Cartesian Feedback Loop Transmitter Narrowband e.g. 25kHz, 12.5kHz, 6.25kHz Wideband Data e.g. >1MHz bandwidth I/Q Signals CMX994 CMX994A CMX994E T/R Ref. Osc. Direct Conversion Receiver Tx LO 1 Baseband Signal Processing C-BUS Reset Rx Enable Tx Enable µC Flash Brief Description The CMX994/CMX994A/CMX994E is a family of direct conversion receiver ICs with PowerTrade™, the ability to dynamically select power vs. performance modes to optimise operating trade-offs. All three devices include a broadband LNA with gain control followed by a high dynamic range, very high IIP2, I/Q demodulator. The receiver baseband section includes amplifiers and precise, configurable bandwidth, baseband filter stages. LO generation is provided by an integer-N PLL and a VCO negative resistance amplifier; an external LO may also be used. LO dividers are provided for flexible multi-band operation. The devices operate from a single 3.3V supply over a temperature range of –40°C to +85°C and are available in a small 40pin VQFN (Q4) package. Relative to the CMX994 the CMX994A enables a significant reduction in power by allowing LO phase correction to be turned off. A further reduction is made possible by the facility to disable either the I or Q channel. The CMX994E expands on that by adding an enhanced performance mode that features improved intermodulation in the receive path mixers. 2015 CML Microsystems Plc D/994_A_E/1 Page 1 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E CONTENTS Section Page 1 Brief Description...................................................................................................................................... 1 2 History ..................................................................................................................................................... 5 3 Block Diagram ......................................................................................................................................... 6 4 4.1 4.2 Pin and Signal List .................................................................................................................................... 7 Signal Definitions ............................................................................................................................................8 Connection of Unused Pins .............................................................................................................................8 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 External Components .............................................................................................................................. 9 Power Supply and Decoupling ........................................................................................................................9 Receiver ..........................................................................................................................................................10 LNA..................................................................................................................................................................10 Mixers and Baseband Section .........................................................................................................................13 Local Oscillator ................................................................................................................................................15 Local Oscillator Input ......................................................................................................................................15 VCO and PLL ..............................................................................................................................................15 RESETN ............................................................................................................................................................16 6 6.1 6.1.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.3 6.3.1 6.3.2 General Description ................................................................................................................................. 17 General Operation ..........................................................................................................................................18 RX/Tx Enable ..............................................................................................................................................18 Receiver Operation .........................................................................................................................................18 DC Offset Correction .......................................................................................................................................18 Receiver Filters and Bandwidth Options.........................................................................................................19 Baseband Filter Design and Required Correction ...........................................................................................20 Operation at Wider Bandwidths .....................................................................................................................21 Local Oscillator Operation ..............................................................................................................................21 PLL ..............................................................................................................................................22 PLL Enable ..............................................................................................................................................23 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.8 C-BUS Interface and Register Descriptions .............................................................................................. 24 General Reset - $10 (no data) .........................................................................................................................25 General Control Register ................................................................................................................................26 General Control - $11 - 8-bit write only ..........................................................................................................26 General Control - $E1 - 8-bit read only ...........................................................................................................26 Rx Control Register .........................................................................................................................................27 Rx Control - $12 – 8-bit write only ..................................................................................................................27 Rx Control - $E2 – 8-bit read only ...................................................................................................................27 Rx Offset Register ...........................................................................................................................................28 Rx Offset - $13 – 8-bit write only ....................................................................................................................28 Rx Offset - $E3 - 8-bit Read only .....................................................................................................................28 Intermodulation Control Register ...................................................................................................................29 IM Control - $14 – 8-bit write only .................................................................................................................29 IM Control - $E4 – 8-bit read only...................................................................................................................29 Rx Gain Register ..............................................................................................................................................31 Rx Gain - $16 – 8-bit write only ......................................................................................................................31 Rx Gain - $E6 – 8-bit read only ........................................................................................................................31 PLL M Divider Register ....................................................................................................................................33 PLL M Divider - $22 - $20 – 8-bit write only....................................................................................................33 PLL M Divider - $D2-$D0 - 8-bit read only ......................................................................................................33 PLL R Divider Register .....................................................................................................................................34 2015 CML Microsystems Plc D/994_A_E/1 Page 2 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.8.1 7.8.2 7.9 7.9.1 7.9.2 PLL R Divider - $24 - $23 – 8-bit write only .....................................................................................................34 PLL R Divider - $D4-$D3 – 8-bit read only .......................................................................................................34 VCO Control Register ......................................................................................................................................35 VCO Control - $25 - 8-bit write only................................................................................................................35 VCO Control - $D5 - 8-bit read only ................................................................................................................35 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.2 8.3 8.4 Application Notes .................................................................................................................................... 36 Typical Receiver Performance ........................................................................................................................36 System Performance .......................................................................................................................................36 DC Offsets .......................................................................................................................................................37 Gain Control ....................................................................................................................................................38 LNA Intermodulation Optimisation ................................................................................................................41 Low Power Mode ............................................................................................................................................42 I/Q Filter Response .........................................................................................................................................42 Baseband Intermodulation .............................................................................................................................43 LO Pulling ........................................................................................................................................................43 Rx Mixer Output (Broadband Operation) .......................................................................................................44 Spurious Responses ........................................................................................................................................45 Operation Below 100MHz...............................................................................................................................46 Transmitter LO Output....................................................................................................................................46 Modem Solutions ............................................................................................................................................48 9 9.1 9.1.1 9.1.2 9.2.1 Performance Specification ....................................................................................................................... 50 Electrical Performance ....................................................................................................................................50 Absolute Maximum Ratings ............................................................................................................................50 Operating Limits..............................................................................................................................................50 Operating Characteristics ...............................................................................................................................51 AC Parameters – Direct Conversion Receiver Sections ....................................................................................54 AC Parameters – Tx Output.............................................................................................................................58 AC Parameters – C-BUS ...................................................................................................................................59 Packaging ........................................................................................................................................................60 9.3 2015 CML Microsystems Plc D/994_A_E/1 Page 3 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Table Table 1 Definition of Power Supply and Reference Voltages Table 2 Decoupling Components Table 3 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 50Ω Table 4 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 100Ω Mode Table 5 150MHz LNA and Inter-stage Components (100Ω output mode) Table 6 450MHz LNA and Inter-stage Components (100Ω output mode) Table 7 900MHz LNA and Inter-stage Components (50Ω output mode) Table 8 CMX994 Rx Mixer Input Impedances and Parallel Equivalent Circuit Table 9 CMX994A/CMX994E Rx Mixer Input Impedances and Parallel Equivalent Circuit Table 10 Receiver Components Table 11 Internal VCO Amplifier Tank Circuit for 440MHz Operation Table 12 3rd Order Loop Filter Circuit Values Table 13 Tx (or Rx) Enable Operation Table 14 DC OffsetCorrection Adjustments Table 15 Typical LNA Gain Step Sizes at 100MHz, ZO=100Ω Table 16 Typical LNA Gain Step Sizes at 450MHz, ZO=100Ω Table 17 Typical LNA Gain Step Sizes at 940MHz, ZO=50Ω Table 18 50MHz LNA and Inter-stage Components (100Ω mode) Table 19 Summary of Results for the Complete Rx Chain at 50MHz Table 20 Modulation/Modem Combinations Page 7 8 10 11 11 11 12 12 13 13 15 15 17 18 38 39 40 45 45 47 Figure Figure 1 Block Diagram Figure 2 Recommended Power Supply Connections and Decoupling Figure 3 LNA S11 (50Ω Mode) Figure 4 LNA S22 (50Ω Mode) Figure 5 LNA S11 (100Ω Mode) Figure 6 LNA S22 (100Ω Mode) Figure 7 Recommended LNA Configuration and Inter-stage Match Figure 8 Rx Mixer Impedance Figure 9 Recommended Receiver Circuit Figure 10 Example External Components – VCO External Tank Circuit Figure 11 Example External Components – PLL Loop Filter Figure 12 Simplified Schematic of How DC Offset Corrections are Applied Figure 13 Baseband I/Q Filtering Figure 14 Schematic Representation of Filters Used in the I and Q Paths Figure 15 Local Oscillator Figure 16 C-BUS Transactions Figure 17 CMX994 and CMX7164 with FI-2 – Typical 4FSK Sensitivity (19.2kbps) Figure 18 I/Q Path DC Offsets Figure 19 Example Variation in Voffset with Gain Control Setting Figure 20 Gain Control Figure 21 Variation of LNA Gain and IMD with IM Register Setting, 450MHz Figure 22 I/Q Filter Response Figure 23 Baseband Intermodulation Test at circa 6Vp-p Differential Output Figure 24 External Baseband Circuit Connections to Mixer Figure 25 Rx Mixer Output Bandwidth Page 5 8 9 9 10 10 11 12 13 14 15 17 18 19 21 24 35 36 37 37 41 41 42 43 44 2015 CML Microsystems Plc D/994_A_E/1 Page 4 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Figure 26 Typical Gain and NF Variation of Demodulator Stages at Low Frequencies Figure 27 Tx Output Level vs. Frequency Figure 28 Typical Tx Output Level (With Divider) vs Temperature Figure 29 Typical Tx Output Level (No Divider) vs. Temperature for Varying LO Input Level Figure 30 C-BUS Timing Figure 31 Q4 Mechanical Outline 2 45 46 46 47 58 59 History Version 1 Changes First published document as Provisional status Date August 2015 It is recommended that you check for the latest product datasheet version from the Product page of the CML website: [www.cmlmicro.com]. 2015 CML Microsystems Plc D/994_A_E/1 Page 5 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Block Diagram QFLT2N QFLT2P IFLT2N IFLT2P RREF QFLT1N QFLT1P IFLT1N MIXIN LNAOUT IFLT1P Optional Bandpass Filter VCCLNA 3 RXIP LNA T/R Tx RXIN LNA IN I Channel /6 /4 /2 VCCRF VCCRXIF VCCLO VCCSYNTH RXEN TXEN RXQP RXQN C-BUS Control Interface Q Channel CSN RDATA SCLK CDATA RESETN /6 /4 /2 /1 PLL VCO 1 External Resonator and Varactors FREF DO LOP LON VCOP2 VCON1 VCOP1 VCON2 TXLO DGND AGND DVDD VDDIO Alternative Local Oscillator Reference Oscillator Figure 1 Block Diagram 2015 CML Microsystems Plc D/994_A_E/1 Page 6 of 70 Direct Conversion Receivers 4 CMX994/CMX994A/CMX994E Pin and Signal List Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name IFLT2N IFLT1P IFLT1N VCCRXIF VCCLNA LNAIN LNAOUT VCCRF MIXIN TXLO VCCLO LOP LON VCOP1 VCOP2 VCON1 VCON2 VCCSYNTH FREF DO DGND TXEN RXEN CSN RDATA SCLK CDATA RESETN DVDD VDDIO RREF QFLT1N QFLT1P QFLT2N QFLT2P RXQP RXQN RXIP RXIN IFLT2P Type IP IP IP PWR PWR IP OP PWR IP OP PWR IP IP IP IP IP IP PWR IP OP PWR IP IP IP TSOP IP IP IP PWR PWR IP IP IP IP IP OP OP OP OP IP EXPOSED METAL PAD AGND PWR Pin Function nd I channel 2 filter capacitor negative st I channel 1 filter capacitor positive st I channel 1 filter capacitor negative Supply for baseband circuits Supply for LNA LNA input LNA output Supply for RF circuits Rx mixer input LO output for Tx Supply for LO sections PLL LO positive input PLL LO negative input PLL VCO positive input 1 PLL VCO positive input 2 PLL VCO1 negative input 1 PLL VCO1 negative input 2 Supply to Integer N PLL Reference frequency input PLL Charge Pump output Digital ground Tx Enable Rx Enable C-BUS Chip Select C-BUS Data output C-BUS Clock input C-BUS Data input C-BUS/Device Reset (Reset when pin Low) Supply to digital circuits Supply to C-BUS circuits Reference resistor for I/Q Filters st Q channel 1 filter capacitor negative st Q channel 1 filter capacitor positive nd Q channel 2 filter capacitor negative nd Q channel 2 filter capacitor positive RxQ positive output RxQ negative output RxI positive output RxI negative output nd I channel 2 filter capacitor positive The exposed metal pad must be electrically connected to analogue ground. Total = 41 Pins (40 pins and central, exposed metal ground pad) 2015 CML Microsystems Plc D/994_A_E/1 Page 7 of 70 Direct Conversion Receivers Notes: 4.1 I/P O/P BI = = = CMX994/CMX994A/CMX994E Input Output Bidirectional T/S NC PWR = = = 3-state Output No Connection Power Signal Definitions Signal Name Vmax AVDD DVDD VDDIO DVSS (GND) AVSS (GND) Pins VCCRF, VCCRXIF, VCCSYNTH, VCCLO VCCLNA (see note) DVDD VDDIO DGND AGND Usage The maximum value of the supplies DVDD and AVDD Power supply for analogue circuits Power supply for digital circuits Power supply voltage for digital interface (C-BUS) Ground for digital circuits Ground for analogue circuits Table 1 Definition of Power Supply and Reference Voltages Note: The LNA has a separate power connection pin to provide isolation of non-differential signals. This may be connected to a common external supply with suitable de-coupling. 4.2 Connection of Unused Pins If the CMX994/CMX994A/CMX994E VCO and PLL functions are not used then pins FREF, DO, VCOP1, VCOP2, VCON1 and VCON2 may be left unconnected. 2015 CML Microsystems Plc D/994_A_E/1 Page 8 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 5 External Components 5.1 Power Supply and Decoupling The CMX994/CMX994A/CMX994E have separate supply pins for the analogue and digital circuitry; a 3.3V nominal supply is recommended for all circuits but the data interface can run at a lower voltage than the rest of the device by setting the VDDIO supply to the required interface voltage. R7 DVDD DVDD R6 VDDIO R5 VCCRF R4 VCCRXIF AVDD R3 VCCLNA R2 AVDD VCCLO VCCSYNTH R1 C7 C6 C5 C4 C3 C2 C1 GND Plane for: AGND GND GND for: DGND Figure 2 Recommended Power Supply Connections and Decoupling C1 C2 C3 C4 C5 C6 C7 10nF 10nF 33pF//10nF 10nF 10nF 10nF 10nF R1 R2 R3 R4 R5 R6 R7 10Ω 3.3Ω 3.3Ω 3.3Ω 3.3Ω 10Ω 10Ω Table 2 Decoupling Components Notes: 1. Maximum Tolerances: Resistors 5%, capacitors 20%. 2. 3. 4. 5. It is expected that any low-frequency interference on the 3.3 Volt supply will be removed by active regulation; a large capacitor is an alternative but may require more board space and so may not be preferred. It is particularly important to ensure that there is no interference from the VDDIO (which supplies the digital I/O) or from any other circuit that may use the DV DD supply (such as a microprocessor), to sensitive analogue supplies (AVDD). It is therefore advisable to use separate power supplies for digital and analogue circuits. The supply decoupling shown is intended for RF noise suppression. It is necessary to have a small series impedance prior to the decoupling capacitor for the decoupling to work well. This may be achieved cost effectively by using the resistor and capacitor values shown. The use of resistors results in small dc voltage drops (up to approx 0.1V). Choosing resistor values approximately inversely proportional to the dc current requirements of each supply ensures the dc voltage drop on each supply is reasonably matched. In any case, the resultant dc voltage change is well within the design tolerance of the device. If higher impedance resistors are used (not recommended) then greater care will be needed to ensure the supply voltages are maintained within tolerance, even when parts of the device are enabled or disabled. It is advisable to have separate ground planes for analogue and digital circuits. Separate regulators for local oscillator sections (VCCLO, VCCSYNTH) may be beneficial depending on circuit noise and type of regulator and this is why two AV DD connections are shown. 2015 CML Microsystems Plc D/994_A_E/1 Page 9 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 5.2 Receiver 5.2.1 LNA The following sections show plots and tables of the LNA input (S 11) and output (S22) impedance. Separate data is shown for the 50 and 100 output modes which are selected by LNAZO bit in the Rx Gain Register (b3, $16; see section 7.7.1). Note that at low frequencies capacitive loads on the LNA output are not recommended, a high-pass matching network is preferred. 50Ω Mode Figure 3 LNA S11 (50Ω Mode) Figure 4 LNA S22 (50Ω Mode) 2015 CML Microsystems Plc D/994_A_E/1 Page 10 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E S11 Freq (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 S22 Impedance (Ω-/+jΩ) Equivalent Parallel Circuit (R//C) Impedance (Ω-/+jΩ) 347 – j296 208 – j263 129 – j217 93 – j181 72 – j154 58 – j130 49 – j114 42 – j102 37.7 – j91 33.9 – j83 29.7 – j74 27.0 – j66 24.7 – j61 22.8 – j55 21.3 – j50 19.9 – j45 18.7 – j41 17.2 – j37.0 15.7 – j32.9 14.8 – j29.1 598.9R // 4.5pF 540.7R // 3.7pF 496R // 3.6pF 444.5R // 3.5pF 401.1R // 3.4pF 351R // 3.4pF 318R // 3.4pF 286.5R // 3.3pF 256.3R // 3.3pF 235.3R // 3.3pF 211.8R // 3.4pF 190.6R // 3.4pF 173.1R // 3.5pF 154.9R // 3.5pF 136.7R // 3.6pF 121.5R // 3.7pF 107R // 3.8pF 96.7R // 3.9pF 84.6R // 4.1pF 72R // 4.3pF 54.4 – j2.4 54.8 + j0.4 55.3 + j1.7 56.1 + j2.9 56.9 + j3.5 57.4 + j3.9 57.7 + j4.0 58.1 + j3.9 58.4 + j4.0 58.4 + j4.2 58.3 + j4.1 57.9 + j3.9 57.3 + j3.8 56.7 + j3.9 55.9 + j3.7 55.3 + j3.6 54.3 + j3.6 52.8 + j3.9 51.5 + j4.7 50.7 + j5.1 Equivalent Parallel Circuit (R//C) 54.5R // 2.6pF 54.8R 55.4R 56.3R 57.1R 57.6R 58.0R 58.4R 58.7R 58.7R 58.6R 58.2R 57.6R 57.0R 56.1R 55.5R 54.5R 53.1R 51.9R 51.2R Table 3 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 50Ω Mode 100Ω Mode Figure 5 LNA S11 (100Ω Mode) Figure 6 LNA S22 (100Ω mode) 2015 CML Microsystems Plc D/994_A_E/1 Page 11 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Freq (MHz) S11 Equivalent Parallel Circuit (R//C) 592.6R // 4.4pf 549.1R // 3.7pF 510.6R // 3.6pF 469.9R // 3.4pF 422.4R // 3.4pF 376.9R // 3.4pF 345.3R // 3.4pF 313.1R // 3.4pF 279.2R // 3.4pF 253R // 3.4pF 228.9R // 3.5pF 203.6R // 3.6pF 183.3R // 3.7pF 162.3R // 3.8pF 140.8R // 3.9pF 122.2R // 4pF 105.5R // 4.1pF 92.2R // 4.3pF 79.6R // 4.5pF 66.6R // 4.8pF Impedance (Ω-/+jΩ) 355 – j291 210 – j267 128 – j222 92 – j186 70 – j157 56 – j134 45 – j117 38 – j103 34.1 – j91 30.5 – j82 26.4 – j73 24.0 – j66 21.7 – j59 19.9 – j53 18.7 – j47.7 17.5 – j42.8 16.5 – j38.3 15.4 – j34.4 14.2 – j30.5 13.4 – j26.7 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Impedance (Ω-/+jΩ) 106 – j7.35 105 – j9.5 104 – j2.8 103 – j15.7 101 – j18.6 98 – j21.4 96 – j23.9 93 – j26.2 90 – j27.8 87 – j28.9 83 – j29.7 80 – j30.5 76 – j30.7 73 – j30.5 69 – j30.5 66 – j30.0 63 – j29.5 60 – j28.4 57 – j27.1 54 – j26.0 S22 Equivalent Parallel Circuit (R//C) 106.6R // 2.1pF 106R // 1.4pF 105.7R // 1.2pF 105.3R // 1.2pF 104.4R // 1.1pF 103R // 1.1pF 101.5R // 1.1pF 99.9R // 1.1pF 98.3R // 1.1pF 96.1R // 1.1pF 93.7R // 1.1pF 91.3R // 1.1pF 88.6R // 1.1pF 85.6R // 1.1pF 82.6R // 1.1pF 79.7R // 1.1pF 76.7R // 1.2pF 73R // 1.2pF 69.5R // 1.2pF 66.3R // 1.2pF Table 4 LNA S11 and S22 Impedances and Parallel Equivalent Circuit in 100Ω Mode L1 L3 MIXIN LNAOUT C2 VCC LNA C3 C1 RF Input LNA IN LNA L2 LO Figure 7 Recommended LNA Configuration and Inter-stage Match C1 C2 C3 1nF 33pF // 10nF 18pF L1 L2 L3 150nH 2.7pF (capacitor) 150nH Table 5 150MHz LNA and Inter-stage Components (100Ω output mode) C1 C2 C3 1nF 33pF // 10nF 10pF L1 L2 L3 39nH 82nH 27nH Table 6 450MHz LNA and Inter-stage Components (100Ω output mode) 2015 CML Microsystems Plc D/994_A_E/1 Page 12 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E C1 C2 C3 100pF 33pF //10nF 4.7pF L1 L2 L3 12nH 8.7nH 5.6nH Table 7 900MHz LNA and Inter-stage Components (50Ω output mode) 5.2.2 Mixers and Baseband Section Figure 8 is a plot of the typical Rx Mixer input impedance; Table 8 gives the measured impedances and the equivalent parallel circuit at some particular frequencies. Figure 8 Rx Mixer Input Impedance Frequency (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 Impedance (Ω-/+jΩ) 180 – j35.2 168 – j49.1 153 – j64 138 – j73 124 – j77 108 – j79 96 – j79 85 – j77 76 – j74 69 – j70 61 – j66 55 – j62 50 – j58 46.1 – j53 42.7 – j48.9 39.8 – j45.3 37.2 – j41.6 34.8 – j38.1 32.3 – j34.9 30.3 – j31.6 Parallel Equivalent Circuit (R // pF) 186.6R // 3.34pF 182.4R // 2.6pF 180.1R/ / 2.5pF 176.4R // 2.4pF 171.4R // 2.3pF 165.8R // 2.3pF 160R // 2.3pF 154.1R // 2.3pF 147.3R // 2.3pF 139.8R // 2.3pF 131.5R // 2.4pF 124R // 2.4pF 116R // 2.4pF 107.1R // 2.4pF 98.9R // 2.5pF 91.4R // 2.5pF 83.7R // 2.5pF 76.6R // 2.5pF 70.2R // 2.6pF 63.2R // 2.6pF Table 8 CMX994 Rx Mixer Input Impedances and Parallel Equivalent Circuit 2015 CML Microsystems Plc D/994_A_E/1 Page 13 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Frequency (MHz) 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 Impedance (Ω-/+jΩ) 172.74-j31.22 162.72-j47.25 148.61-j59.99 132.91-j69.33 116.95-j74.15 101.79-j75.64 88.21-j74.62 76.188-j71.96 66.61-j69.13 58.42-j65.09 52.03-j61.31 46.01-j57.03 41.25-j52.94 37.19-j49.13 34.2-j45.37 31.82-j41.75 29.54-j38.33 27.05-j35.15 24.62-j31.62 22.89-j28.17 21.58-j24.89 20.55-j21.44 19.56-j18.01 18.55-j14.59 Parallel Equivalent Circuit (R // pF) 178.38R//3.23pF 176.44R//2.62pF 172.83R//2.48pF 169.07R//2.46pF 163.96R//2.46pF 158R//2.5pF 151.33R//2.54pF 144.15R//2.61pF 138.36R//2.65pF 130.94R//2.71pF 124.28R//2.74pF 116.7R//2.82pF 109.19R//2.88pF 102.15R//2.94pF 94.39R//2.98pF 86.6R//3.01pF 79.28R//3.06pF 72.73R//3.16pF 65.23R//3.3pF 57.56R//3.4pF 50.29R//3.48pF 42.92R//3.52pF 36.14R//3.53pF 30.03R//3.47pF RREF C3 IFLT2N IFLT2P C1 IFLT1N MIXIN IFLT1P Table 9 CMX994A/CMX994E Rx Mixer Input Impedances and Parallel Equivalent Circuit R1 RXIP RXIN LO RXQP C4 QFLT2N QFLT2P C2 QFLT1N QFLT1P RXQN Figure 9 Recommended Receiver Circuit C1 C2 C3 1.5nF 1.5nF 3.9nF C4 R1 3.9nF 10kΩ Table 10 Receiver Components The bandwidth of the first baseband filters is set by capacitors C1 and C2. Capacitors C3 and C4 together with the reference resistor R1 set the bandwidth of the second baseband filters. Component selection will vary depending on the desired filter bandwidths. For further details see sections 6.2.2 and 6.2.3. 2015 CML Microsystems Plc D/994_A_E/1 Page 14 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 5.3 Local Oscillator 5.3.1 Local Oscillator Input LON and LOP signals form a differential signal pair however the LO input may be driven by a single-ended source, in which case pin LOP should be connected to the LO signal and LON may be connected directly to ground. The inputs have internal ac coupling, so external dc blocking capacitors are not required. 5.3.2 VCO and PLL A typical configuration for using the internal VCO negative resistance amplifier at 440MHz is shown in Figure 10. For the other external components required to complete the PLL (the loop filter components) see Figure 11 which shows a third-order loop filter. Typical values for a 500Hz bandwidth are given in Table 12. VCOP1 should be shorted directly to VCOP2 and similarly VCON1 to VCON2 in order to form the negative resistance loop. It is recommended that the parallel LC tank (L1/C1) is situated as close to the package as possible, with the L closest to the device pins. Also the shorting of VCOP1 to VCOP2 and of VCON1 to VCON2 occurs as close as possible to the tank circuit – this minimises the effects of series inductance on the oscillator behaviour. Enable Enable VCO Negative Resistance (NR) Amplifier VCON2 VCON1 VCOP2 VCOP1 VCO Output Buffer Amplifier L1 should have a Q>30 L1 C1 C2 C3 CV2 CV1 R1 R2 Input from Loop Filter Figure 10 Example External Components – VCO External Tank Circuit 2015 CML Microsystems Plc D/994_A_E/1 Page 15 of 70 Direct Conversion Receivers L1 C1 C2 C3 CMX994/CMX994A/CMX994E 8.2 nH (Note 1) 8.2 pF (Note 2) 22pF 22pF CV1 CV2 R1 R2 SMV1705-079LF SMV1705-079LF 10kΩ 10kΩ Table 11 Internal VCO Amplifier Tank Circuit for 440MHz Operation Note 1: Tolerance of 2% or better recommended Note 2: Tolerance of 5% or better recommended Output to Tank Cct DO R2 C1 R1 C3 C2 Figure 11 Example External Components – PLL Loop Filter C1 C2 C3 150nF 1000nF 15nF R1 R2 1.5kΩ 2.4kΩ Table 12 3rd Order Loop Filter Circuit Values 5.4 RESETN The RESETN pin generates a reset signal when low. The RESETN pin has an internal pull-up resistor of 100kΩ connected to VDDIO. 2015 CML Microsystems Plc D/994_A_E/1 Page 16 of 70 Direct Conversion Receivers 6 CMX994/CMX994A/CMX994E General Description The architecture of the CMX994/CMX994A/CMX994E devices is shown in Figure 1. The CMX994/CMX994A/CMX994E are receiver ICs featuring very high IIP2 I/Q demodulators intended for use as a direct conversion receiver to zero IF, near-zero IF and low IF. The device has flexible LO inputs, integer-N PLL and an on-chip negative resistance amplifier which, with the addition of suitable external components, provides a VCO. The receiver is fully integrated with a Low Noise Amplifier (LNA) preceding the down-converter section. The LNA may be configured with one of two possible output impedance settings (100 or 50). With the 50 mode selected, there is more gain available but the circuit will consume an additional 2mA of current. The 50 mode has primarily been included for use at frequencies of 450MHz or higher. It should be noted that as the output impedance is not the same for each setting, the required matching components between the LNA and mixer will be different for each case. The high-linearity down-converting mixers are immediately followed by a baseband filter stage. The bandwidth of this section is set by external capacitors. This first stage of filtering is designed to remove offchannel blocking signals prior to baseband amplification. Following these filters, gain is applied via a variable gain amplifier. Further filtering is then applied and again the bandwidth of the filters is determined by external capacitors. A reference resistor must also be fitted; this is used to calibrate the internal filter circuits to ensure the cut-off point of the filters is accurately controlled. This system allows effective correction for the analogue response to be applied in signal processing following the CMX994/CMX994A/CMX994E. The output of the CMX994/CMX994A/CMX994E is differential I/Q signals; these may be applied to analogue-todigital converters such as those in the CMX983, CMX910, CMX7163 or the CMX7164 ICs. The receiver I/Q chain includes the facility to correct for inherent dc offsets in the hardware. This process is intended to optimise the dynamic range of the system and must be controlled by the microprocessor or DSP that processes the I/Q signals from the CMX994/CMX994A/CMX994E. DC offsets are a well-known issue with direct conversion receivers. In dynamic signal environments dc offset removal algorithms will be required to track and remove dc offsets generated by off-channel signals. Very high I/Q mixer IIP2 performance minimises such offsets. The receiver sections have a low power mode that reduces current. This mode may be used when reduced intermodulation performance is acceptable. The Local Oscillator section features an integer-N Phase Locked Loop (PLL). This may be used with the on-chip VCO or with an external VCO. The on-chip VCO consists of a negative resistance amplifier and buffers, which allows an external inductor together with external varactor diodes to determine the operating frequency and tuning range. The use of external components allows optimum phase noise to be achieved. The Rx LO signal may be divided by 2, 4 or 6. There is also a Tx LO output provided and the Tx LO signal may be divided by 1, 2, 4 or 6. Alternatively the on-chip PLL and VCO can be disabled and an external LO source supplied. All features of the CMX994/CMX994A/CMX994E may be controlled by the C-BUS control interface. The following sections describe specific features of the CMX994/CMX994A/CMX994E. 2015 CML Microsystems Plc D/994_A_E/1 Page 17 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 6.1 General Operation 6.1.1 Rx/Tx Enable The CMX994/CMX994A/CMX994E has Tx Enable and Rx Enable pins and the same function can be accessed via C-BUS using the General Control Register (section 7.2). The logical signals ‘Tx ON’ and ‘Rx ON’ are the ORed combination of the C-BUS signal and the hardware signals as shown in Table 13. Thus either C-BUS or hardware enable signals may be used, with the unused mode being set to ‘0’. Tx (or Rx) Enable Pin 0 1 0 1 C-BUS Tx (or Rx) Enable 0 0 1 1 ‘Tx ON’ (or ‘Rx ON’) Result 0 1 1 1 Table 13 Tx (or Rx) Enable Operation ‘Tx ON’ enables the following sections of the device: Tx divider (see also Figure 1 and section 7.11.1. ‘Rx ON’ enables the following sections of the device: LNA Down-converters and I/Q baseband amplifiers Rx LO divider 6.2 Receiver Operation 6.2.1 DC Offset Correction Digitally-controlled dc offset correction is provided which is capable of reducing the offset to 25mV or less for errors of up to +/-200mV1 for CMX994 or up to +/-800mV for CMX994A/CMX994E. This represents a reduction in dynamic range of about 0.1dB for a typical ADC input signal range (2Vp-p) and is therefore negligible. The required correction must be measured externally as such measurements are application specific. The correction is applied close to the start of the I/Q baseband chain and therefore maximises dynamic range in the analogue sections. The correction is applied in a differential manner so positive and negative corrections are possible; see Figure 12. This allows the dc to be corrected to the nominal dc bias level. The voltage sources are scaled in a binary fashion so multiple sources can be added to provide the desired correction. The same arrangement applies independently on both I and Q channels. The CMX994 scheme, shown in Figure 12 / Table 14 is extended in the CMX994A/CMX994E with four additional sources to increase correction range. Positive Terminal Vdc3 + + Vdc5 + Vdc2 + Vdc6 + Vdc1 Differential Output Signal Vdc4 + Negative Terminal Figure 12 Simplified Schematic of How DC Offset Corrections are Applied 1 This can be doubled to 400mV using bit 2 of the Rx Control Register (see section 7.2.1) although this also halves the resolution available. 2015 CML Microsystems Plc D/994_A_E/1 Page 18 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Source Voltage Correction at Output for Maximum Gain in Baseband Amplifiers Vdc1 25mV Vdc2 50mV Vdc3 100mV Vdc4 25mV Vdc5 50mV Vdc6 100mV Correction Polarity Positive terminal increase, Negative terminal decrease Positive terminal increase, Negative terminal decrease Positive terminal increase, Negative terminal decrease Negative terminal increase, Positive terminal decrease Negative terminal increase, Positive terminal decrease Negative terminal increase, Positive terminal decrease Table 14 DC Offset Correction Adjustments 6.2.2 Receiver Filters and Bandwidth Options The I and Q channels incorporate two stages of filtering to reduce blocking signals and to attenuate nearby channels. This allows the wanted signal to be maximised without significant distortion being introduced as a result of unwanted larger signals saturating the later amplification stages. The CMX994/CMX994A/CMX994E supports multiple channel bandwidths, providing scalable filtering in the baseband (I/Q) chain. Two filter stages are provided. The post mixer filter provides rejection of large offchannel signals such as those typically used in blocking tests. With this protection in place some gain is provided before narrower filters that provide rejection of the adjacent channel. Following this filter, the remainder of the receiver gain is provided. Both filter stages have single-pole characteristics, having -3dB frequency points set by separate external capacitors. I Channel LO Input Q Channel Post Mixer Filters Adjacent Channel Rejection Filters Figure 13 Baseband I/Q Filtering After setting the second filter stage bandwidth via external capacitors, the bandwidth can then be scaled under serial control to allow multiple channel bandwidths to be supported by the CMX994/CMX994A/CMX994E. A typical requirement is to support 6.25kHz, 12.5kHz and 25kHz channels, so the scaling of the Adjacent Channel Rejection (ACR) filter is 1 : 2 : 4 via a bandwidth mode control. Using the recommended external capacitors for a 6.25kHz design (see 5.2.2), the ACR filter bandwidth (-3dB) is 2kHz. This provides 9dB rejection of the adjacent channel and 15dB rejection at 12.5kHz. Using the bandwidth scaling control, the 2kHz filter bandwidth can then be changed to 4kHz or 8kHz (see Rx Control Register, section 7.3), without changing external components. See also section 8.1.6. 2015 CML Microsystems Plc D/994_A_E/1 Page 19 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E The ACR filter may introduce some deterministic distortion in the signal passband, this distortion can be compensated by using filters external to the CMX994/CMX994A/CMX994E; see section 6.2.3 for further information. The scaling of the post-mixer filter is less critical. The bandwidth (-3dB), using the recommended values, is approximately 88kHz (at maximum gain). This should be suitable for all the channel bandwidths up to 25kHz, so no scaling is provided. Note that the bandwidth of this section will reduce by 30% (typ.) as gain is reduced in the baseband section. 6.2.3 Baseband Filter Design and Required Correction The pole frequencies of the filter stages are set by the addition of external capacitors (see also section 5.2.2); the resistors are internal to the chip and those on the second filter stage are trimmed so as to match the external 10kΩ reference resistor2. 600 CMX994 600 10k External Capacitor CMX994 10k First stage filter. Resistors have 20% tolerance External Capacitor Second stage filter. Resistors are matched to external 10k, 1% resistor Figure 14 Schematic Representation of Filters used in the I and Q Paths Filtering close to the passband distorts the signal and increases the BER, so it is necessary to provide correction for the filter distortion in subsequent external digital filtering. Both filter stages are single-pole filters. The first filter stage is designed to reduce blocking signals and it will typically be set at 4 x the maximum required channel spacing. As a result, tolerance is not particularly critical and it is usually not necessary to compensate the wanted signal for this filter. The second filter is designed to operate close to, or within, the passband. It is therefore important that compensation is provided for the wanted signal. Different modulation schemes occupy different bandwidths within a channel, so optimisation of the filter positioning will vary depending on the modulation scheme. Some experimentation may be required to get the best results but, as a guide, the second filter stage should have its frequency set to between 30% and 40% of the channel spacing. The aim is to reduce adjacent and close-in channels as much as possible. Provided the filter effects are compensated for later, the lowering of the signal amplitude at the band edges is usually well tolerated, although the extent of this will depend on the modulation scheme used. The CMX994/CMX994A/CMX994E allows up to three different channel spacings to be selected via the C-BUS interface. So if, for example, the three channel spacings required are 6.25kHz, 12.5kHz and 25kHz, then the first filter should be set at a nominal desired frequency to ensure large blocking signals are rejected, typically a cut off frequency around 100kHz would be suitable. If only two channel spacings are required, of 6.25kHz and 12.5kHz for example, then it would be slightly beneficial to set the post mixer filter bandwidth to 50kHz. Note that the three channel spacings are always in a 1:2:4 ratio relative to the smallest channel spacing, which is set by external components. 2 The external resistor should be 1% tolerance or better. 2015 CML Microsystems Plc D/994_A_E/1 Page 20 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E The second stage filter capacitor should be selected for the smallest bandwidth requirement. The calculation for the capacitor value is as follows: C 1 2 f 20,000 Where f filter pole frequency (-3dB point). So a capacitor of 4nF would yield a frequency pole of 1989Hz. This may be a typical figure when using a channel spacing of 6.25kHz. To maintain the accuracy of the compensation the capacitor must have a low temperature coefficient and tolerance better than or equal to 2%. A compensation filter would need to be applied in the digital domain having the inverse characteristic. This would be: H (s) 1 s 2 f This would normally be implemented as a FIR filter. It should be followed with another non-critical FIR that rolls off the signal when out of band. This second filter may be part of a required channel filter. Selecting 2x or 4x bandwidth will require the compensation filter to be adjusted in proportion. The first stage filter capacitor may be calculated in a similar way: C Where f 1 2 f 1200 filter pole frequency (-3dB point). So a capacitor of 1.5nF would yield a frequency pole of 88.4kHz. This may be a typical figure if the maximum channel spacing required were 25kHz. There is a wider tolerance on this, as the internal resistors are not trimmed. Consequently it is not required to have a low tolerance value on the first stage filter capacitor. Should it be required to have this closer to the passband then a correction filter may be required. This would have the same form as for the correction filter for the second stage. In general a margin of at least 50% between the filter cut-off and wanted channel is recommended to allow for the resistor tolerances and bandwidth change with gain settings noted in section 6.2.2. Because both filter stages are handling large dynamic signals, the linearity of the external capacitors is important. Use of good dielectric materials is recommended; poor linearity could result in a degradation of the on-channel signal in the presence of large off-channel interferers. 6.2.4 Operation at Wider Bandwidths It is possible to use a much wider channel bandwidth than those used as examples elsewhere in this document. For maximum I/Q bandwidth (1.6MHz) capacitors C1, C2, C3 and C4 in Figure 9 should be removed. In this case the filter calibration circuit should be disabled using b7 of the VCO Control Register ($25); see section 7.11.1. For systems that require greater bandwidths the output should be taken before the baseband amplifiers and filters; see section 8.1.9. 6.3 Local Oscillator Operation The CMX994/CMX994A/CMX994E can use either an external Local Oscillator (LO) source or the on-chip VCO and PLL. The on-chip integer-N PLL can also be used with an external VCO connected to the LO input. 2015 CML Microsystems Plc D/994_A_E/1 Page 21 of 70 Direct Conversion Receivers 6.3.1 CMX994/CMX994A/CMX994E PLL The CMX994/CMX994A/CMX994E provides an integer-N PLL that can be used to create the local oscillator; see Figure 15. The CMX994/CMX994A/CMX994E provides a VCO negative resistance amplifier, so only a tank circuit needs to be implemented externally. Alternatively, this amplifier can be bypassed and an external VCO can be used. CMX994 LO Output to CMX994 Circuits VCO Output Buffer VCO NR Amplifier NR Control R Divider (Reference) 2 - 32767 M Divider (Feedback) 2 - 262143 Phase Detector VCOP1 VCOP2 VCON1 VCON2 LON LOP FREF Lock Detect DO Optional External VCO VCO Tank & Varactors Figure 15 Local Oscillator The integer-N PLL has programmable M and R dividers as shown in Figure 15. The phase detector provides a charge pump output which requires a suitable loop filter to convert this signal into a control voltage for a VCO. The phase detector can be turned off (high impedance mode) and the PLL section disabled if an external LO is to be used; see section 6.3.2 and 7.9 for control details. The output frequency of the PLL is set by the following calculation: fout = fref x ( M / R ) where: fout = The desired output frequency in MHz fref = The reference frequency supplied to the PLL on pin FREF in MHz M = Divider value programmed in the M divider register (see section 7.9.1) R = Divider value programmed in the R divider register (see section 7.10.1) The PLL only supports VCOs with a positive tuning slope, i.e. a higher tuning voltage from DO results in a higher oscillation frequency from the VCO. The PLL has a lock-detect function that can be evaluated using register $D2, b6 (section 7.9.2). The VCO amplifier is a negative resistance amplifier requiring an external tank circuit (see section ). The amplifier has two control bits available in the VCO control register (section 7.11.1 register $25, b2 – b3). These bits can be used to optimise performance for a particular tank circuit depending on its Q value. When using the CMX994/CMX994A/CMX994E PLL, spurious products (spurs) in the receiver I/Q output may be observed. The frequency of the spurs is linked to the PLL M divider value and which of the divide-by-2, 4 or 6 modes is selected for the receiver LO circuits. Operation in divide-by-2 and divide-by-6 modes is most predictable: all even division ratios are problem free and all odd division ratios will give a spurious product at: fspur = flo / ( M * 2 ) 2015 CML Microsystems Plc D/994_A_E/1 Page 22 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E In divide-by-4 mode most odd divisions will produce a spur although at low frequencies (circa 100MHz) operation is spur-free. At circa 300 MHz and above some even divisions are also problematic (in divide-by-4 mode). It is recommended that for safe operation of the CMX994/CMX994A/CMX994E PLL, receiver LO divide-by-2 or divide-by-6 modes, with even division ratios, should be used. When using the CMX994/CMX994A/CMX994E PLL, spurious can also be observed in the output from the TXLO pin. In this case the spurs are at small offsets from the wanted signal – the offset is linked to the PLL comparison frequency. The level of these spurs is typically at a very low (< -80 dBc) and less problematic than in the receiver. 6.3.2 PLL Enable The PLL block can be enabled from the General Control Register $11, b2 (section 7.2.1) and the PLL M Divider Register $22, b7 (section 7.9.1). An AND function is performed on these two bits (see table below). General Control Register $11, b2 0 0 1 1 PLL M Divider Register $22, b7 0 1 0 1 PLL Enable No No No Yes With the PLL disabled an external local oscillator may be supplied to the CMX994/CMX994A/CMX994E. 2015 CML Microsystems Plc D/994_A_E/1 Page 23 of 70 Direct Conversion Receivers 7 CMX994/CMX994A/CMX994E C-BUS Interface and Register Descriptions The C-BUS serial interface supports the transfer of data and control or status information between the CMX994/CMX994A/CMX994E’s internal registers and an external host. Each C-BUS transaction consists of the host sending a single Register Address byte, which may then be followed by zero or more data bytes that are written into the corresponding CMX994/CMX994A/CMX994E register, as illustrated in Figure 16. Data sent from the host on the Command Data (CDATA) line is clocked into the CMX994/CMX994A/CMX994E on the rising edge of the Serial Clock (SCLK) input. The C-BUS interface is compatible with common µC/DSP serial interfaces and may also be easily implemented with general purpose I/O pins controlled by a simple software routine. Section gives the detailed C-BUS timing requirements. Whether a C-BUS register is of the read or write type, it is fixed for a given C-BUS register address thus one cannot both read and write the same C-BUS register address. The CMX994/CMX994A/CMX994E supports several pairs of C-BUS register addresses in order to read and write the same information. In order to provide ease of addressing when using this device with the CMX998 (Cartesian Feed-back Loop Transmitter IC), the C-BUS addresses below are arranged so as not to overlap those used on the CMX998. Thus, a common chip select (CSN) signal can be used, as well as common CDATA (SDI on CMX998), RDATA (SDO on CMX998) and SCLK signals. Also note that the General Reset ($10) command on the CMX994/CMX994A/CMX994E differs from other CML devices (such as CMX998), which use $01 for this General Reset function. This allows the CMX994/CMX994A/CMX994E and CMX998 to be connected to the same interface pins, including chip select, assuming the drive capabilities of the host are adequate. C-BUS Write-only Registers HEX REGISTER ADDRESS $10 General Reset Register (Address only, no data) $11 General Control Register, write only $12 Rx Control Register, write only $13 Rx Offset Register, write only $14 LNA IM Control Register, write only $15 Options Control Register, write only $16 Rx Gain Register, write only $17 Extended Rx Offset Register, write only $20-$22 PLL M Divider Register, write only $23-$24 PLL R Divider Register, write only $25 VCO Control Register, write only WORD SIZE (BITS) 0 8 8 8 8 8 8 16 8 8 8 C-BUS Read-only Registers HEX REGISTER ADDRESS $E1 General Control Register, read only $E2 Rx Control Register, read only $E3 Rx Offset Register, read only $E4 LNA IM Control Register, read only $E5 Options Control Register, read only $E6 Rx Gain Register, read only $E7 Extended Rx Offset Register, read only $D0-$D2 PLL M Divider Register, read only $D3-$D4 PLL R Divider Register, read only $D5 VCO Control Register, read only WORD SIZE (BITS) 8 8 8 8 8 8 16 8 8 8 CMX994A and CMX994E. Specific bits control CMX994E features only. See register descriptions for details. CMX994A and CMX994E only 2015 CML Microsystems Plc D/994_A_E/1 Page 24 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Notes: All registers will retain data if DVDD and VDDIO pins are held high, even if all other power supply pins are disconnected. If clock and data lines are shared with other devices, DVDD and VDDIO must be maintained in their normal operating ranges otherwise ESD protection diodes may cause a problem with loading the signals connected to SCLK, CDATA and RDATA pins, preventing correct programming of other devices. Other supplies may be turned off and all circuits on the device may be powered down without causing this problem. Single byte from µC (General Reset command) CSN Note: The SERIAL CLOCK line may be high or low at the start and end of each transaction. SERIAL CLOCK (SCLK) COMMAND DATA (CDATA) REPLY DATA (RDATA) Hi-Z 7 6 5 4 3 2 1 0 Address (10 Hex = Reset) = Level not important One Address and one Data byte from µC to CMX994 CSN SERIAL CLOCK (SCLK) COMMAND DATA (CDATA) REPLY DATA (RDATA) 7 6 5 4 3 2 1 0 Address 7 6 5 4 3 2 1 0 Data to CMX994 Hi-Z One Address byte from µC and one Reply byte from CMX994 CSN SERIAL CLOCK (SCLK) 7 6 5 4 3 2 1 0 Address COMMAND DATA (CDATA) REPLY DATA (RDATA) 7 6 5 4 3 2 1 0 Data from CMX994 Hi-Z Figure 16 C-BUS Transactions 7.1 General Reset: $10 (no data) A command to this register resets the device and clears all bits of all registers. The General Reset command places the device into powersave mode. Whenever power is applied to the DVDD pin, a built-in power-on-reset circuit ensures that the device powers up into the same state as follows a General Reset command. The RESETN pin on the device will also reset the device to the same state. 2015 CML Microsystems Plc D/994_A_E/1 Page 25 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.2 General Control Register 7.2.1 General Control: $11 - 8-bit write only This register controls general features such as powersave. All bits of this register are cleared to ‘0’ by a General Reset command. 7 En Bias 6 Freq2 5 Freq1 4 LP 3 VCOEN 2 PLLEN 1 RXEN 0 TXEN b7 and 4-0: These bits control power up/power down of the various blocks of the IC. In all cases ‘1’ = power up, ‘0’ = power down. b7 b4 b3 b2 b1 b0 Enables BIAS generator Enables low power mode. When b4 = ‘0’ the device is operating normally, when b4= ‘1’ the device will have reduced power consumption and reduced intermodulation performance. See also section 8.1.5 regarding other CMX994A/CMX994E low power modes. Enables VCO: When b3 =’1’ the setting of the VCO Control Register ($25) takes effect. For details of VCO Control Register see section 7.11. PLL Enable: This bit enables the PLL and is ANDed with PLL M-Divider Register ($21) b7 – section 7.9.1 See also section 6.3.2. C-BUS Rx Enable; see section 6.1.1 C-BUS Tx Enable; see section 6.1.1 b6, b5 These bits optimise the amplitude of the local oscillator path within the device in order to maintain phase balance and noise performance of the receiver mixers over the full range of operating frequencies. 7.2.2 b6 0 0 1 b5 0 1 0 1 1 Operation 100MHz – 150MHz 150MHz – 300MHz 300MHz – 700MHz 700MHz – 1000MHz (700MHz - 940MHz for CMX994) General Control: $E1 - 8-bit read only This register reads the value in register $11; see section 7.2.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 26 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.3 Rx Control Register 7.3.1 Rx Control: $12 – 8-bit write only This register controls general features of the receiver such as Powersave. All bits of this register are cleared to ‘0 by a General Reset command. 7 Mix Pwr b7-5 6 IQ Pwr 5 LNA Pwr 4 ACR Flt2 3 ACR Flt1 2 DC Range 1 DIV2 0 DIV1 These bits control power up/power down of the various blocks of the IC. In all cases ‘0’ = power up, ‘1’ = power down. b7 b6 b5 Disable receiver mixers and divider (see note) Disable baseband amplifier and filters (see note) Disable LNA (see note) Note: These control signals disable the appropriate blocks of the receiver when ‘Rx ON’ is active. If ‘Rx ON’ is not active all receiver circuits will be in powersave mode. b4,3 The baseband I/Q chain provides a narrow filter for rejecting adjacent channel signals. The bandwidth of this filter may be scaled using these bits. For further details see sections 6.2.2, 6.2.3 and 8.1.6. b4 0 0 1 1 b2 b1,0 Function Minimum bandwidth Intermediate bandwidth Maximum bandwidth reserved, do not use When b2 = ’0’ the range of DC correction of the I/Q output is nominal (see sections 6.2.1 and 7.4). With b2 = ‘1’ the total correction range is twice the nominal specified in section 7.4 with all steps doubled in value. Note: CMX994A/CMX994E provide an alternative method of achieving increased correction range without losing resolution using the Extended Rx Offset Register ($17); see section 7.8. Receiver LO divider control b1 0 0 1 1 7.3.2 b3 0 1 0 1 b0 0 1 0 1 Function LO divided by 2 LO divided by 4 LO divided by 6 reserved, do not use Rx Control: $E2 – 8-bit read only This read-only register mirrors the value in register $12; see section 7.3.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 27 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.4 Rx Offset Register 7.4.1 Rx Offset: $13 – 8-bit write only Note: Increased correction range is available in the CMX994A/CMX994E using register $17; see section 7.8. The bits in registers $13 and $17 control the same hardware functions with the most recent write to $17 or $13 being applicable at any given time; if $13 is written then QDC5, QDC4, IDC5 and IDC4 in $17 are automatically set to ‘0’. All bits of registers $13 and $17 are cleared to ‘0’ by a General Reset command. 7 QDC3 b7-0 6 QDC2 5 QDC1 4 QDC0 3 IDC3 2 IDC2 1 IDC1 0 IDC0 I/Q DC offset correction; see section 6.2.1 for further details. The step size can be doubled using the Rx Control Register ($12), b2; see section 7.3.1. The values in the table below are the effects of the offset at the maximum VGA gain (minimum attenuation) setting. They are proportionately lower for lower gain settings (as set by the Rx Gain Register (b2 – b0). The aim of this Rx Offset Register is to allow output offsets to be reduced sufficiently (typically <25mV) to avoid any significant reduction in the dynamic range of any subsequent ADC. It is expected that demodulation software in the baseband processor would be required to correct for the remaining offset as part of the demodulation process. See also section 8.1.2. b3 b7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 7.4.2 b2 b6 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 b1 b5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 b0 b4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 I Channel at maximum gain Q Channel at maximum gain -175mV -150mV -125mV -100mV -75mV -50mV -25mV No correction +175mV +150mV +125mV +100mV +75mV +50mV +25mV No correction Rx Offset: $E3 - 8-bit Read only This read-only register mirrors the value in register $13; see section 7.4.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 28 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.5 LNA Intermodulation Control Register 7.5.1 LNA IM Control: $14 – 8-bit write only This register controls features of the receiver that support intermodulation optimisation. All bits of this register are cleared to ‘0’ by a General Reset command. 7 0 b7,6 b5-0 7.5.2 6 0 5 IM5 4 IM4 3 IM3 2 IM2 1 IM1 0 IM0 reserved, clear to ‘0’ These bits allow the user to adjust the intermodulation performance of the LNA. The default value is ‘0’ for all the bits. Improved intermodulation can be achieved with a particular value in these bits. For further details see section 8.1.4. LNA IM Control: $E4 – 8-bit read only This read-only register mirrors the value in register $14; see section 7.5.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 29 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.6 Options Control Register – CMX994A and CMX994E only 7.6.1 Options Control: $15 – 8-bit write only This register controls options features added in the CMX994A and CMX994E devices only. All bits of this register are cleared to ‘0’ by a General Reset command. 7 IP3X b7 b6 b5 b4 b3 b2 b1-0 6 Reserved 5 Reserved 3 PDQ 2 PDI 1 PHCON 0 PHOFF CMX994E only - ‘1’ enables enhanced mixer intermodulation mode in the receive path mixers; normal operation when set to ‘0’. CMX994A – reserved, clear to ‘0’ reserved, clear to ‘0’ reserved, clear to ‘0’ reserved, clear to ‘0’ When set ‘1’ this bit will power down all circuitry in the Q path leaving only the I channel active; normal operation (I and Q paths active) when bit is cleared to ‘0’. When set ‘1’ this bit will power down all circuitry in the I path leaving only the Q channel active; normal operation (I and Q paths active) when bit is cleared to ‘0’. LO Phase Correction Control b1 0 1 0 1 7.6.2 4 Reserved b0 0 1 1 0 LO Phase Correction Enabled Powered down reserved, do not use reserved, do not use Options Control: $E5 – 8-bit read only This register reads the value in register $15; see section 7.6.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 30 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.7 Rx Gain Register 7.7.1 Rx Gain: $16 – 8-bit write only This register controls receiver gain control. All bits of this register are cleared to ‘0’ by a General Reset command. 7 GS1 b7,6 6 GS0 5 LNA Gain2 b6 0 1 0 1 2 G2 1 G1 0 G0 Function Nominal step size of 6dB Nominal step size + 0.7dB Nominal step size+1.4dB Nominal step size +2.8dB LNA Gain Control: These bits control the LNA gain in nominal 6dB steps, as shown in table below; see also b7 - b6. b5 0 0 1 1 b4 0 1 0 1 Function LNA gain = Nominal LNA gain = Nominal -6dB LNA gain = Nominal -12dB LNA gain = Nominal -18dB b3 Sets the LNA output impedance. The LNA output impedance is approximately 100 if this bit is set to ‘0’ and approximately 50 if this bit is set to ‘1’. If set to 50 the gain will be increased but with an additional LNA current consumption of approximately 2mA. b2-0 I/Q Baseband VGA Control b2 1 1 1 1 0 0 0 0 7.7.2 3 LNA Z0 LNA Gain Control Step: These bits control the LNA gain steps; the nominal step is 6dB however the actual step size can be adjusted by+0.7dB, +1.4dB or +2.8dB, as shown in the table below. For further information see section 8.1.3. b7 0 0 1 1 b5,4 4 LNA Gain1 b1 1 1 0 0 1 1 0 0 b0 1 0 1 0 1 0 1 0 VGA Level VGA = -42dB VGA = -36dB VGA = -30dB VGA = -24dB VGA = -18dB VGA = -12dB VGA = -6dB VGA = 0dB (Maximum gain) Rx Gain: $E6 – 8-bit read only This read only register mirrors the value in register $16; see section 7.7.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 31 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.8 Extended Rx Offset Register – CMX994A and CMX994E only 7.8.1 Extended Rx Offset: $17 – 16-bit write only All bits of this register are cleared to ‘0’ by a General Reset command. Note 1: the bits in registers $13 and $17 control the same hardware functions with the most recent write to $17 or $13 being applicable at any given time; if $13 is written then QDC5, QDC4, IDC5 and IDC4 will automatically be set to ‘0’. Note 2: QDC3 and IDC3 have different function in $13 and $17; in $13 QDC3 and IDC3 sets the correction polarity whereas in $17 the polarity is set by QDC5 and IDC5. 15 0 7 0 b13-8, b5-0 14 0 6 0 13 QDC5 5 IDC5 12 QDC4 4 IDC4 11 QDC3 3 IDC3 10 QDC2 2 IDC2 9 QDC1 1 IDC1 8 QDC0 0 IDC0 I/Q DC Offset correction; see section 6.2.1 The values in the table below are the effects of the offset at the maximum VGA gain (minimum attenuation) setting. They are proportionately lower for lower gain settings (as set by the Rx Gain Register (b2 – b0). The aim of this Rx Offset Register is to allow output offsets to be reduced sufficiently (typically <25mV) to avoid any significant reduction in the dynamic range of any subsequent ADC. It is expected that demodulation software in the baseband processor would be required to correct for the remaining offset as part of the demodulation process. See also section 8.1.2 7.8.2 b5 b13 1 1 b4 b12 1 1 b3 b11 1 1 b2 b10 1 1 b1 b9 1 1 b0 b8 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 I Channel at maximum gain Q Channel at maximum gain -775mV -750mV etc. (i.e. binary count, step 25mV) -125mV -100mV -75mV -50mV -25mV No correction +775mV +750mV etc. (i.e. binary count, step 25mV) +175mV +150mV +125mV +100mV +75mV +50mV +25mV No correction Extended Rx Offset: $E7 – 16-bit read only This read-only register mirrors the value in register $17; see section 7.8.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 32 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.9 PLL M Divider Register 7.9.1 PLL M Divider: $22 - $20 – 8-bit write only These registers set the M divider value for the PLL (Feedback Divider). The divider is updated synchronously when register $22 is written so registers $20 and $21 should be written before $22. Note: the order of writing $20 and $21 is not important. Bits 7 and 5 also control the PLL and charge-pump blocks and these control bits are active immediately on any occasion that $22 is written. (Note: To enable the PLL, b2 of the General Control Register ($11) must also be used; see section 7.2 See also section 6.3.2. $22 7 E 6 LD_PLL 5 CP 4 0 3 0 2 0 1 M17 0 M16 7 M15 6 M14 5 M13 $21 4 3 M12 M11 2 M10 1 M9 0 M8 $20 7 M7 6 M6 5 M5 4 M4 3 M3 2 M2 1 M1 0 M0 M17M0 Phase Locked Loop M divider value CP $22, b5 = ’1’ enables the charge pump, $22 b5 = ’0’ puts the charge pump into high impedance mode LD_PLL Only write ‘0’ to b6 of $22 (when read via $D2, this shows the integer N PLL lock status) E 7.9.2 $22, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL –This bit enables the PLL and is ANDed with General Control Register ($11) b2 – section 7.2 See also section 6.3.2 PLL M Divider: $D2-$D0 - 8-bit read only These registers read the respective values in registers $20, $21 and $22 ($D0 reads back $20 and $D1 reads back $21 etc.); see section 7.9.1 for details of bit functions. Note: $D2 b6 indicates the Synth lock detect status. 2015 CML Microsystems Plc D/994_A_E/1 Page 33 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.10 PLL R Divider Register 7.10.1 PLL R Divider: $24 - $23 – 8-bit write only These registers set the R divider value for the PLL (Reference Divider). The PLL dividers are updated synchronously when $24 is written. Note: $23 should be written first then $24. $24 $23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R14-R0 Phase Locked Loop R divider value. $24 b7 7.10.2 reserved, set to ‘0’. PLL R Divider: $D4-$D3 – 8-bit read only These registers read the respective values in registers $23 and $24 ($D3 reads back $23 and $D4 reads back $24); see section 7.10.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 34 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 7.11 VCO Control Register 7.11.1 VCO Control: $25 - 8-bit write only This register controls the operation of the VCO and LO input. Operation is only enabled when b3 = ‘1’ in the General Control Register ($11), as detailed in section 7.2 All bits of this register are cleared to ‘0’ by a General Reset command. Note: it is not recommended that the LO input and the VCO are enabled simultaneously. 7 6 5 FILT_ CAL TXDIV1 TXDIV0 3 2 VCO_NR2 VCO_ NR1 1 VCO_ NR En 0 VCO_ Buf En b7 This bit, if set to ‘1’, will disable the Filter Calibration System. The default value is ‘0’. b6,5 These bits control the output division of the Tx LO signal available at pin TXLO. The LO signal is divided by the factor as shown in the following table. b6 0 0 1 1 b4,b1, b0 b0 b3,b2 b5 0 1 0 1 Function Divide by 2 Divide by 4 Divide by 6 No division These bits control power up/power down of the various blocks of the device In all cases, ‘1’ = power up, ‘0’ = power down b4 b1 Enable LO input Enable VCO NR Amplifier. When disabled the amplifier is bypassed to support the application of an external LO signal. Enable VCO Buffer VCO amplifier Negative Resistance (NR) control bits optimise phase noise performance. These bits control the Negative Resistance (magnitude of the negative transconductance) of the on-chip VCO NR amplifier. The NR minimum mode would thus be used with the lowest Q external tank circuit and NR maximum with the highest Q value. B3 0 0 1 1 7.11.2 4 LO Input EN B2 0 1 0 1 Function NR maximum NR intermediate value NR intermediate value NR minimum VCO Control: $D5 - 8-bit read only This register reads the value in register $25; see section 7.11.1 for details of bit functions. 2015 CML Microsystems Plc D/994_A_E/1 Page 35 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 8 Application Notes 8.1 Typical Receiver Performance 8.1.1 System Performance This information is intended as a general guide of what can be expected from a CMX994/CMX994A/CMX994E receiver design using the on-chip LNA and I/Q down-conversion stages. The measurement circuit uses the component values given in section 5.2 The results are based on measurements from evaluation of the CMX994/CMX994A/CMX994E operating at 450MHz (CMX994E in normal mode, not enhanced mode). Results are also given for Low Power (LP) mode operation, i.e. General Control Register ($11) b4 = ‘1’; see section 7.2.1. Gain Noise Figure: Input Third Order Intercept Point: Input Second Order Intercept Point: 63dB 4.5dB -3dBm 62dBm (62.5dB in LP mode) (also 4.5 dB in LP mode) (-9dBm in LP mode) (60dBm in LP mode) Notes: Common settings: max gain, max filter bandwidth, freq control bits = 300 to 700MHz, LNA output impedance = 100, LO at x2 (900MHz, level -10dBm), IM Control Register = 0x3F Gain is measured from RF input (assumed to be 50 Ohm source /load) to differential voltage measured at output of I or Q channels. Second Order Intercept Point is the average of values measured from differential signals on I and Q; measured at 1MHz offset. Using the CMX994/CMX994A/CMX994E operating at 448MHz combined with the CMX7164FI-2 modem IC gives the following typical system performance using 19.2kbps 4-FSK modulation, alpha =0.2, deviation =3kHz (based on a 25kHz RF channel). Sensitivity for 1% BER Blocking Adjacent channel rejection Intermodulation -116dBm (see Figure 17) >90dB 73dB 65dB (Measurement methods based on EN 300 113-1). 1.E-01 1.E-02 BER 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 -117 -116 -115 -114 -113 -112 -111 -110 -109 RF Input Level (dBm) Figure 17 CMX994 and CMX7164 with FI-2 – Typical 4-FSK Sensitivity (19.2kbps) 2015 CML Microsystems Plc D/994_A_E/1 Page 36 of 70 Direct Conversion Receivers 8.1.2 CMX994/CMX994A/CMX994E DC Offsets To provide an approximate correction of dc offsets use the following procedure: with the attenuation set at minimum (i.e. max gain) measure the offset at the CMX994/CMX994A/CMX994E I or Q output, then the table in section 7.4.1 can be used to give the required offset correction. The range double bit ($12, b2) can be used to increase the correction range if required. Note that at high attenuation settings there may be an additional error due to residual offsets from within the VGA as explained below. The dc offsets in the CMX994 baseband path are shown in Figure 18. The voltages are only shown on the Q path but the same considerations apply to the I path. Note that the dc offsets in I and Q paths will be different because they relate to random offsets in a number of components; note also that the I and Q paths are differential and that further details of the dc offset correction mechanism are given in section 6.2.1. I Channel + + - Vmo Voffset + + - V01 Vcorr V02 Amplifier #1 Gain = +15 to -27dB In 6dB steps Q Channel Amplifier #2 Gain = +22dB Where: Vmo = dc offset at the output of the mixer VO1 , VO2 = input offsets of amplifiers 1 and 2 respectively Vcorr = correction voltage (value set in Rx Offset register, $13) Voffset = dc offset present at the output Figure 18 I/Q Path dc Offsets Referring to Figure 18, the approximate dc offset for a given gain setting can be calculated as: Voffset = ( (Vmo + Vcorr + V01).G1 .G2 ) + ( VO2 . G2 ) The offset VO2 can be estimated by setting the attenuation in Amplifier #1 to -42dB (G1 = -27dB) and then measuring Voffset , thus VO2 = (Voffset / G2 ). The sum of (Vmo + V01) can then be estimated given that the gain setting of G1 and Vcorr are known. Assuming Voffset is minimised using Vcorr at minimum attenuation then increasing the attenuation may result in an increase in Voffset, however the error is typically ±15 mV (±55 mV absolute maximum). An example of the variation in dc offsets with gain control is shown in Figure 19. It should be noted that as the attenuation is increased the steps of the offset correction mechanism reduce as the reciprocal of the attenuation. The result is that at maximum attenuation the offset correction steps are (-42/20) 25mV x 10 = 0.2mV. 2015 CML Microsystems Plc D/994_A_E/1 Page 37 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Attenuation/ dB 0 -6 -12 -18 -24 -30 -36 -42 0 dc Offset / mV -5 -10 I -15 Q -20 -25 -30 Figure 19 Example Variation in Voffset with Gain Control Setting 8.1.3 Gain Control The CMX994/CMX994A/CMX994E has gain control mechanisms in the LNA and the baseband (see Figure 20) with a total control range of 60dB. The gain can be controlled using the Rx Gain Control Register, $16; see section 7.7.1. The LNA gain control steps can be adjusted to achieve the required accuracy using the step size control bits in the Rx Gain Control Register. The effect of the step size control varies with frequency, as shown in Table 15, Table 16 and Table 17 so for optimum accuracy the best settings should be selected to suit the particular application. (Suggested settings for optimum gain accuracy are shaded grey in the tables.) I Channel LO Input Q Channel 18dB Gain Contol, 6dB Steps 42dB Gain Contol, 6dB Steps Figure 20 Gain Control 2015 CML Microsystems Plc D/994_A_E/1 Page 38 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Gain Setting Gain Cntrl Step Size (dB) Cumulative Variation Gain from Change Nominal (dB) (dB) Nominal step size Max -6 dB -12 dB -18 dB -6.9 -5.4 -4.2 0.0 -6.9 -12.3 -16.5 -0.9 -0.3 1.5 Nominal +0.7 dB Max -6 dB -12 dB -18 dB -7.0 -6.7 -4.1 0.0 -7.0 -13.7 -17.8 -1.0 -1.7 0.2 Nominal +1.4 dB Max -6 dB -12 dB -18 dB -7.0 -7.9 -4.1 0.0 -7.0 -14.9 -18.9 -1.0 -2.9 -0.9 Nominal +2.8 dB Max -6 dB -12 dB -18 dB -7.0 -9.2 -4.0 0.0 -7.0 -16.2 -20.2 -1.0 -4.2 -2.2 Table 15 Typical LNA Gain Step Sizes at 100MHz, ZO=100Ω 2015 CML Microsystems Plc D/994_A_E/1 Page 39 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Gain Setting Nominal step size Max -6 dB -12 dB -18 dB Nominal +0.7 dB Max -6 dB -12 dB -18 dB Nominal +1.4 dB Max -6 dB -12 dB -18 dB Nominal +2.8 dB Max -6 dB -12 dB -18 dB Gain Cntrl Step Size (dB) Cumulative Variation Gain from Change Nominal (dB) (dB) -6.2 -4.5 -3.7 0.0 -6.2 -10.7 -14.5 -0.2 1.3 3.6 -6.2 -5.5 -3.9 0.0 -6.2 -11.8 -15.6 -0.2 0.3 2.4 -6.3 -6.6 -4.0 0.0 -6.3 -12.9 -16.9 -0.3 -0.9 1.1 -6.3 -7.6 -4.4 0.0 -6.3 -13.9 -18.3 -0.3 -1.9 -0.3 Table 16 Typical LNA Gain Step Sizes at 450MHz, ZO=100Ω 2015 CML Microsystems Plc D/994_A_E/1 Page 40 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Gain Setting Nominal step size Max -6 dB -12 dB -18 dB Nominal +0.7 dB Max -6 dB -12 dB -18 dB Nominal +1.4 dB Max -6 dB -12 dB -18 dB Nominal +2.8 dB Max -6 dB -12 dB -18 dB Variation Cumulative Gain Cntrl Step from Gain Change Size (dB) Nominal (dB) (dB) -6.4 -5.6 -5.2 0.0 -6.4 -12.0 -17.2 -0.4 0.0 0.8 0.0 -6.4 -7.1 -5.6 0.0 -6.4 -13.5 -19.1 -0.4 -1.5 -1.1 -6.4 -8.6 -5.7 0.0 -6.4 -15.1 -20.7 -0.4 -3.1 -2.7 -6.5 -10.3 -5.5 0.0 -6.5 -16.8 -22.3 -0.5 -4.8 -4.3 Table 17 Typical LNA Gain Step Sizes at 940MHz, ZO=50Ω 8.1.4 LNA Intermodulation Optimisation The intermodulation (IMD) performance of the LNA can be optimised using the IM bits in the IM Control register ($14); see section 7.5.1. At higher frequencies, typically 400MHz and above, optimum IMD performance is with the IM bits set to maximum, i.e. 0x3F. The improved IMD performance comes with a reduction in gain of approximately 0.5dB; see Figure 21. At minimum frequency (circa 100MHz) the IM bits should be set to minimum i.e. 0x00. 2015 CML Microsystems Plc D/994_A_E/1 Page 41 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 14 Gain Gain(dB) & IIP3 (dBm) 12 10 8 6 IIP3 4 2 0 0 10 20 30 40 50 60 IM Reg setting / dec Figure 21 Variation of LNA Gain and IMD with IM Register Setting, 450 MHz 8.1.5 Low Power Mode If the low power mode is enabled, General Control Register ($11) b4 = 1, the total current drawn in the receiver section reduces by approximately 10mA. For indications of the performance changes in low power mode; see section 8.1.1. The IP2 performance in low power mode varies with frequency. Below 400MHz the average change between normal mode and low power mode is small. Above 400MHz low power mode causes an increasing degradation reaching 15dB (typical) at maximum operating frequency. Around 450MHz the degradation is typically 2 to 5 dB. As is usual with IP2 measurements, variations in measured values are observed at different frequency offsets, between I and Q channels and between devices, so average values must be considered. The CMX994A/CMX994E has other low power modes that are enabled using the Options Control Register ($15). Power can be reduced by disabling the phase correction circuits ($15 = $03) if the excellent I/Q balance provided by the CMX994A/CMX994E is not needed. Another option is to disable either I or Q path; this facility is useful for minimising power when monitoring a channel for a RF signal. 8.1.6 I/Q Filter Response The I/Q filter has a well-defined response and an internal calibration scheme makes it very stable with temperature. The response with temperature, measured through the entire receiver, is shown in Figure 22(a). It will be observed that, apart from a small change in overall gain, the filter response does not vary. The scaling with ACR Flt bits (Rx Control Register ($12), b4-b3) is shown in Figure 22(b). 55.00 5 MAX BW MID BW 3 50.00 MIN BW Room +55degs +85degs -20degs -40degs 1 40.00 -3 Diff Gain (dB) Output Level (dB) -1 45.00 -5 -7 35.00 30.00 -9 25.00 -11 20.00 -13 15.00 -15 0.1 100 1000 10000 100000 1 10 100 Freq (kHz) Frequency (Hz) (a) (b) Figure 22 I/Q Filter Response 2015 CML Microsystems Plc D/994_A_E/1 Page 42 of 70 Direct Conversion Receivers 8.1.7 CMX994/CMX994A/CMX994E Baseband Intermodulation The intermodulation (IMD) performance of the CMX994 I/Q baseband amplifiers is designed to be good enough to ensure that the overall IMD performance of the down-converter section is dominated by the performance of the mixers. Typical in-band linearity with a very large output signal is demonstrated in Figure 23. Note the absence of IMD products. Care should be taken in the CMX994 receiver system design to ensure that the baseband sections do not clip in the presence of intermodulation test signals because, if clipping occurs, the overall intermodulation performance of the receiver will be degraded. The CMX994 provides two I/Q baseband filter stages which can be used to provide selectivity in order to keep IMD test signals within the receiver dynamic range. Figure 23 Baseband Intermodulation Test at circa 6Vp-p Differential Output 8.1.8 LO Pulling A VCO that uses the on-chip negative resistance amplifier can be pulled in frequency if a high level signal is applied to the mixer input, as a result of which the VCO becomes modulated resulting in distortion of the output I/Q signals. The level of signal required before the onset of this effect is typically between around 45dBm and -20dBm (at the LNA input), depending on the settings of I/Q VGA gain, LNA gain and the PLL. The LNA gain control provided by the CMX994 mitigates this effect; at large input signal levels the LNA gain should be set to minimum. Designs using the CMX994 with an external LNA should consider this issue and ensure the external LNA provides sufficient gain control range. Designs that use the CMX994 with an external VCO / PLL, in particular a Fractional-N type, are less susceptible to such frequency pulling but should still employ suitable isolation between the CMX994 LO input and an external VCO, for example by using a common-base buffer stage. Following these guidelines a design can readily achieve good receiver system operation with LNA input levels of >+10dBm. 2015 CML Microsystems Plc D/994_A_E/1 Page 43 of 70 Direct Conversion Receivers 8.1.9 CMX994/CMX994A/CMX994E Rx Mixer Output (Broadband Operation) The CMX994 Rx mixer can be used by coupling the signal from pins IFLT1N, IFLT1P (differential signal, I channel) and QFLT1N, QFLT1P (differential signal, Q channel); see Figure 24. For optimum performance, differential connection is recommended but a single ended connection will also work. The signal is dc coupled with a bias voltage of typically 1.25V. The typical source impedance of each pin is 800 Ohms. When using this configuration the following recommendations should be followed: If signals are to be coupled from the CMX994 mixer outputs then the baseband gain must be set to maximum attenuation (-42dB, minimum gain) by setting all of b2, b1 and b0 of Rx Gain Register: C-BUS address $16 to a value of ‘1’; this applies where the baseband sections are enabled or disabled; If the baseband sections are enabled (set b6 of Rx Control Register: C-BUS address $12, to ‘0’) dc offset correction registers may be used to change the dc offset at mixer outputs; Capacitance, including stray capacitance in the PCB layout, must be minimised to achieve the maximum available signal bandwidth. External Baseband Circuit, Q Q RREF QFLT2N QFLT2P IFLT2N IFLT2P QFLT1N, 32 No Connect Rs Rs Rs I RXIP RXIN (C1) /6 /4 /2 (C3) Q + _ MIXERS DC Offset VGA RXQP No Connect _ External Baseband Circuit, I DC Offset + Rs MIXIN, 9 I QFLT1P, 33 IFLT1N, 3 Components C1, C2, C3, C4 and R1, as shown in Figure 9 are not required; IFLT1P, 2 RXQN BASEBAND DC Offset control blocks are present only when the baseband section is enabled. (C2) (C4) Always set VGA to -42dB (minimum gain), even when the baseband section is disabled. Figure 24 External Baseband Circuit Connections to Mixer 2015 CML Microsystems Plc D/994_A_E/1 Page 44 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E I/Q Relative Output Level from Nominal / dB Assuming a good PCB layout with minimal stray capacitance, Figure 25 shows the typical bandwidth of the Rx mixer output. 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/Q Output Frequency / MHz Figure 25 Rx Mixer Output Bandwidth 8.1.10 Spurious Responses An advantage of the direct conversion receiver approach is the inherently low number of spurious responses, however the circuit still has responses at harmonics and sub-harmonics. The circuit designer will need to provide suitable high-pass and low-pass filtering at the CMX994/CMX994A/CMX994E input (and/or between LNA and mixers) to prevent such responses. Note: large signals at sub-harmonic frequencies will generate harmonics in the LNA output which cannot be removed after the LNA because they are on the wanted frequency of the receiver. 2015 CML Microsystems Plc D/994_A_E/1 Page 45 of 70 Direct Conversion Receivers 8.2 CMX994/CMX994A/CMX994E Operation Below 100MHz The CMX994/CMX994A/CMX994E can be safely used below 100MHz, down to at least 30MHz, however performance will degrade at lower frequencies and will fall particularly rapidly below 50MHz. 50 30 49 Gain / dB 47 20 46 45 15 44 10 43 42 Noise Figure / dB 25 48 5 Gain NF 41 40 20 30 40 50 60 70 80 90 100 110 0 120 Frequency / MHz Figure 26 Typical Gain and NF Variation of Demodulator Stages at Low Frequencies The LNA can be matched for 30MHz giving a gain of 15.5dB and noise figure of 5dB. Intermodulation is typically +3.5dBm. For a 50MHz application, typical circuit values are shown in Table 18using the circuit of Figure 7. Typical results using this configuration are shown in Table 19. C1 C2 C3 1nF 33 pF // 10nF 1nF L1 L2 L3 560 nH 12 pF (capacitor) Not Fitted Table 18 50MHz LNA and Inter-stage Components (100Ω mode) Parameter Gain Noise Figure IIP3 Result 63.5dB 5dB -0.5dBm Table 19 Summary of Results for the Complete Rx Chain at 50MHz 2015 CML Microsystems Plc D/994_A_E/1 Page 46 of 70 Direct Conversion Receivers 8.3 CMX994/CMX994A/CMX994E Transmitter LO Output The transmitter LO output is taken from the CMX994 LO source and is independently buffered or divided to the TXLO pin. The division ratio is selected with the TXDIV0 and TXDIV1 bits in the VCO Control register ($25, b5-b6; see section 7.11.1). The output level variation with frequency of the TXLO output is shown in Figure 27 and typical variation with temperature is shown in Figure 28 and Figure 29. 0 Output Level / dBm -1 -2 No Divider -3 With Divider -4 -5 -6 -7 -8 -9 -10 0 200 400 600 800 1000 Frequency / MHz Figure 27 Tx Output Level vs. Frequency Output Level / dBm 0 150 MHz -1 450 MHz -2 940 MHz -3 -4 -5 -6 -7 -40 -20 0 20 40 60 80 Temperature / deg C Figure 28 Typical Tx Output Level (With Divider) vs. Temperature 2015 CML Microsystems Plc D/994_A_E/1 Page 47 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 0 0 dBm Output Level / dBm -1 -20 dBm -2 -3 -4 -5 -6 -40 -20 0 20 40 60 80 Temperature / deg C Figure 29 Typical Tx Output Level (No Divider) vs. Temperature for Varying LO Input Level 8.4 Modem Solutions The CMX994 supports a wide range of modulations. By way of example, the device can be operated with CML baseband / modem devices as shown in Table 20. This table is not exhaustive and other combinations are also possible. Modulation Standard CML Modem IC 4-FSK dPMR TS 102 490 TS 102 658 DMR TS 102 361 General Purpose General Purpose General Purpose CMX7341 (FI-1) CMX7141 (FI-7) 4-FSK 4-FSK, 8-FSK, 16-FSK GMSK/GFSK 4-QAM, 16-QAM, 64-QAM Pi/4-DQPSK C4FM / H-CPM Analogue FM CMX7341 (FI-2) CMX7161 CMX7164 (FI-2) CMX7164 (FI-1) CMX7163 CMX7164 (FI-4) TETRA EN 300 392-2 APCO P25 TIA-603, EN 300 296 EN 300 086 CML Baseband Interface IC CMX983 CMX981, CMX983 CMX981, CMX7861, CMX983 CMX7341 (FI-1) Table 20 Modulation/Modem Combinations 8.5 Zero IF, near-zero IF and low IF I/Q architectures The CMX994/CMX994A/CMX994E provides a complete receiver signal path including LNA, RF down mixer stage and baseband amplifiers with filters to down convert the wanted RF signal to I/Q baseband while supporting high performance in a small total size. This single conversion approach provides many benefits, e.g. it requires only one LO source, which reduces circuitry and eliminates a source of many spurious responses and relative to multi-stage architectures such as dual superhet, it eliminates one or more bulky image rejection filters. The I/Q output format supports a host of modulations, including phase coherent constant envelope (e.g. CP-FSK) and linear (QAM) ones. Mixing the wanted signal down to 0Hz (zero IF) by setting mixer LO and wanted RF signal frequencies to be the same provides a unique benefit, which is that it avoids placing the image of adjacent channel and other 2015 CML Microsystems Plc D/994_A_E/1 Page 48 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E close-in interferers at the same frequency band as the wanted modulation. This is especially helpful if one considers that the adjacent channel interferer power may be far greater than the wanted signal’s. The zero IF approach also minimises the bandwidth of I/Q output signals, which reduces the cost, power and complexity of ADCs used to sample them. Lastly, it enables a low pass filter on each of I and Q signal paths to provide selectivity, which simplifies design by reducing filter complexity and the required dynamic range of the ADCs. While it is true that second order mixer intermodulation products also lie at 0Hz (DC), the CMX994/CMX994A/CMX994E feature best in class, (+79dBm) mixer IIP2 performance to attenuate such DC intermod products. For specific radio systems one may wish to avoid mixing the wanted signal down to 0Hz. The CMX994/CMX994A/CMX994E readily supports this by allowing the user to select LO frequencies that do not exactly match the wanted RF signal’s carrier. Near-zero IF I/Q architectures often set the LO frequency to between half to two times the required channel bandwidth, which provides frequency separation between the wanted signal and any DC components in the output I and Q signals. Such architectures then sample (ADC convert) the near-zero I/Q IF signal pair and then use digital baseband processing to both implement a simple high pass filter that removes DC and perform a final frequency mix down to 0Hz. Operating in such a near-zero IF mode requires the CMX994 baseband low pass filters to be scaled wider appropriately to pass the chosen IF frequency; the filter components external to the CMX994 will need to be revised; see section 6.2.3. Sampling ADC bandwidth must also be somewhat higher performance and therefore higher power than ADCs used in the zero IF architecture. Another and perhaps more significant trade-off of near-zero IF is that the adjacent channel image generated by unavoidable I/Q gain and phase errors typically now falls on the wanted signal to create a significant interference component if the adjacent channel signal level is high. The low IF I/Q architecture is a conceptual extension of near-zero IF; it sets the mixer LO frequency to something different than the wanted RF carrier frequency but with even more frequency separation than near-zero IF uses. The result is that the wanted signal is mixed to an even higher frequency at the I/Q outputs. This approach can permit receiver I/Q outputs to be AC coupled to ADCs. Low IF I/Q trade-offs are of the same type as those presented by near-zero IF but they are more challenging, i.e. wider bandwidth ADCs must be used. The CMX994/CMX994A/CMX994E supports all of zero IF, near-zero IF and low IF I/Q architectures, with the benefits of LNA to I/Q output integration with amplification, low pass filtering, and operating modes selected via serial host control. 2015 CML Microsystems Plc D/994_A_E/1 Page 49 of 70 Direct Conversion Receivers 9 Performance Specification 9.1 Electrical Performance CMX994/CMX994A/CMX994E For a definition of voltage and reference signals, see section 4.1. 9.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. ESD Warning: This high performance RF integrated circuit is an ESD sensitive device which has unprotected inputs and outputs. Handling and assembly of this device should only be carried out at an ESD protected workstation. Supply (AVDD - AVSS) or (DVDD - DVSS) Voltage on any pin to AGND or DGND pins Voltage between AVDD and DVDD Voltage between AGND and DGND pins Current into or out of DGND, VDDIO, VCCRXIF, VCCRF, VCCLNA, VCCSYNTH, VCCLO or DVDD pins Current into or out of AGND (exposed metal pad) Current into or out of any other pin Min. -0.3 -0.3 -0.3 -50 -75 Max. +4.0 Vmax + 0.3 +0.3 +50 +75 Units V V V mV mA -200 -20 +200 +20 mA mA Max. 1820 18.2 +125 +85 Units mW mW/°C °C °C Min. 3.0 Max. 3.6 Units V 1.6 -40 DVDD + 0.3 +85 V °C +3 dBm Note: see section 4.1 for definitions of signals. Q4 Package Total Allowable Power Dissipation at TAMB = 25°C ... De-rating Storage Temperature Operating Temperature 9.1.2 Min. – – -55 -40 Operating Limits Correct operation of the device outside these limits is not implied. Notes Analogue Supply (AVDD) and Digital Supply (DVDD) IO Supply (VDDIO) Operating Temperature Maximum continuous input to pin LNAIN Notes: A. A For signals that are not continuous, higher input powers are permitted; power levels above +10dBm should be avoided especially when the device is operating close to the maximum rated operating temperature. 2015 CML Microsystems Plc D/994_A_E/1 Page 50 of 70 Direct Conversion Receivers 9.2.1 CMX994/CMX994A/CMX994E Operating Characteristics For the following conditions unless otherwise specified: AVDD = DVDD = VDDIO = 3.0V to 3.6V; VSS = AVSS = DVSS, TAMB = +25°C; registers in default condition except where otherwise specified or as necessary to enable the relevant sections of the device for half duplex operation. DC parameters DC Parameters Total Current Consumption Notes Min. Typ. Max. Units 1, 2 – 25 – µA 4 – 1.7 3.5 mA Rx Only 5 – 66 80 mA Rx Only, Low Power Mode 5a – 56 – mA Rx Only, Low Power Mode and Phase Correction off 5c 42 mA Rx Only, Low Power Mode and Phase Correction off, I or Q channel disabled 5d 33 mA Rx Only, Enhanced Intermodulation Mode 5e 74 90 mA Tx Only 5 – 22 30 mA LNA Only 5 – 9 15 mA LNA in 50 Output Mode 5b – 11 – mA I/Q Demodulator 5 – 41 53 mA Baseband I/Q 5 – 13 15 mA VCO and Buffer 5 – 10 13 mA LO Input 5 – 5 7 mA PLL 5 – 5.5 – mA 3 – – 600 µA Logic “1” Input Level 70% – – VDDIO Logic ‘0’ Input Level – – 30% VDDIO Output Logic ‘1’ Level (lOH = 0.6 mA) 80% – – VDDIO Output Logic ‘0’ Level (lOL = -1.0 mA) – – +0.4 V – – – 0.5 ms – 10 µs Powersave Mode VBIAS Only Operating Currents Stage currents Current from VDDIO Power-up Time Internal Bias Supplies All Blocks Except Internal Bias 6, 7 6 2015 CML Microsystems Plc D/994_A_E/1 Page 51 of 70 Direct Conversion Receivers Notes: CMX994/CMX994A/CMX994E 1. Powersave mode current applies to both the following operating cases: (a) after a General Reset command has been issued and with all analogue and digital supplies applied and also (b) with DV DD applied but with all analogue supplies disconnected. For case (b), DV DD current will not exceed the specified value and is independent of the state of the registers. 2. TAMB = 25°C, not including any current drawn from the device pins by external circuitry. 3. Assumes 30pF on each C-BUS interface line and an operating serial clock frequency of 5MHz. 4. The stated current drawn here is with the bandgap reference and accompanying bias current generators enabled only (General Control Register – $11), all other circuitry is disabled. 5. Not including any current drawn from the device pins by external circuitry or the bias current. Rx Only – Rx Circuitry as enabled: Rx Gain Register = 0x00, General Control Register = 0xC2, Rx Control Register = 0x10 and Intermodulation Control Register = 0x3F; TX Only – General Control Register = 0x81, divide by 2 mode; LNA Only – 0x82 is written to the General Control Register and 0xC0 to the Rx Control register; I/Q Demodulator – 0x60 is written to the Rx Control register; Baseband I/Q – 0xA0 is written to the Rx Control register; VCO and Buffer – 0x88 is written to the General Control Register and 0x03 to the VCO Control Register; LO Input – 0x84 is written to the General Control Register and 0x10 to the VCO Control Register; PLL – 0x00 is written to the VCO Control Register, 0x82 is written to the General Control Register and 0x80 to PLL M register ($22). 5a. As note 5 except General Control Register ($11) b4 = ‘1’; see sections 7.2.1 and 8.1.5. 5b. As note 5 except Rx Gain Register ($16) b3 = ‘1’; see section 7.7.1. 5c. As note 5 except General Control Register ($11) b4 = ‘1’; see section 7.2.1, Option Control Register ($15) b0 = ‘1’ and b1 = ‘1’; see section 7.6.1. 5d. As note 5 except General Control Register ($11) b4 = ‘1’; see section 6.2.1, Option Control Register ($15) b3- b0 = ‘1011 or ‘0111’ section 6.6.1. 5e. As note 5 except Option Control Register ($15) b8 = ‘1’; see section 7.6.1 6. As measured from the rising edge of CSN. 7. Bias is enabled by General Control Register ($11) b7; see section 7.2.1 2015 CML Microsystems Plc D/994_A_E/1 Page 52 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E AC Parameters – Low Noise Amplifier Section LNA Gain Notes Min. Typ. Max. Units 100MHz 14 – 15 – dB 450MHz 12,14 – 12.5 – dB 940MHz 17 – 11 – dB 100MHz 14 – -40 – dB 450MHz 14 – -27 – dB 940MHz 17 – -19 – dB Gain Control Range 16 – 18 – dB Gain Control Step Size 16 4 6 8 dB Noise Figure 14 100MHz 14 – 2 – dB 450MHz 14 – 2 – dB 940MHz 17 – 3.5 – dB 14 – 8 – dBm 450MHz 11,14 – 8 – dBm 940MHz 11,14,17 – 0.5 – dBm 100MHz 14 – -11 – dBm 450MHz 14 – -12 – dBm 940MHz 17 – -10 – dBm 10 – – – Ω 10, 13 – – Ω 15 100 100R // 1.2pF – 1000 MHz – <-90 – dBm Reverse Isolation (S12) Third Order Intercept Point (input) 100MHz 1dB Gain Compression Point (input) Input Impedance Output Impedance Operating Frequency Range LO Leakage at LNA Input Notes: 10. For further details see section 5.2.1 11. Intermodulation optimised using Intermodulation Control Register, for further details see section 6.5. 12. The gain is approximately 2dB higher if the LNA Z0 (Rx Gain Register b3) is set to ‘1’. 13. The impedance is approximately 50Ω if the LNA Z0 (Rx Gain Register b3) is set to ‘1’. 14. Measured at maximum gain with the LNA Zo (Rx Gain Register b3) set to ‘0’. 15. For extended operation down to 50MHz see section 8.2. 16. See section 8.1.3 for further details 17. LNA Z0 = 50Ω (Rx Gain Register b3 set to ‘1’) 2015 CML Microsystems Plc D/994_A_E/1 Page 53 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E AC Parameters – Direct Conversion Receiver Sections (CMX994, CMX994A, CMX994E in normal mixer intermod mode) I/Q Demodulator Notes Min. Typ. Max. Units (combined performance of receiver sections, excluding LNA) Gain 450MHz – 49 – dB(V/V) 940MHz – 49 – dB(V/V) 450MHz – 14.5 – dB 940MHz – 16 – dB Noise Figure Third Order Intercept Point (Input) 450MHz – 11 – dBm 940MHz – 9.5 – dBm Second Order Intercept Point (Input) 100MHz to 600MHz 25 – 79 – dBm 600MHz to 940MHz 25a – 73 – dBm 24, 24a – 0 – dBm 30 40 – dB 25 – – dB – 0.03 0.1 0.15 – dB – – 0.5 2.0 deg. 24 – 22 17 3 33 deg. I/Q DC Offset Correction Steps 1 25 I/Q DC Offset at Maximum Attenuation 20a – 23 – 55 1.6 mV I/Q Output Bandwidth 15 – – 2, 4 or 6 – 1dB Compression Point (Input) Image Rejection (I/Q Gain/Phase Matching) LO Phase Correction On (CMX994 always On) LO Phase Correction Off (CMX994/CMX994E) 24 I/Q Amplitude Balance LO Phase Correction On (CMX994 always On) LO Phase Correction Off (CMX994/CMX994E) 24 dB I/Q Phase Balance LO Phase Correction On (CMX994 always On) LO Phase Correction Off (CMX994/CMX994E) LO Divider Ratios (selectable) mV MHz I/Q Differential Output Voltage Swing 20 – – 4.0 Vp-p Blocking 21 93 96 – dB AC Parameters – Direct Conversion Receiver Sections (CMX994E register $15, b7 set to ‘1’ (enhanced mixer intermodulation mode) I/Q Demodulator (CMX994E) Notes Min. Typ. Max. Units (combined performance of receiver sections, excluding LNA) Gain 450MHz – 49 – dB(V/V) 1000MHz – 49 – dB(V/V) 100MHz – 14.5 – dB 450MHz – 15 – dB 870MHz – 16 – dB Noise Figure 2015 CML Microsystems Plc D/994_A_E/1 Page 54 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E 1000MHz – 16.5 – dB 100MHz – 19 – dBm 450MHz – 15 – dBm 870MHz – 12 – dBm 1000MHz – 11.5 – dBm Third Order Intercept Point (Input) Second Order Intercept Point (Input) 100MHz to 600MHz 25 – 79 – dBm 600MHz to 1000MHz 25a – 73 – dBm 24, 24a – 0 – dBm 30 40 – dB 25 – – dB – 0.03 0.1 0.15 – dB – – 0.5 2.0 deg. 24 – 1 25 3 33 deg. 55 1.6 mV 1dB Compression Point (Input) Image Rejection (I/Q Gain/Phase Matching) LO Phase Correction On LO Phase Correction Off 24 I/Q Amplitude Balance LO Phase Correction On LO Phase Correction Off 24 dB I/Q Phase Balance LO Phase Correction On LO Phase Correction Off I/Q DC Offset Correction Steps 22 17 20a – 23 – 15 – LO Divider Ratios (selectable) – 2, 4 or 6 – LO Divider Noise Floor – -152 – dBc/Hz I/Q DC Offset at Maximum Attenuation I/Q Output Bandwidth mV MHz I/Q Differential Output Voltage Swing 20 – – 4.0 Vp-p Blocking 21 93 96 – dB 2015 CML Microsystems Plc D/994_A_E/1 Page 55 of 70 Direct Conversion Receivers Notes: CMX994/CMX994A/CMX994E 20. This is the maximum swing to guarantee meeting the third order distortion characteristics under the specified conditions and is not the maximum limiting value. For clarity, this means that the device has the capability to produce +/-1V on each of the differential outputs. The outputs are capable of driving a load resistance across the differential outputs of 1kΩ. This voltage output capability provides easy interfacing to other CML devices, like the CMX981, which has a maximum input signal amplitude of 2.4Vp-p. 20a Voffset minimised using Vcorr at minimum attenuation then with maximum baseband attenuation set Voffset is measured, mixer RF input terminated in 50 Ohms; see also section 8.1.2. 21. Test method based on EN 300 166; including operation of selectable dividers. 22. Register $12, b2 = ‘0’. 23. This is the maximum bandwidth of the I and Q output signals with no external capacitors fitted and with the filter calibration circuit disabled. The bandwidth of the I/Q output can be adjusted to suit the application by use of the I/Q filters. This bandwidth can be set by using external capacitors (see sections 6.2.2 and 6.2.3). Note that a 25kHz bandwidth on the I/Q filters supports a modulation signal bandwidth of 50kHz. 24. Measured at 450MHz. 24a Measured with baseband attenuations settings of 30dB and above, with less attenuation measurement is limited by the output compression point. 25. Average value of IIP2 measurements at 1MHz, 5MHz and 10MHz offsets using differential signals on I and Q channels, measurements every 100MHz over the range 100MHz to 600MHz. 25a Average value of IIP2 measurements at 1MHz, 5MHz and 10MHz offsets using differential signals on I and Q channels, measurements at 600MHz and every 50MHz over the range 700MHz to 950MHz (1000 MHz for CMX994A/CMX994E). Rx Direct Conversion Mixers Gain Notes Min. Typ. Max. Units 26 – 15 – dB(V/V) – 15 – dB(V/V) 27 – 13.5 – dB 27, 24 – 11 – dBm Input Frequency Range (CMX994) 15 100 – 940 MHz Input Frequency Range (CMX994A/CMX994E) 15 100 – 1000 MHz LO Frequency Range (before internal division) 15 200 MHz 29 – – – 2000 Input Impedance – Ω 1 – MHz 29a – 10 MHz 28 – -80 450MHz 940MHz Noise Figure 450MHz Third Order Intercept Point (Input) 450MHz Zero-IF Signal Bandwidth at mixer output with CMX994 baseband at mixer output with external baseband LO Leakage at Input Notes: – dBm 26. Measured from matched input source. 27. This is an indicative specification only as the parameter cannot be independently measured other than as part of the complete Rx Path. 28. Measured at input to mixers with 100 Ohm termination. 29. For further details see section 5.2 29a. A 10MHz zero-IF signal bandwidth on the mixer I/Q output (pins IFLT1N, IFLT1P and QFLT1N, QFLT1P) supports a modulation signal bandwidth of 20MHz. See section 8.1.7. 2015 CML Microsystems Plc D/994_A_E/1 Page 56 of 70 Direct Conversion Receivers Zero IF Amplifiers and Filters Gain Noise Figure Third Order Intercept Point (Output) CMX994/CMX994A/CMX994E Notes 26, 30 Min. – 27 27,30a Output Impedance Typ. 34 Max. – Units dB(V/V) – – 10 dB – >50 – dBm – 20 – Ω 1dB Compression Point 27 -30 – – dBm VGA Control Range 31 – 42 – dB VGA Step Size 4 6 8 dB I/Q Output Bandwidth – – 1.6 MHz – – 4.0 Vp-p – AVDD/2 – V 32, 37 – 88 – kHz 32 – 2 – kHz – 1:2:4 – – – 5 % 27, 35 – 90 – dBc st 27, 35 85 – – dBc nd 27, 36 85 – – dBc I/Q Differential Output Voltage Swing 20 I/Q Output Common Mode Post Mixer Filter Bandwidth (-3dB) Adjacent Channel Rejection Bandwidth (-3dB) Scaling Factors Bandwidth Variation Third Order Intermodulation Post Mixer Filter 1 Amplifier 2 Amplifier 33 34 Notes: 30. The first amplifier stage has nominal gain of 15dB, the second stage has nominal gain of 22dB. 30a. In-band intermodulation calculated from output signal assuming 50Ω impedance; see also section 8.1.7. 31. Eight VGA steps. 32. Assumes the recommended external capacitors are used (see section 5.2.2). 33. Assuming external resistors with 1% tolerance and external capacitors with 5% tolerance. 34. Tested at maximum gain setting of VGA. 35. Assuming two 200mVp-p tones at 25kHz and 50kHz. 36. Assuming two 60mVp-p tones at 25kHz and 50kHz. 37. The post mixer filter bandwidth will vary with VGA setting. This may typically be 30%, with the bandwidth reducing at lower gain settings. 2015 CML Microsystems Plc D/994_A_E/1 Page 57 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E AC Parameters – Tx Output Tx Divider Input Frequency Range Notes Output Frequency Range Divider Ratio Min. 100 Typ. – Max. 2000 Units MHz 100 – 1000 MHz – 1, 2, 4 or 6 – Output Level 38 -5.5 -3.5 -1.5 dBm Noise Floor 39 – -146 – dBc/Hz Notes: 38. 448MHz output with LO divider ratio = 2; see section 0 for further information. 39. Noise at 5MHz offset, measured at 500MHz with 1GHz Local Oscillator. AC Parameters – Integer N PLL / VCO and LO input Phase Locked Loop Reference Input Frequency Level Divide Ratios (R Counter) Synthesiser Comparison Frequency (fcomparison) Input Frequency Range Input Level Divide Ratios (M Counter) Charge Pump Current 1Hz Normalised Phase Noise Floor VCO Negative Resistance Amplifier Frequency Range Phase Noise at 10kHz Offset Phase Noise at 100kHz Offset VCO Buffer Frequency Range LO Input Input Level Frequency Range Notes: Notes Min. Typ. Max. Unit 40 5 0.5 2 – – – 30 – 32767 MHz Vp-p – – -4 – 2.5 -216 500 1100 – 262143 – – kHz MHz dBm 43 – 200 -10 2 – – mA dBc/Hz 42 41 41 200 – – – -96 -116 1100 – – MHz dBc/Hz dBc/Hz 200 – 1100 MHz -15 100 -10 – -5 2000 dBm MHz 44 40. 41. 42. 43. Sinewave or clipped sinewave. With external components forming an 750MHz VCO and its LO divider value set to 4. Operation will depend on the choice and layout of external resonant components. 1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within the PLL loop bandwidth by: Measured Phase Noise (in 1Hz) = -PN1Hz - 20log10(M) - 10log10(fcomparison) 44. Single-ended input as described in section 5.3.1. 2015 CML Microsystems Plc D/994_A_E/1 Page 58 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E AC Parameters – C-BUS C-BUS Timings (See Figure 30) tCSE CSN-enable to clock-high time Notes Min. 100 Typ. – Max. – Units ns tCSH Last clock-high to CSN-high time 100 – – ns tLOZ Clock-low to reply output enable time 0.0 – – ns tHIZ CSN-high to reply output 3-state time – – 1.0 µs tCSOFF CSN-high time between transactions 1.0 – – µs tNXT Inter-byte time 200 – – ns tCK Clock-cycle time 200 – – ns tCH Serial clock-high time 100 – – ns tCL Serial clock-low time 100 – – ns tCDS Command data set-up time 75.0 – – ns tCDH Command data hold time 25.0 – – ns tRDS Reply data set-up time 50.0 – – ns tRDH Reply data hold time 0.0 – – ns Maximum 30pF load on each C-BUS interface line. Figure 30 C-BUS Timing 2015 CML Microsystems Plc D/994_A_E/1 Page 59 of 70 Direct Conversion Receivers 9.3 CMX994/CMX994A/CMX994E Packaging DIM. * * MIN. TYP. MAX. 6.00 BSC A B C F G H J K L L1 P T 0.80 4.00 4.00 0.00 0.18 0.20 0.30 0 6.00 BSC 0.90 0.25 1.00 4.30 4.30 0.05 0.30 0.50 0.15 0.40 0.50 0.20 NOTE : * Exposed Metal Pad A & B are reference data and do not include mold deflash or protrusions. All dimensions in mm Angles are in degrees Index Area 1 Dot Index Area 2 Dot Chamfer Index Area 1 is located directly above Index Area 2 Depending on the method of lead termination at the edge of the package, pull back (L1) may be present. L minus L1 to be equal to, or greater than 0.3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also be required Notes: 1. 2. In this device, the underside of the Q4 package should be electrically connected to the analogue ground. The circuit board should be designed so that no unwanted short circuits can occur. As package dimensions may change after publication of this datasheet, it is recommended that you check for the latest Packaging Information from the Datasheets page of the CML website: [www.cmlmicro.com]. Figure 31 Q4 Mechanical Outline Order as part no.CMX994Q4 CMX994AQ4 CMX994EQ4 2015 CML Microsystems Plc D/994_A_E/1 Page 60 of 70 Direct Conversion Receivers CMX994/CMX994A/CMX994E Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.