The following document contains information on Cypress products.
MB9B510R Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF512N/R, MB9BF514N/R,
MB9BF515N/R, MB9BF516N/R
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9B510R-DS706-00025
CONFIDENTIAL
Revision 3.1
Issue Date March 31, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
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consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
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Some data sheets contain a combination of products with different designations (Advance Information,
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disclaimer on the first page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9B510R-DS706-00025-3v1-E, March 31, 2015
CONFIDENTIAL
MB9B510R Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BF512N/R, MB9BF514N/R,
MB9BF515N/R, MB9BF516N/R
Data Sheet (Full Production)
Description
The MB9B510R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN,
UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE4 product categories in FM3
Family Peripheral Manual.
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9B510R-DS706-00025
Revision 3.1
Issue Date March 31, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
・ Processor version: r2p1
・ Up to 144 MHz Frequency Operation
・ Memory Protection Unit (MPU): improves the reliability of an embedded system
・ Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・ 24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash memories.
・ MainFlash
・ Up to 512 Kbyte
・ Built-in Flash Accelerator System with 16 Kbyte trace buffer memory
・ The read access to Flash memory can be achieved without wait cycle up to operation frequency of
72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory
can be obtained by Flash Accelerator System.
・ Security function for code protection
・ WorkFlash
・ 32 Kbyte
・ Read cycle
・ 4 wait-cycle: the operation frequency more than 72 MHz
・ 2 wait-cycle: the operation frequency more than 40 MHz, and to 72 MHz
・ 0 wait-cycle: the operation frequency to 40 MHz
・ Security function is shared with code protection
[SRAM]
This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is
connected to System bus.
・ SRAM0: Up to 32 Kbyte.
・ SRAM1: Up to 32 Kbyte.
External Bus Interface
・ Supports SRAM, NOR and NAND Flash device
・ Up to 8 chip selects
・ 8-/16-bit Data width
・ Up to 25-bit Address bit
・ Maximum area size : Up to 256 Mbytes
・ Supports Address/Data multiplex
・ Supports external RDY input
2
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
USB Interface
USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
・ USB2.0 Full-Speed supported
・ Max 6 EndPoint supported
・ EndPoint 0 is control transfer
・ EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
・ EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer
・ EndPoint 1 to 5 is comprised Double Buffer
・ The size of each EndPoint is as follows.
・ EndPoint 0, 2 to 5:64 bytes
・ EndPoint 1: 256 bytes
[USB host]
・ USB2.0 Full/Low-speed supported
・ Bulk-transfer, interrupt-transfer and Isochronous-transfer support
・ USB Device connected/dis-connected automatically detect
・ IN/OUT token handshake packet automatically
・ Max 256-byte packet-length supported
・ Wake-up function supported
CAN Interface (Max two channels)
・ Compatible with CAN Specification 2.0A/B
・ Maximum transfer rate: 1 Mbps
・ Built-in 32 message buffer
Multi-function Serial Interface (Max eight channels)
・ 4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
・ Operation mode is selectable from the followings for each channel.
・ UART
・ CSIO
・ LIN
・ I 2C
[UART]
・ Full-duplex double buffer
・ Selection with or without parity supported
・ Built-in dedicated baud rate generator
・ External clock available as a serial clock
・ Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・ Full-duplex double buffer
・ Built-in dedicated baud rate generator
・ Overrun error detect function available
[LIN]
・ LIN protocol Rev.2.1 supported
・ Full-duplex double buffer
・ Master/Slave mode supported
・ LIN break field generate (can be changed 13 to 16-bit length)
・ LIN break delimiter generate (can be changed 1 to 4-bit length)
・ Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
3
D a t a S h e e t
DMA Controller (Eight channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・ 8 independently configured and operated channels
・ Transfer can be started by software or request from the built-in peripherals
・ Transfer address area: 32-bit (4 Gbyte)
・ Transfer mode: Block transfer/Burst transfer/Demand transfer
・ Transfer data type: byte/half-word/word
・ Transfer block count: 1 to 16
・ Number of transfers: 1 to 65536
A/D Converter (Max 16 channels)
[12-bit A/D Converter]
・ Successive Approximation Register type
・ Built-in 3unit
・ Conversion time: 1.0 μs @ 5 V
・ Priority conversion available (priority at 2 levels)
・ Scanning conversion mode
・ Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
Base Timer (Max eight channels)
Operation mode is selectable from the followings for each channel.
・ 16-bit PWM timer
・ 16-bit PPG timer
・ 16-/32-bit reload timer
・ 16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
・ Capable of pull-up control per pin
・ Capable of reading pin level directly
・ Built-in the port relocate function
・ Up 103 fast general purpose I/O Ports@ 120 pin Package
・ Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
4
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Multi-function Timer (Max three units)
The Multi-function timer is composed of the following blocks.
・ 16-bit free-run timer × 3ch./unit
・ Input capture × 4ch./unit
・ Output compare × 6ch./unit
・ A/D activation compare × 3ch./unit
・ Waveform generator × 3ch./unit
・ 16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
・ PWM signal output function
・ DC chopper waveform output function
・ Dead time function
・ Input capture function
・ A/D convertor activate function
・ DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
・ Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
・ Timer interrupt function after set time or each set time.
・ Capable of rewriting the time with continuing the time count.
・ Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (Max three channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・ The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・ 16-bit position counter
・ 16-bit revolution counter
・ Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・ Free-running
・ Periodic (=Reload)
・ One-shot
Watch Counter
The Watch counter is used for wake up from power consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
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D a t a S h e e t
External Interrupt Controller Unit
・ Up to 16 external interrupt input pin
・ Include one non-maskable interrupt (NMI)
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power consumption mode except Stop mode.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・ CCITT CRC16 Generator Polynomial: 0x1021
・ IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
・ Main Clock:
・ Sub Clock:
・ High-speed internal CR Clock:
・ Low-speed internal CR Clock:
・ Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
[Resets]
・ Reset requests from INITX pin
・ Power on reset
・ Software reset
・ Watchdog timers reset
・ Low voltage detector reset
・ Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
・ External OSC clock failure (clock stop) is detected, reset is asserted.
・ External OSC frequency anomaly is detected, interrupt or reset is asserted.
6
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
・ LVD1: error reporting via interrupt
・ LVD2: auto-reset operation
Low-Power Consumption Mode
Three power consumption modes supported.
・ Sleep
・ Timer
・ Stop
Debug
・ Serial Wire JTAG Debug Port (SWJ-DP)
・ Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
Power Supply
Two Power Supplies
・Wide range voltage:
VCC
・USB for USB I/O voltage: USBVCC
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
= 2.7 V to 5.5 V
= 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
7
D a t a S h e e t
Product Lineup
Memory size
Product name
MainFlash
WorkFlash
On-chip RAM
SRAM0
SRAM1
8
CONFIDENTIAL
MB9BF512N/R
MB9BF514N/R
MB9BF515N/R
MB9BF516R
128 Kbyte
32 Kbyte
16 Kbyte
8 Kbyte
8 Kbyte
256 Kbyte
32 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
384 Kbyte
32 Kbyte
48 Kbyte
24 Kbyte
24 Kbyte
512 Kbyte
32 Kbyte
64 Kbyte
32 Kbyte
32 Kbyte
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Function
Product name
Pin count
CPU
MB9BF512N
MB9BF514N
MB9BF515N
MB9BF516N
MB9BF512R
MB9BF514R
MB9BF515R
MB9BF516R
100/112
Freq.
Power supply voltage range
USB2.0 (Function/Host)
CAN
DMAC
External Bus Interface
MF Serial Interface
(UART/CSIO/LIN/I2C)
120
Cortex-M3
144 MHz
VCC: 2.7 V to 5.5 V
(USBVCC: 3.0 V to 3.6 V)
1ch.
2ch. (Max)
8ch.
Addr: 25-bit (Max)
Addr: 25-bit (Max)
R/Wdata: 8-/16-bit (Max)
R/Wdata: 8-/16-bit (Max)
CS: 8 (Max)
CS: 8 (Max)
Support: SRAM, NOR Flash
Support: SRAM, NOR & NAND Flash
8ch. (Max)
ch.4 to ch.7: FIFO (16 steps × 9-bit)
ch.0 to ch.3: No FIFO
Base Timer
8ch. (Max)
(PWC/Reload timer/PWM/PPG)
A/D
activation
3ch.
compare
Input
4ch.
capture
Free-run
MF3ch.
3 units (Max)
Timer timer
Output
6ch.
compare
Waveform
3ch.
generator
PPG
3ch.
QPRC
3ch. (Max)
Dual Timer
1 unit
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog timer
1ch. (SW) + 1ch. (HW)
External Interrupts
16pins (Max) + NMI × 1
I/O ports
83 pins (Max)
103 pins (Max)
12-bit A/D converter
16ch. (3 units)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz
Internal
OSC
Low-speed
100 kHz
Debug Function
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See " Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
9
D a t a S h e e t
Packages
Product name
Package
QFP: FPT-100P-M36 (0.65 mm pitch)
LQFP: FPT-100P-M23 (0.5 mm pitch)
LQFP: FPT-120P-M37 (0.5 mm pitch)
BGA: BGA-112P-M04 (0.8 mm pitch)
MB9BF512N
MB9BF514N
MB9BF515N
MB9BF516N
MB9BF512R
MB9BF514R
MB9BF515R
MB9BF516R
-
: Supported
Note: See "Package Dimensions" for detailed information on each package.
10
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin Assignment
・ FPT-100P-M23
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/TX0_2/MOEX_0
P63/INT03_0/SIN5_1/RX0_2/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
2
74
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
3
73
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
4
72
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
5
71
P23/SCK0_0/TIOA7_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
6
70
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
7
69
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P56/INT08_2/DTTI1X_0/MADATA06_0
8
68
P1D/AN13/CTS4_1/IC03_1/MAD21_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0
9
67
P1C/AN12/SCK4_1/IC02_1/MAD20_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0
10
66
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0
11
65
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0
12
64
P19/AN09/SCK2_2/MAD17_0
P34/FRCK0_0/TIOB4_1/TX0_1/MADATA11_0
13
63
P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MADATA12_0
14
62
AVSS
LQFP - 100
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0
15
61
AVRH
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0
16
60
AVCC
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0
17
59
P17/AN07/SIN2_2/INT04_1/MAD15_0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
35
51
VCC
25
34
P10/AN00
VSS
33
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0
52
C
53
24
VSS
23
P3F/RTO05_0/TIOA5_1
32
P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1
31
54
P45/TIOA5_0/RTO15_1/MAD01_0
22
P44/TIOA4_0/RTO14_1/MAD00_0
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1
30
55
P43/TIOA3_0/RTO13_1/ADTG_7
21
29
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1
28
56
P42/TIOA2_0/RTO12_1
20
P41/TIOA1_0/RTO11_1/INT13_1
P15/AN05/SOT0_1/IC03_2/MAD13_0
P3B/RTO01_0/TIOA1_1
27
P16/AN06/SCK0_1/MAD14_0
57
26
58
19
VCC
18
P40/TIOA0_0/RTO10_1/INT12_1
P39/DTTI0X_0/ADTG_2
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
11
D a t a S h e e t
・ FPT-120P-M37
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/TX0_2/MOEX_0
P63/INT03_0/SIN5_1/RX0_2/RTO20_0/MWEX_0
P64/TIOA7_0/SOT5_1/INT10_2/FRCK2_1/RTO21_0
P65/TIOB7_0/SCK5_1/IC23_1/RTO22_0
P66/SIN3_0/ADTG_8/INT11_2/IC22_1/RTO23_0
P67/SOT3_0/TIOA7_2/IC21_1/RTO24_0
P68/SCK3_0/TIOB7_2/INT12_2/IC20_1/RTO25_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
(TOP VIEW)
VCC
1
90
VSS
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
2
89
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
3
88
P21/SIN0_0/INT06_1/BIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
4
87
P22/SOT0_0/TIOB7_1/ZIN1_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
5
86
P23/SCK0_0/TIOA7_1/RTO00_1
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
6
85
P24/RX1_0/SIN2_1/INT01_2/RTO01_1
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
7
84
P25/TX1_0/SOT2_1/RTO02_1
P56/SIN1_0/INT08_2/DTTI1X_0/MADATA06_0
8
83
P26/SCK2_1/RTO03_1
P57/SOT1_0/MADATA07_0
9
82
P27/TIOA6_2/INT02_2/RTO04_1
P58/SCK1_0/AIN2_0/MADATA08_0
10
81
P28/TIOB6_2/ADTG_4/RTO05_1
P59/SIN7_0/RX1_1/INT09_2/BIN2_0/MADATA09_0
11
80
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P5A/SOT7_0/TX1_1/ZIN2_0/MADATA10_0
12
79
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P5B/SCK7_0/MADATA11_0
13
78
P1D/AN13/CTS4_1/IC03_1/MAD21_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA12_0
14
77
P1C/AN12/SCK4_1/IC02_1/MAD20_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA13_0
15
76
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA14_0
16
75
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA15_0
17
74
P19/AN09/SCK2_2/MAD17_0
P34/FRCK0_0/TIOB4_1/TX0_1/MNALE_0
18
73
P18/AN08/SOT2_2/MAD16_0
P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MNCLE_0
19
72
AVSS
P36/IC02_0/SIN5_2/INT09_1/MNWEX_0
20
71
AVRH
P37/IC01_0/SOT5_2/INT10_1/MNREX_0
21
70
AVCC
P38/IC00_0/SCK5_2/INT11_1
22
69
P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/DTTI0X_0/ADTG_2
23
68
P16/AN06/SCK0_1/MAD14_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
24
67
P15/AN05/SOT0_1/IC03_2/MAD13_0
P3B/RTO01_0/TIOA1_1
25
66
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3C/RTO02_0/TIOA2_1
26
65
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3D/RTO03_0/TIOA3_1
27
64
P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0
P3E/RTO04_0/TIOA4_1
28
63
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0
P3F/RTO05_0/TIOA5_1
29
62
P10/AN00
VSS
30
61
VCC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_0
P45/TIOA5_0/RTO15_1/MAD01_0
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
P70/TX0_0/TIOA4_2
P71/RX0_0/INT13_2/TIOB4_2
P72/SIN2_0/INT14_2/TIOA6_0
P73/SOT2_0/INT15_2/TIOB6_0
P74/SCK2_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 120
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ FPT-100P-M36
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0
VCC
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0
P61/SOT5_0/TIOB2_2/UHCONX
P62/SCK5_0/ADTG_3/TX0_2/MOEX_0
P63/INT03_0/SIN5_1/RX0_2/MWEX_0
P0F/NMIX/CROUT_1/RTCCO_0/DTTI2X_0/DTTI2X_1/SUBOUT_0
P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0
P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0
P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0
P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0
P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0
P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0
P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0
P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0
P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0
P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_0
P01/TCK/SWCLK
P00/TRSTX/MCSX7_0
VCC
VSS
P20/INT05_0/CROUT_0/AIN1_1/MAD24_0
P21/SIN0_0/INT06_1/BIN1_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0
81
50
P22/SOT0_0/TIOB7_1/ZIN1_1
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0
82
49
P23/SCK0_0/TIOA7_1
P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0
83
48
P1F/AN15/ADTG_5/FRCK0_1/MAD23_0
P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0
84
47
P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0
P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0
85
46
P1D/AN13/CTS4_1/IC03_1/MAD21_0
P56/INT08_2/DTTI1X_0/MADATA06_0
86
45
P1C/AN12/SCK4_1/IC02_1/MAD20_0
P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0
87
44
P1B/AN11/SOT4_1/IC01_1/MAD19_0
P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0
88
43
P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0
P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0
89
42
P19/AN09/SCK2_2/MAD17_0
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0
90
41
P18/AN08/SOT2_2/MAD16_0
P34/FRCK0_0/TIOB4_1/TX0_1/MADATA11_0
91
40
AVSS
P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MADATA12_0
92
39
AVRH
P36/IC02_0/SIN5_2/INT09_1/MADATA13_0
93
38
AVCC
P37/IC01_0/SOT5_2/INT10_1/MADATA14_0
94
37
P17/AN07/SIN2_2/INT04_1/MAD15_0
P38/IC00_0/SCK5_2/INT11_1/MADATA15_0
95
36
P16/AN06/SCK0_1/MAD14_0
P39/DTTI0X_0/ADTG_2
96
35
P15/AN05/SOT0_1/IC03_2/MAD13_0
P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2
97
34
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0
P3B/RTO01_0/TIOA1_1
98
33
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0
P3C/RTO02_0/TIOA2_1
99
32
P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0
P3D/RTO03_0/TIOA3_1 100
31
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3E/RTO04_0/TIOA4_1
P3F/RTO05_0/TIOA5_1
VSS
VCC
P40/TIOA0_0/RTO10_1/INT12_1
P41/TIOA1_0/RTO11_1/INT13_1
P42/TIOA2_0/RTO12_1
P43/TIOA3_0/RTO13_1/ADTG_7
P44/TIOA4_0/RTO14_1/MAD00_0
P45/TIOA5_0/RTO15_1/MAD01_0
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0
P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0
P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0
P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0
P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0
P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0
P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
VCC
P10/AN00
QFP - 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
13
D a t a S h e e t
・ BGA-112P-M04
(TOP VIEW)
1
2
3
4
5
6
7
8
A
VSS
UDP0
UDM0
USBVCC
P0E
P0B
P07
B
VCC
VSS
P52
P61
P0F
P0C
P08
TDO/
SWO
C
P50
P51
VSS
P60
P62
P0D
P09
D
P53
P54
P55
VSS
P56
P63
P0A
E
P30
P31
P32
P33
Index
F
P34
P35
P36
G
P37
P38
H
P3B
J
9
10
11
VCC
VSS
TCK/
SWCLK
VSS
TDI
P05
VSS
P20
P21
VSS
P06
P23
AN15
P22
AN14
AN12
AN11
P39
AN13
AN10
AN09
AVRH
P3A
P3D
AN08
AN07
AN06
AVSS
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
TMS/
TRSTX
SWDIO
PFBGA - 112
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
1
B1
1
79
2
C1
2
80
3
C2
3
81
4
B3
4
82
5
D1
5
83
6
D2
6
84
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
VCC
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
(PPG10_0)
MADATA00_0
P51
INT01_0
BIN0_2
SOT3_1
(SDA3_1)
RTO11_0
(PPG10_0)
MADATA01_0
P52
INT02_0
ZIN0_2
SCK3_1
(SCL3_1)
RTO12_0
(PPG12_0)
MADATA02_0
P53
SIN6_0
TIOA1_2
INT07_2
RTO13_0
(PPG12_0)
MADATA03_0
P54
SOT6_0
(SDA6_0)
TIOB1_2
RTO14_0
(PPG14_0)
MADATA04_0
I/O circuit
type
Pin state
type
-
E
H
E
H
E
H
E
H
E
I
15
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
7
D3
8
D5
7
QFP-100
85
86
8
-
-
-
-
9
-
-
-
10
-
-
-
11
-
-
-
12
-
-
-
13
-
16
CONFIDENTIAL
-
Pin Name
P55
SCK6_0
(SCL6_0)
ADTG_1
RTO15_0
(PPG14_0)
MADATA05_0
P56
I/O circuit
type
Pin state
type
E
I
E
H
E
I
E
I
E
H
E
I
E
I
INT08_2
DTTI1X_0
MADATA06_0
SIN1_0
(120pin only)
P57
SOT1_0
(SDA1_0)
MADATA07_0
P58
SCK1_0
(SCL1_0)
AIN2_0
MADATA08_0
P59
SIN7_0
RX1_1
INT09_2
BIN2_0
MADATA09_0
P5A
SOT7_0
(SDA7_0)
TX1_1
ZIN2_0
MADATA10_0
P5B
SCK7_0
(SCL7_0)
MADATA11_0
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
14
9
E1
87
-
-
-
14
-
Pin Name
P30
AIN0_0
TIOB0_1
INT03_2
MADATA07_0
(100pin only)
MADATA12_0
(120pin only)
P31
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
I
BIN0_0
15
10
E2
88
-
-
11
E3
15
-
16
89
-
-
16
-
17
12
E4
90
-
-
17
-
18
13
F1
91
-
-
-
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
18
-
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
MADATA08_0
(100pin only)
MADATA13_0
(120pin only)
P32
ZIN0_0
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
MADATA09_0
(100pin only)
MADATA14_0
(120pin only)
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MADATA10_0
(100pin only)
MADATA15_0
(120pin only)
P34
FRCK0_0
TIOB4_1
TX0_1
MADATA11_0
(100pin only)
MNALE_0
(120pin only)
17
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
19
14
F2
92
-
-
15
F3
19
-
20
93
-
-
20
-
21
16
G1
94
-
-
17
G2
21
-
22
95
-
18
F4
23
96
19
G3
24
97
-
B2
-
-
18
CONFIDENTIAL
Pin Name
P35
IC03_0
TIOB5_1
RX0_1
INT08_1
MADATA12_0
(100pin only)
MNCLE_0
(120pin only)
P36
IC02_0
SIN5_2
INT09_1
MADATA13_0
(100pin only)
MNWEX_0
(120pin only)
P37
IC01_0
SOT5_2
(SDA5_2)
INT10_1
MADATA14_0
(100pin only)
MNREX_0
(120pin only)
P38
IC00_0
SCK5_2
(SCL5_2)
INT11_1
MADATA15_0
(100pin only)
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
(PPG00_0)
TIOA0_1
RTCCO_2
SUBOUT_2
VSS
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
I
G
I
-
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
20
H1
25
98
21
H2
26
99
22
G4
27
100
23
H3
28
1
24
J2
29
2
25
26
L1
J1
30
31
3
4
27
J4
32
5
28
L5
33
6
29
K5
34
7
30
J5
35
8
-
K2
J3
H4
-
-
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
P3B
RTO01_0
(PPG00_0)
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
P3D
RTO03_0
(PPG02_0)
TIOA3_1
P3E
RTO04_0
(PPG04_0)
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
VCC
P40
TIOA0_0
RTO10_1
(PPG10_1)
INT12_1
P41
TIOA1_0
RTO11_1
(PPG10_1)
INT13_1
P42
TIOA2_0
RTO12_1
(PPG12_1)
P43
TIOA3_0
RTO13_1
(PPG12_1)
ADTG_7
VSS
VSS
VSS
I/O circuit
type
Pin state
type
G
I
G
I
G
I
G
I
G
I
-
G
H
G
H
G
I
G
I
-
19
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
31
H5
36
9
32
L6
37
10
33
34
35
L2
L4
K1
38
39
40
11
12
13
36
L3
41
14
37
K3
42
15
38
K4
43
16
39
K6
44
17
40
J6
45
18
41
L7
46
19
42
K7
47
20
20
CONFIDENTIAL
Pin Name
P44
TIOA4_0
RTO14_1
(PPG14_1)
MAD00_0
P45
TIOA5_0
RTO15_1
(PPG14_1)
MAD01_0
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
MAD02_0
P49
TIOB0_0
IC10_1
AIN0_1
SOT3_2
(SDA3_2)
MAD03_0
P4A
TIOB1_0
IC11_1
BIN0_1
SCK3_2
(SCL3_2)
MAD04_0
P4B
TIOB2_0
IC12_1
ZIN0_1
MAD05_0
I/O circuit
type
Pin state
type
G
I
G
I
D
M
D
N
B
C
E
H
E
I
E
I
E
I
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
43
H6
48
21
44
J7
49
22
45
K8
50
23
-
-
51
-
-
-
52
-
-
-
53
-
-
-
54
-
-
-
55
-
46
K9
56
24
47
L8
57
25
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
P4C
TIOB3_0
IC13_1
SCK7_1
(SCL7_1)
AIN1_2
MAD06_0
P4D
TIOB4_0
FRCK1_1
SOT7_1
(SDA7_1)
BIN1_2
MAD07_0
P4E
TIOB5_0
INT06_2
SIN7_1
ZIN1_2
MAD08_0
P70
TX0_0
TIOA4_2
P71
RX0_0
INT13_2
TIOB4_2
P72
SIN2_0
INT14_2
TIOA6_0
P73
SOT2_0
(SDA2_0)
INT15_2
TIOB6_0
P74
SCK2_0
(SCL2_0)
PE0
MD1
MD0
I/O circuit
type
Pin state
type
I*
I
I*
I
I*
H
E
I
E
H
E
H
E
H
E
I
C
P
P
D
21
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
48
L9
58
26
49
L10
59
27
50
51
L11
K11
60
61
28
29
52
J11
62
30
53
J10
63
31
-
K10
J9
-
-
54
J8
64
32
55
H10
65
33
22
CONFIDENTIAL
Pin Name
PE2
X0
PE3
X1
VSS
VCC
P10
AN00
P11
AN01
SIN1_1
INT02_1
RX1_2
FRCK0_2
MAD09_0
VSS
VSS
P12
AN02
SOT1_1
(SDA1_1)
TX1_2
IC00_2
MAD10_0
P13
AN03
SCK1_1
(SCL1_1)
RTCCO_1
SUBOUT_1
IC01_2
MAD11_0
I/O circuit
type
Pin state
type
A
A
A
B
-
F
K
F
L
-
F
K
F
K
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
56
H9
66
34
57
H7
67
35
58
G10
68
36
59
G9
69
37
60
61
62
H11
F11
G11
70
71
72
38
39
40
63
G8
73
41
64
F10
74
42
65
F9
75
43
-
H8
-
-
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
P14
AN04
SIN0_1
INT03_1
IC02_2
MAD12_0
P15
AN05
SOT0_1
(SDA0_1)
IC03_2
MAD13_0
P16
AN06
SCK0_1
(SCL0_1)
MAD14_0
P17
AN07
SIN2_2
INT04_1
MAD15_0
AVCC
AVRH
AVSS
P18
AN08
SOT2_2
(SDA2_2)
MAD16_0
P19
AN09
SCK2_2
(SCL2_2)
MAD17_0
P1A
AN10
SIN4_1
INT05_1
IC00_1
MAD18_0
VSS
I/O circuit
type
Pin state
type
F
L
F
K
F
K
F
L
-
F
K
F
K
F
L
-
23
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
66
E11
76
44
67
E10
77
45
68
F8
78
46
69
E9
79
47
70
D11
80
48
-
-
81
-
-
-
82
-
-
-
83
-
24
CONFIDENTIAL
Pin Name
P1B
AN11
SOT4_1
(SDA4_1)
IC01_1
MAD19_0
P1C
AN12
SCK4_1
(SCL4_1)
IC02_1
MAD20_0
P1D
AN13
CTS4_1
IC03_1
MAD21_0
P1E
AN14
RTS4_1
DTTI0X_1
MAD22_0
P1F
AN15
ADTG_5
FRCK0_1
MAD23_0
P28
TIOB6_2
ADTG_4
RTO05_1
(PPG04_1)
P27
TIOA6_2
INT02_2
RTO04_1
(PPG04_1)
P26
SCK2_1
(SCL2_1)
RTO03_1
(PPG02_1)
I/O circuit
type
Pin state
type
F
K
F
K
F
K
F
K
F
K
E
I
E
H
E
I
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
-
-
84
-
-
B10
C9
-
-
-
-
85
-
71
D10
49
86
-
-
-
72
E8
87
50
73
C11
88
51
74
C10
89
52
75
76
A11
A10
90
91
53
54
77
A9
92
55
78
B9
93
56
Pin Name
P25
TX1_0
SOT2_1
(SDA2_1)
RTO02_1
(PPG02_1)
VSS
VSS
P24
RX1_0
SIN2_1
INT01_2
RTO01_1
(PPG00_1)
P23
SCK0_0
(SCL0_0)
TIOA7_1
RTO00_1
(PPG00_1)
P22
SOT0_0
(SDA0_0)
TIOB7_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
CROUT_0
AIN1_1
MAD24_0
VSS
VCC
P00
TRSTX
MCSX7_0
I/O circuit
type
Pin state
type
E
I
-
E
H
E
I
E
I
E
H
E
H
E
E
E
E
P01
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
TCK
SWCLK
25
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
79
B11
94
57
80
A8
95
58
81
B8
96
59
82
C8
97
60
-
D8
-
-
83
D9
98
61
84
A7
99
62
85
B7
100
63
86
C7
101
64
26
CONFIDENTIAL
Pin Name
P02
TDI
MCSX6_0
P03
TMS
SWDIO
P04
TDO
SWO
P05
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_0
VSS
P06
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
AIN2_1
MCSX4_0
P07
TRACED2
ADTG_0
SCK4_2
(SCL4_2)
BIN2_1
MCLKOUT_0
P08
TRACED3
TIOA0_2
CTS4_2
ZIN2_1
MCSX3_0
P09
TRACECLK
TIOB0_2
RTS4_2
RTO20_1
(PPG20_1)
MCSX2_0
I/O circuit
type
Pin state
type
E
E
E
E
E
E
E
F
-
E
F
E
G
E
G
E
G
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
87
D7
102
65
88
A6
103
66
89
B6
104
67
90
C6
105
68
91
A5
106
69
-
D4
C3
-
-
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
P0A
SIN4_0
INT00_2
FRCK1_0
FRCK2_0
RTO21_1
(PPG20_1)
MCSX1_0
P0B
SOT4_0
(SDA4_0)
TIOB6_1
IC10_0
IC20_0
RTO22_1
(PPG22_1)
MCSX0_0
P0C
SCK4_0
(SCL4_0)
TIOA6_1
IC11_0
IC21_0
RTO23_1
MALE_0
P0D
RTS4_0
TIOA3_2
IC12_0
IC22_0
RTO24_1
(PPG24_1)
MDQM0_0
P0E
CTS4_0
TIOB3_2
IC13_0
IC23_0
RTO25_1
(PPG24_1)
MDQM1_0
VSS
VSS
I/O circuit
type
Pin state
type
I*
H
I*
I
I*
I
E
I
E
I
-
27
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
QFP-100
92
B5
107
70
-
-
108
-
-
-
109
-
-
-
110
-
-
-
111
-
-
-
112
-
28
CONFIDENTIAL
Pin Name
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
DTTI2X_0
DTTI2X_1
P68
SCK3_0
(SCL3_0)
TIOB7_2
INT12_2
IC20_1
RTO25_0
(PPG24_0)
P67
SOT3_0
(SDA3_0)
TIOA7_2
IC21_1
RTO24_0
(PPG24_0)
P66
SIN3_0
ADTG_8
INT11_2
IC22_1
RTO23_0
(PPG22_0)
P65
TIOB7_0
SCK5_1
(SCL5_1)
IC23_1
RTO22_0
(PPG22_0)
P64
TIOA7_0
SOT5_1
(SDA5_1)
INT10_2
FRCK2_1
RTO21_0
(PPG20_0)
I/O circuit
type
Pin state
type
E
J
G
H
G
I
G
H
G
I
G
H
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LQFP-100
Pin No
BGA-112 LQFP-120
93
D6
QFP-100
71
113
-
-
94
C5
114
72
95
B4
115
73
96
C4
116
74
97
A4
117
75
98
A3
118
76
99
100
*: 5 V tolerant I/O
-
A2
119
77
A1
120
78
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Pin Name
P63
INT03_0
SIN5_1
RX0_2
MWEX_0
RTO20_0
(PPG20_0)
P62
SCK5_0
(SCL5_0)
ADTG_3
TX0_2
MOEX_0
P61
SOT5_0
(SDA5_0)
TIOB2_2
UHCONX
P60
SIN5_0
TIOA2_2
INT15_1
MRDY_0
USBVCC
P80
UDM0
P81
UDP0
VSS
I/O circuit
type
Pin state
type
G
H
E
I
E
I
I*
H
H
O
H
O
-
29
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Module
Pin name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
Base Timer
0
Base Timer
1
Base Timer
2
30
CONFIDENTIAL
Function
A/D converter external trigger input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
LQFP- BGA- LQFP- QFP100 112 120 100
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
A7
D3
F4
C5
D11
E4
J5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
99
7
23
114
81
80
17
35
110
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
32
24
100
45
14
101
33
25
5
46
15
6
34
26
116
47
16
115
62
85
96
72
48
90
8
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
5
97
63
18
87
64
6
98
83
19
88
84
7
99
74
20
89
73
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
Base Timer
3
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
Base Timer
4
Base Timer
5
Base Timer
6
Base Timer
7
CAN 0
CAN 1
Function
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
CAN interface ch.1 TX output pin
CAN interface ch.1 RX output pin
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
89
88
71
72
13
94
14
93
54
53
J5
G4
C6
H6
E4
A5
H5
H3
J7
F1
L6
J2
C8
K8
F2
D9
B6
A6
D10
E8
F1
C5
F2
D6
J8
J10
35
27
105
48
17
106
36
28
51
49
18
52
37
29
97
50
19
98
53
104
82
54
103
81
112
86
109
111
87
108
51
18
114
52
19
113
84
12
64
85
11
63
8
100
68
21
90
69
9
1
22
91
10
2
60
23
92
61
67
66
49
50
91
72
92
71
32
31
31
D a t a S h e e t
Pin No
Module
Pin name
Debugger
SWCLK
SWDIO
External
Bus
32
CONFIDENTIAL
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
LQFP- BGA- LQFP- QFP100 112 120 100
Function
Serial wire debug interface clock input pin
Serial wire debug interface data input /
output pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
Trace CLK output pin of ETM
Trace data output pin of ETM
J-TAG test reset Input pin
External bus interface address bus
External bus interface chip select output pin
78
B9
93
56
80
A8
95
58
81
78
79
81
80
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
88
87
86
85
83
82
79
77
B8
B9
B11
B8
A8
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
A6
D7
C7
B7
D9
C8
B11
A9
96
93
94
96
95
101
97
98
99
100
92
36
37
44
45
46
47
48
49
50
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
103
102
101
100
98
97
94
92
59
56
57
59
58
64
60
61
62
63
55
9
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
66
65
64
63
61
60
57
55
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
External
Bus
MADATA0_0
MADATA1_0
MADATA2_0
MADATA3_0
MADATA4_0
MADATA5_0
MADATA6_0
MADATA7_0
MADATA8_0
MADATA9_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MDQM0_0
MDQM1_0
MALE_0
MRDY_0
MCLKOUT_0
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MOEX_0
MWEX_0
Function
External bus interface data bus
(Address / data multiplex bus)
External bus interface byte mask signal
output pin
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY input
signal
External bus interface external clock
output pin
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable signal to
control NAND Flash
External bus interface write enable signal
to control NAND Flash
External bus interface read enable signal
for SRAM
External bus interface write enable signal
for SRAM
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
90
91
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
C6
A5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
105
106
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
68
69
89
B6
104
67
96
C4
116
74
84
A7
99
62
-
-
18
-
-
-
19
-
-
-
21
-
-
-
20
-
94
C5
114
72
93
D6
113
71
33
D a t a S h e e t
Pin No
Module
Pin name
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT09_2
INT10_1
INT10_2
INT11_1
INT11_2
INT12_1
INT12_2
INT13_1
INT13_2
INT14_1
INT14_2
INT15_1
INT15_2
NMIX
34
CONFIDENTIAL
Function
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
LQFP- BGA- LQFP- QFP100 112 120 100
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
5
14
8
15
16
17
27
28
39
96
92
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
D1
F2
D5
F3
G1
G2
J4
L5
K6
C4
B5
2
97
102
3
98
85
4
63
82
113
66
14
17
69
15
89
75
16
88
50
5
19
8
20
11
21
112
22
110
32
108
33
52
44
53
116
54
107
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
83
92
86
93
94
95
5
6
17
74
70
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
-
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
-
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
88
87
86
85
84
83
82
81
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
-
35
D a t a S h e e t
Pin No
Module
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
36
CONFIDENTIAL
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
LQFP- BGA- LQFP- QFP100 112 120 100
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
-
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
-
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
41
42
44
45
46
47
48
49
50
2
3
4
5
6
7
8
9
10
11
12
13
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
-
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
GPIO
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
SIN0_0
SIN0_1
Multifunction
Serial
0
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
SIN1_0
SIN1_1
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
Function
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port E
Multi-function serial interface ch.0 input pin
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.0 clock I/O
pin.
This pin operates as SCK0 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SCL0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1 input pin
Multi-function serial interface ch.1 output
pin.
This pin operates as SOT1 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA1 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.1 clock I/O
pin.
This pin operates as SCK1 when it is used in
a CSIO (operation modes 4) and as SCL1
when it is used in an I2C (operation mode 4).
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
96
95
94
93
98
99
46
48
49
73
56
C4
B4
C5
D6
A3
A2
K9
L9
L10
C11
H9
116
115
114
113
112
111
110
109
108
51
52
53
54
55
118
119
56
58
59
88
66
74
73
72
71
76
77
24
26
27
51
34
72
E8
87
50
57
H7
67
35
71
D10
86
49
58
G10
68
36
53
J10
8
63
31
-
-
9
-
54
J8
64
32
-
-
10
-
55
H10
65
33
37
D a t a S h e e t
Pin No.
Module
Pin name
Multifunction
Serial
2
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
Multifunction
Serial
3
38
CONFIDENTIAL
SIN3_1
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
LQFP- BGA- LQFP- QFP100 112 120 100
Function
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output
pin.
This pin operates as SOT2 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA2 when it is used in an I2C
(operation mode 4).
59
G9
53
85
69
37
-
-
54
-
-
-
84
-
63
G8
73
41
-
-
55
-
Multi-function serial interface ch.2 clock I/O
pin.
This pin operates as SCK2 when it is used in
a CSIO (operation modes 2) and as SCL2
when it is used in an I2C (operation mode 4).
-
-
83
-
64
F10
74
42
-
-
110
-
Multi-function serial interface ch.3 input pin
2
C1
2
80
39
K6
44
17
-
-
109
-
3
C2
3
81
40
J6
45
18
-
-
108
-
4
B3
4
82
41
L7
46
19
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA3 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.3 clock I/O
pin.
This pin operates as SCK3 when it is used in
a CSIO (operation modes 2) and as SCL3
when it is used in an I2C (operation mode 4).
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
Multifunction
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Multifunction
Serial
5
Function
87
65
82
D7
F9
C8
102
75
97
65
43
60
Multi-function serial interface ch.4 output
pin.
This pin operates as SOT4 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA4 when it is used in an I2C
(operation mode 4).
88
A6
103
66
66
E11
76
44
83
D9
98
61
Multi-function serial interface ch.4 clock I/O
pin.
This pin operates as SCK4 when it is used in
a CSIO (operation modes 2) and as SCL4
when it is used in an I2C (operation mode 4).
89
B6
104
67
67
E10
77
45
84
A7
99
62
90
69
86
91
68
85
96
93
15
C6
E9
C7
A5
F8
B7
C4
D6
F3
105
79
101
106
78
100
116
113
20
68
47
64
69
46
63
74
93
93
Multi-function serial interface ch.5 output
pin.
This pin operates as SOT5 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA5 when it is used in an I2C
(operation mode 4).
95
B4
115
73
-
-
112
-
16
G1
21
94
Multi-function serial interface ch.5 clock I/O
pin.
This pin operates as SCK5 when it is used in
a CSIO (operation modes 2) and as SCL5
when it is used in an I2C (operation mode 4).
94
C5
114
72
-
-
111
-
17
G2
22
95
Multi-function serial interface ch.4 input pin
Multi-function serial interface ch.4 RTS
output pin
Multi-function serial interface ch.4 CTS
input pin
Multi-function serial interface ch.5 input pin
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
39
D a t a S h e e t
Pin No
Module
Pin name
Multifunction
Serial
6
SIN6_0
SIN6_1
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multifunction
Serial
7
SIN7_0
SIN7_1
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
40
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120 100
Function
Multi-function serial interface ch.6 input pin
Multi-function serial interface ch.6 output
pin.
This pin operates as SOT6 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA6 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.6 clock I/O
pin.
This pin operates as SCK6 when it is used in
a CSIO (operation modes 2) and as SCL6
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.7 input pin
Multi-function serial interface ch.7 output
pin.
This pin operates as SOT7 when it is used in
a UART/CSIO/LIN (operation modes 0 to 3)
and as SDA7 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.7 clock I/O
pin.
This pin operates as SCK7 when it is used in
a CSIO (operation modes 2) and as SCL7
when it is used in an I2C (operation mode 4).
5
12
D1
E4
5
17
83
90
6
D2
6
84
11
E3
16
89
7
D3
7
85
10
E2
15
88
45
K8
11
50
23
-
-
12
-
44
J7
49
22
-
-
13
-
43
H6
48
21
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
Pin name
Function
Multifunction
Timer
0
DTTI0X_0
Input signal controlling wave form generator
outputs RTO00 to RTO05 of Multi-function
timer 0.
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
16-bit free-run timer ch.0 external clock
input pin
16-bit input capture ch.0 input pin of
Multi-function timer 0.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
Wave form generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is used in
PPG0 output modes.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120
100
18
F4
23
96
69
E9
79
47
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
F1
D11
J10
G2
F9
J8
G1
E11
H10
F3
E10
H9
F2
F8
H7
18
80
63
22
75
64
21
76
65
20
77
66
19
78
67
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
19
G3
24
97
-
-
86
-
20
H1
25
98
-
-
85
-
21
H2
26
99
-
-
84
-
22
G4
27
100
-
-
83
-
23
H3
28
1
-
-
82
-
24
J2
29
2
-
-
81
-
41
D a t a S h e e t
Pin No
LQFP- BGA- LQFP- QFP100 112 120
100
Module
Pin name
Function
Multifunction
Timer
1
DTTI1X_0
Input signal controlling wave form generator
outputs RTO10 to RTO15 of Multi-function
timer 1.
42
CONFIDENTIAL
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
16-bit free-run timer ch.1 external clock
input pin
16-bit input capture ch.1 input pin of
Multi-function timer 1.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
RTO14_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output pin of
Multi-function timer 1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
8
D5
8
86
39
K6
44
17
87
44
88
40
89
41
90
42
91
43
D7
J7
A6
J6
B6
L7
C6
K7
A5
H6
102
49
103
45
104
46
105
47
106
48
65
22
66
18
67
19
68
20
69
21
2
C1
2
80
27
J4
32
5
3
C2
3
81
28
L5
33
6
4
B3
4
82
29
K5
34
7
5
D1
5
83
30
J5
35
8
6
D2
6
84
31
H5
36
9
7
D3
7
85
32
L6
37
10
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
LQFP- BGA- LQFP- QFP100 112 120
100
Module
Pin name
Function
Multifunction
Timer
2
DTTI2X_0
Input signal controlling wave form generator
outputs RTO20 to RTO25 of Multi-function
timer 2.
92
B5
107
70
92
B5
107
70
16-bit free-run timer ch.2 external clock input
pin
87
88
89
90
91
-
D7
A6
B6
C6
A5
-
102
112
103
108
104
109
105
110
106
111
65
66
67
68
69
-
-
-
113
-
86
C7
101
64
-
-
112
-
87
D7
102
65
-
-
111
-
88
A6
103
66
-
-
110
-
89
B6
104
67
-
-
109
-
90
C6
105
68
-
-
108
-
91
A5
106
69
DTTI2X_1
FRCK2_0
FRCK2_1
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
IC23_0
IC23_1
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
16-bit input capture ch.2 input pin of
Multi-function timer 2.
ICxx describes channel number.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
RTO24_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Wave form generator output pin of
Multi-function timer 2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
43
D a t a S h e e t
Pin No
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
Function
9
E1
14
87
40
J6
45
18
AIN0_2
2
C1
2
80
BIN0_0
10
E2
15
88
41
L7
46
19
3
C2
3
81
AIN0_1
BIN0_1
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
BIN0_2
ZIN0_0
ZIN0_1
QPRC ch.0 ZIN input pin
ZIN0_2
Quadrature
Position/
Revolution
Counter
1
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
Quadrature
Position/
Revolution
Counter
2
AIN2_0
AIN2_1
BIN2_0
BIN2_1
ZIN2_0
ZIN2_1
Real-time
clock
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
QPRC ch.2 ZIN input pin
RTCCO_0
RTCCO_1
0.5 seconds pulse output pin of Real-time
clock
CONFIDENTIAL
E3
16
89
K7
47
20
4
B3
4
82
74
C10
89
52
43
H6
48
21
73
C11
88
51
44
J7
49
22
72
E8
87
50
45
K8
50
23
-
-
10
-
83
D9
98
61
-
-
11
-
84
A7
99
62
-
-
12
-
85
B7
100
63
92
B5
107
70
55
H10
65
33
19
G3
24
97
SUBOUT_0
92
B5
107
70
55
H10
65
33
19
G3
24
97
98
99
95
A3
A2
B4
118
119
115
76
77
73
Sub clock output pin
SUBOUT_2
44
11
42
RTCCO_2
SUBOUT_1
USB
LQFP- BGA- LQFP- QFP100 112 120
100
UDM0
UDP0
UHCONX
USB function/host D – pin
USB function/host D + pin
USB external pull-up control pin
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin No
Module
RESET
Pin name
INITX
Mode
MD0
MD1
POWER
GND
CLOCK
Analog
POWER
Analog
GND
C pin
VCC
VCC
VCC
VCC
VCC
USBVCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
X0
X0A
X1
X1A
CROUT_0
CROUT_1
AVCC
AVRH
AVSS
C
Function
External Reset Input.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L" must be
input. During serial programming to Flash
memory, MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash memory,
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
38
K4
43
16
47
L8
57
25
46
K9
56
24
1
26
35
51
76
97
25
34
50
75
100
48
36
49
37
74
92
60
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
L9
L3
L10
K3
C10
B5
H11
1
31
40
61
91
117
30
39
60
90
120
58
41
59
42
89
107
70
79
4
13
29
54
75
61
F11
71
39
A/D converter GND pin
62
G11
72
40
Power stabilization capacity pin
33
L2
38
11
Built-in high-speed CR-osc clock output port
A/D converter analog power pin
A/D converter analog reference voltage input
pin
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
LQFP- BGA- LQFP- QFP100 112 120
100
3
12
28
53
78
26
14
27
15
52
70
38
45
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
・ Oscillation feedback
resistor
: Approximately 1 MΩ
・ With Standby mode control
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
Clock input
Feedback
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
・ CMOS level hysteresis
input
・ Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
46
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Digital input
・ Open drain output
・ CMOS level hysteresis
input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
Clock input
Feedback
When the sub oscillation is
selected.
・ Oscillation feedback
resistor
: Approximately 5 MΩ
・ With Standby mode control
When the GPIO is selected.
・ CMOS level output.
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50 kΩ
・ IOH = -4 mA, IOL= 4 mA
resistor
Standby mode Control
Digital input
Standby mode Control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
47
D a t a S h e e t
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
・ +B input is available
E
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
F
P-ch
P-ch
N-ch
R
Digital output
Digital output
Pull-up resistor control
・ CMOS level output
・ CMOS level hysteresis
input
・ With input control
・ Analog input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50 kΩ
・ IOH = -4 mA, IOL = 4 mA
・ When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
・ +B input is available
Digital input
Standby mode Control
Analog input
Input control
48
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Type
Circuit
Remarks
G
P-ch
P-ch
Digital output
N-ch
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ With standby mode control
・ Pull-up resistor
: Approximately 50 kΩ
・ IOH= -12 mA, IOL= 12 mA
・ +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
H
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select the
USB I/O / GPIO function.
When the USB I/O is selected.
・ Full-speed, Low-speed
control
UDP output
UDP/Pxx
USB Full-speed/Low-speed control
UDP input
Differential
UDM/Pxx
Differential input
USB/GPIO select
UDM input
When the GPIO is selected.
・ CMOS level output
・ CMOS level hysteresis
input
・ With standby mode control
・ IOH= -20.5 mA,
IOL= 18.5 mA
UDM output
USB Digital input/output direction
GPIO Digital input
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
49
D a t a S h e e t
Type
Circuit
Remarks
・ CMOS level output
・ CMOS level hysteresis
input
・ With pull-up resistor
control
・ 5 V tolerant
・ With standby mode control
・ IOH = -4 mA, IOL = 4 mA
・ Available to control of PZR
registers.
・ When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
I
P-ch
P-ch
N-ch
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode Control
J
CMOS level hysteresis input
Mode input
50
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
・Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
・Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
・Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
・Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
51
D a t a S h e e t
・Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
・Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
・Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
・Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
・Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion recommends the solder reflow method, and has
established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
52
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
・Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion packages semiconductor devices in highly moisture-resistant aluminum
laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags
for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
・Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
・Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
53
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
54
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the
fluctuation is within the recommended operating conditions of the VCC power supply voltage.
As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation
in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not
exceed 10% of the VCC value in the recommended operating conditions, and the transient
fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching
the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A
pin should be kept open.
・Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
2
Handling when using Multi-function serial pin as I C pin
If it is using multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C
bus system with power OFF.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
55
D a t a S h e e t
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the
regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor
of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation
due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the
capacitor that meets the specifications in the operating conditions to use by evaluating the
temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC → USBVCC
VCC → AVCC → AVRH
Turning off : USBVCC → VCC
AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant
I/O.
56
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Block Diagram
MB9BF512N/R, MB9BF514N/R, MB9BF515N/R, MB9BF516N/R
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
SRAM0
8/16/24/32Kbyte
Cortex-M3 Core
144MHz(Max)
I
Multi-layer AHB (Max 144MHz)
TRSTX,TCK,
TDI,TMS
TDO
D
MPU NVIC
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
SRAM1
8/16/24/32Kbyte
MainFlash
128Kbyte/
256Kbyte/
384Kbyte/
512Kbyte
MainFlash I/F
Trace Buffer
(16Kbyte)
Security
WorkFlash
32Kbyte
WorkFlash I/F
USB 2.0
(Host/
Func)
USBVCC
PHY
UDP0,UDM0
UHCONX
DMAC
8ch.
CSV
CLK
X0
X1
X0A
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
CR
100kHz
CROUT
AVCC,
AVSS, AVRH
CAN
TX0,
RX0
CAN
TX1,
RX1
12-bit A/D Converter × 3
MAD[24:00]
MADATA[15:00]
Unit 0
External Bus I/F
AN[15:00]
MRDY
Unit 1
ADTG[8:0]
Unit 2
AIN[2:0]
QPRC
3ch.
BIN[2:0]
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
16-bit Input Capture
4ch.
FRCK[2:0]
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
USB Clock Ctrl
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[7:0]
Base Timer
16-bit 8ch./
32-bit 4ch.
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[7:0]
CAN Prescaler
LVD Ctrl
IRQ-Monitor
Power On
Reset
LVD
Regulator
C
CRC
Accelerator
RTCCO
SUBOUT
Real-Time Clock
Watch Counter
External Interrupt
Controller
16-pin + NMI
INT[15:00]
NMIX
MODE-Ctrl
GPIO
Waveform Generator
3ch.
16-bit PPG
3ch.
PLL
MCSX[7:0],
MALE,
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MD[1:0]
PIN-Function-Ctrl
P0[F:0],
P1[F:0],
.
.
.
Px[x:0]
Multi-function Serial I/F
8ch.
(with FIFO ch.4-ch.7)
HW flow control(ch.4)
Multi-function Timer x 3
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
Memory Size
See "Product Lineup" of " Memory size" to confirm the memory size.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
57
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4006_4000
0xFFFF_FFFF
Reserved
Cortex-M3 Private
Peripherals
0x7000_0000
External Device
Area
Reserved
0x4400_0000
0x4200_0000
0x4000_0000
0x4006_2000
CAN ch.0
0x4006_1000
Reserved
0x4006_0000
DMAC
0x4005_0000
USB ch.0
0x4004_0000
Reserved
0x6000_0000
CAN ch.1
Reserved
0xE010_0000
0xE000_0000
0x4006_3000
32Mbyte
Bit band alias
Peripherals
0x4003_F000
EXT-bus I/F
0x4003_C000
Reserved
0x4003_B000
RTC
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4003_8000
0x4003_6000
0x4003_5000
LVD Ctrl
0x4003_4000
Reserved
0x4003_7000
0x4003_3000
GPIO
0x4003_2000
Reserved
0x4003_1000
Int-Req. Read
0x4003_0000
EXTI
0x4002_F000
Reserved
0x4002_E000
32Mbyte
Bit band alias
0x4002_8000
0x2400_0000
0x2200_0000
MFS
CAN Prescaler
USB Clock Ctrl
Reserved
CR Trim
Reserved
0x4002_7000
A/DC
0x200E_1000
Reserved
0x4002_6000
QPRC
0x200E_0000
WorkFlash I/F
0x4002_5000
Base Timer
0x200C_0000
WorkFlash
0x4002_4000
PPG
0x2008_0000
Reserved
0x4002_3000
0x2000_0000
SRAM1
0x4002_2000
Reserved
MFT unit2
See the next page
"Memory Map (2), (3)"
SRAM0
0x4002_1000
MFT unit1
0x1FFF_0000
0x4002_0000
MFT unit0
for the memory size
details.
0x0010_2000
0x0010_0000
Reserved
0x4001_6000
Security/CR Trim
0x4001_5000
0x4001_3000
MainFlash
0x0000_0000
SW WDT
0x4001_1000
HW WDT
0x4001_0000
Clock/Reset
0x4000_0000
CONFIDENTIAL
Reserved
0x4001_2000
0x4000_1000
58
Reserved
Dual Timer
Reserved
MainFlash I/F
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Memory Map (2)
MB9BF515N/R
MB9BF516N/R
0x200E_0000
0x200E_0000
Reserved
0x200C_8000
WorkFlash
32Kbyte
0x200C_8000
WorkFlash
32Kbyte
Reserved
SA0-3 (8KBx4)
SA0-3 (8KBx4)
0x200C_0000
0x200C_0000
Reserved
0x2000_8000
Reserved
0x2000_6000
SRAM1
32Kbyte
SRAM1
24Kbyte
0x2000_0000
0x2000_0000
SRAM0
24Kbyte
SRAM0
32Kbyte
0x1FFF_A000
0x1FFF_8000
Reserved
Reserved
0x0010_2000
0x0010_2000
0x0010_1000
CR trimming
0x0010_1000
CR trimming
0x0010_0000
Security
0x0010_0000
Security
Reserved
0x0008_0000
Reserved
0x0006_0000
SA10-15 (64KBx6)
MainFlash
512Kbyte
SA10-13 (64KBx4)
MainFlash
384Kbyte
SA8-9 (48KBx2)
0x0000_0000
SA4-7 (8KBx4)
SA8-9 (48KBx2)
0x0000_0000
SA4-7 (8KBx4)
*: See "MB9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
59
D a t a S h e e t
Memory Map (3)
MB9BF514N/R
MB9BF512N/R
0x200E_0000
0x200E_0000
Reserved
0x200C_8000
WorkFlash
32Kbyte
0x200C_8000
WorkFlash
32Kbyte
Reserved
SA0-3 (8KBx4)
SA0-3 (8KBx4)
0x200C_0000
0x200C_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
SRAM1
16Kbyte
0x2000_0000
0x2000_0000
SRAM0
16Kbyte
0x1FFF_E000
SRAM1
8Kbyte
SRAM0
8Kbyte
0x1FFF_C000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
Reserved
0x0004_0000
SA10-11 (64KBx2)
SA4-7 (8KBx4)
SA8-9 (48KBx2)
0x0000_0000
SA4-7 (8KBx4)
MainFlash
128Kbyte
0x0000_0000
MainFlash
256Kbyte
SA8-9 (48KBx2)
0x0002_0000
*: See "MB9B510R/410R/310R/110R Series Flash programming Manual" for sector structure of Flash.
60
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
AHB
APB0
Peripherals
MainFlash I/F register
Reserved
Software Watchdog timer
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Multi-function timer unit2
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low Voltage Detector
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
0x4006_2000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
CAN ch.1
0x4006_4000
0x41FF_FFFF
Reserved
0x200E_0000
0x200E_FFFF
WorkFlash I/F register
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
APB1
APB2
AHB
Base Timer
Quadrature Position/Revolution Counter
USB clock generator
CAN prescaler
Reserved
CAN ch.0
61
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
・ INITX=0
This is the period when the INITX pin is the "L" level.
・ INITX=1
This is the period when the INITX pin is the "H" level.
・ SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
・ SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
・ Input enabled
Indicates that the input function can be used.
・ Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
・ Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
・ Setting disabled
Indicates that the setting is disabled.
・ Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
・ Analog input is enabled
Indicates that the analog input is enabled.
・ Trace output
Indicates that the trace function can be used.
62
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
LIST OF PIN STATUS
Pin
status
type
A
B
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low voltage
internal reset sleep mode
state
state
detection state
state
state
Power supply
Function group Power supply
Power supply stable
Power supply stable
unstable
stable
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
Input
Input
Input
Input
Input
Input
Main crystal
enabled
enabled
enabled
enabled
enabled
enabled
oscillator input
pin
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
Main crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
INITX input pin
Pull-up/
Input
enabled
Input enabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
GPIO
selected
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Trace selected
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected, or other
than above
resource selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
C
D
E
F
Mode input pin
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
Trace output
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
63
D a t a S h e e t
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low voltage
internal reset sleep mode
state
state
detection state
state
state
Pin
Power supply
status Function group Power supply
Power supply stable
Power supply stable
unstable
stable
type
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
Trace selected
Setting
Setting
Setting
Maintain
Maintain
Trace output
disabled
disabled
disabled
previous
previous
state
state
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
G
or other than
Input
Input
Internal
above resource
enabled
enabled
input fixed
selected
at "0"
External interrupt
Setting
Setting
Setting
Maintain
Maintain
Maintain
enabled selected
disabled
disabled
disabled
previous
previous
previous
state
state
state
H
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
or other than
Input
Input
Internal
above resource
enabled
enabled
input fixed
selected
at "0"
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Maintain
Maintain
Hi-Z/
resource selected
Input
Input
previous
previous
Internal
I
enabled
enabled
state
state
input fixed
at "0"
NMIX selected
Setting
Setting
Setting
Maintain
Maintain
Maintain
disabled
disabled
disabled
previous
previous
previous
state
state
state
J
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
or other than
Input
Input
Internal
above resource
enabled
enabled
input fixed
selected
at "0"
64
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low voltage
internal reset sleep mode
state
state
detection state
state
state
Pin
Power supply
status Function group Power supply
Power supply stable
Power supply stable
unstable
stable
type
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
Analog input
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
selected
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at "0"/
at "0"/
at "0"/
at "0"/
at "0"/
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
K
enabled
enabled
enabled
enabled
enabled
GPIO selected,
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
or other than
disabled
disabled
disabled
previous
previous
Internal
above resource
state
state
input fixed
selected
at "0"
External interrupt
Setting
Setting
Setting
Maintain
Maintain
Maintain
enabled selected
disabled
disabled
disabled
previous
previous
previous
state
state
state
Analog input
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
selected
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at "0"/
at "0"/
at "0"/
at "0"/
at "0"/
L
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
GPIO selected,
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
or other than
disabled
disabled
disabled
previous
previous
Internal
above resource
state
state
input fixed
selected
at "0"
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
M
Sub crystal
oscillator input
pin
Input
enabled
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
65
D a t a S h e e t
Pin
status
type
N
Power-on reset
Device
Run mode
INITX input
Timer mode or sleep mode
or low voltage
internal reset or sleep
state
state
detection state
state
mode state
Power
Function group Power supply
Power supply stable
supply
Power supply stable
unstable
stable
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous state Internal input
state
fixed at "0"
Sub crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
GPIO selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
Maintain
previous
state
USB I/O pin
Setting
disabled
Setting
disabled
Setting
disabled
Mode input pin
Input
enabled
Input
enabled
GPIO selected
Setting
disabled
Setting
disabled
O
Maintain
previous
state/ Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Maintain
previous state
Maintain
previous
state/ Hi-Z at
oscillation
stop*2/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Maintain
previous
state
Hi-Z at
transmission/
Input
enabled/
Internal input
fixed at "0" at
reception
Hi-Z at
transmission/
Input
enabled/
Internal input
fixed at "0" at
reception
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Input enabled
P
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, and Stop mode.
*2: Oscillation is stopped at Stop mode.
66
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MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
Power supply voltage (for USB)*1, * 3
Analog power supply voltage*1, *4
Analog reference voltage*1, *4
Symbol
Min
Max
Unit
Remarks
VSS + 6.5
V
VSS + 6.5
V
VSS + 6.5
V
VSS + 6.5
V
Except for
VCC + 0.5
VSS - 0.5
V
(≤ 6.5 V)
USB pin
Input voltage*1
VI
USBVCC + 0.5
VSS - 0.5
V
USB pin
(≤ 6.5 V)
VSS - 0.5
VSS + 6.5
V
5 V tolerant
AVCC + 0.5
1
Analog pin input voltage*
VIA
VSS - 0.5
V
(≤ 6.5 V)
VCC + 0.5
Output voltage*1
VO
VSS - 0.5
V
(≤ 6.5 V)
Clamp maximum current
ICLAMP
-2
+2
mA *8
Clamp total maximum current
Σ[ICLAMP]
+20
mA *8
10
mA 4 mA type
L level maximum output current*5
IOL
20
mA 12 mA type
39
mA P80, P81
4
mA 4 mA type
L level average output current*6
IOLAV
12
mA 12 mA type
18.5
mA P80, P81
L level total maximum output current
∑IOL
100
mA
7
L level total average output current*
∑IOLAV
50
mA
- 10
mA 4 mA type
H level maximum output current*5
IOH
- 20
mA 12 mA type
- 39
mA P80, P81
-4
mA 4 mA type
H level average output current*6
IOHAV
- 12
mA 12 mA type
- 20.5
mA P80, P81
H level total maximum output current
∑IOH
- 100
mA
H level total average output current*7
∑IOHAV
- 50
mA
Power consumption
PD
1000
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that V SS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is the peak value for a single pin.
*6: The average output is the average current for a single pin over a period of 100 ms.
*7: The total average output current is the average current for all pins over a period of 100 ms.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
VCC
USBVCC
AVCC
AVRH
Rating
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS - 0.5
67
D a t a S h e e t
*8:
・
・
・
・
・
・
・
・
See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
Use within recommended operating conditions.
Use at DC voltage (current) the +B input.
The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.
Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.
The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
68
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MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
2.
Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Power supply voltage
Power supply voltage for
USB ch.0
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
Operating
temperature
FPT-100P-M23
FPT-120P-M37
Symbol
Conditions
VCC
-
USBVCC
-
Value
Min
Max
4
2.7*
Unit
AVCC
AVRH
-
2.7
2.7
5.5
3.6
(≤ VCC)
5.5
(≤ VCC)
5.5
AVCC
CS
-
1
10
μF
TA
When
mounted on
four-layer
PCB
- 40
+ 85
°C
3.0
2.7
Remarks
V
V
V
AVCC = VCC
For built-in
regulator*3
*1
V
*2
FPT-100P-M03
TA
- 40
+ 85
°C
BGA-112P-M04
*1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3 : See " · C Pin" in "Handling Devices" for the connection of the smoothing capacitor.
*4 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
69
D a t a S h e e t
3.
DC Characteristics
(1) Current Rating
(VCC = AVCC = USBVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter Symbol
Pin
name
PLL
Rrun mode
Run
mode
current
ICC
High-speed
CR
Rrun mode
VCC
Sub
Rrun mode
Low-speed
CR
Run mode
Sleep
mode
current
ICCS
Value
Unit Remarks
Typ*3 Max*4
Conditions
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
CPU : 144 MHz,
Peripheral : 72 MHz,
Main Flash 2 Wait
TraceBuffer : ON
FRWTR.RWT = 10
FSYNDN.SD = 000
FBFCR.BE = 1
CPU : 72 MHz,
Peripheral : 72 MHz,
Main Flash 0 Wait
TraceBuffer : OFF
FRWTR.RWT = 00
FSYNDN.SD = 000
FBFCR.BE = 0
CPU/ Peripheral :
4 MHz*2
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral : 32 kHz
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
CPU/ Peripheral :
100 kHz
Main Flash 0 Wait
FRWTR.RWT = 00
FSYNDN.SD = 000
85
117
mA *1, *5
52
70
mA *1, *5
5
17
mA *1
1.3
14
mA *1, *6
1.3
14
mA *1
Peripheral : 72 MHz
28
43
mA *1, *5
Peripheral : 4 MHz*2
3
16
mA *1
Peripheral : 32 kHz
1
14
mA *1, *6
Peripheral : 100 kHz
1
14
mA *1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
70
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MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Pin
name
Parameter Symbol
Timer
mode
current
Main
TIMER
mode
ICCT
VCC
Stop
mode
current
ICCH
Value
Unit Remarks
Typ*2 Max*2
Conditions
Sub
TIMER
mode
Stop mode
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
3.2
6
mA
*1, *3
-
15
mA
*1, *3
0.9
3
mA
*1, *4
-
12
mA
*1, *4
0.8
3
mA
*1
-
12
mA
*1
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Low voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
VCC = 5.5 V
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Value
Typ
Max
MainFlash
11.4
13.1
At Write/Erase
ICCFLASH
VCC
WorkFlash
11.4
13.1
At Write/Erase
*: The current at which to write or erase Flash memory, I CCFLASH is added to ICC.
Flash memory
write/erase
current
Unit
Remarks
mA
*
mA
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Value
Typ
Max
Unit
At 1unit
operation
0.47
0.62
mA
At stop
0.06
25
μA
At 1unit
operation
AVRH=5.5 V
1.1
1.96
mA
At stop
0.06
4
μA
Conditions
Remarks
71
D a t a S h e e t
(2) Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter Symbol Pin name
H level input
voltage
(hysteresis
input)
VIHS
L level input
voltage
(hysteresis
input)
VILS
H level
output voltage
72
CONFIDENTIAL
VOH
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
Min
Value
Typ
Max
-
VCC × 0.8
-
VCC + 0.3
V
-
VCC × 0.8
-
VSS + 5.5
V
-
VSS - 0.3
-
VCC × 0.2
V
-
VSS - 0.3
-
VCC × 0.2
V
VCC - 0.5
-
VCC
V
VCC - 0.5
-
VCC
V
USBVCC 0.4
-
USBVCC
V
Conditions
VCC ≥ 4.5 V
IOH = - 4 mA
4 mA type
VCC < 4.5 V
IOH = - 2 mA
VCC ≥ 4.5 V
IOH = - 12 mA
12 mA type
VCC < 4.5 V
IOH = - 8 mA
USBVCC ≥ 4.5 V
IOH = - 20.5 mA
P80, P81
USBVCC < 4.5 V
IOH = - 13.0 mA
Unit Remarks
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Parameter
L level
output voltage
Input leak
current
Pull-up
resistance
value
Input
capacitance
Symbol
VOL
Pin
name
Max
VSS
-
0.4
V
VSS
-
0.4
V
VSS
-
0.4
V
-
-5
-
+5
μA
VCC ≥ 4.5 V
25
50
100
VCC < 4.5 V
30
80
200
-
-
5
15
VCC ≥ 4.5 V
IOL = 4 mA
4 mA type
VCC < 4.5 V
IOL = 2 mA
VCC ≥ 4.5 V
IOL = 12 mA
12 mA type
VCC < 4.5 V
IOL = 8 mA
USBVCC ≥ 4.5 V
IOL = 18.5 mA
P80, P81
USBVCC < 4.5 V
IOL = 10.5 mA
IIL
-
RPU
Pull-up pin
CIN
Other than
VCC,
USBVCC,
VSS,
AVCC,
AVSS,
AVRH
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Min
Value
Typ
Conditions
Unit Remarks
kΩ
pF
73
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
name
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
PWH/tCYLH
PWL/tCYLH
Value
Min
Max
4
4
4
4
20.83
50
48
20
48
20
250
250
Unit
Remarks
When crystal oscillator
is connected
Input frequency
fCH
When using external
MHz
clock
X0
When using external
Input clock cycle
tCYLH
ns
X1
clock
Input clock pulse
When using external
45
55
%
width
clock
Input clock rise
tCF,
When using external
5
ns
time and fall time
tCR
clock
fCM
144
MHz Master clock
Base clock
fCC
144
MHz
(HCLK/FCLK)
Internal operating
clock*1 frequency
fCP0
72
MHz APB0 bus clock*2
fCP1
72
MHz APB1 bus clock*2
fCP2
72
MHz APB2 bus clock*2
Base clock
tCYCC
6.94
ns
(HCLK/FCLK)
Internal operating
t
13.8
ns
APB0 bus clock*2
CYCP0
clock*1 cycle time
tCYCP1
13.8
ns
APB1 bus clock*2
tCYCP2
13.8
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "■ Block Diagram" in this data sheet.
MHz
X0
74
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Conditions
name
Unit
1/ tCYLL
X0A
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
(3) Internal CR Oscillation Characteristics
・ High-speed Internal CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
TA = + 25°C
Clock frequency
fCRH
TA =
0°C to + 70°C
TA =
- 40°C to + 85°C
TA =
- 40°C to + 85°C
Min
Value
Typ
Max
3.96
4
4.04
3.84
4
4.16
3.8
4
4.2
3
4
5
Unit
Remarks
When trimming*1
MHz
When not trimming
Frequency
tCRWT
90
μs *2
stability time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
・ Low-speed Internal CR
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
Conditions
fCRL
-
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
75
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB clock frequency*3
Value
Min Typ Max
Unit
Remarks
tLOCK
100
-
-
μs
fPLLI
fPLLO
fCLKPLL
4
13
200
-
-
16
75
300
40
MHz
multiple
MHz
MHz
fCLKSPLL
-
-
48
MHz
After the M frequency
division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3: For more information about USB clock, see "CHAPTER 2-2: USB Clock Generation" in "FM3 Family
PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Min Typ Max
Unit
Remarks
PLL oscillation stabilization wait time*1
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiple rate
50
71
multiple
PLL macro oscillation clock frequency
fPLLO
190
300
MHz
Main PLL clock frequency*2
fCLKPLL
40
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
USB PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
76
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Reset input time
Symbol
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply rising time
tVCCR
Power supply shut down time
Time until releasing
Power-on reset
tOFF
Pin
name
Value
Max
0
-
ms
1
-
ms
0.57
0.76
ms
VCC
tPRT
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
tVCCR
tPRT
Internal reset
CPU Operation
Reset active
tOFF
Release
start
Glossary
・ VCC_minimum : Minimum VCC of recommended operating conditions
・ VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "7. Low-voltage Detection Characteristics"
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
77
D a t a S h e e t
(7) External Bus Timing
・ External bus clock output characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Output frequency
Symbol
Pin name
Conditions
tCYCLE
MCLKOUT*1
VCC ≥ 4.5 V
VCC < 4.5 V
Value
Min
Max
Unit
50*2
32*3
MHz
MHz
-
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHPATER 12: External Bus Interface" in "FM3
Family PERIPHERAL MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more
than 4.
*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more
than 4.
MCLKOUT
・ External bus signal input/output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Signal input characteristics
Signal output characteristics
78
CONFIDENTIAL
Symbol
Conditions
VIH
VIL
VOH
-
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ Separate Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5 V
MOEX
tOEW
MOEX
MCLK×n-3
Min pulse width
VCC < 4.5 V
VCC ≥ 4.5 V
-9
MCSX ↓ → Address
MCSX[7:0]
tCSL – AV
output delay time
MAD[24:0]
VCC < 4.5 V
-12
VCC ≥ 4.5 V
MOEX ↑ →
MOEX
tOEH - AX
0
Address hold time
MAD[24:0]
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK×m-9
MCSX ↓ →
tCSL - OEL
MOEX ↓ delay time
VCC < 4.5 V MCLK×m-12
MOEX
MCSX[7:0]
VCC ≥ 4.5 V
MOEX ↑ →
tOEH - CSH
0
MCSX ↑ time
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK×m-9
MCSX ↓ →
MCSX
tCSL - RDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 4.5 V MCLK×m-12
VCC ≥ 4.5 V
20
Data set up →
MOEX
tDS - OE
MOEX ↑ time
MADATA[15:0]
VCC < 4.5 V
38
VCC ≥ 4.5 V
MOEX ↑ →
MOEX
tDH - OE
0
Data hold time
MADATA[15:0]
VCC < 4.5 V
VCC ≥ 4.5 V
MWEX
tWEW
MWEX
MCLK×n-3
Min pulse width
VCC < 4.5 V
VCC ≥ 4.5 V
MWEX ↑ → Address
MWEX
tWEH - AX
0
output delay time
MAD[24:0]
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK×n-9
MCSX ↓ →
tCSL - WEL
MWEX ↓ delay time
VCC < 4.5 V MCLK×n-12
MWEX
MCSX[7:0]
VCC ≥ 4.5 V
MWEX ↑ →
tWEH - CSH
0
MCSX ↑ delay time
VCC < 4.5 V
VCC ≥ 4.5 V
MCLK×n-9
MCSX ↓→
MCSX
tCSL-WDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 4.5 V MCLK×n-12
MCSX
VCC ≥ 4.5 V
MCLK-9
MCSX ↓→
tCSL - DV
MADATA[15:0]
Data output time
VCC < 4.5 V
MCLK-12
VCC ≥ 4.5 V
MWEX ↑ →
MWEX
tWEH - DX
0
Data hold time
MADATA[15:0]
VCC < 4.5 V
Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Max
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
79
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
MADATA[15:0]
tCSL-WEL
tWEW
tDS-OE
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
80
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK
MAD[24:0]
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
tCSL
MCLK
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
MCLK
MADATA[15:0]
MCLK
MADATA[15:0]
tDS
tDH
tWEL
MCLK
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
MCLK
MDQM[1:0]
tDQMH
MCLK ↑ →
MCLK,
tODS
Data output time
MADATA[15:0]
MCLK ↑ →
MCLK
tOD
Data hold time
MADATA[15:0]
Note: When the external load capacitance = 30 pF.
Value
Min
Unit
Max
9
12
9
12
9
12
9
12
9
12
1
1
1
1
1
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
81
D a t a S h e e t
・ Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 4.5 V
Multiplexed
tALE-CHMADV
0
address delay time
VCC < 4.5 V
MALE
MADATA[15:0]
VCC ≥ 4.5 V MCLK×n+0
Multiplexed
tCHMADH
address hold time
VCC < 4.5 V MCLK×n+0
Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Max
10
20
MCLK×n+10
MCLK×n+20
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
82
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
Pin name
Conditions
MCLK
ALE
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
MCLK ↑ →
Multiplexed
tCHMADV
Address delay time
MCLK
MADATA[15:0]
MCLK ↑ →
Multiplexed
tCHMADX
Data output time
Note: When the external load capacitance = 30 pF.
VCC ≥ 4.5 V
Min
VCC < 4.5 V
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
VCC < 4.5 V
VCC ≥ 4.5 V
Value
Max
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
83
D a t a S h e e t
・ NAND Flash Mode
(VCC = 2.7V to 5.5V, VSS = 0V, TA = -40°C to +85°C)
Parameter
Symbol
Pin name
Conditions
VCC ≥ 4.5 V
MNREX
tNREW
MNREX
Min pulse width
VCC < 4.5 V
VCC ≥ 4.5 V
Data setup →
MNREX
tDS – NRE
MNREX ↑ time
MADATA[15:0] VCC < 4.5 V
VCC ≥ 4.5 V
MNREX ↑ →
MNREX
tDH – NRE
Data hold time
MADATA[15:0] VCC < 4.5 V
VCC ≥ 4.5 V
MNALE ↑ →
MNALE
tALEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5 V
VCC ≥ 4.5 V
MNALE ↓ →
MNALE
tALEL - NWEL
MNWEX delay time
MNWEX
VCC < 4.5 V
VCC ≥ 4.5 V
MNCLE ↑ →
MNCLE
tCLEH - NWEL
MNWEX delay time
MNWEX
VCC < 4.5 V
VCC ≥ 4.5 V
MNWEX ↑ →
MNCLE
tNWEH - CLEL
MNCLE delay time
MNWEX
VCC < 4.5 V
VCC ≥ 4.5 V
MNWEX
tNWEW
MNWEX
Min pulse width
VCC < 4.5 V
VCC ≥ 4.5 V
MNWEX ↓ →
MNWEX
tNWEL – DV
Data delay time
MADATA[15:0] VCC < 4.5 V
VCC ≥ 4.5 V
MNWEX ↑ →
MNWEX
tNWEH – DX
Data hold time
MADATA[15:0] VCC < 4.5 V
Note: When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
84
CONFIDENTIAL
Value
Unit
Min
Max
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Read
85
D a t a S h e e t
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
86
CONFIDENTIAL
Write
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ External Ready Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
MCLK ↑
MRDY input
setup time
tRDYI
Pin name Conditions
MCLK
MRDY
Value
Min
VCC ≥ 4.5 V
19
VCC < 4.5 V
37
Max
-
Unit
Remarks
ns
・ When RDY is input
···
MCLK
Over 2cycle
Original
MOEX
MWEX
tRDYI
MRDY
・ When RDY is released
MCLK
··· ···
2 cycle
Extended
MOEX
MWEX
tRDYI
MRDY
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
0.5×VCC
87
D a t a S h e e t
(8) Base Timer Input Timing
・ Timer input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
・ Trigger input timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "■Block Diagram" in this data sheet.
88
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
(9) CSIO/UART Timing
・ CSIO (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
4tCYCP
-
4tCYCP
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "■Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30 pF.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
89
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
VIH
VIL
SIN
tSHIXI
VIH
VIL
Master mode
tSLSH
SCK
tSHSL
VIH
VIH
tF
VIL
VIL
VIH
tR
tSLOVE
SOT
SIN
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
90
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ CSIO (SPI = 0, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx
SOTx
SCKx Master mode
SINx
SCKx
SINx
4tCYCP
-
4tCYCP
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "■Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30 pF.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
91
D a t a S h e e t
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
tSHOVE
VOH
VOL
tIVSLE
SIN
VIL
VIL
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
92
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
VCC < 4.5 V
Min
Max
SCKx
SCKx
SOTx
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
4tCYCP
-
4tCYCP
-
ns
-30
+30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
VCC ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "■Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30 pF.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
93
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSOVLI
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
Master mode
tSLSH
VIH
SCK
SOT
VIL
VIL
tF
*
VOH
VOL
tR
tIVSLE
SIN
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
94
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ CSIO (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
name
VCC < 4.5 V
Min
Max
VCC ≥ 4.5 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx
SOTx
-30
+30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock L pulse width
tSLSH
SCKx
-
ns
Serial clock H pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SINx Master mode
SCKx
SINx
SCKx
SOTx
SCKx
SOTx
SCKx
SINx
SCKx
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes: ・ The above characteristics apply to CLK synchronous mode.
・ tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "■Block Diagram" in
this data sheet.
・ These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
・ When the external load capacitance = 30 pF.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
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D a t a S h e e t
tSCYC
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VOH
VOL
VIH
VIL
Master mode
tR
SCK
VIL
tF
tSHSL
VIH
VIH
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
・ UART external clock input (EXT = 1)
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK fall time
SCK rise time
Symbol Conditions
tSLSH
tSHSL
tF
tR
CL = 30 pF
tR
SCK
96
CONFIDENTIAL
VIL
Max
tCYCP + 10
tCYCP + 10
-
5
5
tF
tSHSL
VIH
Min
VIH
VIL
Unit Remarks
ns
ns
ns
ns
tSLSH
VIL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
(10) External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol Pin name
Conditions
Value
Unit
Min
Max
ADTG
FRCKx
-
2tCYCP*
-
ns
-
2tCYCP*
-
ns
ICxx
Input pulse width
tINH,
tINL
DTTIxX
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
generator
Except
Timer mode, 2tCYCP + 100*
ns
INTxx,
External interrupt
Stop mode
NMIX
NMI
Timer mode,
500
ns
Stop mode
* : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which A/D converter, Multi-function Timer, External interrupt is connected to,
see "■Block Diagram" in this data sheet.
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D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Conditions
Min
Max
Unit
AIN pin H width
tAHL
AIN pin L width
tALL
BIN pin H width
tBHL
BIN pin L width
tBLL
BIN rise time from
PC_Mode2 or
tAUBU
AIN pin H level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBUAD
BIN pin H level
PC_Mode3
BIN fall time from
PC_Mode2 or
tADBD
AIN pin L level
PC_Mode3
AIN rise time from
PC_Mode2 or
tBDAU
BIN pin L level
PC_Mode3
AIN rise time from
PC_Mode2 or
2tCYCP*
ns
tBUAU
BIN pin H level
PC_Mode3
BIN fall time from
PC_Mode2 or
tAUBD
AIN pin H level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBDAD
BIN pin L level
PC_Mode3
BIN rise time from
PC_Mode2 or
tADBU
AIN pin L level
PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC=0
ZIN pin L width
tZLL
QCR:CGSC=0
AIN/BIN rise and fall time
tZABE
QCR:CGSC=1
from determined ZIN level
Determined ZIN level from
tABEZ
QCR:CGSC=1
AIN/BIN rise and fall time
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "■Block
Diagram" in this data sheet.
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
98
CONFIDENTIAL
tBLL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
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D a t a S h e e t
2
(12) I C Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Symbol
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCLclock L width
SCLclock H width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
START condition
fSCL
0
100
0
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
2 tCYCP*4
-
2 tCYCP*4
-
ns
*5
3 tCYCP*4
-
3 tCYCP*4
-
ns
*5
4 tCYCP*4
-
4 tCYCP*4
-
ns
*5
Noise filter
Conditions
Standard-mode Fast-mode
Unit Remarks
Min
Max Min Max
Parameter
tSUSTA
tHDDAT
tSP
CL = 30pF,
R = (Vp/IOL)*1
8MHz ≤
tCYCP ≤ 40MHz
40MHz <
tCYCP ≤ 60MHz
60MHz <
tCYCP ≤ 72MHz
400 kHz
0.9*3 μs
*1:R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2:The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal.
*3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device
satisfies the requirement of tSUDAT ≥ 250 ns.
*4:tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "■Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
*5:The number of the steps of the noise filter can be changed by register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
100
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
(13) ETM Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Data hold
TRACECLK
frequency
Pin name
Conditions
tETMH
TRACECLK
TRACED[3:0]
VCC ≥ 4.5 V
2
9
VCC < 4.5 V
2
15
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V
-
32
MHz
VCC ≥ 4.5 V
20
-
ns
VCC < 4.5 V
31.25
-
ns
1/ tTRACE
TRACECLK
TRACECLK
cycle time
Value
Unit
Min Max
Symbol
tTRACE
Remarks
ns
Note: When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
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D a t a S h e e t
(14) JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
VCC < 4.5 V
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
Note: When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
102
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
5.
12-bit A/D Converter
・Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Max
± 4.0
± 2.3
± 10
12
± 4.5
± 2.5
± 15
1.0*1
1.2*1
*2
*2
-
-
μs
-
50
-
2000
ns
tSTT
-
-
-
1.0
μs
CAIN
-
-
-
12.9
pF
Symbol
Pin
name
Min
VZT
ANxx
-
VFST
ANxx
-
Conversion time
-
-
Sampling time
tS
-
Compare clock cycle*3
tCCK
State transition time to
operation permission
Analog input capacity
Parameter
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
Unit
Remarks
bit
LSB
LSB
AVRH =
mV
2.7 V to 5.5 V
AVRH ± 10 AVRH ± 15 mV
ns
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
AVCC ≥ 4.5 V
AVCC < 4.5 V
2
AVCC ≥ 4.5 V
kΩ
3.8
AVCC < 4.5 V
Interchannel disparity
4
LSB
Analog port input current
ANxx
5
μA
Analog input voltage
ANxx AVSS
AVRH
V
Reference voltage
AVRH
2.7
AVCC
V
*1: Conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 4.5 V, HCLK=120 Hz sampling time: 300 ns, compare time: 700 ns
AVCC < 4.5 V, HCLK=120 Hz sampling time: 500 ns, compare time: 700 ns
Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK).
For setting*4 of sampling time and compare clock cycle, see "CHAPTER 1-1: 12-bit A/D Converter" in
"FM3 Family PERIPHERAL MANUAL Analog Macro Part".
A/D Converter register is set at APB bus clock timing. Sampling and compare clock is set at Base clock
(HCLK).
About the APB bus number which the A/D Converter is connected to, see "■Block Diagram" in this data
sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (tC) is the value of (Equation 2).
Analog input resistance
RAIN
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CONFIDENTIAL
-
-
-
103
D a t a S h e e t
Analog
signal source
REXT
ANxx
Analog input pin
Comparator
RAIN
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
RAIN:
CAIN:
REXT:
Sampling time
input resistance of A/D = 2 kΩ at 4.5 V < AVCC < 5.5 V
input resistance of A/D = 3.8 kΩ at 2.7 V < AVCC < 4.5 V
input capacity of A/D = 12.9 pF at 2.7 V < AVCC < 5.5 V
Output impedance of external circuit
(Equation 2) tC = tCCK × 14
tC:
tCCK:
104
CONFIDENTIAL
Compare time
Compare clock cycle
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・Definition of 12-bit A/D Converter Terms
・ Resolution:
・ Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
・ Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Actual conversion
characteristics
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
Analog input
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
1LSB =
N:
VZT:
VFST:
VNT:
VNT - {1LSB × (N - 1) + VZT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
AVRH
Analog input
105
D a t a S h e e t
6.
USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Input H level voltage
Input L level voltage
Input
charact- Differential input
eristics sensitivity
Different common mode
input voltage
Pin
Conditions
name
Min
Value
Max
Unit Remarks
VIH
-
2.0
VIL
-
VSS - 0.3
USBVCC + 0.3 V
0.8
V
*1
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
Minimum differential input
sensitivity [V]
External
pull-down
Output H level voltage
VOH
2.8
3.6
V *3
resistance =
15 kΩ
UDP0, External
UDM0
pull-up
Output L level voltage
VOL
0.0
0.3
V *3
resistance =
Output
1.5 kΩ
charact- Crossover voltage
VCRS
1.3
2.0
V *4
erstics
Rise time
tFR
Full-Speed
4
20
ns *5
Fall time
tFF
Full-Speed
4
20
ns *5
Rise/ fall time matching
tFRFM
Full-Speed
90
111.11
% *5
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rise time
tLR
Low-Speed
75
300
ns *7
Fall time
tLF
Low-Speed
75
300
ns *7
Rise/ fall time matching
tLRFM
Low-Speed
80
125
% *7
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within V IL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within
0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
106
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MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to the VSS and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Falling time
107
D a t a S h e e t
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ωto 44 Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use resistance with an uncertainty of 5% by E24 sequence.
*7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See "Figure ・Low-Speed Load (Compliance Load)" for conditions of external load.
108
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D a t a S h e e t
・Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
・Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
・Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
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109
D a t a S h e e t
7.
Low-voltage Detection Characteristics
(1) Low-voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
Symbol Conditions
VDL
VDH
-
Min
Value
Typ Max
2.25
2.30
2.45
2.50
Min
Value
Typ Max
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
(2) Interrupt of Low-voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
tLVDW
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Unit
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
4032 ×
tCYCP*
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
110
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MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
8.
MainFlash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Sector erase
time
Value
Typ*
Max*
0.7
3.7
Large Sector
Unit
Includes write time prior to internal
erase
s
Small Sector
0.3
Half word (16-bit)
write time
Remarks
1.1
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
8
38.4
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
12
384
μs
(2) Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
100,000
*: At average + 85C
9.
Remarks
10*
5*
WorkFlash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Value
Typ*
Max*
Sector erase time
0.3
1.5
Half word (16-bit)
write time
20
Unit
s
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
1.2
6
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 10,000 cycles
of erase/write.
384
μs
(2) Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
*: At average + 85C
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Remarks
10*
111
D a t a S h e e t
10. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Value
Typ
Max*
tCYCC
Unit
ns
40
80
μs
453
737
μs
Sub Timer mode
453
737
μs
Stop mode
453
737
μs
Low-speed CR Timer mode
tICNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
112
CONFIDENTIAL
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3
Family PERIPHERAL MANUAL" about the return factor from Low-Power consumption mode.
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
March 31, 2015, MB9B510R-DS706-00025-3v1-E
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(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
321
461
μs
321
461
μs
441
701
μs
Sub Timer mode
441
701
μs
Stop mode
441
701
μs
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tRCNT
Remarks
*: The maximum value depends on the accuracy of built-in CR.
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
114
CONFIDENTIAL
Start
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
*: Internal resource reset
Notes:
Start
is not included in return factor by the kind of Low-Power consumption mode.
・ The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes" in "FM3
Family PERIPHERAL MANUAL".
・ When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
・ The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing" in "4. AC Characteristics" in "■Electrical Characteristics" for the detail on the time
during the power-on reset/low -voltage detection reset.
・ When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
March 31, 2015, MB9B510R-DS706-00025-3v1-E
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115
D a t a S h e e t
Ordering Information
On-chip
Flash
memory
On-chip
SRAM
MB9BF512NPQC-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
8 Kbyte
MB9BF514NPQC-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF515NPQC-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
24 Kbyte
MB9BF516NPQC-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF512NPMC-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
8 Kbyte
MB9BF514NPMC-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF515NPMC-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
24 Kbyte
MB9BF516NPMC-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF512RPMC-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
8 Kbyte
MB9BF514RPMC-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF515RPMC-JNE2
Main: 384 Kbyte
Work: 32 Kbyte
24 Kbyte
MB9BF516RPMC-JNE2
Main: 512 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9BF512NBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
8 Kbyte
MB9BF514NBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9BF515NBGL-GE1
Main: 384 Kbyte
Work: 32 Kbyte
24 Kbyte
MB9BF516NBGL-GE1
Main: 512 Kbyte
Work: 32 Kbyte
32 Kbyte
Part number
116
CONFIDENTIAL
Package
Packing
Plastic QFP
100-pin (0.65 mm pitch),
(FPT-100P-M03)
Plastic LQFP
100-pin (0.5 mm pitch),
(FPT-100P-M23)
Tray
Plastic LQFP
120-pin (0.5 mm pitch),
(FPT-120P-M37)
Plastic PFBGA
112-pin (0.8 mm pitch),
(BGA-112P-M04)
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
26
"A"
1
C
0.22±0.05
(.009±.002)
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
0.60±0.15
(.024±.006)
25
0.50(.020)
0°~8°
0.50±0.20
(.020±.008)
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
117
D a t a S h e e t
120-pin plastic LQFP
(FPT-120P-M37)
120-pin plastic LQFP
(FPT-120P-M37)
Lead pitch
0.50 mm
Package width ×
package length
16.0 mm × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16 × 16-0.50
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 ± 0.20(.709 ± .008) SQ
* 16.00 ± 0.10(.630 ± .004) SQ
90
61
91
Details of "A" part
60
+0.20
+.008
1.50 –0.10 .059 –.004
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60 ± 0.15
(.024 ± .006)
"A"
120
LEAD No.
1
30
0.50(.020)
C
0.22 ± 0.05
(.009 ± .002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1
118
CONFIDENTIAL
0.10 ± 0.05
(.004 ± .002)
(Stand off)
31
+0.05
0.145–0.03
( .006+.002
–.001 )
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14 × 20-0.65
(FPT-100P-M36)
100-pin plastic QFP
(FPT-100P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90± 0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32 ± 0.05
(.013±.002)
"A"
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
0.13(.005)
M
0.17 ± 0.06
(.007 ±. 002)
0.80 ± 0.20
(.031 ±. 008)
0.88 ± 0.15
(.035 ±. 006)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
Dimensions in mm (inches).
Note: The valuesin parentheses are reference values.
119
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
Ф 0.45 mm
Mounting height
1.45 mm Max.
Weight
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S B
0.80(.031)
REF
B
11
10
9
8
7
6
5
4
3
2
0.80(.031)
REF
A
10.00±0.10
(.394±.004)
1
L K J H G F
(INDEX AREA)
0.35±0.10
(.014±.004)
(Stand off)
0.20(.008) S A
1.25±0.20
(.049±.008)
(Seated height)
ED C B A
INDEX
112-Ф0.45±010
(112-Ф0.18±.004)
Ф0.08(.003) M S A B
S
0.10(.004) S
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
120
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
Major Changes
Page
Section
Revision 1.0
Revision 2.0
6
102
-
FEATURES
External Interrupt Controller Unit
ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter
Change Results
Initial release
Corrected the external interrupt input pin.
Corrected the value of "Compare clock cycle".
Max: 10000 → 2000
Electrical Characteristics for the A/D
Converter
ORDERING INFORMATION
Revision 2.1
Revision 3.0
Features
2
External Bus Interface
Features
3
USB Interface
10
Packages
List of Pin Functions
28, 29
· List of pin numbers
48, 50
I/O Circuit Type
48, 49
I/O Circuit Type
55
Handling Devices
Handling Devices
55
Crystal oscillator circuit
Handling Devices
56
C Pin
57
Block Diagram
Memory Map
58
· Memory map(1)
Memory Map
59, 60
· Memory map(2)(3)
111
67, 68
69
70, 71
74
75
76
77
79-81
89-96
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
2. Recommended Operation Conditions
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(1) Main Clock Input Characteristics
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main and
USB PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
(8) CSIO/UART Timing
March 31, 2015, MB9B510R-DS706-00025-3v1-E
CONFIDENTIAL
Corrected the part number.
Company name and layout design change
Added the description of Maximum area size
Added the description of PLL for USB
Deleted the description of ES
Modified I/O circuit type of P63 to P68
Added the description of I2C to the type of E, F, G and I
Added about +B input
Added " tabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount board."
Changed the description
Modified the block diagram
Modified the area of "Extarnal Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80 and P81
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
· Modified the unit of low voltage detection circuit (LVD) power supply
current
Added Master clock at Ingernal operating clock frequency
Added Frequency stability time at Built-in high-speed CR
· Added Main PLL clock frequency
· Added USB clock frequency
· Added the figure of Main PLL connection and USB PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
121
D a t a S h e e t
Page
103
Section
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
7. Low-voltage Detection Characteristics
(2) Interrupt of Low-voltage Detection
Electrical Characteristics
9. WorkFlash Memory Write/Erase
111
Characteristics
(1) Write / Erase time
Electrical Characteristics
112-115
9. Return Time from Low-Power
Consumption Mode
116
Ordering Information
117-120
Package Dimensions
Revision 3.1
Electrical Characteristics
77
4. AC Characteristics
(6) Power-on Reset Timing
110
122
CONFIDENTIAL
Change Results
· Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Modified LVD stabilization wait time
· Modified sector erase time
· Modified half word(16-bit) write time
Added Return Time from Low-Power Consumption Mode
Change to full part number
Deleted FPT-100P-M20 and FPT-120P-M21
Revised the cross-reference in the glossary.
MB9B510R-DS706-00025-3v1-E, March 31, 2015
D a t a S h e e t
March 31, 2015, MB9B510R-DS706-00025-3v1-E
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124
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Cypress
All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
TM
TM
ORNAND , Easy DesignSim , TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
126
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MB9B510R-DS706-00025-3v1-E, March 31, 2015