Freescale MPC8360EVVAJDHA Powerquicc ii pro processor revision 2.x tbga silicon hardware specification Datasheet

Freescale Semiconductor
Technical Data
Document Number: MPC8360EEC
Rev. 5, 09/2011
MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features, including a
block diagram showing the major functional components. This device is
a cost-effective, highly integrated communications processor that
addresses the needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include next generation
DSLAMs, network interface cards for 3G base stations (Node Bs),
routers, media gateways, and high end IADs. The device extends current
PowerQUICC II Pro offerings, adding higher CPU performance,
additional functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related to
time-to-market, price, power, and package size. This device can be used
for the control plane and also has data plane functionality.
For functional characteristics of the processor, refer to the MPC8360E
PowerQUICC II Pro Integrated Communications Processor Reference
Manual, Rev. 3.
To locate any updates for this document, refer to the MPC8360E product
summary page on our website listed on the back cover of this document
or contact your Freescale sales office.
1
Overview
This section describes a high-level overview including features and
general operation of the MPC8360E/58E PowerQUICC II Pro processor.
A major component of this device is the e300 core, which includes
32 Kbytes of instruction and data cache and is fully compatible with the
Power Architecture™ 603e instruction set. The new QUICC Engine
module provides termination, interworking, and switching between a
© 2011 Freescale Semiconductor, Inc. All rights reserved.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . 12
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 14
RESET Initialization . . . . . . . . . . . . . . . . . . . . 16
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 25
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Package and Pin Listings . . . . . . . . . . . . . . . . . 63
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
System Design Information . . . . . . . . . . . . . . . 96
Ordering Information . . . . . . . . . . . . . . . . . . . . 99
Document Revision History . . . . . . . . . . . . . 100
wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’s enhanced interworking eases
the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR
SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in
an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data
plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI
controller, a flexible local bus, and a dedicated security engine.
This figure shows the MPC8360Eblock diagram.
System Interface Unit
(SIU)
e300 Core
32KB
I-Cache
Security Engine
32KB
D-Cache
Memory Controllers
GPCM/UPM/SDRAM
Classic G2 MMUs
32/64 DDR Interface Unit
FPU
Power
Management
PCI Bridge
JTAG/COP
Timers
Local Bus
PCI
Local
Bus Arbitration
QUICC Engine Module
Multi-User
RAM
Accelerators
Baud Rate
Generators
DDRC1
DDRC2
Dual 32-Bit RISC CP
DUART
Serial DMA
&
2 Virtual
DMAs
Dual I2C
4 Channel DMA
Parallel I/O
SPI2
SPI1
USB
UCC8
UCC7
UCC6
UCC5
UCC4
UCC3
UCC2
UCC1
MCC
Interrupt Controller
Protection & Configuration
System Reset
Time Slot Assigner
Clock Synthesizer
Serial Interface
8 TDM Ports
8 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
2 UTOPIA/POS
(124 MPHY)
Figure 1. MPC8360E Block Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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This figure shows the MPC8358E block diagram.
System Interface Unit
(SIU)
e300 Core
Security Engine
32KB
D-Cache
32KB
I-Cache
Memory Controllers
GPCM/UPM/SDRAM
Classic G2 MMUs
32/64 DDR Interface Unit
FPU
Power
Management
PCI Bridge
JTAG/COP
Timers
Local Bus
PCI
Local
Bus Arbitration
QUICC Engine Module
Multi-User
RAM
Accelerators
Baud Rate
Generators
DDRC
Dual 32-Bit RISC CP
DUART
Serial DMA
&
2 Virtual
DMAs
Dual I2C
4 Channel DMA
Parallel I/O
SPI2
SPI1
USB
UCC8
UCC5
UCC4
UCC3
UCC2
UCC1
Interrupt Controller
Protection & Configuration
System Reset
Time Slot Assigner
Clock Synthesizer
Serial Interface
4 TDM Ports
6 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
1 UTOPIA/POS
(31/124 MPHY)
Figure 2. MPC8358E Block Diagram
Major features of the MPC8360E/58E are as follows:
•
•
e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the Freescale processor families implementing the Power Architecture™ technology
QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to
500 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)
— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the MPC8358E
supporting the following protocols and interfaces (not all of them simultaneously):
– IEEE 1588 protocol supported
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a media-independent interface (MII,
RMII, RGMII)1
– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent interface (GMII, RGMII,
TBI, RTBI) on UCC1 and UCC2
– 9.6-Kbyte jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in accordance ITU-T
I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex (with 4 CPS packets
per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM forum TM4.1 for up
to 64-Kbyte simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance with ITU-T I.163.1
and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in accordance with the ATM
forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001 (Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the following RFCs:
1661, 1662, 1990, 2686, and 3153
– IP support for IPv4 packets including TOS, TTL, and header checksum processing
– Ethernet over first mile IEEE 802.3ah
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including bridging of ATM
ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels
— One multichannel communication controller (MCC) only on the MPC8360E supporting the following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces
— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional 2*128 MultiPHY with
extended address) and one UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
1.SMII or SGMII media-independent interface is not currently supported.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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•
•
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3
rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial
channels (MCC is only available on the MPC8360E)
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, 802.11i®, iSCSI,
and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units
(EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the
MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus; on the MPC8358E,
the DDR bus can be configured as a 32- or 64-bit bus
— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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•
•
•
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers, both support ECC)
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:
– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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•
•
•
•
•
2
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication processor
— Redirects interrupts to external INTA pin when in core disable mode
— Unique vector number for each interrupt source
Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data is optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3]. There is one set for
each DMA channel. The pins are multiplexed to the parallel IO pins with other QE functions.
DUART
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers
IEEE Std. 1149.1™-compliant, JTAG boundary scan
Integrated PCI bus and SDRAM clock generation
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8360E/58E. The device
is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a
more complete reference. These are not purely I/O buffer design specifications.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Overall DC Electrical Characteristics
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
This table provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings1
Characteristic
Core and PLL supply voltage for
Symbol
Max Value
Unit
Notes
VDD & AVDD
–0.3 to 1.32
V
—
VDD & AVDD
–0.3 to 1.37
V
—
V
—
MPC8358 Device Part Number with
Processor Frequency label of AD=266MHz and AG=400MHz &
QUICC Engine Frequency label of E=300MHz & G=400MHz
MPC8360 Device Part Number with
Processor Frequency label of AG=400MHz and AJ=533MHz &
QUICC Engine Frequency label of G=400MHz
Core and PLL supply voltage for
MPC8360 device Part Number with
Processor Frequency label of AL=667MHz and QUICC Engine
Frequency label of H=500MHz
DDR and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.89
DDR
DDR2
Three-speed Ethernet I/O, MII management voltage
LVDD
–0.3 to 3.63
V
—
PCI, local bus, DUART, system control and power management,
I2C, SPI, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
—
Input voltage
MVIN
–0.3 to (GVDD + 0.3)
V
2, 5
MVREF
–0.3 to (GVDD + 0.3)
V
2, 5
Three-speed Ethernet signals
LVIN
–0.3 to (LVDD + 0.3)
V
4, 5
Local bus, DUART, CLKIN, system
control and power management, I2C, SPI,
and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
3, 5
PCI
OVIN
–0.3 to (OVDD + 0.3)
V
6
DDR DRAM signals
DDR DRAM reference
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Overall DC Electrical Characteristics
Table 1. Absolute Maximum Ratings1 (continued)
Characteristic
Storage temperature range
Symbol
Max Value
Unit
Notes
TSTG
–55 to 150
°C
—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during
power-on reset and power-down sequences.
5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
shown in Figure 4.
2.1.2
Power Supply Voltage Specification
This table provides the recommended operating conditions for the device. Note that the values in this table are the recommended
and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic
Core and PLL supply voltage for
Symbol
Recommended
Value
Unit
Notes
VDD & AVDD
1.2 V ± 60 mV
V
1, 3
VDD & AVDD
1.3 V ± 50 mV
V
1, 3
V
—
MPC8358 Device Part Number with
Processor Frequency label of AD=266MHz and AG=400MHz &
QUICC Engine Frequency label of E=300MHz & G=400MHz
MPC8360 Device Part Number with
Processor Frequency label of AG=400MHz and AJ=533MHz &
QUICC Engine Frequency label of G=400MHz
Core and PLL supply voltage for
MPC8360 Device Part Number with
Processor Frequency label of AL=667MHz and QUICC Engine
Frequency label of H=500MHz
DDR and DDR2 DRAM I/O supply voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
DDR
DDR2
Three-speed Ethernet I/O supply voltage
LVDD0
3.3 V ± 330 mV
2.5 V ± 125 mV
V
—
Three-speed Ethernet I/O supply voltage
LVDD1
3.3 V ± 330 mV
2.5 V ± 125 mV
V
—
Three-speed Ethernet I/O supply voltage
LVDD2
3.3 V ± 330 mV
2.5 V ± 125 mV
V
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Overall DC Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic
Symbol
Recommended
Value
Unit
Notes
PCI, local bus, DUART, system control and power management, I2C,
SPI, and JTAG I/O voltage
OVDD
3.3 V ± 330 mV
V
—
TJ
0 to 105
–40 to 105
°C
2
Junction temperature
Notes:
1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
2. The operating conditions for junction temperature, TJ, on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is
0° to 70 ° C. Refer to Errata General9 in Chip Errata for the MPC8360E, Rev. 1.
3. For more information on Part Numbering, refer to Table 80.
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/OVDD + 20%
G/L/OVDD + 5%
VIH
G/L/OVDD
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. Note that tinterface refers to the clock period associated with the bus clock interface.
Figure 3. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Power Sequencing
This figure shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V signals, respectively.
11 ns
(Min)
+7.1 V
7.1 V p-to-p
(Min)
Overvoltage
Waveform
4 ns
(Max)
0V
4 ns
(Max)
62.5 ns
+3.6 V
7.1 V p-to-p
(Min)
Undervoltage
Waveform
–3.5 V
Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 3. Output Drive Capability
Driver Type
Output Impedance (Ω)
Supply Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
PCI output clocks (including PCI_SYNC_OUT)
42
DDR signal
20
36 (half-strength mode)1
GVDD = 2.5 V
DDR2 signal
18
36 (half-strength mode)1
GVDD = 1.8 V
42
LVDD = 2.5/3.3 V
42
OVDD = 3.3 V
42
OVDD = 3.3 V
LVDD = 2.5/3.3 V
10/100/1000 Ethernet signals
DUART, system control,
I2C,
SPI, JTAG
GPIO signals
Note:
1. DDR output impedance values for half strength mode are verified by design and not tested.
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8360E/58E.
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Power Sequencing
2.2.1
Power-Up Sequencing
MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD, LVDD, and OVDD)
to be applied in any particular order. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins are actively be driven and cause
contention and excessive current from 3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current
draw, apply the core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal
value before the I/O supplies reach 0.7 V, see this figure.
Voltage
I/O Voltage (GVDD, LVDD, OVDD)
Core Voltage (VDD, AVDD)
0.7 V
90%
Time
Figure 5. Power Sequencing Example
I/O voltage supplies (GVDD, LVDD, and OVDD) do not have any ordering requirements with respect to one another.
2.2.2
Power-Down Sequencing
The MPC8360E/58E does not require the core supply voltage and I/O supply voltages to be powered down in any particular
order.
3
Power Characteristics
The estimated typical power dissipation values are shown in these tables.
Table 4. MPC8360E TBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz)
Typical
Maximum
Unit
Notes
266
266
500
5.0
5.6
W
2, 3, 5
400
266
400
4.5
5.0
W
2, 3, 4
533
266
400
4.8
5.3
W
2, 3, 4
667
333
400
5.8
6.3
W
3, 6, 7, 8
500
333
500
5.9
6.4
W
3, 6, 7, 8
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Power Sequencing
Table 4. MPC8360E TBGA Core Power Dissipation1 (continued)
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz)
Typical
Maximum
Unit
Notes
667
333
500
6.1
6.8
W
2, 3, 5, 9
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 6.
2. Typical power is based on a voltage of VDD = 1.2 V or 1.3 V, a junction temperature of TJ = 105° C, and a Dhrystone
benchmark application.
3. Thermal solutions need to design to a value higher than typical power on the end application, TA target, and I/O power.
4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105° C, and an artificial smoke test.
5. Maximum power is based on a voltage of VDD = 1.3 V for applications that use 667 MHz (CPU)/500 (QE) with WC process,
a junction TJ = 105° C, and an artificial smoke test.
6. Typical power is based on a voltage of VDD = 1.3 V, a junction temperature of TJ = 70° C, and a Dhrystone benchmark
application.
7. Maximum power is based on a voltage of VDD = 1.3 V for applications that use 667 MHz (CPU) or 500 (QE) with WC
process, a junction TJ = 70° C, and an artificial smoke test.
8. This frequency combination is only available for rev. 2.0 silicon.
9. This frequency combination is not available for rev. 2.0 silicon.
Table 5. MPC8358E TBGA Core Power Dissipation1
Core
Frequency (MHz)
CSB
Frequency (MHz)
QUICC Engine
Frequency (MHz)
Typical
Maximum
Unit
Notes
266
266
300
4.1
4.5
W
2, 3, 4
400
266
400
4.5
5.0
W
2, 3, 4
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 6.
2. Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ = 105° C, and a Dhrystone benchmark
application.
3. Thermal solutions need to design to a value higher than typical power on the end application, TA target, and I/O power.
4. Maximum power is based on a voltage of VDD = 1.2 V, WC process, a junction TJ = 105° C, and an artificial smoke test.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
13
Power Sequencing
This table shows the estimated typical I/O power dissipation for the device.
Table 6. Estimated Typical I/O Power Dissipation
GVDD
(1.8 V)
GVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
Unit
Comments
200 MHz, 1 × 32 bits
0.3
0.46
—
—
—
W
—
200 MHz, 1 × 64 bits
0.4
0.58
—
—
—
W
—
200 MHz, 2 × 32 bits
0.6
0.92
—
—
—
W
—
266 MHz, 1 × 32 bits
0.35
0.56
—
—
—
W
—
266 MHz, 1 × 64 bits
0.46
0.7
—
—
—
W
—
266 MHz, 2 × 32 bits
0.7
1.11
—
—
—
W
—
333 MHz, 1 × 32 bits
0.4
0.65
—
—
—
W
—
333 MHz, 1 × 64 bits
0.53
0.82
—
—
—
W
—
333 MHz, 2 × 32 bits
0.81
1.3
—
—
—
W
—
133 MHz, 32 bits
—
—
0.22
—
—
W
—
83 MHz, 32 bits
—
—
0.14
—
—
W
—
66 MHz, 32 bits
—
—
0.12
—
—
W
—
50 MHz, 32 bits
—
—
0.09
—
—
W
—
PCI I/O
Load = 30 pF
33 MHz, 32 bits
—
—
0.05
—
—
W
—
66 MHz, 32 bits
—
—
0.07
—
—
W
—
10/100/1000
Ethernet I/O
Load = 20 pF
MII or RMII
—
—
—
0.01
—
W
GMII or TBI
—
—
—
0.04
—
W
RGMII or RTBI
—
—
—
—
0.04
W
—
—
—
0.1
—
—
W
Interface
DDR I/O
65% utilization
Rs = 20 Ω
Rt = 50 Ω
2 pairs of clocks
Local Bus I/O
Load = 25 pf
3 pairs of clocks
Other I/O
4
Parameter
Multiply by
number of
interfaces used.
—
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.
NOTE
The rise/fall time on QUICC Engine block input pins should not exceed 5 ns. This should
be enforced especially on clock signals. Rise time refers to signal transitions from 10% to
90% of VDD; fall time refers to transitions from 90% to 10% of VDD.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
DC Electrical Characteristics
4.1
DC Electrical Characteristics
This table provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
—
VIH
2.7
OVDD + 0.3
V
Input low voltage
—
VIL
–0.3
0.4
V
0 V ≤VIN ≤OVDD
IIN
—
±10
μA
PCI_SYNC_IN input current
0 V ≤VIN ≤0.5V or
OVDD – 0.5V ≤VIN ≤OVDD
IIN
—
±10
μA
PCI_SYNC_IN input current
0.5 V ≤VIN ≤OVDD – 0.5 V
IIN
—
±100
μA
CLKIN input current
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is
configured in PCI host or PCI agent mode. This table provides the clock input (CLKIN/PCI_CLK) AC timing specifications for
the device.
Table 8. CLKIN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
CLKIN/PCI_CLK frequency
fCLKIN
—
—
66.67
MHz
1
CLKIN/PCI_CLK cycle time
tCLKIN
15
—
—
ns
—
CLKIN/PCI_CLK rise and fall time
tKH, tKL
0.6
1.0
2.3
ns
2
tKHK/tCLKIN
40
—
60
%
3
—
—
—
±150
ps
4, 5
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or
minimum operating frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
4.3
Gigabit Reference Clock Input Timing
This table provides the Gigabit reference clocks (GTX_CLK125) AC timing specifications.
Table 9. GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
GTX_CLK125 frequency
tG125
—
125
—
MHz
—
GTX_CLK125 cycle time
tG125
—
8
—
ns
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
15
RESET DC Electrical Characteristics
Table 9. GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV (continued)
Parameter/Condition
GTX_CLK rise and fall time
Symbol
Min
Typical
tG125R/tG125F
—
—
LVDD = 2.5 V
LVDD = 3.3 V
—
45
47
GMII & TBI
1000Base-T for RGMII & RTBI
GTX_CLK125 jitter
Unit
Notes
ns
1
%
2
ps
2
0.75
1.0
tG125H/tG125
GTX_CLK125 duty cycle
Max
—
55
53
—
—
±150
Notes:
1. Rise and fall times for GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. GTX_CLK125 is used to generate the GTX clock for the UCC Ethernet transmitter with 2% degradation. The GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by GTX_CLK.
See Section 8.2.2, “MII AC Timing Specifications,” Section 8.2.3, “RMII AC Timing Specifications,” and Section 8.2.5,
“RGMII and RTBI AC Timing Specifications” for the duty cycle for 10Base-T and 100Base-T reference clock.
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of
the MPC8360E/58E.
5.1
RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the device.
Table 10. RESET Pins DC Electrical Characteristics 1
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±10
μA
Output high voltage
VOH2
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
16
Freescale Semiconductor
RESET AC Electrical Characteristics
5.2
RESET AC Electrical Characteristics
This section describes the AC electrical specifications for the reset initialization timing requirements of the device. This table
provides the reset initialization AC timing specifications for the DDR SDRAM component(s).
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset
flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock applied to CLKIN
when the device is in PCI host mode
32
—
tCLKIN
2
Required assertion time of PORESET with stable clock applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
—
tPCI_SYNC_IN
1
HRESET negation to SRESET negation (output)
16
—
tPCI_SYNC_IN
1
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device
is in PCI host mode
4
—
tCLKIN
2
Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the device
is in PCI agent mode
4
—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to negation of HRESET
0
—
ns
—
Time for the device to turn off POR config signals with respect to the
assertion of HRESET
—
4
ns
3
Time for the device to turn on POR config signals with respect to the
negation of HRESET
1
—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the
primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. Refer
MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. Refer
MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
This table provides the PLL and DLL lock times.
Table 12. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs
—
DLL lock times
7680
122,880
csb_clk cycles
1, 2
Notes:
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1
ratio results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 21, “Clocking,” for more information.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
17
QUICC Engine Block Operating Frequency Limitations
5.3
QUICC Engine Block Operating Frequency Limitations
This section specify the limits of the AC electrical characteristics for the operation of the QUICC Engine block’s
communication interfaces.
NOTE
The settings listed below are required for correct hardware interface operation. Each
protocol by itself requires a minimal QUICC Engine block operating frequency setting for
meeting the performance target. Because the performance is a complex function of all the
QUICC Engine block settings, the user should make use of the QUICC Engine block
performance utility tool provided by Freescale to validate their system.
This table lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block core frequency for
each interface.
Table 13. QUICC Engine Block Operating Frequency Limitations
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1 (MHz)
Notes
Ethernet Management: MDC/MDIO
10 (max)
10
20
—
MII
25 (typ)
100
50
—
RMII
50 (typ)
100
50
—
GMII/RGMII/TBI/RTBI
125 (typ)
1000
250
—
SPI (master/slave)
10 (max)
10
20
—
UCC through TDM
50 (max)
70
8× F
2
MCC
25 (max)
16.67
16 × F
2, 4
UTOPIA L2
50 (max)
800
2× F
2
POS-PHY L2
50 (max)
800
2× F
2
HDLC bus
10 (max)
10
20
—
HDLC/transparent
50 (max)
50
8/3 × F
2, 3
UART/async HDLC
3.68 (max internal ref
clock)
115 (Kbps)
20
—
2 (max)
2
20
—
48 (ref clock)
12
96
—
Interface
BISYNC
USB
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.\
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface of the
MPC8360E/58E.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
18
Freescale Semiconductor
DDR and DDR2 SDRAM DC Electrical Characteristics
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when
GVDD(typ) = 1.8 V.
Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.125
V
—
Output leakage current
IOZ
—
±10
μA
4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
MVREF input leakage current
IVREF
—
±10
μA
—
Input current (0 V ≤VIN ≤OVDD)
IIN
—
±10
μA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise
on MVREF cannot exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal
MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤VOUT ≤GVDD.
This table provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 15. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) of the device when
GVDD(typ) = 2.5 V.
Table 16. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49 × GVDD
0.51 × GVDD
V
2
VTT
MVREF – 0.04
MVREF + 0.04
V
3
I/O termination voltage
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
19
DDR and DDR2 SDRAM AC Electrical Characteristics
Table 16. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V (continued)
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
—
Input low voltage
VIL
–0.3
MVREF – 0.18
V
—
Output leakage current
IOZ
—
±10
μA
4
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
—
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
—
MVREF input leakage current
IVREF
—
±10
μA
—
Input current (0 V ≤VIN ≤OVDD)
IIN
—
±10
μA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V ≤VOUT ≤GVDD.
This table provides the DDR capacitance when GVDD(typ) = 2.5 V.
Table 17. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Symbol
Min
Max
Unit
Notes
CIO
6
8
pF
1
CDIO
—
0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25° C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM interface when GVDD(typ) = 1.8 V.
Table 18. DDR2 SDRAM Input AC Timing Specifications for GVDD(typ) = 1.8 V
At recommended operating conditions with GVDD of 1.8 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.25
V
—
AC input high voltage
VIH
MVREF + 0.25
—
V
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
20
Freescale Semiconductor
DDR and DDR2 SDRAM AC Electrical Characteristics
This table provides the input AC timing specifications for the DDR SDRAM interface when GVDD(typ) = 2.5 V.
Table 19. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF – 0.31
V
—
AC input high voltage
VIH
MVREF + 0.31
—
V
—
Unit
Notes
ps
1, 2
Table 20. DDR and DDR2 SDRAM Input AC Timing Specifications Mode
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
MDQS—MDQ/MECC input skew per byte
333 MHz
266 MHz
200 MHz
tDISKEW
Min
Max
–750
–1125
–1250
750
1125
1250
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤n ≤7)
or ECC (MECC[{0...7}] if n = 8).
This figure shows the input timing diagram for the DDR controller.
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 6. DDR Input Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
21
DDR and DDR2 SDRAM AC Electrical Characteristics
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 21 and Table 22 provide the output AC timing specifications and measurement conditions for the DDR and DDR2
SDRAM interface.
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
Symbol1
Min
Max
Unit
Notes
tMCK
6
10
ns
2
ns
3
–1.0
–1.1
–1.2
0.2
0.3
0.4
—
ns
4
—
ns
4
—
ns
4
—
ns
4
0.7
ns
5, 9
—
ns
6
—
ns
6
–0.5 × tMCK + 0.6
ns
7
tAOSKEW
333 MHz
266 MHz
200 MHz
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
ADDR/CMD output hold with respect to MCK
tDDKHAX
2.1
2.8
3.5
333 MHz
266 MHz—DDR1
266 MHz—DDR2
200 MHz
MCS(n) output setup with respect to MCK
2.0
2.7
2.8
3.5
tDDKHCS
333 MHz
266 MHz
200 MHz
MCS(n) output hold with respect to MCK
2.1
2.8
3.5
tDDKHCX
333 MHz
266 MHz
200 MHz
2.0
2.7
3.5
MCK to MDQS
tDDKHMH
MDQ/MECC/MDM output setup with respect to MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
MDQ/MECC/MDM output hold with respect to MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
MDQS preamble start
tDDKHMP
–0.8
0.7
1.0
1.2
0.7
1.0
1.2
–0.5 × tMCK – 0.6
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
DDR and DDR2 SDRAM AC Electrical Characteristics
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode (continued)
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
MDQS epilogue end
Symbol1
Min
Max
Unit
Notes
tDDKHME
–0.6
0.9
ns
7
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in ¼ applied cycle increments through the clock control register.
For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks
by ½ applied cycle.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this is typically set to the
same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. Refer MPC8360E PowerQUICC II Pro Integrated Communications
Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol
conventions described in note 1.
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
9. In rev. 2.0 silicon, tDDKHMH maximum meets the specification of 0.6 ns. In rev. 2.0 silicon, due to errata, tDDKHMH minimum
is –0.9 ns. Refer to Errata DDR18 in Chip Errata for the MPC8360E, Rev. 1.
This figure shows the DDR SDRAM output timing for address skew with respect to any MCK.
MCK[n]
MCK[n]
tMCK
tAOSKEW(max)
ADDR/CMD
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
Figure 7. Timing Diagram for tAOSKEW Measurement
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
23
DDR and DDR2 SDRAM AC Electrical Characteristics
This figure provides the AC test load for the DDR bus.
Z0 = 50 Ω
Output
RL = 50 Ω
GVDD/2
Figure 8. DDR AC Test Load
Table 22. DDR and DDR2 SDRAM Measurement Conditions
Symbol
DDR
DDR2
Unit
Notes
VTH
MVREF ± 0.31 V
MVREF ± 0.25 V
V
1
VOUT
0.5 × GVDD
0.5 × GVDD
V
2
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
This figure shows the DDR SDRAM output timing diagram for source synchronous mode.
MCK[n]
MCK[n]
tMCK
tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 9. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
DUART DC Electrical Characteristics
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8360E/58E.
7.1
DUART DC Electrical Characteristics
This table provides the DC electrical characteristics for the DUART interface of the device.
Table 23. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Notes
High-level input voltage
VIH
2
OVDD + 0.3
V
—
Low-level input voltage OVDD
VIL
–0.3
0.8
V
—
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.4
—
V
—
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
—
IIN
—
±10
μA
1
Value
Unit
Notes
Minimum baud rate
256
baud
—
Maximum baud rate
>1,000,000
baud
1
16
—
2
Input current (0 V ≤VIN ≤OVDD)
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
This table provides the AC timing parameters for the DUART interface of the device.
Table 24. DUART AC Timing Specifications
Parameter
Oversample rate
Notes:
1. Actual attainable baud rate is limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each sixteenth sample.
8
UCC Ethernet Controller: Three-Speed Ethernet,
MII Management
This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management.
8.1
Three-Speed Ethernet Controller (10/100/1000 Mbps)—
GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII (media independent
interface), RMII (reduced media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and MDC (management
data clock). The MII, RMII, GMII, and TBI interfaces are only defined for 3.3 V, while the RGMII and RTBI interfaces are only
defined for 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
25
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
Physical Layer Device Specification Version 1.2a (9/22/2000). The electrical characteristics for the MDIO and MDC are
specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.”
8.1.1
10/100/1000 Ethernet DC Electrical Characteristics
The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit media independent
interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent interface (RMII) signals, management data
input/output (MDIO) and management data clock (MDC).
The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated at 2.5 V. The RGMII
and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3. The RMII
interface follows the RMII Consortium RMII Specification Version 1.2.
Table 25. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)
Parameter
Symbol
Conditions
Min
Max
Unit
Notes
Supply voltage 3.3 V
LVDD
—
2.97
3.63
V
1
Output high voltage
VOH
IOH = –4.0 mA
LVDD = Min
2.40
LVDD + 0.3
V
—
Output low voltage
VOL
IOL = 4.0 mA
LVDD = Min
GND
0.50
V
—
Input high voltage
VIH
—
—
2.0
LVDD + 0.3
V
—
Input low voltage
VIL
—
—
–0.3
0.90
V
—
Input current
IIN
—
±10
μA
—
0 V ≤VIN ≤LVDD
Note:
1. GMII/MII pins that are not needed for RGMII, RMII, or RTBI operation are powered by the OVDD supply.
Table 26. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)
Parameters
Symbol
Conditions
Min
Max
Unit
Supply voltage 2.5 V
LVDD
—
2.37
2.63
V
Output high voltage
VOH
IOH = –1.0 mA
LVDD = Min
2.00
LVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
LVDD = Min
GND – 0.3
0.40
V
Input high voltage
VIH
—
LVDD = Min
1.7
LVDD + 0.3
V
Input low voltage
VIL
—
LVDD = Min
–0.3
0.70
V
Input current
IIN
—
±10
μA
8.2
0 V ≤VIN ≤LVDD
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII Timing Specifications
This sections describe the GMII transmit and receive AC timing specifications.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.1.1
GMII Transmit AC Timing Specifications
This table provides the GMII transmit AC timing specifications.
Table 27. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
Notes
tGTX
—
8.0
—
ns
—
tGTXH/tGTX
40
—
60
%
—
tGTKHDX
tGTKHDV
0.5
—
—
—
5.0
ns
3
GTX_CLK clock rise time, (20% to 80%)
tGTXR
—
—
1.0
ns
—
GTX_CLK clock fall time, (80% to 20%)
tGTXF
—
—
1.0
ns
—
GTX_CLK125 clock period
tG125
—
8.0
—
ns
2
tG125H/tG125
45
—
55
%
2
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK125 reference clock duty cycle measured at
LVDD/2
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII
transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input
signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with
respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X)
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
convention.
3. In rev. 2.0 silicon, due to errata, tGTKHDX minimum and tGTKHDV maximum are not supported when the GTX_CLK is
selected. Refer to Errata QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.
This figure shows the GMII transmit AC timing diagram.
tGTXR
tGTX
GTX_CLK
tGTXH
tGTXF
TXD[7:0]
TX_EN
TX_ER
tGTKHDX
Figure 10. GMII Transmit AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
27
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.1.2
GMII Receive AC Timing Specifications
This table provides the GMII receive AC timing specifications.
Table 28. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
Notes
tGRX
—
8.0
—
ns
—
tGRXH/tGRX
40
—
60
%
—
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tGRDVKH
2.0
—
—
ns
—
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tGRDXKH
0.2
—
—
ns
2
RX_CLK clock rise time, (20% to 80%)
tGRXR
—
—
1.0
ns
—
RX_CLK clock fall time, (80% to 20%)
tGRXF
—
—
1.0
ns
—
Parameter/Condition
RX_CLK clock period
RX_CLK duty cycle
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock
reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to
the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. In rev. 2.0 silicon, due to errata, tGRDXKH minimum is 0.5 which is not compliant with the standard. Refer to Errata
QE_ENET18 in Chip Errata for the MPC8360E, Rev. 1.
This figure shows the GMII receive AC timing diagram.
tGRXR
tGRX
RX_CLK
tGRXH
tGRXF
RXD[7:0]
RX_DV
RX_ER
tGRDXKH
tGRDVKH
Figure 11. GMII Receive AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
28
Freescale Semiconductor
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
Table 29. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
TX_CLK clock period 10 Mbps
tMTX
—
400
—
ns
TX_CLK clock period 100 Mbps
tMTX
—
40
—
ns
tMTXH/tMTX
35
—
65
%
tMTKHDX
tMTKHDV
1
—
5
—
15
ns
TX_CLK data clock rise time, (20% to 80%)
tMTXR
1.0
—
4.0
ns
TX_CLK data clock fall time, (80% to 20%)
tMTXF
1.0
—
4.0
ns
Parameter/Condition
TX_CLK duty cycle
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit
timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,
the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.
For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
This figure shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXH
tMTXF
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 12. MII Transmit AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
29
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.2.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
Table 30. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—
400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—
40
—
ns
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
—
ns
RX_CLK clock rise time, (20% to 80%)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time, (80% to 20%)
tMRXF
1.0
—
4.0
ns
Parameter/Condition
RX_CLK duty cycle
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
This figure provides the AC test load.
Z0 = 50 Ω
Output
RL = 50 Ω
LVDD/2
Figure 13. AC Test Load
This figure shows the MII receive AC timing diagram.
tMRXR
tMRX
RX_CLK
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRXF
Valid Data
tMRDVKH
tMRDXKH
Figure 14. MII Receive AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
30
Freescale Semiconductor
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
This table provides the RMII transmit AC timing specifications.
Table 31. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
tRMTKHDX
tRMTKHDV
2
—
—
—
10
ns
REF_CLK data clock rise time
tRMXR
1.0
—
4.0
ns
REF_CLK data clock fall time
tRMXF
1.0
—
4.0
ns
Parameter/Condition
REF_CLK clock
REF_CLK duty cycle
REF_CLK to RMII data TXD[1:0], TX_EN delay
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII
transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that,
in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
This figure shows the RMII transmit AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXH
tRMXF
TXD[1:0]
TX_EN
tRMTKHDX
Figure 15. RMII Transmit AC Timing Diagram
8.2.3.2
RMII Receive AC Timing Specifications
This table provides the RMII receive AC timing specifications.
Table 32. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
REF_CLK clock period
REF_CLK duty cycle
Symbol1
Min
Typ
Max
Unit
tRMX
—
20
—
ns
tRMXH/tRMX
35
—
65
%
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
31
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
Table 32. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
—
—
ns
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
—
—
ns
REF_CLK clock rise time
tRMXR
1.0
—
4.0
ns
REF_CLK clock fall time
tRMXF
1.0
—
4.0
ns
Parameter/Condition
Note:
1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII
receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock
reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect
to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
This figure provides the AC test load.
Z0 = 50 Ω
Output
RL = 50 Ω
LVDD/2
Figure 16. AC Test Load
This figure shows the RMII receive AC timing diagram.
tRMXR
tRMX
REF_CLK
tRMXF
tRMXH
RXD[1:0]
CRS_DV
RX_ER
Valid Data
tRMRDVKH
tRMRDXKH
Figure 17. RMII Receive AC Timing Diagram
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
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GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.4.1
TBI Transmit AC Timing Specifications
This table provides the TBI transmit AC timing specifications.
Table 33. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
Notes
tTTX
—
8.0
—
ns
—
tTTXH/tTTX
40
—
60
%
—
tTTKHDX
tTTKHDV
1.0
—
—
—
5.0
ns
3
GTX_CLK clock rise time, (20% to 80%)
tTTXR
—
—
1.0
ns
—
GTX_CLK clock fall time, (80% to 20%)
tTTXF
—
—
1.0
ns
—
GTX_CLK125 reference clock period
tG125
—
8.0
—
ns
2
tG125H/tG125
45
—
55
ns
—
Parameter/Condition
GTX_CLK clock period
GTX_CLK duty cycle
GTX_CLK to TBI data TCG[9:0] delay
GTX_CLK125 reference clock duty cycle
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
3. In rev. 2.0 silicon, due to errata, tTTKHDX minimum is 0.7 ns for UCC1. Refer to Errata QE_ENET19 in Chip Errata for the
MPC8360E, Rev. 1.
This figure shows the TBI transmit AC timing diagram.
tTTXR
tTTX
GTX_CLK
tTTXH
TXD[7:0]
TX_EN
TX_ER
tTTXF
tTTKHDX
Figure 18. TBI Transmit AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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33
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.4.2
TBI Receive AC Timing Specifications
This table provides the TBI receive AC timing specifications.
Table 34. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
Notes
tTRX
—
16.0
—
ns
—
PMA_RX_CLK skew
tSKTRX
7.5
—
8.5
ns
—
RX_CLK duty cycle
tTRXH/tTRX
40
—
60
%
—
RCG[9:0] setup time to rising PMA_RX_CLK
tTRDVKH
2.5
—
—
ns
2
RCG[9:0] hold time to rising PMA_RX_CLK
tTRDXKH
1.0
—
—
ns
2
RX_CLK clock rise time, VIL(min) to VIH(max)
tTRXR
0.7
—
2.4
ns
—
RX_CLK clock fall time, VIH(max) to VIL(min)
tTRXF
0.7
—
2.4
ns
—
Parameter/Condition
PMA_RX_CLK clock period
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K)
going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data
input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. Note that, in general,
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the
clock that is being skewed (TRX).
2. Setup and hold time of even numbered RCG are measured from riding edge of PMA_RX_CLK1. Setup and hold time of
odd numbered RCG are measured from riding edge of PMA_RX_CLK0.
This figure shows the TBI receive AC timing diagram.
tTRXR
tTRX
PMA_RX_CLK1
tTRXH
RCG[9:0]
tTRXF
Even RCG
Odd RCG
tTRDVKH
tTRDXKH
tSKTRX
PMA_RX_CLK0
tTRDXKH
tTRXH
tTRDVKH
Figure 19. TBI Receive AC Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.5
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Symbol1
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
tSKRGTKHDX
tSKRGTKHDV
–0.5
—
—
—
0.5
ns
7
Data to clock input skew (at receiver)
tSKRGDXKH
tSKRGDVKH
1.0
—
—
—
2.6
ns
2
tRGT
7.2
8.0
8.8
ns
3
Duty cycle for 1000Base-T
tRGTH/tRGT
45
50
55
%
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT
40
50
60
%
3, 5
Rise time (20–80%)
tRGTR
—
—
0.75
ns
—
Fall time (20–80%)
tRGTF
—
—
0.75
ns
—
GTX_CLK125 reference clock period
tG125
—
8.0
—
ns
6
tG125H/tG125
47
—
53
%
—
Parameter/Condition
Clock cycle duration
GTX_CLK125 reference clock duty cycle
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (Rx) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns can
be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Duty cycle reference is LVDD/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. In rev. 2.0 silicon, due to errata, tSKRGTKHDX minimum is –2.3 ns and tSKRGTKHDV maximum is 1 ns for UCC1, 1.2 ns for
UCC2 option 1, and 1.8 ns for UCC2 option 2. In rev. 2.1 silicon, due to errata, tSKRGTKHDX minimum is –0.65 ns for UCC2
option 1 and –0.9 for UCC2 option 2, and tSKRGTKHDV maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2
option 2. Refer to Errata QE_ENET10 in Chip Errata for the MPC8360E, Rev. 1. UCC1 does meet tSKRGTKHDX minimum for
rev. 2.1 silicon.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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35
Ethernet Management Interface Electrical Characteristics
This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGTKHDX
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXD[3:0]
TXD[8:5]
TXD[7:4]
TXD[4]
TXEN
TXD[9]
TXERR
tSKRGTKHDX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[3:0] RXD[7:4]
tSKRGTKHDX
RX_CTL
RXD[4]
RXDV
RXD[9]
RXERR
tSKRGTKHDX
RX_CLK
(At PHY)
Figure 20. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output)
and MDC (management data clock). The electrical characteristics for GMII, RGMII, TBI, and RTBI are specified in
Section 8.1, “Three-Speed Ethernet Controller (10/100/1000 Mbps)— GMII/MII/RMII/TBI/RGMII/RTBI Electrical
Characteristics.”
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC
are provided in this table.
Table 36. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Supply voltage (3.3 V)
Symbol
Conditions
Min
Max
Unit
OVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
OVDD = Min
2.10
OVDD + 0.3
V
Output low voltage
VOL
IOL = 1.0 mA
OVDD = Min
GND
0.50
V
Input high voltage
VIH
—
2.00
—
V
Input low voltage
VIL
—
—
0.80
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
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Ethernet Management Interface Electrical Characteristics
8.3.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 37. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V ± 10%.
Symbol1
Min
Typ
Max
Unit
Notes
MDC frequency
fMDC
—
2.5
—
MHz
2
MDC period
tMDC
—
400
—
ns
—
MDC clock pulse width high
tMDCH
32
—
—
ns
—
MDC to MDIO delay
tMDTKHDX
tMDTKHDV
10
—
—
—
110
ns
3
MDIO to MDC setup time
tMDRDVKH
10
—
—
ns
—
MDIO to MDC hold time
tMDRDXKH
0
—
—
ns
—
MDC rise time
tMDCR
—
—
10
ns
—
MDC fall time
tMDHF
—
—
10
ns
—
Parameter/Condition
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDRDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)
reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of
300 MHz, the delay is 63 ns).
This figure shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDHF
tMDCH
MDIO
(Input)
tMDRDVKH
tMDRDXKH
MDIO
(Output)
tMDTKHDX
Figure 21. MII Management Interface Timing Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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37
Local Bus DC Electrical Characteristics
8.3.3
IEEE 1588 Timer AC Specifications
This table provides the IEEE 1588 timer AC specifications.
Table 38. IEEE 1588 Timer AC Specifications
Parameter
Symbol
Min
Max
Unit
Notes
Timer clock frequency
tTMRCK
0
70
MHz
1
Input setup to timer clock
tTMRCKS
—
—
—
2, 3
Input hold from timer clock
tTMRCKH
—
—
—
2, 3
Output clock to output valid
tGCLKNV
0
6
ns
—
Timer alarm to output valid
tTMRAL
—
—
—
2
Notes:
1. The timer can operate on rtc_clock or tmr_clock. These clocks get muxed and any one of them can be selected. The
minimum and maximum requirement for both rtc_clock and tmr_clock are the same.
2. These are asynchronous signals.
3. Inputs need to be stable at least one TMR clock.
9
Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8360E/58E.
9.1
Local Bus DC Electrical Characteristics
This table provides the DC electrical characteristics for the local bus interface.
Table 39. Local Bus DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.4
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
IIN
—
±10
μA
Input current
9.2
Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device.
Table 40. Local Bus General Timing Parameters—DLL Enabled
Symbol1
Min
Max
Unit
Notes
tLBK
7.5
—
ns
2
Input setup to local bus clock (except LUPWAIT)
tLBIVKH1
1.7
—
ns
3, 4
LUPWAIT input setup to local bus clock
tLBIVKH2
1.9
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
tLBIXKH1
1.0
—
ns
3, 4
Parameter
Local bus cycle time
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Local Bus AC Electrical Specifications
Table 40. Local Bus General Timing Parameters—DLL Enabled (continued)
Symbol1
Min
Max
Unit
Notes
LUPWAIT input hold from local bus clock
tLBIXKH2
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3.0
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Local bus clock to LALE rise
tLBKHLR
—
4.5
ns
—
Local bus clock to output valid (except LAD/LDP and LALE)
tLBKHOV1
—
4.5
ns
—
Local bus clock to data valid for LAD/LDP
tLBKHOV2
—
4.5
ns
3
Local bus clock to address valid for LAD
tLBKHOV3
—
4.5
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
tLBKHOX1
1.0
—
ns
3
Output hold from local bus clock for LAD/LDP
tLBKHOX2
1.0
—
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
3.8
ns
8
Parameter
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect
to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN.
3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than
the load on LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the
load on LAD output pins.
7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
This table describes the general timing parameters of the local bus interface of the device.
Table 41. Local Bus General Timing Parameters—DLL Bypass Mode9
Symbol1
Min
Max
Unit
Notes
tLBK
15
—
ns
2
Input setup to local bus clock
tLBIVKH
7
—
ns
3, 4
Input hold from local bus clock
tLBIXKH
1.0
—
ns
3, 4
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT1
1.5
—
ns
5
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT2
3
—
ns
6
LALE output fall to LAD output transition (LATCH hold time)
tLBOTOT3
2.5
—
ns
7
Parameter
Local bus cycle time
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
39
Local Bus AC Electrical Specifications
Table 41. Local Bus General Timing Parameters—DLL Bypass Mode9 (continued)
Symbol1
Min
Max
Unit
Notes
Local bus clock to output valid
tLBKHOV
—
3
ns
3
Local bus clock to output high impedance for LAD/LDP
tLBKHOZ
—
4
ns
8
Parameter
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one (1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect
to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on LALE output pin is at least 10 pF less than
the load on LAD output pins.
6. tLBOTOT2 should be used when RCWH[LALE] is set and when the load on LALE output pin is at least 10 pF less than the
load on LAD output pins.
7. tLBOTOT3 should be used when RCWH[LALE] is set and when the load on LALE output pin equals to the load on LAD output
pins.
8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.
This figure provides the AC test load for the local bus.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 22. Local Bus C Test Load
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Local Bus AC Electrical Specifications
These figures show the local bus signals.
LSYNC_IN
tLBIVKH
tLBIXKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOV
tLBKHOX
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV
tLBKHOZ
tLBKHOX
Output (Address) Signal:
LAD[0:31]
tLBKHLR
tLBOTOT
LALE
Figure 23. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
LCLK[n]
tLBIVKH
tLBIXKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIVKH
tLBIXKH
Input Signal:
LGTA
tLBIXKH
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
LA[27:31]/LBCTL/LBCKE/LOE/
tLBKHOV
tLBKHOV
tLBKHOZ
Output Signals:
LAD[0:31]/LDP[0:3]
tLBOTOT
LALE
Figure 24. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
41
Local Bus AC Electrical Specifications
LSYNC_IN
T1
T3
tLBKHOV1
tLBKHOZ1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH2
tLBIXKH2
UPM Mode Input Signal:
LUPWAIT
tLBIVKH1
tLBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV1
tLBKHOZ1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Enabled)
LCLK
T1
T3
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 26. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Local Bus AC Electrical Specifications
LCLK
T1
T2
T3
T4
tLBKHOV
tLBKHOZ
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIVKH
tLBIXKH
UPM Mode Input Signal:
LUPWAIT
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
tLBKHOV
tLBIXKH
tLBKHOZ
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 27. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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JTAG DC Electrical Characteristics
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ1
tLBKHOV1
GPCM Mode Output Signals:
LCS[0:3]/LWE
tLBIXKH2
tLBIVKH2
UPM Mode Input Signal:
LUPWAIT
tLBIXKH1
tLBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ1
tLBKHOV1
UPM Mode Output Signals:
LCS[0:3]/LBS[0:3]/LGPL[0:5]
Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (DLL Enabled)
10
JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8360E/58E.
10.1
JTAG DC Electrical Characteristics
This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the device.
Table 42. JTAG interface DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.5
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
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JTAG AC Electrical Characteristics
10.2
JTAG AC Electrical Characteristics
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
This table provides the JTAG AC timing specifications as defined in Figure 30 through Figure 33.
Table 43. JTAG AC Timing Specifications (Independent of CLKIN)1
At recommended operating conditions (see Table 2).
Symbol 2
Min
Max
Unit
Notes
JTAG external clock frequency of operation
fJTG
0
33.3
MHz
—
JTAG external clock cycle time
tJTG
30
—
ns
—
JTAG external clock duty cycle
tJTKHKL/tJTG
45
55
%
—
JTAG external clock rise and fall times
tJTGR & tJTGF
0
2
ns
—
tTRST
25
—
ns
3
ns
4
Boundary-scan data
TMS, TDI
tJTDVKH
tJTIVKH
4
4
—
—
ns
4
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
ns
5
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
ns
5
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
JTAG external clock to output high impedance:
Boundary-scan data
TDO
ns
5, 6
tJTKLDZ
tJTKLOZ
2
2
19
9
Parameter
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Figure 22). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect
to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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45
JTAG AC Electrical Characteristics
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 29. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
VM
VM
tJTGR
tJTKHKL
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 30. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 31. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
JTAG
External Clock
VM
VM
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 32. Boundary-Scan Timing Diagram
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I2C DC Electrical Characteristics
This figure provides the test access port timing diagram.
JTAG
External Clock
VM
VM
tJTIVKH
tJTIXKH
Input
Data Valid
TDI, TMS
tJTKLOV
tJTKLOX
TDO
Output Data Valid
tJTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 33. Test Access Port Timing Diagram
11
I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8360E/58E.
11.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface of the device.
Table 44. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 10%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7 × OVDD
OVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3 × OVDD
V
—
Low level output voltage
VOL
0
0.4
V
1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1 × CB
250
ns
2
Pulse width of spikes which must be suppressed by the input
filter
tI2KHKL
0
50
ns
3
Capacitance for each I/O pin
CI
—
10
pF
—
Input current (0 V ≤VIN ≤OVDD)
IIN
—
±10
μA
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8360E Integrated Communications Processor Reference Manual for information on the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
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47
I2C AC Electrical Specifications
11.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C interface of the device.
Table 45. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 44).
Symbol1
Min
Max
Unit
Note
SCL clock frequency
fI2C
0
400
kHz
2
Low period of the SCL clock
tI2CL
1.3
—
μs
—
High period of the SCL clock
tI2CH
0.6
—
μs
—
Setup time for a repeated START condition
tI2SVKH
0.6
—
μs
—
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
tI2SXKL
0.6
—
μs
—
Data setup time
tI2DVKH
100
—
ns
3
μs
—
—
02
—
0.93
Parameter
tI2DXKL
Data hold time:
CBUS compatible masters
I2C bus devices
Rise time of both SDA and SCL signals
tI2CR
20 + 0.1 Cb4
300
ns
—
Fall time of both SDA and SCL signals
tI2CF
20 + 0.1 Cb4
300
ns
—
Set-up time for STOP condition
tI2PVKH
0.6
—
μs
—
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
μs
—
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1 × OVDD
—
V
—
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2 × OVDD
—
V
—
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional
block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V)
relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing
(I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock
reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the
data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going
to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
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PCI DC Electrical Characteristics
This figure provides the AC test load for the I2C.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Figure 34. I2C AC Test Load
This figure shows the AC timing diagram for the I2C bus.
SDA
tI2CF
tI2DVKH
tI2CL
tI2KHKL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
tI2CH
tI2DXKL
S
tI2SVKH
tI2PVKH
Sr
P
S
2
Figure 35. I C Bus AC Timing Diagram
12
PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8360E/58E.
12.1
PCI DC Electrical Characteristics
This table provides the DC electrical characteristics for the PCI interface of the device.
Table 46. PCI DC Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Max
Unit
High-level input voltage
VIH
VOUT ≥ VOH (min) or
0.5 × OVDD
OVDD + 0.5
V
Low-level input voltage
VIL
VOUT ≤VOL (max)
-0.5
0.3 × OVDD
V
High-level output voltage
VOH
IOH = –500 μA
0.9 × OVDD
—
V
Low-level output voltage
VOL
IOL = 1500 μA
—
0.1 × OVDD
V
IIN
0 V ≤VIN1 ≤OVDD
—
±10
μA
Input current
12.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the PCI_CLK or PCI_SYNC_IN
signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. This table provides
the PCI AC timing specifications at 66 MHz.
.
Table 47. PCI AC Timing Specifications at 66 MHz
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
6.0
ns
2, 5
Output hold from clock
tPCKHOX
1
—
ns
2
Parameter
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PCI AC Electrical Specifications
Table 47. PCI AC Timing Specifications at 66 MHz (continued)
Symbol1
Min
Max
Unit
Notes
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to clock
tPCIVKH
3.0
—
ns
2, 4
Input hold from clock
tPCIXKH
0.3
—
ns
2, 4, 6
Parameter
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing
(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset
(R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev. 2.0 silicon, due to errata, tPCIHOV maximum is 6.6 ns. Refer to Errata PCI21 in Chip Errata for the MPC8360E, Rev. 1.
6. In rev. 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.
Table 48. PCI AC Timing Specifications at 33 MHz
Symbol1
Min
Max
Unit
Notes
Clock to output valid
tPCKHOV
—
11
ns
2
Output hold from clock
tPCKHOX
2
—
ns
2
Clock to output high impedance
tPCKHOZ
—
14
ns
2, 3
Input setup to clock
tPCIVKH
7.0
—
ns
2, 2
Input hold from clock
tPCIXKH
0.3
—
ns
2, 4, 5
Parameter
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS,
reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time
hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. In rev. 2.0 silicon, due to errata, tPCIXKH minimum is 1 ns. Refer to Errata PCI17 in Chip Errata for the MPC8360E, Rev. 1.
This figure provides the AC test load for PCI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 36. PCI AC Test Load
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Timers DC Electrical Characteristics
This figure shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 37. PCI Input AC Timing Measurement Conditions
This figure shows the PCI output AC timing conditions.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 38. PCI Output AC Timing Measurement Condition
13
Timers
This section describes the DC and AC electrical specifications for the timers of the MPC8360E/58E.
13.1
Timers DC Electrical Characteristics
This table provides the DC electrical characteristics for the device timer pins, including TIN, TOUT, TGATE, and RTC_CLK.
Table 49. Timers DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
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51
Timers AC Timing Specifications
13.2
Timers AC Timing Specifications
This table provides the timer input and output AC timing specifications.
Table 50. Timers Input AC Timing Specifications1
Characteristic
Timers inputs—minimum pulse width
Symbol2
Typ
Unit
tTIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation.
This figure provides the AC test load for the timers.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 39. Timers AC Test Load
14
GPIO
This section describes the DC and AC electrical specifications for the GPIO of the MPC8360E/58E.
14.1
GPIO DC Electrical Characteristics
This table provides the DC electrical characteristics for the device GPIO.
Table 51. GPIO DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Notes
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
1
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
1
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
1
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
1
Input low voltage
VIL
—
–0.3
0.8
V
—
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
—
Note:
1. This specification applies when operating from 3.3-V supply.
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GPIO AC Timing Specifications
14.2
GPIO AC Timing Specifications
This table provides the GPIO input and output AC timing specifications.
Table 52. GPIO Input AC Timing Specifications1
Characteristic
GPIO inputs—minimum pulse width
Symbol2
Typ
Unit
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
This figure provides the AC test load for the GPIO.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
Figure 40. GPIO AC Test Load
15
IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8360E/58E.
15.1
IPIC DC Electrical Characteristics
This table provides the DC electrical characteristics for the external interrupt pins of the IPIC.
Table 53. IPIC DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
—
—
±10
μA
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Notes:
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT, and CE ports Interrupts.
2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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IPIC AC Timing Specifications
15.2
IPIC AC Timing Specifications
This table provides the IPIC input and output AC timing specifications.
Table 54. IPIC Input AC Timing Specifications1
Characteristic
IPIC inputs—minimum pulse width
Symbol2
Min
Unit
tPIWID
20
ns
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when
working in edge triggered mode.
16
SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8360E/58E.
16.1
SPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device SPI.
Table 55. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 6.0 mA
—
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.4
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
16.2
SPI AC Timing Specifications
This table and provide the SPI input and output AC timing specifications.
Table 56. SPI AC Timing Specifications1
Symbol2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOX
tNIKHOV
0.3
—
—
8
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOX
tNEKHOV
2
—
—
8
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
8
—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0
—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4
—
ns
Characteristic
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SPI AC Timing Specifications
Table 56. SPI AC Timing Specifications1
Characteristic
SPI inputs—Slave mode (external clock) input hold time
Symbol2
Min
Max
Unit
tNEIXKH
2
—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
This figure provides the AC test load for the SPI.
Z0 = 50 Ω
Output
RL = 50 Ω
OVDD/2
Figure 41. SPI AC Test Load
These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge
of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
This figure shows the SPI timing in slave mode (external clock).
SPICLK (Input)
Input Signals:
SPIMOSI
(See Note)
tNEIVKH
tNEIXKH
tNEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 42. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in Master mode (internal clock).
SPICLK (Output)
Input Signals:
SPIMISO
(See Note)
tNIIVKH
Output Signals:
SPIMOSI
(See Note)
tNIIXKH
tNIKHOV
Note: The clock edge is selectable on SPI.
Figure 43. SPI AC Timing in Master Mode (Internal Clock) Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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TDM/SI DC Electrical Characteristics
17
TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the
MPC8360E/58E.
17.1
TDM/SI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device TDM/SI.
Table 57. TDM/SI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
17.2
TDM/SI AC Timing Specifications
This table provides the TDM/SI input and output AC timing specifications.
Table 58. TDM/SI AC Timing Specifications1
Symbol2
Min
Max3
Unit
TDM/SI outputs—External clock delay
tSEKHOV
2
10
ns
TDM/SI outputs—External clock high impedance
tSEKHOX
2
10
ns
TDM/SI inputs—External clock input setup time
tSEIVKH
5
—
ns
TDM/SI inputs—External clock input hold time
tSEIXKH
2
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI
outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. Timings are measured from the positive or negative edge of the clock, according to SIxMR [CE] and SITXCEI[TXCEIx].
Refer MPC8360E Integrated Communications Processor Reference Manual for more details.
This figure provides the AC test load for the TDM/SI.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 44. TDM/SI AC Test Load
Figure 45 represents the AC timing from Table 56. Note that although the specifications generally reference the rising edge of
the clock, these AC timing diagrams also apply when the falling edge is the active edge.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
UTOPIA/POS
This figure shows the TDM/SI timing with external clock.
TDM/SICLK (Input)
tSEIXKH
tSEIVKH
Input Signals:
TDM/SI
(See Note)
tSEKHOV
Output Signals:
TDM/SI
(See Note)
tSEKHOX
Note: The clock edge is selectable on TDM/SI
Figure 45. TDM/SI AC Timing (External Clock) Diagram
17.3
UTOPIA/POS
This section describes the DC and AC electrical specifications for the UTOPIA/POS of the MPC8360E/58E.
17.4
UTOPIA/POS DC Electrical Characteristics
This table provides the DC electrical characteristics for the device UTOPIA.
Table 59. UTOPIA DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –8.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 8.0 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
17.5
UTOPIA/POS AC Timing Specifications
This table provides the UTOPIA input and output AC timing specifications.
Table 60. UTOPIA AC Timing Specifications1
Symbol2
Min
Max
Unit
Notes
UTOPIA outputs—Internal clock delay
tUIKHOV
0
11.5
ns
—
UTOPIA outputs—External clock delay
tUEKHOV
1
11.6
ns
—
UTOPIA outputs—Internal clock high impedance
tUIKHOX
0
8.0
ns
—
UTOPIA outputs—External clock high impedance
tUEKHOX
1
10.0
ns
—
UTOPIA inputs—Internal clock input setup time
tUIIVKH
6
—
ns
—
UTOPIA inputs—External clock input setup time
tUEIVKH
4
—
ns
3
Characteristic
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
57
UTOPIA/POS AC Timing Specifications
Table 60. UTOPIA AC Timing Specifications1 (continued)
Symbol2
Min
Max
Unit
Notes
UTOPIA inputs—Internal clock input hold time
tUIIXKH
2.4
—
ns
—
UTOPIA inputs—External clock input hold time
tUEIXKH
1
—
ns
3
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUIKHOX symbolizes the UTOPIA
outputs internal timing (UI) for the time tUTOPIA memory clock reference (K) goes from the high state (H) until outputs (O)
are invalid (X).
3. In rev. 2.0 silicon, due to errata, tUEIVKH minimum is 4.3 ns and tUEIXKH minimum is 1.4 ns under specific conditions. Refer
to Errata QE_UPC3 in Chip Errata for the MPC8360E, Rev. 1.
This figure provides the AC test load for the UTOPIA.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 46. UTOPIA AC Test Load
These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge
of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
This figure shows the UTOPIA timing with external clock.
UtopiaCLK (Input)
tUEIVKH
tUEIXKH
Input Signals:
UTOPIA
tUEKHOV
Output Signals:
UTOPIA
tUEKHOX
Figure 47. UTOPIA AC Timing (External Clock) Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
This figure shows the UTOPIA timing with internal clock.
UtopiaCLK (Output)
tUIIXKH
tUIIVKH
Input Signals:
UTOPIA
tUIKHOV
Output Signals:
UTOPIA
tUIKHOX
Figure 48. UTOPIA AC Timing (Internal Clock) Diagram
18
HDLC, BISYNC, Transparent, and Synchronous
UART
This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC,
transparent, and synchronous UART protocols of the MPC8360E/58E.
18.1
HDLC, BISYNC, Transparent, and Synchronous UART DC
Electrical Characteristics
This table provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and synchronous UART
protocols.
Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—
2.0
OVDD + 0.3
V
Input low voltage
VIL
—
–0.3
0.8
V
Input current
IIN
0 V ≤VIN ≤OVDD
—
±10
μA
18.2
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
These tables provide the input and output AC timing specifications for HDLC, BISYNC, transparent, and synchronous UART
protocols.
Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tHIKHOV
0
11.2
ns
Outputs—External clock delay
tHEKHOV
1
10.8
ns
Characteristic
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
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HDLC, BISYNC, Transparent, and Synchronous UART AC Timing Specifications
Table 62. HDLC, BISYNC, and Transparent AC Timing Specifications1 (continued)
Symbol2
Min
Max
Unit
Outputs—Internal clock high impedance
tHIKHOX
-0.5
5.5
ns
Outputs—External clock high impedance
tHEKHOX
1
8
ns
Inputs—Internal clock input setup time
tHIIVKH
8.5
—
ns
Inputs—External clock input setup time
tHEIVKH
4
—
ns
Inputs—Internal clock input hold time
tHIIXKH
1.4
—
ns
Inputs—External clock input hold time
tHEIXKH
1
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 63. Synchronous UART AC Timing Specifications1
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tUAIKHOV
0
11.3
ns
Outputs—External clock delay
tUAEKHOV
1
14
ns
Outputs—Internal clock high impedance
tUAIKHOX
0
11
ns
Outputs—External clock high impedance
tUAEKHOX
1
14
ns
Inputs—Internal clock input setup time
tUAIIVKH
6
—
ns
Inputs—External clock input setup time
tUAEIVKH
8
—
ns
Inputs—Internal clock input hold time
tUAIIXKH
1
—
ns
Inputs—External clock input hold time
tUAEIXKH
1
—
ns
Characteristic
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
This figure provides the AC test load.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 49. AC Test Load
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
AC Test Load
18.3
AC Test Load
These figures represent the AC timing from Table 62 and Table 63. Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
This figure shows the timing with external clock.
Serial CLK (Input)
tHEIXKH
tHEIVKH
Input Signals:
(See Note)
tHEKHOV
Output Signals:
(See Note)
Note: The clock edge is selectable.
tHEKHOX
Figure 50. AC Timing (External Clock) Diagram
This figure shows the timing with internal clock.
Serial CLK (Output)
tHIIVKH
tHIIXKH
Input Signals:
(See Note)
tHIKHOV
Output Signals:
(See Note)
tHIKHOX
Note: The clock edge is selectable.
Figure 51. AC Timing (Internal Clock) Diagram
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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61
USB DC Electrical Characteristics
19
USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8360E/58E.
19.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the USB interface.
Table 64. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2
OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μA
VOH
OVDD – 0.4
—
V
Low-level output voltage, IOL = 100 μA
VOL
—
0.2
V
IIN
—
±10
μA
Input current
19.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 65. USB General Timing Parameters
Symbol1
Min
Max
Unit
USB clock cycle time
tUSCK
20.83
—
ns
Full speed 48 MHz
—
USB clock cycle time
tUSCK
166.67
—
ns
Low speed 6 MHz
—
tUSTSPN
—
5
ns
—
2
Skew among RXP, RXN, and RXD
tUSRSPND
—
10
ns
Full speed transitions
2
Skew among RXP, RXN, and RXD
tUSRPND
—
100
ns
Low speed transitions
2
Parameter
Skew between TXP and TXN
Notes
Note
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(state)(signal) for
receive signals and t(first two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND
symbolizes USB timing (US) for the USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also,
tUSTSPN symbolizes USB timing (US) for the USB transmit signals skew (TS) between TXP and TXN (PN).
2. Skew measurements are done at OVDD/2 of the rising or falling edge of the signals.
This figure provide the AC test load for the USB.
Output
Z0 = 50 Ω
RL = 50 Ω
OVDD/2
Figure 52. USB AC Test Load
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Package Parameters for the TBGA Package
20
Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8360E/58E is available in a tape ball grid
array (TBGA), see Section 20.1, “Package Parameters for the TBGA Package,” and Section 20.2, “Mechanical Dimensions of
the TBGA Package,” for information on the package.
20.1
Package Parameters for the TBGA Package
The package parameters for rev. 2.0 silicon are as provided in the following list. The package type is 37.5 mm × 37.5 mm, 740
tape ball grid array (TBGA).
Package outline
Interconnects
Pitch
Module height (typical)
Solder Balls
Ball diameter (typical)
37.5 mm × 37.5 mm
740
1.00 mm
1.46 mm
62 Sn/36 Pb/2 Ag (ZU package)
95.5 Sn/0.5 Cu/4Ag (VV package)
0.64 mm
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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63
Mechanical Dimensions of the TBGA Package
20.2
Mechanical Dimensions of the TBGA Package
This figure depicts the mechanical dimensions and bottom surface nomenclature of the device, 740-TBGA package.
Figure 53. Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Pinout Listings
20.3
Pinout Listings
Refer to AN3097, “MPC8360/MPC8358E PowerQUICC Design Checklist,” for proper pin termination and usage.
This table shows the pin list of the MPC8360E TBGA package.
Table 66. MPC8360E TBGA Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
Primary DDR SDRAM Memory Controller Interface
MEMC1_MDQ[0:31]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32,
AM36, AN37, AN35, AR34, AT34, AP37, AP36,
AR36, AT35, AP34, AR32, AP32, AM31, AN33,
AM34, AM33, AM30, AP31, AM27, AR30, AT32,
AN29, AP29, AN27, AR29
I/O
GVDD
—
MEMC1_MDQ[32:63]/
MEMC2_MDQ[0:31]
AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6,
AP6, AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5,
AP3, AN3, AN5, AL5, AN4, AM2, AL2, AH5, AK3,
AJ2, AJ3, AH4, AK4, AH3
I/O
GVDD
—
MEMC1_MECC[0:4]/
MSRCID[0:4]
AP24, AN22, AM19, AN19, AM24
I/O
GVDD
—
MEMC1_MECC[5]/
MDVAL
AM23
I/O
GVDD
—
MEMC1_MECC[6:7]
AM22, AN18
I/O
GVDD
—
MEMC1_MDM[0:3]
AL36, AN34, AP33, AN28
O
GVDD
—
MEMC1_MDM[4:7]/
MEMC2_MDM[0:3]
AT9, AU4, AM3, AJ6
O
GVDD
—
MEMC1_MDM[8]
AP27
O
GVDD
—
MEMC1_MDQS[0:3]
AK35, AP35, AN31, AM26
I/O
GVDD
—
MEMC1_MDQS[4:7]/
MEMC2_MDQS[0:3]
AT8, AU3, AL4, AJ5
I/O
GVDD
—
MEMC1_MDQS[8]
AP26
I/O
GVDD
—
MEMC1_MBA[0:1]
AU29, AU30
O
GVDD
—
MEMC1_MBA[2]
AT30
O
GVDD
—
MEMC1_MA[0:14]
AU21, AP22, AP21, AT21, AU25, AU26, AT23,
AR26, AU24, AR23, AR28, AU23, AR22, AU20,
AR18
O
GVDD
—
MEMC1_MODT[0:1]
AG33, AJ36
O
GVDD
6
MEMC1_MODT[2:3]/
MEMC2_MODT[0:1]
AT1, AK2
O
GVDD
6
MEMC1_MWE
AT26
O
GVDD
—
MEMC1_MRAS
AT29
O
GVDD
—
MEMC1_MCAS
AT24
O
GVDD
—
MEMC1_MCS[0:1]
AU27, AT27
O
GVDD
—
MEMC1_MCS[2:3]/
MEMC2_MCS[0:1]
AU8, AU7
O
GVDD
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
65
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
MEMC1_MCKE[0:1]
AL32, AU33
O
GVDD
3
MEMC1_MCK[0:1]
AK37, AT37
O
GVDD
—
MEMC1_MCK[2:3]/
MEMC2_MCK[0:1]
AN1, AR2
O
GVDD
—
MEMC1_MCK[4:5]/
MEMC2_MCKE[0:1]
AN25, AK1
O
GVDD
—
MEMC1_MCK[0:1]
AL37, AT36
O
GVDD
—
MEMC1_MCK[2:3]/
MEMC2_MCK[0:1]
AP2, AT2
O
GVDD
—
MEMC1_MCK[4]/
MEMC2_MDM[8]
AN24
O
GVDD
—
MEMC1_MCK[5]/
MEMC2_MDQS[8]
AL1
O
GVDD
—
MDIC[0:1]
AH6, AP30
I/O
GVDD
10
Secondary DDR SDRAM Memory Controller Interface
MEMC2_MECC[0:7]
AN16, AP18, AM16, AM17, AN17, AP13, AP15,
AN13
I/O
GVDD
—
MEMC2_MBA[0:2]
AU12, AU15, AU13
O
GVDD
—
MEMC2_MA[0:14]
AT12, AP11, AT13, AT14, AR13, AR15, AR16,
AT16, AT18, AT17, AP10, AR20, AR17, AR14,
AR11
O
GVDD
—
MEMC2_MWE
AU10
O
GVDD
—
MEMC2_MRAS
AT11
O
GVDD
—
MEMC2_MCAS
AU11
O
GVDD
—
PCI
PCI_INTA/IRQ_OUT/CE_PF[5]
A20
I/O
LVDD2
2
PCI_RESET_OUT/CE_PF[6]
E19
I/O
LVDD2
—
PCI_AD[31:30]/CE_PG[31:30]
D20, D21
I/O
LVDD2
—
PCI_AD[29:25]/CE_PG[29:25]
A24, B23, C23, E23, A26
I/O
OVDD
—
PCI_AD[24]/CE_PG[24]
B21
I/O
LVDD2
—
PCI_AD[23:0]/CE_PG[23:0]
C24, C25, D25, B25, E24, F24, A27, A28, F27, A30,
C30, D30, E29, B31, C31, D31, D32, A32, C33,
B33, F30, E31, A34, D33
I/O
OVDD
—
PCI_C/BE[3:0]/CE_PF[10:7]
E22, B26, E28, F28
I/O
OVDD
—
PCI_PAR/CE_PF[11]
D28
I/O
OVDD
—
PCI_FRAME/CE_PF[12]
D26
I/O
OVDD
5
PCI_TRDY/CE_PF[13]
C27
I/O
OVDD
5
PCI_IRDY/CE_PF[14]
C28
I/O
OVDD
5
PCI_STOP/CE_PF[15]
B28
I/O
OVDD
5
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI_DEVSEL/CE_PF[16]
E26
I/O
OVDD
5
PCI_IDSEL/CE_PF[17]
F22
I/O
OVDD
—
PCI_SERR/CE_PF[18]
B29
I/O
OVDD
5
PCI_PERR/CE_PF[19]
A29
I/O
OVDD
5
PCI_REQ[0]/CE_PF[20]
F19
I/O
LVDD2
—
PCI_REQ[1]/CPCI_HS_ES/
CE_PF[21]
A21
I/O
LVDD2
—
PCI_REQ[2]/CE_PF[22]
C21
I/O
LVDD2
—
PCI_GNT[0]/CE_PF[23]
E20
I/O
LVDD2
—
PCI_GNT[1]/CPCI1_HS_LED/
CE_PF[24]
B20
I/O
LVDD2
—
PCI_GNT[2]/CPCI1_HS_ENUM/
CE_PF[25]
C20
I/O
LVDD2
—
PCI_MODE
D36
I
OVDD
—
M66EN/CE_PF[4]
B37
I/O
OVDD
—
Local Bus Controller Interface
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35,
R34, R33, T37, T35, T34, T33, U37, T32, U36, U34,
V36, V35, W37, W35, V33, V32, W34, Y36, W32,
AA37, Y33, AA35, AA34
I/O
OVDD
—
LDP[0]/CKSTOP_OUT
AB37
I/O
OVDD
—
LDP[1]/CKSTOP_IN
AB36
I/O
OVDD
—
LDP[2]/LCS[6]
AB35
I/O
OVDD
—
LDP[3]/LCS[7]
AA33
I/O
OVDD
—
LA[27:31]
AC37, AA32, AC36, AC34, AD36
O
OVDD
—
LCS[0:5]
AD33, AG37, AF34, AE33, AD32, AH37
O
OVDD
—
LWE[0:3]/LSDDQM[0:3]/LBS[0:3]
AG35, AG34, AH36, AE32
O
OVDD
—
LBCTL
AD35
O
OVDD
—
LALE
M37
O
OVDD
—
LGPL0/LSDA10/cfg_reset_source0
AB32
I/O
OVDD
—
LGPL1/LSDWE/cfg_reset_source1
AE37
I/O
OVDD
—
LGPL2/LSDRAS/LOE
AC33
O
OVDD
—
LGPL3/LSDCAS/cfg_reset_source2
AD34
I/O
OVDD
—
LGPL4/LGTA/LUPWAIT/LPBSE
AE35
I/O
OVDD
—
LGPL5/cfg_clkin_div
AF36
I/O
OVDD
—
LCKE
G36
O
OVDD
—
LCLK[0]
J33
O
OVDD
—
LCLK[1]/LCS[6]
J34
O
OVDD
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
67
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
LCLK[2]/LCS[7]
G37
O
OVDD
—
LSYNC_OUT
F34
O
OVDD
—
LSYNC_IN
G35
I
OVDD
—
Programmable Interrupt Controller
MCP_OUT
E34
O
OVDD
2
IRQ0/MCP_IN
C37
I
OVDD
—
IRQ[1]/M1SRCID[4]/M2SRCID[4]/
LSRCID[4]
F35
I/O
OVDD
—
IRQ[2]/M1DVAL/M2DVAL/LDVAL
F36
I/O
OVDD
—
IRQ[3]/CORE_SRESET
H34
I/O
OVDD
—
IRQ[4:5]
G33, G32
I/O
OVDD
—
IRQ[6]/LCS[6]/CKSTOP_OUT
E35
I/O
OVDD
—
IRQ[7]/LCS[7]/CKSTOP_IN
H36
I/O
OVDD
—
DUART
UART1_SOUT/M1SRCID[0]/
M2SRCID[0]/LSRCID[0]
E32
O
OVDD
—
UART1_SIN/M1SRCID[1]/
M2SRCID[1]/LSRCID[1]
B34
I/O
OVDD
—
UART1_CTS/M1SRCID[2]/
M2SRCID[2]/LSRCID[2]
C34
I/O
OVDD
—
UART1_RTS/M1SRCID[3]/
M2SRCID[3]/LSRCID[3]
A35
O
OVDD
—
I2C Interface
IIC1_SDA
D34
I/O
OVDD
2
IIC1_SCL
B35
I/O
OVDD
2
IIC2_SDA
E33
I/O
OVDD
2
IIC2_SCL
C35
I/O
OVDD
2
QUICC Engine Block
CE_PA[0]
F8
I/O
LVDD0
—
CE_PA[1:2]
AH1, AG5
I/O
OVDD
—
CE_PA[3:7]
F6, D4, C3, E5, A3
I/O
LVDD0
—
CE_PA[8]
AG3
I/O
OVDD
—
CE_PA[9:12]
F7, B3, E6, B4
I/O
LVDD0
—
CE_PA[13:14]
AG1, AF6
I/O
OVDD
—
CE_PA[15]
B2
I/O
LVDD0
—
CE_PA[16]
AF4
I/O
OVDD
—
CE_PA[17:21]
B16, A16, E17, A17, B17
I/O
LVDD1
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
CE_PA[22]
AF3
I/O
OVDD
—
CE_PA[23:26]
C18, D18, E18, A18
I/O
LVDD1
—
CE_PA[27:28]
AF2, AE6
I/O
OVDD
—
CE_PA[29]
B19
I/O
LVDD1
—
CE_PA[30]
AE5
I/O
OVDD
—
CE_PA[31]
F16
I/O
LVDD1
—
CE_PB[0:27]
AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2,
AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4,
Y3, Y2, Y1, W6, W5, W2, V5, V3, V2
I/O
OVDD
—
CE_PC[0:1]
V1, U6
I/O
OVDD
—
CE_PC[2:3]
C16, A15
I/O
LVDD1
—
CE_PC[4:6]
U4, U3, T6
I/O
OVDD
—
CE_PC[7]
C19
I/O
LVDD2
—
CE_PC[8:9]
A4, C5
I/O
LVDD0
—
CE_PC[10:30]
T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10,
C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2
I/O
OVDD
—
CE_PD[0:27]
E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8,
B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1,
F2, G3, H4
I/O
OVDD
—
CE_PE[0:31]
K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6,
P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6,
L1, L2, L4, E14, C13, C14, B13
I/O
OVDD
—
CE_PF[0:3]
F14, D13, A12, A11
I/O
OVDD
—
Clocks
PCI_CLK_OUT[0]/CE_PF[26]
B22
I/O
LVDD2
—
PCI_CLK_OUT[1:2]/CE_PF[27:28]
D22, A23
I/O
OVDD
—
CLKIN
E37
I
OVDD
—
PCI_CLOCK/PCI_SYNC_IN
M36
I
OVDD
—
PCI_SYNC_OUT/CE_PF[29]
D37
I/O
OVDD
3
JTAG
TCK
K33
I
OVDD
—
TDI
K34
I
OVDD
4
TDO
H37
O
OVDD
3
TMS
J36
I
OVDD
4
TRST
L32
I
OVDD
4
Test
TEST
L35
I
OVDD
7
TEST_SEL
AU34
I
GVDD
7
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
69
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
O
OVDD
—
PMC
QUIESCE
B36
System Control
PORESET
L37
I
OVDD
—
HRESET
L36
I/O
OVDD
1
SRESET
M33
I/O
OVDD
2
Thermal Management
THERM0
AP19
I
GVDD
—
THERM1
AT31
I
GVDD
—
Power and Ground Signals
AVDD1
K35
Power for
LBIU DLL
(1.2 V)
AVDD1
—
AVDD2
K36
Power for
CE PLL
(1.2 V)
AVDD2
—
AVDD5
AM29
Power for
e300 PLL
(1.2 V)
AVDD5
—
AVDD6
K37
Power for
system
PLL (1.2 V)
AVDD6
—
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7,
B12, B24, B27, B30, C4, C6, C9, C15, C26, C32,
D3, D8, D11, D14, D17, D19, D23, D27, E7, E13,
E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4,
J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37,
P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1,
W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35,
AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6,
AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36,
AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,
AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9,
AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19,
AT20, AT25, AU14, AU22, AU28, AU35
—
—
—
GVDD
AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36,
AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10,
AN11, AN12, AN14, AN32, AN36, AP5, AP23,
AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27,
AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16,
AU31, AU36
Power for
DDR
DRAM I/O
voltage
(2.5 or
1.8 V)
GVDD
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
LVDD0
D5, D6
Power for
UCC1
Ethernet
interface
(2.5 V,
3.3 V)
LVDD0
—
LVDD1
C17, D16
Power for
UCC2
Ethernet
interface
option 1
(2.5 V,
3.3 V)
LVDD1
9
LVDD2
B18, E21
Power for
UCC2
Ethernet
interface
option 2
(2.5 V,
3.3 V)
LVDD2
9
VDD
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20,
F21, F23, F25, F26, F29, F31, F32, F33, G6, J6,
K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32,
AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9,
AM10, AM11, AM12, AM13, AM14, AM15, AM18,
AM21, AM25, AM28, AM32, AN15, AN21, AN26,
AU9, AU17
Power for
core
(1.2 V)
VDD
—
OVDD
A10, B9, B15, B32, C1, C12, C22, C29, D24, E3,
E10, E27, G4, H35, J1, J35, K2, M4, N3, N34, R2,
R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1,
AA36, AB2, AB34
PCI,
10/100
Ethernet,
and other
standard
(3.3 V)
OVDD
—
MVREF1
AN20
I
DDR
reference
voltage
—
MVREF2
AU32
I
DDR
reference
voltage
—
SPARE1
B11
I/O
OVDD
8
SPARE3
AH32
—
GVDD
8
SPARE4
AU18
—
GVDD
7
SPARE5
AP1
—
GVDD
8
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
71
Pinout Listings
Table 66. MPC8360E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
—
—
—
No Connect
NC
AM20, AU19
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. Refer to MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual section on “RGMII Pins,”
for information about the two UCC2 Ethernet interface options.
10.It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
This table shows the pin list of the MPC8358E TBGA package.
Table 67. MPC8358E TBGA Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
DDR SDRAM Memory Controller Interface
MEMC1_MDQ[0:63]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32,
AM36, AN37, AN35, AR34, AT34, AP37, AP36,
AR36, AT35, AP34, AR32, AP32, AM31, AN33,
AM34, AM33, AM30, AP31, AM27, AR30, AT32,
AN29, AP29, AN27, AR29, AN8, AN7, AM8, AM6,
AP9, AN9, AT7, AP7, AU6, AP6, AR4, AR3, AT6,
AT5, AR5, AT3, AP4, AM5, AP3, AN3, AN5, AL5,
AN4, AM2, AL2, AH5, AK3, AJ2, AJ3, AH4, AK4,
AH3
I/O
GVDD
—
MEMC_MECC[0:4]/MSRCID[0:4]
AP24, AN22, AM19, AN19, AM24
I/O
GVDD
—
MEMC_MECC[5]/MDVAL
AM23
I/O
GVDD
—
MEMC_MECC[6:7]
AM22, AN18
I/O
GVDD
—
MEMC_MDM[0:8]
AL36, AN34, AP33, AN28,AT9, AU4, AM3,
AJ6,AP27
O
GVDD
—
MEMC_MDQS[0:8]
AK35, AP35, AN31, AM26,AT8, AU3, AL4, AJ5,
AP26
I/O
GVDD
—
MEMC_MBA[0:1]
AU29, AU30
O
GVDD
MEMC_MBA[2]
AT30
O
GVDD
—
MEMC_MA[0:14]
AU21, AP22, AP21, AT21, AU25, AU26, AT23,
AR26, AU24, AR23, AR28, AU23, AR22, AU20,
AR18
O
GVDD
—
MEMC_MODT[0:3]
AG33, AJ36, AT1, AK2
O
GVDD
6
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
72
Freescale Semiconductor
Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
MEMC_MWE
AT26
O
GVDD
—
MEMC_MRAS
AT29
O
GVDD
—
MEMC_MCAS
AT24
O
GVDD
—
MEMC_MCS[0:3]
AU27, AT27, AU8, AU7
O
GVDD
—
MEMC_MCKE[0:1]
AL32, AU33
O
GVDD
3
MEMC_MCK[0:5]
AK37, AT37, AN1, AR2, AN25, AK1
O
GVDD
—
MEMC_MCK[0:5]
AL37, AT36, AP2, AT2, AN24, AL1
O
GVDD
—
MDIC[0:1]
AH6, AP30
I/O
GVDD
11
PCI
PCI_INTA/IRQ_OUT/CE_PF[5]
A20
I/O
LVDD2
2
PCI_RESET_OUT/CE_PF[6]
E19
I/O
LVDD2
—
PCI_AD[31:30]/CE_PG[31:30]
D20, D21
I/O
LVDD2
—
PCI_AD[29:25]/CE_PG[29:25]
A24, B23, C23, E23, A26
I/O
OVDD
—
PCI_AD[24]/CE_PG[24]
B21
I/O
LVDD2
—
PCI_AD[23:0]/CE_PG[23:0]
C24, C25, D25, B25, E24, F24, A27, A28, F27, A30,
C30, D30, E29, B31, C31, D31, D32, A32, C33,
B33, F30, E31, A34, D33
I/O
OVDD
—
PCI_C/BE[3:0]/CE_PF[10:7]
E22, B26, E28, F28
I/O
OVDD
—
PCI_PAR/CE_PF[11]
D28
I/O
OVDD
—
PCI_FRAME/CE_PF[12]
D26
I/O
OVDD
5
PCI_TRDY/CE_PF[13]
C27
I/O
OVDD
5
PCI_IRDY/CE_PF[14]
C28
I/O
OVDD
5
PCI_STOP/CE_PF[15]
B28
I/O
OVDD
5
PCI_DEVSEL/CE_PF[16]
E26
I/O
OVDD
5
PCI_IDSEL/CE_PF[17]
F22
I/O
OVDD
—
PCI_SERR/CE_PF[18]
B29
I/O
OVDD
5
PCI_PERR/CE_PF[19]
A29
I/O
OVDD
5
PCI_REQ[0]/CE_PF[20]
F19
I/O
LVDD2
—
PCI_REQ[1]/CPCI_HS_ES/
CE_PF[21]
A21
I/O
LVDD2
—
PCI_REQ[2]/CE_PF[22]
C21
I/O
LVDD2
—
PCI_GNT[0]/CE_PF[23]
E20
I/O
LVDD2
—
PCI_GNT[1]/CPCI1_HS_LED/
CE_PF[24]
B20
I/O
LVDD2
—
PCI_GNT[2]/CPCI1_HS_ENUM/
CE_PF[25]
C20
I/O
LVDD2
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
73
Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PCI_MODE
D36
I
OVDD
—
M66EN/CE_PF[4]
B37
I/O
OVDD
—
Local Bus Controller Interface
LAD[0:31]
N32, N33, N35, N36, P37, P32, P34, R36, R35,
R34, R33, T37, T35, T34, T33, U37, T32, U36, U34,
V36, V35, W37, W35, V33, V32, W34, Y36, W32,
AA37, Y33, AA35, AA34
I/O
OVDD
—
LDP[0]/CKSTOP_OUT
AB37
I/O
OVDD
—
LDP[1]/CKSTOP_IN
AB36
I/O
OVDD
—
LDP[2]/LCS[6]
AB35
I/O
OVDD
—
LDP[3]/LCS[7]
AA33
I/O
OVDD
—
LA[27:31]
AC37, AA32, AC36, AC34, AD36
O
OVDD
—
LCS[0:5]
AD33, AG37, AF34, AE33, AD32, AH37
O
OVDD
—
LWE[0:3]/LSDDQM[0:3]/LBS[0:3]
AG35, AG34, AH36, AE32
O
OVDD
—
LBCTL
AD35
O
OVDD
—
LALE
M37
O
OVDD
—
LGPL0/LSDA10/cfg_reset_source0
AB32
I/O
OVDD
—
LGPL1/LSDWE/cfg_reset_source1
AE37
I/O
OVDD
—
LGPL2/LSDRAS/LOE
AC33
O
OVDD
—
LGPL3/LSDCAS/cfg_reset_source2
AD34
I/O
OVDD
—
LGPL4/LGTA/LUPWAIT/LPBSE
AE35
I/O
OVDD
—
LGPL5/cfg_clkin_div
AF36
I/O
OVDD
—
LCKE
G36
O
OVDD
—
LCLK[0]
J33
O
OVDD
—
LCLK[1]/LCS[6]
J34
O
OVDD
—
LCLK[2]/LCS[7]
G37
O
OVDD
—
LSYNC_OUT
F34
O
OVDD
—
LSYNC_IN
G35
I
OVDD
—
Programmable Interrupt Controller
MCP_OUT
E34
O
OVDD
2
IRQ0/MCP_IN
C37
I
OVDD
—
IRQ[1]/M1SRCID[4]/M2SRCID[4]/
LSRCID[4]
F35
I/O
OVDD
—
IRQ[2]/M1DVAL/M2DVAL/LDVAL
F36
I/O
OVDD
—
IRQ[3]/CORE_SRESET
H34
I/O
OVDD
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
74
Freescale Semiconductor
Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
IRQ[4:5]
G33, G32
I/O
OVDD
—
IRQ[6]/LCS[6]/CKSTOP_OUT
E35
I/O
OVDD
—
IRQ[7]/LCS[7]/CKSTOP_IN
H36
I/O
OVDD
—
DUART
UART1_SOUT/M1SRCID[0]/
M2SRCID[0]/LSRCID[0]
E32
O
OVDD
—
UART1_SIN/M1SRCID[1]/
M2SRCID[1]/LSRCID[1]
B34
I/O
OVDD
—
UART1_CTS/M1SRCID[2]/
M2SRCID[2]/LSRCID[2]
C34
I/O
OVDD
—
UART1_RTS/M1SRCID[3]/
M2SRCID[3]/LSRCID[3]
A35
O
OVDD
—
I2C Interface
IIC1_SDA
D34
I/O
OVDD
2
IIC1_SCL
B35
I/O
OVDD
2
IIC2_SDA
E33
I/O
OVDD
2
IIC2_SCL
C35
I/O
OVDD
2
QUICC Engine
CE_PA[0]
F8
I/O
LVDD0
—
CE_PA[1:2]
AH1, AG5
I/O
OVDD
—
CE_PA[3:7]
F6, D4, C3, E5, A3
I/O
LVDD0
—
CE_PA[8]
AG3
I/O
OVDD
—
CE_PA[9:12]
F7, B3, E6, B4
I/O
LVDD0
—
CE_PA[13:14]
AG1, AF6
I/O
OVDD
—
CE_PA[15]
B2
I/O
LVDD0
—
CE_PA[16]
AF4
I/O
OVDD
—
CE_PA[17:21]
B16, A16, E17, A17, B17
I/O
LVDD1
—
CE_PA[22]
AF3
I/O
OVDD
—
CE_PA[23:26]
C18, D18, E18, A18
I/O
LVDD1
—
CE_PA[27:28]
AF2, AE6
I/O
OVDD
—
CE_PA[29]
B19
I/O
LVDD1
—
CE_PA[30]
AE5
I/O
OVDD
—
CE_PA[31]
F16
I/O
LVDD1
—
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
75
Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Package Pin Number
Pin Type
Power
Supply
Notes
CE_PB[0:27]
AE2, AE1, AD5, AD3, AD2, AC6, AC5, AC4, AC2,
AC1, AB5, AB4, AB3, AB1, AA6, AA4, AA2, Y6, Y4,
Y3, Y2, Y1, W6, W5, W2, V5, V3, V2
I/O
OVDD
—
CE_PC[0:1]
V1, U6
I/O
OVDD
CE_PC[2:3]
C16, A15
I/O
LVDD1
—
CE_PC[4:6]
U4, U3, T6
I/O
OVDD
—
CE_PC[7]
C19
I/O
LVDD2
—
CE_PC[8:9]
A4, C5
I/O
LVDD0
—
CE_PC[10:30]
T5, T4, T2, T1, R5, R3, R1, C11, D12, F13, B10,
C10, E12, A9, B8, D10, A14, E15, B14, D15, AH2
I/O
OVDD
—
CE_PD[0:27]
E11, D9, C8, F11, A7, E9, C7, A6, F10, B6, D7, E8,
B5, A5, C2, E4, F5, B1, D2, G5, D1, E2, H6, F3, E1,
F2, G3, H4
I/O
OVDD
—
CE_PE[0:31]
K3, J2, F1, G2, J5, H3, G1, H2, K6, J3, K5, K4, L6,
P6, P4, P3, P1, N4, N5, N2, N1, M2, M3, M5, M6,
L1, L2, L4, E14, C13, C14, B13
I/O
OVDD
—
CE_PF[0:3]
F14, D13, A12, A11
I/O
OVDD
—
Signal
Clocks
PCI_CLK_OUT[0]/CE_PF[26]
B22
I/O
LVDD2
—
PCI_CLK_OUT[1:2]/CE_PF[27:28]
D22, A23
I/O
OVDD
—
CLKIN
E37
I
OVDD
—
PCI_CLOCK/PCI_SYNC_IN
M36
I
OVDD
—
PCI_SYNC_OUT/CE_PF[29]
D37
I/O
OVDD
3
JTAG
TCK
K33
I
OVDD
—
TDI
K34
I
OVDD
4
TDO
H37
O
OVDD
3
TMS
J36
I
OVDD
4
TRST
L32
I
OVDD
4
Test
TEST
L35
I
OVDD
7
TEST_SEL
AU34
I
GVDD
10
O
OVDD
—
PMC
QUIESCE
B36
System Control
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Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
PORESET
L37
I
OVDD
—
HRESET
L36
I/O
OVDD
1
SRESET
M33
I/O
OVDD
2
Thermal Management
THERM0
AP19
I
GVDD
—
THERM1
AT31
I
GVDD
—
Power and Ground Signals
AVDD1
K35
Power for
LBIU DLL
(1.2 V)
AVDD1
—
AVDD2
K36
Power for
CE PLL
(1.2 V)
AVDD2
—
AVDD5
AM29
Power for
e300 PLL
(1.2 V)
AVDD5
—
AVDD6
K37
Power for
system
PLL (1.2 V)
AVDD6
—
GND
A2, A8, A13, A19, A22, A25, A31, A33, A36, B7,
B12, B24, B27, B30, C4, C6, C9, C15, C26, C32,
D3, D8, D11, D14, D17, D19, D23, D27, E7, E13,
E25, E30, E36, F4, F37, G34, H1, H5, H32, H33, J4,
J32, J37, K1, L3, L5, L33, L34, M1, M34, M35, N37,
P2, P5, P35, P36, R4, T3, U1, U5, U35, V37, W1,
W4, W33, W36, Y34, AA3, AA5, AC3, AC32, AC35,
AD1, AD37, AE4, AE34, AE36, AF33, AG4, AG6,
AG32, AH35, AJ1, AJ4, AJ32, AJ35, AJ37, AK36,
AL3, AL34, AM4, AN6, AN23, AN30, AP8, AP12,
AP14, AP16, AP17, AP20, AP25, AR6, AR8, AR9,
AR19, AR24, AR31, AR35, AR37, AT4, AT10, AT19,
AT20, AT25, AU14, AU22, AU28, AU35
—
—
—
GVDD
AD4, AE3, AF1, AF5, AF35, AF37, AG2, AG36,
AH33, AH34, AK5, AM1, AM35, AM37, AN2, AN10,
AN11, AN12, AN14, AN32, AN36, AP5, AP23,
AP28, AR1, AR7, AR10, AR12, AR21, AR25, AR27,
AR33, AT15, AT22, AT28, AT33, AU2, AU5, AU16,
AU31, AU36
Power for
DDR
DRAM I/O
voltage
(2.5 or
1.8 V)
GVDD
—
LVDD0
D5, D6
Power for
UCC1
Ethernet
interface
(2.5 V,
3.3 V)
LVDD0
—
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Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
LVDD1
C17, D16
Power for
UCC2
Ethernet
interface
option 1
(2.5 V,
3.3 V)
LVDD1
9
LVDD2
B18, E21
Power for
UCC2
Ethernet
interface
option 2
(2.5 V,
3.3 V)
LVDD2
9
VDD
C36, D29, D35, E16, F9, F12, F15, F17, F18, F20,
F21, F23, F25, F26, F29, F31, F32, F33, G6, J6,
K32, M32, N6, P33, R6, R32, U32, V6, Y5, Y32,
AB6, AB33, AD6, AF32, AK6, AL6, AM7, AM9,
AM10, AM11, AM12, AM13, AM14, AM15, AM18,
AM21, AM25, AM28, AM32, AN15, AN21, AN26,
AU9, AU17
Power for
core
(1.2 V)
VDD
—
OVDD
A10, B9, B15, B32, C1, C12, C22, C29, D24, E3,
E10, E27, G4, H35, J1, J35, K2, M4, N3, N34, R2,
R37, T36, U2, U33, V4, V34, W3, Y35, Y37, AA1,
AA36, AB2, AB34
PCI,
10/100
Ethernet,
and other
standard
(3.3 V)
OVDD
—
MVREF1
AN20
I
DDR
reference
voltage
—
MVREF2
AU32
I
DDR
reference
voltage
—
SPARE1
B11
I/O
OVDD
8
SPARE3
AH32
—
GVDD
8
SPARE4
AU18
—
GVDD
7
SPARE5
AP1
—
GVDD
8
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Pinout Listings
Table 67. MPC8358E TBGA Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
—
—
—
No Connect
NC
AM16, AM17, AM20, AN13, AN16, AN17, AP10,
AP11, AP13, AP15, AP18, AR11, AR13, AR14,
AR15, AR16, AR17, AR20, AT11, AT12, AT13,
AT14, AT16, AT17, AT18, AU10, AU11, AU12,
AU13, AU15, AU19
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being three-stated during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND.
8. This pin must always be left not connected.
9. Refer to MPC8360E PowerQUICC II Pro Integrated Communications Processor Reference Manual section on “RGMII Pins,”
for information about the two UCC2 Ethernet interface options.
10.This pin must always be tied to GVDD.
11.It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor for DDR2.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Pinout Listings
21
Clocking
This figure shows the internal distribution of clocks within the MPC8360E.
MPC8360E
e300 Core
Core PLL
core_clk
csb_clk
ce_clk to QUICC Engine Block
DDRC1
MEMC1_MCK[0:5]
/2
MEMC1_MCK[0:5]
DDRC2
MEMC2_MCK[0:1]
DDRC1
Memory
Device
ddr1_clk
QUICC
Engine
PLL
System
PLL
Clock
Unit
/2
lb_clk
/n
To Local
Bus/DDRC2 LBIU
Controller
DLL
MEMC2_MCK[0:1]
DDRC2
Memory
Device
LCLK[0:2]
LSYNC_OUT
Local Bus
Memory
Device
LSYNC_IN
csb_clk to Rest
of the Device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
PCI_CLK_OUT[0:2]
Figure 54. MPC8360E Clock Subsystem
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Pinout Listings
This figure shows the internal distribution of clocks within the MPC8358E.
MPC8358E
e300 Core
Core PLL
core_clk
csb_clk
ce_clk to QUICC Engine Block
DDRC
/2
MEMC1_MCK[0:5] DDRC
Memory
MEMC1_MCK[0:5] Device
ddr1_clk
QUICC
Engine
PLL
System
PLL
Clock
Unit
lb_clk
/n
LCLK[0:2]
LBIU
DLL
Local Bus
LSYNC_OUT Memory
Device
LSYNC_IN
csb_clk to Rest
of the Device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI Clock
Divider
PCI_CLK_OUT[0:2]
Figure 55. MPC8358E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is
configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary clock input also depends on whether PCI
clock outputs are selected with RCWH[PCICKDRV]. When the device is configured as a PCI host device (RCWH[PCIHOST]
= 1) and PCI clock output is selected (RCWH[PCICKDRV] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock
divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCIOENn] parameters enable
the PCI_CLK_OUTn, respectively.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subystem to synchronize to the system
PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the
system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Pinout Listings
clock. When the device is configured as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to
GND.
When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is disabled
(RCWH[PCICKDRV] = 0), clock distribution and balancing done externally on the board. Therefore, PCI_SYNC_IN is the
primary input clock.
As shown in Figure 54 and Figure 55, the primary clock input (frequency) is multiplied by the QUICC Engine block
phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent system
bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the local bus interface unit and
DDR2 memory controller (lb_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent mode, CFG_CLKIN_DIV
must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the PCI_CLK frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency
to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and
COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded
reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8360E PowerQUICC II Pro Integrated
Communications Processor Reference Manual for more information on the clock subsystem.
The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine
PLL division factor (RCWL[CEPDF]) according to the following equation:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
The internal ddr1_clk frequency is determined by the following equation:
ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])
Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal ddr1_clk frequency is not the
external memory bus frequency; ddr1_clk passes through the DDRC1 clock divider (÷2) to create the differential DDRC1
memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.
The internal lb_clk frequency is determined by the following equation:
lb_clk = csb_clk × (1 + RCWL[LBCM])
Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the
external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV].
Additionally, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency.
Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset.
This table specifies which units have a configurable clock frequency.
Table 68. Configurable Clock Units
Unit
Security core
PCI and DMA complex
1
Default
Frequency
csb_clk/3
csb_clk
Options
Off, csb_clk1,
csb_clk/3
csb_clk/2,
Off, csb_clk
With limitation, only for slow csb_clk rates, up to 166 MHz.
This table provides the operating frequencies for the TBGA package under recommended operating conditions (see Table 2).
All frequency combinations shown in the table below may not be available. Maximum operating frequencies depend on the part
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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System PLL Configuration
ordered, see Section 24.1, “Part Numbers Fully Addressed by this Document,” for part ordering details and contact your
Freescale sales representative or authorized distributor for more information.
Table 69. Operating Frequencies for the TBGA Package
Characteristic1
e300 core frequency (core_clk)
400 MHz
533 MHz
667 MHz2
Unit
266–400
266–533
266–667
MHz
Coherent system bus frequency (csb_clk)
133–333
MHz
266–500
MHz
DDR and DDR2 memory bus frequency (MCLK)
100–166.67
MHz
Local bus frequency (LCLKn)5
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66.67
MHz
QUICC Engine frequency3 (ce_clk)
4
Security core maximum internal operating frequency
133
133
166
MHz
Notes:
1. The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The 667 MHz core frequency is based on a 1.3 V VDD supply voltage.
3. The 500 MHz QE frequency is based on a 1.3 V VDD supply voltage.
4. The DDR data rate is 2x the DDR memory bus frequency.
5. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWL[LBCM]).
21.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. This table shows the multiplication
factor encodings for the system PLL.
Table 70. System PLL Multiplication Factors
RCWL[SPMF]
System PLL
Multiplication Factor
0000
× 16
0001
Reserved
0010
×2
0011
×3
0100
×4
0101
×5
0110
×6
0111
×7
1000
×8
1001
×9
1010
× 10
1011
× 11
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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83
System PLL Configuration
Table 70. System PLL Multiplication Factors (continued)
RCWL[SPMF]
System PLL
Multiplication Factor
1100
× 12
1101
× 13
1110
× 14
1111
× 15
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in this table.
Table 71. System PLL VCO Divider
RCWL[SVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved
NOTE
The VCO divider must be set properly so that the system VCO frequency is in the range of
600–1400 MHz.
The system VCO frequency is derived from the following equations:
•
•
•
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
System VCO Frequency = csb_clk × VCO divider (if both RCWL[DDRCM] and RCWL[LBCM] are cleared)
OR
System VCO frequency = 2 × csb_clk × VCO divider (if either RCWL[DDRCM] or RCWL[LBCM] are set).
As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and
the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and
the internal coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB frequency for
select csb_clk to CLKIN/PCI_SYNC_IN ratios.
Table 72. CSB Frequency Options
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk:
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2:1
Low
0011
3:1
Low
0100
4:1
Low
0101
5:1
133
100
200
100
133
266
125
166
333
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System PLL Configuration
Table 72. CSB Frequency Options (continued)
Input Clock Frequency (MHz)2
CFG_CLKIN_DIV
at Reset1
SPMF
csb_clk:
Input Clock Ratio2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0110
6:1
100
150
200
Low
0111
7:1
116
175
233
Low
1000
8:1
133
200
266
Low
1001
9:1
150
225
300
Low
1010
10:1
166
250
333
Low
1011
11:1
183
275
Low
1100
12:1
200
300
Low
1101
13:1
216
325
Low
1110
14:1
233
Low
1111
15:1
250
Low
0000
16:1
266
High
0010
2:1
High
0011
3:1
100
200
High
0100
4:1
133
266
High
0101
5:1
166
333
High
0110
6:1
200
High
0111
7:1
233
High
1000
8:1
High
1001
9:1
High
1010
10:1
High
1011
11:1
High
1100
12:1
High
1101
13:1
High
1110
14:1
High
1111
15:1
High
0000
16:1
133
1
CFG_CLKIN_DIV is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down (low) in
agent mode.
2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
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85
Core PLL Configuration
21.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock
(core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values not listed in this table should be
considered reserved.
Table 73. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk:csb_clk
Ratio
VCO divider
0–1
2–5
6
nn
0000
n
00
0001
0
1:1
÷2
01
0001
0
1:1
÷4
10
0001
0
1:1
÷8
11
0001
0
1:1
÷8
00
0001
1
1.5:1
÷2
01
0001
1
1.5:1
÷4
10
0001
1
1.5:1
÷8
11
0001
1
1.5:1
÷8
00
0010
0
2:1
÷2
01
0010
0
2:1
÷4
10
0010
0
2:1
÷8
11
0010
0
2:1
÷8
00
0010
1
2.5:1
÷2
01
0010
1
2.5:1
÷4
10
0010
1
2.5:1
÷8
11
0010
1
2.5:1
÷8
00
0011
0
3:1
÷2
01
0011
0
3:1
÷4
10
0011
0
3:1
÷8
11
0011
0
3:1
÷8
PLL bypassed
PLL bypassed
(PLL off, csb_clk
(PLL off, csb_clk
clocks core directly) clocks core directly)
NOTE
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the
range of 800–1800 MHz. Having a core frequency below the CSB frequency is not a
possible option because the core frequency must be equal to or greater than the CSB
frequency.
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QUICC Engine Block PLL Configuration
21.3
QUICC Engine Block PLL Configuration
The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and RCWL[CEVCOD] parameters.
This table shows the multiplication factor encodings for the QUICC Engine block PLL.
Table 74. QUICC Engine Block PLL Multiplication Factors
QUICC Engine PLL
RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF])
00000
0
× 16
00001
0
Reserved
00010
0
×2
00011
0
×3
00100
0
×4
00101
0
×5
00110
0
×6
00111
0
×7
01000
0
×8
01001
0
×9
01010
0
× 10
01011
0
× 11
01100
0
× 12
01101
0
× 13
01110
0
× 14
01111
0
× 15
10000
0
× 16
10001
0
× 17
10010
0
× 18
10011
0
× 19
10100
0
× 20
10101
0
× 21
10110
0
× 22
10111
0
× 23
11000
0
× 24
11001
0
× 25
11010
0
× 26
11011
0
× 27
11100
0
× 28
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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QUICC Engine Block PLL Configuration
Table 74. QUICC Engine Block PLL Multiplication Factors (continued)
QUICC Engine PLL
RCWL[CEPMF] RCWL[CEPDF] Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF])
11101
0
× 29
11110
0
× 30
11111
0
× 31
00011
1
× 1.5
00101
1
× 2.5
00111
1
× 3.5
01001
1
× 4.5
01011
1
× 5.5
01101
1
× 6.5
01111
1
× 7.5
10001
1
× 8.5
10011
1
× 9.5
10101
1
× 10.5
10111
1
× 11.5
11001
1
× 12.5
11011
1
× 13.5
11101
1
× 14.5
Note:
1. Reserved modes are not listed.
The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in this table.
Table 75. QUICC Engine Block PLL VCO Divider
RCWL[CEVCOD]
VCO Divider
00
4
01
8
10
2
11
Reserved
NOTE
The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine
block VCO frequency is in the range of 600–1400 MHz. The QUICC Engine block
frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC
Engine block frequencies should be selected according to the performance requirements.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Suggested PLL Configurations
The QUICC Engine block VCO frequency is derived from the following equations:
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
21.4
Suggested PLL Configurations
To simplify the PLL configurations, the device might be separated into two clock domains. The first domain contains the CSB
PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second
clock domain has the QUICC Engine block PLL. The clock domains are independent, and each of their PLLs are configured
separately. Both of the domains has one common input clock. This table shows suggested PLL configurations for 33 and
66 MHz input clocks and illustrates each of the clock domains separately. Any combination of clock domains setting with same
input clock are valid. Refer to Section 21, “Clocking,” for the appropriate operating frequencies for your device.
Table 76. Suggested PLL Configurations
Conf
No.1
SPMF
CORE
PLL
CEPMF
CEPDF
Input
CSB Freq Core Freq
Clock Freq
(MHz)
(MHz)
(MHz)
QUICC
Engine
Freq (MHz)
400
533
667
(MHz) (MHz) (MHz)
33 MHz CLKIN/PCI_SYNC_IN Options
s1
0100
0000100
æ
æ
33
133
266
—
∞
∞
∞
s2
0100
0000101
æ
æ
33
133
333
—
∞
∞
∞
s3
0101
0000100
æ
æ
33
166
333
—
∞
∞
∞
s4
0101
0000101
æ
æ
33
166
416
—
—
∞
∞
s5
0110
0000100
æ
æ
33
200
400
—
∞
∞
∞
s6
0110
0000110
æ
æ
33
200
600
—
—
—
∞
s7
0111
0000011
æ
æ
33
233
350
—
∞
∞
∞
s8
0111
0000100
æ
æ
33
233
466
—
—
∞
∞
s9
0111
0000101
æ
æ
33
233
583
—
—
—
∞
s10
1000
0000011
æ
æ
33
266
400
—
∞
∞
∞
s11
1000
0000100
æ
æ
33
266
533
—
—
∞
∞
s12
1000
0000101
æ
æ
33
266
667
—
—
—
∞
s13
1001
0000010
æ
æ
33
300
300
—
∞
∞
∞
s14
1001
0000011
æ
æ
33
300
450
—
—
∞
∞
s15
1001
0000100
æ
æ
33
300
600
—
—
—
∞
s16
1010
0000010
æ
æ
33
333
333
—
∞
∞
∞
s17
1010
0000011
æ
æ
33
333
500
—
—
∞
∞
s18
1010
0000100
æ
æ
33
333
667
—
—
—
∞
c1
æ
æ
01001
0
33
—
—
300
∞
∞
∞
c2
æ
æ
01100
0
33
—
—
400
∞
∞
∞
c3
æ
æ
01110
0
33
—
—
466
—
∞
∞
c4
æ
æ
01111
0
33
—
—
500
—
∞
∞
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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89
Suggested PLL Configurations
Table 76. Suggested PLL Configurations (continued)
Input
CSB Freq Core Freq
Clock Freq
(MHz)
(MHz)
(MHz)
QUICC
Engine
Freq (MHz)
Conf
No.1
SPMF
CORE
PLL
CEPMF
CEPDF
c5
æ
æ
10000
0
33
—
—
533
—
∞
∞
c6
æ
æ
10001
0
33
—
—
566
—
—
∞
400
533
667
(MHz) (MHz) (MHz)
66 MHz CLKIN/PCI_SYNC_IN Options
s1h
0011
0000110
æ
æ
66
200
400
—
∞
∞
∞
s2h
0011
0000101
æ
æ
66
200
500
—
—
∞
∞
s3h
0011
0000110
æ
æ
66
200
600
—
—
—
∞
s4h
0100
0000011
æ
æ
66
266
400
—
∞
∞
∞
s5h
0100
0000100
æ
æ
66
266
533
—
—
∞
∞
s6h
0100
0000101
æ
æ
66
266
667
—
—
—
∞
s7h
0101
0000010
æ
æ
66
333
333
—
∞
∞
∞
s8h
0101
0000011
æ
æ
66
333
500
—
—
∞
∞
s9h
0101
0000100
æ
æ
66
333
667
—
—
—
∞
c1h
æ
æ
00101
0
66
—
—
333
∞
∞
∞
c2h
æ
æ
00110
0
66
—
—
400
∞
∞
∞
c3h
æ
æ
00111
0
66
—
—
466
—
∞
∞
c4h
æ
æ
01000
0
66
—
—
533
—
∞
∞
c5h
æ
æ
01001
0
66
—
—
600
—
—
∞
Note:
1. The Conf No. consist of prefix, an index and a postfix. The prefix “s” and “c” stands for “syset” and “ce” respectively. The
postfix “h” stands for “high input clock.’”The index is a serial number.
The following steps describe how to use above table. See Example 1.
2.
3.
4.
5.
Choose the up or down sections in the table according to input clock rate 33 MHz or 66 MHz.
Select a suitable CSB and core clock rates from Table 76. Copy the SPMF and CORE PLL configuration bits.
Select a suitable QUICC Engine block clock rate from Table 76. Copy the CEPMF and CEPDF configuration bits.
Insert the chosen SPMF, COREPLL, CEPMF and CEPDF to the RCWL fields, respectively.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Thermal Characteristics
Example 1. Sample Table Use
QUICC
Input Clock CSB Freq Core Freq
400
533
667
Engine Freq
(MHz)
(MHz)
(MHz)
(MHz) (MHz) (MHz)
(MHz)
Index
SPMF
CORE
PLL
A
1000
0000011
01001
0
33
266
400
300
∞
∞
∞
B
0100
0000100
00110
0
66
266
533
400
∞
∞
∞
•
•
22
CEPMF CEPDF
Example A. To configure the device with CSB clock rate of 266 MHz, core rate of 400 MHz, and QUICC Engine
clock rate 300 MHz while the input clock rate is 33 MHz. Conf No. ‘s10’ and ‘c1’ are selected from Table 76. SPMF
is 1000, CORPLL is 0000011, CEPMF is 01001, and CEPDF is 0.
Example B. To configure the device with CSBCSB clock rate of 266 MHz, core rate of 533 MHz and QUICC Engine
clock rate 400 MHz while the input clock rate is 66 MHz. Conf No. ‘s5h’ and ‘c2h’ are selected from Table 76. SPMF
is 0100, CORPLL is 0000100, CEPMF is 00110, and CEPDF is 0.
Thermal
This section describes the thermal specifications of the MPC8360E/58E.
22.1
Thermal Characteristics
This table provides the package thermal characteristics for the 37.5 mm × 37.5 mm 740-TBGA package.
Table 77. Package Thermal Characteristics for the TBGA Package
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection on single-layer board (1s)
RθJA
15
° C/W
1, 2
Junction-to-ambient natural convection on four-layer board (2s2p)
RθJA
11
° C/W
1, 3
Junction-to-ambient (@1 m/s) on single-layer board (1s)
RθJMA
10
° C/W
1, 3
Junction-to-ambient (@ 1 m/s) on four-layer board (2s2p)
RθJMA
8
° C/W
1, 3
Junction-to-ambient (@ 2 m/s) on single-layer board (1s)
RθJMA
9
° C/W
1, 3
Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p)
RθJMA
7
° C/W
1, 3
Junction-to-board thermal
RθJB
4.5
° C/W
4
Junction-to-case thermal
RθJC
1.1
° C/W
5
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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91
Thermal Management Information
Table 77. Package Thermal Characteristics for the TBGA Package (continued)
Characteristic
Junction-to-package natural convection on top
Symbol
Value
Unit
Notes
ψJT
1
° C/W
6
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 and SEMI G38-87 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal. 1 m/sec is approximately equal to 200 linear feet per minute (LFM).
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
22.2
Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 6 for
typical power dissipations values.
22.2.1
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (° C)
TA = ambient temperature for the package (° C)
RθJA = junction-to-ambient thermal resistance (° C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. As a general statement, the value obtained on a single-layer board is appropriate for a tightly packed
printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power
dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity
TJ – TA) are possible.
22.2.2
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The
thermal performance of any component is strongly dependent on the power dissipation of surrounding components.
Additionally, the ambient temperature varies widely within the application. For many natural convection and especially closed
box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air
temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise
description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the
junction temperature is estimated using the following equation:
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Thermal Management Information
TJ = TB + (RθJB × PD)
where:
TJ = junction temperature (° C)
TB = board temperature at the package perimeter (° C)
RθJA = junction to board thermal resistance (° C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
22.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TJ = junction temperature (° C)
TT = thermocouple temperature on top of package (° C)
ΨJT = junction-to-ambient thermal resistance (° C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
22.2.4
Heat Sinks and Junction-to-Ambient Thermal Resistance
In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a
heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient
thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction-to-ambient thermal resistance (° C/W)
RθJC = junction-to-case thermal resistance (° C/W)
RθCA = case-to-ambient thermal resistance (° C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the
case-to-ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the airflow around the
device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the
printed-circuit board surrounding the device.
To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few
commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, airflow,
adjacent component power dissipation) and the physical space available. Because there is not a standard application
environment, a standard heat sink is not required.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
93
Thermal Management Information
This table shows heat sinks and junction-to-ambient thermal resistance for TBGA package.
Table 78. Heat Sinks and Junction-to-Ambient Thermal Resistance of TBGA Package
35 × 35 mm TBGA
Heat Sink Assuming Thermal Grease
Airflow
Junction-to-Ambient
Thermal Resistance
AAVID 30 × 30 × 9.4 mm pin fin
Natural convention
10.7
AAVID 30 × 30 × 9.4 mm pin fin
1 m/s
6.2
AAVID 30 × 30 × 9.4 mm pin fin
2 m/s
5.3
AAVID 31 × 35 × 23 mm pin fin
Natural convention
8.1
AAVID 31 × 35 × 23 mm pin fin
1 m/s
4.4
AAVID 31 × 35 × 23 mm pin fin
2 m/s
3.7
Wakefield, 53 × 53 × 25 mm pin fin
Natural convention
5.4
Wakefield, 53 × 53 × 25 mm pin fin
1 m/s
3.2
Wakefield, 53 × 53 × 25 mm pin fin
2 m/s
2.4
MEI, 75 × 85 × 12 no adjacent board, extrusion
Natural convention
6.4
MEI, 75 × 85 × 12 no adjacent board, extrusion
1 m/s
3.8
MEI, 75 × 85 × 12 no adjacent board, extrusion
2 m/s
2.5
MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass
1 m/s
2.8
Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics
software which can model both the conduction cooling and the convection cooling of the air moving through the application.
Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal
resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.
Heat sink vendors include the following:
Aavid Thermalloy
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
603-224-9988
Alpha Novatech
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
408-749-7601
International Electronic Research Corporation (IERC)
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
818-842-7277
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Freescale Semiconductor
Heat Sink Attachment
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-millennium.com
408-436-8770
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
800-522-6752
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
603-635-5102
Interface material vendors include the following:
22.3
Chomerics, Inc.
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
781-935-4850
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
Midland, MI 48686-0997
Internet: www.dowcorning.com
800-248-2481
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com
888-642-7674
The Bergquist Company
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
800-347-4572
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a
spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board,
or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board.
Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package is
10 lb force (4.5 kg force). If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or
plastic surfaces and its performance verified under the application requirements.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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95
System Clocking
22.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case
of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of
the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to
the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature
and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
TJ = TC + (RθJC × PD)
where:
TJ = junction temperature (° C)
TC = case temperature of the package (° C)
RθJC = junction to case thermal resistance (° C/W)
PD = power dissipation (W)
23
System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8360E/58E.
Additional information can be found in MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097).
23.1
System Clocking
The device includes two PLLs, as follows.
•
•
23.2
The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency
ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in
Section 21.1, “System PLL Configuration.”
The e300 core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between
the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in
Section 21.2, “Core PLL Configuration.”
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1, AVDD2, respectively).
The AVDD level should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a
low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide five independent
filter circuits as illustrated in Figure 56, one to each of the five AVDD pins. By providing independent filters to each PLL, the
opportunity to cause noise injection from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built
with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.
Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors
of equal value are recommended over a single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from
nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package,
without the inductance of vias.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Decoupling Recommendations
This figure shows the PLL power supply filter circuit.
VDD
10 Ω
AVDDn
2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 56. PLL Power Supply Filter Circuit
23.3
Decoupling Recommendations
Due to large address and data buses as well as high operating frequencies, the device can generate transient power surges and
high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from
reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power.
Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and
LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and
GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device
using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be
used to minimize lead inductance, preferably 0402 or 0603 sizes.
Additionally, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD,
OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have
a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
23.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active
low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All
NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the device.
23.5
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended
driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the
value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 57). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and
RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are
designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
97
Configuration Pin Muxing
OVDD
RN
SW2
Data
Pad
SW1
RP
OGND
Figure 57. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the
output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is
V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential
termination resistor of value Rterm. The measured voltage is V2 = 1/(1/R1 + 1/R2)) × Isource. Solving for the output impedance
gives Rsource = Rterm × (V1/V2 – 1). The drive current is then Isource = V1/Rsource.
This table summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD,
105° C.
Table 79. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART,
Control, Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
20 Target
Z0
W
RP
42 Target
25 Target
20 Target
Z0
W
Differential
NA
NA
NA
ZDIFF
W
Note: Nominal supply voltages. See Table 1, TJ = 105° C.
23.6
Configuration Pin Muxing
The device provides the user with power-on configuration options that can be set through the use of external pull-up or
pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as
output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is
asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the
pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
98
Freescale Semiconductor
Pull-Up Resistor Requirements
23.7
Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins including I2C pins,
Ethernet Management MDIO pin, and EPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface, see
MPC8360E/MPC8358E PowerQUICC Design Checklist (AN3097).
24
Ordering Information
24.1
Part Numbers Fully Addressed by this Document
This table provides the Freescale part numbering nomenclature for the MPC8360E/58E. Note that the individual part numbers
correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office.
Additionally to the processor frequency, the part numbering scheme also includes an application modifier, which may specify
special application conditions. Each part number also contains a revision code that refers to the die mask revision number.
Table 80. Part Numbering Nomenclature1
MPC nnnn
e
t
Product
Part
Encryption Temperature
Code Identifier Acceleration
Range
MPC
8358
Blank = not
included
E = included
8360
MPC
(rev. 2.0
silicon
only)
8360
pp
aa
a
a
A
Package2
Processor
Frequency3
Platform
Frequency
QUICC
Engine
Frequency
Die
Revision
Blank = 0° C ZU = TBGA
TA to 105° C VV = TBGA
TJ
(no lead)
C= –40° C TA
to 105° C TJ
Blank = not
included
E = included
0° C TA to
70° C TJ
ZU = TBGA
VV = TBGA
(no lead)
e300 core speed D = 266 MHz E = 300 MHz A = rev. 2.1
AD = 266 MHz
G = 400 MHz
silicon
AG = 400 MHz
e300 core speed D = 266 MHz G = 400 MHz A = rev. 2.1
AG = 400 MHz F = 333 MHz H = 500 MHz
silicon
AJ = 533 MHz
AL = 667 MHz
e300 core speed F = 333 MHz G = 400 MHz
AH = 500 MHz
H = 500 MHz
AL = 667 MHz
—
Notes:
1. Not all processor, platform, and QUICC Engine block frequency combinations are supported. For available frequency
combinations, contact your local Freescale sales office or authorized distributor.
2. See Section 20, “Package and Pin Listings,” for more information on available package types.
3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support other
maximum core frequencies.
This table shows the SVR settings by device and package type.
Table 81. SVR Settings
Package
SVR
(Rev. 2.0)
SVR
(Rev. 2.1)
MPC8360E
TBGA
0x8048_0020
0x8048_0021
MPC8360
TBGA
0x8049_0020
0x8049_0021
Device
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
99
Part Numbers Fully Addressed by this Document
Table 81. SVR Settings (continued)
Package
SVR
(Rev. 2.0)
SVR
(Rev. 2.1)
MPC8358E
TBGA
0x804A_0020
0x804A_0021
MPC8358
TBGA
0x804B_0020
0x804B_0021
Device
25
Document Revision History
This table provides a revision history for this document.
Table 82. Revision History
Rev.
Number
Date
Substantive Change(s)
5
09/2011
• Section 2.2.1, “Power-Up Sequencing”, added the current limitation “3A to 5A” for the excessive current.
• Section 2.1.2, “Power Supply Voltage Specification, Updated the Characteristic for TBGA (MPC8358 &
MPC8360 Device) with specific frequency for Core and PLL voltages.
• Added table footnote 3 to Table 2.
• Applied table footnotes 1 and 2 to Table 10.
• Removed table footnotes from Table 19.
• Applied table footnote 8 to the last row of Table 40.
• Applied table footnotes 8 and 9 to Table 41.
• Applied table footnotes 2and 3 to Table 45.
• Removed table footnotes from Table 46.
• Applied table footnote to last three rows of Table 65.
4
01/2011
• Updated references to the LCRR register throughout
• Removed references to DDR DLL mode in Section 6.2.2, “DDR and DDR2 SDRAM Output AC Timing
Specifications.”
• Changed “Junction-to-Case” to “Junction-to-Ambient” in Section 22.2.4, “Heat Sinks and
Junction-to-Ambient Thermal Resistance,” and Table 78, “Heat Sinks and Junction-to-Ambient Thermal
Resistance of TBGA Package,” titles.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
Part Numbers Fully Addressed by this Document
Table 82. Revision History (continued)
Rev.
Number
Date
3
03/2010
Substantive Change(s)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
Changed references to RCWH[PCICKEN] to RCWH[PCICKDRV].
In Table 2, added extended temperature characteristics.
Added Figure 6, “DDR Input Timing Diagram.”
In Figure 53, “Mechanical Dimensions and Bottom Surface Nomenclature of the TBGA Package,”
removed watermark.
Updated the title of Table 19,”DDR SDRAM Input AC Timing Specifications.”
In Table 20, “DDR and DDR2 SDRAM Input AC Timing Specifications Mode,” changed table subtitle.
In Table 27–Table 30, and Table 33—Table 34, changed the rise and fall time specifications to reference
20–80% and 80–20% of the voltage supply, respectively.
In Table 38, “IEEE 1588 Timer AC Specifications,” changed first parameter to “Timer clock frequency.”
In Table 45, “I2C AC Electrical Specifications,” changed units to “ns” for tI2DVKH.
In Table 66, “MPC8360E TBGA Pinout Listing,” and Table 67 “MPC8358E TBGA Pinout Listing, added
note 7: “This pin must always be tied to GND” to the TEST pin and added a note to SPARE1 stating: “This
pin must always be left not connected.”
In Section 4, “Clock Input Timing,” added note regarding rise/fall time on QUICC Engine block input pins.
Added Section 4.3, “Gigabit Reference Clock Input Timing.”
Updated Section 8.1.1, “10/100/1000 Ethernet DC Electrical Characteristics.”
In Section 20.3, “Pinout Listings,” added sentence stating “Refer to AN3097, ‘MPC8360/MPC8358E
PowerQUICC Design Checklist,’ for proper pin termination and usage.”
In Section 21, “Clocking,” removed statement: “The OCCR[PCICDn] parameters select whether CLKIN
or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.”
In Section 21.1, “System PLL Configuration,” updated the system VCO frequency conditions.
In Table 80, added extended temperature characteristics.
12/2007 Initial release.
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
101
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Document Number: MPC8360EEC
Rev. 5
09/2011
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