Mitsubishi M5M467805BTP-5 Edo mode 67108864-bit (16777216-word by 4-bit) dynamic ram Datasheet

(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
The M5M467405/465405BJ,BTP is organized 16777216-word by 4-bit, M5M467805/465805BJ,BTP is organized 8388608-word by
8-bit, and M5M465165BJ,BTP is organized 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS
process, and are suitable for large-capacity memory systems with high speed and low power dissipation.
The use of double-layer aluminum process combined with CMOS technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density. Multiplexed address inputs permit both a reduction in pins and an increase in system
densities.
FEATURES
Address
Power
RAS
OE
CAS
Cycle
access access access
access
dissipatime
tion
time
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
Type name
M5M467405BXX-5,5S
M5M467805BXX-5,5S
50
13
25
13
84
300
M5M467405BXX-6,6S
M5M467805BXX-6,6S
60
15
30
15
104
250
M5M465405BXX-5,5S
M5M465805BXX-5,5S
50
13
25
13
84
390
M5M465405BXX-6,6S
M5M465805BXX-6,6S
60
15
30
15
104
325
Type name
Power
Address
RAS
CAS
OE
Cycle
dissipaaccess access access
access
time
time
tion
time
time
time
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M465165BXX-5,5S
50
13
25
13
84
420
M5M465165BXX-6,6S
60
15
30
15
104
390
XX=J,TP
Standard 32 pin SOJ, 32 pin TSOP (M5M467405Bxx/M5M465405Bxx/M5M467805Bxx/M5M465805Bxx)
Standard 50 pin SOJ, 50 pin TSOP (M5M465165Bxx)
Single 3.3 ± 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467405Bxx-5,5S / M5M467805Bxx-5,5S
360.0mW (Max)
M5M467405Bxx-6,6S / M5M467805Bxx-6,6S
324.0mW (Max)
M5M465405Bxx-5,5S / M5M465805Bxx-5,5S
468.0mW (Max)
M5M465405Bxx-6,6S / M5M465805Bxx-6,6S
432.0mW (Max)
M5M465165Bxx-5,5S
504.0mW (Max)
M5M465165Bxx-6,6S
468.0mW (Max)
Self refresh capability*
Self refresh current
400µA (Max)
EDO mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode , OE and W to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
* :Applicable to self refresh version(M5M467405/465405/467805/465805/465165BJ,BTP-5S,-6S:option) only
ADDRESS
Part No.
Row Add Col Add
Refresh
Refresh Cycle
Normal
S-version
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467405Bxx A0-A12 A0-A10
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
Only Ref,Normal R/W 4096/64ms 4096/128ms
M5M465405Bxx A0-A11 A0-A11 RAS
CBR Ref,Hidden Ref
RAS Only Ref,Normal R/W 8192/64ms 8192/128ms
M5M467805Bxx A0-A12 A0-A9
CBR Ref,Hidden Ref
4096/64ms 4096/128ms
Only Ref,Normal R/W 4096/64ms 4096/128ms
M5M465805Bxx A0-A11 A0-A10 RAS
CBR Ref,Hidden Ref
M5M465165Bxx A0-A11 A0-A9
RAS Only Ref,Normal R/W 4096/64ms 4096/128ms
CBR Ref,Hidden Ref
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
1
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
PIN DESCRIPTION
M5M467405Bxx / M5M465405Bxx
M5M467805Bxx / M5M465805Bxx
Pin Name
Function
Pin Name
Function
A0-A12
Address Inputs
A0-A12
Address Inputs
DQ1-DQ4
Data Inputs / Outputs
DQ1-DQ8
Data Inputs / Outputs
RAS
Row Address Strobe Input
Column Address Strobe Input
RAS
Row Address Strobe Input
Column Address Strobe Input
W
OE
Vcc
Write Control Input
W
OE
Vcc
Write Control Input
Output Enable Input
Power Supply (+3.3V)
Vss
NC
Ground (0V)
No Connection
Vss
NC
Ground (0V)
No Connection
CAS
CAS
Output Enable Input
Power Supply (+3.3V)
M5M465165Bxx
Pin Name
Function
A0-A11
Address Inputs
DQ1-DQ16 Data Inputs / Outputs
Row Address Strobe Input
RAS
Upper byte control
UCAS
Column Address Strobe Input
Lower byte control
LCAS
Column Address Strobe Input
Write Control Input
W
OE
Vcc
Output Enable Input
Vss
NC
Ground (0V)
No Connection
Power Supply (+3.3V)
XX=BJ,BTP
M5M467400/465400BJ,BTP
3
30
4
29
5
28
6
7
8
9
10
11
27
26
25
24
23
22
12
21
13
20
14
19
15
18
16
17
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
Vss
DQ4
DQ3
NC
NC
NC
CAS
OE
A12/NC(Note)
A11
A10
A9
A8
A7
A6
Vss
Outline 32P0N (400mil SOJ)
1
32
2
31
3
30
4
29
5
28
6
7
8
9
10
11
12
M5M467405BTP
31
M5M465405BTP
32
2
M5M467405BJ
1
M5M465405BJ
Vcc
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
PIN CONFIGURATION (TOP VIEW)
27
26
25
24
23
22
21
13
20
14
19
15
18
16
17
Vss
DQ4
DQ3
NC
NC
NC
CAS
OE
A12/NC(Note)
A11
A10
A9
A8
A7
A6
Vss
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467405Bxx, NC...M5M465405Bxx
: NO CONNECTION
NC
2
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467805/465805BJ,BTP
PIN CONFIGURATION (TOP VIEW)
3
30
DQ3
DQ4
NC
Vcc
4
29
5
28
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
8
6
7
9
10
11
27
26
25
24
23
22
12
21
13
20
14
19
15
18
16
17
Vss
DQ8
DQ7
DQ6
DQ5
Vss
CAS
Vcc
DQ1
DQ2
DQ3
DQ4
NC
Vcc
1
32
2
31
3
30
4
29
5
28
OE
A12/NC(Note)
A11
A10
A9
A8
A7
A6
Vss
W
RAS
A0
A1
A2
A3
A4
A5
Vcc
8
Outline 32P0N (400mil SOJ)
6
7
9
10
11
12
M5M467805BTP
31
M5M465805BTP
32
2
M5M467805BJ
1
M5M465805BJ
Vcc
DQ1
DQ2
27
26
25
24
23
22
21
13
20
14
19
15
18
16
17
Vss
DQ8
DQ7
DQ6
DQ5
Vss
CAS
OE
A12/NC(Note)
A11
A10
A9
A8
A7
A6
Vss
Outline 32P3N (400mil TSOP Normal Bend)
Note : A12...M5M467800Bxx, NC...M5M465800Bxx
: NO CONNECTION
NC
PIN CONFIGURATION (TOP VIEW)
M5M465165BJ,BTP
Vcc
1
50
Vss
Vcc
1
50
Vss
DQ1
2
49
DQ16
DQ1
2
49
DQ16
DQ2
3
48
DQ15
DQ2
3
48
DQ15
DQ3
4
47
DQ14
DQ3
4
47
DQ14
DQ4
5
46
DQ13
DQ4
5
46
DQ13
Vcc
6
45
Vss
Vcc
6
45
Vss
44
DQ12
DQ5
7
44
DQ12
8
43
DQ11
DQ6
8
43
DQ11
DQ7
9
42
DQ10
DQ7
9
42
DQ10
DQ8
10
41
DQ9
DQ8
10
41
DQ9
NC
Vcc
11
40
NC
Vcc
11
40
39
NC
Vss
39
NC
Vss
38
LCAS
LCAS
UCAS
W
RAS
NC
38
37
15
12 12
13
12 12
13
M5M465165BTP
7
M5M465165BJ
DQ5
DQ6
W
RAS
NC
15
NC
16
35
OE
NC
NC
16
35
OE
NC
NC
17
34
NC
NC
17
34
NC
NC
18
33
NC
NC
18
33
NC
A0
19
32
A11
A0
19
32
A11
A10
A9
14
36
14
37
36
UCAS
A1
20
31
A10
A1
20
31
A2
21
30
A9
A2
21
30
A3
22
29
A8
A3
22
29
A8
A4
23
28
A7
A4
23
28
A7
A5
24
27
A6
A5
24
27
A6
Vcc
25
26
Vss
Vcc
25
26
Vss
Outline 50P0G (400mil SOJ)
Outline 50P3G (400mil TSOP Normal Bend)
NC : NO CONNECTION
3
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
The M5M467405(805)/465405(805,165)BJ, BTP provide, in addition to normal read, write, and read-modify-write operations,
a number of other functions, e.g., EDO mode, CAS before RAS refresh, and delayed-write.
The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
M5M467405Bxx / M5M465405Bxx / M5M467805Bxx / M5M465805Bxx
Inputs
Input/Output
Operation
Column
address
APD
Refresh
RAS
CAS
W
OE
Read
ACT
ACT
NAC
ACT
Row
address
APD
OPN
VLD
NO
Write (Early write)
ACT
ACT
ACT
DNC
APD
APD
VLD
OPN
NO
Write (Delayed write)
ACT
ACT
ACT
DNC
APD
APD
VLD
IVD
NO
Read-modify-write
ACT
ACT
ACT
ACT
APD
APD
VLD
VLD
NO
RAS-only refresh
ACT
NAC
DNC
DNC
APD
DNC
OPN
OPN
YES
Hidden refresh
ACT
ACT
DNC
ACT
DNC
DNC
OPN
VLD
YES
CAS before RAS refresh
ACT
ACT
NAC
DNC
DNC
DNC
DNC
OPN
YES
Standby
NAC
DNC
DNC
DNC
DNC
DNC
DNC
OPN
NO
Column
address
APD
DQ1~DQ8
DQ9~DQ16
Input
Output
Remark
EDO mode
identical
M5M465165Bxx
Inputs
Input/Output
Operation
Refresh
RAS
LCAS
UCAS
W
OE
Lower byte read
ACT
ACT
NAC
NAC
ACT
Row
address
APD
VLD
OPN
NO
Upper byte read
ACT
NAC
ACT
NAC
ACT
APD
APD
OPN
VLD
NO
Word read
ACT
ACT
ACT
NAC
ACT
APD
APD
VLD
VLD
NO
Lower byte write
ACT
ACT
NAC
ACT
NAC
APD
APD
DIN
DNC
NO
Upper byte write
ACT
NAC
ACT
ACT
NAC
APD
APD
DNC
DIN
NO
Word write
ACT
ACT
ACT
ACT
NAC
APD
APD
DIN
DIN
NO
RAS-only refresh
ACT
NAC
NAC
DNC
DNC
APD
DNC
OPN
OPN
YES
Hidden refresh
ACT
ACT
ACT
NAC
ACT
DNC
DNC
VLD
VLD
YES
CAS before RAS refresh
ACT
ACT
ACT
DNC
DNC
DNC
DNC
OPN
OPN
YES
Stand-by
NAC
DNC
DNC
DNC
DNC
DNC
DNC
OPN
OPN
NO
Remark
EDO mode
identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
4
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467405Bxx / M5M465405Bxx
BLOCK DIAGRAM
Vcc (3.3V)
CAS
RAS
WRITE CONTROL
INPUT
W
CLOCK GENERATOR
CIRCUIT
A0~A11
(Note)
A0
COLUMN DECODER
A1
A4
A5
ADDRESS INPUTS
A6
A7
A8
A9
DQ2
DQ3
A0~
A12
(Note)
A10
A11
DQ1
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW DECODER
A3
ROW & COLUMN
ADDRESS BUFFER
A2
Vss (0V)
(4)
DATA IN
BUFFERS
ROW ADDRESS
STROBE INPUT
MEMORY CELL
(67108864 BITS)
(4)
DATA OUT
BUFFERS
COLUMN ADDRESS
STROBE INPUT
DATA
INPUTS / OUTPUTS
DQ4
OE OUTPUT ENABLE
INPUT
A12
(Note)
Note
:
Refer to Page 1 (ADDRESS)
M5M467805Bxx / M5M465805Bxx
BLOCK DIAGRAM
Vcc (3.3V)
CAS
RAS
WRITE CONTROL
INPUT
W
A0~A10
A0
(Note)
COLUMN DECODER
A1
A2
A5
ADDRESS INPUTS
A6
A7
A8
A9
A0~
A12
MEMORY CELL
(67108864 BITS)
DQ4
DATA
INPUTS / OUTPUTS
DQ6
DQ7
DQ8
OE OUTPUT ENABLE
INPUT
A11
A12
(Note)
Note
5
DQ2
DQ5
(Note)
A10
DQ1
DQ3
SENSE REFRESH
AMPLIFIER & I /O CONTROL
ROW DECODER
A4
ROW & COLUMN
ADDRESS BUFFER
A3
Vss (0V)
(8)
DATA IN
BUFFERS
ROW ADDRESS
STROBE INPUT
CLOCK GENERATOR
CIRCUIT
(8)
DATA OUT
BUFFERS
COLUMN ADDRESS
STROBE INPUT
:
Refer to Page 1 (ADDRESS)
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M465165Bxx
BLOCK DIAGRAM
ROW ADDRESS
RAS
STROBE INPUT
LOWER BYTE CONTROL LCAS
COLUMN ADDRESS
STROBE INPUT
UPPER BYTE CONTROL UCAS
COLUMN ADDRESS
STROBE INPUT
CIRCUIT
DATA IN
BUFFERS
BUFFERS
BUFFERS
(8)LOWER
W
DATA OUT
UPPER
DATA IN
LOWER
(8)LOWER
VSS (0V)
(8)UPPER
WRITE CONTROL INPUT
VCC (3.3V)
CLOCK GENERATOR
DQ1
DQ2
LOWER DATA
INPUTS / OUTPUTS
DQ8
A0~A9
6
SENSE REFRESH
AMPLIFIER & I /O
DQ9
DQ10
UPPER DATA
INPUTS / OUTPUTS
MEMORY CELL
(67108864BITS)
BUFFERS
A11
(8)UPPER
A0 ~
DATA OUT
CONTROL
ROW DECODER
ROW & COLUMN
COLUMN DECODER
ADDRESS BUFFER
ADDRESS INPUTS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DQ16
OE OUTPUT ENABLE
INPUT
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc
Supply voltage
VI
Input voltage
V0
Output voltage
I0
Output current
Pd
Power dissipation
Topr
Operating temperature
Tstg
Storage temperature
Conditions
Unit
~ 4.6
-0.5 ~ 4.6
-0.5 ~ 4.6
With respect to Vss
Ta=25 C
V
V
V
50
mA
1000
mW
~ 70
-65 ~ 150
0
RECOMMENDED OPERATING CONDITIONS
Symbol
Ratings
-0.5
~ 70 C, unless
(Ta=0
Min
Nom
Max
C
otherwise noted) (Note 1)
Limits
Parameter
C
Unit
Vcc
Supply voltage
3.0
3.3
3.6
V
Vss
Supply voltage
0
0
0
V
VIH
High-level input voltage, all inputs
2.0
Vcc+0.3
V
VIL
Low-level input voltage, all inputs
-0.3
0.8
V
Note 1 : All voltage values are with respect to Vss.
ELECTRICAL CHARACTERISTICS
[M5M467405B / M5M467805B]
Symbol
(Ta=0
~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless
Parameter
Test conditions
VOH
High-level output voltage
IOH=-2mA
VOL
Low-level output voltage
IOZ
Off-state output current
IOL=2mA
Q floating 0V ≤ VOUT
II
Input current
ICC1 (AV)
Average supply current
from Vcc
operating
(Note 3,4,5)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
Average supply current
from Vcc
(Note 6)
stand-by
otherwise noted) (Note 2)
≤
Vcc
0V≤VIN ≤ Vcc+0.3V, Other input pins=0V
M5M467405B-5,5S
M5M467805B-5,5S
M5M467405B-6,6S
M5M467805B-6,6S
M5M467405B-5,5S
-6,6S
M5M467805B-5,5S
-6,6S
RAS, CAS cycling
tRC=tWC=min.
output open
RAS= CAS =VIH, output open
Average supply current
from Vcc
EDO-Mode
(Note 3,4,5)
M5M467405B-5,6
M5M467805B-5,6
M5M467405B-5S,6S
M5M467805B-5S,6S
M5M467405B-5,5S
M5M467805B-5,5S
M5M467405B-6,6S
M5M467805B-6,6S
Average supply current
from Vcc
CAS before RAS refresh
(Note 3,5)
mode
M5M467405B-5,5S
M5M467805B-5,5S
M5M467405B-6,6S
M5M467805B-6,6S
Limits
Min
Typ
Max
Unit
2.4
Vcc
0
0.4
V
-10
10
-10
10
µA
µA
V
100
mA
90
1
mA
0.5
RAS= CAS ≥Vcc -0.2V,output open
0.3
RAS=VIL, CAS cycling
tHPC=min.
output open
100
CAS before RAS refresh cycling
tRC=min.
output open
130
mA
90
mA
120
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column Address can be changed once or less while RAS=VIL and CAS=VIH.
7
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
ELECTRICAL CHARACTERISTICS
[M5M465405B / M5M465805B]
Symbol
(Ta=0
~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless
Parameter
Test conditions
VOH
High-level output voltage
IOH=-2mA
VOL
Low-level output voltage
IOZ
Off-state output current
IOL=2mA
Q floating 0V ≤ VOUT
II
Input current
ICC1 (AV)
Average supply current
from Vcc
operating
(Note 3,4,5)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
otherwise noted) (Note 2)
≤
Vcc
0V≤VIN ≤ Vcc+0.3V, Other input pins=0V
Average supply current
from Vcc
(Note 6)
stand-by
M5M465405B-5,5S
M5M465805B-5,5S
M5M465405B-6,6S
M5M465805B-6,6S
M5M465405B-5,5S
-6,6S
M5M465805B-5,5S
-6,6S
Limits
Min
Typ
Vcc
0
0.4
V
-10
10
µA
µA
-10
10
Average supply current
from Vcc
CAS before RAS refresh
(Note 3,5)
mode
M5M465405B-5,5S
M5M465805B-5,5S
M5M465405B-6,6S
M5M465805B-6,6S
V
130
mA
120
RAS= CAS =VIH, output open
Average supply current
from Vcc
EDO-Mode
(Note 3,4,5)
Unit
2.4
RAS, CAS cycling
tRC=tWC=min.
output open
M5M465405B-5,6
M5M465805B-5,6
RAS= CAS ≥Vcc -0.2V,output open
M5M465405B-5S,6S
M5M465805B-5S,6S
M5M465405B-5,5S
RAS=VIL, CAS cycling
M5M465805B-5,5S
tHPC=min.
M5M465405B-6,6S
output open
M5M465805B-6,6S
Max
1
mA
0.5
0.3
100
mA
90
130
CAS before RAS refresh cycling
tRC=min.
output open
mA
120
[M5M465165B]
Symbol
Parameter
Test conditions
VOH
High-level output voltage
IOH=-2mA
VOL
Low-level output voltage
IOL=2mA
IOZ
Off-state output current
II
ICC1 (AV)
ICC2 (AV)
ICC4 (AV)
ICC6 (AV)
8
Limits
Min
Typ
Max
Unit
2.4
Vcc
0
0.4
Q floating 0V ≤ VOUT ≤ Vcc
V
-10
10
Input current
0V
-10
µA
µA
Average supply current
M5M465165B-5,5S
from Vcc
(Note 3,4,5) M5M465165B-6,6S
operating
RAS, CAS cycling
tRC=tWC=min.
output open
Average supply current
from Vcc
(Note 6)
stand-by
M5M465165B-5,5S
-6,6S
M5M465165B-5,6
≤ VIN ≤
Vcc+0.3V, Other input pins=0V
RAS= CAS =VIH, output open
M5M465165B-5S,6S
RAS= CAS
≥ Vcc -0.2V, output open
10
140
130
0.5
120
Average supply current
from Vcc
CAS before RAS refresh
(Note 3,5)
mode
CAS before RAS refresh cycling
tRC=min.
output open
140
MITSUBISHI
ELECTRIC
mA
0.3
RAS=VIL, CAS cycling
tHPC=min.
output open
M5M465165B-6,6S
mA
1
Average supply current
M5M465165B-5,5S
from Vcc
(Note 3,4,5) M5M465165B-6,6S
EDO-Mode
M5M465165B-5,5S
V
110
mA
mA
130
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE
Symbol
~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless
(Ta=0
Parameter
otherwise noted)
Limits
Test conditions
CI (A)
Input capacitance,address inputs
CI (OE)
Input capacitance, OE input
CI (W)
Input capacitance, write control input
CI (RAS)
Input capacitance, RAS input
CI (CAS)
CI / O
Min
Max
5
Typ
Unit
pF
7
pF
7
pF
7
pF
Input capacitance, CAS input
7
pF
Input/Output capacitance, data ports
7
pF
SWITCHING CHARACTERISTICS
VI=Vss
f=1MHZ
Vi=25mVrms
(Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Limits
Symbol
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Unit
Max
tCAC
Access time from CAS
(Note 7,8)
13
15
ns
tRAC
Access time from RAS
(Note 7,9)
50
60
ns
tAA
Column address access time
(Note 7,10)
25
30
ns
tCPA
Access time from CAS precharge
(Note 7,11)
28
33
ns
tOEA
Access time from OE
(Note 7)
13
15
ns
tOHC
Output hold time from CAS
tOHR
Output hold time from RAS
tCLZ
tOEZ
5
5
(Note 13)
5
5
ns
ns
Output low impedance time from CAS low
(Note 7)
5
Output disable time after OE high
(Note 12)
13
15
tWEZ
Output disable time after W high
(Note 12)
13
15
tOFF
Output disable time after CAS high
(Note 12,13)
13
15
tREZ
Output disable time after RAS high
(Note 12,13)
13
15
ns
5
ns
ns
ns
ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing RAS-only refresh or CAS before RAS refresh).
Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are VOH=2.0V and VOL=0.8V.
8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tOEZ(max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ± 10 µA) and is
not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
9
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
(Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted See notes 14,15)
Symbol
Limits
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Unit
Max
tREF
Refresh cycle time
tREF
Refresh cycle time (S-version only)
tRP
RAS high pulse width
tRCD
Delay time, RAS low to CAS low
tCRP
Delay time, CAS high to RAS low
5
5
ns
tRPC
Delay time, RAS high to CAS low
CAS high pulse width
0
8
0
10
ns
tCPN
tRAD
Column address delay time from RAS low
tASR
Row address setup time before RAS low
tASC
Column address setup time before CAS low
tRAH
Row address hold time after RAS low
8
10
ns
tCAH
Column address hold time after CAS low
8
10
ns
tDZC
Delay time, data to CAS low
(Note19)
0
0
ns
tDZO
Delay time, data to OE low
(Note19)
0
0
ns
tRDD
Delay time, RAS high to data
(Note20)
13
15
ns
tCDD
Delay time, CAS high to data
(Note20)
13
15
tODD
Delay time, OE high to data
(Note20)
13
15
ns
ns
tWED
Delay time, W low to data
Transition time
(Note20)
(Note21)
13
tT
64
64
ms
128
128
ms
30
(Note16)
(Note17)
40
14
37
25
10
45
ns
ns
12
0
(Note18)
ns
14
30
ns
13
ns
ns
0
10
0
0
15
1
50
1
ns
ns
50
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA.
17: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD or tWED must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Symbol
Limits
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Unit
Max
tRC
Read cycle time
84
tRAS
RAS low pulse width
50
10000
60
10000
ns
tCAS
CAS low pulse width
8
10000
10
10000
ns
tCSH
CAS hold time after RAS low
35
40
ns
tRSH
RAS hold time after CAS low
13
15
ns
tRCS
Read Setup time before CAS low
0
0
ns
tRCH
Read hold time after CAS high
(Note 22)
0
0
ns
tRRH
Read hold time after RAS high
(Note 22)
0
0
ns
tRAL
tCAL
Column address to RAS hold time
Column address to CAS hold time
25
30
ns
13
18
ns
tORH
RAS hold time after OE low
13
15
ns
tOCH
CAS hold time after OE low
13
15
ns
104
ns
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
10
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Unit
Max
tWC
Write cycle time
84
tRAS
RAS low pulse width
50
10000
60
10000
ns
tCAS
CAS low pulse width
8
10000
10
10000
ns
tCSH
CAS hold time after RAS low
35
40
ns
tRSH
RAS hold time after CAS low
13
15
ns
tWCS
Write setup time before CAS low
0
0
ns
tWCH
Write hold time after CAS low
8
10
ns
tCWL
CAS hold time after W low
8
10
ns
tRWL
RAS hold time after W low
8
10
ns
tWP
Write pulse width
8
10
ns
tDS
Data setup time before CAS low or W low
0
0
ns
tDH
Data hold time after CAS low or W low
8
10
ns
(Note 24)
104
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Max
tRWC
Read write/read modify write cycle time
tRAS
RAS low pulse width
75
10000
89
10000
ns
tCAS
CAS low pulse width
38
10000
44
10000
ns
tCSH
CAS hold time after RAS low
70
82
ns
tRSH
RAS hold time after CAS low
38
44
ns
tRCS
Read setup time before CAS low
0
0
ns
tCWD
Delay time, CAS low to W low
(Note24)
28
32
ns
tRWD
Delay time, RAS low to W low
(Note24)
65
77
ns
tAWD
Delay time, address to W low
(Note24)
40
47
ns
tOEH
OE hold time after W low
13
15
ns
(Note23)
109
Unit
133
ns
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD (min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
11
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle,
Read Write Mix Cycle, Hi-Z control by OE or W)
(Note 25)
Limits
Symbol
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S
M5M465165B-5,5S M5M465165B-6,6S
Parameter
Min
Max
Min
Unit
Max
tHPC
tHPRWC
EDO mode read/write cycle time
EDO Mode read write / read modify write cycle time
20
25
ns
55
66
tDOH
tRAS
Output hold time from CAS low
RAS low pulse width for read write cycle
ns
5
5
(Note26)
tCP
CAS high pulse width
(Note27)
tCPRH
RAS hold time after CAS precharge
28
33
ns
tCPWD
tCHOL
(Note24)
Delay time, CAS precharge to W low
Hold time to maintain the data Hi-Z until CAS access
43
50
ns
7
7
ns
tOEPE
OE Pulse Width (Hi-Z control)
7
7
ns
tWPE
W Pulse Width (Hi-Z control)
7
ns
tHCWD
Delay time, CAS low to W low after read
7
28
32
ns
tHAWD
Delay time, Address to W low after read
40
47
ns
tHPWD
Delay time, CAS precharge to W low after read
43
50
ns
tHCOD
Delay time, CAS low to OE high after read
13
15
ns
tHAOD
Delay time, Address to OE high after read
25
30
ns
tHPOD
Delay time, CAS precharge to OE high after read
28
33
ns
65
100000
77
100000
ns
ns
8
13
10
16
ns
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
26: tRAS(min) is specified as two cycles of CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max) , access time is controlled exclusively by tCAC.
CAS before RAS Refresh Cycle
Symbol
Parameter
(Note 28)
Limits
M5M46X405B-5,5S M5M46X405B-6,6S
M5M46X805B-5,5S M5M46X805B-6,6S Unit
M5M465165B-5,5S M5M465165B-6,6S
Min
tCSR
CAS setup time before RAS low
tCHR
Max
Min
Max
5
5
ns
CAS hold time after RAS low
10
10
ns
tRSR
Read setup time before RAS low
10
10
ns
tRHR
Read hold time after RAS low
10
10
ns
Note 28: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
12
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
SELF REFRESH SPECIFICATIONS
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics
and requirements than the below are same as normal devices.
ELECTRICAL CHARACTERISTICS
Symbol
ICC8 (AV)
ICC9 (AV)
(Ta=0 ~ 70 C , Vcc=3.3V
Parameter
otherwise noted) (Note 2)
Test conditions
Average supply current
from Vcc
Self - Refresh cycle
(note 6)
M5M46X405B-5S,6S
M5M46X805B-5S,6S
M5M465165B-5S,6S
(Ta=0 ~ 70 C , Vcc=3.3V
Min
Limits
Typ
CAS before RAS refresh cycling
input high level ≥ Vcc-0.2V
input low level ≤ 0.2V
output = OPEN , tRC = 31.25µs
tRAS = tRAS(min) ~ 300ns
Average supply current
M5M46X405B-5S,6S
from Vcc
M5M46X805B-5S,6S
Extended - Refresh cycle M5M465165B-5S,6S
(note 5,6)
TIMING REQUIREMENTS
± 0.3V, Vss=0V, unless
RAS = CAS
≤ 0.2V
output = OPEN
± 0.3V, Vss=0V, unless
Max
Unit
500
µA
400
µA
otherwise noted See notes 14,15)
Limits
Symbol
Parameter
M5M46X405B-5S M5M46X405B-6S
M5M46X805B-5S M5M46X805B-6S
M5M465165B-5S M5M465165B-6S
Min
Max
Min
Unit
Max
100
100
µS
tRPS
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
84
104
ns
tCHS
Self Refresh CAS hold time
- 50
- 50
ns
tRASS
SELF REFRESH ENTRY & EXIT CONDITIONS
(1) In case of CBR distributed refresh
The last / first full refresh cycles must be made within
on the condition of tNS ≤ 128 ms and tSN ≤ 128 ms.
tNS / tSN before / after self refresh ,
tSN
tNS
Self refresh period
DISTRIBUTED REFRESH
< 128 ms >
DISTRIBUTED REFRESH
< 128 ms >
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS ≤ 16 ms and tSN ≤ 16 ms.
tSN
tNS
Self refresh period
BURST REFRESH
< 128 ms >
13
BURST REFRESH
< 128 ms >
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams
Read Cycle
(Note 29)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC
tRSH
tCRP
tCAS
VIH
CAS
tCPN
LCAS / UCAS VIL
(at M5M465165Bxx only)
tASR
VIH
Address
tRAL
tCAL
tRAD
tRAH
tASC
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
VIL
tASR
tCAH
tRRH
tRCH
tRCS
VIH
W
VIL
tDZC
tCDD
tRDD
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
Hi-Z
tREZ
tCAC
tAA
tCLZ
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
tWEZ
tOFF
tOHC
tOHR
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tODD
tOEA
tOCH
VIH
OE
tORH
VIL
Note 29:
Indicates the don't care input.
VIH(min) ≤ VIN ≤ VIH(max) or VIL(min)
≤ VIN ≤ VIL(max)
Indicates the invalid output.
Indicates the skew of the two inputs. (at M5M465165Bxx only)
14
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
tRPC
tCRP
tCAS
VIH
CAS
LCAS / UCAS
VIL
(at M5M465165Bxx only)
tASR
VIH
Address
VIL
tRAH
tASC
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tWCS
ROW
ADDRESS
tWCH
VIH
W
VIL
tDS
DQ1 ~ DQ4 (8,16)
(INPUTS)
tDH
VIH
DATA VALID
VIL
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
Hi-Z
VIH
OE
VIL
15
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Delayed Write)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRPC tCRP
tRSH
tCAS
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Bxx only)
tASR
VIH
Address
VIL
tRAH
tASC
ROW
ADDRESS
tCAH
tASR
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tRCS
tWP
VIH
W
VIL
tWCH
tDS
tDZC
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
Hi-Z
tDH
DATA
VALID
tCLZ
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
Hi-Z
Hi-Z
tDZO
tOEH
tOEZ
tODD
VIH
OE
VIL
16
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCSH
tCRP
tRCD
tCRP
tRSH
tCAS
VIH
CAS
LCAS / UCAS VIL
tRAD
(at M5M465165Bxx only)
tASR
tRAH
VIH
Address
VIL
tASR
tCAH
tASC
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
tCWL
tRWL
tWP
tAWD
tCWD
tRWD
tRCS
VIH
W
VIL
tDS
tDZC
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIH
Hi-Z
VIL
tDH
DATA VALID
tCAC
tAA
tCLZ
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOH
Hi-Z
Hi-Z
DATA
VALID
VOL
tRAC
tODD
tDZO
tOEA
tOEH
tOEZ
VIH
OE
VIL
17
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tHPC
tCAS
tCP
tCAS
tRSH
tCAS
tCP
tRPC
tCRP
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Bxx only)
tRAD
tASR
VIH
Address
VIL
tRAH
tCPRH
tASC
tCAH
tASC
COLUMN
ADDRESS-1
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS-3
COLUMN
ADDRESS-2
tRCS
tRAL
tCAL
tASR
tCAH
tCAL
tCAL
ROW
ADDRESS
tRRH
tRCH
VIH
W
VIL
tWEZ
tDZC
tRDD
tCDD
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
Hi-Z
tAA
tCLZ
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
Hi-Z
tAA
tAA
tDOH
tDOH
DATA
VALID-1
tRAC
tDZO
tCAC
tCAC
tCAC
tCPA
tOEA
DATA
VALID-2
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tOEZ
tOCH
VIH
OE
VIL
tODD
18
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Write Cycle (Early Write)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRSH
tHPC
tRCD
tCAS
tCP
tCAS
tCP
tCAS
tRPC
tCRP
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Bxx only)
VIH
Address
VIL
tCAL
tCAL
tASR
tRAH
ROW
ADDRESS
tCAH
tASC
COLUMN
ADDRESS-1
tCAH
tASC
COLUMN
ADDRESS-2
tCAL
tCAH
tASC
COLUMN
ADDRESS-3
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
tDS
tDH
tDS
tDH
tDS
tDH
tASR
ROW
ADDRESS
VIH
W
VIL
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIH
VIL
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
DATA
VALID-1
DATA
VALID-2
DATA
VALID-3
Hi-Z
VIH
OE
VIL
19
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRP
tRAS
VIH
RAS
tRPC
VIL
tRWL
tCSH
tRCD
tCRP
tCAS
tHPRWC
tCAS
tCP
tCRP
VIH
CAS
LCAS / UCAS VIL
tRAD
(at M5M465165Bxx only)
tASR
VIH
Address
VIL
tRAH
tASC
tCAH
tASC
ROW
ADDRESS
tASR
COLUMN
ADDRESS-2
COLUMN
ADDRESS-1
tAWD
tRCS
tCWL
tCAH
tAWD
tCWD
tCWL
tCWD
tWP
ROW
ADDRESS
tRCS
tWP
VIH
W
VIL
tRWD
tCPWD
tDZC
tDH
tDS
DQ1 ~ DQ4 (8,16) VIH
(INPUTS)
VIL
Hi-Z
DATA
VALID-2
tCAC
tAA
tCLZ
tCLZ
Hi-Z
Hi-Z
DATA
VALID
-1
tRAC
tOEA
VIH
Hi-Z
DATA
VALID
-2
tCPA
tDZO
tODD
tOEZ
OE
Hi-Z
tCAC
tDZO
tDH
tDS
DATA
VALID-1
tAA
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
tDZC
tODD
tOEH
tOEH
tOEA
tOEZ
VIL
20
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
(Note 30)
tRAS
tRP
tRWL
VIH
RAS
tRPC
VIL
tCSH
tCRP
tRCD
tHPC
tCP
tCAS
tCAS
tHPRWC
tCWL
VIH
CAS
tCRP
tCAS
tCP
LCAS / UCAS VIL
(at M5M465165Bxx only)
tRAD
tASR
VIH
Address
VIL
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
COLUMN
ADDRESS-1
tCAH
tASC
COLUMN
ADDRESS-2
tRCS
tCPWD
tAWD
tCWD
tCAL
tCAL
ROW
ADDRESS
COLUMN
ADDRESS-3
tWCH
tWCS
tASR
tCAH
tWP
VIH
W
VIL
tDZC
tDH
tDS
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
DATA
VALID-2
tCAC
tAA
VOH
tRAC
tDZO
DATA
VALID
-3
tCPA
tOEA
tOEZ
tDZO
tOEA
tOEZ
tOEH
tOCH
VIH
OE
DATA
VALID-3
tCLZ
DATA
VALID
-1
VOL
tDH
tCAC
tWEZ
Hi-Z
tDS
tAA
tWED
tCLZ
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
tDZC
VIL
tODD
tODD
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
21
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
(Note 30)
VIH
RAS
VIL
tHPC
CAS
VIH
LCAS / UCAS
VIL
(at M5M465165Bxx only)
tCP
tASC
Address
VIH
VIL
tCAS
tCAS
tCAH
tASC
COLUMN
ADDRESS-1
tCAH
tASC
COLUMN
ADDRESS-2
tRCH
tCAL
tCAH
COLUMN
ADDRESS-3
tCAL
tWCH
tWCS
VIH
W
VIL
tHCWD
tHAWD
tDH
tHPWD
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIH
tCAC
tCAC
tAA
tCPA
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
tAA
tWED
tCPA
tWEZ
DATA
VALID-1
tHCOD
tHAOD
VIH
Hi-Z
DATA
VALID-2
Hi-Z
VIL
tDZC
tDS
tOEZ
tODD
tCLZ
Hi-Z
DATA
VALID-3
tDZC
tOEA
tHPOD
OE
VIL
Note 30: OE=L; W Hi-Z control
OE=H; OE Hi-Z control
22
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRAS
tRP
VIH
RAS
VIL
tCSH
CAS
tCRP
tRCD
tASR
tRAD
tRAH
tASC
tCAS
tCP
tHPC
tCAS
tCP
tRSH
tCAS
tCPRH
tASC
tCAH
tRPC
tCRP
VIH
LCAS / UCAS VIL
(at M5M465165Bxx only)
VIH
Address
VIL
ROW
ADDRESS
tCAH
tASC
COLUMN
ADDRESS-1
tCAH
COLUMN
ADDRESS-2
tASR
ROW
ADDRESS
COLUMN
ADDRESS-3
tRRH
tRAL
tRCS
tRCH
VIH
W
VIL
tWEZ
tDZC
DQ1 ~ DQ4 (8,16)
(INPUTS)
tRDD
tCDD
VIH
Hi-Z
tCAC
tCAC
VIL
tAA
tRAC
DATA
VALID
-1
tOEZ
VIH
DATA
VALID-2
tCPA
tOEA
Hi-Z
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tCHOL
tOCH
OE
tCLZ
tDOH
DATA
VALID-1
Hi-Z
tDZO
tAA
tAA
tCLZ
DQ1 ~ DQ4 (8,16) VOH
(OUTPUTS)
VOL
tCAC
tOEZ
tOEZ
tOEA
VIL
tOEPE
23
MITSUBISHI
ELECTRIC
tOEPE
tODD
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tCAS
tCP
tHPC
tCAS
tRSH
tCAS
tCP
tRPC
tCRP
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Bxx only)
tRAD
tASR
Address
VIH
VIL
tRAH
tASC
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS-1
tCPRH
tCAH
tASC
tCAH
COLUMN
ADDRESS-2
tASR
ROW
ADDRESS
COLUMN
ADDRESS-3
tRAL
tRRH
tRCH
tRCS
tRCS
tRCH
VIH
W
VIL
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIH
tRDD
tCDD
Hi-Z
VIL
tCAC
tAA
tAA
tCLZ
tDOH
Hi-Z
tRAC
tOEA
tWEZ
DATA
VALID-2
DATA
VALID-1
tDZO
tCAC
tCAC
tAA
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
tWEZ
tWPE
tDZC
tCPA
tOCH
tCLZ
Hi-Z
tREZ
tOHR
tOFF
tOHC
DATA
VALID-3
tCPA
tOEZ
VIH
OE
VIL
tODD
24
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
CAS
tCRP
VIH
LCAS / UCAS VIL
(at M5M465165Bxx only)
tASR
VIH
Address
VIL
tRAH
tASR
ROW
ADDRESS
ROW
ADDRESS
VIH
W
VIL
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
Hi-Z
VIH
OE
VIL
25
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC
tRP
tRC
tRAS
tRAS
tRP
VIH
RAS
VIL
tRPC tCSR
CAS
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH
LCAS / UCAS VIL
(at M5M465165Bxx only)
tCPN
tASR
VIH
ROW
ADDRESS
Address
VIL
COLUMN
ADDRESS
tRRH
tRCH tRSR
tRHR
tRSR
tRHR
tRCS
VIH
W
VIL
tCDD
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
tREZ
tOHR
tOFF
tOHC
VOH
Hi-Z
VOL
tODD
tOEZ
VIH
OE
VIL
26
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 31)
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
RAS
VIL
tRPC
tCRP
tRCD
tCRP
tCHR
tRSH
VIH
CAS
LCAS / UCAS VIL
(at M5M465165xx only)B
tRAD
tASR
Address
VIH
VIL
tRAH
tASC
tASR
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tRCS
tRAL
tRRH tRSR
tRHR
VIH
W
VIL
tCDD
tDZC
VIH
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIL
tRDD
Hi-Z
tREZ
tOHR
tCAC
tAA
tCLZ
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOH
Hi-Z
tOFF
tOHC
Hi-Z
DATA VALID
VOL
tRAC
tDZO
tOEA
tORH
tOEZ
tODD
VIH
OE
VIL
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
27
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle
tRASS
tRP
tRPS
VIH
RAS
VIL
tRPC
tRPC tCSR
tCHS
tCRP
VIH
CAS
LCAS / UCAS VIL
(at M5M465165Bxx only)
tCPN
tASR
Address
VIH
ROW
ADDRESS
VIL
tRRH
tRCH tRSR
tRHR
VIH
W
VIL
tCDD
DQ1 ~ DQ4 (8,16)
(INPUTS)
VIH
VIL
tREZ
tOHR
tOFF
tOHC
VOH
DQ1 ~ DQ4 (8,16)
(OUTPUTS)
VOL
Hi-Z
tOEZ
VIH
OE
VIL
28
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read Cycle
(at M5M465165Bxx only)
tRC
tRP
tRAS
VIH
RAS
VIL
tRPC
tCSH
tCRP
LCAS
(or UCAS)
tCRP
tRSH
tRCD
VIH
VIL
tRPC
tCAS
UCAS
(or LCAS)
VIH
tCPN
VIL
tRAD
tASR
VIH
Address
VIL
tRAL
tCAL
tRAH
tASC
ROW
ADDRESS
tASR
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRRH
tRCS
tRCH
VIH
W
VIL
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tDZC
tCDD
tRDD
DQ9 ~ DQ16
VIH
(or DQ1 ~ DQ8)
(INPUTS)
VIL
Hi-Z
tREZ
tCAC
tAA
tCLZ
VOH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(OUTPUTS)
VOL
tWEZ
tOHR
tOFF
tOHC
Hi-Z
Hi-Z
DATA VALID
tRAC
tDZO
tOEZ
tOEA
tOCH
tODD
VIH
OE
VIL
tORH
29
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Early Write)
(at M5M465165Bxx only)
tWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
LCAS
(or UCAS)
tRCD
tRSH
tCRP
tRPC
tCRP
VIH
VIL
tCAS
UCAS
(or LCAS)
tRPC
VIH
VIL
tASR
VIH
Address
VIL
tRAH
tASC
tASR
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tWCS
ROW
ADDRESS
tWCH
VIH
W
VIL
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tDS
VIH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
VOH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
tDH
DATA VALID
Hi-Z
VIH
OE
VIL
30
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Write Cycle (Delayed Write)
(at M5M465165Bxx only)
tWC
tRP
tRAS
VIH
RAS
VIL
tRPC tCRP
tCSH
tCRP
LCAS
(or UCAS)
tRCD
tRSH
VIH
VIL
tRPC tCRP
tCAS
UCAS
(or LCAS)
VIH
VIL
tASR
VIH
Address
VIL
tRAH
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS
ROW
ADDRESS
tCWL
tRWL
tRCS
tWP
VIH
W
VIL
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
VOH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tWCH
tDZC
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
VIH
tDS
Hi-Z
tDH
DATA
VALID
tCLZ
VOH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO
tOEH
tOEZ
tODD
VIH
OE
VIL
31
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Byte Read-Write, Upper / (Lower) Byte Read-Modify-Write Cycle.
(at M5M465165Bxx only)
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tRCD
tCRP
LCAS
(or UCAS)
tRPC
tCRP
tRPC
tCRP
tRSH
VIH
VIL
tCAS
UCAS
(or LCAS)
VIH
VIL
tRAD
tASR
VIH
Address
VIL
tRAH
tASR
tCAH
tASC
ROW
ADDRESS
ROW
ADDRESS
COLUMN
ADDRESS
tAWD
tCWD
tRCS
tCWL
tRWL
tWP
tRWD
VIH
W
VIL
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
VOH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(OUTPUTS)
VOL
Hi-Z
tDH
tDS
tDZC
VIH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
Hi-Z
DATA VALID
tCAC
tAA
tCLZ
DQ9 ~ DQ16 VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
Hi-Z
Hi-Z
DATA
VALID
tRAC
tDZO
tODD
tOEA
tOEH
tOEZ
VIH
OE
VIL
32
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
(at M5M465165Bxx only)
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
LCAS
(or UCAS)
tRSH
tHPC
tRCD
tCP
tCAS
tCP
tCRP
tRPC
tCRP
VIH
VIL
tCAS
UCAS
(or LCAS)
tRPC
tCAS
VIH
VIL
tRAD
tASR
VIH
Address
VIL
tRAH
tCPRH
tASC
ROW
ADDRESS
tASC
tCAH
COLUMN
ADDRESS-1
tASC
tCAH
COLUMN
ADDRESS-2
ROW
ADDRESS
COLUMN
ADDRESS-3
tRAL
tRCS
tCAL
tCAL
tASR
tCAH
tRRH
tRCH
tCAL
VIH
W
VIL
tDZC
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
Hi-Z
tREZ
tCAC
tOHR
tAA
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
DATA
VALID-2
tCLZ
VIH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
tRDD
tCPA
tDZC
tCDD
Hi-Z
tCAC
tCAC
tAA
tAA
tDOH
tCLZ
DQ9 ~ DQ16 VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
Hi-Z
DATA
VALID-1
tRAC
tDZO
tWEZ
tOFF
tOHC
DATA
VALID-3
tCPA
tODD
tOEA
tOCH
tOEZ
VIH
OE
VIL
33
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Write Cycle (Early Write)
(at M5M465165Bxx only)
tRP
tRAS
VIH
RAS
VIL
tCSH
tHPC
tRSH
tCRP
LCAS
(or UCAS)
tRPC
tCRP
VIH
VIL
tRPC
tRCD
UCAS
(or LCAS)
tCAS
tCP
tCAS
tCP
tCAS
tCRP
VIH
VIL
tCAL
tASR
VIH
Address
VIL
tRAH
ROW
ADDRESS
tCAH
tASC
COLUMN
ADDRESS-1
tWCS
tWCH
tCAL
tCAH
tASC
COLUMN
ADDRESS-2
tWCS
tWCH
tCAL
tCAH
tASC
COLUMN
ADDRESS-3
tWCS
tWCH
tDS
tDH
tASR
ROW
ADDRESS
VIH
W
VIL
tDS
VIH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DATA
VALID-2
VOH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tDS
VIH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16 VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
tDH
tDH
DATA
VALID-3
DATA
VALID-1
Hi-Z
VIH
OE
VIL
34
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle
(at M5M465165Bxx only)
tRAS
tRP
VIH
RAS
tRPC
VIL
tCSH
tRWL
tCRP
tCRP
LCAS
(or UCAS)
VIH
VIL
tRPC
tRCD
UCAS
(or LCAS)
tHPRWC
tCAS
tCP
tCAS
tCRP
VIH
VIL
tASR
VIH
Address
VIL
tRAD
tRAH
ROW
ADDRESS
tASC
tCAH
tASC
tASR
ROW
ADDRESS
COLUMN
ADDRESS-2
COLUMN
ADDRESS-1
tAWD
tCWD
tRCS
tCWL
tCAH
tAWD
tCWL
tRCS
tCWD
tWP
tWP
VIH
W
VIL
tRWD
tCPWD
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tDZC
DQ9 ~ DQ16
VIH
(or DQ1 ~ DQ8)
(INPUTS)
VIL
tDH
tDS
Hi-Z
tDZC
Hi-Z
DATA
VALID-1
tCAC
tAA
tCLZ
tCLZ
Hi-Z
Hi-Z
DATA
VALID
-1
tRAC
tDZO
DATA
VALID-2
tCAC
tAA
VOH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
tDH
tDS
tCPA
tODD
tODD
tDZO
tOEA
tOEZ
VIH
Hi-Z
DATA
VALID
-2
tOEH
tOEH
tOEA
tOEZ
OE
VIL
35
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) CAS before RAS Refresh Cycle
(at M5M465165Bxx only)
tRP
tRP
tRAS
tRAS
VIH
RAS
tRC
tRC
VIL
tRPC
LCAS
(or UCAS)
tCRP
tRPC
tCSR
tRPC
tRPC
tCRP
tCRP
VIH
VIL
tRPC
tRPC
UCAS
VIH
(or LCAS)
VIL
tCRP
tCSR
tCHR
tCHR
tCPN
tASR
VIH
Address
ROW
ADDRESS
VIL
tRSR
tRCH
tRHR
tRSR
tRHR
tRCS
VIH
W
VIL
Å
@
Å
@
Å
@
Å
@
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
tOFF
tOHC
tREZ
tOHR
VOH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tOEZ
tCDD
tOFF
VIH
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16 VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
Hi-Z
tOEZ
tODD
VIH
OE
VIL
36
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Upper / (Lower) Hidden Refresh Cycle (Byte Read)
(at M5M465165Bxx only)
(Note 31)
tRC
tRC
tRAS
tRAS
tRP
tRP
VIH
tRPC
RAS
VIL
tRPC
tRCD
tCRP
LCAS
VIH
(or UCAS)
VIL
tRSH
tCRP
tCRP
tCRP
UCAS
VIH
(or LCAS)
VIL
tCHR
tRAD
tASR
VIH
Address
VIL
tASC
tRAH
ROW
ADDRESS
tASR
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tRCS
tRRH
tRAL
tRSR
tRHR
VIH
W
VIL
Å
@
Å
@
Å
@
Å
@
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
DQ1 ~ DQ8
VOH
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tDZC
DQ9 ~ DQ16
(or DQ1 ~ DQ8)
VIH
(INPUTS)
VIL
tCDD
Hi-Z
tOFF
tREZ
OFF
tOHC
tCAC
tCLZ
DQ9 ~ DQ16
VOH
(or DQ1 ~ DQ8)
(OUTPUTS) VOL
tOHR
Hi-Z
DATA VALID
tAA
tOEZ
tRAC
tDZO
tOEA
tODD
tORH
VIH
OE
VIL
37
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Byte Self Refresh Cycle
(at M5M465165Bxx only)
tRASS
tRP
tRPS
VIH
RAS
VIL
tRPC
tCRP
tRPC
tCSR
tRPC
tCRP
VIH
LCAS
(or UCAS)
VIL
tRPC
UCAS
VIH
(or LCAS)
VIL
tCHS
tCRP
tCPN
tASR
VIH
Address
ROW
ADDRESS
VIL
tRSR
tRCH
tRHR
VIH
W
VIL
Å
@
Å
@
Å
@
Å
@
DQ1 ~ DQ8
VIH
(or DQ9 ~ DQ16)
(INPUTS)
VIL
tOFF
tOHC
tREZ
tOHR
VOH
DQ1 ~ DQ8
(or DQ9 ~ DQ16)
(OUTPUTS) VOL
Hi-Z
tOEZ
tCDD
tOFF
DQ9 ~ DQ16
VIH
(or DQ1 ~ DQ8)
(INPUTS)
VIL
DQ9 ~ DQ16
VOH
(or DQ1 ~ DQ8)
(OUTPUTS)
VOL
Hi-Z
tOEZ
tODD
VIH
OE
VIL
38
MITSUBISHI
ELECTRIC
Jun. 1999
(Rev. 1.1)
MITSUBISHI LSIs
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable,but there is always the possibility that trouble may
occur with them. Trouble with semiconductors consideration to safety when making
your circuit designs,with appropriate measures such as (i) placement of substitutive,
auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application;they do not
convey any license under any intellectual property rights,or any other rights,belonging to
Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage,or infringement
of any third-party's rights,originating in the use of any product data,diagrams,charts or
circuit application examples contained in these materials.
• All information contained in these materials,including product data,diagrams and charts,
represent information on products at the time of publication of these materials,and are
subject to change by Mitsubishi Electric Corporation without notice due to product
improvements or other reasons. It is therefore recommended that customers contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use
in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,vehicular,
medical,aerospace,nuclear,or undersea repeater use.
•The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
•If these products or technologies are subject the Japanese export control restrictions,they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
•Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
39
MITSUBISHI
ELECTRIC
Jun. 1999