ON NCP81111MNzzTXG High speed digital controller Datasheet

NCP81111
3 Phase VR12.5­6 High
Speed Digital Controller
with SVID and I2C
Interfaces for 5 MHz
Desktop, Notebook CPU
Applications
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MARKING
DIAGRAM
The NCP81111 is a high performance digital single output three
phase VR12.5−6 compatible buck solution optimized to operate at
frequencies up to 5 MHz for Intel CPU applications. The NCP81111
and can also work as a general purpose I2C controlled multiphase
voltage regulator. The NCP81111 is designed to support the
NCP81163 digital phase doubler IC which expands the capability of
the part to 6 phases for high current handling. The controller includes
true differential voltage sensing, differential current sensing, digital
input voltage feed−forward, DAC feed forward, and adaptive voltage
positioning. These features combine to provide an accurately
regulated dynamic voltage system. The control system makes use of
digital constant on time modulation and is combined with an analog
and digital current sensing system. This system provides the fastest
initial response to dynamic load events to reduced system cost. On
board user programmable memory is included for configuring the
controller’s parameters. User programmable voltage and droop
compensation is internally integrated to minimize the total board
space used. The NCP81111 is optimized for use with DRMOS.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Meets Intel®’s VR12.5 Specifications
On Board EEPROM for User Configuration
High Performance Digital Architecture
Dynamic Reference Injection
Fully Differential Voltage Current Sense Amplifiers
“Lossless” DCR Current Sensing for Current Balancing
Thermally Compensated Inductor Current Sensing for Droop
User Adjustable Internal Compensation
Switching Frequency Range of 250 kHz − 5.0 MHz
Input Voltage Feed−forward
Startup into Pre−Charged Loads
Power Saving Phase Shedding
Supports Lower Power Operation in PS3
This is a Pb−Free Device
1
1
32
QFN32
CASE 485CE
NCP81111
zzRr
AWLYYWWG
G
NCP81111 = Specific Device Code
zz
= Configuration Option
Rr
= Revision Number
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device*
Package
Shipping†
NCP81111MNDFTXG
QFN32
(Pb−Free)
2500 / Tape &
Reel
NCP81111MNzzTXG
QFN32
(Pb−Free)
2500 / Tape &
Reel
*zz = Configurable Option, please contact Sales for
additional information.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• Desktop, Notebook Processors, and General Purpose I2C Controlled
Multiphase Regulators.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 4
1
Publication Order Number:
NCP81111/D
SDIO
ALERT#
SCLK
VR_RDY
VR_HOT#
T_SENSE
VSN
VSP
NCP81111
32
31
30
29
28
27
26
25
SDA
1
24
TEST1
SCL
2
23
TEST2/I2CADDR1
EN
3
22
CSP1
TEST3/I2CADDR0
4
21
CSN1
GND
19
CSN2
VCCD
7
18
CSP3
VCCA
8
17
CSN3
10
PWM1
VCCP
9
11
12
13
14
15
16
SMOD3
6
PWM3
VDIG
SMOD2
CSP2
PWM2
20
DRVON
5
SMOD1
VFF
Figure 1. Pinout Diagram
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2
NCP81111
VSP
VID<>
DAC
OV_THRESHOLD<>
OV_TRSHLD
OV_TRSHLD
3V
OVP
VSN
OVP COMPARATOR
COMPENSATION SETTINGS<>
AGND
DUAL DAC
VCCA
VDIG
UVLO
5us Blanking
UVLO
COMP
DIFFOUT
VFB
DIFFOUT
UVP
HIGH SPEED PROGRAMMABLE COMPENSATOR
0.85V
SDA
SCL
EN
SCLK
ALERT#
SDIO
SETTINGS
UVP MONITOR
DRVON
VR_RDY
V_THRESHOLD<>
VRHOT#
DAC
FAULT STATUS
ANALOG MONITORING
+
− STOP
COMP
Nonvolatile Memory
DIGITAL INTERFACE
+ V1P3
− DAC
+ VSP
− VSN
DIFFOUT
+ GND
+ DROOP_P
− DROOP_N
DROOP_P
Av
CSN
CSN
DROOP_N
DIFFOUT
STOP
CSP
CSP
GAIN<>
STOP CONTROL
+ CSP1
− CSN1
+ CSP2
− CSN2
+ CSP3
− CSN3
Ramp Current<>
Ramp Cap<>
Ramp Reset Voltage <>
Phase Count<>
Ioffset
V1P3
GAIN<>
DROOP CURRENT SUMMING AMP
RAMP
5ns
100MHz
RAMP_GO
SUMMING AMP
VN
DROOP GAIN CONTROL
RAMP
COMP
DIGITAL INTEGRATOR
RAMP GENERATOR
TRIGGER
VP
V1
TEMP_CONTROL<>
CSP1
COMP
ERROR AMP
1.3Vdc
RAMP COMPARATOR
CSP
0
CSN1
CSN
THERMAL COMPENSATION
PWM_GO
TON<10:0>
CLK_800MHZ
PWM
PWM1
Ton Timer
TEMP_CONTROL<>
CSP2
CSP
CSN2
CSN
ZCD_THRESHOLD<>
DAC
THERMAL COMPENSATION
CSP1
TRIGGER
PWM_GO1
PSx STATE
PWM_GO2
FAULTS
PWM_GO3
RAMP_GO
PHASE COUNT<>
SMOD1
ZCD1
SMOD2
SMOD3
ZDC1
PWM_GO
TON<10:0>
CLK_800MHZ
PWM
PWM2
Ton Timer
CSN1
TEMP_CONTROL<>
CSP3
PWM_GO
TON<10:0>
CLK_800MHZ
PWM CONTROL
ZCD COMPARE
CSP
Ton Timer
CSN3
CSN
THERMAL COMPENSATION
FREQ SETTING
TON1<>
PSx STATE
TON2<>
CSOUT
TON3<>
VFF_OUT<>
PHASE MUX
6BIT FLASH
+ CSP1
− CSN1
+ CSP2
− CSN2
+ CSP3
− CSN3
CSP
CSP
CSOUT<5:0>
CSN
CSN
TON CONTROL
VFF
AtoD
VFF_OUT<>
VFF MONITOR
CURRENT LIMIT
CURRENT LIMIT<>
DAC
+ CSP1
− CSN1
+ CSP2
− CSN2
+ CSP3
− CSN3
CSP
OCP
CSP
CSN
CSN
CURRENT LIMIT CURRENT SUMMING AMP
IOUT GAIN CONTROL
+ CSP1
− CSN1
+ CSP2
− CSN2
+ CSP3
− CSN3
CSP
CSP
IOUT_P
Av
PHASE MUX
+VSP
− VSN
+T_SENSE
−T_SENSE
IOUT_P
IOUT_N
10BIT AtoD
AOUT_P
IN_P
OUT<9:0>
IN_N
AOUT_N
CSN
IOUT CURRENT SUMMING AMP
CSN
IOUT_N
GAIN<>
Figure 2. Block Diagram
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3
PWM
PWM3
NCP81111
PIN LIST DESCRIPTION
Pin No.
Symbol
1
SDA
Serial Data Configuration Port
Description
2
SCL
Serial Clock Configuration Port
3
EN
Logic input. Logic high enables output.
4
TEST3/I2CCADR0
5
VFF
Input voltage monitor
6
VDIG
Digital power filter pin. Internally regulated
7
VCCD
5V digital VCC
8
VCCA
5V analog VCC
9
VCCP
5V driver VCC
10
PWM1
Phase 1 PWM output.
11
SMOD1
Low side FET enable signal
12
DRON
Gate driver enable
13
PWM2
Phase 2 PWM output
14
SMOD2
PWM 2 low side FET enable signal
15
PWM3
Phase 3 PWM output
16
SMOD3
PWM3 low side FET enable signal
17
CSN3
Inverting input to current balance sense amplifier for phase 2
18
CSP3
Non−Inverting input to current balance sense amplifier for phase 2
19
CSN2
Inverting input to current balance sense amplifier for phase 2
20
CSP2
Non−inverting input to current balance sense amplifier for phase 2
21
CSN1
Inverting input to current balance sense amplifier for phase 1
22
CSP1
Non−inverting input to current balance sense amplifier for phase 1
23
TEST2/ADDR1
24
TEST1
Debug and monitor port / I2C Programming Address Offset 0
Monitor port / I2C Programming Address Offset 1
Debug and monitor port
25
VSP
Non−inverting input to the core differential remote sense amplifier.
26
VSN
Inverting input to the core differential remote sense amplifier.
27
T_SENSE
Temp sense for the single phase converter
28
VR_HOT#
Thermal logic output for over temperature.
29
VR_RDY
Open drain output. High indicates that the core output is regulating.
30
SCLK
31
ALERT#
32
SDIO
Serial VID data interface.
FLAG
GND
Power supply return ( QFN Flag )
Serial VID clock.
Serial VID ALERT#.
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4
NCP81111
R34
100
R2
0.0
VSN
R12
J99
VSENSE J131
R4
R48
100
C51
AGND
Place Near J92 an J93
J94
J27
VDC
JP5
1
25
26
VSN
VSP
27
28
T_SENSE
VR_HOT#
29
CSN3
C89
23
CSN1
10.0
22
C88
100pF
AGND
21
R27
20
19
18
CSN2
C86
100pF
AGND
R10
C92
DNP
CSP3
10.0
SMOD3
PWM3
SMOD2
PWM2
DRON
SMOD1
PWM1
ETCH
AGND
AGND
14.0K
C83
.015uF R23
CSN3
C222
10uF
C84
CSP2
10.0
17
0.01uF
0.01uF
14.0K
C85
.015uF R22
C93
DNP
C82
0.01uF
2
VR_RDY
CSP3
VCCA
9
VFF
1.0K
30
VCCD
10
R40
J29
SCLK
31
CSN2
VCCP
8
VDIG
SMOD3
1.0K
CSP2
PWM3
7
R161
VFF
R47
J93
0k
CSP1
14.0K
C80
.015uF R24
C94
DNP
16
6
CSP1
CSN1
NCP81111
QFN 32, 5X5mm, 0P5
SMOD2
5
EN
TEST3/I2CADDR0
PWM2
4
J92
24
TEST1
15
0k
14
J95
R46
VR_RDY
R9
AGND
TEST2/ADDR1
DRVON
ENABLE
VR_RDY
SDA
SCL
13
3
12
2
SMOD1
SCL
ENABLE
PWM1
1
11
SCL
SDA
SDA
ALERT#
SDIO
FLAG
SDIO
ALERT
J131
SCLK
USB−I2C_COMM_MODULE
32
U6
33
AGND
GND
INPUT1
SCL
SCA
+5V
Place by phase 1 inductor
RT22
220K
0.0
75.0
54.9
130
1000pF
SDIO
0.0
R156
130
R155
R162
R3
R157
VCC_SENSE
VSP
V_1P05_VCCP VCCU
VR_HOT
49.9
J104
SCLK
2
J100
ALERT_VR
VSS_SENSE
C87
100pF
AGND
R45
V5_CONT
1
Figure 3. Three Phase Application Control Circuit
VDC
Place caps close to
DRMOS pins on top
VDC
VDC
C280 C281 C274
Place caps close to
DRMOS pins on top
22uF 22uF 1uF
C282 C283 C272
JP19
1
CSP1
4
PWM
38
4
BOOT
THWN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
DISB#
GH
ETCH
C37
0.1uF
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
7
15
43
35
34
33
32
31
30
29
L6
DNP
L2
VCCU
DNP
SW2
JP17
CSN2
ETCH
R15
DRON
SW2
GL2
GH2
C146
16
17
18
19
20
21
22
23
24
25
26
27
28
PWM2
J133J118
JP18
CSP2
ETCH
0.00
470pF
Place caps close to
DRMOS pins on top
39
40
R8
1.0
VDC
NCP5338
U1
PHASE
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C267
1uF
4.7uF
JP20
0.00
SMOD1
ZCD_EN#
C44
CSN1
ETCH
16
17
18
19
20
21
22
23
24
25
26
27
28
41
5
37
36
6
42
14
13
12
11
10
9
8
Place close
to DRMOS pins
SW1
GL1
GH1
DRON
NC
CGND
CGND
CGND
DNP
SW1
VCIN
VCCU
PWM1
R16
3
41
5
37
GL
GH
PWM
2
R14
1.00
L3
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
40
CGND
CGND
CGND
DISB#
4.7uF
V5_DRMOS
DNP
L5
GL
39
V5S
15
43
35
34
33
32
31
30
29
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
NCP5338
C50
C268
1uF
0.1uF
7
PHASE
36
ZCD_EN#
22uF 22uF 1uF
C38
6
1
U2
BOOT
NC
THWN
VCIN
3
Place close
to DRMOS pins
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
2
R18
1.00
38
42
14
13
12
11
10
9
8
V5S
V5_DRMOS
R7
1.0
SMOD2
Place close
to DRMOS pins
J132J117
C145
C284 C285 C277
470pF
Place close
to DRMOS pins
22uF 22uF 1uF
Place close
to DRMOS pins
1
VCIN
NC
ZCD_EN#
C52
PWM
GH
40
DISB#
CGND
CGND
CGND
39
GL
C269
1uF
4.7uF
4
38
U3
C39
0.1uF
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
NCP5338
BOOT
3
R20
1.00
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
2
THWN
42
14
13
12
11
10
9
8
V5S
V5_DRMOS
7
15
43
35
34
33
32
31
30
29
L7
DNP
L4
VCCU
DNP
SW3
JP21
CSN3
ETCH
16
17
18
19
20
21
22
23
24
25
26
27
28
SW3
GL3
GH3
DRON
41
5
37
6
R19
36
PWM3
JP22
CSP3
ETCH
0.00
R21
1.0
SMOD3
J134J119
C147
470pF
Place close
to DRMOS pins
Figure 4. Three Phase Applications Power Stage Circuit
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5
NCP81111
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
VFF
30 V
−0.3 V
N/A
N/A
VDIG
3.3 V
All Other Pins
6.5 V
−0.3 V
N/A
N/A
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Symbol
Typ
Unit
Thermal Characteristic, QFN Package (Note 1)
RqJA
44
_C/W
Operating Junction Temperature Range (Note 2)
TJ
−10 to 125
_C
−10 to 100
_C
_C
Operating Ambient Temperature Range
Maximum Storage Temperature Range
TSTG
−40 to +150
Moisture Sensitivity Level
QFN Package
MSL
1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
EN = high
30
40
50
mA
BIAS SUPPLY
VCC Quiescent Current
VCCA UVLO Threshold
EN = low
10
mA
PS3
40
mA
VCC rising
VCC falling
4.4
4.1
VCCA UVLO Hysteresis
VDIG UVLO Threshold
VDIG rising
VDIG falling
VDIG UVLO Hysteresis
V
V
200
mV
1.65
1.27
4.55
4.2
1.8
V
1.45
V
200
mV
ENABLE INPUT
Enable High Input Leakage Current
External 1k pull−up to 3.3 V
Upper Threshold
VUPPER
Lower Threshold
VLOWER
Total Hysteresis
VUPPER − VLOWER
Enable Delay Time
1.0
0.8
V
0.4
100
Measure time from Enable transitioning HI
to when DRON goes high, Vboot is not 0 V
mA
V
mV
1
ms
DIFFERENTIAL VOLTAGE SENSE
Input Bias Current
−400
400
nA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
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NCP81111
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Output High Voltage
Sourcing 500 mA
3.5
Output Low Voltage
Sinking 500 mA
Typ
Max
Unit
DRVON
Rise/Fall Time
Internal Pull Down Resistance
V
0.1
V
CL (PCB) = 20 pF,
DVo = 10% to 90%
10
ns
EN = Low
70
kW
IOUT MONITOR
Analog Gain Accuracy
Analog Gain Range
−3%
+3%
16
1024
Analog Gain Step Size
Analog IOUT Offset Accuracy
Digital Gain Step Size
Binary
weigh
ted
Gain = 64, CSx sum = 40 mV,
Digital Gain = 1
3
Digital gain is 2.8 format
LSB
0.4%
Digital Gain Range
0.004
4
ADC Voltage Range
0
2.56
V
−1
+1
%
1
LSB
ADC Total Unadjusted Error (TUE)
Max % error of the ideal value
ADC Differential Nonlinearity (DNL)
Highest 8−bits
ADC Conversion Time
ADC Conversion Rate
Per Channel
10
ms
33
kHz
INTERNAL RAMP
−5
Ramp Slope Accuracy
Ramp Reset Voltage Step Size
5
8
Maximum Ramp Reset Step
486
512
%
mV
538
mV
Ramp Slope Maximum
Single Phase Mode
4000
mV/ms
Ramp Slope Minimum
Single Phase Mode
5.6
mV/ms
Ramp Slope Step Size
Single Phase Mode Typical
5.3
5.6
5.88
mV/ms
20
mV
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Set Point Accuracy
Threshold is programmable
−20
Over Voltage Max Capability
Over Voltage Delay
VSP(A) rising to PWMx low
Under Voltage Threshold Below DAC−DROOP
VSP(A) falling
Under Voltage Hysteresis
VSP(A) rising
415
Under Voltage Delay
3
V
400
ns
450
475
mV
100
mV
150
ns
DROOP
Gain Accuracy
Programmable Gain Range
Guaranteed by Design
−2
+2
CSx sum to Diffout
0,0.3
16.5
Gain Step Size
1.2
Offset Accuracy
CSx input referred from 1.0 V to 2.0 V
−2.5
Common Mode Rejection
CSx input referred from 1.0 V to 2.0 V
60
Sum of CSx inputs
−3.5
%
%
2.5
80
mV
db
OVERCURRENT PROTECTION
ILIM Threshold Accuracy
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7
3.5
mV
NCP81111
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
OVERCURRENT PROTECTION
Step Size
Maximum Setting
Sum of CSx inputs
ILIM Delay
2
mV
126
mV
1000
ns
ZCD COMPARATOR
Offset Accuracy
Offset Programmable Range
Guaranteed by Design
Offset Step Size
Guaranteed by Design
−1.5
1.5
mV
−6.2
6.2
mV
0.2
mV
VR_HOT#
Output Low Resistance
I_VRHOT = −10 mA
13
W
Output Leakage Current
High Impedance State
−1.0
1.0
mA
(0°C and 125°C)
Using Murata thermistor
NCP18WM224J03RB (220 kW)
−4
4
°C
Internal Resistance Hot Range
50°C to 125°C
9.8
11.5
13.2
kW
Internal Resistance Cold Range
0°C to 50°C
146
172.5
198
kW
Bias Current Hot Range
50°C to 125°C
49.3
58
66.7
mA
Bias Current Cold Range
0°C to 50°C
4.1
4.83
5.6
mA
TSENSE
Temperature Accuracy
6 BIT CURRENT SHARE ADC
−24
Voltage Range
Differential Nonlinearity (DNL)
Step Size
Conversion Time
Common Mode Range
39
mV
2
LSB
1
mV
550
ns
0.5
2.5
V
VR_RDY (Power Good)
Output Low Saturation Voltage
IVR_RDY(A) = 4 mA,
0.3
V
Rise Time
External pull−up of 1 kW to 3.3 V, CTOT =
45 pF, DVo = 10% to 90%
100
ns
Fall Time
External pull−up of 1 kW to 3.3V, CTOT =
45 pF, DVo = 90% to 10%
10
ns
Output Voltage at Power−up
Output Leakage Current when High
VR_RDY pulled up to 5 V via 2 kW
VR_RDY = 5.0 V
−1.0
1.0
V
1.0
mA
6
ms
VR_RDY Delay (rising)
DAC=TARGET to VR_RDY
5
VR_RDY Delay (falling)
UVP response time
5
ms
VR_RDY Delay (falling)
OCP response time
1000
ns
VR_RDY Delay (falling)
OVP response time
250
ns
VR_RDY Delay (falling)
SetVID 0 V if register 34h is set to respond
VR_RDY Delay (falling)
Time after Enable transitions low
1.3
Output High Voltage
No Load
VCC
V
Output Low Voltage
No Load
GND
V
500
ns
1.5
ms
PWM
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8
NCP81111
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
PWM
Rise and Fall Time
CL (PCB) = 25 pF,
DVo = GND to VCC
Ton Accuracy
1
−5
Ton Step Size
ns
5
1.25
Ton Range
15
%
ns
2559
ns
SMOD
Output High Voltage
No Load
VCC
V
Output Low Voltage
No Load
GND
V
Rise and Fall Time
CL (PCB) = 25 pF,
DVo = GND to VCC
1
ns
VFF ADC / VFF UVLO
Note: UVLO threshold is programmable
Step Size
200
mV
Maximum Tracking Slew Rate
2.5
V/us
Maximum Input
25.5
V
General
The NCP81111 is a single output three phase digital controller designed to meet the Intel VR12.5 specifications with a serial
SVID control interface. The NCP81111 implements VR12.5 or VR12.6 depending on the device configuration.
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NCP81111
I2C USER COMMANDS
These commands operate on a subset range of address space and are primarily for use by end users during application
configuration.
USER_REG_READ
This command can read one or more bytes from the working register set. The address (USER_ADDR) specified with this
command is a working set address from the user address range (refer to the USER column in the Register Map). Only registers
which have read access (shown as (R) or (RW) in the USER column) can be read with this command. If the command is
specified with an address that does not have read access the device will respond with NA (not−acknowledge).
However, if a block of registers are read which start from a valid address, then via the auto−incrementing address point to
an address that does not have read access, then for those invalid registers the return value will be 00h (zeros). The invalid
registers do not stop the command, and the device will respond with an A (acknowledge). This allows a single
USER_REG_READ command to read a contiguous block of data even if it spans addresses that are not valid. Note that this
command requires a repeated START sequence to change the data direction. Also, for the final byte received by the master it
must signal end of data to the device by responding with a NA (not−acknowledge). This allows the device to release the data
line so the master can send the STOP sequence. If a long sequence of data is read, which due to the auto−incrementing address
exceeds the allowable address range, then the device will return zero values (00h) for bytes beyond the address boundary.
For a single−byte read the sequence is as follows:
S
I2C_ADDR+W
A
USER_REG_READ
A
USER_ADDR
A
Sr
I2C_ADDR+R
A
D0
NA
P
This will read the data from the working register map as shown:
Working Registers
Data
Address
D0
USER_ADDR
For a multi−byte read command the sequence is as follows:
S
I2C_ADDR+W
D1
A
D2
A
A
...
USER_REG_READ
NA
A
USER_ADDR
A
Sr
I2C_ADDR+R
A
D0
A
P
This will read the data from the working registers as shown:
Working Registers
Data
Address
D0
USER_ADDR
D1
USER_ADDR+1
D2
USER_ADDR+2
...
...
USER_REG_WRITE
This command will write one or more bytes into the working register set. The address (USER_ADDR) specified with this
command is a working set address from the user address range (refer to the USER column in the Register Map). Only registers
which have write access (shown as (RW) in the USER column) can be written with this command. If the command is specified
with an address that does not have write access the device will respond with NA (not−acknowledge). However, if a block of
registers are written which start from a valid address, then via the auto−incrementing address point to an address that does not
have write access, then for those invalid registers the input data will be ignored. The invalid registers do not stop the command,
and the device will respond with an A (acknowledge). This allows a single USER_REG_WRITE command to write a
contiguous block of data even if it spans addresses that are not valid. If a long sequence of data is written which exceeds the
allowable address range then the command will automatically terminate when the end of the address range is reached.
Attempting to write past this point will result in NA (not−acknowledge) responses from the device.
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NCP81111
For a single−byte write the sequence is as follows:
S
I2C_ADDR+W
A
USER_REG_WRITE
A
USER_ADDR
A
D0
A
P
A
...
A
P
This will insert data into the register as shown:
Working Registers
Data
Address
D0
USER_ADDR
For a multi−byte write command the sequence is as follows:
S
I2C_ADDR+W
A
USER_REG_WRITE
A
USER_ADDR
A
D0
A
D1
A
D2
This will insert a block of data into the registers as shown:
Working Registers
Data
Address
D0
USER_ADDR
D1
USER_ADDR+1
D2
USER_ADDR+2
...
...
USER_NVM_RELOAD
This command will reload the User NVM settings from the NVM into the working registers.
The sequence is as follows:
S
I2C_ADDR+W
A
USER_NVM_RELOAD
A
P
The command will reload all the registers at once and should complete in less than 50 ms (worst case). This can be used to
restore User settings after altering the working registers via the I2C interface. The reload is forced and does not require the
settings to be configured.
USER_NVM_WRITE
This is the primary method for writing the User NVM settings into the NVM.
The sequence is as follows:
S
I2C_ADDR+W
A
USER_NVM_WRITE
A
P
The command will write all the current User settings from the working registers into the NVM. It should complete in less
than 988 ms (worst case, 380 ms typical case).
I2C USER_POWER CONTROL
Due to the internal construction of the device, when the EN pin goes low the internal regulators will turn off and the device
will lose its working state. Subsequently if the EN pin goes high the device will reinitialize its state from the NVM
configuration. For purposes of test and application configuration it is useful to power cycle the device without necessarily
losing state. In addition, preserving state allows the device to optionally skip NVM load and/or auto−calibration sequences
resulting in a faster startup time. To accomplish this, the USER_POWER command was added which allows the user to
Enable/Disable the device without power−cycling the part. It also allows the NVM, working registers, and auto−calibration
behavior to be modified when exiting the DISABLED state. The key to this command is the concept of a “Virtual Enable”
signal. This virtual−EN signal can be controlled via the USER_POWER command and will behave in a similar way to the actual
EN−pin, however when the virtual−EN is set low it will not completely power off the device. The internal regulators and clocks
will continue running in order to preserve device state. Note, the EN−pin must remain high at all times when using the device
in this way.
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NCP81111
The command sequence is as follows:
S
I2C_ADDR+W
A
USER_POWER
A
POWER_SETTING
A
P
Where the POWER_SETTING byte is mapped as follows:
POWER_SETTING:
0
0
0
RESET_TEST
RESET_MEM
RESET_AUTOCAL
RESTART
ENABLE
− ENABLE − This bit is the “Virtual Enable” signal. When the device is in the DISABLED state, sending the
USER_POWER command with this bit set to “1” will cause the device to exit the DISABLED state and begin the
power−up sequence. The exact power−up sequence followed will depend on the other bit settings. If the device is in an
operational state (not DISABLED) and the command is issued with this bit set to “0” then the device will stop operation
and enter the DISABLED state.
− RESTART − This bit is used in conjunction with the ENABLE bit. It is used to immediately restart the device when the
DISABLED state has been entered. So when the device is in an operational state, if the USER_POWER command is
issued with this bit set to “1” and the ENABLE bit set to “0”, the device will stop operation, enter the DISABLED state,
and then immediately power−up again. It is in essence a fast toggle on the Virtual Enable signal, used to quickly cycle
the device through its power−up sequence.
− RESET_AUTOCAL − When this bit is set to “1”, upon exiting the DISABLED state, the device will reset its
auto−calibration state and proceed to recalibrate during power−up. Normally auto−calibration is only required if the
device has lost its state (thus it will occur anytime the actual EN−pin is toggled), however the procedure takes a few
milliseconds to complete. Since the device can retain state using this command, if this bit is set to “0”, the
auto−calibration settings will be retained and the procedure will be skipped. A “0” setting will allow the device to
power−up several milliseconds faster than normal.
− RESET_MEM − This bit controls the behavior of the working registers and the NVM during power−up. If the bit is set
to “1” then upon exiting the DISABLED state the working registers will be reinitialized − first the POR settings will be
applied, then the NVM will be read and those settings will be applied. Any changes to the working registers that were
not programmed to the NVM will be lost. If the bit is instead set to “0” then the device will retain all the settings that are
currently in the working registers. A “0” setting is useful for testing minor changes to device settings without needing to
program them to NVM.
− RESET_TEST − If the bit is set to “1” then upon exiting the DISABLED state, the test registers will be reset to their
POR defaults. A “1” setting is useful for quickly clearing all test modes when cycling through a power−up sequence. If
the bit is set to “0” then the test registers will be unaffected by the power−up sequence.
Example command sequences:
Starting from a normal operational state, issuing the following command:
S
I2C_ADDR+W
A
USER_POWER
A
00000000b
A
P
Will cause the part to exit to the DISABLED state and remain there. The test interface can then be used to modify the working
registers and adjust settings prior to re−enabling the part.
Starting from the DISABLED state, issuing the following command:
S
I2C_ADDR+W
A
USER_POWER
A
00000001b
A
P
Will cause the part to exit the DISABLED state and begin power−up. The working registers will not be affected during
power−up, and auto−calibration will be skipped (Note: this is only true if auto−cal has completed its sequence at least once.
Starting from any state, issuing the following command:
S
I2C_ADDR+W
A
USER_POWER
A
00000110b
A
P
Will cause the part to exit to the DISABLED state, then immediately begin power−up. The working registers will not be affected
during power−up, however the part will recalibrate.
Starting from any state, issuing the following command:
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NCP81111
S
I2C_ADDR+W
A
USER_POWER
A
00011010b
A
P
Will cause the part to exit to the DISABLED state, then immediately power−up again. On power−up it will clear the test
registers and reload the NVM into the working registers. It will skip the auto−calibration sequence. This is very similar to
toggling the EN−pin, but with a faster powerup time.
Starting from any state, issuing the following command:
S
I2C_ADDR+W
A
USER_POWER
A
00011110b
A
P
Will cause the part to exit to the DISABLED state, then immediately power−up again. On power−up the controller will clear
the test registers and reload the NVM into the working registers. It will recalibrate during power−up. This is exactly the same
as toggling the EN−pin, but with a slightly faster power−up time (due to regulators and clocks already being powered up and
running).
DEVICE CONFIGURATION
The following sections describe the configuration of certain device register groups based on function.
External Address Offset
There is an external address offset circuit which can be used to allow otherwise identically programmed devices to be placed
on a common bus. The address that the devices will respond to can be altered via an external resistor network. The address offset
circuit can offset both the I2C and SVID addresses by an offset range of +0 to +15. The address system is controlled by the
following registers:
Table 1. I2C / SVID ADDRESS REGISTERS
Register
(I2C Addr)
R/W
Purpose
Description
This register has bit flags as follows:
0
43 Bits<2:0>
RW
Address Offset
Configuration
0
0
0
0
apply_svid_
addr_offset
apply_i2c_
addr_offset
en_addr_offset
These bit flags control whether the External Address Offset function is enabled, and if
so how the offset is applied.
apply_svid_addr_offset = When set the address offset will be applied to the SVID
Address (Default enabled)
apply_i2c_addr_offset = When set, the address offset will be applied to the I2C
Address (Default enabled)
en_addr_offset = Controls if the address offset circuit is enabled (Default enabled)
This settings holds the base I2C address. The value should be between 8 to 119.
Default is 68 (44h).
50 Bits<6:0>
RW
I2C Address
51 Bits<3:0>
RW
SVID Address
0−7 = Invalid (I2C reserved)
8−119 = Valid (08h − 77h)
120−127 = Invalid (I2C reserved)
This setting holds the base SVID address. The value can be between 0 to 15 (0h −
Fh). Default is 0 (0h).
The address offset circuit is enabled by default on an unprogrammed device. It can be disabled by writing a zero into
en_addr_offset (Register 43, Bit 0) when programming the device. When enabled, the device will sense resistors attached to
the TEST2 and TEST3 pins during powerup and will add the resulting offset to the SVID and I2C base addresses as defined
by the bit flag settings above.
Addresses that exceed the maximum address will wrap around. For instance:
The address offset that is generated is determined by the resistors placed between the TEST2/TEST3 pins and GND. The
system uses 20 kW increments per step, and both the highest and lowest settings will give an address offset of zero (this is to
allow the TEST pins to be either shorted or open on a single−VR application or during device evaluation).
The following tables list the resultant offsets versus resistance for the TEST2 and TEST3 pins. The individual offsets are
added to give a total offset.
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NCP81111
Table 2. TEST2 ADDRESS OFFSET
Address Offset
Resistance (kW)
0
0−60
+8
80−140
0
>160
Table 3. TEST3 ADDRESS OFFSET
Address Offset
Resistance (kW)
0
0
+1
20
+2
40
+3
60
+4
80
+5
100
+6
120
+7
140
0
>160
The address offset value is latched during power−up as part of NVM initialization. It will be retained for the duration of
device operation. Enabling/Disabling the device via USER_POWER commands will not cause the address offset value to be
relatched. The only way to relatch the address offset value is to either power cycle the device or use a USER_POWER command
with the RESET_MEM flag set. After power−up the resulting address offset value can be read via I2C (Note: if I2C address
offset is enabled, this requires knowing the offset in advance, if this is not the case, then the hardwired addressing mode can
be used):
Table 4. ADDRESS OFFSET READBACK
Register
(I2C Addr)
R/W
Purpose
219 Bits<3:0>
R
Address Offset
Description
Readback of the latched address offset
DAC FEED FORWARD
A DAC Feed Forward (abbreviated DACFF) function has been added to the device. The purpose of this circuit is to
counteract the transient response of the output pole given by the droop resistance and the output load capacitance. In order to
do this the DACFF circuit adds a counteracting zero which cancels the pole.
This is illustrated below, where ωz = ω = 1/RC, with R = droop resistance and C = output load capacitance:
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NCP81111
DACFF(s) +
s
wz
DACFF
R
DAC
VSP
C
s
wz
G(s) + 1 )
H(s) +
1
VSP
1 ) ws
DAC
mag(dB)
mag(dB)
mag(dB)
0
0
0
w
w
w z + 1ńRC
ǒ
+ 1)
s
wz
Ǔǒ
1
1 ) ws
Ǔ+1
w
w z + 1ńRC
Figure 5.
There are some important things to note about the DACFF system:
• This effect is only applied in the VID UP direction, and allows the DAC to closely follow the ideal ramp slope
behavior. The effect is not applied in the VID DOWN direction to prevent potential voltage undershoot.
• For the effect to work properly the internal DACFF coefficients (given below) must be set properly with respect to the
actual droop resistance and output load capacitance. Improperly setting the coefficients may yield a lagging voltage
response (under−compensated) or overshoot artifacts (over−compensated). For this reason the feature is disabled by
default and must be explicitly enabled via end−user configuration.
• The above representation is a theoretical idealized model. In practice due to the digital nature and internal clock
frequency of the VID controller an additional high−frequency pole is introduced. The actual transfer function of the
DACFF circuit is given below. From a transient perspective this pole will have an effect on the leading and trailing
response of the DACFF function (the transition from VID up to VID stable, or vice−versa), and it’s effect will be
discussed more in the coefficient calculation section below.
DACFF(s) +
s
wz
(eq. 1)
1 ) ws
p
There are two DACFF coefficients, a 16−bit A−coefficient and an 8−bit B−coefficient. They can be calculated with the
following equations and procedure.
ǒ
2
A[15 : 0] +
T@w z
ǒ1 ) Ǔ
@ 128
B[7 : 0] +
2
T@w p
2
T@w p
Ǔ
*1
ǒ1 ) Ǔ
2
T@w p
where:
wz +
1
RC
w p + 2p @ f p where f p t 3.18 MHz
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@ 256
(eq. 2)
NCP81111
T = 100 ns = 1 • 10−7
R = droop resistance
C = output load capacitance
Calculation procedure:
1. Calculate ωz and choose initial ωp. Use those parameters to calculate A/B−coefficients.
2. Program the device with the coefficients, and enable the DACFF function. Observe the transient behavior.
3. Adjust A/B−coefficients directly as needed to modify the transient behavior as shown below.
4. Program the new coefficients and iterate as needed until satisfactory transients are obtained.
To the first−order the magnitude of the DACFF function will be controlled by the A−coefficient and the frequency response
will be controlled by the B−coefficient. This is illustrated below and can be used as a guideline when adjusting the coefficients
to obtain the desired response.
B−coeff controls speed
of trailing−edge
transient roll−off
VSP (DACFF enabled)
A−coeff controls
magnitude
VSP (DACFF disabled)
DAC
DAC
Figure 6.
IOUT Gain Programming
The NCP81111 has a high accuracy 10 bit A/D to monitor the total output current. The IOUT gain and the ICCMAX register
are user programmed and stored in the nonvolatile memory. The IOUT gain consists of two analog gain stages and one digital
gain stage for fine gain adjustment. When setting the IOUT gain the user must be care not to exceed the maximum input A/D
signal capability using the analog gain. Set the digital gain to unity and then adjust the analog gain to get the maximum signal
into the A/D without exceeding FFh at ICCMAX load in the IOUT register. Then fine tune the digital gain to achieve FFh in
the IOUT register under the ICCMAX load condition. IOUT Offset can be adjusted after the A/D conversion via register 84d.
IMON SUMMING AMP
Av=16
+ CSP1
− CSN1
CSP
IOUT 2nd Gain Stage
CSP
IOUT 3d Gain Stage
IOUT_P
CSP
Av
+ CSP2
− CSN2
CSN
IOUT_P
10BIT A/D
IN_P
OUT<9:0>
Av
CSN
IOUT_N
CSN
IOUT_N
IN_N
+ CSP3
− CSN3
Gain<>
81d<1:0>
Gain<>
81d<2:3>
Digital Adjust
SUM
IOUT<9:0>
Av
OUT<7:0>
700Hz
84d<7:0>
82d<7:0>
OFFSET<7:0>
GAIN<7:0>
Figure 7. IOUT Signal Chain
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IOUT<7:0>
NCP81111
IOUT CONFIGURATION TABLE
Function
Register
Value
Stage2 IOUT Gain
Stage3 IOUT Gain
81d<1:0>
81d<3:2>
0: 1
1: 2
2: 4
3: 8
Digital Gain
82d<7:0>
absolute 2.8 format (2 integer, 8 fractional), 0.00390625 per step
Example 100h = 256d ≥ Gain = 1
Iout Offset PS0
84d<7:0>
2’s complement format
Imon Offset PS1
115d<7:0>
2’s complement format
Imon Offset PS23
116d<7:0>
2’s complement format
Imon Settling time
110d<1:0>
99% Settle in => 00b=840 ms, 01b=1.68 ms, 10b=3.36 ms, 11b:6.72 ms
The equation for Iout tuning is as follows.
2.5 V + G 1 @ G 2 @ DCR @ 0.75 @ G Digital @ I CC_MAX
(eq. 3)
When tuning the Iout Analog gain G1 and G1 need to be set such that the Iout is between 80h and FFh but the voltage at the
A/D should not exceed 2.5V at Icc_max or the Iout signal will saturate the A/D converter. The offset can also be adjusted.
A/D Range
FFh
Analog Gain Target
Window
Digital Gain =1
Offset=0
80h
ICC_MAX
Figure 8.
The internal offset of the Iout signal chain is auto−calibrated and has very low offset. The current sense RC filter itself has
some nonlinear behavior when using thick film resistors. This creates a positive offset on Iout that can be observed to follow
the input supply voltage, Vout, and phase count. Using physically larger thick film 0805 resistors or two 0603 resistors in series
can reduce but not eliminate this effect. The system provides the IOUT offset adjust registers to help compensate for this effect.
For best performance using a metal film resistor is required in the cs filter network.
OCP Current Limit Programming
The NCP81111 uses a latching total current limit function. If the current limit is exceeded the controller will tri−state the
output stage. There is an adjustable filter speed for the OCP function. The filter can be disabled for the fastest response. The
OCP has three user settings to accommodate different current limits in separate power states.
The current limit is a total current limit and is digitally programmable in 2 mV steps to a maximum of 126 mV referred to
the total CS input sum.
Table 5. OCP CONFIGURATION TABLE
Function
Register
Value
OCP PS0
85d<5:0>
2 mV per step 0d = 0 mV to 63d = 126 mV
OCP PS1
86d<5:0>
2 mV per step 0d = 0 mV to 63d = 126 mV
OCP PS23
87d<5:0>
2 mV per step 0d = 0 mV to 63d = 126 mV
OCP Filter Bandwidth
85d<7:6>
00b:250 kHz , 01b:125 kHz, 10b:75 kHz, 11b:50 kHz
OCP Filter Enable
86d<6>
0:Use Filter, 1:No Filter
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NCP81111
Compensator Tuning
The NCP81111 uses a hybrid compensator. The high frequency performance is provided by a 100 MHz BW op−amp. The
digital integrator allows better control of the low frequency transient response. R1 and can be adjusted for power states PS0
and PS1,2,3 to optimize the loop gain based on the number of phases running.
Diffout
1.3V
VSN
GND
VSP
DAC
Droop_p
Droop_n
C2
C1
R3
Sum
50k
R1
50k
−
Digital
Integrator
1.3V
Comp
+
1.3V
Figure 9. Hybrid Compensator Diagram
Equation 4 − Compensator Transfer Function
ǒ
−
Comp(s)
Diffout(s)
Ai@gm
2@C cap@Divisor@V ramp@s
+
1
R1
1
)
R3)
1
1
C3@s
) 100k
Ǔ
(eq. 4)
) C2 @ s
ANALOG COMPENSATION CONFIGURATION TABLE
Function
Register
Value
R1 (PS0)
R1 (PS123)
95d<3:0>
95d<7:4>
0:33k, 1:50k, 2:75k, 3:100k, 4:150k, 5:200k, 6:250k, 7:300k, 8:350k, 9:400k, 10:450k
R3
96d<5:3>
0:10k, 1:20k, 2:30k, 3:40k, 4−7:50k
C1
96d<2:0>
0:0pF, 1:1.23pF, 2:3.48pF, 3:8.02pF, 4:17.12pF, 5:35.8pF, 6−7:24.3pF
C2
97d<2:0>
0:0fF, 1:185fF, 2:90fF,3:522fF,4−7:1.373pF
Digital Integrator
The digital integrator allows for independent tuning of the load step and load release response time and allows the user to
change the offset during power state changes to smooth the transition of the power state changes. The current DAC step size
controls the working range/ resolution of the digital integrator.
OSC
Diffout
Up
Divisor
gm
1.3V
Down
Divisor
Counter
+
offset
Power state
step size
Current
DAC
Step Size
Figure 10.
The digital integrator is a voltage to current function. The gm is approximately 180 ms, Vramp is ~50 mVm and Ccap in the
oscillator is 2 pF. The step size Ai for the current DAC is user adjustable. The digital integrator transfer function can be
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NCP81111
approximated with the following equation below. The current gain Ai is the integrator current step multiplied by the size
multiplier.
I(s)
Verror(s)
+
Ai @ gm
(eq. 5)
Divisor @ V ramp @ C cap @ s
The digital integrator also includes a stop function that can be adjusted to improve some aspects of the dynamic response
such as load release. If the output of the error amplifier falls below the integrator stop threshold the digital integrator counter
will be stopped to limit the integrator windup effect. In some cases the range of the integrator is sufficient to stop the windup
effect.
Figure 11. Example Compensator Gain Transfer Function with Mismatched Increment and Decrement Gains
DIGITAL INTEGRATOR CONFIGURATION TABLE
Function
Register
Value
Integrator Step Size Multiplier
Integrator Current Step
88d:<7>
89d:<4:3>
0: 100% step size 1: 75% step size
0: 5nA, 1:10nA, 2:15nA, 3:20nA
Integrator Decrement Divisor
PS0
PS1
PS23
90d<5:3>
91d<5:3>
92d<5:3>
Integrator Increment Divisor
PS0
PS1
PS23
90d<2:0>
91d<2:0>
92d<2:0>
0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128
Integrator Offset PS1 Step
93d<7:0>
2’s compliment format
Integrator Offset PS23 Step
94d<7:0>
2’s compliment format
Integrator Stop Threshold
PS0
PS1
PS23
88d<0:2>
88d<5:3>
89d<2:0>
0:0.90V, 1:0.95V, 2:1.00V, 3:1.05V, 4:1.10V, 5:1.15V, 6:1.20V, 7:1.25V
0:1, 1:2, 2:4, 3:8, 4:16, 5:32, 6:64, 7:128
Phase Shedding Threshold
When a power state command alters the phase count the controller will automatically reduce the current in the phases that
are to be shed to the threshold level set by the user and then shutdown the phase. This allows the controller to minimize the
voltage deviation during phase shedding operation.
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NCP81111
PHASE SHED THRESHOLD CONFIGURATION TABLE
Function
Phase Shed Threshold
Register
73d<5:0>
Value
LSB = 1 mV 2’s complement format
VBOOT Voltage Programming
The NCP81111 has a Vboot voltage register that can be configured to any valid VID value. If Vboot is configured to zero,
the controller will wait for an initial SVID voltage command to begin soft start.
DAC Offset Voltage Programming
The NCP81111 has a user fine trim for the output voltage that is adjustable for each power state.
ZDC Offset Programming
The NCP81111 is optimized to work with the ON’s HFVR high performance DRMOS drive stage. The ZCD detector is
located in the controller and the offset is adjustable for optimization by the user. This allows for timing variations in the design
ZCD OFFSET CONFIGURATION TABLE
Function
ZDC Offset Trim
Register
114d<5:0>
Value
0.2 mV per LSB Sign magnitude format.
VFF Under-Voltage Protection Programming
The controller is protected against under−voltage on the VFF input pin. The threshold is user programmable.
VFF Under−Voltage Configuration Table
Function
VFF UVLO Threshold
Register
Value
93d<6:0>
200 mV per LSB Example 14h = 4.0 V
Programming the Phase Count
The phase count must be configured buy the user and stored in NVM before enabling the output.
PHASE COUNT CONFIGURATION TABLE
Function
VR Phase Count
Register
64d<7:6>
Value
1: 1phase
2: 2phase
3: 3phase
Programming the Minimum ON, Minimum OFF, and SMOD Skew Timing
The controller is designed to guarantee the timing in certain cases to protect the gate driver from very rapid signal changes
that could potentially result is shoot though of the power stage. The user may select the setting for this based on the application
selection of the power stage. The recommended values for the HFVR DRMOS are noted in the table.
MINIMUM ON AND OFF TIME AND SMOD SKEW CONFIGURATION TABLE
Function
Register
Value
Minimum On Time Phases 1
65d<5:0>
Minimum On time 1.25 ns per LSB Example 1Ah = 32.5 ns
Minimum On Time Phases 2 and 3
64d<5:0>
Minimum On time 1.25 ns per LSB Example 1Ah = 32.5 ns
Minimum Off Time
66d<4:0>
LSB = 2.5 ns Example 0Dh = 32.5 ns
SMOD Skew Time
69d<4:0>
LSB = 2.5 ns Example 06h = 15 ns
Programming the Period of Operation
The NCP81111 is designed to maintain a constant frequency in as many operating cases as possible. The On time of the
controller varies based on many factors including VID setting, input voltage feed forward, load and power state. The frequency
in continuous mode operations is controlled by the user period setting. Under some conditions including low VID and high
Vin the frequency of operation may reduce due to reaching the minimum on time limits. The period setting is based on the
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NCP81111
individual phase frequency desired. Example 134h = 770 ns for 1.3 MHz For this case the registers would be configured as
follows. 72d = 34h with 73d<3:0> = 001b.
PERIOD CONFIGURATION TABLE
Function
Register
USER Period low byte
71d<7:0>
USER Period high byte
72d<3:0>
Value
2.5 ns per LSB
Programming the Boost Cap Functions
Due to the high voltage operation of the output under some conditions the gate driver floating boost cap voltage may
discharge to unacceptable levels, this is especially likely to occur when using 5 V gate drivers. The NCP81111 has several
functions to maintain the charge on the boost capacitors such that the gate driver is ready to use when needed. These timers
are user adjustable for custom optimization. The Tboost Period sets the time between recharge events for the phases that are
shed. The Tboost Time sets the amount of time the switch node is pulled low to charge the boost cap. The Boost Loop Count
is used at soft−start and sets the number of times the boost cap is charged before soft−start occurs.
BOOST CAP CONFIGURATION TABLE
Function
Register
Value
Tboost Period
67<7:4>
Default 1h = 81.92 ms
Tboost Time
68d<7:0>
2.5 ns per LSB Default 33h = 127.5 ns
Boost Loop Count
70d<3:0>
Default 8h for 8 loops.
Programming the Ramp Function
The ramp signal is user adjustable. This allows the user to maximize the performance of the controller. The ramp provides
a synchronization function for the controller and stabilizes the loop gain as well as the phase angles. The ramp has a reset voltage
for each phase and the slope automatically adjusts for the phase count during phase shedding. To achieve a wide verity of
accurate settings both the current and the ramp capacitor are adjustable. The adjustable ramp reset voltage allow for fine tuning
of the phase angles if the ripple feedback is not well balanced. The ramp descends to 1.3 V and remains there until reset again.
Use the equation I = Cdv/dt the ramp current setting is based on single phase ramp operation. Figure x shows how to select
the ramp cap and ramp slope. The design should target the trigger point near 1.31 V just above were the ramp goes flat at 1.3 V.
If the ramp intersects comp at high levels the load release response will be less aggressive and transitions into and out of DCM
mode operation will be less smooth. If the ramp is too steep the comp will trigger on a flat ramp and the system will be less
stable.
Figure 12.
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21
NCP81111
Figure 13. Multiphase Ramp Function
Modulator Gain Analysis
The NCP81111 modulator has an inherent non−linear transient response that varies depending on the ramp settings. The
small signal modulator gain can be found by taking the derivative of the non linear curve at the operating point. The result is
the equation for Am.
A m :+
Mc @ Ton
N @ ǒVreset * comp opp ) Mc @ TresetǓ
2
comp opp :+
Mc@Ton
D
* N @ Vreset * N @ Mc @ Treset
(eq. 6)
−N
0.8
D ( comp )
0.6
A m@( comp *comp opp) + D ( comp opp)
0.4
0.2
0
0
0.05
0.1
0.15
comp
Figure 14. Modulator Gain Function
RAMP CONFIGURATION TABLE
Function
Register
Value
Ramp Cap Setting
77d<3:0>
0: 0 pF
1: 1 pF
2: 2 pF
3: 3 pF
4: 4 pF
5: 5 pF
6: 6 pF
7: 7 pF
8: 8 pF
9: 9 pF
10: 10 pF
11: 11 pF
12-15: 12 pF
Ramp Current Setting
78d<7:0>
0 to 4.2291 uA 33.3 nA per LSB
Phase 1 Reset Voltage
74d<7:0>
4 mV per LSB Example 3Fh = 63d = 1.556 V
Phase 2 Reset Voltage
75d<7:0>
4 mV per LSB
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22
0.2
NCP81111
RAMP CONFIGURATION TABLE
Function
Phase 3 Reset Voltage
Register
76d<7:0>
Value
4 mV per LSB
Ramp Reset Time
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23
NCP81111
Control Loop Analysis
The NCP8111 control loop diagram can be modeled as shown below. The NCP81111 system is best described as voltage
mode control with AVP. AVP does create a current feedback loop but the compensation signal does not directly control the
current.
Figure 15. NCP81111 Control Loop
Figure 16. Current Loop Closed
Using the Test Ports for Debug
This controller has dedicated test ports for monitoring internal signals for debug purposes. Some of the more useful settings
include access to the internal droop, IOUT, and comp signals. The test pins have some impedance. For proper monitoring please
use 1 MQ or higher impedance probes.
Analog Application Notes Section
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points.
Differential Current Feedback Amplifiers
Each phase has a low offset differential amplifier to sense that phase current for current balance. Resistor RCSN must be
14 kW to work correctly with the internal thermal compensation. It is also recommended that the voltage sense element be no
less than 0.5 mW for accurate current monitor and balance. The internal CS pin resistance forms a divider with the external
CS filter resistor. Only 14 kW may be used for the external resistor. Fine tuning of the CS filter must be done by adjusting the
capacitor values. Two parallel capacitors should be placed on each phase to allow for fine tuning of the time constant of the
CS filter. The effective R in the RC time constant calculation will always be 10 kW. Select the C based on the L/(DCR * 10k)
= CCSN. The internal thermal compensation resistor attenuates the signal from the inductor DCR. The thermal gain is
approximately 0.75 at 25C for the inductor current sensing inputs. When calculating the droop gain the thermal gain effect must
be included. For best droop and IMON offset performance RCSN should be of the metal film type resistor. Using a larger thick
film 14 kW 0805 case size or two thick film 0603 case size resistors in series can offer improved current sense offset
performance over a standard 0603 case size.
Equation 7 − Initial Estimate Equation for Ccs Total
L
+ Ccs_total
DCR @ 10k
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24
(eq. 7)
NCP81111
DRMOS
DCR
Vout
Rcs =14 k
CSP
Rinternal
L
SWN
Ccs 1
Ccs 2
CSN
Rhf =10
Chf =100 pF
Figure 17. Phase Current Sense Network
TSENSE
One temperature sense input is provided which monitors both VR_HOT and Inductor temperature for thermal compensation.
A precision current is sourced out the output of the TSENSE pin to generate a voltage on the temperature sense network. There
are two internal networks that connect to the NTC depending on the measured temperature to extend the accuracy of the
thermal measurement across a greater temperature range. The hot and cold range limits are controlled by the internal user
registers. The voltage on the temperature sense input is sampled by the internal A/D converter and then digitally converted
to temperature and stored in SVID register. A 220k NTC similar to the Murata NCP18WM224J03RB should be used.
Internal IC
Board
4.83uA
58uA
Tsense
220k
NTC
Place by
phase 1
inductor
3x
A/D
Cold Hot
172.5k
11.5k
Figure 18. Thermal Sense Diagram
Equation 8 − Tsense Voltage Calculation
V ADC + 3 @ I bias @
ǒR NTC @ R internalǓ
ǒR NTC ) R internalǓ
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25
(eq. 8)
NCP81111
Bias
Current
58uA
4.38uA
A/D Result
temp_adc_cold
temp_adc_hot
Figure 19. Thermal Bias Current Selection Function
The onboard A/D converter has 10 bits and the maximum DAC voltage is 2.56 V with 2.5 mV per step. The user enters two
constants 1/M and C for both the thermal ranges this adjusts the temperature calculation reported for the temperature registers
and for VR_HOT activation. C has an offset effect and M adjusts a slope effect. This allows the user to adjust the thermal gain.
The conversion equation form the ADC result to the reported temperature is shown below.
Equation 9 − A/D Temperature Conversion Equation
Temperature +
C * Result ADC
M
+
C * 3 @ V Tsense
(eq. 9)
M
Figure 20. Example Results of the Thermal Sense Circuit
TSENSE CONFIGURATION TABLE
Function
Register
Notes
temp_adc_cold_low
100d<7:0>
Default value = DEh = 222d => 57C
temp_adc_cold_high
101d<1:0>
Default value = 0h
temp_adc_hot_low
105d<7:0>
Default value = A2h
temp_adc_hot_high
106d<1:0>
Default value = 2h 2A2h = 674 => 54C
temp_inv_m_cold
102d<7:0>
1/M used for the cold range temperature calculation. Default value = 18h = 24d
temp_inv_m_hot
107d<1:0>
1/M used for the hot range temperature calculation. Default value = 28h = 40d
Temp_c_cold_low
103d<7:0>
Default value = 3Ch
Temp_c_cold_high
104d<1:0>
Default value = 03h note 33Ch = 828d
Temp_c_hot_low
108d<7:0>
Default value = FDh
Temp_c_hot_high
109d<1:0>
Default value= 03h note 3Fdh = 1021d
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26
NCP81111
VR_HOT Operation
The VR_HOT thresholds are controlled by the user setting for the Temp Max register. Calculate the voltage thresholds on
the Tsense pin using the user settings for C and 1/M . See the equations below.
Tsense_VR_HOT_Assert_Threshold +
ǒC HOT * M HOT @ Temp_MaxǓ @ 2.56 V
(eq. 10)
10243
Tsense_VR_HOT_Deassert_Threshold +
ƪC HOT * M HOT @ (Temp_ThermAlert)ƫ @ 2.56 V
(eq. 11)
10243
TEMP_MAX CONFIGURATION TABLE
Function
Register
vr_temp_max
18d<7:0>
Notes
1degC per LSB
INPUT UNDER-VOLTAGE PROTECTION
Under Voltage Protection
Under voltage protection will shut off the output similar to OCP to protect against short circuits. The threshold is specified
in the parametric spec tables and is not adjustable. The controller is protected against under−voltage on the VCC and VFF pins.
Function
Register
disable_vff_uvlo
52d<2>
Vff_threshold
98d<6:0>
Notes
0:VFF UVLO Enabled 1: VFF UVLO Disabled
LSB = 200 mV Default = 0
Assigning Unused PWM and CS Pins
When using lower phase count arrangements always connect unused CSN and CSP pins together and to the nearest CSN
signal. Unused PWM pins should be left floating.
Phase Count
PWM1
PWM2
PWM3
CSP1
CSN1
CSP2
CSN2
CSP3
CSN3
3
Used
Used
Used
Used
Used
Used
Used
Used
Used
2
Used
Used
No Connect
Used
Used
Used
Used
Connect to
CSN2
Connect to
CSN2
1
Used
No Connect No Connect
Used
Used
Connect to
CSN1
Connect to
CSN1
Connect to Connect to
CSN1
CSN1
Layout Notes
The NCP81111 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues
related to layout for easy design use. To insure proper function there are some general rules to follow. Always place the inductor
current sense RC filters as close to the CSN and CSP pins on the controller as possible. Place the VCC decoupling caps as close
as possible to the controller VCC pin.
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NCP81111
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 485CE
ISSUE O
A
B
D
PIN ONE
REFERENCE
0.15 C
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÉÉ
ÇÇ
ÇÇ
EXPOSED Cu
0.15 C
TOP VIEW
DETAIL B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
(A3)
MOLD CMPD
DETAIL B
0.10 C
ALTERNATE
CONSTRUCTION
A
0.08 C
NOTE 4
A1
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.20
0.30
5.00 BSC
3.40
3.60
5.00 BSC
3.40
3.60
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
D2
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
5.30
K
8
3.70
17
32X
0.62
E2
32X
24
1
32
L
3.70
25
e
e/2
32X
b
0.10
M
C A-B B
0.05
M
C
BOTTOM VIEW
5.30
NOTE 3
0.50
PITCH
32X
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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