MB96340
SPECIFICATION
FME-MB96340 rev 5
16-bit Proprietary Microcontroller
CMOS
Y
F2MC-16FX MB96340 Series
AR
■ DESCRIPTION
MB96340 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
PR
EL
IM
IN
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimised by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
FME/EMDC- 2007-9-12MB96340_DS_cover.fm
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
2
FME/EMDC- 2007-9-12
MB96340_DS_cover.fm
Specification
MB96340
■ FEATURES
Feature
Description
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
• 8-byte instruction execution queue
Y
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
CPU
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
AR
• On-chip PLL clock multiplier (x1..25, x1 when PLL stop)
• 3-16 MHz external quartz clock, up to 4MHz external clock
• 32-100 kHz subsystem quartz clock
• 100kHz/2MHz internal RC clock for quick and save startup, oscillator stop detection,
watchdog
System clock
IN
• Clock source selectable from main- and subclock oscillator (partnumber suffix “W”)
on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
Low voltage reset
Code Security
EL
IM
On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
tor
and low power consumption figures
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
Memory Patch Function
DMA
• Replaces ROM content
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
• 8 programmable priority levels
Timers
PR
• Non-Maskable Interrupt (NMI)
• Two independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
3
MB96340 Series
Specification
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
Y
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
AR
• Full duplex USARTs (SCI/LIN)
• Wide range of baud rate settings using a dedicated reload timer
USART
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Up to 400 kbit/s
I2C
• SAR-type
A/D converter
• 10bit resolution
IN
• Master and Slave functionality, 8-bit and 10-bit addressing
A/D Converter Reference Voltage switch
• 2 independant positive A/D converter reference voltages available
• 16-bit wide
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
PR
EL
Reload Timers
IM
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
• Event count function
Free Running Timers
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 , 1/27 ,1/28 of
peripheral clock frequency
• 16-bit wide
Input Capture Units
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
4
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
Specification
MB96340
Feature
Description
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse
Generator
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer overflow as clock input
• Can be triggered by software or reload timer
Y
• Can be clocked either from sub oscillator (devices with partnumber suffix “W”),main
oscillator or from the RC oscillator
Real Time Clock
AR
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
• Read/write accessible second/minute/hour registers
• Can signal interrupts every halfsecond/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32
kHz clock input (devices with partnumber suffix “W”) clock input
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
IN
External Interrupts
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
• Once enabled, can not be disabled other than by reset.
EL
IM
Non Maskable Interrupt
• Level high or level low sensitive
• Pin shared with external interrupt 0.
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
External bus interface
• Multiplexed address/data lines
• Wait state request
PR
• External bus master possible
• Timing programmable
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Alarm comparators
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
5
MB96340 Series
Specification
Feature
Description
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
I/O Ports
• Bit-wise programmable input enable
• Bit-wise programmable input levels (Automotive / CMOS-Schmitt trigger / TTL)
• Bit-wise programmable pull-up resistor
Package
• 100-pin plastic QFP and LQFP
Y
• Bit-wise programmable output driving strength for EMI optimization
• Supports automatic programming, Embedded AlgorithmTM*1
AR
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles : 10,000 times
Flash Memory
• Data retention time : 20 years
• Sector protection
IN
• Erase can be performed on each sector individually
• Flash Security feature to protect the content of the Flash
• Low voltage detection during Flash erase
: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
PR
EL
IM
*1
6
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
Specification
MB96340
■ PRODUCT LINEUP
Features
MB96V300
MB9634x
Product type
Evaluation sample
Flash product: MB96F34x
Mask ROM product: MB9634x
Product options
LVD persistently on / Single clock devices
RS
LVD can be disabled / Single clock devices
YW
LVD persistently on / Dual clock devices
RW
LVD can be disabled / Dual clock devices
AR
Y
YS
TS
Satellite Flash / LVD persistently on / Single clock devices
HS
Satellite Flash / LVD can be disabled / Single clock devices
TW
NA
Satellite Flash / LVD can be disabled / Dual clock devices
IN
HW
Satellite Flash / LVD persistently on / Dual clock devices
No CAN / No Satellite Flash / LVD persistently on / Single clock
devices
AS
No CAN / /Satellite Flash / LVD can be disabled / Single clock
devices
CS
EL
IM
No CAN / No Satellite Flash / LVD persistently on / Dual clock
devices
AW
CW
No CAN / Satellite Flash / LVD can be disabled / Dual clock devices
Flash/
ROM
RAM
128kB
6kB
288kB
16kB
416kB
16kB
544kB
24kB
MB96344R, MB96344Y
MB96F346R, MB96346R, MB96F346Y, MB96346Y, MB96F346A
ROM/Flash memory emulation
by external RAM,
MB96F347R, MB96347R, MB96F347Y, MB96347Y, MB96F347A
MB96F348R, MB96F348Y, MB96F348A
24kB
Package
DMA
PR
92kB internal RAM
Main:
544kB,
Sat.:
32kB
BGA416
MB96F348C,
MB96F348H, MB96F348T
FPT-100P-M20
FPT-100P-M22
16 channels
6 channels
USART
10 channels
7 channels
MB96F348 TSA/HSA/TWA/HWA: 4 channels
I2C
2 channels
2 channel
A/D Converter
40 channels
24 channels
FME/EMDC- 2007-9-12
MB96340_DS_lineup.fm
7
MB96340 Series
MB96V300
MB9634x
A/D Converter
Reference
Voltage switch
yes
yes
16-bit Reload
Timer
6 channels
4 channels
16-bit FreeRunning Timer
4 channels
2 channels
16-bit Output
Compare
12 channels
16-bit Input
Capture
12 channels
16-bit
Programmable
Pulse Generator
20 channels
CAN Interface
(not available on
MB963xxA,
MB963xxC)
5 channels
Low voltage reset
On-chip RCoscillator
AR
IN
2 channels
IM
136
80 for part number with suffix "W", 82 for part number with suffix "S"
PR
EL
Clock output
function
16 channels
1
MB96F348TSA/HSA/TWA/HWA: not available
I/O Ports
Chip select
8 channels
1 channel
Real Time Clock
External bus
interface
8 channels
16 channels
Non-Maskable
Interrupt
Alarm comparator
Y
Features
External
Interrupts
8
Specification
FME/EMDC- 2007-9-12
2 channels
Multiplexed
Yes
6 signal
2 channels
Reset is generated when supply voltage is below minimum.
Yes
MB96340_DS_lineup.fm
Specification
MB96340
■ BLOCK DIAGRAM
AD00 ... AD15
A16 ... A23
ALE
RDX
WRLX, WRHX
HRQ
HAKX
RDY
ECLK
LBX, UBX
CS0 ... CS5
NMI
Interrupt
Controller
16FX
CPU
Main Flash
Memory
Satellite Flash
Memory 1)
EL
IM
10-bit ADC
24 ch.
FRCK0
IN0 ... IN3
OUT0 ... OUT3
I/O Timer 0
ICU 0/1/2/3
OCU 0/1/2/3
FRCK1
IN4 ... IN7
OUT4 ... OUT7
I/O Timer 1
ICU 4/5/6/7
OCU 4/5/6/7
INT0 ... INT15
USART
7 ch.
Alarm
Comparator
2 ch.
16-bit PPG
16 ch.
PR
TOT0 ... TOT3
16-bit Reload
Timer
4 ch.
TIN0 ... TIN3
External
Interrupt
Real Time
Clock 2)
Clock Output
Function
2 ch.
1)
2)
RAM
IN
I2C
2 ch.
SCL0 ... SCL1
AVCC
AVSS
AVRH
AVRL
AN0 ... AN23
ADTG
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0 ... SDA1
Peripheral
Bus Bridge
Peripheral Bus 1 (CLKP1)
Watchdog
AR
16FX Core Bus (CLKB)
DMA
Controller
Memory Patch
Unit
Clock &
Mode Controller
Y
External Bus
Interface
X0, X1
X0A, X1A
RSTX
MD0...MD2
CAN
Interface
2 ch.
Boot ROM
Voltage
Regulator
VCC
VSS
C
TX0, TX1
RX0, RX1
SIN0...SIN3, SIN72)...SIN92)
SOT0...SOT3, SOT72)...SOT92)
SCK0...SCK3, SCK72)...SCK92)
ALARM0
ALARM1
TTG0 ... TTG15
PPG0 ... PPG15
WOT
CKOT0, CKOT1
CKOTX0, CKOTX1
Available only on devices with suffix , “C”, “H” or suffix “T”
Not available on MB96F348 HSA/HWA/TSA/TWA
FME/EMDC- 2007-9-11
MB96340_DS_block_diagram.fm
9
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
10
FME/EMDC- 2007-9-11
MB96340_DS_block_diagram.fm
Specification
MB96340
■ PIN ASSIGNMENTS
MD2
MD1
MD0
RSTX
Y
P07_6/AN22/INT6/SOT9_R2)
P07_7/AN23/INT7/SIN9_R2)
P08_0/TIN0/CKOTX0/ADTG/INT12_R
P08_1/TOT0/CKOT0/INT13_R
P08_2/SIN0/TIN2/INT14_R
P08_3/SOT0/TOT2
AR
P08_4/SCK0/INT15_R
P08_5/SIN1/INT1_R
P08_6/SOT1
P08_7/SCK1
Vcc
Vss
P09_0/PPG8/UBX
P09_1/PPG9/LBX
P09_2/PPG10/CS5
P09_3/PPG11/CS4
P09_4/OUT0/CS3
P09_5/OUT1/CS2
P09_6/OUT2/CS1
P09_7/OUT3/CS0
P10_0/RX0/INT8_R
P10_1/TX0
P00_0/AD00/INT8/SCK7_R2)
P00_1/AD01/INT9/SOT7_R2)
P00_2/AD02/INT10/SIN7_R2)
P00_3/AD03/INT11/SCK8_R2)
Pin assignment (FPT-100P-M22)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
P00_5/AD05/INT13/SIN8_R2)
82
P00_6/AD06/INT14
83
P00_7/AD07/INT15
84
P01_0/AD08/CKOT1/TIN1
85
P01_1/AD09/CKOTX1/TOT1
86
P01_2/AD10/INT11_R/SIN3
87
P01_3/AD11/SOT3
88
P01_4/AD12/SCK3
89
Vcc
90
Vss
91
X1
92
X0
93
P01_5/AD13/INT7_R/SIN2_R
94
P01_6/AD14/SOT2_R
95
P01_7/AD15/SCK2_R
96
P02_0/A16/PPG12
97
P02_1/A17/PPG13
98
P02_2/A18/PPG14
99
P02_3/A19/PPG15
100
IN
QFP - 100
P07_3/AN19/INT3
47
P07_2/AN18/INT2
46
P07_1/AN17/INT1
45
P07_0/AN16/INT0/NMI
44
Vss
43
P06_7/AN7/PPG7
42
P06_6/AN6/PPG6
41
P06_5/AN5/PPG5
40
P06_4/AN4/PPG4
39
P06_3/AN3/PPG3
38
P06_2/AN2/PPG2
37
P06_1/AN1/PPG1
36
P06_0/AN0/PPG0
35
AVss
34
AVRL
33
AVRH
AVcc
P05_7/AN15/INT5_R
P05_6/AN14/INT4_R
P05_5/AN13/INT0_R/NMI_R
P05_4/AN12/TOT3/INT2_R
P05_3/AN11/TIN3/WOT2)
P05_2/AN10/SCK2
P05_1/AN9/ALARM1/SOT2
P05_0/AN8/ALARM0/SIN2/INT3_R1
P04_7/SCL1
P03_3/WRHX
P04_6/SDA1
P03_2/WRLX/WRX/INT10_R
P04_5/SCL0/FRCK1
P03_1/RDX/IN5/TTG5/TTG13
P04_4/SDA0/FRCK0
P03_0/ALE/IN4/TTG4/TTG12
P04_3/IN7/TX1/TTG7/TTG15
P02_7/A23/IN3/TTG3/TTG11
P07_4/AN20/INT4
48
31
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
P02_6/A22/IN2/TTG2/TTG10
P07_5/AN21/INT5/SCK9_R2)
49
32
C
P02_4/A20/TTG8/TTG0/IN0
50
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Vss
8
Vcc
7
X1A1)/P04_11)
6
X0A1)/P04_01)
5
P03_7/ECLK/OUT7
4
P03_6/RDY/OUT6
3
P03_5/HAKX/OUT5
2
P03_4/HRQ/OUT4
1
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
EL
IM
Package code (mold)
FPT-100P-M22
PR
1)
P00_4/AD04/INT12/SOT8_R2)
Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R not available on MB96F348TSB/HSB/TWB/HWB
(FPT-100P-M22)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
FME/EMDC- 2007-9-12
MB96340_DS_pin_assignement.fm
11
MB96340 Series
Specification
Vss
89
X1
90
X0
91
P01_5/AD13/INT7_R/SIN2_R
92
P01_6/AD14/SOT2_R
93
P01_7/AD15/SCK2_R
94
P02_0/A16/PPG12
95
P02_1/A17/PPG13
96
P02_2/A18/PPG14
97
P02_3/A19/PPG15
98
P02_4/A20/TTG8/TTG0/IN0
99
1)
MD0
RSTX
P07_6/AN22/INT6/AIN2/SOT9_R2)
P07_7/AN23/INT7/AIN3/SIN9_R2)
P08_0/TIN0/CKOTX0/ADTG/INT12_R
P08_1/TOT0/CKOT0/INT13_R
P08_2/SIN0/TIN2/INT14_R
P08_3/SOT0/TOT2
P08_4/SCK0/INT15_R
P08_5/SIN1/INT1_R
P08_6/SOT1
P08_7/SCK1
Vcc
Vss
P09_0/PPG8/UBX
P09_1/PPG9/LBX
P09_2/PPG10/CS5
P09_3/PPG11/CS4
P09_5/OUT1/CS2
P09_6/OUT2/CS1
P09_7/OUT3/CS0
P10_0/RX0/INT8_R
P09_4/OUT0/CS3
P06_5/AN5/PPG5
38
P06_4/AN4/PPG4
Package code (mold)
FPT-100P-M20
37
P06_3/AN3/PPG3
36
P06_2/AN2/PPG2
35
P06_1/AN1/PPG1
34
P06_0/AN0/PPG0
33
AVss
32
AVRL
31
AVRH
30
AVcc
29
P05_7/AN15/INT5_R
28
P05_6/AN14/INT4_R
27
P05_5/AN13/INT0_R/NMI_R
1
2
3
4
5
6
7 8
P02_6/A22/IN2/TTG2/TTG10
P02_7/A23/IN3/TTG3/TTG11
P03_0/ALE/IN4/TTG4/TTG12
P03_1/RDX/IN5/TTG5/TTG13
P03_2/WRLX/WRX/INT10_R
P03_3/WRHX
P03_4/HRQ/OUT4
100
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
PR
EL
P02_5/A21/TTG9/TTG1/IN1/ADTG_R
Y
88
P05_4/AN12/TOT3/INT2_R
P05_3/AN11/TIN3/WOT2)
Vcc
P06_6/AN6/PPG6
39
P05_2/AN10/SCK2
87
P05_1/AN9/ALARM1/SOT2
P01_4/AD12/SCK3
P06_7/AN7/PPG7
40
LQFP - 100
P05_0/AN8/ALARM0/SIN2/INT3_R1
86
P04_7/SCL1
P01_3/AD11/SOT3
Vss
41
P04_6/SDA1
85
AR
P01_2/AD10/INT11_R/SIN3
P07_0/AN16/INT0/NMI
42
P04_5/SCL0/FRCK1
84
P04_4/SDA0/FRCK0
P01_1/AD09/CKOTX1/TOT1
P07_1/AN17/INT1
43
P04_3/IN7/TX1/TTG7/TTG15
83
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
P01_0/AD08/CKOT1/TIN1
P07_2/AN18/INT2
44
C
82
P07_3/AN19/INT3
45
IN
P00_7/AD07/INT15
46
Vss
81
Vcc
80
P00_6/AD06/INT14
P07_5/AN21/INT5/SCK9_R2)
P07_4/AN20/INT4
X1A /P04_1
P00_5/AD05/INT13/SIN8_R2)
MD2
47
1)
79
1)
P00_4/AD04/INT12/SOT8_R2)
MD1
48
X0A1)/P04_01)
78
IM
P00_3/AD03/INT11/SCK8_R2)
49
P03_7/ECLK/OUT7
77
P00_2/AD02/INT10/SIN7_R
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
P03_6/RDY/OUT6
76
2)
P03_5/HAKX/OUT5
P00_1AD01/INT9/SOT7_R2)
P10_1/TX0
P00_0/AD00/INT8/SCK7_R2)
Pin assignment (FPT-100P-M20)
Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
2) SIN7_R, SOT7_R, SCK7_R, SIN8_R, SOT8_R, SCK8_R, SIN9_R, SOT9_R, SCK9_R not available on MB96F348TSB/HSB/TWB/HWB
(FPT-100P-M20)
Remark:
MB96(F)34x products are pin-compatible to F2MC-16LX family MB90340 series.
12
FME/EMDC- 2007-9-12
MB96340_DS_pin_assignement.fm
Specification
MB96340
■ PIN CIRCUIT TYPE
Circuit
type
Pin no.
Circuit
type
1-10
H
1-12
H
11,12
B1)
13, 14
B1)
11,12
H2)
13, 14
H2)
13,14
Supply
15,16
Supply
15
C-Pin
17
C-Pin
16,17
H
18,19
H
18-21
N
20-23
N
22-29
I
24-31
I
30
F
32
F
31
G
33
32-33
F
34-35
34 to 41
I
36 to 43
42
Supply
43 to 48
I
49 to 51
C
52
E
53 to 54
I
55 to 62
H
63, 64
Supply
65 to 87
H
88,89
2)
IN
G
F
EL
IM
I
44
Supply
45 to 50
I
51 to 53
C
54
E
55 to 56
I
57 to 64
H
65, 66
Supply
67 to 89
H
Supply
90, 91
Supply
90, 91
A
92, 93
A
92-100
H
94 to 100
H
PR
1)
AR
Pin no.
Y
FPT-100P-M22
FPT-100P-M20
Devices with suffix ”W”
Devices without suffix ”W”
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
13
MB96340 Series
Specification
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Oscillation circuit
High-speed oscillation feedback resistor =
approx. 1 MΩ
Xout
B
X1A
Xout
Oscillation circuit
Low-speed oscillation feedback resistor =
approx. 10 MΩ
IN
X0A
AR
Standby control signal
Y
X0
Standby control signal
IM
C
R
Hysteresis
inputs
PR
EL
E
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
CMOS Hysteresis input pin
Pull-up resistor value: approx. 50 kΩ
Pull-up
Resistor
R
F
14
FME/EMDC- 2007-9-12
Hysteresis
inputs
Power supply input protection circuit
MB96340_DS_pin_circuit_type.fm
Specification
Type
MB96340
Circuit
Remarks
G
A/D converter ref+ (AVRH) power supply input
pin, With the protection circuit
ANE
Flash devices do not have a protection circuit
against VCC for pin AVRH
AVR
ANE
Nout
R
Hysteresis input
IN
Standby control
for input shutdown
AR
pull-up control
Pout
Hysteresis input
Standby control
for input shutdown
Automotive inputs
EL
IM
Standby control
for input shutdown
TTL input
PR
Standby control
for input shutdown
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
Y
H
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
15
MB96340 Series
Circuit
Remarks
I
CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function)
TTL input with input shutdown function
Programmable pull-up registor: 50kΩ approx.
Analogue input
pull-up control
Pout
Nout
Y
Type
Specification
R
AR
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive inputs
Standby control
for input shutdown
TTL input
IN
Standby control
for input shutdown
Analog input
IM
N
pull-up control
PR
EL
Pout
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up registor:50kΩ approx.
Nout
R
Standby control
for input shutdown
16
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive inputs
Standby control
for input shutdown
TTL input
FME/EMDC- 2007-9-12
MB96340_DS_pin_circuit_type.fm
Specification
MB96340
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 / 2)
Feature
Description
ADn
External bus
External bus interface (multiplexed mode) address/data input/
output
ADTG
ADC
A/D converter trigger input
ADTG_R
ADC
Relocated A/D converter trigger input
ALARMn
Alarm comparator
Alarm Comparator n input
ALE
External bus
External bus Address Latch Enable output
ANn
ADC
A/D converter channel n input
AVCC
Supply
AVRH
ADC
A/D converter high reference voltage input
AVRL
ADC
A/D converter low reference voltage input
AVSS
Supply
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin.
CKOTn
Clock output function
Clock Output function n output
CKOTXn
Clock output function
Clock Output Function n inverted output
ECLK
External bus
External bus clock output
CSn
External bus
External bus chip select n output
FRCKn
Free Running Timer
Free Running Timer n input
HAKX
External bus
External bus Hold Acknowlegde
HRQ
External bus
External bus Hold Request
INn
ICU
Input Capture Unit n input
INTn
External Interrupt
External Interrupt n input
INTn_R
External Interrupt
Relocated External Interrupt n input
LBX
External bus
External Bus Interface Lower Byte select strobe output
Core
Input pins for specifying the operating mode.
NMI
External Interrupt
Non-Maskable Interrupt input
NMI_R
External Interrupt
Relocated Non-Maskable Interrupt input
OUTn
OCU
Output Compare Unit n waveform output
PPGn
PPG
Programmable Pulse Generator n output
PPGn_R
PPG
Relocated Programmable Pulse Generator n output
FME/EMDC- 2007-9-12
AR
IN
Analogue circuits power supply
Analogue circuits power supply
EL
IM
PR
MDn
Y
Pin name
MB96300_DS_pin_function_desc.fm
17
MB96340 Series
Specification
Pin Function description (2 / 2)
Feature
Description
RDX
External bus
External bus interface read strobe output
RDY
External bus
External bus interface external wait state request input
RSTX
Core
Reset input
RXn
CAN
CAN interface n RX input
SCKn
USART
USART n serial clock input/output
SCKn_R
USART
Relocated USART n serial clock input/output
SCLn
I2C
I2C interface n clock I/O input/output
SDAn
I2C
I2C interface n serial data I/O input/output
SINn
USART
USART n serial data input
SINn_R
USART
SOTn
USART
SOTn_R
USART
TINn
Reload Timer
TOTn
Reload Timer
TTGn
PPG
TTGn_R
PPG
TXn
CAN
UBX
External bus
VSS
WOT
WRHX
WRLX
X0
X0A
X1
X1A
18
AR
Relocated USART n serial data input
IN
USART n serial data output
Relocated USART n serial data output
Reload Timer n event input
Reload Timer n output
IM
Programmable Pulse Generator n trigger input
Relocated Programmable Pulse Generator n trigger input
CAN interface n TX output
External Bus Interface Upper Byte select strobe output
PR
EL
VCC
Y
Pin name
Supply
Power supply
Supply
Power supply
RTC
Real Timer clock output
External bus
External bus High byte Write strobe output
External bus
External bus Low byte Write strobe output
Clock
Oscillator input
Clock
"Subclock Oscillator input (only for devices with suffix ""W"")"
Clock
Oscillator output
Clock
"Subclock Oscillator output (only for devices with suffix
""W"")"
FME/EMDC- 2007-9-12
MB96300_DS_pin_function_desc.fm
Specification
MB96340
■ MEMORY MAP
MB96V300
MB96(F)34x
ff.ffff
User
ROM
de.0000
df.007f
df.0000
Small Sectors
Main RCB ***
de.002f
de.0000
Sat RCB ***
external
Bus
10.0000
0f.e000
DSU
area
0f.0000
external
RAM
EL
IM
02.0000
00.8000
Boot-ROM
IN
0e.0000
AR
external
Bus
Satellite Flash
(available on devices with suffix”T”, “H”, “C”)
Y
Emulation
ROM
internal
RAM
internal
RAM
ROM/RAM
-Mirror
ROM/RAM
-Mirror
01.0000
Start address of
User ROM area and
number of small sector
depends on the device
Main Flash
RAM availability and mapping
depending on device
Not used for current available devices
internal
RAM
internal
RAM
RAMSTART**
00.1200
ext. bus
ext. bus
Peripheral
Peripheral
GPR*
DMA
ext. bus
Peripheral
GPR*
DMA
ext. bus
Peripheral
PR
00.0c00
Reserved
External Bus end address**
00.0380
00.0180
00.0100
00.00f0
00.0000
* Unused GPR banks can be used as RAM area.
** Please refer to the table “RAMSTART for different RAM sizes” on the next page
*** ROM Configuration Block (RCB) must not be used for other purposes than described in the manual
The external Bus area DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device configuration.
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
19
MB96340 Series
Specification
■ RAMSTART AND EXTERNAL BUS END ADDRESS FOR DIFFERENT RAM SIZES
RAM size
RAMSTART
End address of external bus area
MB96344
6 kB
6A40
69FF
MB96(F)346, MB96(F)347
16 kB
4240
41FF
MB96F348
24 kB
2240
21FF
PR
EL
IM
IN
AR
Y
Devices
20
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ FLASH SECTOR CONFIGURATION
MB96F346Y
MB96F346R
MB96F346A
FF:0000h
FE:FFFFh
3F:0000h
3E:FFFFh
FE:0000h
FD:FFFFh
3E:0000h
3D:FFFFh
FD:0000h
FC:FFFFh
3D:0000h
3C:FFFFh
FC:0000h
FB:FFFFh
3C:0000h
3B:FFFFh
FB:0000h
FA:FFFFh
3B:0000h
3A:FFFFh
FA:0000h
F9:FFFFh
3A:0000h
39:FFFFh
F9:0000h
F8:FFFFh
39:0000h
38:FFFFh
F8:0000h
F7:FFFFh
38:0000h
37:FFFFh
F7:0000h
37:0000h
.
.
.
.
.
.
.
.
E0:FFFFh
20:FFFFh
E0:0000h
DF:FFFFh
DF:E000h
DF:DFFFh
DF:C000h
DF:BFFFh
DF:A000h
DF:9FFFh
DF:8000h
DF:7FFFh
DF:6000h
DF:5FFFh
DF:4000h
DF:3FFFh
DF:2000h
DF:1FFFh
DF:0000h
DE:FFFFh
DE:E000h
DE:DFFFh
DE:C000h
DE:BFFFh
DE:A000h
DE:9FFFh
DE:8000h
DE:7FFFh
DE:6000h
DE:5FFFh
DE:4000h
DE:3FFFh
DE:2000h
DE:1FFFh
DE:0000h
20:0000h
1F:FFFFh
1F:E000h
1F:DFFFh
1F:C000h
1F:BFFFh
1F:A000h
1F:9FFFh
1F:8000h
1F:7FFFh
1F:6000h
1F:5FFFh
1F:4000h
1F:3FFFh
1F:2000h
1F:1FFFh
1F:0000h
1E:FFFFh
1E:E000h
1E:DFFFh
1E:C000h
1E:BFFFh
1E:A000h
1E:9FFFh
1E:8000h
1E:7FFFh
1E:6000h
1E:5FFFh
1E:4000h
1E:3FFFh
1E:2000h
1E:1FFFh
1E:0000h
MB96F348C
MB96F348H
MB96F348T
Main Flash size
288kByte
Main Flash size
416kByte
Main Flash size
544kByte
SA39 - 64K
SA39 - 64K
SA39 - 64K
SA39 - 64K
SA38 - 64K
SA38 - 64K
SA38 - 64K
SA38 - 64K
SA37 - 64K
SA37 - 64K
SA37 - 64K
SA37 - 64K
SA36 - 64K
SA36 - 64K
SA36 - 64K
SA36 - 64K
SA35 - 64K
SA35 - 64K
SA35 - 64K
SA34 - 64K
SA34 - 64K
SA34 - 64K
SA33 - 64K
SA33 - 64K
SA32 - 64K
SA32 - 64K
.
.
.
.
.
.
.
.
.
.
.
.
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
EL
IM
.
.
.
.
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB0 - 8K
PR
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K
Y
3F:FFFFh
AR
FF:FFFFh
MB96F348Y
MB96F348R
MB96F348A
Main Flash size
544kByte
Satellite Flash size
32kByte
IN
Alternative mode Flash memory
CPU address mode address
MB96F347Y
MB96F347R
MB96F347A
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
21
MB96340 Series
Specification
■ PARALLEL PROGRAMMING FLASH MEMORY CONTROL SIGNALS
Flash memory control signals (MD[2:0] = 111)
MB96F34X
Pin number
Flash memory mode
LQFP
QFP
3
5
P03_0
AQ16
4
6
P03_1
CE
CE
5
7
P03_2
OE
OE
6
8
P03_3
7
9
P03_4
8
10
P03_5
9
11
P03_6
10
12
P03_7
16 to 19
18 to 21
20 to 21
AR
Y
A15
WE
WE
AQ17
A16
AQ18
BYTE
RY/BY
RY/BY
P04_2 to P04_5
AQ8 to AQ11
A7 to A10
22 to 23
P04_6 to P04_7
AQ12 to AQ13
A11 to A12
22 to 23
24 to 25
P05_0 to P05_1
AQ14 to AQ15
A13 to A14
27 to 29
29 to 31
49
51
50
52
75 to 82
83 to 86
87, 92 to 94
99 to 2, 95 to 98
IM
P05_5 to P05_7
AQ19 to AQ21
MD2
MD2
OE
MD1
MD1
RESET
PR
EL
52
IN
BYTE
51
22
MBM29LV200
Normal function
53
MD0
MDO
A9
54
RST
RESET
RESET
77 to 84
P00_0 to P00_7
DQ0 to DQ7
DQ0 to DQ7
85 to 88
P01_0 to P01_3
DQ8 to DQ11
DQ8 to DQ11
89, 94 to 96
P01_4 to P01_7
DQ12 to DQ15
DQ12 to DQ15
1 to 4, 97 to 100
P02_0 to P02_7
AQ0 to AQ7
A-1, A0 to A6
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F34x
Pin number
USART Number
Normal function
LQFP-100
QFP-100
57
59
58
60
59
61
SCK0
60
62
SIN1
61
63
62
64
22
24
23
25
24
26
92
94
93
95
94
96
85
87
86
88
87
89
77
79
76
78
75
77
80
82
78
54
53
USART1
48
81
SOT0
AR
USART0
SOT1
SCK1
SIN2
SOT2
IN
USART2
SCK2
SIN2_R
EL
IM
USART2
PR
79
SIN0
USART3
USART7
USART8
SOT2_R
SCK2_R
SIN3
SOT3
SCK3
SIN7_R
SOT7_R
SCK7_R
SIN8_R
SOT8_R
80
SCK8_R
56
SIN9_R
55
50
Y
Pin number
USART9
SOT9_R
SCK9_R
Note: For handshaking pin, please use for this device the default pin P00_1. If any other pin is required, please
contact the Flash programmer device vendor.
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
23
MB96340 Series
Specification
■ I/O MAP
I/O map (1 / 34)
24
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
000000H
P00 - I/O Port Port Data Register
PDR00
RW
000001H
P01 - I/O Port Port Data Register
PDR01
RW
000002H
P02 - I/O Port Port Data Register
PDR02
RW
000003H
P03 - I/O Port Port Data Register
PDR03
000004H
P04 - I/O Port Port Data Register
PDR04
000005H
P05 - I/O Port Port Data Register
000006H
P06 - I/O Port Port Data Register
000007H
P07 - I/O Port Port Data Register
000008H
P08 - I/O Port Port Data Register
000009H
P09 - I/O Port Port Data Register
00000AH
P10 - I/O Port Port Data Register
00000BH
000017H
Reserved
000018H
ADC - Control Status register 0 Low
ADCSL
000019H
ADC - Control Status register 0 High
ADCSH
00001AH
ADC - Data Register 0 Low
ADCRL
00001BH
ADC - Data Register 0 High
00001CH
ADC - Setting Register Low 0
00001DH
ADC - Setting Register High 0
00001EH
ADC - Extended Configuration
Register
000020H
FRT0 - Data register of free-running
timer
000021H
FRT0 - Data register of free-running
timer
000022H
FRT0 - Control status register of freerunning timer
TCCSL0
000023H
FRT0 - Control status register of freerunning timer
TCCSH0
000024H
FRT1 - Data register of free-running
timer
AR
RW
RW
PDR05
RW
PDR06
RW
PDR07
RW
PDR08
RW
PDR09
RW
PDR10
RW
IN
IM
PR
EL
FME/EMDC- 2007-9-12
Y
Address
ADCS
RW
RW
ADCR
ADCRH
R
R
ADSR
ADECR
RW
RW
TCDT0
RW
RW
TCCS0
RW
RW
TCDT1
MB96340_DS_memory.fm
RW
Specification
MB96340
I/O map (2 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Address
Register
000025H
FRT1 - Data register of free-running
timer
000026H
FRT1 - Control status register of freerunning timer
TCCSL1
000027H
FRT1 - Control status register of freerunning timer
TCCSH1
000028H
OCU0 - Output Compare Control
Status
000029H
OCU1 - Output Compare Control
Status
00002AH
OCU0 - Compare Register
00002BH
OCU0 - Compare Register
00002CH
OCU1 - Compare Register
00002DH
OCU1 - Compare Register
00002EH
OCU2 - Output Compare Control
Status
00002FH
OCU3 - Output Compare Control
Status
000030H
OCU2 - Compare Register
000031H
OCU2 - Compare Register
000032H
OCU3 - Compare Register
000033H
OCU3 - Compare Register
000034H
OCU4 - Output Compare Control
Status
OCS4
RW
000035H
OCU5 - Output Compare Control
Status
OCS5
RW
000036H
OCU4 - Compare Register
000037H
OCU4 - Compare Register
000038H
OCU5 - Compare Register
000039H
OCU5 - Compare Register
00003AH
OCU6 - Output Compare Control
Status
OCS6
RW
00003BH
OCU7 - Output Compare Control
Status
OCS7
RW
RW
Y
OCS1
RW
RW
OCCP0
RW
RW
IN
OCCP1
EL
IM
PR
FME/EMDC- 2007-9-12
RW
RW
AR
OCS0
TCCS1
RW
RW
OCS2
RW
OCS3
RW
OCCP2
RW
RW
OCCP3
RW
RW
OCCP4
RW
RW
OCCP5
RW
RW
MB96340_DS_memory.fm
25
MB96340 Series
Specification
I/O map (3 / 34)
26
Abbreviation
8-bit access
Address
Register
00003CH
OCU6 - Compare Register
00003DH
OCU6 - Compare Register
00003EH
OCU7 - Compare Register
00003FH
OCU7 - Compare Register
000040H
ICU0/ICU1 - Control Status Register
ICS01
000041H
ICU0/ICU1 - Edge register
ICE01
000042H
ICU0 - Capture Register
000043H
ICU0 - Capture Register
000044H
ICU1 - Capture Register
000045H
ICU1 - Capture Register
000046H
ICU2/ICU3 - Control Status Register
000047H
ICU2/3 - Edge register
000048H
ICU2 - Capture Register
000049H
ICU2 - Capture Register
00004AH
ICU3 - Capture Register
00004BH
ICU3 - Capture Register
00004CH
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
OCCP6
RW
RW
OCCP7
RW
IPCP0
AR
IPCPL0
Y
RW
IPCPH0
IPCPL1
RW
R
R
IPCP1
R
R
ICS23
RW
IN
IPCPH1
IPCP2
IPCPL3
IPCP3
ICE23
IPCPL2
RW
IPCPH2
IM
RW
R
R
R
R
ICU4/ICU5 - Control Status Register
ICS45
RW
00004DH
ICU4/ICU5 - Edge register
ICE45
RW
00004EH
ICU4 - Capture Register
IPCPL4
00004FH
ICU4 - Capture Register
IPCPH4
000050H
ICU5 - Capture Register
IPCPL5
000051H
ICU5 - Capture Register
IPCPH5
R
000052H
ICU6/ICU7 - Control Status Register
ICS67
RW
000053H
ICU6/ICU7 - Edge register
ICE67
RW
000054H
ICU6 - Capture Register
IPCPL6
000055H
ICU6 - Capture Register
IPCPH6
000056H
ICU7 - Capture Register
IPCPL7
000057H
ICU7 - Capture Register
IPCPH7
R
000058H
EXTINT0 - External Interrupt Enable
Register
ENIR0
RW
PR
EL
IPCPH3
FME/EMDC- 2007-9-12
IPCP4
R
R
IPCP5
IPCP6
R
R
R
IPCP7
MB96340_DS_memory.fm
R
Specification
MB96340
I/O map (4 / 34)
Abbreviation
8-bit access
Address
Register
000059H
EXTINT0 - External Interrupt Interrupt
request Register
00005AH
EXTINT0 - External Interrupt Level
Select
ELVRL0
00005BH
EXTINT0 - External Interrupt Level
Select
ELVRH0
00005CH
EXTINT1 - External Interrupt Enable
Register
00005DH
EXTINT1 - External Interrupt Interrupt
request Register
00005EH
EXTINT1 - External Interrupt Level
Select
ELVRL1
00005FH
EXTINT1 - External Interrupt Level
Select
ELVRH1
000060H
RLT0 - Timer Control Status Register
Low
000061H
RLT0 - Timer Control Status Register
High
000062H
RLT0 - Reload Register Low
TMRLR0
000063H
RLT0 - Reload Register High
TMRHR0
000064H
RLT1 - Timer Control Status Register
Low
TMCSRL1
000065H
RLT1 - Timer Control Status Register
High
TMCSRH1
000066H
RLT1 - Reload Register Low
TMRLR1
000067H
RLT1 - Reload Register High
TMRHR1
000068H
RLT2 - Timer Control Status Register
Low
TMCSRL2
000069H
RLT2 - Timer Control Status Register
High
TMCSRH2
00006AH
RLT2 - Reload Register Low
TMRLR2
00006BH
RLT2 - Reload Register High
TMRHR2
00006CH
RLT3 - Timer Control Status Register
Low
TMCSRL3
00006DH
RLT3 - Timer Control Status Register
High
TMCSRH3
Abbreviation
32-bit access
Access
EIRR0
RW
ELVR0
IN
Y
EIRR1
TMCSRL0
RW
RW
AR
ENIR1
RW
RW
ELVR1
RW
RW
TMCSR0
TMCSRH0
EL
IM
PR
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
RW
RW
TMR0
RW
RW
TMCSR1
RW
RW
TMR1
RW
RW
TMCSR2
RW
RW
TMR2
RW
RW
TMCSR3
RW
RW
MB96340_DS_memory.fm
27
MB96340 Series
Specification
I/O map (5 / 34)
28
Abbreviation
8-bit access
Abbreviation
16-bit access
RLT3 - Reload Register Low
TMRLR3
TMR3
00006FH
RLT3 - Reload Register High
TMRHR3
000070H
RLT6 - Timer Control Status Register
Low (dedic. RLT for PPG)
TMCSRL6
000071H
RLT6 - Timer Control Status Register
High (dedic. RLT for PPG)
TMCSRH6
000072H
RLT6 - Reload Register Low (dedic.
RLT for PPG) - for writing
000072H
RLT6 - Reload Register Low (dedic.
RLT for PPG) - for reading
000073H
RLT6 - Reload Register High (dedic.
RLT for PPG) - for writing
000073H
RLT6 - Reload Register High (dedic.
RLT for PPG) - for reading
000074H
PPG3-PPG0 - General Control register
1 Low
GCN1L0
000075H
PPG3-PPG0 - General Control register
1 High
GCN1H0
000076H
PPG3-PPG0 - General Control register
2 Low
GCN2L0
000077H
PPG3-PPG0 - General Control register
2 High
GCN2H0
000078H
PPG0 - Timer register
000079H
PPG0 - Timer register
00007AH
PPG0 - Period setting register
00007BH
PPG0 - Period setting register
00007CH
PPG0 - Duty cycle register
00007DH
PPG0 - Duty cycle register
00007EH
PPG0 - Control status register
PCNL0
00007FH
PPG0 - Control status register
PCNH0
000080H
PPG1 - Timer register
000081H
PPG1 - Timer register
000082H
PPG1 - Period setting register
000083H
PPG1 - Period setting register
RW
RW
TMCSR6
RW
RW
TMRLR6
IM
PR
EL
FME/EMDC- 2007-9-12
Access
Y
00006EH
Abbreviation
32-bit access
AR
Register
TMR6
IN
Address
RW
RW
RW
RW
GCN10
RW
RW
GCN20
RW
RW
PTMR0
R
R
PCSR0
W
W
PDUT0
W
W
PCN0
RW
RW
PTMR1
R
R
PCSR1
W
W
MB96340_DS_memory.fm
Specification
MB96340
I/O map (6 / 34)
Abbreviation
8-bit access
Address
Register
000084H
PPG1 - Duty cycle register
000085H
PPG1 - Duty cycle register
000086H
PPG1 - Control status register
PCNL1
000087H
PPG1 - Control status register
PCNH1
000088H
PPG2 - Timer register
000089H
PPG2 - Timer register
00008AH
PPG2 - Period setting register
00008BH
PPG2 - Period setting register
00008CH
PPG2 - Duty cycle register
00008DH
PPG2 - Duty cycle register
00008EH
PPG2 - Control status register
00008FH
PPG2 - Control status register
000090H
PPG3 - Timer register
000091H
PPG3 - Timer register
000092H
PPG3 - Period setting register
000093H
PPG3 - Period setting register
000094H
PPG3 - Duty cycle register
000095H
PPG3 - Duty cycle register
000096H
PPG3 - Control status register
PCNL3
000097H
PPG3 - Control status register
PCNH3
000098H
PPG7-PPG4 - General Control register
1 Low
GCN1L1
000099H
PPG7-PPG4 - General Control register
1 High
GCN1H1
00009AH
PPG7-PPG4 - General Control register
2 Low
GCN2L1
00009BH
PPG7-PPG4 - General Control register
2 High
GCN2H1
00009CH
PPG4 - Timer register
00009DH
PPG4 - Timer register
00009EH
PPG4 - Period setting register
Abbreviation
32-bit access
Access
PDUT1
W
W
PCN1
Y
AR
PCSR2
IN
R
R
W
W
PDUT2
PCNL2
RW
RW
PTMR2
W
W
PCN2
PCNH2
EL
IM
PR
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
RW
RW
PTMR3
R
R
PCSR3
W
W
PDUT3
W
W
PCN3
RW
RW
GCN11
RW
RW
GCN21
RW
RW
PTMR4
R
R
PCSR4
MB96340_DS_memory.fm
W
29
MB96340 Series
Specification
I/O map (7 / 34)
30
Abbreviation
8-bit access
Address
Register
00009FH
PPG4 - Period setting register
0000A0H
PPG4 - Duty cycle register
0000A1H
PPG4 - Duty cycle register
0000A2H
PPG4 - Control status register
PCNL4
0000A3H
PPG4 - Control status register
PCNH4
0000A4H
PPG5 - Timer register
0000A5H
PPG5 - Timer register
0000A6H
PPG5 - Period setting register
0000A7H
PPG5 - Period setting register
0000A8H
PPG5 - Duty cycle register
0000A9H
PPG5 - Duty cycle register
0000AAH
PPG5 - Control status register
0000ABH
PPG5 - Control status register
0000ACH
I2C0 - Bus Status Register
0000ADH
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
W
PDUT4
W
W
Y
PCN4
AR
PTMR5
PCSR5
IN
RW
R
R
W
W
PDUT5
PCNL5
RW
W
W
PCN5
RW
RW
IBSR0
R
I2C0 - Bus Control Register
IBCR0
RW
0000AEH
I2C0 - Ten bit Slave address Register
Low
ITBAL0
0000AFH
I2C0 - Ten bit Slave address Register
High
ITBAH0
0000B0H
I2C0 - Ten bit Address mask Register
Low
ITMKL0
0000B1H
I2C0 - Ten bit Address mask Register
High
ITMKH0
RW
0000B2H
I2C0 - Seven bit Slave address
Register
ISBA0
RW
0000B3H
I2C0 - Seven bit Address mask
Register
ISMK0
RW
0000B4H
I2C0 - Data Register
IDAR0
RW
0000B5H
I2C0 - Clock Control Register
ICCR0
RW
0000B6H
I2C1 - Bus Status Register
IBSR1
R
0000B7H
I2C1 - Bus Control Register
IBCR1
RW
0000B8H
I2C1 - Ten bit Slave address Register
Low
ITBAL1
PR
EL
IM
PCNH5
FME/EMDC- 2007-9-12
ITBA0
RW
RW
ITMK0
ITBA1
MB96340_DS_memory.fm
RW
RW
Specification
MB96340
I/O map (8 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Address
Register
0000B9H
I2C1 - Ten bit Slave address Register
High
ITBAH1
0000BAH
I2C1 - Ten bit Address mask Register
Low
ITMKL1
0000BBH
I2C1 - Ten bit Address mask Register
High
ITMKH1
0000BCH
I2C1 - Seven bit Slave address
Register
ISBA1
0000BDH
I2C1 - Seven bit Address mask
Register
ISMK1
RW
0000BEH
I2C1 - Data Register
IDAR1
RW
0000BFH
I2C1 - Clock Control Register
ICCR1
RW
0000C0H
USART0 USART - Serial Mode
Register
SMR0
0000C1H
USART0 - Serial Control Register
0000C2H
USART0 - TX Register
0000C2H
USART0 - RX Register
0000C3H
USART0 - Serial Status
0000C4H
RW
ITMK1
RW
RW
RW
SCR0
RW
TDR0
W
RDR0
R
SSR0
RW
USART0 - Control/Com. Register
ECCR0
RW
0000C5H
USART0 - Ext. Status Register
ESCR0
RW
0000C6H
USART0 - Baud Rate Generator
Register Low
BGRL0
0000C7H
USART0 - Baud Rate Generator
Register High
BGRH0
RW
0000C8H
USART0 - Extended Serial Interrupt
Register
ESIR0
RW
0000C9H
Reserved
0000CAH
USART1 - Serial Mode Register
SMR1
RW
0000CBH
USART1 - Serial Control Register
SCR1
RW
0000CCH
USART1 - TX Register
TDR1
W
0000CCH
USART1 - RX Register
RDR1
R
0000CDH
USART1 - Serial Status
SSR1
RW
0000CEH
USART1 - Control/Com. Register
ECCR1
RW
PR
EL
IM
IN
AR
Y
RW
FME/EMDC- 2007-9-12
BGR0
MB96340_DS_memory.fm
RW
31
MB96340 Series
Specification
I/O map (9 / 34)
32
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Address
Register
0000CFH
USART1 - Ext. Status Register
ESCR1
0000D0H
USART1 - Baud Rate Generator
Register Low
BGRL1
0000D1H
USART1 - Baud Rate Generator
Register High
BGRH1
0000D2H
USART1 - Extended Serial Interrupt
Register
ESIR1
0000D3H
Reserved
0000D4H
USART2 - Serial Mode Register
0000D5H
USART2 - Serial Control Register
0000D6H
USART2 - TX Register
0000D6H
USART2 - RX Register
0000D7H
USART2 - Serial Status
0000D8H
USART2 - Control/Com. Register
0000D9H
USART2 - Ext. Status Register
0000DAH
USART2 - Baud Rate Generator
Register Low
BGRL2
0000DBH
USART2 - Baud Rate Generator
Register High
BGRH2
RW
0000DCH
USART2 - Extended Serial Interrupt
Register
ESIR2
RW
0000DDH
Reserved
0000DEH
USART3 - Serial Mode Register
SMR3
RW
0000DFH
USART3 - Serial Control Register
SCR3
RW
0000E0H
USART3 - TX Register
TDR3
W
0000E0H
USART3 - RX Register
RDR3
R
0000E1H
USART3 - Serial Status
SSR3
RW
0000E2H
USART3 - Control/Com. Register
ECCR3
RW
0000E3H
USART3 - Ext. Status Register
ESCR3
RW
0000E4H
USART3 - Baud Rate Generator
Register Low
BGRL3
0000E5H
USART3 - Baud Rate Generator
Register High
BGRH3
BGR1
RW
AR
Y
RW
RW
SMR2
RW
SCR2
RW
TDR2
W
RDR2
R
IN
IM
PR
EL
FME/EMDC- 2007-9-12
RW
SSR2
RW
ECCR2
RW
ESCR2
RW
BGR2
BGR3
RW
RW
RW
MB96340_DS_memory.fm
Specification
MB96340
I/O map (10 / 34)
Abbreviation
8-bit access
Address
Register
0000E6H
USART3 - Extended Serial Interrupt
Register
0000F0H
external bus
000100H
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
RW
EXTBUS0
RW
DMA0 - Buffer address pointer low byte
BAPL0
RW
000101H
DMA0 - Buffer address pointer middle
byte
BAPM0
RW
000102H
DMA0 - Buffer address pointer high
byte
BAPH0
000103H
DMA0 - DMA control register
000104H
DMA0 - I/O register address pointer
low byte
000105H
DMA0 - I/O register address pointer
high byte
000106H
DMA0 - Data counter low byte
000107H
DMA0 - Data counter high byte
000108H
AR
Y
ESIR3
DMACS0
IOAL0
RW
IOA0
IN
IOAH0
DCTL0
RW
RW
RW
DCT0
RW
RW
DMA1 - Buffer address pointer low byte
BAPL1
RW
000109H
DMA1 - Buffer address pointer middle
byte
BAPM1
RW
00010AH
DMA1 - Buffer address pointer high
byte
BAPH1
RW
00010BH
DMA1 - DMA control register
DMACS1
RW
00010CH
DMA1 - I/O register address pointer
low byte
IOAL1
00010DH
DMA1 - I/O register address pointer
high byte
IOAH1
00010EH
DMA1 - Data counter low byte
DCTL1
00010FH
DMA1 - Data counter high byte
DCTH1
RW
000110H
DMA2 - Buffer address pointer low byte
BAPL2
RW
000111H
DMA2 - Buffer address pointer middle
byte
BAPM2
RW
000112H
DMA2 - Buffer address pointer high
byte
BAPH2
RW
000113H
DMA2 - DMA control register
DMACS2
RW
000114H
DMA2 - I/O register address pointer
low byte
PR
EL
IM
DCTH0
FME/EMDC- 2007-9-12
IOAL2
IOA1
RW
RW
DCT1
IOA2
MB96340_DS_memory.fm
RW
RW
33
MB96340 Series
Specification
I/O map (11 / 34)
34
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Address
Register
000115H
DMA2 - I/O register address pointer
high byte
IOAH2
000116H
DMA2 - Data counter low byte
DCTL2
000117H
DMA2 - Data counter high byte
DCTH2
RW
000118H
DMA3 - Buffer address pointer low byte
BAPL3
RW
000119H
DMA3 - Buffer address pointer middle
byte
BAPM3
00011AH
DMA3 - Buffer address pointer high
byte
00011BH
DMA3 - DMA control register
00011CH
DMA3 - I/O register address pointer
low byte
00011DH
DMA3 - I/O register address pointer
high byte
00011EH
DMA3 - Data counter low byte
00011FH
DMA3 - Data counter high byte
000120H
RW
AR
Y
DCT2
RW
RW
BAPH3
RW
DMACS3
RW
IN
IOAL3
IOA3
IOAH3
DCTL3
RW
RW
DCT3
RW
RW
DMA4 - Buffer address pointer low byte
BAPL4
RW
000121H
DMA4 - Buffer address pointer middle
byte
BAPM4
RW
000122H
DMA4 - Buffer address pointer high
byte
BAPH4
RW
000123H
DMA4 - DMA control register
DMACS4
RW
000124H
DMA4 - I/O register address pointer
low byte
IOAL4
000125H
DMA4 - I/O register address pointer
high byte
IOAH4
000126H
DMA4 - Data counter low byte
DCTL4
000127H
DMA4 - Data counter high byte
DCTH4
RW
000128H
DMA5 - Buffer address pointer low byte
BAPL5
RW
000129H
DMA5 - Buffer address pointer middle
byte
BAPM5
RW
00012AH
DMA5 - Buffer address pointer high
byte
BAPH5
RW
00012BH
DMA5 - DMA control register
DMACS5
RW
PR
EL
IM
DCTH3
FME/EMDC- 2007-9-12
IOA4
RW
RW
DCT4
MB96340_DS_memory.fm
RW
Specification
MB96340
I/O map (12 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
DMA5 - I/O register address pointer
low byte
IOAL5
IOA5
00012DH
DMA5 - I/O register address pointer
high byte
IOAH5
00012EH
DMA5 - Data counter low byte
DCTL5
00012FH
DMA5 - Data counter high byte
DCTH5
000180H
CPU - General Purpose registers
(RAM access)
000380H
DMA0 - Interrupt select
DISEL0
RW
000381H
DMA1 - Interrupt select
DISEL1
RW
000382H
DMA2 - Interrupt select
DISEL2
RW
000383H
DMA3 - Interrupt select
DISEL3
RW
000384H
DMA4 - Interrupt select
DISEL4
RW
000385H
DMA5 - Interrupt select
DISEL5
RW
000386H
00038FH
Reserved
000390H
DMA7-DMA0 - status register
000391H
Reserved
000392H
DMA7-DMA0 - stop status register
000393H
Reserved
000394H
DMA7-DMA0 - enable register
000395H
000398H
Reserved
000399H
Unused
0003A0H
Access
RW
RW
Y
DCT5
AR
GPR_RAM
Abbreviation
32-bit access
IN
00012CH
EL
IM
Register
RW
RW
RW
DSRL
DSR
RW
DSSRL
DSSR
RW
DERL
DER
RW
Interrupt level register
ILR
ICR
RW
0003A1H
Interrupt Index register
IDX
0003A2H
PR
Address
Interrupt vector Table base register
TBRL
0003A3H
Interrupt vector Table base register
TBRH
RW
0003A4H
Delayed Interrupt register
DIRR
RW
0003A5H
Non maskable Interrupt register
NMI
RW
FME/EMDC- 2007-9-12
RW
TBR
MB96340_DS_memory.fm
RW
35
MB96340 Series
Specification
I/O map (13 / 34)
36
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
0003A6H
0003ADH
Reserved
0003AEH
ROM mirror control register
ROMM
RW
0003AFH
EDSU configuration register
EDSU
RW
0003B0H
Memory patch control/status register
ch 0/1
0003B1H
Memory patch control/status register
ch 0/1
0003B2H
Memory patch control/status register
ch 2/3
0003B3H
Memory patch control/status register
ch 2/3
0003B4H
Memory patch control/status register
ch 4/5
0003B5H
Memory patch control/status register
ch 4/5
0003B6H
Memory patch control/status register
ch 6/7
0003B7H
Memory patch control/status register
ch 6/7
0003B8H
Memory Patch function - Patch
address 0 low
PFAL0
RW
0003B9H
Memory Patch function - Patch
address 0 middle
PFAM0
RW
0003BAH
Memory Patch function - Patch
address 0 high
PFAH0
RW
0003BBH
Memory Patch function - Patch
address 1 low
PFAL1
RW
0003BCH
Memory Patch function - Patch
address 1 middle
PFAM1
RW
0003BDH
Memory Patch function - Patch
address 1 high
PFAH1
RW
0003BEH
Memory Patch function - Patch
address 2 low
PFAL2
RW
0003BFH
Memory Patch function - Patch
address 2 middle
PFAM2
RW
Y
Address
AR
PFCS0
PR
EL
IM
IN
PFCS1
FME/EMDC- 2007-9-12
RW
RW
RW
RW
PFCS2
RW
RW
PFCS3
RW
RW
MB96340_DS_memory.fm
Specification
MB96340
I/O map (14 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
0003C0H
Memory Patch function - Patch
address 2 high
PFAH2
RW
0003C1H
Memory Patch function - Patch
address 3 low
PFAL3
RW
0003C2H
Memory Patch function - Patch
address 3 middle
PFAM3
RW
0003C3H
Memory Patch function - Patch
address 3 high
PFAH3
0003C4H
Memory Patch function - Patch
address 4 low
0003C5H
RW
AR
Y
Address
RW
PFAL5
RW
PFAM5
RW
RW
Memory Patch function - Patch
address 4 middle
PFAM4
0003C6H
Memory Patch function - Patch
address 4 high
PFAH4
RW
0003C7H
Memory Patch function - Patch
address 5 low
0003C8H
Memory Patch function - Patch
address 5 middle
0003C9H
Memory Patch function - Patch
address 5 high
PFAH5
RW
0003CAH
Memory Patch function - Patch
address 6 low
PFAL6
RW
0003CBH
Memory Patch function - Patch
address 6 middle
PFAM6
RW
0003CCH
Memory Patch function - Patch
address 6 high
PFAH6
RW
0003CDH
Memory Patch function - Patch
address 7 low
PFAL7
RW
0003CEH
Memory Patch function - Patch
address 7 middle
PFAM7
RW
0003CFH
Memory Patch function - Patch
address 7 high
PFAH7
RW
0003D0H
Memory Patch function - Patch data 0
PFDL0
0003D1H
Memory Patch function - Patch data 0
PFDH0
0003D2H
Memory Patch function - Patch data 1
PFDL1
0003D3H
Memory Patch function - Patch data 1
PFDH1
PR
EL
IM
IN
PFAL4
FME/EMDC- 2007-9-12
PFD0
RW
RW
PFD1
RW
RW
MB96340_DS_memory.fm
37
MB96340 Series
Specification
I/O map (15 / 34)
38
Abbreviation
8-bit access
Abbreviation
16-bit access
Memory Patch function - Patch data 2
PFDL2
PFD2
0003D5H
Memory Patch function - Patch data 2
PFDH2
0003D6H
Memory Patch function - Patch data 3
PFDL3
0003D7H
Memory Patch function - Patch data 3
PFDH3
0003D8H
Memory Patch function - Patch data 4
PFDL4
0003D9H
Memory Patch function - Patch data 4
PFDH4
0003DAH
Memory Patch function - Patch data 5
PFDL5
0003DBH
Memory Patch function - Patch data 5
0003DCH
Memory Patch function - Patch data 6
0003DDH
Memory Patch function - Patch data 6
0003DEH
Memory Patch function - Patch data 7
0003DFH
Memory Patch function - Patch data 7
0003E0H
0003EFH
Reserved
0003F0H
0003F2H
Reserved
0003F3H
Access
PFD3
PFD4
PFD5
RW
RW
RW
RW
PFD6
PFDH6
PFDL7
RW
RW
PFDH5
PFDL6
RW
RW
Y
0003D4H
Abbreviation
32-bit access
AR
Register
RW
RW
PFD7
IN
Address
RW
RW
Flash Memory Timing Configuration
register 1 (Main Flash)
MFMTCH
RW
0003F7H
Flash Memory Timing Configuration
register 1 (Sat Flash)
SFMTCH
RW
0003F8H
Flash Memory Write Control register 0
FMWC0
RW
0003F9H
Flash Memory Write Control register 1
FMWC1
RW
0003FDH
Flash Memory Write Control register 5
FMWC5
RW
000401H
Clock select register
CKSR
RW
000402H
Clock Stabilisation select register
CKSSR
RW
000403H
Clock monitor register
CKMR
R
000404H
Clock Frequency control register Low
CKFCRL
000405H
Clock Frequency control register High
CKFCRH
000406H
PLL Control register Low
PLLCRL
000408H
RC clock timer control register
RCTCR
PR
EL
IM
PFDH7
FME/EMDC- 2007-9-12
CKFCR
RW
RW
PLLCR
RW
RW
MB96340_DS_memory.fm
Specification
MB96340
I/O map (16 / 34)
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
000409H
Main clock timer control register
MCTCR
RW
00040AH
Sub clock timer control register
SCTCR
RW
00040BH
Reset cause and clock status register
with clear function
RCCSRC
R
00040CH
Reset configuration register
RCR
RW
00040DH
Reset cause and clock status register
RCCSR
00040EH
Watch dog timer configuration register
WDTC
00040FH
Watch dog timer clear pattern register
WDTCP
W
000410H
000414H
Reserved
000415H
Clock output activation register
COAR
RW
000416H
Clock output configuration register 0
COCR0
RW
000417H
Clock output configuration register 1
COCR1
RW
000418H
Clock Modulator control register
CMCR
RW
000419H
Unused
00041AH
Clock Modulator Parameter register
Low
CMPRL
00041BH
Clock Modulator Parameter register
High
CMPRH
RW
00041CH
00042BH
Reserved
00042CH
Voltage Regulator Control register
VRCR
RW
00042DH
00042FH
Reserved
000430H
P00 - I/O Port Data Direction Register
DDR00
RW
000431H
P01 - I/O Port Data Direction Register
DDR01
RW
000432H
P02 - I/O Port Data Direction Register
DDR02
RW
000433H
P03 - I/O Port Data Direction Register
DDR03
RW
000434H
P04 - I/O Port Data Direction Register
DDR04
RW
000435H
P05 - I/O Port Data Direction Register
DDR05
RW
FME/EMDC- 2007-9-12
EL
IM
IN
AR
Y
Register
PR
Abbreviation
8-bit access
Address
CMPR
MB96340_DS_memory.fm
R
RW
RW
39
MB96340 Series
Specification
I/O map (17 / 34)
40
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
000436H
P06 - I/O Port Data Direction Register
DDR06
RW
000437H
P07 - I/O Port Data Direction Register
DDR07
RW
000438H
P08 - I/O Port Data Direction Register
DDR08
RW
000439H
P09 - I/O Port Data Direction Register
DDR09
RW
00043AH
P10 - I/O Port Data Direction Register
DDR10
RW
00043BH
000443H
Reserved
000444H
P00 - I/O Port Port Input Enable
Register
000445H
P01 - I/O Port Port Input Enable
Register
000446H
P02 - I/O Port Port Input Enable
Register
000447H
P03 - I/O Port Port Input Enable
Register
000448H
P04 - I/O Port Port Input Enable
Register
000449H
RW
PIER01
RW
PIER02
RW
PIER03
RW
PIER04
RW
P05 - I/O Port Port Input Enable
Register
PIER05
RW
00044AH
P06 - I/O Port Port Input Enable
Register
PIER06
RW
00044BH
P07 - I/O Port Port Input Enable
Register
PIER07
RW
00044CH
P08 - I/O Port Port Input Enable
Register
PIER08
RW
00044DH
P09 - I/O Port Port Input Enable
Register
PIER09
RW
00044EH
P10 - I/O Port Port Input Enable
Register
PIER10
RW
00044FH
000457H
Reserved
000458H
P00 - I/O Port Port Input Level Register
PILR00
RW
000459H
P01 - I/O Port Port Input Level Register
PILR01
RW
00045AH
P02 - I/O Port Port Input Level Register
PILR02
RW
PR
EL
IM
PIER00
IN
AR
Y
Address
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (18 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
00045BH
P03 - I/O Port Port Input Level Register
PILR03
RW
00045CH
P04 - I/O Port Port Input Level Register
PILR04
RW
00045DH
P05 - I/O Port Port Input Level Register
PILR05
RW
00045EH
P06 - I/O Port Port Input Level Register
PILR06
RW
00045FH
P07 - I/O Port Port Input Level Register
PILR07
RW
000460H
P08 - I/O Port Port Input Level Register
PILR08
000461H
P09 - I/O Port Port Input Level Register
PILR09
000462H
P10 - I/O Port Port Input Level Register
PILR10
RW
000463H
00046BH
Reserved
00046CH
P00 - I/O Port Extended Port Input
Level Register
EPILR00
RW
00046DH
P01 - I/O Port Extended Port Input
Level Register
EPILR01
RW
00046EH
P02 - I/O Port Extended Port Input
Level Register
EPILR02
RW
00046FH
P03 - I/O Port Extended Port Input
Level Register
EPILR03
RW
000470H
P04 - I/O Port Extended Port Input
Level Register
EPILR04
RW
000471H
P05 - I/O Port Extended Port Input
Level Register
EPILR05
RW
000472H
P06 - I/O Port Extended Port Input
Level Register
EPILR06
RW
000473H
P07 - I/O Port Extended Port Input
Level Register
EPILR07
RW
000474H
P08 - I/O Port Extended Port Input
Level Register
EPILR08
RW
000475H
P09 - I/O Port Extended Port Input
Level Register
EPILR09
RW
000476H
P10 - I/O Port Extended Port Input
Level Register
EPILR10
RW
000477H
00047FH
Reserved
PR
EL
IM
IN
AR
Y
Address
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
RW
RW
41
MB96340 Series
Specification
I/O map (19 / 34)
42
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
000480H
P00 - I/O Port Port Output Drive
Register
PODR00
RW
000481H
P01 - I/O Port Port Output Drive
Register
PODR01
RW
000482H
P02 - I/O Port Port Output Drive
Register
PODR02
RW
000483H
P03 - I/O Port Port Output Drive
Register
PODR03
000484H
P04 - I/O Port Port Output Drive
Register
000485H
P05 - I/O Port Port Output Drive
Register
000486H
P06 - I/O Port Port Output Drive
Register
000487H
P07 - I/O Port Port Output Drive
Register
000488H
P08 - I/O Port Port Output Drive
Register
000489H
AR
Y
Address
RW
RW
PODR05
RW
PODR06
RW
IN
PODR04
RW
PODR08
RW
P09 - I/O Port Port Output Drive
Register
PODR09
RW
00048AH
P10 - I/O Port Port Output Drive
Register
PODR10
RW
00049CH
0004A7H
Reserved
0004A8H
P00 - I/O Port Pull-Up resistor Control
Register
PUCR00
RW
0004A9H
P01 - I/O Port Pull-Up resistor Control
Register
PUCR01
RW
0004AAH
P02 - I/O Port Pull-Up resistor Control
Register
PUCR02
RW
0004ABH
P03 - I/O Port Pull-Up resistor Control
Register
PUCR03
RW
0004ACH
P04 - I/O Port Pull-Up resistor Control
Register
PUCR04
RW
0004ADH
P05 - I/O Port Pull-Up resistor Control
Register
PUCR05
RW
PR
EL
IM
PODR07
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
I/O map (20 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
0004AEH
P06 - I/O Port Pull-Up resistor Control
Register
PUCR06
RW
0004AFH
P07 - I/O Port Pull-Up resistor Control
Register
PUCR07
RW
0004B0H
P08 - I/O Port Pull-Up resistor Control
Register
PUCR08
RW
0004B1H
P09 - I/O Port Pull-Up resistor Control
Register
PUCR09
0004B2H
P10 - I/O Port Pull-Up resistor Control
Register
PUCR10
RW
0004B3H
0004BBH
Reserved
0004BCH
P00 - I/O Port External Pin State
Register
EPSR00
R
0004BDH
P01 - I/O Port External Pin State
Register
EPSR01
R
0004BEH
P02 - I/O Port External Pin State
Register
EPSR02
R
0004BFH
P03 - I/O Port External Pin State
Register
EPSR03
R
0004C0H
P04 - I/O Port External Pin State
Register
EPSR04
R
0004C1H
P05 - I/O Port External Pin State
Register
EPSR05
R
0004C2H
P06 - I/O Port External Pin State
Register
EPSR06
R
0004C3H
P07 - I/O Port External Pin State
Register
EPSR07
R
0004C4H
P08 - I/O Port External Pin State
Register
EPSR08
R
0004C5H
P09 - I/O Port External Pin State
Register
EPSR09
R
0004C6H
P10 - I/O Port External Pin State
Register
EPSR10
R
0004C7H
0004CFH
Reserved
PR
EL
IM
IN
AR
Y
Address
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
RW
43
MB96340 Series
Specification
I/O map (21 / 34)
44
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
0004D0H
ADC analog input enable register 0
ADER0
RW
0004D1H
ADC analog input enable register 1
ADER1
RW
0004D2H
ADC analog input enable register 2
ADER2
RW
0004D3H
0004D4H
Reserved
0004D5H
Reserved
0004D6H
Peripheral Resource Relocation
Register 0
0004D7H
Peripheral Resource Relocation
Register 1
0004D8H
0004DBH
Reserved
0004DCH
Peripheral Resource Relocation
Register 6
0004DDH
Peripheral Resource Relocation
Register 7
0004DEH
RW
PRRR1
RW
PRRR6
RW
PRRR7
RW
Peripheral Resource Relocation
Register 8
PRRR8
RW
0004DFH
Peripheral Resource Relocation
Register 9
PRRR9
RW
0004E0H
RTC - Sub Second Register L
WTBRL0
0004E1H
RTC - Sub Second Register M
WTBRH0
RW
0004E2H
RTC - Sub-Second Register H
WTBR1
RW
0004E3H
RTC - Second Register
WTSR
RW
0004E4H
RTC - Minutes
WTMR
RW
0004E5H
RTC - Hour
WTHR
RW
0004E6H
RTC - Timer Control Extended
Register
WTCER
RW
0004E7H
RTC - Clock select register
WTCKSR
RW
0004E8H
Reserved
0004E9H
RTC - Timer Control Register H
WTCRH
RW
0004EAH
CAL - Calibration unit Control register
CUCR
RW
PR
EL
IM
PRRR0
IN
AR
Y
Address
FME/EMDC- 2007-9-12
WTBR0
MB96340_DS_memory.fm
RW
Specification
MB96340
Abbreviation
8-bit access
Abbreviation
16-bit access
CAL - Sub/RC-clock timer data register
L
CUTDL
CUTD
0004EDH
CAL - Sub/RC-clock timer data register
H
CUTDH
0004EEH
CAL - Main clock timer data register 2
L
CUTR2L
0004EFH
CAL - Main clock timer data register 2
H
CUTR2H
0004F0H
CAL - Main clock timer data register 1
L
CUTR1L
0004F1H
CAL - Main clock timer data register 1
H
CUTR1H
0004F2H
0004F9H
Reserved
0004FAH
RLT - Timer input select (for
Cascading)
0004FBH
00053DH
Reserved
00053EH
USART7 - Serial Mode Register
SMR7
RW
00053FH
USART7 - Serial Control Register
SCR7
RW
000540H
USART7 - Serial TX Register
TDR7
W
000540H
USART7 - Serial RX Register
RDR7
R
000541H
USART7 - Serial Status Register
SSR7
RW
000542H
USART7 - Ext. Control/Com. Register
ECCR7
RW
000543H
USART7 - Ext. Status Com. Register
ESCR7
RW
000544H
USART7 - Baud Rate Generator
Register
BGRL7
000545H
PR
I/O map (22 / 34)
USART7 - Baud Rate Generator
Register
BGRH7
RW
000546H
USART7 - Extended Serial Interrupt
Register
ESIR7
RW
000548H
USART8 - Serial Mode Register
SMR8
RW
0004ECH
FME/EMDC- 2007-9-12
RW
RW
Y
Reserved
Access
CUTR2
AR
0004EBH
Abbreviation
32-bit access
CUTR1
R
R
R
R
IN
Register
TMISR
EL
IM
Address
RW
BGR7
MB96340_DS_memory.fm
RW
45
MB96340 Series
Specification
I/O map (23 / 34)
46
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
000549H
USART8 - Serial Control Register
SCR8
RW
00054AH
USART8 - Serial TX Register
TDR8
W
00054AH
USART8 - Serial RX Register
RDR8
R
00054BH
USART8 - Serial Status Register
SSR8
RW
00054CH
USART8 - Ext. Control/Com. Register
ECCR8
RW
00054DH
USART8 - Ext. Status Com. Register
ESCR8
00054EH
USART8 - Baud Rate Generator
Register
00054FH
USART8 - Baud Rate Generator
Register
000550H
USART8 - Extended Serial Interrupt
Register
000552H
USART9 - Serial Mode Register
000553H
USART9 - Serial Control Register
000554H
USART9 - Serial TX Register
000554H
AR
Y
Address
BGRL8
BGR8
RW
RW
RW
ESIR8
RW
IN
BGRH8
RW
SCR9
RW
TDR9
W
USART9 - Serial RX Register
RDR9
R
000555H
USART9 - Serial Status Register
SSR9
RW
000556H
USART9 - Ext. Control/Com. Register
ECCR9
RW
000557H
USART9 - Ext. Status Com. Register
ESCR9
RW
000558H
USART9 - Baud Rate Generator
Register
BGRL9
000559H
USART9 - Baud Rate Generator
Register
BGRH9
RW
00055AH
USART9 - Extended Serial Interrupt
Register
ESIR9
RW
000560H
ALARM0 - Control Status Register
ACSR0
RW
000561H
ALARM0 - Extended Control Status
Register
AECSR0
RW
000562H
ALARM1 - Control Status Register
ACSR1
RW
000563H
ALARM1 - Extended Control Status
Register
AECSR1
RW
000564H
PPG6 - Timer register
000565H
PPG6 - Timer register
PR
EL
IM
SMR9
FME/EMDC- 2007-9-12
BGR9
PTMR6
RW
R
R
MB96340_DS_memory.fm
Specification
MB96340
I/O map (24 / 34)
Abbreviation
8-bit access
Address
Register
000566H
PPG6 - Period setting register
000567H
PPG6 - Period setting register
000568H
PPG6 - Duty cycle register
000569H
PPG6 - Duty cycle register
00056AH
PPG6 - Control status register
PCNL6
00056BH
PPG6 - Control status register
PCNH6
00056CH
PPG7 - Timer register
00056DH
PPG7 - Timer register
00056EH
PPG7 - Period setting register
00056FH
PPG7 - Period setting register
000570H
PPG7 - Duty cycle register
000571H
PPG7 - Duty cycle register
000572H
PPG7 - Control status register
000573H
PPG7 - Control status register
000574H
PPG11-PPG8 - General Control
register 1 Low
000575H
PPG11-PPG8 - General Control
register 1 High
GCN1H2
000576H
PPG11-PPG8 - General Control
register 2 Low
GCN2L2
000577H
PPG11-PPG8 - General Control
register 2 High
GCN2H2
000578H
PPG8 - Timer register
000579H
PPG8 - Timer register
00057AH
PPG8 - Period setting register
00057BH
PPG8 - Period setting register
00057CH
PPG8 - Duty cycle register
00057DH
PPG8 - Duty cycle register
00057EH
PPG8 - Control status register
PCNL8
00057FH
PPG8 - Control status register
PCNH8
000580H
PPG9 - Timer register
Abbreviation
32-bit access
Access
PCSR6
W
W
PDUT6
W
W
Y
PCN6
AR
PTMR7
IN
EL
IM
R
W
W
W
PCN7
PCNH7
GCN1L2
RW
W
PDUT7
PCNL7
RW
R
PCSR7
PR
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
RW
RW
GCN12
RW
RW
GCN22
RW
RW
PTMR8
R
R
PCSR8
W
W
PDUT8
W
W
PCN8
RW
RW
PTMR9
MB96340_DS_memory.fm
R
47
MB96340 Series
Specification
I/O map (25 / 34)
48
Abbreviation
8-bit access
Address
Register
000581H
PPG9 - Timer register
000582H
PPG9 - Period setting register
000583H
PPG9 - Period setting register
000584H
PPG9 - Duty cycle register
000585H
PPG9 - Duty cycle register
000586H
PPG9 - Control status register
PCNL9
000587H
PPG9 - Control status register
PCNH9
000588H
PPG10 - Timer register
000589H
PPG10 - Timer register
00058AH
PPG10 - Period setting register
00058BH
PPG10 - Period setting register
00058CH
PPG10 - Duty cycle register
00058DH
PPG10 - Duty cycle register
00058EH
PPG10 - Control status register
00058FH
PPG10 - Control status register
000590H
PPG11 - Timer register
000591H
PPG11 - Timer register
000592H
PPG11 - Period setting register
000593H
PPG11 - Period setting register
000594H
PPG11 - Duty cycle register
000595H
PPG11 - Duty cycle register
000596H
PPG11 - Control status register
PCNL11
000597H
PPG11 - Control status register
PCNH11
000598H
PPG15-PPG12 - General Control
register 1 Low
GCN1L3
000599H
PPG15-PPG12 - General Control
register 1 High
GCN1H3
00059AH
PPG15-PPG12 - General Control
register 2 Low
GCN2L3
00059BH
PPG15-PPG12 - General Control
register 2 High
GCN2H3
Abbreviation
32-bit access
Access
R
PCSR9
W
PDUT9
W
Y
W
W
AR
PCN9
PTMR10
IN
IM
PCNL10
RW
RW
R
R
PCSR10
PR
EL
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
W
W
PDUT10
W
W
PCN10
PCNH10
RW
RW
PTMR11
R
R
PCSR11
W
W
PDUT11
W
W
PCN11
RW
RW
GCN13
RW
RW
GCN23
RW
RW
MB96340_DS_memory.fm
Specification
MB96340
I/O map (26 / 34)
Abbreviation
8-bit access
Address
Register
00059CH
PPG12 - Timer register
00059DH
PPG12 - Timer register
00059EH
PPG12 - Period setting register
00059FH
PPG12 - Period setting register
0005A0H
PPG12 - Duty cycle register
0005A1H
PPG12 - Duty cycle register
0005A2H
PPG12 - Control status register
PCNL12
0005A3H
PPG12 - Control status register
PCNH12
0005A4H
PPG13 - Timer register
0005A5H
PPG13 - Timer register
0005A6H
PPG13 - Period setting register
0005A7H
PPG13 - Period setting register
0005A8H
PPG13 - Duty cycle register
0005A9H
PPG13 - Duty cycle register
0005AAH
PPG13 - Control status register
0005ABH
PPG13 - Control status register
0005ACH
PPG14 - Timer register
0005ADH
PPG14 - Timer register
0005AEH
PPG14 - Period setting register
0005AFH
PPG14 - Period setting register
0005B0H
PPG14 - Duty cycle register
0005B1H
PPG14 - Duty cycle register
0005B2H
PPG14 - Control status register
PCNL14
0005B3H
PPG14 - Control status register
PCNH14
0005B4H
PPG15 - Timer register
0005B5H
PPG15 - Timer register
0005B6H
PPG15 - Period setting register
0005B7H
PPG15 - Period setting register
0005B8H
PPG15 - Duty cycle register
0005B9H
PPG15 - Duty cycle register
Abbreviation
32-bit access
Access
PTMR12
R
R
PCSR12
W
W
Y
PDUT12
AR
PCN12
IN
W
RW
R
R
PCSR13
PCNL13
W
RW
PTMR13
EL
IM
PR
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
W
W
PDUT13
W
W
PCN13
PCNH13
RW
RW
PTMR14
R
R
PCSR14
W
W
PDUT14
W
W
PCN14
RW
RW
PTMR15
R
R
PCSR15
W
W
PDUT15
W
W
MB96340_DS_memory.fm
49
MB96340 Series
Specification
I/O map (27 / 34)
50
Abbreviation
8-bit access
Abbreviation
16-bit access
PPG15 - Control status register
PCNL15
PCN15
0005BBH
PPG15 - Control status register
PCNH15
0005BCH
0006DFH
Reserved
0006E0H
External bus Area configuration
register 0
EACL0
0006E1H
External bus Area configuration
register 0
EACH0
0006E2H
External bus Area configuration
register 1
0006E3H
External bus Area configuration
register 1
0006E4H
External bus Area configuration
register 2
0006E5H
External bus Area configuration
register 2
0006E6H
External bus Area configuration
register 3
EACL3
0006E7H
External bus Area configuration
register 3
EACH3
0006E8H
External bus Area configuration
register 4
EACL4
0006E9H
External bus Area configuration
register 4
EACH4
0006EAH
External bus Area configuration
register 5
EACL5
0006EBH
External bus Area configuration
register 5
EACH5
RW
0006ECH
External bus Area select register 2
EAS2
RW
0006EDH
External bus Area select register 3
EAS3
RW
0006EEH
External bus Area select register 4
EAS4
RW
0006EFH
External bus Area select register 5
EAS5
RW
0006F0H
External bus Mode register
EBM
RW
0006F1H
External bus Clock and Function
register
EBCF
RW
EACL1
Access
EACL2
RW
Y
RW
EAC0
EAC1
EACH1
PR
EL
FME/EMDC- 2007-9-12
Abbreviation
32-bit access
AR
0005BAH
IN
Register
IM
Address
RW
RW
RW
RW
EAC2
EACH2
RW
RW
EAC3
RW
RW
EAC4
RW
RW
EAC5
MB96340_DS_memory.fm
RW
Specification
MB96340
I/O map (28 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Abbreviation
32-bit access
Access
Register
0006F2H
External bus Address output enable
register 0
EBAE0
RW
0006F3H
External bus Address output enable
register 1
EBAE1
RW
0006F4H
External bus Address output enable
register 2
EBAE2
RW
0006F5H
External bus Control signal register
EBCS
0006F6H
0006FFH
Reserved
000700H
CAN0 - Control register
CTRLRL0
000701H
CAN0 - Control register
CTRLRH0
000702H
CAN0 - Status register
STATRL0
000703H
CAN0 - Status register
000704H
CAN0 - Error Counter (Transmit)
000705H
CAN0 - Error Counter (Receive)
000706H
CAN0 - Bit Timing Register
000707H
CAN0 - Bit Timing Register
BTRH0
000708H
CAN0 - Interrupt Register
INTRL0
000709H
CAN0 - Interrupt Register
INTRH0
00070AH
CAN0 - Test Register
TESTRL0
00070BH
CAN0 - Test Register
TESTRH0
00070CH
CAN0 - BRP Extension register
BRPERL0
00070DH
CAN0 - BRP Extension register
BRPERH0
00070EH
00070FH
Reserved
000710H
CAN0 - IF1 Command request register
IF1CREQL0
000711H
CAN0 - IF1 Command request register
IF1CREQH0
000712H
CAN0 - IF1 Command Mask register
IF1CMSKL0
000713H
CAN0 - IF1 Command Mask register
IF1CMSKH0
000714H
CAN0 - IF1 Mask Register
IF1MSK1L0
000715H
CAN0 - IF1 Mask Register
IF1MSK1H0
IN
AR
RW
CTRLR0
RW
R
STATR0
RW
STATRH0
ERRCNTL0
R
ERRCNT0
R
ERRCNTH0
BTRL0
EL
IM
PR
FME/EMDC- 2007-9-12
Y
Address
R
BTR0
RW
RW
INTR0
R
R
TESTR0
RW
R
BRPER0
RW
R
IF1CREQ0
RW
RW
IF1CMSK0
RW
R
IF1MSK10
IF1MSK0
RW
RW
MB96340_DS_memory.fm
51
MB96340 Series
Specification
I/O map (29 / 34)
52
Abbreviation
8-bit access
Abbreviation
16-bit access
CAN0 - IF1 Mask Register
IF1MSK2L0
IF1MSK20
000717H
CAN0 - IF1 Mask Register
IF1MSK2H0
000718H
CAN0 - IF1 Arbitration register
IF1ARB1L0
000719H
CAN0 - IF1 Arbitration register
IF1ARB1H0
00071AH
CAN0 - IF1 Arbitration register
IF1ARB2L0
00071BH
CAN0 - IF1 Arbitration register
IF1ARB2H0
00071CH
CAN0 - IF1 Message Control Register
IF1MCTRL0
00071DH
CAN0 - IF1 Message Control Register
IF1MCTRH0
00071EH
CAN0 - IF1 Data A1
IF1DTA1L0
00071FH
CAN0 - IF1 Data A1
IF1DTA1H0
000720H
CAN0 - IF1 Data A2
IF1DTA2L0
000721H
CAN0 - IF1 Data A2
000722H
CAN0 - IF1 Data B1
000723H
CAN0 - IF1 Data B1
000724H
CAN0 - IF1 Data B2
000725H
CAN0 - IF1 Data B2
000726H
00073FH
Reserved
000740H
CAN0 - IF2 Command request register
IF2CREQL0
000741H
CAN0 - IF2 Command request register
IF2CREQH0
000742H
CAN0 - IF2 Command Mask register
IF2CMSKL0
000743H
CAN0 - IF2 Command Mask register
IF2CMSKH0
000744H
CAN0 - IF2 Mask Register
IF2MSK1L0
000745H
CAN0 - IF2 Mask Register
IF2MSK1H0
000746H
CAN0 - IF2 Mask Register
IF2MSK2L0
000747H
CAN0 - IF2 Mask Register
IF2MSK2H0
000748H
CAN0 - IF2 Arbitration register
IF2ARB1L0
000749H
CAN0 - IF2 Arbitration register
IF2ARB1H0
00074AH
CAN0 - IF2 Arbitration register
IF2ARB2L0
00074BH
CAN0 - IF2 Arbitration register
IF2ARB2H0
FME/EMDC- 2007-9-12
Abbreviation
32-bit access
Access
RW
RW
IF1ARB10
1F1ARB0
RW
Y
IF1ARB20
RW
IF1MCTR0
RW
RW
IF1DTA10
IF1DTA0
IF1DTA20
RW
RW
IF1DTB10
IF1DTB0
IF1DTB1H0
IF1DTB2L0
RW
RW
IF1DTA2H0
IF1DTB1L0
RW
RW
AR
IN
000716H
IM
Register
PR
EL
Address
RW
RW
IF1DTB20
RW
IF1DTB2H0
RW
IF2CREQ0
RW
RW
IF2CMSK0
RW
R
IF2MSK10
IF2MSK0
RW
RW
IF2MSK20
RW
RW
IF2ARB10
IF2ARB0
RW
RW
IF2ARB20
RW
RW
MB96340_DS_memory.fm
Specification
MB96340
I/O map (30 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
CAN0 - IF2 Message Control Register
IF2MCTRL0
IF2MCTR0
00074DH
CAN0 - IF2 Message Control Register
IF2MCTRH0
00074EH
CAN0 - IF2 Data A1
IF2DTA1L0
00074FH
CAN0 - IF2 Data A1
IF2DTA1H0
000750H
CAN0 - IF2 Data A2
IF2DTA2L0
000751H
CAN0 - IF2 Data A2
IF2DTA2H0
000752H
CAN0 - IF2 Data B1
IF2DTB1L0
000753H
CAN0 - IF2 Data B1
IF2DTB1H0
000754H
CAN0 - IF2 Data B2
IF2DTB2L0
000755H
CAN0 - IF2 Data B2
IF2DTB2H0
000756H
000779H
Reserved
000780H
CAN0 - Transmission Request
Register
000781H
CAN0 - Transmission Request
Register
000782H
CAN0 - Transmission Request
Register
TREQR2L0
000783H
CAN0 - Transmission Request
Register
TREQR2H0
000784H
00078FH
Reserved
000790H
CAN0 - New Data Register
000791H
CAN0 - New Data Register
NEWDT1H0
000792H
CAN0 - New Data Register
NEWDT2L0
000793H
CAN0 - New Data Register
NEWDT2H0
000794H
00079FH
Reserved
0007A0H
CAN0 - Interrupt Pending Register
INTPND1L0
0007A1H
CAN0 - Interrupt Pending Register
INTPND1H0
0007A2H
CAN0 - Interrupt Pending Register
INTPND2L0
FME/EMDC- 2007-9-12
TREQR1L0
Abbreviation
32-bit access
Access
RW
RW
IF2DTA10
IF2DTA0
Y
IF2DTA20
IF2DTB10
RW
RW
IF2DTB0
RW
RW
IF2DTB20
RW
RW
TREQR10
TREQR0
TREQR1H0
NEWDT1L0
RW
RW
AR
IN
00074CH
EL
IM
Register
PR
Address
R
R
TREQR20
R
R
NEWDT10
NEWDT0
R
R
NEWDT20
R
R
INTPND10
INTPND0
R
R
INTPND20
MB96340_DS_memory.fm
R
53
MB96340 Series
Specification
I/O map (31 / 34)
54
Address
Register
Abbreviation
8-bit access
0007A3H
CAN0 - Interrupt Pending Register
INTPND2H0
0007A4H
0007AFH
Reserved
0007B0H
CAN0 - Message Valid Register
MSGVAL1L0
0007B1H
CAN0 - Message Valid Register
MSGVAL1H0
0007B2H
CAN0 - Message Valid Register
MSGVAL2L0
0007B3H
CAN0 - Message Valid Register
MSGVAL2H0
R
0007B4H
0007CDH
Reserved
0007CEH
CAN0 - Output enable register
COER0
RW
0007CFH
0007FFH
Reserved
000800H
CAN1 - Control register
000801H
CAN1 - Control register
000802H
CAN1 - Status register
000803H
CAN1 - Status register
000804H
CAN1 - Error Counter (Transmit)
000805H
CAN1 - Error Counter (Receive)
000806H
CAN1 - Bit Timing Register
BTRL1
000807H
CAN1 - Bit Timing Register
BTRH1
000808H
CAN1 - Interrupt Register
INTRL1
000809H
CAN1 - Interrupt Register
INTRH1
00080AH
CAN1 - Test Register
TESTRL1
00080BH
CAN1 - Test Register
TESTRH1
00080CH
CAN1 - BRP Extension register
BRPERL1
00080DH
CAN1 - BRP Extension register
BRPERH1
00080EH
00080FH
Reserved
000810H
CAN1 - IF1 Command request register
Abbreviation
32-bit access
Access
R
MSGVAL0
Y
MSGVAL10
MSGVAL20
AR
IN
CTRLRL1
CTRLR1
CTRLRH1
IM
PR
EL
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
STATRL1
STATR1
R
RW
RW
R
ERRCNT1
ERRCNTH1
IF1CREQL1
R
R
STATRH1
ERRCNTL1
R
R
R
BTR1
RW
RW
INTR1
R
R
TESTR1
RW
R
BRPER1
RW
R
IF1CREQ1
MB96340_DS_memory.fm
RW
Specification
MB96340
Address
Register
Abbreviation
8-bit access
000811H
CAN1 - IF1 Command request register
IF1CREQH1
000812H
CAN1 - IF1 Command Mask register
IF1CMSKL1
000813H
CAN1 - IF1 Command Mask register
IF1CMSKH1
000814H
CAN1 - IF1 Mask Register
IF1MSK1L1
000815H
CAN1 - IF1 Mask Register
IF1MSK1H1
000816H
CAN1 - IF1 Mask Register
IF1MSK2L1
000817H
CAN1 - IF1 Mask Register
IF1MSK2H1
000818H
CAN1 - IF1 Arbitration register
IF1ARB1L1
000819H
CAN1 - IF1 Arbitration register
IF1ARB1H1
00081AH
CAN1 - IF1 Arbitration register
IF1ARB2L1
00081BH
CAN1 - IF1 Arbitration register
IF1ARB2H1
00081CH
CAN1 - IF1 Message Control Register
IF1MCTRL1
IF1MCTR1
00081DH
CAN1 - IF1 Message Control Register
IF1MCTRH1
00081EH
CAN1 - IF1 Data A1
00081FH
CAN1 - IF1 Data A1
IN
I/O map (32 / 34)
000820H
CAN1 - IF1 Data A2
IF1DTA2L1
IF1DTA21
000821H
CAN1 - IF1 Data A2
IF1DTA2H1
000822H
CAN1 - IF1 Data B1
IF1DTB1L1
000823H
CAN1 - IF1 Data B1
IF1DTB1H1
000824H
CAN1 - IF1 Data B2
IF1DTB2L1
000825H
CAN1 - IF1 Data B2
IF1DTB2H1
000826H
00083FH
Reserved
000840H
CAN1 - IF2 Command request register
IF2CREQL1
000841H
CAN1 - IF2 Command request register
IF2CREQH1
000842H
CAN1 - IF2 Command Mask register
IF2CMSKL1
000843H
CAN1 - IF2 Command Mask register
IF2CMSKH1
000844H
CAN1 - IF2 Mask Register
IF2MSK1L1
000845H
CAN1 - IF2 Mask Register
IF2MSK1H1
000846H
CAN1 - IF2 Mask Register
IF2MSK2L1
Abbreviation
32-bit access
Access
RW
IF1CMSK1
RW
R
Y
IF1MSK11
IF1MSK21
AR
IF1DTA1L1
IF1ARB11
RW
RW
RW
RW
RW
RW
IF1ARB21
RW
RW
RW
RW
IF1DTA11
IF1DTA1H1
EL
IM
PR
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
RW
RW
RW
RW
IF1DTB11
RW
RW
IF1DTB21
RW
RW
IF2CREQ1
RW
RW
IF2CMSK1
RW
R
IF2MSK11
RW
RW
IF2MSK21
MB96340_DS_memory.fm
RW
55
MB96340 Series
Specification
I/O map (33 / 34)
56
Abbreviation
8-bit access
000847H
CAN1 - IF2 Mask Register
IF2MSK2H1
000848H
CAN1 - IF2 Arbitration register
IF2ARB1L1
000849H
CAN1 - IF2 Arbitration register
IF2ARB1H1
00084AH
CAN1 - IF2 Arbitration register
IF2ARB2L1
00084BH
CAN1 - IF2 Arbitration register
IF2ARB2H1
00084CH
CAN1 - IF2 Message Control Register
IF2MCTRL1
00084DH
CAN1 - IF2 Message Control Register
IF2MCTRH1
00084EH
CAN1 - IF2 Data A1
IF2DTA1L1
00084FH
CAN1 - IF2 Data A1
IF2DTA1H1
000850H
CAN1 - IF2 Data A2
IF2DTA2L1
000851H
CAN1 - IF2 Data A2
IF2DTA2H1
000852H
CAN1 - IF2 Data B1
000853H
CAN1 - IF2 Data B1
000854H
CAN1 - IF2 Data B2
000855H
CAN1 - IF2 Data B2
000856H
00087FH
Reserved
000880H
CAN1 - Transmission Request
Register
TREQR1L1
000881H
CAN1 - Transmission Request
Register
TREQR1H1
000882H
CAN1 - Transmission Request
Register
TREQR2L1
000883H
CAN1 - Transmission Request
Register
TREQR2H1
000890H
CAN1 - New Data Register
NEWDT1L1
000891H
CAN1 - New Data Register
NEWDT1H1
000892H
CAN1 - New Data Register
NEWDT2L1
000893H
CAN1 - New Data Register
NEWDT2H1
000894H
00089FH
Reserved
Abbreviation
32-bit access
Access
RW
IF2ARB11
RW
RW
IF2ARB21
IF2MCTR1
RW
RW
RW
RW
IF2DTB1L1
RW
IN
RW
IF2DTA11
IF2DTA21
IF2DTB11
RW
RW
IF2DTB21
IM
IF2DTB2L1
RW
RW
IF2DTB1H1
PR
EL
FME/EMDC- 2007-9-12
Abbreviation
16-bit access
Y
Register
AR
Address
IF2DTB2H1
RW
RW
TREQR11
R
R
TREQR21
R
R
NEWDT11
R
R
NEWDT21
R
R
MB96340_DS_memory.fm
Specification
MB96340
I/O map (34 / 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
CAN1 - Interrupt Pending Register
INTPND1L1
INTPND11
0008A1H
CAN1 - Interrupt Pending Register
INTPND1H1
0008A2H
CAN1 - Interrupt Pending Register
INTPND2L1
0008A3H
CAN1 - Interrupt Pending Register
INTPND2H1
0008B0H
CAN1 - Message Valid Register
MSGVAL1L1
0008B1H
CAN1 - Message Valid Register
MSGVAL1H1
0008B2H
CAN1 - Message Valid Register
MSGVAL2L1
0008B3H
CAN1 - Message Valid Register
MSGVAL2H1
R
0008CEH
CAN1 - Output enable register
COER1
RW
000C00H
External bus area (16-bit address up to
000FFFH)
EXTBUS1
RW
001000H
External bus area (Remaining RAM
AREA)
EXTBUS1
RW
Access
R
R
INTPND21
R
R
Y
MSGVAL11
MSGVAL21
AR
0008A0H
Abbreviation
32-bit access
IN
Register
R
R
R
PR
EL
IM
Address
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
57
MB96340 Series
Specification
■ INTERRUPT VECTOR TABLE
Interrupt vector table (1 / 4)
58
Vector name
Cleared
by DMA
Index in
ICR to
program
0
3FC
CALLV0
No
-
1
3F8
CALLV1
No
-
2
3F4
CALLV2
No
-
3
3F0
CALLV3
No
-
4
3EC
CALLV4
No
5
3E8
CALLV5
No
6
3E4
CALLV6
No
7
3E0
CALLV7
No
8
3DC
RESET
No
9
3D8
INT9
10
3D4
EXCEPTION
11
3D0
NMI
12
3CC
DLY
13
3C8
14
3C4
15
3C0
SC_TIMER
16
3BC
17
Description
Y
Offset in
vector table
AR
Vector
number
-
IN
-
-
No
-
No
-
No
12
Delayed Interrupt
RC_TIMER
No
13
RC Timer
MC_TIMER
No
14
Main Clock Timer
No
15
Sub Clock Timer
RESERVED
No
16
Reserved
3B8
EXTINT0
Yes
17
External Interrupt 0
18
3B4
EXTINT1
Yes
18
External Interrupt 1
19
3B0
EXTINT2
Yes
19
External Interrupt 2
20
3AC
EXTINT3
Yes
20
External Interrupt 3
21
3A8
EXTINT4
Yes
21
External Interrupt 4
22
3A4
EXTINT5
Yes
22
External Interrupt 5
23
3A0
EXTINT6
Yes
23
External Interrupt 6
24
39C
EXTINT7
Yes
24
External Interrupt 7
25
398
EXTINT8
Yes
25
External Interrupt 8
26
394
EXTINT9
Yes
26
External Interrupt 9
PR
EL
IM
No
FME/EMDC- 2007-9-12
Non-Maskable Interrupt
MB96340_DS_memory.fm
Specification
MB96340
Vector
number
Offset in
vector table
Vector name
Cleared
by DMA
Index in
ICR to
program
27
390
EXTINT10
Yes
27
External Interrupt 10
28
38C
EXTINT11
Yes
28
External Interrupt 11
29
388
EXTINT12
Yes
29
External Interrupt 12
30
384
EXTINT13
Yes
30
External Interrupt 13
31
380
EXTINT14
Yes
31
32
37C
EXTINT15
Yes
32
Y
Interrupt vector table (2 / 4)
33
378
CAN0
No
34
374
CAN1
No
35
370
PPG0
Yes
36
36C
PPG1
Yes
37
368
PPG2
Yes
38
364
PPG3
39
360
40
35C
41
358
42
354
43
350
44
34C
45
Description
External Interrupt 14
AR
External Interrupt 15
CAN Controller 0
34
CAN Controller 1
35
Programmable Pulse Generator 0
36
Programmable Pulse Generator 1
37
Programmable Pulse Generator 2
Yes
38
Programmable Pulse Generator 3
PPG4
Yes
39
Programmable Pulse Generator 4
PPG5
Yes
40
Programmable Pulse Generator 5
EL
IM
IN
33
Yes
41
Programmable Pulse Generator 6
PPG7
Yes
42
Programmable Pulse Generator 7
PPG8
Yes
43
Programmable Pulse Generator 8
PPG9
Yes
44
Programmable Pulse Generator 9
348
PPG10
Yes
45
Programmable Pulse Generator 10
46
344
PPG11
Yes
46
Programmable Pulse Generator 11
47
340
PPG12
Yes
47
Programmable Pulse Generator 12
48
33C
PPG13
Yes
48
Programmable Pulse Generator 13
49
338
PPG14
Yes
49
Programmable Pulse Generator 14
50
334
PPG15
Yes
50
Programmable Pulse Generator 15
51
330
RLT0
Yes
51
Reload Timer 0
52
32C
RLT1
Yes
52
Reload Timer 1
53
328
RLT2
Yes
53
Reload Timer 2
54
324
RLT3
Yes
54
Reload Timer 3
55
320
PPGRLT
Yes
55
Reload Timer 6 - dedicated for PPG
PR
PPG6
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
59
MB96340 Series
Specification
Interrupt vector table (3 / 4)
60
Vector
number
Offset in
vector table
Vector name
Cleared
by DMA
Index in
ICR to
program
56
31C
ICU0
Yes
56
Input Capture Unit 0
57
318
ICU1
Yes
57
Input Capture Unit 1
58
314
ICU2
Yes
58
Input Capture Unit 2
59
310
ICU3
Yes
59
Input Capture Unit 3
60
30C
ICU4
Yes
60
61
308
ICU5
Yes
61
62
304
ICU6
Yes
63
300
ICU7
Yes
64
2FC
OCU0
Yes
65
2F8
OCU1
Yes
66
2F4
OCU2
Yes
67
2F0
OCU3
68
2EC
69
Y
Description
Input Capture Unit 4
Input Capture Unit 6
63
Input Capture Unit 7
64
Output Compare Unit 0
65
Output Compare Unit 1
66
Output Compare Unit 2
Yes
67
Output Compare Unit 3
OCU4
Yes
68
Output Compare Unit 4
2E8
OCU5
Yes
69
Output Compare Unit 5
70
2E4
OCU6
Yes
70
Output Compare Unit 6
71
2E0
OCU7
Yes
71
Output Compare Unit 7
72
2DC
FRT0
Yes
72
Free Running Timer 0
73
2D8
FRT1
Yes
73
Free Running Timer 1
74
2D4
IIC0
Yes
74
I2C interface
75
2D0
IIC1
Yes
75
I2C interface
76
2CC
ADC0
Yes
76
A/D Converter
77
2C8
ALARM0
No
77
Alarm Comparator 0
78
2C4
ALARM1
No
78
Alarm Comparator 1
79
2C0
LINR0
Yes
79
LIN USART 0 RX
80
2BC
LINT0
Yes
80
LIN USART 0 TX
81
2B8
LINR1
Yes
81
LIN USART 1 RX
82
2B4
LINT1
Yes
82
LIN USART 1 TX
83
2B0
LINR2
Yes
83
LIN USART 2 RX
84
2AC
LINT2
Yes
84
LIN USART 2 TX
PR
EL
IM
62
IN
AR
Input Capture Unit 5
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
Interrupt vector table (4 / 4)
Vector
number
Offset in
vector table
Vector name
Cleared
by DMA
Index in
ICR to
program
85
2A8
LINR3
Yes
85
LIN USART 3 RX
86
2A4
LINT3
Yes
86
LIN USART 3 TX
87
2A0
MAIN_FLASH
No
87
Main Flash memory
88
29C
SAT_FLASH
No
88
Satellite Flash memory
(only MB96F348H/T)
89
298
LINR7
Yes
89
90
294
LINT7
Yes
91
290
LINR8
Yes
92
28C
LINT8
Yes
93
288
LINR9
94
284
95
280
96
27C
Y
AR
LIN USART 7 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
LIN USART 7 TX
(not available on MB96F348TSA/HSA/
TWA/HWA)
91
LIN USART 8 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
IN
90
LIN USART 8 TX
(not available on MB96F348TSA/HSA/
TWA/HWA)
Yes
93
LIN USART 9 RX
(not available on MB96F348TSA/HSA/
TWA/HWA)
LINT9
Yes
94
LIN USART 9 TX
(not available on MB96F348TSA/HSA/
TWA/HWA)
RTC0
No
95
Real Timer Clock
(not available on MB96F348TSA/HSA/
TWA/HWA)
CAL0
No
96
Clock Calibration Unit
(not available on MB96F348TSA/HSA/
TWA/HWA)
EL
IM
92
PR
FME/EMDC- 2007-9-12
Description
MB96340_DS_memory.fm
61
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
62
FME/EMDC- 2007-9-12
MB96340_DS_memory.fm
Specification
MB96340
■ HANDLING DEVICES
Special care is required for the following when handling the device:
Latch-up prevention
Treatment of unused pins
External clock
Precautions for when not using a sub clock signal
Notes on PLL clock mode operation
Power supply pins (VCC/VSS)
Crystal Oscillator Circuit
Turn on Sequence of Power Supply to A/D Converter and Analog Inputs
Connection of Unused Pins of A/D Converter
Notes on Energization
Stabilization of power supply voltage
Y
•
•
•
•
•
•
•
•
•
•
•
AR
1. Preventing latch-up
• CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
IN
• Latch-up may increase the power supply current drastically, causing thermal damage to the device.
• For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the
digital power-supply voltage.
2. Treatment of unused pins
EL
IM
• Unused input pins may be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
• Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. Therefore they must be pulled up or pulled down through resistors. To prevent latchup, those resistors should be more than 2 kΩ.
• Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
• To use external clock, drive the X0 pin and leave X1 pin open.
4. Precautions for when not using a sub clock signal
PR
• If you do not connect pins X0A and X1A to an oscillator, use a pull-down resistor on the X0A pin, and leave
the X1A pin open.
5. Notes on PLL clock mode operation
• If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the freely oscillating PLL. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the same for all
VSS-level power supply pins. If there are more than one VCC or VSS systems, the device may operate
incorrectly even within the guaranteed operating range.
• Connect VCC and VSS to the device from the power supply with lowest possible impedance.
FME/EMDC- 2007-9-12
MB96300_DS_handling.fm
51
MB96340 Series
Specification
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor
between VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal Oscillator Circuit
• Noise at X0 or X1 pins may possibly cause abnormal operation. Make sure to provide bypass capacitors with
shortest distance to X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to
the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
• It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
Y
• It is highly recommended to evaluate the quartz/MCU system at the quartz manufacturer.
8. Turn on Sequence of Power Supply to A/D Converter and Analog Inputs
AR
• Make sure to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
• Turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, make sure
that the voltage does not exceed AVRH or AVCC (turning the analog and digital power supplies
simultaneously on or off is acceptable).
9. Connection of Unused Pins of A/D Converter
10. Notes on Energization
IN
• Connect unused pins of A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
• To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply
on should be slower than 50µs from 0.2 V to 2.7 V.
IM
11. Stabilization of power supply voltage
PR
EL
• If the power supply voltage varies acutely even within the operation assurance range of the Vcc power supply
voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization
guidelines, stabilize the power supply voltage so that Vcc ripple fluctuations (peak to peak value) in the
commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
52
FME/EMDC- 2007-9-12
MB96300_DS_handling.fm
Specification
MB96340
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage
Rating
Unit
Remarks
Min
Max
VCC
VSS - 0.3
VSS + 6.0
V
AVCC
VSS - 0.3
VSS + 6.0
V
VCC = AVCC *1
AVRH, AVRL VSS - 0.3
VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
VI
VSS - 0.3
VSS + 6.0
V
VI ≤ VCC + 0.3V
Output voltage
VO
VSS - 0.3
VSS + 6.0
V
VO ≤ VCC + 0.3V *2
ICLAMP
-4.0
+4.0
mA
Applicable to general purpose
I/O pins *3
Σ|ICLAMP|
-
40
mA
Applicable to general purpose
I/O pins *3
-
15
mA
Normal outputs for normal drive
output port setting
-
5
mA
Normal outputs for normal drive
output port setting
-
100
mA
Normal outputs for normal drive
output port setting
-
50
mA
Normal outputs for normal drive
output port setting
IOH1
-
-15
mA
Normal outputs for normal drive
output port setting
“H” level average output current
IOHAV1
-
-5
mA
Normal outputs for normal drive
output port setting
“H” level maximum overall output current
ΣIOH1
-
-100
mA
Normal outputs for normal drive
output port setting
“H” level average overall output current
ΣIOHAV1
-
-50
mA
Normal outputs for normal drive
output port setting
PD
-
600
mW
0
+70
“L” level maximum output current
IOL1
“L” level average output current
IOLAV1
“L” level maximum overall output current
ΣIOL1
“H” level maximum output current
Power consumption
PR
Operating temperature
ΣIOLAV1
EL
IM
“L” level average overall output current
AR
Total Maximum Clamp Current
IN
Maximum Clamp Current
TA
Y
Input voltage
-40
+125
*4
*2
MB96V300B
o
C
Operating temperature at Flash erase/
write
TAF
-40
+105
o
C
Storage temperature
TSTG
-55
+150
o
C
others
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum
current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI
rating. Input/output voltages of standard ports depend on VCC.
FME/EMDC- 2007-9-12
MB96300_DS_el_abs_max_rat.fm
53
MB96340 Series
Specification
AR
Y
*3: • Applicable to all general purpose I/O pins (Pnn_m)
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistant low voltage
reset in internal vector mode).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
IN
N-ch
R
IM
+B input (0V to 16V)
P-ch
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
*
54
If used exceeding TA = +105˚C, be sure to contact Fujitsu for reliability limitations.
PR
EL
*4
FME/EMDC- 2007-9-12
MB96300_DS_el_abs_max_rat.fm
Specification
MB96340
2. Recommended Conditions
Parameter
Symbol
Value
Unit
Min
Typ
Max
Vcc, DVcc
3.0
-
5.5
V
Smoothing capacitor at C
pin
CS
4.7
-
10
µF
Operating temperature
TA
0
-
+70
-40
-
+125*1
o
Use a X7R Ceramic Capacitor
MB96V300B
C
Y
Power supply voltage
Remarks
others
AR
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the devices electrical characteristics are warranted when the device is operated
within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside
these ranges may adversely affect reliability and could result in device failure.
IN
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
PR
EL
IM
*1: If used exceeding TA = +105˚C, be sure to contact Fujitsu for reliability limitations.
FME/EMDC- 2007-9-12
MB96300_DS_el_rec_cond.fm
55
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
56
FME/EMDC- 2007-9-12
MB96300_DS_el_rec_cond.fm
Specification
MB96340
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Symbol
Pin
Condition
Remarks
Max
-
Port inputs if
CMOS Hysteresis
0.8/0.2 input is
selected
0.8
VCC
-
VCC +
0.3
V
-
Port inputs if
CMOS Hysteresis
0.7/0.3 input is
selected
0.7
VCC
-
VCC +
0.3
V
-
Port inputs if AUTOMOTIVE Hysteresis input is selected
0.8
VCC
-
VCC +
0.3
V
-
Port inputs if TTL
input is selected
2.0
-
VCC +
0.3
V
VIHR
RSTX
-
0.8
VCC
-
VCC +
0.3
V
RSTX input pin
(CMOS Hysteresis)
VIHM
MD2-MD0
-
VCC 0.3
-
VCC +
0.3
V
MDx input pins
VIHX0S
X0,X0A
-
2.5
-
VCC +
0.3
V
External clock in “Oscillation mode”
External clock in
“Fast Clock Input
mode” (Not available
in MB96V300,
MB96F34xY/R/A)
AR
Y
Typ
EL
IM
Input “H” voltage
X0
-
0.8
VCC
-
VCC +
0.3
V
-
Port inputs if
CMOS Hysteresis
0.8/0.2 input is
selected
VSS 0.3
-
0.2
VCC
V
-
Port inputs if
CMOS Hysteresis
0.7/0.3 input is
selected
VSS 0.3
-
0.3
VCC
V
-
Port inputs if AUTOMOTIVE Hys- VSS teresis input is se- 0.3
lected
-
0.5
VCC
V
-
Port inputs if TTL
input is selected
VSS 0.3
-
0.8
V
VILR
RSTX
-
VSS 0.3
-
0.2 VCC
V
RSTX input pin
(CMOS Hysteresis)
VILM
MD2-MD0
-
VSS 0.3
-
VSS +
0.3
V
MDx input pins
VILX0S
X0, X0A
-
VSS 0.3
-
0.5
V
External clock in “Oscillation mode”
VIHX0F
PR
VIL
Input “L” voltage
Unit
Min
VIH
Input “H” voltage
Value
IN
Parameter
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
57
MB96340 Series
Specification
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
VILX0F
Pin
Condition
X0
-
Value
Min
Typ
VSS 0.3
-
VCC 0.5
-
Unit
Remarks
V
External clock in
“Fast Clock Input
mode” (Not available
in MB96V300,
MB96F34xY/R/A)
-
V
Driving strength set
to 2mA
Driving strength set
to 5mA
Max
0.2 VCC
VOH2
Normal
outputs
IOH = -2mA
3.0V ≤ VCC < 4.5V
Y
4.5V ≤ VCC ≤ 5.5V
IOH = -1.6mA
Output “H” voltage
VOH5
Normal
outputs
AR
4.5V ≤ VCC ≤ 5.5V
IOH = -5mA
3.0V ≤ VCC < 4.5V
VCC 0.5
-
-
V
VCC 0.5
-
-
V
-
-
0.4
V
Driving strength set
to 2mA
-
-
0.4
V
Driving strength set
to 5mA
-
-
0.4
V
-1
-
+1
µA
25
50
100
kΩ
IOH = -3mA
4.5V ≤ VCC ≤ 5.5V
VOH3
I2C outputs
IOH = -3mA
3.0V ≤ VCC < 4.5V
IN
Output “H” voltage
IOH = -2mA
4.5V ≤ VCC ≤ 5.5V
Normal
outputs
IOL = +2mA
3.0V ≤ VCC < 4.5V
IM
VOL2
IOL = +1.6mA
Output “L” voltage
4.5V ≤ VCC ≤ 5.5V
Normal
outputs
IOL = +5mA
3.0V ≤ VCC < 4.5V
PR
EL
VOL5
IOL = +3mA
4.5V ≤ VCC ≤ 5.5V
Output “L” voltage
VOL3
I2C outputs
IOL = +3mA
3.0V ≤ VCC < 4.5V
IOL = +2mA
Input leak current
Pull-up resistance
IIL
Pnn_m
RUP
Pnn_m,
RSTX
VCC = 5.5V
VSS < VI < VCC
-
Note: Input/output voltages of ports depend on VCC.
58
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
Specification
MB96340
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Symbol
Value
Condition
Typ
Max
PLL Run mode with
CLKS1/2 = 56MHz =
CLKB = CLKP1, CLKP2
= 28MHz
44
57
45
60
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
25
34
ICCRCH
AR
26
37
125˚C
4.5
5.5
25˚C
PR
ICCRCL
RC Run mode with
CLKS1/2 = CLKB =
CLKP1 /2 = 100kHz, SMCR:LPMS=1
ICCSUB
5.1
8.5
125˚C
2.9
4
25˚C
3.5
6.5
125˚C
0.4
0.6
25˚C
mA
0.9
3.5
125˚C
0.15
0.25
25˚C
mA
0.65
3.2
125˚C
0.1
0.2
25˚C
mA
0.6
FME/EMDC- 2007-9-12
CLKMC, CLKPLL and
CLKSC stopped
mA
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
3
CLKRC and CLKSC
stopped. Core voltage at
1.9V
CLKPLL, CLKSC and
CLKRC stopped
mA
RC Run mode with
CLKS1=CLKS2=CLKB
= CLKP1/2 = 2MHz
RC Run mode with
CLKS1/2 = CLKB =
CLKP1 /2 = 100kHz, SMCR:LPMS=0
Power supply current in Run
modes*
25˚C
mA
EL
IM
Power supply current in Run
modes*
CLKRC and CLKSC
stopped. Core voltage at
1.9V
125˚C
IN
ICCMAIN
Remarks
25˚C
mA
ICCPLL
Main Run mode with
CLKS1/2=CLKB =
CLKP1/2 = 4MHz
temp
Unit
Y
Parameter
125˚C
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in high
power mode
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing
allowed.
CLKMC, CLKPLL and
CLKRC stopped, no
Flash programming/
erasing allowed.
MB96300_DS_el_DC_char.fm
59
MB96340 Series
Parameter
Symbol
Specification
Value
Condition
Typ
Max
9
10.5
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
9.7
13
14
15.5
Y
25˚C
AR
18
125˚C
1.5
1.8
25˚C
CLKRC and CLKSC
stopped.
CLKPLL CLKRC and
CLKSC stopped
mA
2
4.5
125˚C
0.8
1.3
25˚C
CLKMC, CLKPLL and
CLKSC stopped
mA
1.4
4
125˚C
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz, SMCR:LPMSS=0
0.3
0.5
25˚C
0.8
3.4
125˚C
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz, SMCR:LPMSS=1
0.06
0.15
25˚C
PR
EL
ICCSRCH
125˚C
14.8
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
IM
Power supply current in Sleep
modes*
CLKRC and CLKSC
stopped.
mA
IN
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
Remarks
25˚C
mA
ICCSPLL
PLL Sleep mode with
CLKS1/2 = CLKP1 =
56MHz, CLKP2 =
28MHz
temp
Unit
mA
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in high
power mode
ICCSRCL
Power supply current in Sleep
modes*
ICCSSUB
mA
0.56
3
125˚C
0.04
0.12
25˚C
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
60
FME/EMDC- 2007-9-12
CLKMC, CLKPLL and
CLKRC stopped
mA
0.54
2.9
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in low power mode
125˚C
MB96300_DS_el_DC_char.fm
Specification
Value
Condition
ICCTPLL
PLL Timer mode with
CLKMC = 4MHz, CLKPLL = 56MHz
Main Timer mode with
CLKMC = 4MHz, SMCR:LPMSS=0
ICCTMAIN
Max
1.6
2
2.1
4.8
0.35
0.5
ICCTRCH
125˚C
25˚C
0.85
3.3
125˚C
0.1
0.15
25˚C
mA
0.6
2.9
125˚C
0.35
0.5
25˚C
mA
0.85
3.3
125˚C
0.1
0.15
25˚C
RC Timer mode with
CLKRC = 2MHz, SMCR:LPMSS=1
PR
CLKRC and CLKSC
stopped. Core voltage at
1.9V
mA
RC Timer mode with
CLKRC = 2MHz, SMCR:LPMSS=0
mA
0.6
2.9
125˚C
0.3
0.45
25˚C
RC Timer mode with
CLKRC = 100kHz, SMCR:LPMSS=0
Remarks
25˚C
mA
EL
IM
Power supply current in Timer
modes*
temp
Unit
IN
Main Timer mode with
CLKMC = 4MHz, SMCR:LPMSS=1
Typ
Y
Symbol
AR
Parameter
MB96340
CLKPLL, CLKRC and
CLKSC stopped. Voltage regulator in high
power mode
CLKPLL, CLKRC and
CLKSC stopped. Voltage regulator in low power mode
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in high
power mode
CLKMC, CLKPLL and
CLKSC stopped. Voltage regulator in low power mode
CLKMC, CLKPLL and
CLKSC stopped. Voltage in high power mode
mA
0.8
3.2
125˚C
0.05
0.1
25˚C
ICCTRCL
RC Timer mode with
CLKRC = 100kHz, SMCR:LPMSS=1
0.55
FME/EMDC- 2007-9-12
CLKMC, CLKPLL and
CLKSC stopped. Voltage in low power mode
mA
2.8
125˚C
MB96300_DS_el_DC_char.fm
61
MB96340 Series
Power supply current in Timer
modes*
Symbol
ICCTSUB
Value
Condition
ICCCLOMO
Flash Write/Erase
current
ICCFLASH
Input capacitance
CIN
0.1
0.53
2.8
0.02
0.08
0.52
2.8
0.015
0.06
0.4
2.3
70
100
Clock modulator enabled (CMCR:PDX = ‘1’)
-
CLKMC, CLKPLL and
CLKRC stopped
125˚C
25˚C
mA
125˚C
AR
70
100
3
4
3
4
15
40
15
40
5
15
Remarks
25˚C
mA
25˚C
125˚C
mA
mA
Core voltage at 1.8V
Core voltage at 1.2V
25˚C
This current must be
added to all Power supply currents above
µA
IN
Clock modulator
current
Low voltage detector enabled (RCR:LVDE=’1’)
IM
ICCLVD
0.03
temp
Unit
mA
ICCH
VRCR:LPMB[2:0] =
“000”
Power supply current for active Low
Voltage detector
Max
Sub Timer mode with
CLKSC = 32kHz
VRCR:LPMB[2:0] =
“110”
Stop Mode
Typ
Y
Parameter
Specification
125˚C
25˚C
125˚C
25˚C
125˚C
Must be added to all current above
Must be added to all current above
pF
PR
EL
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a
32kHz external clock connected to the Sub oscillator. See chapter 10 of the Harware Manual for further details
about voltage regulator control.
62
FME/EMDC- 2007-9-12
MB96300_DS_el_DC_char.fm
Specification
MB96340
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
X0, X1
Clock frequency
fFCI
X0
Clock frequency
fCL
X0A, X1A
Clock frequency
fCR
Value
Max
3
-
16
MHz When using an oscillation circuit, PLL off
3.5
-
16
MHz When using an oscillation circuit, PLL on
0
-
4
MHz When using an external clock, PLL off
3.5
-
4
MHz When using an external clock, PLL on
0
-
56
When using an external clock in “Fast
MHz Clock Input mode” (not available in
MB96V300, MB96F34xY/R/A)
32
32.768
0
-
50
100
1
2
100
kHz When using an oscillation circuit
100
kHz When using an external clock
200
kHz
When using slow frequency of RC oscillator
4
MHz
When using fast frequency of RC oscillator
-
200
MHz
VCO output frequency of PLL
(CLKVCO)
-
-
ns
-
-
50
Input clock pulse
width
PWH, PWL
X0
8
Input clock pulse
width
PWHL, PWLL
Input clock rise
and fall time
tCR, tCF
EL
IM
fCLKVCO
X0A
5
-
-
µs
X0
-
-
5
ns
PR
Remarks
Typ
Clock frequency
X0
Unit
Min
Y
fC
Pin
AR
Clock frequency
Symbol
IN
Parameter
PWH
Duty ratio is about 30% to 70%
When using external clock
tCYL
VIH
VIL
PWL
tCR
tCF
tCYLL
VIH
X0A
VIL
PWHL
PWLL
tCF
FME/EMDC- 2007-9-12
tCR
MB96300_DS_el_AC_src_clk.fm
63
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
64
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_src_clk.fm
Specification
MB96340
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Core Voltage Settings
Symbol
1.8V
1.9V
Unit
Min
Max
Min
Max
0
92
0
96
MHz
0
68
0
74
MHz
56
MHz
32
MHz
fCLKS1, fCLKS2
Internal CPU clock frequency (CLKB), internal peripheral clock frequency
(CLKP1)
fCLKB, fCLKP1
0
52
0
Internal peripheral clock frequency (Clock CLKP2)
fCLKP2
0
28
0
MB96F34xY/R
PR
EL
IM
IN
AR
Internal System clock frequency (CLKS1 and
CLKS2)
Remarks
Y
Parameter
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_int_clk.fm
65
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
66
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_int_clk.fm
Specification
MB96340
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Reset input time
Value
Symbol
Pin
tRSTL
RSTX
Min
Typ
Max
500
-
-
Unit
Remarks
ns
tRSTL
Y
RSTX
0.2 VCC
PR
EL
IM
IN
AR
0.2 VCC
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_rst.fm
67
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
68
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_rst.fm
Specification
MB96340
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Power on rise time
Power off time
Symbol
Pin
tR
tOFF
Value
Min
Typ
Max
Vcc
0.05
-
30
Vcc
1
-
-
Unit
Remarks
ms
ms Due to repetitive operation
2.7V
VCC
0.2 V
0.2 V
AR
0.2 V
Y
tR
tOFF
IN
If you change the power supply too rapidly, a power-on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However if voltage drops are below 1 V/s, you can
operate while using the PLL clock.
EL
IM
VCC
Rising edge of 50 mV/ms
maximum is allowed
PR
3V
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_pon_rst.fm
69
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
70
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_pon_rst.fm
Specification
MB96340
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter Symbol
Pin
Condition
Min
Max
INTn
NMI
tINH
tINL
ns
Used Pin input function
External Interrupt
NMI
Pnn_m
General Purpose IO
TINn
Reload Timer
TTGn
Y
Input pulse
width
200
Unit
tCLKP1 + 200
ADTG
(tCLKP1=1/fCLKP1)
ns
AR
FRCKn
INn
PPG Trigger input
AD Converter Trigger
Free Running Timer
external clock
Input Capture
External Pin input
VIH
IN
Note : Relocated Resource Inputs have same characteristics
VIH
tINL
PR
EL
IM
tINH
VIL
VIL
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_inpt.fm
71
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
72
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_inpt.fm
Specification
MB96340
External Bus timing
Basic Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Symbol
Pin
Condition
Max
25
ns
tCYC/2-5
tCYC/2+5
ns
tCLCH
tCYC/2-5
tCYC/2+5
ns
tCHCBH
tCHCBL
tCLCBH
ECLK
CSn, UBX,
LBX,ECLK
tCLCBL
tCHLH
tCHLL
ECLK → ALE time
tCLLH
ALE, ECLK
ECLK → address valid time
tCHAV
tCLAV
tCLADV
tCHADV
tCHRWL
tCLRWH
-20
20
ns
-20
20
ns
-20
20
ns
-10
10
ns
-10
10
ns
-10
10
ns
-10
10
ns
-15
15
ns
-15
15
ns
-15
15
ns
-15
15
ns
-10
10
ns
-10
10
ns
-10
10
ns
-10
10
ns
A[23:16],ECLK
AD[15:0],ECLK
tCHRWH
ECLK → RDX /WRX time
ns
EL
IM
ECLK → address valid time
20
IN
tCLLL
-20
AR
tCHCL
ECLK →
UBX/ LBX / CSn time
Unit
Min
tCYC
ECLK
Value
RDX, WRX,
WRLX,WRHX,
ECLK
tCLRWL
Y
Parameter
Remarks
if CLKB duty cycle is 50%
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Parameter
Symbol
Pin
30
ns
tCYC/2-8
tCYC/2+8
ns
tCLCH
tCYC/2-8
tCYC/2+8
ns
tCHCBH
-25
25
ns
-25
25
ns
-25
25
ns
-25
25
ns
tCHCL
tCHCBL
tCLCBH
tCLCBL
FME/EMDC- 2007-9-12
Unit
Max
PR
ECLK →
UBX/ LBX / CSn time
Value
Min
tCYC
ECLK
Condition
ECLK
CSn, UBX,
LBX,ECLK
Remarks
if CLKB duty cycle is 50%
MB96300_DS_el_AC_ext_bus.fm
81
MB96340 Series
Symbol
Pin
Condition
tCHLH
tCHLL
ECLK → ALE time
ALE, ECLK
tCLLH
tCLLL
tCHAV
A[23:16],ECLK
tCLAV
tCLADV
ECLK → address valid time
AD[15:0],ECLK
tCHADV
ECLK → RDX /WRX time
RDX, WRX,
WRLX, WRHX,
ECLK
tCHRWL
tCLRWH
tCYC
tCLCH
0.8*Vcc
ECLK
tCHAV
tCHCBL
LBX
15
ns
-15
15
ns
-15
15
ns
-15
15
ns
-20
20
ns
-20
20
ns
-20
20
ns
-20
20
ns
-15
15
ns
-15
15
ns
-15
15
ns
-15
15
ns
Remarks
tCLAV
tCLCBH
PR
EL
CSn
-15
IM
0.2*Vcc
A[23:16]
IN
tCLRWL
tCHCL
Max
tCHRWH
Unit
Min
AR
ECLK → address valid time
Value
Y
Parameter
Specification
tCLCBL
tCHCBH
tCLRWL
tCHRWH
UBX
tCHRWL
RDX
tCLRWH
WRX (WRLX, WRHX)
tCLLH
ALE
tCHLL
tCLLL
tCHADV
tCLADV
AD[15:0]
tCHLH
Address
Refer to the Hardware Manual for detailed Timing Charts.
82
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF
Value
SymPin
Conditions
Unit Remarks
bol
Min
Max
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
tLHLL ALE
ns
tCYC − 5
ns
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 5
ns
EACL:STS=0 and
EACL:ACE=0
tCYC − 15
ns
EACL:STS=1 and
3tCYC/2 − 15
EACL:ACE=0
ns
EACL:STS=0 and
EACL:ACE=1
ns
EACL:STS=1 and
5tCYC/2 − 15
EACL:ACE=1
ns
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 15
ns
EACL:STS=1 and
EACL:ACE=0
tCYC − 15
ns
EACL:STS=0 and
3tCYC/2 − 15
EACL:ACE=1
ns
EACL:STS=1 and
EACL:ACE=1
2tCYC − 15
ns
EACL:STS=0
tCYC/2 − 15
ns
EACL:STS=1
-15
ns
EACL:ACE=0
3tCYC/2 − 15
ns
EACL:ACE=1
5tCYC/2 − 15
ns
EACL:ACE=0
tCYC − 15
ns
EACL:ACE=1
2tCYC − 15
ns
EACL:ACE=0
3tCYC − 55
ns
EACL:ACE=1
4tCYC − 55
ns
EACL:ACE=0
5tCYC/2 − 55 ns
EACL:ACE=1
7tCYC/2 − 55 ns
EACL:STS=1
2tCYC − 15
Valid address
⇒ ALE ↓ time
tADVLL ALE,AD[15 :0]
tLLAX ALE, AD[15 :0]
Valid address
⇒ RDX ↓ time
tAVRL
Valid address
⇒ RDX ↓ time
tADVRL RDX,AD[15 :0]
Valid address
⇒ Valid data input
tAVDV
Valid address
⇒ Valid data input
tADVDV AD[15 :0]
EL
IM
ALE ↓
⇒ Address valid time
IN
AR
tAVLL ALE, A[23:16],
tCYC/2 − 5
Y
Bus Timing (Read)
MB96340
RDX, A[23:16]
PR
A[23:16],
AD[15;0]
3 tCYC/2 − 5
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
RDX ↑ ⇒ Data hold time
0
ns
0
ns
EACL:STS=1 and
3tCYC/2 − 10
EACL:ACE=1
ns
other ECL:STS,
tCYC/2 − 10
EACL:ACE setting
ns
RDX pulse width
tRLRH RDX
tRHDX RDX, AD[15:0]
Address valid ⇒ Data hold
A[23:16],
tAXDX
time
AD[15:0]
RDX ↑ ⇒ ALE ↑ time
FME/EMDC- 2007-9-12
tRHLH RDX, ALE
w/o cycle
extension
w/o cycle
extension;
ns
w/o cycle
extension
3 tCYC/2 − 50 ns
w/o cycle
extension
MB96300_DS_el_AC_ext_bus.fm
83
MB96340 Series
Parameter
Specification
Symbol
Pin
Conditions
Min
Max
Unit Remarks
Valid address
⇒ ECLK ↑ time
tAVCH A[23:16], ECLK
tCYC − 15
ns
tADVCH AD[15:0], ECLK
tCYC/2 − 15
ns
RDX ↓ ⇒ ECLK ↑ time
tRLCH RDX, CLK
tCYC/2 − 10
ns
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
EACL:STS=0
tCYC/2 − 10
ns
EACL:STS=1
− 10
ns
ECLK↑ ⇒ Valid data input
tCHDV AD[15:0], ECLK
tCYC − 50
ns
Y
(TA = −40 °C to +125 °C, VCC = , VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
SymPin
Conditions
Unit Remarks
bol
Min
Max
AR
Parameter
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
tLHLL ALE
tCYC/2 − 8
ns
tCYC − 8
ns
3tCYC/2 − 8
ns
tCYC − 20
ns
EACL:STS=1 and
3tCYC/2 − 20
EACL:ACE=0
ns
EACL:STS=0 and
EACL:ACE=1
ns
EACL:STS=1 and
5tCYC/2 − 20
EACL:ACE=1
ns
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 20
ns
EACL:STS=1 and
EACL:ACE=0
tCYC − 20
ns
EACL:STS=0 and
3tCYC/2 − 20
EACL:ACE=1
ns
EACL:STS=1 and
EACL:ACE=1
2tCYC − 20
ns
EACL:STS=0
tCYC/2 − 20
ns
EACL:STS=1
-20
ns
EACL:ACE=0
3tCYC/2 − 20
ns
EACL:ACE=1
5tCYC/2 − 20
ns
EACL:ACE=0
tCYC − 20
ns
EACL:ACE=1
2tCYC − 20
ns
EACL:ACE=0
3tCYC − 60
ns
EACL:ACE=1
4tCYC − 60
ns
EACL:ACE=0
5tCYC/2 − 60 ns
EACL:ACE=1
7tCYC/2 − 60 ns
EACL:STS=1
IN
EACL:STS=0 and
EACL:ACE=1
EACL:STS=0 and
EACL:ACE=0
IM
tAVLL ALE, A[23:16],
PR
EL
Valid address
⇒ ALE ↓ time
tADVLL ALE,AD[15 :0]
ALE ↓
⇒ Address valid time
tLLAX ALE, AD[15 :0]
Valid address
⇒ RDX ↓ time
tAVRL
Valid address
⇒ RDX ↓ time
84
Value
RDX, A[23:16]
tADVRL RDX,AD[15 :0]
Valid address
⇒ Valid data input
tAVDV
Valid address
⇒ Valid data input
tADVDV AD[15 :0]
RDX pulse width
tRLRH RDX
FME/EMDC- 2007-9-12
A[23:16],
AD[15;0]
2tCYC − 20
3tCYC/2 − 8
ns
w/o cycle
extension
w/o cycle
extension;
w/o cycle
extension
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
Symbol
Parameter
Pin
Value
Conditions
Min
Unit Remarks
Max
RDX ↑ ⇒ Data hold time
0
ns
0
ns
EACL:STS=1 and
3tCYC/2 − 15
EACL:ACE=1
ns
other ECL:STS,
tCYC/2 − 15
EACL:ACE setting
ns
tCYC − 20
ns
tCYC/2 − 20
ns
tRHDX RDX, AD[15:0]
Address valid ⇒ Data hold
tAXDX A[23:16]
time
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
tAVCH A[23:16], ECLK
tADVCH AD[15:0], ECLK
RDX ↓ ⇒ ECLK ↑ time
tRLCH RDX, CLK
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
ECLK↑ ⇒ Valid data input
tCHDV AD[15:0], ECLK
tCYC/2 − 15
ns
EACL:STS=0
tCYC/2 − 15
ns
EACL:STS=1
− 15
ns
tCYC − 55
ns
IN
tAVCH
tRLCH
tADVCH
0.8*Vcc
ECLK
AR
Valid address
⇒ ECLK ↑ time
tLLAX
tADVLL
ALE
w/o cycle
extension
tCHDV
EL
IM
tAVLL
3tCYC/2 − 55 ns
Y
RDX ↓ ⇒ Valid data input tRLDV RDX, AD[15:0]
tRHLH
0.2*Vcc
tLHLL
tAVRL
tADVRL
RDX
tRLRH
A[23:16]
AD[15:0]
PR
tLLRL
tRLDV
tAXDX
tAVDV
tRHDX
tADVDV
Address
VIH
VIL
VIH
Read data
VIL
Refer to the Hardware Manual for detailed Timing Charts.
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
85
MB96340 Series
Parameter
Valid address
⇒ WRX ↓ time
tAVWL
WRX, WRLX,
WRHX,
A[23:16]
EACL:ACE=0
3tCYC/2 −
15
ns
EACL:ACE=1
5tCYC/2 −
15
ns
WRX, WRLX,
WRHX,
AD[15:0]
EACL:ACE=0
tCYC − 15
ns
EACL:ACE=1
2tCYC − 15
ns
Valid address
⇒ WRX ↓ time
tADVWL
WRX pulse width
tWLWH
WRX, WRXL,
WRHX
Valid data output
⇒ WRX ↑ time
tDVWH
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
⇒ Data hold time
tWHDX
WRX, WRLX,
WRHX,
AD[15:0]
WRX ↑
⇒ Address valid time
tWHAX
WRX, WRLX,
WRHX,
A[23:16]
tWHLH
WRX, WRLX,
WRHX, ALE
WRX ⇒ CSn time
WRX ⇒ CSn time
Parameter
Valid address
⇒ WRX ↓ time
Valid address
⇒ WRX ↓ time
tWLCH
ns
w/o cycle
extension
tCYC − 20
ns
w/o cycle
extension
tCYC/2 − 15
ns
tCYC/2 − 15
ns
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE and
EACL:STS setting
2tCYC − 10
ns
tCYC − 10
ns
tCYC/2 − 10
ns
3tCYC/2 −
15
ns
EACL:ACE=1
5tCYC/2 −
15
ns
EACL:STS=0
tCYC/2 − 15
ns
WRX, WRLX,
WRHX, ECLK
WRX, WRLX,
WRHX, CSn
tCSLWL
tWHCSH
Symbol
tAVWL
tADVWL
FME/EMDC- 2007-9-12
WRX, WRLX,
WRHX, CSn
tCYC − 5
AR
IN
EACL:STS=0
EACL:ACE=0
PR
EL
WRX ↓ ⇒ ECLK ↑
time
IM
WRX ↑ ⇒ ALE ↑ time
86
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
Max
Y
Bus Timing (Write)
Specification
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Value
Pin
Condition
Unit
Remarks
Min
Max
WRX, WRLX,
WRHX,
A[23:16]
EACL:ACE=0
3tCYC/2 −
20
ns
EACL:ACE=1
5tCYC/2 −
20
ns
WRX, WRLX,
WRHX,
AD[15:0]
EACL:ACE=0
tCYC − 20
EACL:ACE=1
2tCYC − 20
MB96300_DS_el_AC_ext_bus.fm
Specification
Parameter
MB96340
Symbol
Pin
Value
Condition
Min
Max
Unit
Remarks
tWLWH
WRX, WRLX,
WRHX
tCYC − 8
ns
w/o cycle
extension
Valid data output
⇒ WRX ↑ time
tDVWH
WRX, WRLX,
WRHX,
AD[15:0]
tCYC − 25
ns
w/o cycle
extension
WRX ↑
⇒ Data hold time
tWHDX
WRX, WRLX,
WRHX,
AD[15:0]
tCYC/2 − 20
ns
WRX ↑
⇒ Address valid time
tWHAX
WRX, WRLX,
WRHX,
A[23:16]
EACL:STS=0
tWHLH
WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE and
EACL:STS setting
tWLCH
WRX, WRLX,
WRHX, ECLK
tCSLWL
WRX, WRLX,
WRHX, CSn
CSn ⇒ WRX time
tWHCSH
WRX, WRLX,
WRHX, CSn
2tCYC − 15
ns
tCYC − 15
ns
tCYC/2 − 15
ns
EACL:ACE=0
3tCYC/2 −
20
ns
EACL:ACE=1
5tCYC/2 −
20
ns
EACL:STS=0
tCYC/2 − 20
ns
AR
ns
PR
WRX ⇒ CSn time
tCYC/2 − 20
IN
WRX ↓ ⇒ ECLK ↑
time
EL
IM
WRX ↑ ⇒ ALE ↑ time
Y
WRX pulse width
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
87
MB96340 Series
Specification
tWLCH
0.8*Vcc
ECLK
tWHLH
ALE
tWLWH
tADVWL
WRX (WRLX, WRHX)
AR
0.2*Vcc
Y
tAVWL
tCSLWL
A[23:16]
IN
CSn
tWHCSH
tWHAX
tDVWH
AD[15:0]
PR
EL
Ready Input Timing
Parameter
RDY setup time
RDY hold time
Parameter
RDY setup time
RDY hold time
IM
Address
tWHDX
Write data
Refer to the Hardware Manual for detailed Timing Charts.
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Rated Value
SymTest
Pin
Units
Remarks
bol
Condition
Min
Max
tRYHS
RDY
tRYHH
RDY
35
ns
0
ns
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,CL=50pF)
Rated Value
SymTest
Pin
Units
Remarks
bol
Condition
Min
Max
tRYHS
RDY
tRYHH
RDY
45
ns
0
ns
Note : If the RDY setup time is insufficient, use the auto-ready function.
88
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
MB96340
0.8*Vcc
ECLK
RDY
When WAIT is used.
tRYHH
VIH
VIH
Y
RDY
When WAIT is not used.
tRYHS
AR
VIL
Refer to the Hardware Manual for detailed Timing Charts.
Hold Timing
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive=5mA,Cl=50pF)
Value
Symbol
Pin
Condition
Units Remarks
Min
Max
tXHAL
HAKX
HAKX ↑ time ⇒ Pin valid time
tHAHV
HAKX
Pin floating ⇒ HAKX ↓ time
HAKX ↑ time ⇒ Pin valid time
HAKX
tCYC − 20 tCYC + 20
ns
tCYC − 20 tCYC + 20
ns
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive=5mA,Cl=50pF)
Value
Symbol
Pin
Condition
Units Remarks
Min
Max
EL
IM
Parameter
IN
Pin floating ⇒ HAKX ↓ time
tXHAL
HAKX
tHAHV
HAKX
tCYC − 25 tCYC + 25
ns
tCYC − 25 tCYC + 25
ns
0.8*Vcc
0.2*Vcc
tHAHV
Each pin
PR
tXHAL
FME/EMDC- 2007-9-12
0.8*Vcc
High-Z
0.2*Vcc
Refer to the Hardware Manual for detailed Timing Charts.
MB96300_DS_el_AC_ext_bus.fm
89
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
90
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_ext_bus.fm
Specification
USART timing
Parameter
MB96340
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V, IOdrive=5mA, CL=50pF)
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Symbol
Pin
Condition
Unit
Min
Max
Min
Max
tSCYCI
SCKn
4 tCLKP1
4 tCLKP1
ns
SCK ↓ → SOT delay
time
tSLOVI
SCKn,
SOTn
-20
+20
-30
+30
ns
SOT → SCK ↑ delay
time
tOVSHI
SCKn,
SOTn
N*tCLKP1
- 20 *1
N*tCLKP1 30 *1
Valid SIN → SCK ↑
tIVSHI
SCKn,
SINn
tCLKP1 +
45
tCLKP1 +
55
ns
SCK ↑ → Valid SIN
hold time
tSHIXI
SCKn,
SINn
0
0
ns
Serial clock “L” pulse
width
tSLSHE
SCKn
tCLKP1 +
10
tCLKP1 +
10
ns
Serial clock “H” pulse
width
tSHSLE
SCKn
tCLKP1 +
10
tCLKP1 +
10
ns
SCK ↓ → SOT delay
time
tSLOVE
SCKn,
SOTn
2 tCLKP1
+ 45
2 tCLKP1
+ 55
ns
Valid SIN → SCK ↑
tIVSHE
SCKn,
SINn
tCLKP1/2
+ 10
tCLKP1/2 +
10
ns
SCK ↑ → Valid SIN
hold time
tSHIXE
SCKn,
SINn
tCLKP1 +
10
tCLKP1 +
10
ns
SCKn
20
20
ns
SCKn
20
20
ns
tFE
SCK rise time
tRE
AR
IN
External Shift
Clock Mode
EL
IM
SCK fall time
Internal Shift
Clock Mode
Y
Serial clock cycle time
Notes: • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
PR
*1: Parameter N depends on tSCYCI and can be calculated as:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
FME/EMDC- 2007-9-12
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
3
7*tCLKP1, 8*tCLKP1
4
...
...
MB96300_DS_el_AC_usart.fm
73
MB96340 Series
Specification
tSCYCI
SCK for
ESCR:SCES = 0
0.8*Vcc
SCK for
ESCR:SCES = 1
0.2*Vcc
0.2*Vcc
0.8*Vcc
0.8*Vcc
0.2*Vcc
tSLOVI
0.8*Vcc
SOT
0.2*Vcc
AR
tSHIXI
tIVSHI
VIH
SIN
VIL
Y
tOVSHI
VIH
VIL
IN
Internal Shift Clock Mode
SCK for
ESCR:SCES = 0
VIH
VIL
VIL
VIH
VIH
PR
EL
SCK for
ESCR:SCES = 1
IM
tSLSHE
VIL
tFE
SOT
SIN
tSLOVE
tSHSLE
VIH
VIH
VIL
VIL
tRE
0.8*Vcc
0.2*Vcc
tIVSHE
tSHIXE
VIH
VIH
VIL
VIL
External Shift Clock Mode
74
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_usart.fm
Specification
MB96340
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC= 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
0.6
µs
“L” width of the SCL clock
tLOW
4.7
1.3
µs
“H” width of the SCL clock
tHIGH
4.0
0.6
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
Data hold time
SCL↓→SDA↓↑
tHDDAT
Data set-up time
SDA↓↑→SCL↑
tSUDAT
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
Bus free time between a STOP and START
condition
tBUS
R = 1.7 kΩ,
C = 50 pF*1
4.7
0.6
µs
0
3.45*2
0
0.9*3
µs
250
100
ns
4.0
0.6
µs
4.7
1.3
µs
AR
Hold time (repeated) START condition
SDA↓→SCL↓
IN
SCL clock frequency
Y
Min
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
EL
IM
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
SDA
tSUDAT
tLOW
tHDSTA
PR
SCL
tHDDAT
FME/EMDC- 2007-9-12
tHIGH
tSUSTA
tBUS
tHDSTA
tSUSTO
MB96300_DS_el_AC_i2c.fm
95
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
96
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_i2c.fm
Specification
MB96340
5. Analogue Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
-
-
-
-
10
bit
Total error
-
-
-3
-
+3
LSB
Nonlinearity error
-
-
-2.5
-
+2.5
LSB
Differential nonlinearity error
-
-
-1.9
-
+1.9
LSB
VOT
ANn
AVRL 1.5
AVRL+
0.5
VFST
ANn
AVRH 3.5
AVRH - AVRH +
LSB
1.5
0.5
Compare time
-
-
Sampling time
-
-
Analog port input current
IAIN
ANn
Analog input voltage
range
VAIN
ANn
Reference voltage
range
Power supply current
Offset between input
channels
2.0
0.5
1.2
-
16,500
µs
4.5V ≤ ΑVCC ≤ 5.5V
-
-
µs
3.0V ≤ ΑVCC < 4.5V
-
-
µs
4.5V ≤ ΑVCC ≤ 5.5V
-
-
µs
3.0V ≤ ΑVCC < 4.5V
-1
-
+1
µA TA = 25 ˚C
-3
-
+3
µA TA = 125 ˚C
AVRL
-
AVRH
V
AVRH
AVRH/
AVRH2
0.75
AVcc
-
AVcc
V
AVRL
AVRL
AVSS
-
0.25
AVCC
V
IA
AVcc
-
2.5
5
mA AC Converter active
AVcc
-
-
5
µA
AVRH/
AVRL
-
0.7
1
mA AC Converter active
AVRH/
AVRL
-
-
5
µA
ANn
-
-
TBD
LSB
IAH
IR
IRH
PR
Reference voltage current
1.0
AR
voltage
AVRL +
LSB
2.5
IN
Full scale reading
EL
IM
Zero reading voltage
Y
Resolution
-
AD Converter not
operated *1
AD Converter not
operated
*1: If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
Note : The accuracy gets worse as AVRH - AVRL becomes smaller.
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Non linearity error: Deviation between a line across zero-transition line ( “00 0000 0000” <--> “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” <--> “11 1111 1111” ) and actual conversion characteristics.
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
75
MB96340 Series
Specification
Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from
an ideal value.
Total error: Difference between an actual value and an ideal value. A total error includes zero transition error,
full-scale transition error, and linear error.
Zero reading voltage: Input voltage which results in the minimum conversion value.
Full scale reading voltage: Input voltage which results in the maximum conversion value.
Y
Total error
3FF
1.5 LSB
Actual conversion
characteristics
AR
3FE
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
002
001
IM
0.5 LSB
AVRL
IN
003
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
VOT (Ideal value) = AVRL + 0.5 LSB [V]
[LSB]
PR
EL
Total error of digital output “N” =
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
76
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
Specification
MB96340
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
VNT (actual
measurement value)
004
Actual conversion
characteristics
003
002
Ideal characteristics
N
N−1
N−2
001
VOT (actual measurement value)
AVRL
Actual conversion
characteristics
AR
VFST (actual
measurement
value)
Digital output
Digital output
3FD
N+1
Y
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
3FE
AVRH
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
Actual conversion
characteristics
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
IN
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
VFST − VOT
1022
EL
IM
1 LSB =
V (N+1) T − VNT
1 LSB
[LSB]
−1 LSB [LSB]
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
Notes on A/D Converter Section
• About the external impedance of the analog input and its sampling time
PR
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/
D conversion precision.
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
77
MB96340 Series
Specification
• Analog input circuit model:
R
Comparator
Analog input
C
Sampling switch
Y
Reference values:
• R = 2.6 kΩ (Max)
• C = 8.5 pF (Max)
AR
To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and
minimum sampling time and either adjust the resistor value and operating frequency or decrease the external
impedance so that the sampling time (Tsamp) is longer than the minimum value. Usually, this value is set to 7τ,
where τ = RC. If you include the external input resistance (Rext) connected to the analog input, the sampling time
is expressed:
Tsamp [min] = 7.(Rext + R).C
•
About the error
IN
If the sampling time cannot be sufficient, connect a capacitor of about 0.1 mF to the analog input pin.
PR
EL
IM
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
78
FME/EMDC- 2007-9-12
MB96300_DS_el_adc.fm
Specification
MB96340
6. Alarm Comparator
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Min
Typ
Power supply current
AVCC
IA5ALMS
IA5ALMH
Unit
Remarks
-
25
40
µA
Alarm comparator
enabled in fast
mode (one channel)
-
7
10
µA
Alarm comparator
enabled in slow
mode (one channel)
-
-
5
µA
Alarm comparator
disabled
-1
-
+1
µA TA = 25 ˚C
Y
IA5ALMF
Max
IALIN
ALARM pin input voltage range
VALIN
External low threshold
VEVTL
0.36 * AVCC
0.36 * AVCC
0.36 * AVCC
-5%
+5%
V
INTREF=0
External high threshold
VEVTH
ALARM0, 0.78 * AVCC
0.78 * AVCC
0.78 * AVCC
ALARM1
-3%
+3%
V
INTREF=0
Internal low threshold
VIVTL
Internal high threshold
VIVTH
Switching hysteresis
VHYS
-3
+3
-
AVCC
V
1.15
1.25
1.35
V
INTREF=1
2.45
2.55
2.65
V
INTREF=1
50
-
250
mV
EL
IM
Comparison time
µA TA = 125 ˚C
-
IN
0
AR
ALARM pin input current
tCOMPF
-
0.1
-
µs
CMD=1 (fast)
tCOMPS
-
-
100
µs
CMD=0 (slow)
Comparator
Output
PR
H
L
FME/EMDC- 2007-9-12
VEVTL, VEVTH
VIVTL, VIVTH
VALIN
VHYS
MB96300_DS_el_alarm.fm
101
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
102
FME/EMDC- 2007-9-12
MB96300_DS_el_alarm.fm
Specification
MB96340
7. LOW VOLTAGE DETECTOR CHARACTERISTICS
Max
Unit
-
75
100
µA
Level 0
VDL0
2.7
-
2.95
V
Level 1
VDL1
2.9
-
3.2
V
Level 2
VDL2
3.1
-
3.4
V
Level 3
VDL3
3.5
-
3.85
V
Level 4
VDL4
3.6
-
3.95
V
Level 5
VDL5
3.7
-
4.05
V
Level 6
VDL6
3.8
-
4.15
V
Level 7
VDL7
-
4.3
V
Level 8
VDL8
4.0
-
4.4
V
Level 9
VDL9
4.1
-
4.5
V
Level 10
VDL10
Level 11
VDL11
Level 12
VDL12
Level 13
VDL13
Level 14
VDL14
Level 15
VDL15
3.9
IN
VCC
Remarks
Not supported for this device
PR
EL
IM
Power consumptiont
AR
ICCLVD
Y
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin
Min
Typ
FME/EMDC- 2007-9-12
MB96300_DS_el_LVD_char.fm
105
MB96340
PR
EL
IM
IN
AR
Y
Specification
FME/EMDC- 2007-9-12
MB96300_DS_el_LVD_char.fm
106
Specification
MB96340
8. FLASH memory program/erase characteristics
(TA = 25oC, Vcc = 5.0V)
Value
Unit
Remarks
3.6
s
Erasure programming time not
included
n*0.9
n*3.6
s
n is the number of Flash sector
of the device
23
370
us
System overhead time not included
Programme/Erase cycle 10 000
cycle
100 000 cycles for Tj < 105 oC
Flash data retention time
year
*1
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
-
AR
20
Y
Parameter
PR
EL
IM
IN
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into into normalized value at 85oC))
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_Flash.fm
107
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
108
FME/EMDC- 2007-9-12
MB96300_DS_el_AC_Flash.fm
Specification
MB96340
■ EXAMPLE CHARACTERISTICS
The diagrams below show the characteristics of one measured sample of MB96F348HSB with typical process
parameters.
Run Mode
100.00
Y
PLL clock (56 MHz)
10.00
RC clock (100 kHz)
0.10
Sub osc.(32 kHz)
0.01
-50.00
0.00
AR
RC clock (2 MHz)
1.00
IN
Icc [mA]
Main osc. (4 MHz)
50.00
100.00
150.00
100.00
150.00
EL
IM
Ta [ºC]
Sleep mode
100.00
PLL clock (56 MHz)
Icc [mA]
10.00
Main osc. (4 MHz)
1.00
RC clock (2 MHz)
0.10
PR
RC clock (100 kHz)
Sub osc.(32 kHz)
0.01
-50.00
FME/EMDC- 2007-9-12
0.00
50.00
Ta [ºC]
MB96300_DS_el_example_char.fm
109
Specification
MB96340
Timer mode
10.00
PLL clock (56 MHz)
Icc [mA]
1.00
Y
Main osc. (4 MHz)
RC clock (2 MHz)
0.10
Sub osc. (32 kHz)
0.01
-50.00
0.00
AR
RC clock (100 kHz)
50.00
100.00
150.00
100.00
150.00
IN
Ta [ºC]
Stop mode
EL
IM
1.00
Icc [mA]
0.10
PR
0.01
0.00
-50.00
FME/EMDC- 2007-9-12
0.00
50.00
Ta [ºC]
MB96300_DS_el_example_char.fm
110
Specification
MB96340
Used settings
Sleep mode
Clock/Regulator Settings
CLKS1 = CLKS2 = CLKB = CLKP1 = 56 MHz
CLKP2 = 28 MHz
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2 MHz
Regulator in High Power Mode
Core Voltage = 1.8 V
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100 kHz
Regulator in High Power Mode
Core Voltage = 1.8 V
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32 kHz
Regulator in Low Power Mode A
Core Voltage = 1.8 V
PLL
CLKS1 = CLKS2 = CLKP1 = 56 MHz
CLKP2 = 28 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.9 V
Main osc.
AR
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2 MHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
PR
RC clock fast
Y
PLL
IN
Run mode
Selected Source
Clock
EL
IM
Mode
RC clock slow
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100 kHz
(CLKB is stopped in this mode)
Regulator in High Power Mode
Core Voltage = 1.8 V
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32 kHz
(CLKB is stopped in this mode)
Regulator in Low Power Mode A
Core Voltage = 1.8 V
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm
111
Specification
MB96340
Used settings
CLKMC = 4 MHz, CLKPLL = 56 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.9 V
Main osc.
CLKMC = 4 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
RC clock fast
CLKRC = 2 MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
RC clock slow
CLKRC = 100 kHz
(System clocks are stopped in this mode)
Regulator in High Power Mode, Core Voltage = 1.8 V
Sub osc.
CLKSC = 100 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode A, Core Voltage = 1.8 V
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode B
Y
PLL
PR
EL
IM
Stop mode
Clock/Regulator Settings
AR
Timer mode
Selected Source
Clock
IN
Mode
FME/EMDC- 2007-9-12
MB96300_DS_el_example_char.fm
112
Specification
MB96340
■ PACKAGE DIMENSION MB96(F)34x LQFP 100P
100-pin plastic LQFP
(FPT-100P-M20)
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Y
Package width ×
package length
Mounting height
1.70 mm Max
Weight
0.65 g
51
76
P-LFQFP100-14×14-0.50
IN
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
EL
IM
50
INDEX
0.08(.003)
Details of "A" part
+0.20
PR
1
0.50(.020)
2005 FUJITSU LIMITED F100031S-c-2-1
FME/EMDC- 2007-9-12
0.20±0.05
(.008±.002)
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
25
0.08(.003)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
26
100
C
0.50 mm
Code
(Reference)
(FPT-100P-M20)
75
Lead pitch
AR
100-pin plastic LQFP
M
0.145±0.055
(.0057±.0022)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB96340_DS_package.fm
113
MB96340 Series
Specification
■ PACKAGE DIMENSION MB96(F)34x QFP 100P
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Y
100-pin plastic QFP
AR
Mounting height
Code
(Reference)
(FPT-100P-M22)
(FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
P-QFP100-14×20-0.65
IN
100-pin plastic QFP
(FPT-100P-M22)
3.35 mm MAX
IM
50
0.10(.004)
17.90±0.40
(.705±.016)
PR
EL
*14.00±0.20
(.551±.008)
INDEX
100
1
C
114
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
30
0.65(.026)
"A"
Details of "A" part
2002 FUJITSU LIMITED F100008S-c-5-5
FME/EMDC- 2007-9-12
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB96340_DS_package.fm
Specification
MB96340
■ ORDERING INFORMATION
MCU with CAN controller
MB96F346YSA PQC-GSE2
MB96F346YWA PQC-GSE2
Yes
MB96F347YSA PQC-GSE2
No
MB96F347RSA PQC-GSE2
MB96F347YWA PQC-GSE2
No
MB96F348TSB PQC-GSE2
MB96F348HSB PQC-GSE2
MB96F348TWB PQC-GSE2
MB96F348HWB PQC-GSE2
MB96F348TSB PMC-GSE2
MB96F348HSB PMC-GSE2
Yes
No
Yes
Yes
No
MB96F348HWB PMC-GSE2
MB96V300BRB-ES
FME/EMDC- 2007-9-12
Emulated
by ext.
RAM
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Yes
No
100 pin Plastic LQFP
(FPT-100P-M20)
No
PR
MB96F348TWB PMC-GSE2
No
Yes
EL
IM
MB96F347RWA PMC-GSE2
Yes
100 pin Plastic QFP
(FPT-100P-M22)
100 pin Plastic QFP
(FPT-100P-M22)
Yes
MB96F347RSA PMC-GSE2
MB96F347YWA PMC-GSE2
No
No
MB96F346RWA PMC-GSE2
MB96F347YSA PMC-GSE2
Yes
No
MB96F346YWA PMC-GSE2
MB96F347RWA PQC-GSE2
No
Yes
MB96F346RSA PMC-GSE2
Yes
Yes
Remarks
AR
MB96F346YSA PMC-GSE2
Package
Yes
No
MB96F346RSA PQC-GSE2
MB96F346RWA PQC-GSE2
Persistant
Low Voltage Reset
Subclock
Y
Satellite
flash
memory
IN
Part number
No
Yes
No
Yes
No
Yes
No
Yes
100 pin Plastic QFP
(FPT-100P-M22)
No
Yes
No
Yes
100 pin Plastic LQFP
(FPT-100P-M20)
No
No
416 pin Plastic BGA For evalua(BGA416-M02)
tion
MB96340_DS_order.fm
115
MB96340 Series
Specification
MCU without CAN controller
Subclock
Package
No
100 pin Plastic QFP
(FPT-100P-M22)
MB96F346ASA PQC-GSE2
MB96F346AWA PQC-GSE2
MB96F346ASA PMC-GSE2
Yes
No
No
MB96F346AWA PMC-GSE2
Yes
MB96F347ASA PQC-GSE2
No
MB96F347AWA PQC-GSE2
MB96F347ASA PMC-GSE2
No
MB96F347AWA PMC-GSE2
Yes
MB96F348ASA PQC-GSE2
No
MB96F348ASA PMC-GSE2
Yes
100 pin Plastic LQFP
(FPT-100P-M20)
100 pin Plastic QFP
(FPT-100P-M22)
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Yes
100 pin Plastic QFP
(FPT-100P-M22)
100 pin Plastic LQFP
(FPT-100P-M20)
PR
EL
MB96F348CWB PMC-GSE2
No
IM
MB96F348CSB PMC-GSE2
No
Yes
MB96F348CSB PQC-GSE2
MB96F348CWB PQC-GSE2
Yes
No
MB96F348AWA PMC-GSE2
100 pin Plastic QFP
(FPT-100P-M22)
IN
MB96F348AWA PQC-GSE2
100 pin Plastic LQFP
(FPT-100P-M20)
Yes
No
Remarks
Y
Satellite
flash
memory
AR
Part number
116
FME/EMDC- 2007-9-12
MB96340_DS_order.fm
Specification
MB96340
■ REVISION HISTORY
Revision
Date
Modification
2007-05-07
Creation
2
2007-05-10
External bus hold timing update
3
2007-05-23
Electrical characteristics updates
4
2007-08-02
Electrical characteristics updates, Product lineup, changes and ordering
information
5
2007-09-12
Addition of the electrical charcateristic examples and the LVD
characteristics specifications, updates of the DC charcateristics. Pin circuit
type drawing modifications.
PR
EL
IM
IN
AR
Y
1
FME/EMDC- 2007-9-12
MB96340_DS_revisions.fm
117
Specification
PR
EL
IM
IN
AR
Y
MB96340 Series
118
FME/EMDC- 2007-9-12
MB96340_DS_revisions.fm