GeneSiC GA05JT06-CAL Off silicon carbide junction transistor Datasheet

Die Datasheet
GA05JT06-CAL
Normally – OFF Silicon Carbide
Junction Transistor
VDS
RDS(ON)
ID @ 25 oC
hFE
=
=
=
=
600 V
240 mΩ
15 A
110
Features








210°C maximum operating temperature
Gate Oxide Free SiC switch
Exceptional Safe Operating Area
Excellent Gain Linearity
Temperature Independent Switching Performance
Low Output Capacitance
Positive Temperature Co-efficient of RDS,ON
Suitable for connecting an anti-parallel diode
Die Size = 1.57 mm x 1.57 mm
Advantages
Applications














Compatible with Si MOSFET/IGBT gate-drivers
> 20 µs Short-Withstand Capability
Lowest-in-class Conduction Losses
High Circuit Efficiency
Minimal Input Signal Distortion
High Amplifier Bandwidth
Down Hole Oil Drilling, Geothermal Instrumentation
Hybrid Electric Vehicles (HEV)
Solar Inverters
Switched-Mode Power Supply (SMPS)
Power Factor Correction (PFC)
Induction Heating
Uninterruptible Power Supply (UPS)
Motor Drives
Absolute Maximum Ratings (TC = 25 oC unless otherwise specified)
Parameter
Drain – Source Voltage
Continuous Drain Current
Continuous Drain Current
Continuous Gate Current
Symbol
VDS
ID
ID
IG
Turn-Off Safe Operating Area
RBSOA
Short Circuit Safe Operating Area
SCSOA
Reverse Gate – Source Voltage
Reverse Drain – Source Voltage
Operating Junction and Storage
Temperature
Maximum Processing Temperature
Conditions
VGS = 0 V
TC = 25°C
TC > 125°C, assumes RthJC < 1.41 oC/W
TVJ = 210 oC,
Clamped Inductive Load
TVJ = 210 oC, IG = 0.2 A, VDS = 400 V,
Non Repetitive
Value
600
15
5
0.25
ID,max = 5
@ VDS ≤ VDSmax
Unit
V
A
A
A
A
> 20
µs
VSG
VSD
30
25
V
V
Tj, Tstg
-55 to 210
°C
325
°C
TProc
10 min. maximum
Notes
Electrical Characteristics
Parameter
Symbol
Conditions
Min.
Value
Typical
Max.
Unit
Notes
mΩ
Fig. 5
V
Fig. 4
–
Fig. 5
On State Characteristics
Drain – Source On Resistance
RDS(ON)
ID = 5 A, Tj = 25 °C
ID = 5 A, Tj = 125 °C
ID = 5 A, Tj = 175 °C
ID = 5 A, Tj = 210 °C
Gate – Source Saturation Voltage
VGS,SAT
ID = 5 A, ID/IG = 40, Tj = 25 °C
ID = 5 A, ID/IG = 30, Tj = 175 °C
hFE
VDS = 5 V, ID = 5 A, Tj = 25 °C
VDS = 5 V, ID = 5 A, Tj = 125 °C
VDS = 5 V, ID = 5 A, Tj = 175 °C
VDS = 5 V, ID = 5 A, Tj = 210 °C
Drain Leakage Current
IDSS
VR = 600 V, VGS = 0 V, Tj = 25 °C
VR = 600 V, VGS = 0 V, Tj = 125 °C
VR = 600 V, VGS = 0 V, Tj = 210 °C
Gate Leakage Current
ISG
VSG = 20 V, Tj = 25 °C
DC Current Gain
240
368
455
620
3.45
3.22
110
79
72
69
Off State Characteristics
Feb 2015
10
50
100
20
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
100
500
1000
nA
nA
Pg1 of 9
Die Datasheet
GA05JT06-CAL
Electrical Characteristics
Parameter
Symbol
Conditions
Ciss
Crss/Coss
EOSS
VGS = 0 V, VD = 300 V, f = 1 MHz
VD = 300 V, f = 1 MHz
VGS = 0 V, VD = 300 V, f = 1 MHz
Min.
Value
Typical
Max.
Unit
Notes
pF
pF
µJ
Fig. 7
Fig. 7
Fig. 8
Capacitance Characteristics
Input Capacitance
Reverse Transfer/Output Capacitance
Output Capacitance Stored Energy
527
24
1.1
Figures
Figure 1: Typical Output Characteristics at 25 °C
Figure 2: Typical Output Characteristics at 125 °C
Figure 3: Typical Output Characteristics at 210 °C
Figure 4: Typical Gate – Source Saturation Voltage
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg2 of 9
Die Datasheet
GA05JT06-CAL
Figure 5: Normalized On-Resistance and Current Gain vs.
Temperature
Figure 6: Typical Blocking Characteristics
Figure 7: Input, Output, and Reverse Transfer Capacitance
Figure 8: Output Capacitance Stored Energy
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg3 of 9
Die Datasheet
GA05JT06-CAL
Driving the GA05JT06-CAL
Drive Topology
TTL Logic
Constant Current
High Speed – Boost Capacitor
High Speed – Boost Inductor
Proportional
Pulsed Power
Gate Drive Power
Consumption
High
Medium
Medium
Low
Lowest
Medium
Switching
Frequency
Low
Medium
High
High
High
N/A
Application Emphasis
Availability
Wide Temperature Range
Wide Temperature Range
Fast Switching
Ultra Fast Switching
Wide Drain Current Range
Pulse Power
Coming Soon
Coming Soon
Production
Coming Soon
Coming Soon
Coming Soon
A: Static TTL Logic Driving
The GA05JT06-CAL may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must
meet or exceed the steady state gate current (IG,steady) required to operate the GA05JT06-CAL. The power level of the supply can be estimated
from the target duty cycle of the particular application. IG,steady is dependent on the anticipated drain current ID through the SJT and the DC
current gain hFE, it may be calculated from the following equation. An accurate value of the hFE may be read from Figure 5.
5V
SiC SJT
TTL
Gate Signal
D
G
5/0V
TTL i/p
IG,steady
S
Figure 9: TTL Gate Drive Schematic
B: High Speed Driving
The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate
current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 10 which features a positive
current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on.
Figure 10: An idealized gate current waveform for fast switching of an SJT.
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg4 of 9
Die Datasheet
GA05JT06-CAL
Ideally, IG,pon should terminate when the drain voltage falls to its on-state value in order to avoid unnecessary drive losses during the steady
on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the device package and drive circuit. A
voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain currents begin
to flow through the device. The voltage applied to the gate pin should be maintained high enough, above the V GS,sat (see Figure 4) level to
counter these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with V GS = 0 V, a negative gate voltage VGS may be used in
order to speed up the turn-off transition.
Two high-speed drive topologies for the SiC SJTs are presented below.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA05JT06-CAL may be driven using a High Speed, Low Loss Drive with Boost Capacitor topology in which multiple voltage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and lowside driving, its datasheet provides additional details about this drive topology.
C2
+12 V
GA03IDDJT30-FR4
Gate Driver Board
VGL
VCC High
U3
C5
VCC High RTN
CG1
VGL
VGH
Signal
R1
R2
U1
CG2
U5
R4
C9
VEE C6
Gate
Signal
VEE C10
VGL
VGL
R3
U2
VEE
VCC Low RTN
G
SiC SJT
RG2
S
C8
VGH
VCC Low
C1
U6
VEE
IG
RG1
D1
Signal RTN
+12 V
D
Gate
U4
C3
C4
Source
VEE
Voltage Isolation Barrier
Figure 11: Topology of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
3
gate resistance of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA05JT06-CAL. The steady state current supplied to the gate pin of the GA05JT06-CAL with on-board RG = 3.75 Ω, is shown
in Figure12. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 13.
For the GA05JT06-CAL, RG must be reduced for ID ≥ ~8 A for safe operation with the GA03IDDJT30-FR4.
For operation at ID ≥ ~8 A, RG may be calculated from the following equation, which contains the DC current gain hFE (Figur 5) and the gatesource saturation voltage VGS,sat (Figure 4).
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg5 of 9
Die Datasheet
Figure 12: Typical steady state gate current supplied by the
GA03IDDJT30-FR4 board for the GA05JT12-CAL with the on
board resistance of 3.75 Ω
GA05JT06-CAL
Figure 13: Maximum gate resistance for safe operation of
the GA05JT12-CAL at different drain currents using the
GA03IDDJT30-FR4 board.
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA05JT06-CAL at high-speed. It utilizes a gate drive
inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a
specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 14.
After turn on, while the device remains on the necessary steady state gate current IG,steady is supplied from source VCC through RG. Please
refer to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional
4
information on this driving topology.
VCC
S1
VCC
S2
L
VEE
S3
SiC SJT
D
G
RG
S4
S
VEE
Figure 14: Simplified Inductive Pulsed Drive Topology
3
– RG = (1/RG1 +1/RG2)-1. Driver is pre-installed with RG1 = RG2 = 7.5 Ω
4
Feb 2015
– Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg6 of 9
Die Datasheet
GA05JT06-CAL
C: Proportional Gate Current Driving
For applications in which the GA05JT06-CAL will operate over a wide range of drain current conditions, it may be beneficial to drive the device
using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain
current ID feedback to vary the steady state gate current IG,steady supplied to the GA05JT06-CAL
C:1: Voltage Controlled Proportional Driver
The voltage controlled proportional driver relies on a gate drive IC to detect the GA05JT06-CAL drain-source voltage VDS during on-state to
sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power
consumption, to be reduced while ID is relatively low or for IG,steady to increase when is ID higher. A high voltage diode connected between the
drain and sense protects the IC from high-voltage when the driver and GA05JT06-CAL are in off-state. A simplified version of this topology is
shown in Figure 15, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
HV Diode
Sense
Gate Signal
Proportional
Gate Current
Driver
Signal
D
G
Output
IG,steady
SiC SJT
S
Figure 15: Simplified Voltage Controlled Proportional Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the GA05JT06CAL during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID. at a fixed forced current gain
which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA05JT06-CAL is initially tuned-on using a gate current pulse supplied
into an RC drive circuit to allow ID current to begin flowing. This topology allows I G,steady, and thus the gate drive power consumption, to be
reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 16,
additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/.
N2
SiC SJT
Gate Signal
D
G
S
N3
N1
N2
Figure 16: Simplified Current Controlled Proportional Driver
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg7 of 9
Die Datasheet
GA05JT06-CAL
Mechanical Parameters
1.57 x 1.57
mm2
62 x 62
mil2
2.46/1.66
mm2
3820/4271
mil
Die Thickness
360
µm
14
mil
Wafer Size
100
mm
3937
mil
0
deg
0
deg
Die Dimensions
Die Area total / active
Flat Position
Die Frontside Passivation
2
Polyimide
Gate/Source Pad Metallization
4000 nm Al
Bottom Drain Pad Metallization
400 nm Ni + 200 nm Au
Die Attach
Electrically conductive glue or solder
Wire Bond
Al ≤ 8 mil (Source)
Al ≤ 1.25 mil (Gate)
Φ ≥ 0.3 mm
Reject ink dot size
Store in original container, in dry nitrogen,
Recommended storage environment
< 6 months at an ambient temperature of 23 °C
Chip Dimensions:
A
C
E
A
1.57
62
D
B
B
1.57
62
C
1.01
40
SOURCE
WIREBONDABLE
D
1.01
40
E
0.10
4
F
0.27
11
GATE
WIREBONDABLE
G
0.18
7
H
0.17
7
H
Feb 2015
mil
DIE
F
G
mm
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg8 of 9
Die Datasheet
GA05JT06-CAL
Revision History
Date
Revision
Comments
2015/02/6
1
Updated Electrical Characteristics
2014/08/28
0
Initial release
Supersedes
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
Feb 2015
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-bare-die/
Pg9 of 9
Die Datasheet
GA05JT06-CAL
SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/hit_sic/baredie/sjt/GA05JT06-CAL_SPICE.pdf) into LTSPICE
(version 4) software for simulation of the GA05JT06-CAL.
*
MODEL OF GeneSiC Semiconductor Inc.
*
*
$Revision:
1.0
$
*
$Date:
26-AUG-2014
$
*
*
GeneSiC Semiconductor Inc.
*
43670 Trade Center Place Ste. 155
*
Dulles, VA 20166
*
*
COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc.
*
ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA05JT06 NPN
+ IS
5.0E-47
+ ISE
1.25E-28
+ EG
3.2
+ BF
110
+ BR
0.55
+ IKF
200
+ NF
1
+ NE
2
+ RB
14.5
+ RE
0.01
+ RC
0.23
+ CJC
2.16E-10
+ VJC
3.656
+ MJC
0.4717
+ CJE
5.021E-10
+ VJE
2.95
+ MJE
0.4867
+ XTI
3
+ XTB
-1.0
+ TRC1
1.050E-2
+ VCEO
600
+ ICRATING 5
+ MFG
GeneSiC_Semiconductor
*
* End of GA05JT06 SPICE Model
August 2014
http://www.genesicsemi.com/high-temperature-sic/high-temperature-sic-junction-transistors/
Pg1 of 1
Similar pages