Supertex inc. LP0701 P-Channel Enhancement-Mode Lateral MOSFET Features General Description ►► Ultra-low threshold ►► High input impedance ►► Low input capacitance ►► Fast switching speeds ►► Low on-resistance ►► Freedom from secondary breakdown ►► Low input and output leakage These enhancement-mode (normally-off) transistors utilize a lateral MOS structure and Supertex’s well-proven silicongate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and negative temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. The low threshold voltage and low on-resistance characteristics are ideally suited for hand held, battery operated applications. Applications ►► Logic level interfaces ►► Solid state relays ►► Battery operated systems ►► Photo voltaic drives ►► Analog switches ►► General purpose line drivers Ordering Information Product Summary Part Number Package Options Packing LP0701LG-G 8-Lead SOIC 2500/Reel LP0701N3-G TO-92 1000/Bag LP0701N3-G P002 TO-92 2000/Reel LP0701N3-G P003 TO-92 2000/Reel LP0701N3-G P005 TO-92 2000/Reel LP0701N3-G P013 TO-92 2000/Reel LP0701N3-G P014 TO-92 RDS(ON) VGS(TH) ID(ON) -16.5V 3.0kΩ -1.0V (max) 3.0mA (min) Pin Configuration D D D D DRAIN 2000/Reel NC -G denotes a lead (Pb)-free / RoHS compliant package Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014 TO-92 Taping Specifications and Winding Styles NC S SOURCE G 8-Lead SOIC TO-92 GATE Product Marking Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±10V Operating and storage temperature BVDSS/BVDGS YYWW P0701 LLLL YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging Package may or may not include the following marks: Si or 8-Lead SOIC -55°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Si LP 0 7 0 1 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging Package may or may not include the following marks: Si or TO-92 Doc.# DSFP-LP0701 B071513 Supertex inc. www.supertex.com LP0701 Thermal Characteristics ID ID Package (continuous)† (mA) (pulsed)† (A) 8-Lead SOIC -700 TO-92 -500 Power Dissipation ( C/W) IDR (mA) IDRM† 1.5‡ 101‡ -700 -1.25 1.0 132 -500 -1.25 @TC = 25OC (W) -1.25 -1.25 O θja (A) Notes: † ID (continuous) is limited by max rated Tj. ‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm Electrical Characteristics (T = 25°C unless otherwise specified) A Sym Parameter Min Typ Max Units Drain-to-source breakdown voltage -16.5 - - V VGS = 0V, ID = -1.0mA Gate threshold voltage -0.5 -0.7 -1.0 V VGS = VDS, ID = -1.0mA Change in VGS(th) with temperature - - -4.0 mV/ C VGS = VDS, ID = -1.0mA IGSS Gate body leakage - - -100 nA VGS = ±10V, VDS = 0V - - -100 nA IDSS Zero gate voltage drain current VDS = -15V, VGS = 0V - - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125OC - -0.4 - -0.6 -1.0 - -1.25 -2.30 - - 2.0 4.0 - 1.7 2.0 - 1.3 1.5 - - 0.75 %/ C VGS = -5.0V, ID = -300mA 500 700 - mmho VGS = -15V, ID = -1.0A BVDSS VGS ΔVGS(th) ID(ON) On-state drain current Static drain-to-source on-state resistance RDS(ON) ΔRDS(ON) Change in RDS(ON) with temperature GFS Forward transconductance CISS Input capacitance - 120 250 COSS Common source output capacitance - 100 125 CRSS Reverse transfer capacitance - 40 60 td(ON) Turn-on delay time - - 20 Rise time - - 20 Turn-off delay time - - 30 Fall time - - 30 Diode forward voltage drop - -1.2 -1.5 tr td(OFF) tf VSD O Conditions VGS = VDS = -2.0V A VGS = VDS = -3.0V VGS = VDS = -5.0V VGS = -2.0V, ID = -50mA Ω VGS = -3.0V, ID = -150mA VGS = -5.0V, ID = -300mA O pF VGS = 0V, VDS = -15V, f = 1.0MHz ns VDD = -15V, ID = -1.25A, RGEN = 25Ω V VGS = 0V, ISD = -500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V INPUT -10V Pulse Generator 10% td(ON) 0V OUTPUT VDD Doc.# DSFP-LP0701 B071513 tr td(OFF) 90% 10% RGEN 90% t(OFF) t(ON) D.U.T. tf INPUT OUTPUT RL 90% 10% VDD 2 Supertex inc. www.supertex.com LP0701 Typical Performance Curves Output Characteristics -2.5 Saturation Characteristics -2.5 VGS = -5.0V VGS = -5.0V -2.0 -4V ID (amperes) ID (amperes) -2.0 -1.5 -3V -1.0 -2V -0.5 -4V -1.5 -3V -1.0 -2V -0.5 -1V 0 -4 -8 -12 VDS (volts) -16 Transconductance vs. Drain Current 1.0 VDS = -15V -1V 0 -1 TA = 125OC 0.4 -3 -4 VDS (volts) -5 SO-8 TA = 25OC 0.6 -2 Power Dissipation vs. Case Temperature 2 TA = -55OC 0.8 GFS (seimens) 0 PD (watts) 0 1 TO-92 0.2 0 -1.0 ID (amperes) 0 -2.0 Maximum Rated Safe Operating Area -10 1.0 ID (amperes) TO-92/SO-8 (pulsed) -1.0 TO-92 (DC) -0.1 -0.01 -0.1 Doc.# DSFP-LP0701 B071513 SO-8 (DC) TC = 25OC -1.0 -10 VDS (volts) 0 25 50 75 100 125 150 TC (OC) Thermal Resistance (normalized) 0 0.8 0.6 TO-92 TC = 25V PD = 1.0W 0.4 0.2 0 0.001 -100 Thermal Response Characteristics 0.01 0.1 1.0 10 tp (seconds) 3 Supertex inc. www.supertex.com LP0701 Typical Performance Curves (cont.) BVDSS Variation with Temperature On-Resistance vs. Drain Current 10 VGS = -2.0V 1.1 RDSS(ON) (ohms) BVDSS (normalized) 8 1.0 VGS = -3.0V VGS = -5.0V 6 4 2 0.9 0 50 100 0 150 -1 0 TJ ( C) O Transfer Characteristics -2 V(th) and RDS Variation with Temperature 1.4 VDS = -15V 1.2 TA = -55 C VGS(th) (normalized) ID (amperes) O TA = 25OC -1 TA = 125OC 0 -1 -2 -3 -4 1.2 0.8 1.0 RDS(ON) @ -5V, -300mA 0 50 VGS (volts) VDS = -10V CISS 100 VGS (volts) C (picofarads) -8 COSS CRSS 0 -5 -10 -20V -6 238pF -4 -2 0 -15 VDS (volts) Doc.# DSFP-LP0701 B071513 0.6 150 100 Gate Drive Dynamic Characteristics -10 f = 1.0MHz 0 0.8 TJ (OC) Capacitance vs. Drain-to-Source Voltage 200 1.4 1.0 0.4 -50 -5 1.6 V(th) @ -1.0mA 0.6 0 -3 -2 ID (amperes) RDS(ON) (normalized) -50 4 CISS = 115pF 0 1 2 3 QG (nanocoulombs) 4 5 Supertex inc. www.supertex.com LP0701 8-Lead SOIC (Narrow Body) Package Outline (LG) θ1 D 8 Note 1 (Index Area D/2 x E1/2) E1 E L2 L 1 θ L1 Top View View B Note 1 Gauge Plane Seating Plane View B h A h A A2 Seating Plane A1 e b Side View View A-A A Note: 1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol Dimension (mm) A A1 A2 b MIN 1.35* 0.10 1.25 0.31 NOM - - - - MAX 1.75 0.25 1.65* 0.51 D E E1 4.80* 5.80* 3.80* 4.90 6.00 3.90 5.00* 6.20* 4.00* e 1.27 BSC h L 0.25 0.40 - - 0.50 1.27 L1 1.04 REF L2 0.25 BSC θ θ1 0O 5O - - 8O 15O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. Doc.# DSFP-LP0701 B071513 5 Supertex inc. www.supertex.com LP0701 3-Lead TO-92 Package Outline (N3) D A Seating Plane 1 2 3 L c b e1 e Side View Front View E1 E 1 3 2 Bottom View Symbol Dimensions (inches) A b c D E E1 e e1 L MIN .170 .014† .014† .175 .125 .080 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022† .022† .205 .165 .105 .105 .055 .610* JEDEC Registration TO-92. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E041009. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-LP0701 B071513 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com