LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 LM139JAN Low Power Low Offset Voltage Quad Comparators Check for Samples: LM139JAN FEATURES DESCRIPTION • The LM139 consists of four independent precision voltage comparators with an offset voltage specification as low as 2 mV max for all four comparators. These were designed specifically to operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. These comparators also have a unique characteristic in that the input common-mode voltage range includes ground, even though operated from a single power supply voltage. 1 2 • • • • • • • • Wide Supply Voltage Range 5V to 36 VDCor ±2.5V to ±18 VDC Very Low Supply Current Drain (0.8 mA) Independent of Supply Voltage Low Input Biasing Current: 25 nA Low Input Offset Current: ±5 nA Offset Voltage: ±3 mV Input Common-Mode Voltage Range Includes GND Differential Input Voltage Range Equal to the Power Supply Voltage Low Output Saturation Voltage: 250 mV at 4 mA Output Voltage Compatible with TTL, DTL, ECL, MOS and CMOS Logic Systems ADVANTAGES • • • • • • High Precision Comparators Reduced VOS Drift Over Temperature Eliminates Need for Dual Supplies Allows Sensing Near GND Compatible with All Forms of Logic Power Drain Suitable for Battery Operation Application areas include limit comparators, simple analog to digital converters; pulse, squarewave and time delay generators; wide range VCO; MOS clock timers; multivibrators and high voltage digital logic gates. The LM139 was designed to directly interface with TTL and CMOS. When operated from both plus and minus power supplies, they will directly interface with MOS logic— where the low power drain of the LM139 is a distinct advantage over standard comparators. Connection Diagrams Figure 1. See Package Number NAD0014B 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Schematic Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Supply Voltage, V+ (2) 36 VDC or ±18 VDC Differential Input Voltage (3) 36 VDC Output Voltage 36 VDC −0.3 VDC to +36 VDC Input Voltage Input Current (VIN < −0.3 VDC) (4) (5) 50 mA Power Dissipation (6) (7) CLGA 350 mW @ TA = 125°C Output Short-Circuit to GND, (8) Continuous −65°C ≤ TA ≤ +150°C Storage Temperature Range Maximum Junction Temperature (TJ) +175°C Lead Temperature (Soldering, 10 seconds) 260°C −55°C ≤ TA ≤ +125°C Operating Temperature Range Thermal Resistance θJA θJC Package Weight (typical) CLGA (Still Air) 183°C/W CLGA (500LF / Min Air flow) 120°C/W CLGA 23°C/W CLGA 460mg ESD rating (9) (1) (2) (3) (4) (5) (6) (7) (8) (9) 600V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see, the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20mA independent of the magnitude of V+ Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the comparator will provide a proper output state. The low input voltage state must not be less than −0.3 VDC (or 0.3 VDCbelow the magnitude of the negative power supply, if used) (at 25°C). This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than −0.3 VDC (at 25°)C. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output so no loading change exists on the reference or input lines. The low bias dissipation and the ON-OFF characteristics of the outputs keeps the chip dissipation very small (PD ≤ 100mW), provided the output transistors are allowed to saturate. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (Package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax — TA) / θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Short circuits from the output to V+ can cause excessive heating and eventual destruction. When considering short circuits to ground, the maximum output current is approximately 20 mA independent of the magnitude of V+. Human Body model, 1.5 KΩ in series with 100 pF Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (°C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 3 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Quality Conformance Inspection (continued) Mil-Std-883, Method 5005 - Group A Subgroup Description Temp (°C) 11 Switching tests at -55 LM139 JAN Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. Symbol VIO Parameters Input Offset Voltage −VCC = 0V Conditions Notes Max Unit -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 2V, -VCC = -28V, VO = -13V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 +VCC = 5V, VO = 1.4V -5.0 5.0 mV 1 -7.0 7.0 mV 2, 3 -5.0 5.0 mV 1 +VCC = 30V, VO = 15V +VCC = 2V, -VCC = -3V, VO = -1.6V IIO Input Offset Current ±IIB Input Bias Current -7.0 7.0 mV 2, 3 +VCC = 30V, RS = 20KΩ, VO = 15V See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 2V, -VCC = -28V, RS = 20KΩ, VO = -13V See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 5V, RS = 20KΩ, VO = 1.4V See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 2V, -VCC = -3V, RS = 20KΩ, VO = -1.6V See (1) -25 25 nA 1, 2 See (1) -75 75 nA 3 +VCC = 30V, RS = 20KΩ, VO = 15V See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 +VCC = 2V, -VCC = -28V, RS = 20KΩ, VO = -13V See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 (1) 1, 2 +VCC = 5V, RS = 20KΩ, VO = 1.4V See -100 +0.1 nA See (1) -200 +0.1 nA 3 +VCC = 2V, -VCC = -3V, RS = 20KΩ, VO = -1.6V See (1) -100 +0.1 nA 1, 2 See (1) -200 +0.1 nA 3 dB 1, 2, 3 CMRR Input Voltage Common Mode Rejection +VCC = 30V 76 +VCC = 5V 70 ICEX Output Leakage +VCC = 30V, VO = +30V +IIL Input Leakage Current +VCC = 36V, V + i = 34V, V − i = 0V -IIL Input Leakage Current +VCC = 36V, V + i = 0V, V − i = 34V VOL Logical "0" Output Voltage +VCC = 4.5V, IO = 4mA +VCC = 4.5V, IO = 8mA ICC Power Supply Current +VCC = 5V, VID = 15mV +VCC = 30V, VID = 15mV (1) 4 Subgroups Min dB 1, 2, 3 1.0 µA 1, 2, 3 -500 500 nA 1, 2, 3 -500 500 nA 1, 2, 3 0.4 V 1 0.7 V 2, 3 1.5 V 1 2.0 V 2, 3 2.0 mA 1, 2 3.0 mA 3 3.0 mA 1, 2 4.0 mA 3 S/S RS = 20KΩ, tested at RS = 10KΩ as equivalent test. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 LM139 JAN Electrical Characteristics DC Parameters (continued) The following conditions apply, unless otherwise specified. Symbol ΔVIO /ΔT ΔIIO /ΔT AVS Parameters −VCC = 0V Conditions Notes Min Max Unit Subgroups Temperature Coefficient of Input Offset Voltage 25°C ≤ TA ≤ 125°C See (2) -25 25 µV/°C 2 -55°C ≤ TA ≤ 25°C See (2) -25 25 µV/°C 3 Temperature Coefficient of Input Offset Current 25°C ≤ TA ≤ 125°C See (2) -300 300 pA/°C 2 -55°C ≤ TA ≤ 25°C See (2) -400 400 pA/°C 3 Open Loop Voltage Gain +VCC = 15V, RL=15KΩ, 1V ≤ VO ≤ 11V See (3) 50 V/mV 4 See (3) 25 V/mV 5, 6 VIO Tempco Screen 4.0 mV CMRR Tempco Screen 70 dB IIO Tempco Screen 13 nA IIB Tempco Screen 12 nA (2) (3) Calculated parameter; for Delta VIO / Delta T use VIO test at +VCC = 30V, −VCC = 0V, VO = 15V; and for Delta IIO / Delta T use IIB test at +VCC = 30V, −VCC = 0V, VO = 15V Datalog of K = V/mV. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 5 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com LM139 JAN Electrical Characteristics AC Parameters Symbol tRLH Response Time: Low-to-High tRHL Response Time: High-to-Low CS Channel Separation VLAT Max Unit Subgroups +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 5mV 5.0 µS 7, 8B 7.0 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.2 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 5mV 2.5 µS 7, 8B 3.0 µS 8A +VCC = 5V, VI = 100mV, RL = 5.1KΩ, VOD = 50mV 0.8 µS 7, 8B 1.0 µS 8A Parameters Voltage Latch (Logical "1" Input) Conditions Notes Min +VCC = 20V, -VCC = -10V, A to B 80 dB 7 +VCC = 20V, -VCC = -10V, A to C 80 dB 7 +VCC = 20V, -VCC = -10V, A to D 80 dB 7 +VCC = 20V, -VCC = -10V, B to A 80 dB 7 +VCC = 20V, -VCC = -10V, B to C 80 dB 7 +VCC = 20V, -VCC = -10V, B to D 80 dB 7 +VCC = 20V, -VCC = -10V, C to A 80 dB 7 +VCC = 20V, -VCC = -10V, C to B 80 dB 7 +VCC = 20V, -VCC = -10V, C to D 80 dB 7 +VCC = 20V, -VCC = -10V, D to A 80 dB 7 +VCC = 20V, -VCC = -10V, D to B 80 dB 7 +VCC = 20V, -VCC = -10V, D to C 80 dB 7 0.4 V 9 Min Max Unit Subgroups +VCC = 5V, VI = 10V, IO = 4mA LM139 JAN Electrical Characteristics DC Parameters Drift Values The following conditions apply, unless otherwise specified. −VCC = 0V Delta calculations performed on JAN S product at Group B, Subgroup 5. Symbol Parameters Conditions VIO Input Offset Voltage VCC = 30V,VO = 15V -1.0 1.0 mV 1 ±IBias Input Bias Current VCC = 30V,RS = 20KΩ, VO = 15V -15 15 nA 1 6 Submit Documentation Feedback Notes Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Typical Performance Characteristics Supply Current Input Current Figure 2. Figure 3. Output Saturation Voltage Response Time for Various Input Overdrives —Negative Transition Figure 4. Figure 5. Response Time for Various Input Overdrives —Positive Transition Figure 6. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 7 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com APPLICATION HINTS The LM139 is a high gain, wide bandwidth device which, like most comparators, can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator changes states. Power supply bypassing is not required to solve this problem. Standard PC board layout is helpful as it reduces stray input-output coupling. Reducing the input resistors to < 10 kΩ reduces the feedback signal levels and finally, adding even a small amount (1 to 10 mV) of positive feedback (hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible. Simply socketing the IC and attaching resistors to the pins will cause input-output oscillations during the small transition intervals unless hysteresis is used. If the input signal is a pulse waveform, with relatively fast rise and fall times, hysteresis is not required. All pins of any unused comparators should be tied to the negative supply. The bias network of the LM139 establishes a drain current which is independent of the magnitude of the power supply voltage over the range of from 5 VDC to 30 VDC. It is usually unnecessary to use a bypass capacitor across the power supply line. The differential input voltage may be larger than V+ without damaging the device. Protection should be provided to prevent the input voltages from going negative more than −0.3 VDC (at 25°C). An input clamp diode can be used as shown in the applications section. The output of the LM139 is the uncommitted collector of a grounded-emitter NPN output transistor. Many collectors can be tied together to provide an output OR'ing function. An output pull-up resistor can be connected to any available power supply voltage within the permitted supply voltage range and there is no restriction on this voltage due to the magnitude of the voltage which is applied to the V+ terminal of the LM139 package. The output can also be used as a simple SPST switch to ground (when a pull-up resistor is not used). The amount of current which the output device can sink is limited by the drive available (which is independent of V+) and the β of this device. When the maximum current limit is reached (approximately 16 mA), the output transistor will come out of saturation and the output voltage will rise very rapidly. The output saturation voltage is limited by the approximately 60Ω RSAT of the output transistor. The low offset voltage of the output transistor (1 mV) allows the output to clamp essentially to ground level for small load currents. Typical Applications (V+ = 5.0 VDC) Figure 7. Basic Comparator Figure 8. Driving CMOS 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Figure 9. Driving TTL Figure 10. AND Gate Figure 11. OR Gate Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 9 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Typical Applications (V+= 15 VDC) Figure 12. One-Shot Multivibrator Figure 13. Bi-Stable Multivibrator 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Figure 14. One-Shot Multivibrator with Input Lock Out Figure 15. Pulse Generator Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 11 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com Figure 16. Large Fan-In AND Gate 12 Figure 17. ORing the Outputs Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Figure 18. Time Delay Generator Figure 19. Non-Inverting Comparator with Hysteresis Figure 20. Inverting Comparator with Hysteresis Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 13 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 14 www.ti.com Figure 21. Squarewave Oscillator Figure 22. Basic Comparator Figure 23. Limit Comparator Figure 24. Comparing Input Voltages of Opposite Polarity Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 * Or open-collector logic gate without pull-up resistor Figure 25. Output Strobing Figure 26. Crystal Controlled Oscillator Figure 27. Transducer Amplifier Figure 28. Zero Crossing Detector (Single Power Supply) Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 15 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com V+ = +30 VDC 250 mVDC ≤ VC ≤ +50 VDC 700 Hz ≤ fO ≤ 100 kHz Figure 29. Two-Decade High-Frequency VCO 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN LM139JAN www.ti.com SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 Split-Supply Applications (V+ = +15 VDC and V− = −15 VDC) Figure 30. MOS Clock Driver Figure 31. Zero Crossing Detector Figure 32. Comparator With a Negative Reference Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN 17 LM139JAN SNOSAJ7B – FEBRUARY 2005 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Date Released Section Changes 02/15/05 A New Release to corporate format 1 MDS datasheet converted into Corp. datasheet format. MJLM139-X rev 0D0. MDS datasheet will be archived. 10/26/2010 B Order Information, Connection Diagrams, Absolute Ratings, Physical Dimensions drawings, Update with current device information and format. Deleted J and WG pkg references. Revision A will be Archived 03/20/2013 B All Changed layout of National Data Sheet to TI format 18 Revision Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: LM139JAN PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Top-Side Markings (4) JL139BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q JM38510/ 11201BDA ACO 11201BDA >T JM38510/11201BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q JM38510/ 11201BDA ACO 11201BDA >T M38510/11201BDA ACTIVE CFP NAD 14 19 TBD Call TI Call TI -55 to 125 JL139BDA Q JM38510/ 11201BDA ACO 11201BDA >T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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OTHER QUALIFIED VERSIONS OF LM139JAN, LM139JAN-SP : • Military: LM139JAN • Space: LM139JAN-SP NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2 MECHANICAL DATA NAD0014B W14B (Rev P) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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