Intersil ISL97672BIRZ-EVAL 6-channel led driver with ultra low dimming capability Datasheet

6-Channel LED Driver with Ultra Low Dimming
Capability
ISL97672B
Features
The ISL97672B is an integrated power LED driver that controls
six channels of LED current for LCD backlight applications. The
ISL97672B is capable of driving LEDs from 4.5V to 26.5V, with
a maximum output of 45V.
• 6 x 50mA Channels
The ISL97672B employs an adaptive boost switching
architecture that allows Direct PWM dimming with linearity as
low as 0.007% at 200Hz or 0.8% at 20kHz. Dimming can be as
high as 30kHz.
The ISL97672B can compensate for non-uniformity of forward
voltage drops in the LED strings. Its headroom control circuit
monitors the highest LED forward voltage string for output
regulation to minimize voltage headroom and power loss in a
typical multi-string operation. Typical current matching between
channels is ±0.7%.
The ISL97672B features extensive protection functions that
flag whenever a fault occurs. The protections include
string-open and short-circuit detections, OVP, OTP, and an
optional output short-circuit protection with a fault disconnect
switch.
The ISL97672B is offered in a compact 20 Ld QFN 3x4
package and can operate in ambient temperatures of -40°C to
+85°C.
• 4.5V to 26.5V Input
• 45V Output Max
• Adaptive Boost Switching Architecture
• Direct PWM Dimming with Dimming Linearity of
0.007%~100% at 200Hz or 0.8%~100% <20kHz
• Adjustable 200kHz to 1.4MHz Switching Frequency
• Dynamic Headroom Control
• Fault Protections with Latched Flag Indication
- String Open/Short Circuit
- OVP
- OTP
- Optional Output Short-Circuit Fault Protection Switch
• Current Matching ±0.7%
• 20 Ld 3x4 QFN Package
Applications
• Notebook Displays LED Backlighting
• LCD Monitor LED Backlighting
• Multi-Function Printer Scanning Light Source
VOUT = 45V*, 6 x 50mA
VIN = 4.5V~26.5V
Q1 OPTIONAL
ISL97672B
1 FAULT
LX 20
2 VIN
1.2
OVP 16
4 VDC
1.0
PGND 19
6 /FLAG
18 COMP
0.8
ILED (mA)
CH0 10
CH1 11
CH2 12
3 EN
0.4
CH3 13
5 PWM
CH4 14
17 RSET
0.2
CH5 15
8 FSW
ILED = 20mA
FPWM = 20kHz
* VIN > 12V
9 AGND
0.6
0.0
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2
PWM DIMMING DUTY CYCLE (%)
FIGURE 1. TYPICAL APPLICATION DIAGRAM
June 13, 2012
FN7995.0
1
FIGURE 2. DIMMING LINEARITY AT 20kHz
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97672B
Block Diagram
45V*, 6x50mA
VIN: 4.5V~26.5V
10µH/1.5A
FAULT
VIN
O/P SHORT
INTERNAL BIAS
EN
4.7µF/50V
LX
OVP
REG
OVP
FAULT
FLAG
VDC
OSC & RAMP
COMP
SUM = 0
LOGIC
IMAX
/FLAG
FET
DRIVERS
ILIMIT
PGND
FAULT
FLAG
GM
AMP
COMP
DYNAMIC
HEADROOM
CONTROL
8-BIT
DAC
HIGHEST VF
STRING
DETECT
OPEN CKT, SHORT CKT
DETECTION
CH1
CH2
CH3
CH4
1
+
-
+
-
CH5
2
CH6
REF
GEN
ISET
3
4
* VIN >= 12V
5
REF_OVP REF_VSC
6
+
-
PWM
DIMMING CONTROLLER
TEMP
SENSOR
ISL97672B
FIGURE 3. ISL97672B BLOCK DIAGRAM
Ordering Information
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief TB347 for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL97672B. For more information on MSL, please see Tech
Brief TB363.
2
RSET
Evaluation Board
20
19
18
17
FAULT
1
16
OVP
VIN
2
15
CH5
EN
3
14
CH4
VDC
4
13
CH3
PWM
5
12
CH2
/FLAG
6
11
CH1
7
8
9
10
CH0
ISL97672BIRZ-EVAL
L20.3x4
COMP
20 Ld 3x4 QFN
AGND
672B
PGND
ISL97672BIRZ
PKG.
DWG. #
FSW
PACKAGE
(Pb-Free)
LX
PART
MARKING
ISL97672B
(20 LD 3X4 QFN)
TOP VIEW
NC
PART
NUMBER
(Notes 1, 2, 3)
Pin Configuration
FN7995.0
June 13, 2012
ISL97672B
Pin Descriptions (I = Input, O = Output, S = Supply)
PIN NAME
PIN #
TYPE
DESCRIPTION
FAULT
1
O
Fault disconnect switch.
VIN
2
S
Input voltage for device and LED power.
EN
3
I
The device needs 4ms for initial power-up Enable.
VDC
4
S
De-couple capacitor for internally generated supply rail.
PWM
5
I
PWM brightness control pin.
/FLAG
6
O
/Flag is latched low under any fault condition and resets after input power is recycled or part is re-enabled. This pin
is an open drain that needs pull-up.
NC
7
I
No Connect.
FSW
8
I
Boost switching frequency set pin by connecting a resistor. See “Switching Frequency” on page 11 for resistor
calculation.
AGND
9
S
Analog Ground for precision circuits.
CH0, CH1
CH2, CH3
CH4, CH5
10, 11,
12, 13,
14, 15
I
Input 0, Input 1, Input 2, Input 3, Input 4, Input 5 to current source, FB, and monitoring.
OVP
16
I
Overvoltage protection input.
RSET
17
I
Resistor connection for setting LED current (see Equation 1 for calculating the ILED peak).
COMP
18
O
Boost compensation pin.
PGND
19
S
Power ground (LX Power return).
LX
20
O
Input to boost switch.
3
FN7995.0
June 13, 2012
ISL97672B
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PWM Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OVP and VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current Matching and Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Dynamic Headroom Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Dimming Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5V Low Dropout Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-Up Sequencing, Soft-Start, and Fault Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
In-Rush Control and Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fault Protection and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Short-Circuit Protection (SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Open-Circuit Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Undervoltage Lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Input Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Schottky Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High-Current Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Low-Voltage Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
FN7995.0
June 13, 2012
ISL97672B
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
VIN, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V
FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 8.5V to VIN + 0.3V
VDC, COMP, RSET, PWM, OVP, FSW . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V
CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
20 Ld QFN Package (Notes 4, 5, 7) . . . . . .
40
2.5
Thermal Characterization (Typical)
PSIJT (°C/W)
NOTE: Voltage ratings are with respect to AGND pin.
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
20 Ld QFN Package (Note 6) . . . . . . . . . . . . . . . . . . . . .
1
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. PSIJT is the junction-to-top thermal resistance. If the package top temperature can be measured, with this rating then the die junction temperature
can be estimated more accurately than the θJA and θJC thermal resistance ratings.
7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
PARAMETER
All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted.
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
26.5
V
GENERAL
VIN (Note 9)
IVIN
IVIN_STBY
VOUT
Backlight Supply Voltage
TC = <+60°C
TA = +25°C
VIN Current
EN = 5V
VIN Shutdown Current
TA = +25°C
5
µA
Output Voltage
4.5V < VIN ≤ 26V,
FSW = 600kHz
45
V
8.55V < VIN ≤ 26V,
FSW = 1.2MHz
45
V
4.5V < VIN ≤ 8.55V,
FSW = 1.2MHz
VIN/0.19
V
2.6
V
VUVLO
Undervoltage Lock-out Threshold
VUVLO_HYS
Undervoltage Lock-out Hysteresis
4.5
5
2.1
mA
200
mV
ENABLE AND PWM GENERATOR
VIL
Guaranteed Range for PWM Input Low Voltage
VIH
Guaranteed Range for PWM Input High Voltage
FPWM
tON
0.8
V
1.5
VDD
V
PWM Input Frequency Range
200
30,000
Hz
Minimum On Time
250
350
ns
5
FN7995.0
June 13, 2012
ISL97672B
Electrical Specifications
PARAMETER
All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted.
DESCRIPTION
CONDITION
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
4.55
4.8
5
V
5
µA
200
mV
0.5
V
REGULATOR
VDC
LDO Output Voltage
VIN > 6V
Standby Current
EN = 0V
VLDO
VDC LDO Droop Voltage
VIN > 5.5V, 20mA
ENLow
Guaranteed Range for EN Input Low Voltage
ENHi
Guaranteed Range for EN Input High Voltage
1.8
SWILimit
Boost FET Current Limit
1.5
rDS(ON)
Internal Boost Switch ON-Resistance
TA = +25°C
Soft-start
100% LED Duty Cycle
Peak Efficiency
IVDC_STBY
20
V
BOOST
SS
Eff_peak
ΔIOUT/ΔVIN
Dmax
Dmin
Boost Minimum Duty Cycle
2.7
A
235
300
mΩ
7
ms
VIN = 12V, 72 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, TA = +25°C
92.9
%
VIN = 12V, 60 LEDs, 20mA
each, L = 10µH with DCR
101mΩ, TA = +25°C
90.8
%
0.1
%
Line Regulation
Boost Maximum Duty Cycle
2.0
FSW = 600kHz
90
%
FSW = 1.2MHz
81
%
FSW = 600kHz
9.5
%
FSW = 1.2MHz
17
%
fS
Minimum Switching Frequency
RFSW = 200kΩ
175
200
235
kHz
fS
Maximum Switching Frequency
RFSW = 33kΩ
1.312
1.50
1.69
MHz
LX Leakage Current
LX = 45V, EN = 0
10
µA
±1.0
%
+1.5
%
ILX_leakage
CURRENT SOURCES
IMATCH
IACC
Vheadroom
VRSET
ILEDmax
Channel-to-Channel Current Matching
RSET =20.1kΩ
(IOUT = 20mA)
Current Accuracy
±0.7
-1.5
Dominant Channel Current Source Headroom
at IIN Pin
ILED = 20mA
TA = +25°C
Voltage at RSET Pin
RSET = 20.1kΩ
Maximum LED Current per Channel
VIN = 12V, VOUT = 45V,
FSW = 1.2MHz, TA = +25°C
Short Circuit Threshold
PWM Dimming = 100%
500
1.2
1.22
mV
1.24
V
50
mA
8.2
V
FAULT DETECTION
VSC
7.5
Temp_shtdwn
Temperature Shutdown Threshold
150
°C
Temp_Hyst
Temperature Shutdown Hysteresis
23
°C
VOVPlo
FLAG_ON
Overvoltage Limit on OVP Pin
1.19
Fault Flag
When Fault Occurs,
IPULLUP= 4mA
Fault Pull-down Current
VIN = 12V
1.25
0.4
V
V
FAULT PIN
IFAULT
6
12
21
30
µA
FN7995.0
June 13, 2012
ISL97672B
Electrical Specifications
PARAMETER
VFAULT
All specifications are tested at TA = +25°C, VIN = 12V, EN = 5V, RSET = 20.1kΩ, unless otherwise noted.
DESCRIPTION
CONDITION
Fault Clamp Voltage with Respect to VIN
LXstart_thres
ILXStartup
MIN
(Note 8)
TYP
MAX
(Note 8)
UNIT
6
7
8.3
V
1.2
V
5
mA
VIN = 12, VIN - VFAULT
LX Start-up Threshold
0.9
LX Start-up Current
VDC = 5.0V
1
3.5
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. At maximum VIN of 26.5V, minimum VOUT is 28V. Minimum VOUT can be lower at lower VIN.
100
100
90
90
80
80
70
24VIN
12VIN
60
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
5VIN
50
40
30
70
40
30
20
10
5
10
15
20
0
25
5VIN
50
10
0
24VIN
12VIN
60
20
0
6P10S_30mA/CHANNEL
0
5
10
15
20
25
30
35
ILED(mA)
ILED(mA)
FIGURE 4. EFFICIENCY vs UP TO 20mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
FIGURE 5. EFFICIENCY vs UP TO 30mA LED CURRENT (100% LED
DUTY CYCLE) vs VIN
100
100
90
80
70
580k
1.2MHz
60
EFFICIENCY (%)
EFFICIENCY (%)
80
50
40
30
20
60
1.2MHz
580k
40
20
10
0
0
5
10
15
20
25
30
VIN
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT
20mA (100% LED DUTY CYCLE)
7
0
0
5
10
15
20
25
30
VIN
FIGURE 7. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT
30mA (100% LED DUTY CYCLE)
FN7995.0
June 13, 2012
ISL97672B
Typical Performance Curves
(Continued)
100
0.40
90
+25°C
70
60
-40°C
+85°C
0.30
CURRENT MATCHING (%)
EFFICIENCY (%)
80
0°C
50
40
30
20
0.20
0.10
0.00
4.5 VIN
12 VIN
-0.10
-0.20
21 VIN
-0.30
10
0
0
5
10
15
20
25
-0.40
30
0
1
2
3
4
5
6
7
CHANNEL
VIN
FIGURE 8. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100%
LED DUTY CYCLE)
FIGURE 9. CHANNEL-TO-CHANNEL CURRENT MATCHING
1.2
0.60
-40°C
+25°C
1.0
CURRENT
VHEADROOM (V)
0.55
0.8
4.5 VIN
0.6
12 VIN
0.4
0.50
0°C
0.45
0.2
0
0
1
2
3
DC
4
5
6
FIGURE 10. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE vs VIN
0.40
0
5
10
15
VIN (V)
20
25
30
FIGURE 11. VHEADROOM vs VIN AT 20mA
VIN = 6V, 6P12S
VO = 20V/DIV
VO = 50mV/DIV
2.00µs/DIV
2.00ms/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
EN
FIGURE 12. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT
20mA/CHANNEL
8
FIGURE 13. IN-RUSH and LED CURRENT AT VIN = 6V FOR 6P12S AT
20mA/CHANNEL
FN7995.0
June 13, 2012
ISL97672B
Typical Performance Curves
(Continued)
6P12S, 20mA/CH
VIN = 12V, 6P12S
VIN = 10V/DIV
VO = 20V/DIV
10.0ms/DIV
2.00ms/DIV
ILED = 20mA/DIV
I_VIN = 1A/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
EN
FIGURE 14. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 6P12S
AT 20mA/CHANNEL
6P12S, 20mA/CH
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V,
VIN = 12V, 6P12S AT 20mA/CHANNEL
6P12S, 20mA/CH
VIN = 10V/DIV
VO = 1V/DIV
10.0ms/DIV
10.0ms/DIV
I_VIN = 1A/DIV
ILED = 20mA/DIV
ILED = 20mA/DIV
FIGURE 16. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V
FOR 6P12S AT 20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE FROM 0% TO
100% PWM DIMMING, VIN = 12V, 6P12S AT
20mA/CHANNEL
6P12S, 20mA/CH
VO = 1V/DIV
10.0ms/DIV
ILED = 20mA/DIV
FIGURE 18. LOAD REGULATION WITH ILED CHANGE FROM 100% TO 0% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
9
FN7995.0
June 13, 2012
ISL97672B
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED stack with the highest forward
voltage drop to run at the programmed current. The ISL97672B
employs current mode control boost architecture that has a fast
current sense loop and a slow voltage feedback loop. Such
architecture achieves a fast transient response that is essential
for notebook backlight applications in which drained batteries
can be instantly changed to an AC/DC adapter without
noticeable visual disturbance. The number of LEDs that can be
driven by ISL97672B depends on the type of LED chosen in the
application. The ISL97672B is capable of boosting up to 45V and
typically driving 13 LEDs in series for each of the 8 channels,
enabling a total of 104 pieces of the 3.2V/20mA type of LEDs.
the op amp’s offset, internal layout, and reference, and these
parameters are optimized for current matching and absolute
current accuracy. The absolute accuracy is also determined by
the external RSET. A 1% tolerance resistor should be used.
+
-
REF
+
-
RSET
+
-
Enable
The Enable pin is used to enable the device. The Enable pin should
not float. If it does, a 10k or higher pull-down resistor should be
added.
OVP and VOUT
The Overvoltage Protection (OVP) pin has a function of setting the
overvoltage trip level as well as limiting the VOUT regulation
range.
The ISL97672B OVP threshold is set by RUPPER and RLOWER such
that:
VOUT_ovp = 1.21V * (RUPPER + RLOWER)/RLOWER
and VOUT can only regulate between 60% and 100% of the
VOUT_ovp such that:
Allowable VOUT = 60% to 100% of VOUT_ovp
if, for example, 10 LEDs are used with the worst-case VOUT of
35V.
PWM DIMMING
FIGURE 19. SIMPLIFIED CURRENT SOURCE CIRCUIT
Dynamic Headroom Control
The ISL97672B features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage string or
effectively the lowest voltage from any of the CH0 through CH5
pins. When this lowest channel voltage is lower than the
short-circuit threshold, VSC, this voltage is used as the feedback
signal for the boost regulator. The boost adjusts the output to the
correct level such that the lowest channel pin is at the target
headroom voltage. Since all LED stacks are connected to the
same output voltage, the other channel pins will have a higher
voltage, but the regulated current source circuit on each channel
ensures that each channel has the same current. The output
voltage regulates cycle by cycle, and it is always referenced to the
highest forward voltage string in the architecture.
If R1 and R2 are chosen such that the OVP level is set at 40V,
then VOUT is allowed to operate between 24V and 40V. If the VOUT
requirement is changed to an application of six LEDs of 21V, then
the OVP level must be reduced. Users should follow the
VOUT = (60% ~100%) OVP level requirement; otherwise, the
headroom control will be disturbed such that the channel voltage
can be much higher than expected. This can sometimes prevent
the driver from operating properly.
Dimming Controls
The ratio of the OVP capacitors should be the inverse of the OVP
resistors. For example, if RUPPER/RLOWER = 33/1, then
CUPPER/CLOWER = 1/33 with CUPPER = 100pF and
CLOWER = 3.3nF.
The initial brightness should be set by choosing an appropriate
value for RSET. This should be chosen to fix the maximum
possible LED current:
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 19.
The LED peak current is set by translating the RSET current to the
output, with a scaling factor of 401.8/RSET. The source terminals
of the current source MOSFETs are designed to run at 500mV to
optimize power loss versus accuracy requirements. The sources
of errors of the channel-to-channel current matching come from
10
The ISL97672B allows two ways of controlling the LED current,
and therefore, the brightness. They are:
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
MAXIMUM DC CURRENT SETTING
401.8
I LEDmax = --------------R SET
(EQ. 1)
For example, if the maximum required LED current
(ILED(max)) is 20mA, rearranging Equation 1 yields Equation 2:
R SET = 401.8 ⁄ 0.02 = 20.1kΩ
(EQ. 2)
FN7995.0
June 13, 2012
ISL97672B
PWM CURRENT CONTROL
The ISL97672B employs direct PWM dimming such that the output
PWM dimming follows directly with the input PWM signal without
modifying the input frequency. The average LED current of each
channel can be calculated as shown in Equation 3:
I LED ( ave ) = I LED × PWM
(EQ. 3)
Switching Frequency
The boost switching frequency can be adjusted by a resistor as
shown in Equation 4:
10
( 5 ×10 )
f SW = -----------------------R FSW
(EQ. 4)
where fSW is the desirable boost switching frequency, and RFSW
is the setting resistor.
5V Low Dropout Regulator
A 5V low dropout (LDO) regulator is present at the VDC pin to
develop the necessary low-voltage supply, which is used by the
chip’s internal control circuitry. Because VDC is an LDO pin, it
requires a bypass capacitor of 1µF or more for the regulation.
The VDC pin can be used as a coarse reference as long as it is
sourcing only a few milliamps.
Power-Up Sequencing, Soft-Start, and Fault
Management
To reduce in-rush current as various bulk capacitors charge up,
the ISL97672B includes circuits to manage input current draw
during normal start-up. The ISL97672B also detects several
external fault conditions and acts to limit fault energy and
prevent continued start-up while detected faults exist. Optionally,
an external high-side PFET can be fitted in series with VIN. The
ISL97672B turns this fault protection PFET off in the event of a
short fault to ground in the boost converter. This action prevents
damage to the system's main power supply in such an overload
condition.
In-Rush Control and Soft-Start
The ISL97672B has separate, built-in, independent in-rush
control and soft-start functions. The in-rush control function is
built around the short-circuit protection FET and is only available
in applications that include this device. At start-up, the fault
protection FET is turned on slowly due to a 30µA pull-down
current output from the FAULT pin. This discharges the fault FET's
gate-source capacitance, turning on the FET in a controlled
fashion. As this happens, the output capacitor is charged slowly
through the low-current FET before it becomes fully enhanced.
This results in a low in-rush current. This current can be further
reduced by adding a capacitor (in the 1nF to 5nF range) across
the gate source terminals of the FET.
Once the chip detects that the fault protection FET is turned on
fully, it assumes that in-rush is complete. At this point, the boost
regulator begins to switch, and the current in the inductor ramps
up. The current in the boost power switch is monitored, and
switching is terminated in any cycle in which the current exceeds
the current limit. The ISL97672B includes a soft-start feature in
which this current limit starts at a low value (275mA). This value
11
is stepped up to the final 2.2A current limit in seven additional
steps of 275mA each. These steps happen over at least 8ms and
are extended at low LED PWM frequencies if the LED duty cycle is
low. This extension allows the output capacitor to charge to the
required value at a low current limit and prevents high input
current for systems that have only a low to medium output
current requirement.
For systems with no master fault protection FET, the in-rush
current flows towards COUT when VIN is applied. The in-rush
current is determined by the ramp rate of VIN and the values of
COUT and L.
Fault Protection and Monitoring
The ISL97672B features extensive protection functions to cover
all perceivable failure conditions. The /FLAG pin is a latched
open-drain output that monitors string open, LED short, VOUT
short, and overvoltage and over-temperature conditions. This pin
resets only when input power is recycled or the part is re-enabled.
The failure mode of an LED can be either an open circuit or a
short. The behavior of an open-circuited LED can additionally
take the form of either infinite resistance or, for some LEDs, a
Zener diode, which is integrated into the device in parallel with
the now-opened LED.
For basic LEDs (which do not have built-in Zener diodes), an
open-circuit failure of an LED results only in the loss of one
channel of LEDs, without affecting other channels. Similarly, a
short-circuit condition on a channel that results in that channel
being turned off does not affect other channels unless a similar
fault is occurring.
Due to the lag in boost response to any load change at its output,
certain transient events (such as LED current steps or significant
step changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97672B uses feedback from the LEDs to
determine when it is in a stable operating region and prevents
apparent faults during these transient events from allowing any
of the LED stacks to fault out. See Table 1 for details.
A fault condition that results in an input current that exceeds the
device’s electrical limits will result in a shutdown of all output
channels.
Short-Circuit Protection (SCP)
The short-circuit detection circuit monitors the voltage on each
channel and disables faulty channels that are above
approximately 7.5V (this action is described in Table 1 on
page 13).
Open-Circuit Protection (OCP)
When one of the LEDs becomes an open circuit, it can behave as
either an infinite resistance or as a gradually increasing finite
resistance. The ISL97672B monitors the current in each channel
such that any string that reaches the intended output current is
considered “good.” Should the current subsequently fall below the
target, the channel is considered an “open circuit.” Furthermore,
should the boost output of the ISL97672B reach the OVP limit, or
should the lower over-temperature threshold be reached, all
channels that are not good are immediately considered to be open
circuit. Detection of an open circuit channel results in a time-out
FN7995.0
June 13, 2012
ISL97672B
before the affected channel is disabled. This time-out is sped up
when the device is above the lower over-temperature threshold, in
an attempt to prevent the upper over-temperature trip point from
being reached.
Some users employ special types of LEDs that have a Zener
diode structure in parallel with the LED. This configuration
provides ESD enhancement and enables open-circuit operation.
When this type of LED is open circuited, the effect is as if the LED
forward voltage has increased but the lighting level has not
increased. Any affected string will not be disabled, unless the
failure results in the boost OVP limit being reached, which allows
all other LEDs in the string to remain functional. In this case, care
should be taken that the boost OVP limit and SCP limit are set
properly, to ensure that multiple failures on one string do not
cause all other good channels to fault out. This condition could
arise if the increased forward voltage of the faulty channel
makes all other channels look as if they have LED shorts. See
Table 1 for details of responses to fault conditions.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps
the voltage at a safe level. The OVP threshold is set as shown in
Equation 5:
OVP = 1.21V × ( R UPPER + R LOWER ) ⁄ R LOWER
(EQ. 5)
The resistors should be large, to minimize power loss. For
example, a 1MΩ RUPPER and a 30kΩ RLOWER sets OVP to 41.2V.
Large OVP resistors also allow COUT to discharge slowly during the
PWM Off time. Parallel capacitors should also be placed across
the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER.
Using a CUPPER value of at least 30pF is recommended. These
capacitors reduce the AC impedance of the OVP node, which is
important when using high-value resistors.
Undervoltage Lock-out
If the input voltage falls below the UVLO level of 2.45V, the device
stops switching and is reset. Operation restarts only when VIN
returns to the normal operating range.
Input Overcurrent Protection
During a normal switching operation, the current through the
internal boost power FET is monitored. If the current exceeds the
current limit, the internal switch is turned off. Monitoring occurs
on a cycle-by-cycle basis in a self-protecting way.
Additionally, the ISL97672B monitors the voltage at the LX and
OVP pins. At start-up, the LX pins inject a fixed current into the
output capacitor. The device does not start unless the voltage at
LX exceeds 1.2V. The OVP pin is also monitored such that if it
rises above and subsequently falls below 20% of the target OVP
level, the input protection FET is also switched off.
Over-Temperature Protection (OTP)
The ISL97672B includes two over-temperature thresholds. The
lower threshold is set to +130°C. When this threshold is reached,
any channel that is outputting current at a level significantly below
the regulation target is treated as “open circuit” and is disabled after
a time-out period. This time-out period is reduced to 800µs when it
is above the lower threshold. The lower threshold isolates and
disables bad channels before they cause enough power dissipation
(as a result of other channels having large voltages across them) to
hit the upper temperature threshold.
The upper threshold is set to +150°C. Each time this threshold is
reached, the boost stops switching, and the output current
sources switch off. Once the device has cooled to approximately
+100°C, the device restarts, with the DC LED current level
reduced to 75% of the initial setting. If dissipation persists,
subsequent hitting of the limit causes identical behavior, with the
current reduced in steps to 50% and finally 25%. Unless disabled
via the EN pin, the device stays in an active state throughout.
For complete details of fault protection conditions, see Figure 20
and Table 1.
12
FN7995.0
June 13, 2012
ISL97672B
LX
VOUT
VIN
/FLAG
LX
FAULT
O/P
SHORT
DRIVER
OVP
IMAX
ILIMIT
FET
DRIVER
LOGIC
CH0
VSC
FAULT FLAG
CH5
THRM
SHDN
REF
T2
TEMP
SENSOR
OTP
T1
FAULT
DETECT
LOGIC
VSET
Q0
PWM/OC0/SC0
VSET
Q5
PWM/OC5/SC5
PWM
GENERATOR
FIGURE 20. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNEL ACTION
1
CH0 short circuit
Upper
Over-Temperature
Protection limit (OTP)
not triggered, and
CH0 < 7.5V
CH0 ON and burns power.
2
CH0 short circuit
Upper OTP triggered,
but VCH0 < 7.5V
All channels go off until chip cools,
Same as CH0
and then come back on with current
reduced to 76%. Subsequent OTP
triggers further reduce IOUT.
Highest VF of CH1
through CH5
3
CH0 short circuit
Upper OTP not
triggered, but
CH0 > 7.5V
CH1 disabled after six PWM cycle
time-outs.
CH1 through CH5 Normal
Highest VF of CH1
through CH5
4
CH0 open circuit with Upper OTP not
infinite resistance
triggered, and
CH0 < 7.5V
VOUT ramps to OVP. CH1 times out
after six PWM cycles and switches
off. VOUT drops to normal level.
CH1 through CH5 Normal
Highest VF of CH1
through CH5
5
CH0 LED open circuit Upper OTP not
triggered, and
but has paralleled
CH0 < 7.5V
Zener
CH1 remains ON and has highest VF; CH1 through CH5 ON, Q1 through
thus, VOUT increases.
Q5 burn power
13
CH1 through CH5 Normal
VOUT
REGULATED BY
Highest VF of CH1
through CH5
VF of CH0
FN7995.0
June 13, 2012
ISL97672B
TABLE 1. PROTECTIONS TABLE (Continued)
CASE
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNEL ACTION
VOUT
REGULATED BY
6
CH0 LED open circuit Upper OTP triggered,
but CH0 < 7.5V
but has paralleled
Zener
All channels go off until chip cools,
Same as CH0
and then come back on with current
reduced to 76%. Subsequent OTP
triggers further reduce IOUT.
7
CH0 LED open circuit Upper OTP not
triggered, but
but has paralleled
CHx > 7.5V
Zener
CH0 remains ON and has highest VF; VOUT increases, then CH-X switches VF of CH0
thus, VOUT increases.
OFF after six PWM cycles. This is an
unwanted shut off and can be
prevented by setting OVP at an
appropriate level.
8
Channel-to-channel
ΔVF too high
Lower OTP triggered,
but CHx < 7.5V
Any channel below the target current faults out after six PWM cycles.
Remaining channels are driven with normal current.
Highest VF of CH0
through CH5
9
Channel-to-channel
ΔVF too high
Upper OTP triggered,
but CHx < 7.5V
All channels go off until chip cools and then come back on with current
reduced to 76%. Subsequent OTP triggers further reduce IOUT.
Highest VF of CH0
through CH5
10
Output LED stack
voltage too high
VOUT > VOVP
Any channel that is below the target current times out after six PWM cycles, Highest VF of CH0
and VOUT returns to normal regulation voltage required for other channels. through CH5
11
VOUT/LX shorted to
GND at start-up, or
VOUT shorted in
operation
LX current and timing Chip is permanently shut down 31ms after power-up if VOUT/Lx is shorted to
monitored.
GND.
OVP pins monitored
for excursions below
20% of OVP
threshold.
Component Selection
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator On
time is equal to the change of inductor current during the
switching regulator Off time. As shown in Equations 6 and 7,
since the voltage across an inductor is:
(EQ. 6)
V L = L × ΔI L ⁄ Δt
and ΔIL @ On = ΔIL @ Off, therefore:
( V I – 0 ) ⁄ L × D × tS = ( VO – V D – VI ) ⁄ L × ( 1 – D ) × tS
value for temperature and voltage coefficient compared to other
ceramic capacitors.
In boost mode, input current flows continuously into the inductor,
with an AC ripple component proportional to the rate of inductor
charging only. In this mode, smaller-value input capacitors may
be used. An input capacitor of at least 10µF is recommended.
Ensure that the voltage rating of the input capacitor is able to
handle the full supply range.
Inductor
(EQ. 7)
where D is the switching duty cycle defined by the turn-on time
over the switching period. VD is a Schottky diode forward voltage
that can be neglected for approximation.
Rearranging the terms without accounting for VD gives the boost
ratio and duty cycle, respectively, as shown in Equations 8 and 9:
VO ⁄ VI = 1 ⁄ ( 1 – D )
(EQ. 8)
D = ( VO – VI ) ⁄ VO
(EQ. 9)
Input Capacitor
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. The capacitors reduce interaction between the regulator
and input supply, thus improving system stability. The high
switching frequency of the loop causes almost all ripple current
to flow into the input capacitor, which must be rated accordingly.
A capacitor with low internal series resistance should be chosen
to minimize heating effects and to improve system efficiency.
The X5R and X7R ceramic capacitors offer small size and a lower
14
VF of CH0
Inductor selection should be based on its maximum current (ISAT)
characteristics, power dissipation (DCR), EMI susceptibility
(shielded vs unshielded), and size. Inductor type and value
influence many key parameters, including ripple current, current
limit, efficiency, transient performance, and stability.
Inductor maximum current capability must be adequate to
handle the peak current in the worst-case condition. If an
inductor core with too low a current rating is chosen, saturation
in the core will cause the effective inductor value to fall, leading
to an increase in peak-to-average current level, poor efficiency,
and overheating in the core. The series resistance, DCR, within
the inductor causes conduction loss and heat dissipation. A
shielded inductor is usually more suitable for EMI-susceptible
applications, such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off period, as shown in Equation 10:
IL peak = ( V O × I O ) ⁄ ( 85% × V I ) + 1 ⁄ 2 [ V I × ( V O – V I ) ⁄ ( L × V O × f S ) ]
(EQ. 10)
The value of 85% is an average term for the efficiency
approximation. The first term is average current that is inversely
proportional to the input voltage. The second term is inductor
FN7995.0
June 13, 2012
ISL97672B
current change that is inversely proportional to L and fS. As a
result, for a given switching frequency and minimum input
voltage at which the system operates, the inductor ISAT must be
chosen carefully. Usually, at a given inductor size, the larger the
inductance, the higher the series resistance because of the extra
winding of the coil. Thus, the higher the inductance, the lower the
peak current capability. The ISL97672B current limit may also
have to be considered.
VOUT
CH0
Output Capacitors
The output capacitor smooths the output voltage and supplies
load current directly during the conduction phase of the power
switch. Output ripple voltage consists of the discharge of the
output capacitor for ILPEAK during FET On and the voltage drop
due to flow through the ESR of the output capacitor. The ripple
voltage can be shown as Equation 11:
ΔV CO = ( I O ⁄ C O × D ⁄ f S ) + ( ( I O × ESR )
(EQ. 11)
The conservation of charge principle shown in Equation 9 also
indicates that, during the boost switch Off period, the output
capacitor is charged with the inductor ripple current, minus a
relatively small output current in boost topology. As a result, the
user must select an output capacitor with low ESR and adequate
input ripple current capability.
Output Ripple
The value of ΔVCo can be reduced by increasing CO or fS, or by
using small ESR capacitors. In general, ceramic capacitors are
the best choice for output capacitors in small- to medium-sized
LCD backlight applications, due to their cost, form factor, and low
ESR.
A larger output capacitor also eases driver response during the
PWM dimming Off period, due to the longer sample and hold
effect of the output drooping. The driver does not need to boost
harder in the next On period that minimizes transient current.
The output capacitor is also needed for compensation, and in
general, 2x4.7µF/50V ceramic capacitors are suitable for
notebook display backlight applications.
CH1
CH2
FIGURE 21. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT
APPLICATIONS
Low-Voltage Operations
The ISL97672B VIN pin can be separately biased from the LED
power input to allow low-voltage operation. For systems that have
only a single supply, VOUT can be tied to the driver VIN pin to allow
initial start-up (Figure 22). The circuit works as follows: when the
input voltage is available and the device is not enabled, VOUT
follows VIN with a Schottky diode voltage drop. The VOUT bootstrapped to the VIN pin allows initial start-up, once the part is
enabled. Once the driver starts up with VOUT regulating to the
target, the VIN pin voltage also increases. As long as VOUT does
not exceed 26.5V and the extra power loss on VIN is acceptable,
this configuration can be used for input voltage as low as 3.0V.
The Fault Protection FET feature cannot be used in this
configuration.
For systems that have dual supplies, the VIN pin can be biased
from 5V to 12V, while input voltage can be as low as 2.7V
(Figure 23). In this configuration, VBIAS must be greater than or
equal to VIN to use the fault FET.
VOUT = 26.5, 6 x 50mA*
VIN = 3.0V~21V
Schottky Diode
A high-speed rectifier diode is necessary to prevent excessive
voltage overshoot, especially in the boost configuration. Schottky
diodes are the preferred choice because of their low forward
voltage and reverse leakage current, which minimize losses.
Although the Schottky diode turns on only during the boost
switch Off period, it carries the same peak current as the
inductor, and therefore, a suitable current-rated Schottky diode
must be used.
ISL97672B
1 FAULT
2 VIN
4 VDC
6 /FLAG
LX 20
OVP 16
PGND 19
CH0 10
CH1 11
Applications
High-Current Applications
Each channel of the ISL97672B can support up to 30mA. For
applications that need higher current, multiple channels can be
grouped to achieve the desired current (Figure 21). For example,
the cathode of the last LED can be connected to CH0 through
CH2; this configuration can be treated as a single string with
90mA current driving capability.
15
5 PWM
CH2 12
3 EN
CH3 13
17 RSET
8 FSW
9 AGND
CH4 14
CH5 15
COMP 18
* VIN > 12V
FIGURE 22. SINGLE SUPPLY 3.0V OPERATION
FN7995.0
June 13, 2012
ISL97672B
VOUT = 45V*, 6 x 50mA*
VIN = 2.7V~26.5V
Q1 OPTIONAL
ISL97672B
VBIAS = 5V~12V
1 FAULT
LX 20
2 VIN
OVP 16
4 VDC
6 /FLAG
PGND 19
CH0 10
CH1 11
5 PWM
CH2 12
3 EN
CH3 13
CH4 14
17 RSET
CH5 15
8 FSW
9 AGND
COMP 18
* VIN > 12V
Compensation
The ISL97672B has two main elements in the system: the
Current Mode Boost Regulator, and the op amp-based,
multi-channel current sources. The ISL97672B incorporates a
transconductance amplifier in its feedback path to allow the user
better regulation and some level of adjustment on the transient
response. The ISL97672B uses current mode control
architecture, which has a fast current sense loop and a slow
voltage feedback loop. The fast current feedback loop does not
require any compensation, but for stable operation, the slow
voltage loop must be compensated. The compensation network
is a series Rc, Cc1 network from COMP pin to ground, with an
optional Cc2 capacitor connected to the COMP pin. The Rc sets
the high-frequency integrator gain for fast transient response,
and the Cc1 sets the integrator zero to ensure loop stability. For
most applications, Rc is in the range of 15kΩ, and Cc1 is in the
range of 2.2nF. Depending upon the PCB layout, for stability, a
Cc2 in the range of 47pF may be needed to create a pole to
cancel the output capacitor ESR’s zero effect.
FIGURE 23. DUAL SUPPLY 2.7V OPERATION
16
FN7995.0
June 13, 2012
ISL97672B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
June 13, 2012
FN7995.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL97672B
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
FN7995.0
June 13, 2012
ISL97672B
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0.9± 0.10
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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