MB96690 Series
F2MC-16FX , 16-bit Proprietary
Microcontroller
MB96690 series is based on Cypress advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy
migration of F2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to
the previous generation include significantly improved performance - even at the same operation frequency, reduced
power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum
instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the
on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable
operation frequencies for peripheral resources independent of the CPU speed.
Features
Technology
On-chip voltage regulator
0.18µm CMOS
Internal voltage regulator supports a wide MCU
supply voltage range (Min=2.7V), offering low power
consumption
CPU
F2MC-16FX CPU
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different
addressing modes, barrel shift, variety of pointers)
8-byte instruction queue
Signed multiply (16-bit × 16-bit) and divide
(32-bit/16-bit) instructions available
Low voltage detection function
Reset is generated when supply voltage falls below
programmable reference voltage
Code Security
Protects Flash Memory content from unintended
read-out
System clock
DMA
On-chip PLL clock multiplier (×1 to ×8, ×1 when PLL
stop)
Automatic transfer function independent of CPU, can
be assigned freely to resources
4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator
depends on Q-factor)
Interrupts
Up to 8MHz external clock for devices with fast clock
input feature
8 programmable priority levels
Fast Interrupt processing
32.768kHz subsystem quartz clock
Non-Maskable Interrupt (NMI)
100kHz/2MHz internal RC clock for quick and safe
startup, clock stop detection function, watchdog
CAN
Clock source selectable from mainclock oscillator,
subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of
peripherals
The subclock oscillator is enabled by the Boot ROM
program controlled by a configuration marker after a
Power or External reset
Low Power Consumption - 13 operating modes
(different Run, Sleep, Timer, Stop modes)
Cypress Semiconductor Corporation
Document Number: 002-04717 Rev *A
•
198 Champion Court
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1Mbps
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of
message objects)
Maskable interrupt
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 19, 2016
MB96690 Series
Disabled Automatic Retransmission mode for Time
Triggered CAN applications
Programmable loop-back mode for self-test operation
USART
Full duplex USARTs (SCI/LIN)
Free-Running Timers
Signals an interrupt on overflow, supports timer clear
upon match with Output Compare (0, 4)
1
2
3
4
5
6
7
Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 ,
8
1/2 of peripheral clock frequency
Wide range of baud rate settings using a dedicated
reload timer
Input Capture Units
Special synchronous options for adapting to different
synchronous serial protocols
Signals an interrupt upon external event
LIN functionality working either as master or slave
LIN device.
Extended support for LIN-Protocol (with 16-byte FIFO
for selected channels) to reduce interrupt load.
I2C
Up to 400kbps
Master and Slave functionality, 7-bit and 10-bit
addressing
16-bit wide
Rising edge, Falling edge or Both (rising & falling)
edges sensitive
Output Compare Units
16-bit wide
Signals an interrupt when a match with Free-running
Timer occurs
A pair of compare registers can be used to generate
an output signal
Programmable Pulse Generator
A/D converter
16-bit down counter, cycle and duty setting registers
SAR-type
Can be used as 2 ×8-bit PPG
8/10-bit resolution
Interrupt at trigger, counter borrow and/or duty match
Signals interrupt on conversion end, single
conversion mode, continuous conversion mode, stop
conversion mode, activation by software, external
trigger, reload timers and PPGs
PWM operation and one-shot operation
Range Comparator Function
Scan disable Function
ADC Pulse Detection Function
Internal prescaler allows 1, 1/4, 1/16, 1/64 of
peripheral clock as counter clock or of selected
Reload timer underflow as clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Source Clock Timers
Start delay
Three independent clock timers (23-bit RC clock
timer, 23-bit Main clock timer, 17-bit Sub clock timer)
Stepping Motor Controller
Hardware Watchdog Timer
Stepping Motor Controller with integrated high
current output drivers
Hardware watchdog timer is active after reset
Four high current outputs for each channel
Window function of Watchdog Timer is used to select
the lower window limit of the watchdog interval
Two synchronized 8/10-bit PWMs per channel
Reload Timers
16-bit wide
Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6,
1/8, 1/10, 1/12, 1/16 of peripheral clock
Dedicated power supply for high current output
drivers
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of
peripheral clock frequency
Event count function
Document Number: 002-04717 Rev *A
Page 2 of 75
MB96690 Series
LCD Controller
Non Maskable Interrupt
LCD controller with up to 4COM ×36SEG
Disabled after reset, can be enabled by Boot-ROM
depending on ROM configuration block
Internal or external voltage generation
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Fixed 1/3 bias
Programmable frame period
Clock source selectable from four options (main clock,
peripheral clock, subclock or RC oscillator clock)
Internal divider resistors or external divider resistors
On-chip data memory for display
Once enabled, cannot be disabled other than by
reset
High or Low level sensitive
Pin shared with external interrupt 0
I/O Ports
Most of the external pins can be used as general
purpose I/O
Blank display: selectable
All push-pull outputs(except when used as I2C
SDA/SCL line)
All SEG, COM and V pins can be switched between
general and specialized purposes
Bit-wise programmable as input/output or peripheral
signal
LCD display can be operated in Timer Mode
Bit-wise programmable input enable
Sound Generator
8-bit PWM signal is mixed with tone frequency from
16-bit reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of
peripheral clock
Real Time Clock
Operational on main oscillation (4MHz), sub
oscillation (32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock
or RC oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s
clock
One input level per GPIO-pin (either Automotive or
CMOS hysteresis)
Bit-wise programmable pull-up resistor
Built-in On Chip Debugger (OCD)
One-wire debug tool interface
Break function:
Hardware break: 6 points (shared with code
event)
Software break: 4096 points
Event function
Code event: 6 points (shared with hardware
break)
Data event: 6 points
Event sequencer: 2 levels + reset
Execution time measurement function
External Interrupts
Trace function: 42 branches
Edge or Level sensitive
Security function
Interrupt mask bit per channel
Each available CAN channel RX has an external
interrupt for wake-up
Selected USART channels SIN have an external
interrupt for wake-up
Document Number: 002-04717 Rev *A
Page 3 of 75
MB96690 Series
Flash Memory
Write/Erase/Erase-Suspend/Resume commands
Dual operation flash allowing reading of one Flash
bank while programming or erasing the other bank
A flag indicating completion of the automatic
algorithm
Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory
Erase can be performed on each sector individually
Supports automatic programming, Embedded
Algorithm
Sector protection
Flash Security feature to protect the content of the
Flash
Low voltage detection during Flash erase or write
Cypress provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.cypress.com/cypress-microcontrollers
Document Number: 002-04717 Rev *A
Page 4 of 75
MB96690 Series
Contents
1.
Product Lineup ...................................................................................................................................................... 7
2.
Block Diagram ....................................................................................................................................................... 8
3.
Pin Assignment ..................................................................................................................................................... 9
4.
Pin Description .................................................................................................................................................... 10
5.
Pin Circuit Type ................................................................................................................................................... 12
6.
I/O Circuit Type.................................................................................................................................................... 15
7.
Memory Map ........................................................................................................................................................ 22
8.
RAM start Addresses .......................................................................................................................................... 23
9.
User ROM Memory Map For Flash Devices ...................................................................................................... 24
10. Serial Programming Communication Interface ................................................................................................ 25
11. Interrupt Vector Table ......................................................................................................................................... 26
12. Handling Precautions ......................................................................................................................................... 30
12.1 Precautions for Product Design .......................................................................................................................... 30
12.2 Precautions for Package Mounting..................................................................................................................... 31
12.3 Precautions for Use Environment ....................................................................................................................... 33
13. Handling Devices ................................................................................................................................................ 34
13.1 Latch-up prevention............................................................................................................................................ 34
13.2 Unused pins handling ......................................................................................................................................... 34
13.3 External clock usage .......................................................................................................................................... 34
13.3.1 Single phase external clock for Main oscillator ................................................................................................... 34
13.3.2 Single phase external clock for Sub oscillator ..................................................................................................... 35
13.3.3 Opposite phase external clock ............................................................................................................................ 35
13.4 Notes on PLL clock mode operation................................................................................................................... 35
13.5 Power supply pins (Vcc/Vss) .............................................................................................................................. 35
13.6 Crystal oscillator and ceramic resonator circuit .................................................................................................. 35
13.7 Turn on sequence of power supply to A/D converter and analog inputs ............................................................ 36
13.8 Pin handling when not using the A/D converter .................................................................................................. 36
13.9 Notes on Power-on............................................................................................................................................. 36
13.10 Stabilization of power supply voltage ................................................................................................................. 36
13.11 SMC power supply pins ...................................................................................................................................... 36
13.12 Serial communication ......................................................................................................................................... 36
13.13 Mode Pin (MD) ................................................................................................................................................... 36
14. Electrical Characteristics ................................................................................................................................... 37
14.1 Absolute Maximum Ratings ................................................................................................................................ 37
14.2 Recommended Operating Conditions ................................................................................................................ 39
14.3 DC Characteristics ............................................................................................................................................. 40
14.3.1 Current Rating..................................................................................................................................................... 40
14.3.2 Pin Characteristics .............................................................................................................................................. 43
14.4 AC Characteristics.............................................................................................................................................. 47
14.4.1 Main Clock Input Characteristics......................................................................................................................... 47
14.4.2 Sub Clock Input Characteristics .......................................................................................................................... 48
14.4.3 Built-in RC Oscillation Characteristics ................................................................................................................. 49
14.4.4 Internal Clock Timing .......................................................................................................................................... 49
14.4.5 Operating Conditions of PLL ............................................................................................................................... 50
14.4.6 Reset Input.......................................................................................................................................................... 50
14.4.7 Power-on Reset Timing ...................................................................................................................................... 51
Document Number: 002-04717 Rev *A
Page 5 of 75
MB96690 Series
14.4.8 USART Timing .................................................................................................................................................... 52
14.4.9 External Input Timing .......................................................................................................................................... 54
14.4.10 I2C Timing ........................................................................................................................................................ 55
14.5 A/D Converter .................................................................................................................................................... 56
14.5.1 Electrical Characteristics for the A/D Converter .................................................................................................. 56
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ................................................................................ 57
14.5.3 Definition of A/D Converter Terms ...................................................................................................................... 58
14.6 High Current Output Slew Rate .......................................................................................................................... 60
14.7 Low Voltage Detection Function Characteristics ................................................................................................ 60
14.8 Flash Memory Write/Erase Characteristics ........................................................................................................ 62
15. Example Characteristics .................................................................................................................................... 63
16. Ordering Information .......................................................................................................................................... 66
17. Package Dimension ............................................................................................................................................ 67
18. Major Changes .................................................................................................................................................... 68
Document History ........................................................................................................................................ 74
Document Number: 002-04717 Rev *A
Page 6 of 75
MB96690 Series
1.
Product Lineup
Features
Product Type
Subclock
Dual Operation Flash Memory
64.5KB + 32KB
128.5KB + 32KB
256.5KB + 32KB
MB96690
Flash Memory Product
Subclock can be set by software
MB96F693R, MB96F693A
MB96F695R, MB96F695A
MB96F696R
LQFP-100
FPT-100P-M20
4ch
5ch
Product Options
R: MCU with CAN
A: MCU without CAN
2ch
LIN-USART 0/1
IC
1ch
8/10-bit A/D Converter
27ch
IC0
AN 2 to 4/6 to 8/10 to 12/
14 to 31
with Data Buffer
with Range Comparator
with Scan Disable
with ADC Pulse Detection
16-bit Reload Timer (RLT)
16-bit Free-Running Timer (FRT)
No
Yes
Yes
Yes
5ch
2ch
16-bit Input Capture Unit (ICU)
6ch
(5 channels for LIN-USART)
16-bit Output Compare Unit (OCU)
8/16-bit Programmable Pulse Generator (PPG)
with Timing point capture
with Start delay
with Ramp
4ch
10ch (16-bit) / 14ch (8-bit)
Yes
Yes
No
CAN Interface
1ch
Stepping Motor Controller (SMC)
External Interrupts (INT)
Non-Maskable Interrupt (NMI)
Sound Generator (SG)
4ch
16ch
1ch
2ch
LCD Controller
4COM × 36SEG
Real Time Clock (RTC)
Clock Calibration Unit (CAL)
1ch
75 (Dual clock mode)
77 (Single clock mode)
1ch
Clock Output Function
2ch
Low Voltage Detection Function
Yes
RAM
8KB
8KB
16KB
Package
DMA
USART
with automatic LIN-Header
transmission/reception
with 16 byte RX- and
TX-FIFO
2
I/O Ports
Remark
LIN-USART 0 to 2/4/5
2
RLT 0 to 3/6
FRT 0/1
ICU 0/1/4 to 7
(ICU 0/1/4 to 6
for LIN-USART)
OCU 0 to 3
PPG 0 to 7/14/15
CAN 0
32 Message Buffers
SMC 0 to 2/4
INT 0 to 15
SG 0/1
COM 0 to 3
SEG 0 to 4/7/
11 to 28/30/33/36 to 45
Low voltage detection
function can be
disabled by software
Hardware Watchdog Timer
Yes
On-chip RC-oscillator
Yes
On-chip Debugger
Yes
Note:
− All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the general I/O port according to your function use.
Document Number: 002-04717 Rev *A
Page 7 of 75
MB96690 Series
2.
Block Diagram
CKOT0_R, CKOT1, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A
RSTX
MD
NMI
DEBUG I/F
16FX
CPU
OCD
Interrupt
Controller
Clock &
Mode Controller
Flash
Memory A
16FX Core Bus (CLKB)
SDA0
SCL0
AVcc
AVss
AVRH
AVRL
AN2 to AN4
AN6 to AN8
AN10 to AN12
2
IC
1ch
8/10-bit ADC
27ch
AN14 to AN31
ADTG
TIN0 to TIN3
TOT0 to TOT3
FRCK0
FRCK0_R
IN0
IN0_R, IN1_R
OUT0 to OUT3
OUT0_R, OUT2_R
FRCK1
IN6, IN7
IN4_R, IN5_R, IN7_R
16-bit
Reload Timer
0/1/2/3/6
5ch
I/O Timer 0
FRT0
ICU 0/1
OCU 0/1/2/3
I/O Timer 1
FRT1
ICU 4/5/6/7
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
Peripheral
Bus Bridge
Watchdog
Peripheral Bus 1 (CLKP1)
DMA
Controller
RAM
CAN Interface
1ch
Sound
Generator
2ch
USART
5ch
PPG
10ch (16-bit) /
14ch (8-bit)
Stepping
Motor
Controller
4ch
Boot ROM
Voltage
Regulator
RX0
Vcc
Vss
C
TX0
SGO0, SGO1, SGO1_R
SGA0, SGA1, SGA1_R
SIN0 to SIN2, SIN4, SIN5, SIN5_R
SOT0 to SOT2, SOT4, SOT5_R
SCK0 to SCK2, SCK4, SCK5_R
TTG0, TTG2 to TTG4, TTG6, TTG7
TTG12 to TTG14
PPG0, PPG1, PPG3 to PPG7
PPG0_R to PPG4_R
PPG4_B to PPG7_B, PPG14_B, PPG15_B
DVcc
DVss
PWM1M0 to PWM1M2, PWM1M4
PWM1P0 to PWM1P2, PWM1P4
PWM2M0 to PWM2M2, PWM2M4
PWM2P0 to PWM2P2, PWM2P4
V0 to V3
COM0 to COM3
SEG0 to SEG4, SEG7
SEG11 to SEG28
SEG30, SEG33
SEG36 to SEG45
Document Number: 002-04717 Rev *A
LCD
controller/
driver
Real Time
Clock
4COM×36SEG
External
Interrupt
16ch
WOT, WOT_R
INT0 to INT15
INT1_R to INT7_R
Page 8 of 75
MB96690 Series
3.
Pin Assignment
Vss
P00_3 / SEG15 / INT6_R
P00_4 / SEG16 / INT7_R
Vss
P17_0
DEBUG I/F
MD
X0
X1
Vss
P04_1 / X1A*3
P04_0 / X0A*3
RSTX
P11_0 / COM0
P11_1 / COM1 / PPG0_R
P11_2 / COM2 / PPG1_R
P11_3 / COM3 / PPG2_R
P11_4 / SEG0 / PPG3_R
P11_5 / SEG1 / PPG4_R
P11_6 / SEG2 / FRCK0_R
P12_0 / SEG4 / IN1_R
P11_7 / SEG3 / IN0_R
P12_7 / SEG11 / INT1_R
P12_3 / SEG7 / OUT2_R
P00_0 / SEG12 / INT3_R
P00_1 / SEG13 / INT4_R
P00_2 / SEG14 / INT5_R
Vcc
(Top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
Vcc
77
49
P10_2 / PWM2P4 / SCK2 / PPG6 / AN30*1
P10_1 / PWM1M4 /SOT2 / TOT3 / AN29
P10_3 / PWM2M4 / PPG7 / AN31
78
48
P00_5 / SEG17 / IN6 / TTG2 / TTG6
79
47
P00_6 / SEG18 / IN7 / TTG3 / TTG7
80
46
P10_0 / PWM1P4 / SIN2 / TIN3 / INT11 / AN28*1
P00_7 / SEG19 / SGO0 / INT14
81
45
DVss
DVcc
P01_0 / SEG20 / SGA0
82
44
P01_1 / SEG21 / CKOT1 / OUT0
83
43
P09_3 / PWM2M2 / AN27
P01_2 / SEG22 / CKOTX1 / OUT1 / INT15
84
42
P09_2 / PWM2P2 / AN26
P01_3 / SEG23 / PPG5
85
41
P09_1 / PWM1M2 / AN25
P01_4 / SEG24 / SIN4 / INT8*1
86
40
P09_0 / PWM1P2 / AN24
39
P08_7 / PWM2M1 / AN23 /PPG7_B
38
P08_6 / PWM2P1 / AN22 /PPG6_B
P01_5 / SEG25 / SOT4
87
P01_6 / SEG26 / SCK4 / TTG12*1
88
P01_7 / SEG27 / CKOTX1_R / INT9 / TTG13
89
37
P08_5 / PWM1M1 / AN21
P02_0 / SEG28 / CKOT1_R / INT10 / TTG14
90
36
DVss
LQFP - 100
P02_2 / SEG30 / IN7_R / CKOT0_R / INT12
91
35
DVcc
P02_5 / SEG33 / OUT0_R / INT13 / SIN5_R*1
92
34
P08_4 / PWM1P1 / AN20
P03_0 / V0 / SEG36 / PPG4_B
93
33
P08_3 / PWM2M0 / AN19
P03_1 / V1 / SEG37 / PPG5_B
94
32
P08_2 / PWM2P0 / AN18
P03_2 / V2 / SEG38 / PPG14_B / SOT5_R
95
31
P08_1 / PWM1M0 / AN17
P03_3 / V3 / SEG39 / PPG15_B / SCK5_R*1
96
30
P08_0 / PWM1P0 / AN16
1
97
29
P05_7 / AN15 / TOT2 / SGA1_R
P03_5 / TX0
98
28
P05_6 / AN14 / TIN2 / SGO1_R
P03_6 / INT0 / NMI
99
27
P05_4 / AN12 / INT2_R / WOT_R
Vss
Vcc
P05_3 / AN11 / OUT3 / SGA1
P05_2 / AN10 / OUT2 / SGO1
P05_0 / AN8
AVss
AVRL
AVRH
AVcc
P06_7 / AN7 / TOT1 / IN5_R
P13_4 / SIN0 / INT6 / SEG45*1
P06_6 / AN6 / TIN1 / IN4_R
P13_3 / PPG1 / TOT0 / WOT / SEG44
P06_4 / AN4 / IN0 / TTG0 / TTG4
P13_2 / PPG0 / TIN0 / FRCK1 / SEG43
P06_3 / AN3 / FRCK0
P13_1 / INT3 / SCK1 / SEG42*1
P06_2 / AN2 / INT5 / SIN5*1
8
P04_5 / PPG4 / SCL0*2
7
P04_4 / PPG3 / SDA0*2
6
P13_6 / SCK0 / CKOTX0*1
5
P13_5 / SOT0 / ADTG / INT7
4
P13_0 / INT2 / SOT1 / SEG41
26
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
3
P03_7 / INT1 / SIN1 / SEG40*1
100
1 2
Vss
Vcc
C
P03_4 / RX0 / INT4*
(FPT-100P-M20)
*1: CMOS input level only
*2: CMOS input level only for I2C
*3: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
Document Number: 002-04717 Rev *A
Page 9 of 75
MB96690 Series
4.
Pin Description
Pin name
Feature
Description
ADTG
ADC
A/D converter trigger input pin
ANn
ADC
A/D converter channel n input pin
AVcc
Supply
Analog circuits power supply pin
AVRH
ADC
A/D converter high reference voltage input pin
AVRL
ADC
A/D converter low reference voltage input pin
AVss
Supply
Analog circuits power supply pin
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock Output function
Clock Output function n output pin
CKOTn_R
Clock Output function
Relocated Clock Output function n output pin
CKOTXn
Clock Output function
Clock Output function n inverted output pin
CKOTXn_R
Clock Output function
Relocated Clock Output function n inverted output pin
COMn
LCD
LCD Common driver pin
DEBUG I/F
OCD
On Chip Debugger input/output pin
DVcc
Supply
SMC pins power supply
DVss
Supply
SMC pins power supply
FRCKn
Free-Running Timer
Free-Running Timer n input pin
FRCKn_R
Free-Running Timer
Relocated Free-Running Timer n input pin
INn
ICU
Input Capture Unit n input pin
INn_R
ICU
Relocated Input Capture Unit n input pin
INTn
External Interrupt
External Interrupt n input pin
INTn_R
External Interrupt
Relocated External Interrupt n input pin
MD
Core
Input pin for specifying the operating mode
NMI
External Interrupt
Non-Maskable Interrupt input pin
OUTn
OCU
Output Compare Unit n waveform output pin
OUTn_R
OCU
Relocated Output Compare Unit n waveform output pin
Pnn_m
GPIO
General purpose I/O pin
PPGn
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_R
PPG
Relocated Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_B
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PWMn
SMC
SMC PWM high current output pin
RSTX
Core
Reset input pin
RXn
CAN
CAN interface n RX input pin
SCKn
USART
USART n serial clock input/output pin
SCKn_R
USART
Relocated USART n serial clock input/output pin
SCLn
2
I C interface n clock I/O input/output pin
2
IC
2
2
SDAn
IC
I C interface n serial data I/O input/output pin
SEGn
LCD
LCD Segment driver pin
SGAn
Sound Generator
Sound Generator amplitude output pin
Document Number: 002-04717 Rev *A
Page 10 of 75
MB96690 Series
Pin name
Feature
Description
SGAn_R
Sound Generator
Relocated Sound Generator amplitude output pin
SGOn
Sound Generator
Sound Generator sound/tone output pin
SGOn_R
Sound Generator
Relocated Sound Generator sound/tone output pin
SINn
USART
USART n serial data input pin
SINn_R
USART
Relocated USART n serial data input pin
SOTn
USART
USART n serial data output pin
SOTn_R
USART
Relocated USART n serial data output pin
TINn
Reload Timer
Reload Timer n event input pin
TOTn
Reload Timer
Reload Timer n output pin
TTGn
PPG
Programmable Pulse Generator n trigger input pin
TXn
CAN
CAN interface n TX output pin
Vn
LCD
LCD voltage reference pin
Vcc
Supply
Power supply pin
Vss
Supply
Power supply pin
WOT
RTC
Real Time clock output pin
WOT_R
RTC
Relocated Real Time clock output pin
X0
Clock
Oscillator input pin
X0A
Clock
Subclock Oscillator input pin
X1
Clock
Oscillator output pin
X1A
Clock
Subclock Oscillator output pin
Document Number: 002-04717 Rev *A
Page 11 of 75
MB96690 Series
5.
Pin Circuit Type
Pin no.
I/O circuit type*
Pin name
1
Supply
Vss
2
F
C
3
P
P03_7 / INT1 / SIN1 / SEG40
4
J
P13_0 / INT2 / SOT1 / SEG41
5
P
P13_1 / INT3 / SCK1 / SEG42
6
J
P13_2 / PPG0 / TIN0 / FRCK1 / SEG43
7
J
P13_3 / PPG1 / TOT0 / WOT / SEG44
8
P
P13_4 / SIN0 / INT6 / SEG45
9
H
P13_5 / SOT0 / ADTG / INT7
10
M
P13_6 / SCK0 / CKOTX0
11
N
P04_4 / PPG3 / SDA0
12
N
P04_5 / PPG4 / SCL0
13
I
P06_2 / AN2 / INT5 / SIN5
14
K
P06_3 / AN3 / FRCK0
15
K
P06_4 / AN4 / IN0 / TTG0 / TTG4
16
K
P06_6 / AN6 / TIN1 / IN4_R
17
K
P06_7 / AN7 / TOT1 / IN5_R
18
Supply
AVcc
19
G
AVRH
20
G
AVRL
21
Supply
AVss
22
K
P05_0 / AN8
23
K
P05_2 / AN10 / OUT2 / SGO1
24
K
P05_3 / AN11 / OUT3 / SGA1
25
Supply
Vcc
26
Supply
Vss
27
K
P05_4 / AN12 / INT2_R / WOT_R
28
K
P05_6 / AN14 / TIN2 / SGO1_R
29
K
P05_7 / AN15 / TOT2 / SGA1_R
30
R
P08_0 / PWM1P0 / AN16
31
R
P08_1 / PWM1M0 / AN17
32
R
P08_2 / PWM2P0 / AN18
33
R
P08_3 / PWM2M0 / AN19
34
R
P08_4 / PWM1P1 / AN20
35
Supply
DVcc
36
Supply
DVss
Document Number: 002-04717 Rev *A
Page 12 of 75
MB96690 Series
Pin no.
I/O circuit type*
Pin name
37
R
P08_5 / PWM1M1 / AN21
38
R
P08_6 / PWM2P1 / AN22 / PPG6_B
39
R
P08_7 / PWM2M1 / AN23 / PPG7_B
40
R
P09_0 / PWM1P2 / AN24
41
R
P09_1 / PWM1M2 / AN25
42
R
P09_2 / PWM2P2 / AN26
43
R
P09_3 / PWM2M2 / AN27
44
Supply
DVcc
45
Supply
DVss
46
S
P10_0 / PWM1P4 / SIN2 / TIN3 / INT11 / AN28
47
R
P10_1 / PWM1M4 / SOT2 / TOT3 / AN29
48
S
P10_2 / PWM2P4 / SCK2 / PPG6 / AN30
49
R
P10_3 / PWM2M4 / PPG7 / AN31
50
Supply
Vcc
51
Supply
Vss
52
O
DEBUG I/F
53
H
P17_0
54
C
MD
55
A
X0
56
A
X1
57
Supply
Vss
58
B
P04_0 / X0A
59
B
P04_1 / X1A
60
C
RSTX
61
J
P11_0 / COM0
62
J
P11_1 / COM1 / PPG0_R
63
J
P11_2 / COM2 / PPG1_R
64
J
P11_3 / COM3 / PPG2_R
65
J
P11_4 / SEG0 / PPG3_R
66
J
P11_5 / SEG1 / PPG4_R
67
J
P11_6 / SEG2 / FRCK0_R
68
J
P11_7 / SEG3 / IN0_R
69
J
P12_0 / SEG4 / IN1_R
70
J
P12_3 / SEG7 / OUT2_R
71
J
P12_7 / SEG11 / INT1_R
72
J
P00_0 / SEG12 / INT3_R
73
J
P00_1 / SEG13 / INT4_R
Document Number: 002-04717 Rev *A
Page 13 of 75
MB96690 Series
Pin no.
I/O circuit type*
Pin name
74
J
P00_2 / SEG14 / INT5_R
75
Supply
Vcc
76
Supply
Vss
77
J
P00_3 / SEG15 / INT6_R
78
J
P00_4 / SEG16 / INT7_R
79
J
P00_5 / SEG17 / IN6 / TTG2 / TTG6
80
J
P00_6 / SEG18 / IN7 / TTG3 / TTG7
81
J
P00_7 / SEG19 / SGO0 / INT14
82
J
P01_0 / SEG20 / SGA0
83
J
P01_1 / SEG21 / CKOT1 / OUT0
84
J
P01_2 / SEG22 / CKOTX1 / OUT1 / INT15
85
J
P01_3 / SEG23 / PPG5
86
P
P01_4 / SEG24 / SIN4 / INT8
87
J
P01_5 / SEG25 / SOT4
88
P
P01_6 / SEG26 / SCK4 / TTG12
89
J
P01_7 / SEG27 / CKOTX1_R / INT9 / TTG13
90
J
P02_0 / SEG28 / CKOT1_R / INT10 / TTG14
91
J
P02_2 / SEG30 / IN7_R / CKOT0_R / INT12
92
P
P02_5 / SEG33 / OUT0_R / INT13 / SIN5_R
93
L
P03_0 / V0 / SEG36 / PPG4_B
94
L
P03_1 / V1 / SEG37 / PPG5_B
95
L
P03_2 / V2 / SEG38 / PPG14_B / SOT5_R
96
Q
P03_3 / V3 / SEG39 / PPG15_B / SCK5_R
97
M
P03_4 / RX0 / INT4
98
H
P03_5 / TX0
99
H
P03_6 / INT0 / NMI
100
Supply
Vcc
*: See I/O Circuit Type” for details on the I/O circuit types.
Document Number: 002-04717 Rev *A
Page 14 of 75
MB96690 Series
6.
I/O Circuit Type
Type
Circuit
Remarks
High-speed oscillation circuit:
A
Programmable between
X1
oscillation mode (external crystal
or resonator connected to X0/X1
pins) and Fast external Clock
Input (FCI) mode (external clock
connected to X0 pin)
R
Feedback resistor = approx.
0
1
X out
1.0MΩ
The amplitude: 1.8V±0.15V
to operate by the internal supply
voltage
FCI
X0
FCI or Osc disable
Document Number: 002-04717 Rev *A
Page 15 of 75
MB96690 Series
Type
Circuit
Remarks
B
Pull-up control
Low-speed oscillation circuit shared
with GPIO functionality:
Feedback resistor = approx.
5.0MΩ
P-ch
Standby
control
for input
shutdown
P-ch
N-ch
GPIO functionality selectable
Pout
(CMOS level output (IOL = 4mA,
IOH = -4mA), Automotive input with
input shutdown function and
programmable pull-up resistor)
Nout
R
Automotive input
X1A
R
X out
0
1
FCI
X0A
FCI or Osc disable
Pull-up control
P-ch
Standby
control
for input
shutdown
P-ch
Pout
N-ch
Nout
R
Document Number: 002-04717 Rev *A
Automotive input
Page 16 of 75
MB96690 Series
Type
Circuit
Remarks
CMOS hysteresis input pin
C
R
Hysteresis
inputs
Power supply input protection circuit
F
P-ch
N-ch
G
A/D converter ref+ (AVRH)/ ref(AVRL) power supply input pin
with protection circuit
P-ch
Without protection circuit against
VCC for pins AVRH/AVRL
N-ch
H
CMOS level output (IOL = 4mA, IOH
Pull-up control
= -4mA)
Automotive input with input
shutdown function
P-ch
P-ch
Pout
N-ch
Nout
Programmable pull-up resistor
R
Standby control
for input shutdown
Document Number: 002-04717 Rev *A
Automotive input
Page 17 of 75
MB96690 Series
Type
Circuit
Remarks
I
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis input with input
shutdown function
P-ch
P-ch
N-ch
Pout
Programmable pull-up resistor
Analog input
Nout
R
Hysteresis input
Standby control
for input shutdown
Analog input
J
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
P-ch
P-ch
Pout
Programmable pull-up resistor
SEG or COM output
N-ch
Nout
R
Automotive input
Standby control
for input shutdown
SEG or COM output
K
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
P-ch
P-ch
Pout
Programmable pull-up resistor
Analog input
N-ch
Nout
R
Automotive input
Standby control
for input shutdown
Analog input
Document Number: 002-04717 Rev *A
Page 18 of 75
MB96690 Series
Type
Circuit
Remarks
L
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
P-ch
P-ch
Pout
Programmable pull-up resistor
Vn input or SEG output
N-ch
Nout
R
Automotive input
Standby control
for input shutdown
Vn input or SEG output
M
CMOS level output
(IOL = 4mA, IOH = -4mA)
Pull-up control
CMOS hysteresis input with input
shutdown function
Programmable pull-up resistor
P-ch
P-ch
Pout
N-ch
Nout
R
Hysteresis input
Standby control
for input shutdown
N
CMOS level output
(IOL = 3mA, IOH = -3mA)
Pull-up control
CMOS hysteresis input with input
shutdown function
Programmable pull-up resistor
P-ch
R
P-ch
Pout
N-ch
Nout*
*: N-channel transistor has slew rate
2
control according to I C spec,
irrespective of usage.
Hysteresis input
Standby control
for input shutdown
Document Number: 002-04717 Rev *A
Page 19 of 75
MB96690 Series
Type
Circuit
Remarks
O
Open-drain I/O
Output 25mA, Vcc = 2.7V
TTL input
N-ch
Nout
R
Standby control
for input shutdown
TTL input
P
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis inputs with input
shutdown function
P-ch
P-ch
Pout
Programmable pull-up resistor
SEG or COM output
N-ch
Nout
R
Hysteresis input
Standby control
for input shutdown
SEG or COM output
Q
CMOS level output
Pull-up control
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis inputs with input
shutdown function
P-ch
P-ch
Pout
Programmable pull-up resistor
Vn input or SEG output
N-ch
Nout
R
Hysteresis input
Standby control
for input shutdown
Vn input or SEG output
Document Number: 002-04717 Rev *A
Page 20 of 75
MB96690 Series
Type
Circuit
Remarks
R
CMOS level output
Pull-up control
P-ch
P-ch
Pout
(programmable IOL = 4mA, IOH =
-4mA and IOL = 30mA, IOH =
-30mA)
Automotive input with input
shutdown function
Programmable pull-up / pull-down
resistor
N-ch
N-ch
Nout
Analog input
Pull-down control
R
Automotive input
Standby control
for input shutdown
Analog input
S
CMOS level output
Pull-up control
(programmable IOL = 4mA, IOH =
-4mA and IOL = 30mA, IOH =
-30mA)
CMOS hysteresis input with input
P-ch
P-ch
Pout
shutdown function
Programmable pull-up / pull-down
resistor
N-ch
N-ch
Nout
Analog input
Pull-down control
R
Hysteresis input
Standby control
for input shutdown
Analog input
Document Number: 002-04717 Rev *A
Page 21 of 75
MB96690 Series
7.
Memory Map
FF:FFFFH
USER ROM*1
DE:0000H
DD:FFFFH
Reserved
10:0000H
0F:C000H
Boot-ROM
Peripheral
0E:9000H
Reserved
01:0000H
00:8000H
RAMSTART0*2
ROM/RAM
MIRROR
Internal RAM
bank0
Reserved
00:0C00H
00:0380H
Peripheral
00:0180H
GPR*3
00:0100H
DMA
00:00F0H
Reserved
00:0000H
Peripheral
*1: For details about USER ROM area, see ”User ROM Memory Map For Flash Devices” on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
Document Number: 002-04717 Rev *A
Page 22 of 75
MB96690 Series
8.
RAM start Addresses
Bank 0
Devices
RAM size
RAMSTART0
MB96F693
MB96F695
8KB
00:6200H
MB96F696
16KB
00:4200H
Document Number: 002-04717 Rev *A
Page 23 of 75
MB96690 Series
9.
User ROM Memory Map For Flash Devices
MB96F693
CPU mode
address
Flash memory
mode address
FF:FFFFH
3F:FFFFH
FF:0000H
3F:0000H
FE:FFFFH
3E:FFFFH
FE:0000H
3E:0000H
FD:FFFFH
3D:FFFFH
FD:0000H
3D:0000H
FC:FFFFH
3C:FFFFH
FC:0000H
3C:0000H
MB96F695
MB96F696
Flash size
Flash size
Flash size
64.5KB + 32KB
128.5KB + 32KB
256.5KB + 32KB
SA39 - 64KB
SA39 - 64KB
SA39 - 64KB
SA38 - 64KB
SA38 - 64KB
Bank A of Flash A
SA37 - 64KB
SA36 - 64KB
FB:FFFFH
Reserved
Reserved
Reserved
DF:A000H
DF:9FFFH
1F:9FFFH
DF:8000H
1F:8000H
DF:7FFFH
1F:7FFFH
DF:6000H
1F:6000H
DF:5FFFH
1F:5FFFH
DF:4000H
1F:4000H
DF:3FFFH
1F:3FFFH
DF:2000H
1F:2000H
DF:1FFFH
1F:1FFFH
DF:0000H
1F:0000H
DE:FFFFH
DE:0000H
SA4 - 8KB
SA4 - 8KB
SA4 - 8KB
SA3 - 8KB
SA3 - 8KB
SA3 - 8KB
SA2 - 8KB
SA2 - 8KB
SA2 - 8KB
SA1 - 8KB
SA1 - 8KB
SA1 - 8KB
SAS - 512B*
SAS - 512B*
SAS - 512B*
Reserved
Reserved
Reserved
Bank B of Flash A
Bank A of Flash A
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
SAS cannot be used for E2PROM emulation.
Document Number: 002-04717 Rev *A
Page 24 of 75
MB96690 Series
10.
Serial Programming Communication Interface
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
MB96690
Pin Number
USART Number
8
9
Normal Function
SIN0
USART0
SOT0
10
SCK0
3
SIN1
4
USART1
SOT1
5
SCK1
46
SIN2
47
USART2
SOT2
48
SCK2
86
SIN4
87
USART4
88
Document Number: 002-04717 Rev *A
SOT4
SCK4
Page 25 of 75
MB96690 Series
11.
Interrupt Vector Table
Vector
Offset in
number
vector table
Cleared by
Index in
DMA
ICR to program
0
3FCH
CALLV0
No
-
CALLV instruction
1
2
3F8H
CALLV1
No
-
CALLV instruction
3F4H
CALLV2
No
-
CALLV instruction
3
3F0H
CALLV3
No
-
CALLV instruction
4
3ECH
CALLV4
No
-
CALLV instruction
5
3E8H
CALLV5
No
-
CALLV instruction
6
3E4H
CALLV6
No
-
CALLV instruction
7
3E0H
CALLV7
No
-
CALLV instruction
8
3DCH
RESET
No
-
Reset vector
9
3D8H
INT9
No
-
INT9 instruction
10
3D4H
EXCEPTION
No
-
Undefined instruction execution
11
3D0H
NMI
No
-
Non-Maskable Interrupt
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Clock Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
LVDI
No
16
Low Voltage Detector
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
EXTINT5
Yes
22
External Interrupt 5
23
3A0H
EXTINT6
Yes
23
External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
EXTINT8
Yes
25
External Interrupt 8
26
394H
EXTINT9
Yes
26
External Interrupt 9
27
390H
EXTINT10
Yes
27
External Interrupt 10
28
38CH
EXTINT11
Yes
28
External Interrupt 11
29
388H
EXTINT12
Yes
29
External Interrupt 12
30
384H
EXTINT13
Yes
30
External Interrupt 13
31
380H
EXTINT14
Yes
31
External Interrupt 14
32
37CH
EXTINT15
Yes
32
External Interrupt 15
33
378H
CAN0
No
33
CAN Controller 0
34
374H
-
-
34
Reserved
35
370H
-
-
35
Reserved
36
36CH
-
-
36
Reserved
37
368H
-
-
37
Reserved
Vector name
Document Number: 002-04717 Rev *A
Description
Page 26 of 75
MB96690 Series
Vector
Offset in
number
vector table
Cleared by
Index in
DMA
ICR to program
38
364H
39
360H
PPG0
Yes
38
Programmable Pulse Generator 0
PPG1
Yes
39
Programmable Pulse Generator 1
40
35CH
PPG2
Yes
40
Programmable Pulse Generator 2
41
358H
PPG3
Yes
41
Programmable Pulse Generator 3
42
354H
PPG4
Yes
42
Programmable Pulse Generator 4
43
350H
PPG5
Yes
43
Programmable Pulse Generator 5
44
34CH
PPG6
Yes
44
Programmable Pulse Generator 6
45
348H
PPG7
Yes
45
Programmable Pulse Generator 7
46
344H
-
-
46
Reserved
47
340H
-
-
47
Reserved
48
33CH
-
-
48
Reserved
49
338H
-
-
49
Reserved
50
334H
-
-
50
Reserved
51
330H
-
-
51
Reserved
52
32CH
PPG14
Yes
52
Programmable Pulse Generator 14
53
328H
PPG15
Yes
53
Programmable Pulse Generator 15
54
324H
-
-
54
Reserved
55
320H
-
-
55
Reserved
56
31CH
-
-
56
Reserved
57
318H
-
-
57
Reserved
58
314H
RLT0
Yes
58
Reload Timer 0
59
310H
RLT1
Yes
59
Reload Timer 1
60
30CH
RLT2
Yes
60
Reload Timer 2
61
308H
RLT3
Yes
61
Reload Timer 3
62
304H
-
-
62
Reserved
63
300H
-
-
63
Reserved
64
2FCH
RLT6
Yes
64
Reload Timer 6
65
2F8H
ICU0
Yes
65
Input Capture Unit 0
66
2F4H
ICU1
Yes
66
Input Capture Unit 1
67
2F0H
-
-
67
Reserved
68
2ECH
-
-
68
Reserved
69
2E8H
ICU4
Yes
69
Input Capture Unit 4
70
2E4H
ICU5
Yes
70
Input Capture Unit 5
71
2E0H
ICU6
Yes
71
Input Capture Unit 6
72
2DCH
ICU7
Yes
72
Input Capture Unit 7
73
2D8H
-
-
73
Reserved
74
2D4H
-
-
74
Reserved
75
2D0H
-
-
75
Reserved
76
2CCH
-
-
76
Reserved
77
2C8H
OCU0
Yes
77
Output Compare Unit 0
Vector name
Document Number: 002-04717 Rev *A
Description
Page 27 of 75
MB96690 Series
Vector
Offset in
number
vector table
Cleared by
Index in
DMA
ICR to program
78
2C4H
79
2C0H
OCU1
Yes
78
Output Compare Unit 1
OCU2
Yes
79
Output Compare Unit 2
80
2BCH
OCU3
Yes
80
Output Compare Unit 3
81
2B8H
-
-
81
Reserved
82
2B4H
-
-
82
Reserved
83
2B0H
-
-
83
Reserved
84
2ACH
-
-
84
Reserved
85
2A8H
-
-
85
Reserved
86
2A4H
-
-
86
Reserved
87
2A0H
-
-
87
Reserved
88
29CH
-
-
88
Reserved
89
298H
FRT0
Yes
89
Free-Running Timer 0
90
294H
FRT1
Yes
90
Free-Running Timer 1
91
290H
-
-
91
Reserved
92
28CH
-
-
92
Reserved
93
288H
RTC0
No
93
Real Time Clock
94
284H
CAL0
No
94
Clock Calibration Unit
95
280H
SG0
No
95
Sound Generator 0
96
27CH
IIC0
Yes
96
I C interface 0
97
278H
-
-
97
Reserved
98
274H
ADC0
Yes
98
A/D Converter 0
99
270H
-
-
99
Reserved
100
26CH
-
-
100
Reserved
101
268H
LINR0
Yes
101
LIN USART 0 RX
102
264H
LINT0
Yes
102
LIN USART 0 TX
103
260H
LINR1
Yes
103
LIN USART 1 RX
104
25CH
LINT1
Yes
104
LIN USART 1 TX
105
258H
LINR2
Yes
105
LIN USART 2 RX
106
254H
LINT2
Yes
106
LIN USART 2 TX
107
250H
-
-
107
Reserved
108
24CH
-
-
108
Reserved
109
248H
LINR4
Yes
109
LIN USART 4 RX
110
244H
LINT4
Yes
110
LIN USART 4 TX
111
240H
LINR5
Yes
111
LIN USART 5 RX
112
23CH
LINT5
Yes
112
LIN USART 5 TX
113
238H
-
-
113
Reserved
114
234H
-
-
114
Reserved
115
230H
-
-
115
Reserved
116
22CH
-
-
116
Reserved
117
228H
-
-
117
Reserved
Vector name
Document Number: 002-04717 Rev *A
Description
2
Page 28 of 75
MB96690 Series
Vector
Offset in
number
vector table
Cleared by
Index in
DMA
ICR to program
118
224H
119
220H
-
-
118
Reserved
-
-
119
Reserved
120
21CH
-
-
120
Reserved
121
218H
SG1
No
121
Sound Generator 1
122
214H
-
-
122
Reserved
123
210H
-
-
123
Reserved
124
20CH
-
-
124
Reserved
125
208H
-
-
125
Reserved
126
204H
-
-
126
Reserved
127
200H
-
-
127
Reserved
128
1FCH
-
-
128
Reserved
129
1F8H
-
-
129
Reserved
130
1F4H
-
-
130
Reserved
131
1F0H
-
-
131
Reserved
132
1ECH
-
-
132
Reserved
133
1E8H
FLASHA
Yes
133
Flash memory A interrupt
134
1E4H
-
-
134
Reserved
135
1E0H
-
-
135
Reserved
136
1DCH
-
-
136
Reserved
137
1D8H
-
-
137
Reserved
138
1D4H
-
-
138
Reserved
139
1D0H
ADCRC0
No
139
A/D Converter 0 - Range Comparator
140
1CCH
ADCPD0
No
140
A/D Converter 0 - Pulse detection
141
1C8H
-
-
141
Reserved
142
1C4H
-
-
142
Reserved
143
1C0H
-
-
143
Reserved
Vector name
Document Number: 002-04717 Rev *A
Description
Page 29 of 75
MB96690 Series
12.
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions
that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress
semiconductor devices.
12.1
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Users considering application outside the listed conditions are advised to contact their sales representative
beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or
over-current conditions at the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current
flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should
be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected
to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing
large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is
called latch-up.
CAUTION:
The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1.
2.
Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention
to abnormal noise, surge levels, etc.
Be sure that abnormal current flows do not occur during the power-on sequence.
Document Number: 002-04717 Rev *A
Page 30 of 75
MB96690 Series
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the
design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are
demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls,
medical devices for life support, etc.) are requested to consult with sales representatives before such use. The
company will not be responsible for damages arising from such use without prior approval.
12.2
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on
the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket
contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established
a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
Document Number: 002-04717 Rev *A
Page 31 of 75
MB96690 Series
Lead-Free Packaging
CAUTION:
When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
1.
2.
3.
4.
Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locations where temperature changes are slight.
Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the
following precautions:
1.
2.
3.
4.
5.
Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion
generation may be needed to remove electricity.
Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on
the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
Ground all fixtures and instruments, or protect with anti-static measures.
Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-04717 Rev *A
Page 32 of 75
MB96690 Series
12.3
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1.
Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels
are anticipated, consider anti-humidity processing.
2.
Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such
cases, use anti-static measures or processing to prevent discharges.
3.
Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the
device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
5. Smoke, Flame
CAUTION:
Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
Document Number: 002-04717 Rev *A
Page 33 of 75
MB96690 Series
13.
Handling Devices
Special care is required for the following when handling the device:
Latch-up prevention
Unused pins handling
External clock usage
Notes on PLL clock mode operation
Power supply pins (Vcc/Vss)
Crystal oscillator and ceramic resonator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on Power-on
Stabilization of power supply voltage
SMC power supply pins
Serial communication
Mode Pin (MD)
13.1
Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed the
digital power-supply voltage.
13.2
Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which
should be more than 2kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
13.3
External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be
connected as follows:
13.3.1 Single phase external clock for Main oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
Document Number: 002-04717 Rev *A
Page 34 of 75
MB96690 Series
X0
X1
13.3.2 Single phase external clock for Sub oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and
X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO.
13.3.3 Opposite phase external clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has the
opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
X0
X1
13.4
Notes on PLL clock mode operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is
supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however,
cannot be guaranteed.
13.5
Power supply pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than
one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1µF
between Vcc and Vss pins as close as possible to Vcc and Vss pins.
13.6
Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground
lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a
ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
Document Number: 002-04717 Rev *A
Page 35 of 75
MB96690 Series
13.7
Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the
digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case,
AVRH must not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC
(turning the analog and digital power supplies simultaneously on or off is acceptable).
13.8
Pin handling when not using the A/D converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC ,
AVSS = AVRH = AVRL = VSS.
13.9
Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2V to 2.7V.
13.10
Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a
malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the
power supply voltage must be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the
commercial frequencies (50Hz to 60Hz) fall within 10% of the standard VCC power supply voltage and the transient
fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
13.11
SMC power supply pins
All DVcc /DVss pins must be set to the same level as the Vcc /Vss pins.
Note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, VCC must
always be powered on before DVCC.
DVCC/DVSS must be applied when using SMC I/O pin as GPIO.
13.12
Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13.13
Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise,
lay out the printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a
low-impedance connection.
Document Number: 002-04717 Rev *A
Page 36 of 75
MB96690 Series
14.
Electrical Characteristics
14.1
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
VCC
-
Min
VSS - 0.3
Analog power supply
[1]
voltage
AVCC
-
VSS - 0.3
Analog reference
AVRH,
Power supply voltage
[1]
Unit
Max
VSS + 6.0
V
VSS + 6.0
V
Remarks
VCC = AVCC
[2]
AVCC≥ AVRH,
voltage
[1]
AVRL
-
VSS - 0.3
VSS + 6.0
V
AVCC ≥ AVRL,
AVRH > AVRL,
AVRL ≥ AVSS
[1]
[2]
SMC Power supply
DVCC
-
VSS - 0.3
VSS + 6.0
V
VCC = AVCC= DVCC
LCD power supply
[1]
voltage
V0 to V3
-
VSS - 0.3
VSS + 6.0
V
V0 to V3 must not exceed
VCC
VI
-
VSS - 0.3
VSS + 6.0
V
VI ≤ (D)VCC + 0.3V
VO
-
VSS - 0.3
VSS + 6.0
V
VO ≤ (D)VCC + 0.3V
Maximum Clamp
Current
ICLAMP
-
-4.0
+4.0
mA
Applicable to general
[4]
purpose I/O pins
Total Maximum Clamp
Current
Σ|ICLAMP|
-
25
mA
Applicable to general
[4]
purpose I/O pins
Normal port
Input voltage
[1]
Output voltage
[1]
-
-
15
mA
TA= -40°C
-
52
mA
TA= +25°C
-
39
mA
TA= +85°C
-
32
mA
TA= +105°C
-
30
mA
IOL
"L" level maximum
output current
IOLSMC
IOLAV
"L" level average output
current
IOLAVSMC
-
-
-
4
mA
TA= -40°C
-
40
mA
TA= +25°C
-
30
mA
TA= +85°C
-
25
mA
TA= +105°C
-
23
mA
[3]
High current port
Normal port
High current port
"L" level maximum
overall output current
ΣIOL
-
-
50
mA
Normal port
ΣIOLSMC
-
-
260
mA
High current port
"L" level average
overall output current
ΣIOLAV
-
-
25
mA
Normal port
ΣIOLAVSMC
-
-
170
mA
High current port
Document Number: 002-04717 Rev *A
[3]
Page 37 of 75
MB96690 Series
Parameter
Symbol
"H" level maximum
output current
IOH
IOHSMC
IOHAV
"H" level average
output current
IOHAVSMC
Condition
Rating
Unit
Min
-
Max
-15
mA
TA= -40°C
-
-52
mA
TA= +25°C
-
-39
mA
TA= +85°C
-
-32
mA
TA= +105°C
-
-30
mA
-
-
-4
mA
TA= -40°C
-
-
-40
mA
TA= +25°C
-
-30
mA
TA= +85°C
-
-25
mA
TA= +105°C
-
-23
mA
Remarks
Normal port
High current port
Normal port
High current port
"H" level maximum
overall output current
ΣIOH
-
-
-50
mA
Normal port
ΣIOHSMC
-
-
-260
mA
High current port
"H" level average
overall output current
ΣIOHAV
-
-
-25
mA
Normal port
ΣIOHAVSMC
-
-
-170
mA
High current port
PD
TA= +105°C
-
333
Operating ambient
temperature
TA
-
-40
+105
°C
Storage temperature
TSTG
-
-55
+150
°C
Power consumption
[5]
[6]
mW
[1]: This parameter is based on VSS = AVSS = DVSS = 0V.
[2]: AVCC and VCC and DVCC must be set to the same voltage. It is required that AVCC does not exceed VCC, DVCC and
that the voltage at the analog inputs does not exceed AVCC when the power is switched on.
[3]: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
Input/Output voltages of high current ports depend on DVCC. Input/Output voltages of standard ports depend on VCC.
[4]:
Applicable to all general purpose I/O pins (Pnn_m).
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
The value of the limiting resistance should be set so that when the +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential
may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is
provided from the pins, so that incomplete operation may result.
Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the Power reset.
The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping
current (4mA). For protection against positive input voltages, use an external clamping diode which limits the input
voltage to maximum 6.0V.
Document Number: 002-04717 Rev *A
Page 38 of 75
MB96690 Series
Sample recommended circuits:
Protective diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
[5]: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL × IOL + VOH × IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC × (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
[6]: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
WARNING:
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
14.2
Recommended Operating Conditions
(VSS = AVSS = DVSS = 0V)
Parameter
Symbol
VCC,
Power supply voltage
AVCC,
DVCC
Value
Min
2.7
Typ
-
Max
5.5
2.0
-
5.5
Unit
Remarks
V
V
Maintains RAM data in stop mode
1.0µF (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Smoothing capacitor at
C pin
CS
0.5
1.0 to 3.9
4.7
µF
Please use the ceramic capacitor or the
capacitor of the frequency response of this
level.
The smoothing capacitor at VCC must use
the one of a capacity value that is larger
than CS.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is operated
within these ranges. Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is
made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
Document Number: 002-04717 Rev *A
Page 39 of 75
MB96690 Series
14.3
DC Characteristics
14.3.1 Current Rating
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Pin
Parameter
Symbol
nam
Value
Conditions
Max
-
28
-
mA
TA = +25°C
-
-
38
mA
TA = +105°C
-
3.5
-
mA
TA = +25°C
(CLKPLL, CLKSC and
CLKRC stopped)
-
-
8
mA
TA = +105°C
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
2MHz
-
1.8
-
mA
TA = +25°C
(CLKMC, CLKPLL and
CLKSC stopped)
-
-
6
mA
TA = +105°C
RC Run mode with CLKS1/2 =
CLKB = CLKP1/2 = CLKRC =
100kHz
-
0.16
-
mA
TA = +25°C
(CLKMC, CLKPLL and CLKSC
stopped)
-
-
3.5
mA
TA = +105°C
Sub Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32kHz
-
0.1
-
mA
TA = +25°C
-
-
3.3
mA
TA = +105°C
Flash 0 wait
(CLKRC and CLKSC stopped)
Main Run mode with CLKS1/2
= CLKB = CLKP1/2 = 4MHz
Flash 0 wait
ICCMAIN
Power supply
current in Run
[1]
modes
ICCRCH
Remarks
Typ
PLL Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 32MHz
ICCPLL
Unit
Min
e
Vcc
ICCRCL
ICCSUB
Flash 0 wait
Flash 0 wait
Flash 0 wait
(CLKMC, CLKPLL and
CLKRC stopped)
Document Number: 002-04717 Rev *A
Page 40 of 75
MB96690 Series
Parameter
Symbol
Pin
name
Value
Conditions
Max
-
9.5
-
-
-
15
mA
TA = +105°C
-
1.1
-
mA
TA = +25°C
-
-
4.7
mA
TA = +105°C
-
0.6
-
mA
TA = +25°C
-
-
4.1
mA
TA = +105°C
RC Sleep mode with CLKS1/2 =
CLKP1/2 = CLKRC = 100kHz
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.07
-
mA
TA = +25°C
-
-
2.9
mA
TA = +105°C
Sub Sleep mode with CLKS1/2
= CLKP1/2 = 32kHz,
(CLKMC, CLKPLL and CLKRC
stopped)
-
0.04
-
mA
TA = +25°C
-
-
2.7
mA
TA = +105°C
-
1800
2250
µA
TA = +25°C
-
-
3220
µA
TA = +105°C
Main Timer mode with CLKMC =
4MHz, SMCR:LPMSS = 0
(CLKPLL, CLKRC and CLKSC
stopped)
-
285
330
µA
TA = +25°C
-
-
1200
µA
TA = +105°C
RC Timer mode with CLKRC =
2MHz, SMCR:LPMSS = 0
(CLKPLL, CLKMC and CLKSC
stopped)
-
160
215
µA
TA = +25°C
-
-
1110
µA
TA = +105°C
RC Timer mode with CLKRC =
100kHz, (CLKPLL, CLKMC and
CLKSC stopped)
-
35
75
µA
TA = +25°C
-
-
910
µA
TA = +105°C
-
25
65
µA
TA = +25°C
Main Sleep mode with CLKS1/2
= CLKP1/2 = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and CLKSC
stopped)
ICCSMAIN
Vcc
ICCSRCL
ICCSSUB
ICCTMAIN
ICCTRCH
RC Sleep mode with CLKS1/2 =
CLKP1/2 = CLKRC = 2MHz,
SMCR:LPMSS = 0 (CLKMC,
CLKPLL and CLKSC stopped)
PLL Timer mode with CLKPLL =
32MHz (CLKRC and CLKSC
stopped)
ICCTPLL
Power supply
current in
[2]
Timer modes
mA
TA = +25°C
CLKS1/2 = CLKP1/2 = 32MHz
(CLKRC and CLKSC stopped)
ICCSRCH
Remarks
Typ
PLL Sleep mode with
ICCSPLL
Power supply
current in
[1]
Sleep modes
Unit
Min
Vcc
ICCTRCL
ICCTSUB
Document Number: 002-04717 Rev *A
Sub Timer mode with CLKSC =
32kHz (CLKMC, CLKPLL and
CLKRC stopped)
-
-
885
µA
TA = +105°C
Page 41 of 75
MB96690 Series
Parameter
Symbol
Power supply
current in Stop
[3]
mode
Flash Power
Down current
Pin
ICCH
Unit
Remarks
Min
Typ
Max
-
20
60
µA
TA = +25°C
-
-
880
µA
TA = +105°C
-
36
70
µA
-
5
-
µA
TA = +25°C
-
-
12.5
µA
TA = +105°C
-
12.5
-
mA
TA = +25°C
-
-
20
mA
TA = +105°C
-
ICCFLASHP
-
D
Power supply
current
for active Low
Vcc
ICCLVD
Low voltage detector
enabled
Voltage
[4]
detector
Flash Write/
Erase current
Value
Conditions
name
[5]
ICCFLASH
-
[1]: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control
circuit” of the Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part
is not included. Power supply current in Run mode does not include Flash Write / Erase current.
[2]: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32 kHz
external clock connected to the Sub oscillator. The current for "On Chip Debugger" part is not included.
[3]: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
[4]: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
[5]: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
Document Number: 002-04717 Rev *A
Page 42 of 75
MB96690 Series
14.3.2 Pin Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
VIH
Port
inputs
Pnn_m
Value
Conditions
Min
Typ
Max
Unit
Remarks
-
VCC×0.7
-
VCC+ 0.3
V
CMOS Hysteresis
input
-
VCC×0.8
-
VCC+ 0.3
V
AUTOMOTIVE
Hysteresis input
VD×0.8
-
VD
V
VD=1.8V±0.15V
VCC×0.8
-
VCC+ 0.3
V
External clock in
"H" level
input voltage
"L" level input
voltage
VIHX0S
X0
VIHX0AS
X0A
VIHR
RSTX
-
VCC×0.8
-
VCC+ 0.3
V
CMOS Hysteresis
input
VIHM
MD
-
VCC- 0.3
-
VCC+ 0.3
V
CMOS Hysteresis
input
VIHD
DEBUG
I/F
-
2.0
-
VCC+ 0.3
V
TTL Input
-
VSS- 0.3
-
VCC×0.3
V
VIL
Port
inputs
Pnn_m
CMOS Hysteresis
input
-
VSS- 0.3
-
VCC×0.5
V
AUTOMOTIVE
Hysteresis input
External clock in
"Fast Clock Input
mode"
VSS
-
VD×0.2
V
VD=1.8V±0.15V
VSS- 0.3
-
VCC×0.2
V
"Fast Clock Input
mode"
External clock in
"Oscillation mode"
VILX0S
X0
VILX0AS
X0A
VILR
RSTX
-
VSS- 0.3
-
VCC×0.2
V
CMOS Hysteresis
input
VILM
MD
-
VSS- 0.3
-
VSS+ 0.3
V
CMOS Hysteresis
input
VILD
DEBUG
I/F
-
VSS- 0.3
-
0.8
V
TTL Input
Document Number: 002-04717 Rev *A
External clock in
"Oscillation mode"
Page 43 of 75
MB96690 Series
Parameters
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
4.5V ≤ (D)VCC ≤ 5.5V
IOH = -4mA
2.7V ≤ (D)VCC < 4.5V
(D)VCC- 0.5
-
(D)VCC
V
IOH = -1.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -52mA
TA = -40°C
2.7V ≤ DVCC < 4.5V
IOH = -18mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -39mA
TA = +25°C
2.7V ≤ DVCC < 4.5V
"H" level
output
voltage
VOH30
High
Drive
*
type
IOH = -16mA
4.5V ≤ DVCC ≤ 5.5V
DVCC- 0.5
-
DVCC
V
IOH = -32mA
TA = +85°C
2.7V ≤ DVCC < 4.5V
IOH = -14.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
TA = +105°C
2.7V ≤ DVCC < 4.5V
IOH = -14mA
4.5V ≤ VCC ≤ 5.5V
VOH3
3mA type
IOH = -3mA
2.7V ≤ VCC < 4.5V
VCC- 0.5
-
VCC
V
IOH = -1.5mA
Document Number: 002-04717 Rev *A
Page 44 of 75
MB96690 Series
Parameters
Symbol
Pin name
Value
Conditions
Min
Typ
Max
-
0.4
Unit
Remarks
4.5V ≤ (D)VCC ≤ 5.5V
IOL = +4mA
2.7V ≤ (D)VCC < 4.5V
-
V
IOL = +1.7mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +52mA
TA = -40°C
2.7V ≤ DVCC < 4.5V
IOL = +22mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +39mA
TA = +25°C
2.7V ≤ DVCC < 4.5V
"L" level
output
voltage
VOL30
High
Drive
*
type
IOL = +18mA
4.5V ≤ DVCC ≤ 5.5V
-
-
0.5
V
IOL = +32mA
TA = +85°C
2.7V ≤ DVCC < 4.5V
IOL = +14mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +30mA
TA = +105°C
2.7V ≤ DVCC < 4.5V
IOL = +13.5mA
VOL3
3mA type
VOLD
DEBUG
I/F
2.7V ≤ VCC < 5.5V
IOL = +3mA
VCC = 2.7V
IOL = +25mA
-
-
0.4
V
0
-
0.25
V
Single port
pin
VSS < VI < VCC
Input leak
current
Pnn_m
AVSS, AVRL < VI <
AVCC, AVRH
P08_m,
DVSS < VI < DVCC
P09_m,
AVSS, AVRL < VI <
AVCC, AVRH
-
+1
µA
-3
-
+3
µA
IIL
P10_m
Total LCD
leak current
-1
Σ|IILCD|
All SEG/
COM pin
VCC = 5.0V
-
0.5
10
µA
VCC = 5.0V
6.25
12.5
25
kΩ
except high
current
output I/O for
SMC
Maximum
leakage
current of all
LCD pins
Between
Internal LCD
divide
resistance
RLCD
V3 and
V2, V2
and V1,
V1 and
V0
Document Number: 002-04717 Rev *A
Page 45 of 75
MB96690 Series
Parameters
Pull-up
resistance
Symbol
Pin-name
RPU
Pnn_m
Values
Conditions
Unit
Typ
Max
50
100
kΩ
25
50
100
kΩ
-
-
5
15
pF
-
-
15
30
pF
VCC = 5.0V ±10%
Min
25
Remarks
value
Pull-down
resistance
P08_m,
RDOWN
value
Input
capacitance
P09_m,
VCC = 5.0V ±10%
P10_m
CIN
Other
than C,
Vcc,
Vss,
DVcc,
DVss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
P08_m,
P09_m,
P10_m
*: In the case of driving stepping motor directly or high current outputs, set "1" to the bit in the Port High Drive Register
(PHDRnn:HDx="1").
Document Number: 002-04717 Rev *A
Page 46 of 75
MB96690 Series
14.4
AC Characteristics
14.4.1 Main Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Input frequency
Input frequency
fC
fFCI
Value
Pin
Symbol
name
Unit
Min
Typ
Max
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
-
-
8
MHz
4
-
8
MHz
X0, X1
X0
Input clock cycle
tCYLH
-
125
-
-
ns
Input clock pulse width
PWH, PWL
-
55
-
-
ns
Remarks
When using a crystal
oscillator, PLL off
When using an opposite
phase external clock, PLL off
When using a crystal
oscillator or opposite phase
external clock, PLL on
When using a single phase
external clock in “Fast Clock
Input mode”, PLL off
When using a single phase
external clock in “Fast Clock
Input mode”, PLL on
When using the crystal oscillator
tCYLH
Reference value:
1.8V±0.15V
X0,X1
The amplitude changes by resistance, capacity which added outside or the difference of the device.
When using the external clock
tCYLH
X0
VIHX0S
VIHX0S
VILX0S
PWH
Document Number: 002-04717 Rev *A
VIHX0S
VILX0S
PWL
Page 47 of 75
MB96690 Series
14.4.2 Sub Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin name
Value
Conditions
Unit
Typ
Max
-
-
32.768
-
kHz
When using an
oscillation circuit
-
-
-
100
kHz
When using an
opposite phase
external clock
X0A
-
-
-
50
kHz
When using a
single phase
external clock
X0A, X1A
Input frequency
Remarks
Min
fCL
Input clock cycle
tCYLL
-
-
10
-
-
µs
Input clock pulse
width
-
-
PWH/tCYLL,
PWL/tCYLL
30
-
70
%
When using the crystal oscillator
tCYLL
VCC
X0A,X1A
When using the external clock
tCYLL
X0A
VIHX0AS
VIHX0AS
VILX0AS
PWH
Document Number: 002-04717 Rev *A
VIHX0AS
VILX0AS
PWL
Page 48 of 75
MB96690 Series
14.4.3 Built-in RC Oscillation Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Clock frequency
RC clock stabilization
time
Value
Symbol
Min
Typ
Max
Unit
Remarks
50
100
200
kHz
When using slow frequency of RC
oscillator
1
2
4
MHz
When using fast frequency of RC
oscillator
80
160
320
µs
When using slow frequency of RC
oscillator (16 RC clock cycles)
64
128
256
µs
When using fast frequency of RC
oscillator (256 RC clock cycles)
fRC
tRCSTAB
14.4.4 Internal Clock Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Min
Max
Internal System clock frequency (CLKS1 and CLKS2)
fCLKS1, fCLKS2
-
54
MHz
Internal CPU clock frequency (CLKB), Internal
peripheral clock frequency (CLKP1)
fCLKB, fCLKP1
-
32
MHz
Internal peripheral clock frequency (CLKP2)
fCLKP2
-
32
MHz
Document Number: 002-04717 Rev *A
Page 49 of 75
MB96690 Series
14.4.5 Operating Conditions of PLL
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Unit
Min
Typ
Remarks
Max
PLL oscillation stabilization wait time
tLOCK
1
-
4
ms
For CLKMC = 4MHz
PLL input clock frequency
fPLLI
4
-
8
MHz
PLL oscillation clock frequency
fCLKVCO
56
-
108
MHz
Permitted VCO output
frequency of PLL (CLKVCO)
PLL phase jitter
tPSKEW
-5
-
+5
ns
For CLKMC (PLL input clock)
≥ 4MHz
Deviation time from the ideal clock is assured per cycle out of 20,000 cycles.
PLL output
t1
t2
t3
tn-1
tn
Ideal clock
Slow
Deviation
time
t1
t3
t2
tn-1
tn
Fast
14.4.6 Reset Input
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Pin name
Reset input time
tRSTL
Unit
Min
Max
10
-
µs
1
-
µs
RSTX
Rejection of reset input time
tRSTL
RSTX
0.2VCC
Document Number: 002-04717 Rev *A
0.2VCC
Page 50 of 75
MB96690 Series
14.4.7 Power-on Reset Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Value
Parameter
Symbol
Pin name
Unit
Min
Typ
Max
Power on rise time
tR
Vcc
0.05
-
30
ms
Power off time
tOFF
Vcc
1
-
-
ms
tR
tOFF
2.7V
VCC
0.2V
0.2V
0.2V
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below.
5.0V
VCC
2.7V
0V
VSS
Document Number: 002-04717 Rev *A
It is required that rises in voltage
have a slope of 50 mV/ms or less.
Page 51 of 75
MB96690 Series
14.4.8
USART Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C, CL=50pF)
Parameter
Symbol
Serial clock cycle time
Pin name
Conditions
4.5V ≤ VCC < 5.5V
2.7V ≤ VCC < 4.5V
Min
Min
Max
4tCLKP1
-
ns
- 30
+ 30
ns
-
ns
Max
tSCYC
SCKn
4tCLKP1
SCK ↓ → SOT delay
time
tSLOVI
SCKn,
SOTn
- 20
SOT → SCK ↑ delay
time
tOVSHI
SCKn,
SOTn
SIN →SCK ↑setup time
tIVSHI
SCKn,
SINn
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse
width
Internal
shift clock
mode
+ 20
Unit
N×tCLKP1–
*
20
-
N×tCLKP1– 30
tCLKP1+ 45
-
tCLKP1+ 55
-
ns
SCKn,
SINn
0
-
0
-
ns
tSLSH
SCKn
tCLKP1+ 10
-
tCLKP1+ 10
-
ns
Serial clock "H" pulse
width
tSHSL
SCKn
tCLKP1+ 10
-
tCLKP1+ 10
-
ns
SCK ↓ → SOT delay
time
tSLOVE
SCKn,
SOTn
2tCLKP1+ 55
ns
SIN →SCK ↑setup time
tIVSHE
SCKn,
SINn
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
tF
SCKn
-
20
-
20
ns
SCK rise time
tR
SCKn
-
20
-
20
ns
Notes:
SCKn,
SINn
External
shift clock
mode
*
-
2tCLKP1+
45
tCLKP1/2+ 10
-
tCLKP1/2+ 10
-
ns
tCLKP1+ 10
-
tCLKP1+ 10
-
ns
-
−AC characteristic in CLK synchronized mode.
−CL is the load capacity value of pins when testing.
−Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96600 series HARDWARE MANUAL”.
−tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
−These characteristics only guarantee the same relocate port number.
For example, the combination of SCKn and SOTn_R is not guaranteed.
*: Parameter N depends on tSCYC and can be calculated as follows:
• If tSCYC = 2 × k × tCLKP1, then N = k, where k is an integer > 2
• If tSCYC = (2 × k + 1) × tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC
N
4 ×tCLKP1
2
5 ×tCLKP1, 6 ×tCLKP1
3
7 ×tCLKP1, 8 ×tCLKP1
4
Document Number: 002-04717 Rev *A
Page 52 of 75
MB96690 Series
tSCYC
VOH
SCK
VOL
VOL
tOVSHI
tSLOVI
VOH
SOT
VOL
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
Internal shift clock mode
SCK
tSHSL
tSLSH
VIH
VIH
VIL
tF
VIL
VIH
tR
tSLOVE
SOT
VOH
VOL
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
External shift clock mode
Document Number: 002-04717 Rev *A
Page 53 of 75
MB96690 Series
14.4.9 External Input Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Max
Unit
Remarks
General Purpose I/O
ADTG
A/D Converter trigger
input
2tCLKP1 +200
(tCLKP1=1/fCLKP1)*
TTGn
tINH, tINL
Min
Pnn_m
TINn
Input pulse width
Value
Pin name
Reload Timer
-
ns
FRCKn,
PPG trigger input
FRCKn_R
Free-Running Timer
input clock
INn, INn_R
Input Capture
INTn, INTn_R
NMI
200
-
ns
External Interrupt
Non-Maskable Interrupt
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
tINH
External input timing
VIH
tINL
VIH
VIL
Document Number: 002-04717 Rev *A
VIL
Page 54 of 75
MB96690 Series
14.4.10 I2C Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
High-speed
Typical mode
Conditions
Unit
SCL clock frequency
fSCL
(Repeated) START condition hold time SDA
↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
µs
SCL clock "L" width
tLOW
4.7
-
1.3
-
µs
SCL clock "H" width
tHIGH
4.0
-
0.6
-
µs
(Repeated) START condition setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
µs
0
3.45
0
0.9
tSUDAT
250
-
100
-
ns
STOP condition setup time SCL ↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
µs
Bus free time between "STOP condition"
and "START condition"
tBUS
4.7
-
1.3
-
µs
Pulse width of spikes which will be
suppressed by input noise filter
tSP
0
(1-1.5)
[5]
×tCLKP1
0
(1-1.5)
[5]
×tCLKP1
ns
Data hold time
tHDDAT
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ →SCL ↑
R = (Vp/IOL)
Min
[4]
Min
0
CL = 50pF,
Max
100
mode
0
Max
400
kHz
[1]
-
[2]
[3]
µs
[1]: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
[2]: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
2
2
[3]: A high-speed mode I C bus device can be used on a standard mode I C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250ns".
[4]: For use at over 100 kHz, set the peripheral clock1 (CLKP1) to at least 6 MHz.
[5]: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time.
SDA
tSUDAT
tSUSTA
tBUS
tLOW
SCL
tHDSTA
tHDDAT
Document Number: 002-04717 Rev *A
tHIGH
tHDSTA
tSP
tSUSTO
Page 55 of 75
MB96690 Series
14.5
A/D Converter
14.5.1 Electrical Characteristics for the A/D Converter
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symb
Pin
ol
name
Value
Min
Typ
Max
Unit
Resolution
-
-
-
-
10
bit
Total error
-
-
- 3.0
-
+ 3.0
LSB
Nonlinearity error
-
-
- 2.5
-
+ 2.5
LSB
Differential
Nonlinearity error
-
-
- 1.9
-
+ 1.9
LSB
Zero transition voltage
VOT
ANn
Typ - 20
AVRL+ 0.5LSB
Typ + 20
mV
Full scale transition
voltage
VFST
ANn
Typ - 20
AVRH- 1.5LSB
Typ + 20
mV
-
-
1.0
-
5.0
µs
Compare time
*
Sampling time
*
-
-
IA
Power supply current
Reference power
supply current
(between AVRH and
AVRL)
Analog input capacity
Analog impedance
Analog port input
current (during
conversion)
Analog input voltage
Reference voltage
range
Variation between
channels
IAH
AVCC
4.5V ≤ ΑVCC ≤ 5.5V
2.2
-
8.0
µs
2.7V ≤ ΑVCC < 4.5V
0.5
-
-
µs
4.5V ≤ ΑVCC ≤ 5.5V
1.2
-
-
µs
2.7V ≤ ΑVCC < 4.5V
-
2.0
3.1
mA
A/D Converter active
-
-
3.3
µA
A/D Converter not
operated
-
520
810
µA
A/D Converter active
-
-
1.0
µA
A/D Converter not
operated
AN2 to 4,
6 to 8, 10
to 12, 14,
15
-
-
16.0
pF
Normal outputs
AN16 to
31
-
-
17.8
pF
High current outputs
-
-
2050
Ω
4.5V ≤ AVCC ≤ 5.5V
2.7V ≤ AVCC < 4.5V
IR
AVRH
IRH
CVIN
Remarks
RVIN
ANn
-
-
3600
Ω
- 0.3
-
+ 0.3
µA
IAIN
AN2 to 4,
6 to 8, 10
to 12, 14,
15
AN16 to
31
- 3.0
-
+ 3.0
µA
VAIN
ANn
AVRL
-
AVRH
V
-
AVRH
-
AVCC
V
-
AVRL
AVSS
-
AVSS+
0.1
V
-
ANn
-
-
4.0
LSB
AVCC
- 0.1
AVSS , AVRL < VAIN <
AVCC, AVRH
*: Time for each channel.
Document Number: 002-04717 Rev *A
Page 56 of 75
MB96690 Series
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample
and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
(Tsamp) depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext
and the AVCC voltage level. The following replacement model can be used for the calculation:
MCU
Rext
Analog
input
RVIN
Source
Comparator
Cext
CVIN
Sampling switch
(During sampling:ON)
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62 × (Rext × Cext + (Rext + RVIN) × CVIN)
Do not select a sampling time below the absolute minimum permitted value.
(0.5µs for 4.5V ≤ AVCC ≤ 5.5V, 1.2µs for 2.7V ≤ AVCC < 4.5V)
If the sampling time cannot be sufficient, connect a capacitor of about 0.1µF to the analog input pin.
A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage
current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current
of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be
compensated by an external capacitor.
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Document Number: 002-04717 Rev *A
Page 57 of 75
MB96690 Series
14.5.3
Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Nonlinearity error : Deviation of the actual conversion characteristics from a straight line that connects the zero
transition point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→
0b1111111111).
Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the
output code by 1LSB.
Total error
: Difference between the actual value and the theoretical value. The total error includes zero
transition error, full-scale transition error and nonlinearity error.
Zero transition voltage: Input voltage which results in the minimum conversion value.
Full scale transition voltage: Input voltage which results in the maximum conversion value.
Nonlinearity error
Differential nonlinearity error
0x3FF
Actual conversion
characteristics
0x3FE
Actual conversion
characteristics
0x(N+1)
Digital output
VFST
(Actuallymeasured
value)
0x003
VNT
(Actually-measured
value)
0x002
Actual conversion
characteristics
0x004
Digital output
{1 LSB(N-1) + VOT}
0x3FD
Ideal characteristics
0xN
Ideal characteristics
0x(N-2)
0x001
VOT (Actually-measured value)
AVRL
AVRH
Analog input
Nonlinearity error of digital output N =
Differential nonlinearity error of digital output N =
1LSB =
N
VOT
VFST
VNT
:
:
:
:
V(N+1)T
(Actually-measured
value)
0x(N-1)
VNT
(Actually-measured
value)
Actual conversion characteristics
AVRL
AVRH
Analog input
VNT - {1LSB ×(N - 1) + VOT}
1LSB
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VOT
1022
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0x3FE to 0x3FF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04717 Rev *A
Page 58 of 75
MB96690 Series
Total error
0x3FF
1.5 LSB
0x3FE
Actual conversion
characteristics
Digital output
0x3FD
{1 LSB (N-1) + 0.5 LSB}
0x004
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0x003
0x002
0x001
0.5 LSB
AVRL
AVRH
Analog input
1LSB (Ideal value) =
Total error of digital output N =
AVRH - AVRL
1024
[V]
VNT - {1LSB × (N - 1) + 0.5LSB}
1LSB
N
: A/D converter digital output value.
VNT
: Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVRL + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
Document Number: 002-04717 Rev *A
Page 59 of 75
MB96690 Series
14.6
High Current Output Slew Rate
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Output rise/fall
time
Pin name
Outputs
driving
strength set
to "30mA"
P08_m,
P09_m,
P10_m
tR30, tF30
Value
Conditions
Min
15
Typ
Unit
Max
-
75
Voltage
Remarks
ns
CL=85pF
VH=VOL30+0.9 × (V OH30-VOL30)
VL=VOL30+0.1 × (V OH30-VOL30)
VH
VH
VL
VL
tR30
tF30
Time
14.7
Low Voltage Detection Function Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Unit
VDL0
CILCR:LVL = 0000B
Min
2.70
VDL1
CILCR:LVL = 0001B
2.79
3.00
3.21
V
VDL2
CILCR:LVL = 0010B
2.98
3.20
3.42
V
VDL3
CILCR:LVL = 0011B
3.26
3.50
3.74
V
VDL4
CILCR:LVL = 0100B
3.45
3.70
3.95
V
VDL5
CILCR:LVL = 0111B
3.73
4.00
4.27
V
VDL6
CILCR:LVL = 1001B
3.91
4.20
4.49
V
Power supply voltage
[2]
change rate
dV/dt
-
- 0.004
-
+ 0.004
V/µs
CILCR:LVHYS=0
-
-
50
mV
Hysteresis width
VHYS
CILCR:LVHYS=1
80
100
120
mV
-
-
-
75
Detected voltage
[1]
Typ
2.90
Max
3.10
V
µs
Stabilization time
TLVDSTAB
Detection delay time
td
30
µs
[1]: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility
that the low voltage detection will occur or stop after the power supply voltage passes the detection range.
Document Number: 002-04717 Rev *A
Page 60 of 75
MB96690 Series
[2]: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the
power supply voltage within the limits of the change ration of power supply voltage.
Voltage
Vcc
dV
Detected Voltage
dt
VDLX max
VDLX min
Time
Voltage
Internal Reset
Vcc
Release Voltage
dV
dt
VHYS
Time
td
Normal Operation
td
Low Voltage Reset Assertion
Power Reset Extension Time
RCR:LVDE
···Low voltage detection
function enable
Document Number: 002-04717 Rev *A
Low voltage detection
function disable
Stabilization time
TLVDSTAB
Low voltage detection
function enable···
Page 61 of 75
MB96690 Series
14.8
Flash Memory Write/Erase Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Conditions
Value
Unit
Large Sector
-
Small Sector
-
-
0.4
2.1
s
Security Sector
-
-
0.31
1.65
s
Word (16-bit) write time
-
-
25
400
µs
Not including system-level
overhead time.
Chip erase time
-
-
8.31
40.05
s
Includes write time prior to
internal erase.
Sector erase time
Typ
1.6
Max
7.5
s
Remarks
Min
-
Includes write time prior to
internal erase.
Note:
While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the
application system where the external power (VCC) might be shut down while writing or erasing, be sure to turn
the power off by using a low voltage detection function.
To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/µs
[1]
to +0.004V/µs) after the external power falls below the detection voltage (VDLX) .
Write/Erase cycles and data hold time
Write/Erase cycles
Data hold time
(cycle)
(year)
1,000
20
[2]
10,000
10
[2]
100,000
5
[2]
[1]: See "14.7 Low Voltage Detection Function Characteristics".
[2]: This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85°C).
Document Number: 002-04717 Rev *A
Page 62 of 75
MB96690 Series
15.
Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
MB96F696
Run Mode
(VCC = 5.5V)
100.00
PLL clock (32MHz)
10.00
ICC [mA]
Main osc. (4MHz)
1.00
RC clock (2MHz)
RC clock (100kHz)
0.10
Sub osc. (32kHz)
0.01
-50
0
50
100
150
TA [ºC]
Sleep Mode
(VCC = 5.5V)
100.000
PLL clock (32MHz)
10.000
ICC [mA]
Main osc. (4MHz)
1.000
RC clock (2MHz)
0.100
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04717 Rev *A
Page 63 of 75
MB96690 Series
MB96F696
Timer Mode
(VCC = 5.5V)
10.000
PLL clock (32MHz)
ICC [mA]
1.000
Main osc. (4MHz)
0.100
RC clock (2MHz)
RC clock (100kHz)
0.010
Sub osc. (32kHz)
0.001
-50
0
50
100
150
TA [ºC]
Stop Mode
(VCC = 5.5V)
1.000
ICC [mA]
0.100
0.010
0.001
-50
0
50
100
150
TA [ºC]
Document Number: 002-04717 Rev *A
Page 64 of 75
MB96690 Series
Used setting
Mode
Run mode
Sleep mode
Selected Source Clock
Clock/Regulator and FLASH Settings
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
PLL
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock fast
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock slow
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Timer mode
PLL
CLKMC = 4MHz, CLKPLL = 32MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
Main osc.
CLKMC = 4MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock fast
CLKMC = 2MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock slow
CLKMC = 100kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Sub osc.
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Stop mode
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Document Number: 002-04717 Rev *A
Page 65 of 75
MB96690 Series
16.
Ordering Information
MCU with CAN controller
Part number
MB96F693RBPMC-GSE1
MB96F693RBPMC-GSE2
MB96F695RBPMC-GSE1
MB96F695RBPMC-GSE2
MB96F696RBPMC-GSE1
MB96F696RBPMC-GSE2
Flash memory
Package*
Flash A (96.5KB)
100-pin plastic LQFP (FPT-100P-M20)
Flash A (160.5KB)
100-pin plastic LQFP (FPT-100P-M20)
Flash A (288.5KB)
100-pin plastic LQFP (FPT-100P-M20)
*: For details about package, see "Package Dimension".
MCU without CAN controller
Part number
MB96F693ABPMC-GSE1
MB96F693ABPMC-GSE2
MB96F695ABPMC-GSE1
MB96F695ABPMC-GSE2
Flash memory
Package*
Flash A (96.5KB)
100-pin plastic LQFP (FPT-100P-M20)
Flash A (160.5KB)
100-pin plastic LQFP (FPT-100P-M20)
*: For details about package, see "Package Dimension".
Document Number: 002-04717 Rev *A
Page 66 of 75
MB96690 Series
17.
Package Dimension
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
"A"
1
25
0.50(.020)
C
0.20 ±0.05
(.008 ±.002)
0.08(.003) M
2005 -2010 FUJITSU SEMICONDUCTOR LIMITED F100031S-c-3-5
Document Number: 002-04717 Rev *A
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.006 ±.002)
0°~8°
0.50 ±0.20
(.020 ±.008)
0.60 ±0.15
(.024 ±.006)
0.10 ±0.10
(.004 ±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Page 67 of 75
MB96690 Series
18.
Major Changes
Spansion Publication Number: MB96F696-DS704-00011
Page
Section
Change Results
Revision 1.0
-
-
FEATURES
1
2
2
PRELIMINARY → Data sheet
Changed the description of “System clock”
Up to 16 MHz external clock for devices with fast clock input
feature
Up to 8 MHz external clock for devices with fast clock input
feature
Changed the description of “Free-Running Timers” Signals an
interrupt on overflow
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4)
Changed the description of “LCD Controller”
On-chip drivers for internal divider resistors or external divider
resistors
Internal divider resistors or external divider resistors
16
Changed the description of “External Interrupts”
Interrupt mask and pending bit per channel
Interrupt mask bit per channel
Changed the description of “Built-in On Chip Debugger”
- Event sequencer: 2 levels
- Event sequencer: 2 levels + reset
Added the Product
Changed the Remark of RLT
RLT 0/1/2/3/6 Only RLT6 can be used as PPG clock source
RLT 0 to 3/6
Changed number of the I/O Ports
77 (Dual clock mode)
79 (Single clock mode)
75 (Dual clock mode)
77 (Single clock mode)
Deleted the block of RLT6 from PPG block
Changed the RLT block
4ch 0/1/2/3/6 5ch
Changed the Description of PPGn_B Programmable Pulse
Generator n output (8bit)
Programmable Pulse Generator n output (16bit/8bit)
Changed the I/O circuit type of Pin no.96
PQ
Changed the figure of type B
Changed the Remarks of type B (CMOS hysteresis input with
input shutdown function, IOL = 4mA, IOH = -4mA, Programmable
pull-up resister) (CMOS level output (IOL = 4mA, IOH = -4mA),
Automotive input with input shutdown function and
programmable pull-up resistor)
Changed the figure of type G
19
Added the Type Q
3
3
PRODUCT LINEUP
6
7
9
13
BLOCK DIAGRAM
PIN DESCRIPTION
PIN CIRCUIT TYPE
I/O CIRCUIT TYPE
14
21
23
MEMORY MAP
Changed the START addresses of Boot-ROM
0F:E000H 0F:C000H
USER ROM MEMORY MAP FOR FLASH
Changed the annotation
Others (from DF:0200H to DF:1FFFH) are all mirror area of
SAS-512B.
DEVICES
Others (from DF:0200H to DF:1FFFH) is mirror area of
SAS-512B.
Document Number: 002-04717 Rev *A
Page 68 of 75
MB96690 Series
Page
Section
INTERRUPT VECTOR TABLE
25
26
29 to 32
33
HANDLING PRECAUTIONS
HANDLING DEVICES
35
35
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
36
37
Change Results
Changed the Description of CALLV0 to CALLV7
Reserved
CALLV instruction
Changed the Description of RESET
Reserved
Reset vector
Changed the Description of INT9
Reserved
INT9 instruction
Changed the Description of EXCEPTION
Reserved
Undefined instruction execution
Changed the Vector name of Vector number 64 PPGRLT RLT6
Changed the Description of Vector number 64
Reload Timer 6 can be used as PPG clock source
Reload Timer 6
Added a section
Added the description to “3. External clock usage”
(3) Opposite phase external clock
Changed the description in “7. Turn on sequence of power
supply to A/D converter and analog inputs” In this case, the
voltage must not exceed AVRH or AVCC
In this case, AVRH must not exceed AVCC. Input voltage for
ports shared with analog input ports also must not exceed AVCC
Changed the description in “11. SMC power supply pins”
To avoid this, VCC must always be powered on before DVCC.
To avoid this, VCC must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
Added the description “13. Mode Pin (MD)”
Changed the Symbol of “"L" level average overall output
current”
ΣIOLSMCAV ΣIOLAVSMC
Changed the Symbol of “"H" level average overall output
current”
ΣIOHSMCAV ΣIOHAVSMC
Changed the annotation *2
It is required that AVCC does not exceed VCC and that the
voltage at the analog inputs does not exceed AVCC when the
power is switched on. It is required that AVCC does not exceed
VCC, DVCC and that the voltage at the analog inputs does not
exceed AVCC when the power is switched on.
Changed the annotation *3
Input/Output voltages of standard ports depend on VCC.
Input/Output voltages of high current ports depend on DVCC.
Input/Output voltages of standard ports depend on VCC.
Changed the annotation *4
Note that if the +B input is applied during power-on, the power
supply is provided from the pins and the resulting supply
voltage may not be sufficient to operate the Power reset
(except devices with persistent low voltage reset in internal
vector mode).
Note that if the +B input is applied during power-on, the power
supply is provided from the pins and the resulting supply
voltage may not be sufficient to operate the Power reset.
Added the annotation *4
The DEBUG I/F pin has only a protective diode against VSS.
Hence it is only permitted to input a negative clamping current
(4mA). For protection against positive input voltages, use an
external clamping diode which limits the input voltage to
maximum 6.0V.
Document Number: 002-04717 Rev *A
Page 69 of 75
MB96690 Series
Page
Section
2. Recommended Operating Conditions
38
3. DC Characteristics
(1) Current Rating
39
40
Change Results
Added the Value and Remarks to “Power supply voltage”
Min: 2.0V
Typ: Max: 5.5V
Remarks: Maintains RAM data in stop mode
Changed the Value of “Smoothing capacitor at C pin”
Typ: 1.0µF → 1.0µF to 3.9µF
Max: 1.5µF → 4.7µF
Changed the Remarks of “Smoothing capacitor at C pin”
Deleted “(Target value)”
Added “3.9µF (Allowance within ± 20%)”
Deleted “(Target value)”
Added the Symbol to “Power supply current in Run modes”
ICCRCH, ICCRCL
Changed the Conditions of ICCPLL, ICCMAIN, ICCSUB in “Power
supply current in Run modes” “Flash 0 wait” is added
Changed the Value of “Power supply current in Run modes”
ICCPLL Typ: 28.5mA → 28mA (TA = +25°C)
ICCMAIN Typ:5mA → 3.5mA (TA = +25°C)
Max: 10mA → 8mA (TA = +105°C)
ICCSUB Typ:0.5mA → 0.1mA (TA = +25°C)
Max: 6mA → 3.3mA (TA = +105°C)
Added the Symbol to “Power supply current in Sleep modes”
ICCSRCH, ICCSRCL
Changed the Conditions of ICCSMAIN in “Power supply current in
Sleep modes” “SMCR:LPMSS=0” is added
Changed the Value of “Power supply current in Sleep modes”
ICCSPLL
Typ:10mA → 9.5m A (TA = +25°C)
ICCSMAIN
Typ: 3mA → 1.1m A (TA = +25°C)
Max: 8mA → 4.7m A (TA = +105°C)
ICCSSUB
Typ: 0.3mA → 0.04m A (TA = +25°C)
Max: 4.5mA → 2.7m A (TA = +105°C)
Added the Symbol to “Power supply current in Timer modes”
ICCTPLL
Changed the Conditions of ICCTMAIN, ICCTRCH in “Power supply
current in Timer modes”
“SMCR:LPMSS=0” is added
Changed the Value of “Power supply current in Timer modes”
ICCTMAIN
Max: 355µA → 330µA (TA = +25°C)
Max: 1320µA→ 1200µA (TA = +105°C)
ICCTRCH
Max: 245µA → 215µA (TA = +25°C)
Max: 1230µA→ 1110µA (TA = +105°C)
ICCTRCL
Max: 105µA → 75µA (TA = +25°C)
Max: 1030µA → 910µA (TA = +105°C)
ICCTSUB
Typ: 90µA→ 65µA (TA = +25°C)
Max: 1000µA → 885µA (TA = +105°C)
3. DC Characteristics
(1) Current Rating
41
Changed the Value of “Power supply current in Stop modes”
ICCH
Max: 90µA → 60µA (TA = +25°C)
Max: 1000µA → 880µA (TA = +105°C)
Document Number: 002-04717 Rev *A
Page 70 of 75
MB96690 Series
Page
Section
Change Results
Added the Symbol
ICCFLASHPD
Changed the Value and condition of “Power supply current for
active Low Voltage detector”
ICCLVD
Typ: 5µA, Max: 15µA, Remarks: nothing
Typ: 5µA, Max: -, Remarks: TA = +25°C
Typ: -, Max: 12.5µA, Remarks: TA = +105°C
Changed the condition of “Flash Write/Erase current”
ICCFLASH
Typ: 12.5mA, Max: 20mA, Remarks: nothing
Typ: 12.5mA, Max: -, Remarks: TA = +25°C
Typ: -, Max: 20mA, Remarks: TA = +105°C
Changed the annotation *2
The power supply current is measured with a 4MHz external
clock connected to the Main oscillator and a 32kHz external
clock connected to the Sub oscillator.
When Flash is not in Power-down / reset mode, ICCFLASHPD must
be added to the Power supply current.
The power supply current is measured with a 4MHz external
clock connected to the Main oscillator and a 32kHz external
clock connected to the Sub oscillator. The current for "On Chip
Debugger" part is not included.
42
3. DC Characteristics
(2) Pin Characteristics
43
Added the Symbol for DEBUG I/F pin VOLD
Changed the Pin name of “Input capacitance”
Other than
Vcc,
Vss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
Other than
C,
Vcc,
Vss,
DVcc,
DVss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
Deleted the annotation “IOH and IOL are target value.”
Added the annotation
“In the case of driving stepping motor directly or high current
outputs, set "1" to the bit in the Port High Drive Register
(PHDRnn:HDx="1").”
4. AC Characteristics
(1) Main Clock Input Characteristics
46
Document Number: 002-04717 Rev *A
Changed MAX frequency for fFCI in all conditions 16 → 8
Changed MIN frequency for tCYLH 62.5 → 125
Changed MIN, MAX and Unit for PWH, PWL
MIN: 30 → 55
MAX: 70 → Unit: % → ns
Page 71 of 75
MB96690 Series
Page
Section
Change Results
Added the figure (tCYLH) when using the external clock
47
4. AC Characteristics
(2) Sub Clock Input Characteristics
Added the figure (tCYLL) when using the crystal oscillator clock
48
4. AC Characteristics
(3) Built-in RC Oscillation Characteristics
Added “RC clock stabilization time”
4. AC Characteristics
(5) Operating Conditions of PLL
Changed the Value of “PLL input clock frequency”
Max: 16MHz → 8MHz
Changed the Symbol of “PLL macro oscillation clock frequency”
fPLLO → fCLKVCO
Added Remarks to “PLL oscillation clock frequency”
Added “ PLL phase jitter” and the figure
4. AC Characteristics
(6) Reset Input
4. AC Characteristics
(8) USART Timing
Added the figure for reset input time (tRSTL)
49
51
52
54
4. AC Characteristics
2
(10) I C timing
55
5. A/D Converter
(1) Electrical Characteristics for
the A/D Converter
56
5. A/D Converter
(2) Accuracy and Setting of the A/D Converter
Sampling Time
5. A/D Converter
(3) Definition of A/D Converter Terms
57
Changed the condition
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA
= - 40°C to + 105°C)
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA
= - 40°C to + 105°C, CL = 50pF)
Changed the HARDWARE MANUAL
“MB96690 series HARDWARE MANUAL”
“MB96600 series HARDWARE MANUAL”
Changed the figure for “Internal shift clock mode”
Added parameter, “Noise filter” and an annotation *5 for it
Added tSP to the figure
Added “Analog impedance”
Added “Variation between channels”
Added the annotation
Deleted the unit “[Min]” from approximation formula of Sampling
time
Changed the Description and the figure
“Linearity” → “Nonlinearity”
“Differential linearity error”
“Differential nonlinearity error”
Changed the Description
Linearity error:
Deviation of the line between the zero-transition point
(0b0000000000←→0b0000000001) and the full-scale transition
point (0b1111111110←→0b1111111111) from the actual
conversion characteristics.
Nonlinearity error:
Deviation of the actual conversion characteristics from a
straight line that connects the zero transition point
(0b0000000000 ←→ 0b0000000001) to the full-scale transition
point (0b1111111110 ←→ 0b1111111111).
Added the Description
“Zero transition voltage”
“Full scale transition voltage”
6. High Current Output Slew Rate
59
Changed the condition
(VCC = AVCC = 2.7V to 5.5V, DVCC = 4.5V to 5.5V, VSS = AVSS =
DVSS = 0V, TA = - 40°C to + 105°C)
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA
= - 40°C to + 105°C)
Document Number: 002-04717 Rev *A
Page 72 of 75
MB96690 Series
Page
Section
Change Results
Changed the Symbol and figure
tR2, tF2, VOL2
tR30, tF30, VOL30
7. Low Voltage Detection Function
Characteristics
Added the Value of “ Power supply voltage change rate”
Max: +0.004 V/µs
Added “Hysteresis width” (VHYS)
Added “Stabilization time” (TLVDSTAB)
59
Added “Detection delay time” (td)
Deleted the Remarks
Added the annotation *1, *2
59
7. Low Voltage Detection Function
Characteristics
8. Flash Memory Write/Erase Characteristics
Added the figure for “Hysteresis width”
Added the figure for “Stabilization time”
Changed the Value of “Sector erase time”
Added “Security Sector” to “Sector erase time”
Changed the Parameter
“Half word (16 bit) write time”
“Word (16-bit) write time”
Changed the Value of “Chip erase time”
61
Changed the Remarks of “Sector erase time”
Excludes write time prior to internal erase
Includes write time prior to internal erase
Added the Note and annotation *1
Deleted “(targeted value)” from title “ Write/Erase cycles and
data hold time”
62 to 63
EXAMPLE CHARACTERISTICS
ORDERING INFORMATION
Added a section
Changed part number
MCU with CAN controller
MB96F696RAPMC-GSE1* → MB96F696RBPMC-GSE1
MB96F696RAPMC-GSE2* → MB96F696RBPMC-GSE2
Added part number
MCU with CAN controller
MB96F693RBPMC-GSE1
65
MB96F693RBPMC-GSE2
MB96F695RBPMC-GSE1
MB96F695RBPMC-GSE2
MCU without CAN controller
MB96F693ABPMC-GSE1
MB96F693ABPMC-GSE2
MB96F695ABPMC-GSE1
MB96F695ABPMC-GSE2
Revision 1.1
-
-
Company name and layout design change
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04717 Rev *A
Page 73 of 75
MB96690 Series
Document History
Document Title: MB96690 Series, F2MC, 16FX, 16-bit Proprietary Microcontroller
Document Number: 002-04717
Revision
ECN
Orig. of
Change
Submission
Date
**
−
TORS
01/31/2014
*A
5148388
TORS
09/22/2016 Updated to Cypress template
Document Number: 002-04717 Rev *A
Description of Change
Migrated to Cypress and assigned document number 002-04717.
No change to document contents or format.
Page 74 of 75
MB96690 Series
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Document Number: 002-04717 Rev *A
Page 75 of 75