Product Folder Sample & Buy Support & Community Tools & Software Technical Documents AFE58JD18 SBAS735 – AUGUST 2015 AFE58JD18 16-Channel, Ultrasound AFE with 14-Bit, 65-MSPS or 12-Bit, 80-MSPS ADC, Passive CW Mixer, I/Q Demodulator, and LVDS, JESD204B Outputs 1 1 Features • • • • • • • • • • • • • 16-Channel, Complete Analog Front-End (AFE): – LNA, VCAT, PGA, LPF, ADC, and CW Mixer LNA with Programmable Gain: – Gain: 24 dB, 18 dB, and 12 dB – Linear Input Range: 0.25 VPP, 0.5 VPP, and 1 VPP – Input-Referred Noise: 0.63 nV/√Hz, 0.7 nV/√Hz, and 0.9 nV/√Hz – Programmable Active Termination Voltage-Controlled Attenuator (VCAT): 40 dB Programmable Gain Amplifier (PGA): 24 dB and 30 dB Total Signal Chain Gain: 54 dB (max) 3rd-Order, Linear-Phase LPF: – 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, and 50 MHz Analog-to-Digital Converter (ADC): – 14-Bit ADC: 75-dBFS SNR at 65 MSPS – 12-Bit ADC: 72-dBFS SNR at 80 MSPS LVDS Interface Maximum Speed of 1 Gbps Noise and Power Optimizations (Full-Channel): – 140 mW/Ch at 0.75 nV/√Hz, 65 MSPS – 91.5 mW/Ch at 1.1 nV/√Hz, 40 MSPS – 80 mW/Ch at CW Mode Excellent Device-to-Device Gain Matching: – ±0.5 dB (typical) and ±1.1 dB (max) Low Harmonic Distortion Fast and Consistent Overload Recovery Passive Mixer for CWD: – Low Close-In Phase Noise: –156 dBc/Hz at 1 kHz Off 2.5-MHz Carrier • • • – Phase Resolution: λ / 16 – Supports 16X, 8X, 4X, and 1X CW Clocks – CWD High-Pass Filter Rejects Undesired LowFrequency Signals < 1 kHz Digital Features: – Digital I/Q Demodulator after ADC: – Fractional Decimation Filter M = 1 to 63 with 0.25X Increment Step – Data Throughput Reduction After Decimation – On-Chip RAM with 32 Preset Profiles 5-Gbps JESD Interface: – JESD204B Subclass 0, 1, and 2 – 2, 4, or 8 Channels per JESD Lane Small Package: 15-mm × 15-mm NFBGA-289 2 Applications • • • Medical Ultrasound Imaging Nondestructive Evaluation Equipment Sonar Imaging Equipment 3 Description The AFE58JD18 is a highly-integrated, analog frontend (AFE) solutions specifically designed for ultrasound systems where high performance and small size are required. Device Information(1) PART NUMBER AFE58JD18 OUTPUT INTERFACE LVDS and JESD DIGITAL I/Q DEMODULATOR Supported (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Block Diagram Device (1 of 16 Channels) SPI IN SPI OUT SPI Logic VCAT 0 dB to -40 dB LNA PGA 24, 30 dB LNA IN 3rd-Order LPF with 10, 15, 20, 30, 35, and 50 MHz 12-, 14-Bit ADC JESD JESD Outputs LVDS LVDS Outputs Digital Processing (Optional) 16X CLK 16 Phases Generator CW Mixer Summing Amplifier Reference Reference 1X CLK 16 x 8 Crosspoint SW 1X CLK CW I/Q VOUT Differential TGC VCNTL 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AFE58JD18 SBAS735 – AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Functional Block Diagram .................................... Device and Documentation Support.................... 7.1 7.2 7.3 7.4 7.5 1 1 1 2 3 4 5 8 Documentation Support ............................................ Trademarks ............................................................... Electrostatic Discharge Caution ................................ Export Control Notice................................................ Glossary .................................................................... 5 6 6 6 6 Mechanical, Packaging, and Orderable Information ............................................................. 6 8.1 Tray Information ........................................................ 7 4 Revision History 2 DATE REVISION NOTES August 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 AFE58JD18 www.ti.com SBAS735 – AUGUST 2015 5 Description (continued) The AFE58JD18 has a total of 16 channels, with each channel consisting of a voltage-controlled amplifier (VCA), a simultaneous sampling 14-bit and 12-bit analog-to-digital converter (ADC), and a continuous wave (CW) mixer. The VCA includes a low-noise amplifier (LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and a low-pass filter (LPF). LNA gain is programmable and supports 250-mVPP to 1-VPP input signals and programmable active termination. The ultra-low noise VCAT provides an attenuation control range of 40 dB and improves overall low-gain SNR, which benefits harmonic and near-field imaging. The PGA provides gain options of 24 dB and 30 dB. In front of the ADC, an LPF can be configured at 10 MHz, 15 MHz, 20 MHz, 30 MHz, 35 MHz, or 50 MHz to support ultrasound applications with different frequencies. The AFE58JD18 also integrates a low-power passive mixer and a low-noise summing amplifier to create an onchip CWD beamformer. 16 selectable phase delays can be applied to each analog input signal. Furthermore, a unique third- and fifth-order harmonic suppression filter is implemented to enhance CW sensitivity The high-performance, 14-bit ADC achieves 75-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The device can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively. The ADC low-voltage differential signaling (LVDS) outputs enable a flexible system integration that is desirable for miniaturized systems. The AFE58JD18 additionally includes an optional digital demodulator and JESD204B data packing blocks after the 12- or 14-bit ADC. The digital in-phase and quadrature (I/Q) demodulator with programmable fractional decimation filters accelerates computationally-intensive algorithms at low power. A JESD204B interface that runs up to 5 Gbps further reduces the circuit board routing challenges in high-channel count systems. The AFE58JD18 also allows various power and noise combinations to be selected to optimize system performance. Therefore, the AFE58JD18 is a suitable ultrasound AFE solution for both high-end and portable systems. The AFE58JD18 is available in a 15-mm × 15-mm NFBGA-289 package (ZBV package, S-PBGA-N289) and is specified for operation from –40°C to 85°C. The device pinout is also similar to the AFE5816 device family. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 3 AFE58JD18 SBAS735 – AUGUST 2015 www.ti.com DVDD_1P8 DVDD_1P2 AVDD_1P8 AVDD_5V AVDD_3P3 6 Functional Block Diagram VCM CM_BYP1 Reference Voltage, Current Generator CM_BYP2 VHIGH1 VHIGH2 Programmable Active Termination ACT1 LVDS LNA INM1 DOUTP1 LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB DOUTM1 ADC 1 DOUTP2 VNCTL CW Mixer DOUTM2 CW_CH1 LVDS Serializer Digital Processing including Demodulator (Optional) Programmable Active Termination ACT2 VCAT 0 dB to -40 dB LNA LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB ADC 2 VCNTL CW_CH2 CW Mixer 16x16 CrossPoint SW CW_CLOCK DOUTP16 DOUTM16 FCLKP FCLKM DCLKP DCLKM CML Programmable Active Termination ACT16 INP16 VCAT 0 dB to -40 dB LNA INM16 CML1_OUTP JESD204B Transmitter Analog Inputs INP2 INM2 LVDS Outputs 16x16 CrossPoint SW CW_CLOCK LPF 10, 15, 20, 30, 35, and 50 MHz PGA 24 dB, 30 dB CML1_OUTM CML8_OUTP CML Outputs INP1 VCAT 0 dB to -40 dB ADC 16 CML8_OUTM VCNTL CW Mixer CW_CH16 Conversion Clock 16x16 CrossPoint SW CW_CLOCK VCNTL CW_CLOCK CW Clock CLKM_16x Clock Generator CW_CH15 CW_CH16 CW_CH1 CW_CH2 VCNTRL Block CLKP_16x Serial Interface SYNC Generator SDOUT 16 Phase Generator CLKP_1x CLKM_1x SEN SDIN SCLK RESET PDN_GBL PDN_FAST SYSREF_SERDES SYNC_SERDES CW_IP_OUTP, CW_IP_OUTM, CW_QP_OUTP, CW_QP_OUTM, TX_TRIG ADC_CLKP ADC_CLKM VCNTLM VCNTLP DVSS AVSS Summing Amplifier ADC Clock or System Clock 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 AFE58JD18 www.ti.com SBAS735 – AUGUST 2015 7 Device and Documentation Support 7.1 Documentation Support 7.1.1 Related Documentation AFE5816 Data Sheet, SBAS688 MicroStar BGA Packaging Reference Guide, SSYZ015 Clocking High-Speed Data Converters, SLYT075 Design for a Wideband Differential Transimpedance DAC Output, SBAA150 TI Active Filter Design Tool, WEBENCH® Filter Designer CDCM7005 Data Sheet, SCAS793 CDCE72010 Data Sheet, SCAS858 TLV5626 Data Sheet, SLAS236 DAC7821 Data Sheet, SBAS365 THS413x Data Sheet, SLOS318 OPA1632 Data Sheet, SBOS286 LMK048x Data Sheet, SNAS489 OPA2211 Data Sheet, SBOS377 ADS8413 Data Sheet, SLAS490 ADS8472 Data Sheet, SLAS514 ADS8881 Data Sheet, SBAS547 SN74AUP1T04 Data Sheet, SCES800 UCC28250 Data Sheet,SLUSA29 ISO7240 Data Sheet, SLLS868 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 5 AFE58JD18 SBAS735 – AUGUST 2015 www.ti.com 7.2 Trademarks All trademarks are the property of their respective owners. 7.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 7.4 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 7.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 8 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 AFE58JD18 www.ti.com SBAS735 – AUGUST 2015 8.1 Tray Information Figure 1. Tray Diagram, Section 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 7 AFE58JD18 SBAS735 – AUGUST 2015 www.ti.com Tray Information (continued) Figure 2. Tray Diagram, Section 2 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: AFE58JD18 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) AFE58JD18ZBV ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZBV 289 126 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 85 AFE58JD18 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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