Maxim DS28EA00U+TR 1-wire digital thermometer with sequence detect and pio Datasheet

Rev 2; 4/09
1-Wire Digital Thermometer with
Sequence Detect and PIO
The DS28EA00 is a digital thermometer with 9-bit (0.5°C)
to 12-bit (1/16°C) resolution and alarm function with nonvolatile (NV), user-programmable upper and lower trigger
points. Each DS28EA00 has its own unique 64-bit registration number that is factory programmed into the chip.
Data is transferred serially through the 1-Wire® protocol,
which requires only one data line and a ground reference
for communication. The improved 1-Wire front-end with
hysteresis and glitch filter enables the DS28EA00 to perform reliably in large 1-Wire networks. Unlike other 1-Wire
thermometers, the DS28EA00 has two additional pins to
implement a sequence-detect function. This feature
allows the user to discover the registration numbers
according to the physical device location in a chain, e.g.,
to measure the temperature in a storage tower at different
height. If the sequence-detect function is not needed,
these pins can be used as general-purpose input or output. The DS28EA00 can derive the power for its operation
directly from the data line (“parasite power”), eliminating
the need for an external power supply.
Applications
Data Communication Equipment
♦ Digital Thermometer Measures Temperatures
from -40°C to +85°C
♦ Thermometer Resolution is User Selectable from
9 to 12 Bits
♦ Unique 1-Wire Interface Requires Only One Port
Pin for Communication
♦ Each Device Has a Unique 64-Bit, FactoryLasered Registration Number
♦ Multidrop Capability Simplifies Distributed
Temperature-Sensing Applications
♦ Improved 1-Wire Interface with Hysteresis and
Glitch Filter
♦ User-Definable NV Alarm Threshold Settings/User
Bytes
♦ Alarm Search Command to Quickly Identify
Devices Whose Temperature is Outside of
Programmed Limits
♦ Standard and Overdrive 1-Wire Speed
♦ Two General-Purpose Programmable IO (PIO) Pins
Process Temperature Monitoring
♦ Chain Function Sharing the PIO Pins to Detect
Physical Sequence of Devices in Network
HVAC Systems
PART
Features
Ordering Information
♦ Operating Range: +3.0V to +5.5V, -40°C to +85°C
TEMP RANGE
PIN-PACKAGE
♦ Can Be Powered from Data Line
♦ 8-Pin µSOP Package
DS28EA00U+
-40°C to +85°C
8 μSOP
DS28EA00U+T&R
-40°C to +85°C
8 μSOP
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Typical Operating Circuit
VDD
1-Wire
MASTER
#1
#2
#3
VDD
PX. Y
VDD
IO
VDD
IO
DS28EA00
IO
DS28EA00
DS28EA00
MICROCONTROLLER
PIOB
PIOA
PIOB
GND
PIOA
GND
PIOB
PIOA
GND
NOTE: SCHEMATIC SHOWS PIO PINS WIRED FOR SEQUENCE-DETECT FUNCTION.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS28EA00
General Description
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
ABSOLUTE MAXIMUM RATINGS
IO Voltage Range to GND ........................................-0.5V to +6V
IO Sink Current....................................................................20mA
Maximum PIOA or PIOB Pin Current...................................20mA
Maximum Current Through GND Pin ..................................40mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage
VDD
(Note 2)
5.5
V
Supply Current (Note 3)
IDD
VDD = +5.5V
3.0
1.5
mA
Standby Current
IDDS
VDD = +5.5V
1.5
μA
IO PIN: GENERAL DATA
Local power
3.0
VDD
Parasite power
3.0
5.5
RPUP
(Notes 2, 4)
0.3
2.2
Input Capacitance
CIO
(Notes 3, 5)
1000
pF
Input Load Current
IL
IO pin at VPUP
0.1
1.5
μA
High-to-Low Switching Threshold
VTL
(Notes 3, 6, 7)
0.46
VPUP 1.9V
V
Input Low Voltage (Notes 2, 8)
VIL
Low-to-High Switching Threshold
(Notes 3, 6, 9)
VTH
Parasite power
1.0
VPUP 1.1V
V
Switching Hysteresis
(Notes 3, 6, 10)
VHY
Parasite power
0.21
1.7
V
Output Low Voltage (Note 11)
VOL
At 4mA
0.4
V
1-Wire Pullup Voltage (Note 2)
VPUP
1-Wire Pullup Resistance
Recovery Time
(Notes 2, 12)
tREC
Rising-Edge Hold-Off Time
(Notes 3, 13)
tREH
Time-Slot Duration
(Notes 2, 14)
t SLOT
Parasite powered
0.5
VDD powered (Note 3)
0.7
Standard speed, RPUP = 2.2k
Overdrive speed, RPUP = 2.2k
Overdrive speed, directly prior to reset
pulse; RPUP = 2.2k
Standard speed
Overdrive speed
V
k
V
5
2
μs
5
0.5
5.0
Not applicable (0)
Standard speed
65
Overdrive speed
8
μs
μs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Reset Low Time (Note 2)
2
tRSTL
Standard speed
480
640
Overdrive speed
48
80
_______________________________________________________________________________________
μs
1-Wire Digital Thermometer with
Sequence Detect and PIO
(TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
Presence-Detect High Time
t PDH
Presence-Detect Fall Time
(Notes 3, 15)
tFPD
Presence-Detect Low Time
t PDL
Presence-Detect Sample Time
(Notes 2, 16)
tMSP
CONDITIONS
MIN
TYP
MAX
Standard speed
15
60
Overdrive speed
2
6
Standard speed
1.125
8.1
Overdrive speed
0
1.3
Standard speed
60
240
Overdrive speed
8
24
Standard speed
68.1
75
Overdrive speed
7.3
10
Standard speed
60
120
Overdrive speed
6
16
Standard speed
5
15
Overdrive speed
1
2
Standard speed
5
15 - Overdrive speed
1
2-
Standard speed
tRL + 15
Overdrive speed
tRL + 2
UNITS
μs
μs
μs
μs
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 17)
tW0L
Write-One Low Time
(Notes 2, 17)
tW1L
μs
μs
IO PIN: 1-Wire READ
Read Low Time (Notes 2, 18)
Read Sample Time (Notes 2, 18)
tRL
tMSR
μs
μs
PIO PINS
Input Low Voltage
VILP
(Note 2)
Input High Voltage (Note 2)
VIHP
VX = Max(VPUP, VDD)
Pin at GND
Input Load Current (Note 19)
ILP
Output Low Voltage (Note 11)
VOLP
At 4mA
Chain-On Pullup Impedance
RCO
(Note 3)
0.3
VX - 1.6
V
-1.1
20
V
μA
40
0.4
V
60
k
EEPROM
Programming Current
I PROG
(Notes 3, 20)
1.5
mA
Programming Time
t PROG
(Note 21)
10
ms
Write/Erase Cycles (Endurance)
(Notes 22, 23)
NCY
Data Retention (Notes 24, 25)
tDR
At +25°C
200,000
-40°C to +85°C
50,000
At +85°C (worst case)
—
10
Years
TEMPERATURE CONVERTER
Conversion Current
Conversion Time (Note 26)
ICONV
tCONV
Conversion Error
Converter Drift
D
(Notes 3, 20)
1.5
12-bit resolution (1/16°C)
750
11-bit resolution (1/8°C)
375
10-bit resolution (1/4°C)
187.5
9-bit resolution (1/2°C)
93.75
-10°C to +85°C
-0.5
+0.5
Below -10°C (Note 3)
-0.5
+2.0
(Note 27)
-0.2
+0.2
mA
ms
°C
°C
_______________________________________________________________________________________
3
DS28EA00
ELECTRICAL CHARACTERISTICS (continued)
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40°C to +85°C.) (Note 1)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
Note 21:
Note 22:
Note 23:
Note 24:
Note 25:
Note 26:
Note 27:
4
Specifications at TA = -40°C are guaranteed by design and not production tested.
System requirement.
Guaranteed by design, characterization, and/or simulation only. Not production tested.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to parasitically powered systems with only one device and with the minimum
1-Wire recovery times. For more heavily loaded systems, local power or an active pullup such as that found in the
DS2482-x00, DS2480B, or DS2490 may be required. If longer tREC is used, higher RPUP values may be tolerable.
Value is 25pF maximum with local power. Maximum value represents the internal parasite capacitance when VPUP is first
applied. If RPUP = 2.2kΩ, 2.5µs after VPUP has been applied, the parasite capacitance does not affect normal communications.
VTL, VTH, and VHY are a function of the internal supply voltage, which is a function VDD, VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VDD, VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to VILMAX at all times when the master drives the line to a logic 0.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
The I-V characteristic is linear for voltages less than +1V.
Applies to a single parasitically powered DS28EA00 attached to a 1-Wire line. These values also apply to networks of
multiple DS28EA00 with local supply.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Interval during the negative edge on IO at the beginning of a presence-detect pulse between the time at which the voltage
is 80% of VPUP and the time at which the voltage is 20% of VPUP.
Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28EA00 present.
Minimum limit is tPDHMAX + tFPDMAX; the maximum limit is tPDHMIN + tPDLMIN.
ε in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
δ in Figure 13 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
This load current is caused by the internal weak pullup, which asserts a logic 1 to the PIOB and PIOA pins. The logical
state of PIOB must not change during the execution of the Conditional Read ROM command.
Current drawn from IO during EEPROM programming or temperature conversion interval in parasite-powered mode. The
pullup circuit on IO during the programming or temperature conversion interval should be such that the voltage at IO is
greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, then a low-impedance bypass of RPUP, which
can be activated during programming or temperature conversions, may need to be added. The bypass must be activated
within 10µs from the beginning of the tPROG or tCONV interval, respectively.
The tPROG interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the command byte for a valid
Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from IPROG to IL (parasite power) or IDDS (local power).
Write-cycle endurance is degraded as TA increases.
Not 100% production tested. Guaranteed by reliability monitor sampling.
Data retention is degraded as TA increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
The tCONV interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the command byte for a valid
convert temperature sequence. The interval ends once the device’s self-timed temperature conversion cycle is complete
and the current drawn by the device has returned from ICONV to IL (parasite power) or IDDS (local power).
Drift data is preliminary and based on a 1000-hour stress test performed on another device with comparable design and
fabricated in the same manufacturing process. This test was performed at greater than +85°C with VDD = +5.5V.
Confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test.
_______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
PIN
NAME
1
IO
FUNCTION
1-Wire Bus Interface and Parasitic Power Supply. Open-drain pin that requires external pullup
resistor.
2, 3, 5
N.C.
No Connection
4
GND
Ground Supply
6
Open-Drain PIOA Channel and Chain Output. For sequence detection, PIOA must be connected to
PIOA (DONE) PIOB of the next device in the chain; leave open or connect to GND for the last device in the
chain.
7
PIOB (EN)
8
VDD
Open-Drain PIOB Channel and Chain Input. For sequence detection, PIOB of the first device in the
chain must be connected to GND.
Power Supply. Must be connected to GND for operation in parasite-power mode.
Detailed Description
The Block Diagram shows the relationships between
the major function blocks of the DS28EA00. The device
has three main data components: 64-bit registration
number, 64-bit scratchpad, and alarm and configuration registers. The 1-Wire ROM function control unit
processes the ROM function commands that allow the
device to function in a networked environment. The
device function control unit implements the device-specific control functions, such as read/write, temperature
conversion, setting the chain state for sequence detection, and PIO access. The cyclic redundancy check
(CRC) generator assists the master verifying data
integrity when reading temperatures and memory data.
In the sequence-detect process, PIOB functions as an
input, while PIOA provides the connection to the next
device. The power-supply sensor allows the master to
remotely read whether the DS28EA00 has local power
available.
Figure 1 shows the hierarchical structure of the 1-Wire
protocol. The bus master must first provide one of the
eight ROM function commands: Read ROM, Match
ROM, Search ROM, Conditional (Alarm) Search ROM,
Conditional Read ROM, Skip ROM, Overdrive-Skip
ROM, Overdrive-Match ROM.
Upon completion of an overdrive ROM command executed at standard speed, the device enters overdrive
mode, where all subsequent communication occurs at
a higher speed. The protocol required for these ROM
function commands is described in Figure 11. After a
ROM function command is successfully executed, the
device-specific control functions become accessible
and the master can provide any one of the nine available commands. The protocol for these control function
commands is described in Figure 9. All data is read
and written least significant (LS) bit first.
64-Bit Registration Number
Each DS28EA00 contains a unique registration number
that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a CRC of the first 56 bits (see Figure 2 for
details). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR
gates as shown in Figure 3. The polynomial is X8 + X5 +
X4 + 1. Additional information about the 1-Wire CRC is
available in Application Note 27: Understanding and
Using Cyclic Redundancy Checks with Maxim iButton®
Products.
The shift register bits are initialized to 0. Then starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the eighth bit of the family
code has been entered, then the 48-bit serial number is
entered. After the last byte of the serial number has
been entered, the shift register contains the CRC value.
Shifting in the 8 bits of CRC returns the shift register to
all 0s.
iButton is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
5
DS28EA00
Pin Description
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
Block Diagram
INTERNAL VDD
DS28EA00
POWER-SUPPLY
SENSOR
VDD
(ON)
1-Wire ROM
FUNCTION
CONTROL
IO
RCO
64-BIT
REGISTRATION
NUMBER
PIOB (EN)
PIOA (DONE)
DEVICE
FUNCTION
CONTROL
8-BIT CRC
GENERATOR
ALARM AND
CONFIGURATION
REGISTERS
64-BIT
SCRATCHPAD
TEMPERATURE
SENSOR
DS28EA00
COMMAND LEVEL:
AVAILABLE COMMANDS:
DATA FIELD AFFECTED:
1-Wire ROM
FUNCTION COMMANDS
(SEE FIGURE 11)
READ ROM
MATCH ROM
SEARCH ROM
CONDITIONAL SEARCH ROM
CONDITIONAL READ ROM
SKIP ROM
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT ROM
64-BIT ROM
64-BIT ROM
64-BIT ROM, TEMPERATURE ALARM REGISTERS, SCRATCHPAD
64-BIT ROM, PIOB PIN STATE, CHAIN STATE
(NONE)
64-BIT ROM, OD-FLAG
64-BIT ROM, OD-FLAG
WRITE SCRATCHPAD
READ SCRATCHPAD
COPY SCRATCHPAD
CONVERT TEMPERATURE
READ POWER MODE
RECALL EEPROM
PIO ACCESS READ
PIO ACCESS WRITE
CHAIN
SCRATCHPAD
SCRATCHPAD
TEMPERATURE ALARM AND CONFIGURATION REGISTERS
SCRATCHPAD, TEMPERATURE ALARM REGISTERS
VDD PIN VOLTAGE
SCRATCHPAD, TEMPERATURE ALARM, AND CONFIGURATION REGISTERS
PIO PINS
PIO PINS
CHAIN STATE, PIOA PIN STATE
DS28EA00-SPECIFIC
CONTROL FUNCTION COMMANDS
(SEE FIGURE 9)
Figure 1. Hierarchical Structure for 1-Wire Protocol
6
_______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
MSB
LSB
8-BIT
CRC CODE
8-BIT FAMILY CODE
(42h)
48-BIT SERIAL NUMBER
MSB
LSB MSB
LSB MSB
LSB
Figure 2. 64-Bit Registration Number
POLYNOMIAL = X8 + X5 + X4 + 1
1ST
STAGE
X0
2ND
STAGE
X1
3RD
STAGE
X2
4TH
STAGE
X3
5TH
STAGE
X4
6TH
STAGE
X5
7TH
STAGE
X6
8TH
STAGE
X7
X8
INPUT DATA
Figure 3. 1-Wire CRC Generator
Memory Description
The memory map of the DS28EA00 is shown in Figure 4.
It consists of an 8-byte scratchpad and 3 bytes of backup EEPROM. The first 2 bytes form the Temperature
Readout register, which is updated after a temperature
conversion and is read only. The next 3 bytes are userwritable; they contain the Temperature High (TH) and the
Temperature Low (TL) Alarm register and a Configuration
register. The remaining 3 bytes are “reserved.” They
power up with constant data and cannot be written by
the user. The TH, TL, and Configuration register data in
the scratchpad control the resolution of a temperature
conversion and decide whether a temperature is considered as “alarming.” TH, TL, and Configuration can be
copied to the EEPROM to become nonvolatile. The
scratchpad is automatically loaded with EEPROM data
when the DS28EA00 powers up.
BYTE
ADDRESS
SCRATCHPAD (POWER-UP STATE)
BACKUP EEPROM
0
TEMPERATURE LSB (50h)
N/A
1
TEMPERATURE MSB (05h)
N/A
2
TH REGISTER OR USER BYTE 1*
TH REGISTER OR USER BYTE 1
3
TL REGISTER OR USER BYTE 2*
TL REGISTER OR USER BYTE 2
4
CONFIGURATION REGISTER*
CONFIGURATION REGISTER
5
RESERVED (FFh)
N/A
6
RESERVED (0Ch)
N/A
7
RESERVED (10h)
N/A
*POWER-UP STATE DEPENDS ON VALUE(S) STORED IN EEPROM.
Figure 4. Memory Map
_______________________________________________________________________________________
7
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
Register Detailed Descriptions
Temperature Readout Register Bitmap
ADDRRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0h
23
22
21
20
2-1
2-2
2-3
2-4
LS BYTE
S
26
25
24
MS BYTE
1h
S
S
S
S
Temperature Alarm Registers Bitmap
ADDRRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
2h
S
26
25
24
23
22
21
20
HIGH ALARM (TH)
3h
S
26
25
24
23
22
21
20
LOW ALARM (TL)
Table 1. Temperature/Data Relationship
TEMPERATURE
(°C)
DIGITAL OUTPUT
(BINARY)
DIGITAL OUTPUT
(HEX)
+85*
0000 0101 0101 0000
0550h
+25.0625
0000 0001 1001 0001
0191h
+10.125
0000 0000 1010 0010
00A2h
+0.5
0000 0000 0000 1000
0008h
0
0000 0000 0000 0000
0000h
-0.5
1111 1111 1111 1000
FFF8h
-10.125
1111 1111 0101 1110
FF5Eh
-25.0625
1111 1110 0110 1111
FE6Fh
-40
1111 1101 1000 0000
FD80h
*The power-on reset value of the Temperature Readout register is +85°C.
The temperature reading is in °C using a 16-bit signextended two’s complement format. Table 1 shows
examples of temperature and the corresponding data
for 12-bit resolution. With two’s complement, the sign
bit(s) is set if the value is negative. If the device is configured for 12-bit resolution, all bits in the LS byte are
valid; for a reduced resolution, bit 0 (11-bit mode), bits
0 to 1 (10-bit mode), and bits 0 to 2 (9-bit mode) are
undefined.
The result of a temperature conversion is automatically
compared to the values in the alarm registers to determine whether an alarm condition exists. Alarm thresh-
8
olds are represented as two’s complement number.
With 8 bits available for sign and value, alarm thresholds can be set in increments of 1°C. An alarm condition exists if a temperature conversion results in a value
that is either higher than or equal to the value stored
in the TH register or lower than or equal to the value
stored in the TL register. If a temperature alarm condition exists, the device responds to the Conditional
Search ROM command. The alarm condition is cleared
if a subsequent temperature conversion results in a
temperature reading within the boundaries defined by
the data in the TH and TL registers.
_______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
ADDRRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4h
0
R1
R0
1
1
1
1
1
The functional assignments of the individual bits are
explained in the table below. Bits [4:0] and bit 7 have
BIT DESCRIPTION
R1, R0: Temperature
Converter Resolution
no function and cannot be changed by the user. As a
factory default, the device operates in 12-bit resolution.
BIT(S)
DEFINITION
[6:5]
These bits control the resolution of the temperature converter. The codes are as follows:
R1
R0
0
0
9 bits
0
1
10 bits
1
0
11 bits
1
1
12 bits
PIO Structure
Each PIO consists of an open-drain pulldown transistor
and an input path to read the pin state. The transistor is
controlled by the PIO output latch, as shown in Figure
5. The device function control unit connects the PIO
pins logically to the 1-Wire interface. PIOA has a pullup
path to internal VDD to facilitate the sequence-detect
function (see the Block Diagram) in conjunction with the
Chain command; PIOB is truly an open-drain structure.
The power-on default state of the PIO output transistors
is off; high-impedance, on-chip resistors (not shown in
Figure 5) pull the PIO pins to internal VDD.
Chain Function
The chain function is a feature that allows the 1-Wire
master to discover the physical sequence of devices
that are wired as a linear network (chain). This is particularly convenient for devices that are installed at equal
spacing along a long cable (e.g., to measure temperatures at different locations inside a storage tower or
tank). Without chain function, the master needs a
lookup table to correlate the registration number to the
physical location.
The chain function requires two pins: an input (EN) to
enable a device to respond during the discovery and
an output (DONE) to inform the next device in the chain
that the discovery of its neighbor is done. The two gen-
PIO PIN STATE
PIO PIN
PIO OUTPUT LATCH STATE
PIO DATA
PIO CLOCK
D
CLOCK
Q
Q
PIO OUTPUT LATCH
Figure 5. PIO Simplified Logic Diagram
eral-purpose ports of the DS28EA00 are reused for the
chain function. PIOB functions as an EN input and PIOA
generates the DONE signal, which is connected to the
EN input of the next device, as shown in the Typical
Operating Circuit. The EN input of the first device in the
chain needs to be hardwired to GND or logic 0 must be
applied for the duration of the sequence discovery
process. Besides the two pins, the sequence discovery
relies on the Conditional Read ROM command.
For the chain function and normal PIO operation to
coexist, the DS28EA00 distinguishes three chain states:
OFF, ON, and DONE. The transition from one chain
state to another is controlled through the Chain command. Table 2 summarizes the chain states and the
specific behavior of the PIO pins.
Table 2. Chain States
DEVICE BEHAVIOR
CHAIN STATE
OFF (Default)
ON
DONE
PIOB (EN)
PIOA (DONE)
CONDITIONAL READ ROM
PIO (High Impedance)
PIO (High Impedance)
Not Recognized
EN Input
Pullup On
Recognized if EN is 0
No Function
Pulldown On (DONE Logic 0)
Not Recognized
_______________________________________________________________________________________
9
DS28EA00
Configuration Register
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
The power-on default chain state is OFF, where PIOA
and PIOB are solely controlled through the PIO Access
Read and Write commands. In the chain ON state,
PIOA is pulled high to the device’s internal VDD supply
through an approximately 40kΩ resistor, applying a
logic 1 to the PIOB (EN) pin of the next device. Only in
the ON state does a DS28EA00 respond to the
Conditional Read ROM command, provided its EN is at
logic 0. After a device’s ROM registration number is
read, it is put into the chain DONE state, which enables
the next device in the chain to respond to the
Conditional Read ROM command.
At the beginning of the sequence discovery process, all
devices are put into the chain ON state. As the discovery progresses, one device after another is transitioned
into the DONE state until all devices are identified.
Finally, all devices are put into the chain OFF state,
which releases the PIO pins and restores their poweron default state.
Control Function Commands
Figure 9 shows the protocols necessary for measuring
temperatures, accessing the memory and PIO pins,
and changing the chain state. Examples on how to use
these and other functions are included at the end of this
document. The communication between master and
DS28EA00 takes place either at standard speed
(default, OD = 0) or at overdrive speed (OD = 1). If not
explicitly set into the overdrive mode after power-up,
the DS28EA00 communicates at standard speed.
Write Scratchpad [4Eh]
This command allows the master to write 3 bytes of
data to the scratchpad of the DS28EA00. The first data
byte is associated with the TH register (byte address
2), the second byte is associated with the TL register
(byte address 3), and the third byte is associated with
the Configuration register (byte address 4). Data must
be transmitted least significant bit first. All 3 bytes must
be written before the master issues a reset, or the data
can be corrupted.
Read Scratchpad [BEh]
This command allows the master to read the contents
of the scratchpad. The data transfer starts with the least
significant bit of the Temperature Readout register at
byte address 0 and continues through the remaining 7
bytes of the scratchpad. If the master continues reading, it gets a ninth byte, which is an 8-bit CRC of all the
data in the scratchpad. This CRC is generated by the
DS28EA00 and uses the same polynomial function as is
10
used with the ROM registration number. The CRC is
transmitted in its true (noninverted) form. The master
can issue a reset to terminate the reading early if only
part of the scratchpad data is needed.
Copy Scratchpad [48H]
This command copies the contents of the scratchpad
byte addresses 2 to 4 (TH, TL, and Configuration registers) to the backup EEPROM. If the device has no VDD
power, the master must enable a strong pullup on the
1-Wire bus for the duration of tPROGMAX within 10µs
after this command is issued. If the device is powered
through the VDD pin, the master can generate read time
slots to monitor the copy process. Copy is completed
when the master reads 1 bits instead of 0 bits.
Convert Temperature [44h]
This command initiates a temperature conversion.
Following the conversion, the resulting thermal data is
found in the Temperature Readout register in the
scratchpad and the DS28EA00 returns to its low-power
idle state. If the device has no VDD power, the master
must enable a strong pullup on the 1-Wire bus for the
duration of the applicable resolution-dependent
tCONVMAX within 10µs after this command is issued. If
the device is powered through the VDD pin, the master
can generate read time slots to monitor the conversion
process. The conversion is completed when the master
reads 1 bits instead of 0 bits.
Read Power Mode [B4h]
For Copy Scratchpad and Convert Temperature, the
master needs to know whether the DS28EA00 has VDD
power available. The Read Power Mode command is
implemented to provide the master with this information. After the command code, master issues read time
slots. If the master reads 1s, the device is powered
through the VDD pin. If the device is powered through
the 1-Wire line, the master read 0s. The power-supply
sensor samples the state of the VDD pin for every time
slot that the master generates after the command code.
Recall EEPROM [B8h]
This command recalls the TH and TL alarm trigger values and configuration data from backup EEPROM into
their respective locations in the scratchpad. After having transmitted the command code, the master can
issue read time slots to monitor the completion of the
recall process. Recall is completed when the master
reads 1 bits instead of 0 bits. The recall occurs automatically at power-up, not requiring any activity by the
master.
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
BIT 7
BIT 6
BIT 5
BIT 4
COMPLEMENT OF B3 TO B0
BIT 3
BIT 2
BIT 1
BIT 0
PIOB OUTPUT
LATCH STATE
PIOB PIN
STATE
PIOA OUTPUT
LATCH STATE
PIOA PIN
STATE
PIO Output Data Bit Assignment
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
X
X
PIOB
PIOA
PIO Access Read [F5h]
PIO Access Write [A5h]
This command reads the PIO logical status and reports
it together with the state of the PIO output latch in an
endless loop. A PIO Access Read can be terminated at
any time with a 1-Wire reset. PIO Access Read can be
executed in the Chain ON and Chain DONE state.
While the device is in the Chain ON or Chain DONE
state, the PIO output latch states always read out as 1s;
the PIO pin state may not be reported correctly.
The state of both PIO channels is sampled at the same
time. The first sampling occurs during the last (most
significant) bit of the command code F5h. The PIO status is then reported to the bus master. While the master
receives the last (most significant) bit of the PIO status
byte, the next sampling occurs and so on until the master generates a 1-Wire reset. The sampling occurs with
a delay of tREH + x from the rising edge of the MS bit of
the previous byte, as shown in Figure 6. The value of
“x” is approximately 0.2µs.
The PIO Access Write command writes to the PIO output latches, which control the pulldown transistors of
the PIO channels. In an endless loop, this command
first writes new data to the PIO and then reads back the
PIO status. This implicit read-after-write can be used by
the master for status verification. A PIO Access Write
can be terminated at any time with a 1-Wire reset. The
PIO Access Write command is ignored by the device
while in Chain ON or Chain DONE state.
MOST SIGNIFICANT 2 BITS OF PREVIOUS BYTE*
After the command code, the master transmits a PIO
output data byte that determines the new state of the
PIO output transistors. The first (least significant) bit is
associated to PIOA; the next bit affects PIOB. The other
6 bits of the new state byte do not have corresponding
PIO pins. These bits should always be transmitted as 1s.
To switch the output transistor on, the corresponding bit
value is 0. To switch the output transistor off (non-conducting), the bit must be 1. This way the bit transmitted
LEAST SIGNIFICANT 2 BITS OF PIO STATUS BYTE
VTH
IO
tREH + X
SAMPLING POINT**
*THE "PREVIOUS BYTE" COULD BE THE COMMAND CODE OR THE DATA BYTE RESULTING FROM THE PREVIOUS PIO SAMPLE.
**THE SAMPLE POINT TIMING ALSO APPLIES TO THE PIO ACCESS WRITE COMMAND, WITH THE "PREVIOUS BYTE" BEING THE WRITE CONFIRMATION BYTE (AAh).
Figure 6. PIO Access Read Timing Diagram
______________________________________________________________________________________
11
DS28EA00
PIO Status Bit Assignment
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
MOST SIGNIFICANT 2 BITS OF INVERTED PIO OUTPUT DATA BYTE
LEAST SIGNIFICANT 2 BITS OF CONFIRMATION BYTE (AAh)
IO
VTH
tREH + X
PIO
Figure 7. PIO Access Write Timing Diagram
as the new PIO output state arrives in its true form at the
PIO pin. To protect the transmission against data errors,
the master must repeat the PIO output data byte in its
inverted form. Only if the transmission was error-free can
the PIO status change. The actual PIO transition to the
new state occurs with a delay of tREH + x from the rising
edge of the MS bit of the inverted PIO byte, as shown in
Figure 7. The value of “x” is approximately 0.2µs. To
inform the master about the successful communication
of the PIO byte, the DS28EA00 transmits a confirmation
byte with the data pattern AAh. While the MS bit of the
confirmation byte is transmitted, the DS28EA00 samples
the state of the PIO pins, as shown in Figure 6, and
sends it to the master. The master can either continue
writing more data to the PIO or issue a 1-Wire reset to
end the command.
Chain [99h]
This command allows the master to put the DS28EA00
into one of the three chain states, as shown in Figure 8.
The device powers up in the chain OFF state. To transition a DS28EA00 from one state to another, the master
must send a suitable chain control byte after the chain
command code. Only the codes 3Ch, 5Ah, and 96h
(true form) are valid, assigned to OFF, ON, and DONE,
12
POWER-ON RESET (POR)
OFF
CHAIN DONE
CHAIN ON
CHAIN OFF
OR POR
CHAIN DONE
ON
DONE
CHAIN ON
THESE TRANSITIONS ARE PERMISSIBLE, BUT DO NOT
OCCUR DURING NORMAL OPERATION.
Figure 8. Chain State Transition Diagram
in this sequence. This control byte is first transmitted in
its true form and then in its inverted form. If the chain
state change was successful, the master receives AAh
confirmation bytes. If the change was not successful
(control byte transmission error, invalid control byte),
the master reads 00h bytes instead.
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
4Eh
WRITE SCRATCHPAD?
BEh
READ SCRATCHPAD?
N
Y
48h
COPY SCRATCHPAD?
N
DS28EA00 SETS
BYTE ADDRESS = 2
DS28EA00 SETS
BYTE ADDRESS = 0
MASTER Tx DATA
BYTE TO SCRATCHPAD
MASTER Rx BYTE
FROM SCRATCHPAD
MASTER Tx RESET?
Y
MASTER Tx RESET?
N
Y
VDD POWERED?
DS28EA00 STARTS
COPY TO EEPROM
Y
COPY
COMPLETED?
N
MASTER ACTIVATES STRONG
PULLUP FOR tPROG
DS28EA00 COPIES
SCRATCHPAD DATA TO EEPROM
Y
N
N
TO FIGURE 9b
MASTER DECISION.
THE MASTER NEEDS TO
KNOW WHETHER VDD
POWER IS AVAILABLE.
Y
Y
N
MASTER DEACTIVATES
STRONG PULLUP
MASTER Rx "0"s
BYTE
ADDRESS = 4?
BYTE
ADDRESS = 7?
Y
N
Y
N
DS28EA00 INCREMENTS
BYTE ADDRESS
DS28EA00 INCREMENTS
BYTE ADDRESS
MASTER Rx 8-BIT
CRC OF DATA
N
MASTER Tx RESET?
MASTER Tx RESET?
Y
N
MASTER Rx "1"s
Y
MASTER Tx RESET?
Y
N
MASTER Rx "1"s
FROM FIGURE 9b
TO ROM FUNCTIONS
FLOWCHART (FIGURE 11)
Figure 9a. Control Function Flowchart
______________________________________________________________________________________
13
DS28EA00
FROM ROM FUNCTIONS
FLOWCHART (FIGURE 11)
BUS MASTER Tx CONTROL
FUNCTION COMMAND
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
44h
CONVERT
TEMPERATURE
FROM FIGURE 9a
MASTER DECISION.
THE MASTER NEEDS TO
KNOW WHETHER VDD
POWER IS AVAILABLE.
B4h
READ POWER
MODE?
N
Y
Y
CONVERSION
COMPLETED?
TO FIGURE 9c
Y
VDD POWERED?
DS28EA00 STARTS
TEMPERATURE CONVERSION
N
N
MASTER DEACTIVATES STRONG
PULLUP FOR tCONV
Y
VDD POWERED?
MASTER Rx "1"s
N
MASTER Rx "0"s
DS28EA00 CONVERTS
TEMPERATURE
Y
N
MASTER DEACTIVATES
STRONG PULLUP
MASTER Rx "0"s
MASTER Tx RESET?
N
Y
MASTER Tx RESET?
Y
N
MASTER Rx "1"s
TO FIGURE 9a
Figure 9b. Control Function Flowchart
14
______________________________________________________________________________________
FROM FIGURE 9c
1-Wire Digital Thermometer with
Sequence Detect and PIO
B8h
RECALL EEPROM?
N
F5h
PIO ACCESS
READ?
A5h
PIO ACCESS
WRITE?
N
DS28EA00 STARTS RECALL
EEPROM TO SCRATCHPAD
RECALL
COMPLETED?
TO FIGURE 9d
N
Y
Y
Y
DS28EA00
FROM FIGURE 9b
BUS MASTER Tx NEW PIO
OUTPUT DATA BYTE
BUS MASTER Tx INVERTED NEW
PIO OUTPUT DATA BYTE
Y
N
DS28EA00 SAMPLES
PIO PIN
*
TRANSMISSION
OK?
MASTER Rx "0"s
N
Y
DS28EA00 UPDATES
PIO
*
MASTER Rx "1"s
BUS MASTER Rx
CONFIRMATION AAh
BUS MASTER Rx
PIO PIN STATUS
BUS MASTER Rx "1"s
DS28EA00 SAMPLES
PIO PIN
*
MASTER Tx RESET?
BUS MASTER Rx
PIO PIN STATUS
MASTER Tx RESET?
Y
MASTER Tx RESET?
Y
N
N
N
N
Y
MASTER Tx RESET?
Y
MASTER Rx "1"s
TO FIGURE 9b
FROM FIGURE 9d
*SEE THE COMMAND DESCRIPTION FOR THE EXACT TIMING OF THE PIO PIN SAMPLING AND UPDATING.
Figure 9c. Control Function Flowchart
______________________________________________________________________________________
15
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
FROM FIGURE 9c
99h
CHAIN COMMAND?
N
Y
MASTER Tx CHAIN
CONTROL BYTE
MASTER Tx RESET?
N
MASTER Tx INVERTED
CHAIN CONTROL BYTE
TRANSMISSION
ERROR?
ERROR DEFINED AS:
REPEATED CONTROL BYTE
NOT EQUAL TO INVERTED
CONTROL BYTE
MASTER Rx "1"s
Y
N
CONTROL BYTE
VALID?
VALID CHAIN CONTROL
BYTE CODES:
3Ch OFF
5Ah ON
96h DONE
N
Y
DS28EA00 UPDATES
CHAIN STATE
MASTER Rx CONFIRMATION
CODE AAh
N
MASTER Tx RESET?
Y
MASTER Rx INVERTED CHAIN
CONTROL BYTE
N
MASTER Tx RESET?
Y
MASTER Rx ERROR
CODE 00h
N
MASTER Tx RESET?
Y
TO FIGURE 9c
Figure 9d. Control Function Flowchart
16
______________________________________________________________________________________
Y
1-Wire Digital Thermometer with
Sequence Detect and PIO
1-Wire physical interface enhancement to improve
noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions.
The DS28EA00 requires a pullup resistor of 2.2kΩ
(max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus must
be left in the idle state if the transaction is to resume. If
this does not occur and the bus is left low for more than
16µs (overdrive speed) or more than 120µs (standard
speed), one or more devices on the bus could be reset.
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS28EA00
is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken
down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots,
which are initiated on the falling edge of sync pulses
from the bus master.
Hardware Configuration
Transaction Sequence
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS28EA00 is
open drain with an internal circuit equivalent to that
shown in Figure 10.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28EA00 supports both a standard and overdrive communication speed of 15.3kbps
(max) and 125kbps (max), respectively. Note that legacy 1-Wire products support a standard communication
speed of 16.3kbps and overdrive of 142kbps. The
slightly reduced rates for the DS28EA00 are a result of
additional recovery times, which in turn are driven by a
The protocol for accessing the DS28EA00 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Control Function Command
• Transaction/Data
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by presence pulse(s) transmitted by the slave(s). The
presence pulse lets the bus master know that the
DS28EA00 is on the bus and is ready to operate. For
more details, see the 1-Wire Signaling section.
VPUP
BUS MASTER
DS28EA00 1-Wire PORT
RPUP
DATA
Rx
Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
PORT PIN
Rx
IL
Tx
100Ω MOSFET
Figure 10. Hardware Configuration
______________________________________________________________________________________
17
DS28EA00
1-Wire Bus System
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the eight ROM function commands that the
DS28EA00 supports. All ROM function commands are 8
bits long. A list of these commands follows (refer to the
flowchart in Figure 11).
Read ROM [33h]
This command allows the bus master to read the
DS28EA00’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if
there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of
the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM
sequence, allows the bus master to address a specific
DS28EA00 on a multidrop bus. Only the DS28EA00 that
exactly matches the 64-bit ROM sequence responds to
the following Control Function command. All other
slaves wait for a reset pulse. This command can be
used with a single device or multiple devices on the
bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their registration numbers. By taking advantage
of the wired-AND property of the bus, the master can
use a process of elimination to identify the registration
numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the
bus master issues a triplet of time slots. On the first slot,
each slave device participating in the search outputs
the true value of its registration number bit. On the second slot, each slave device participating in the search
outputs the complemented value of its registration number bit. On the third slot, the master writes the true
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participating in the search. If both of the read bits are zero, the
18
master knows that slave devices exist with both states
of the bit. By choosing which state to write, the bus
master branches in the ROM code tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to
Application Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example. The Search
ROM command does not reveal any information about
the location of a device in a network. If multiple
DS28EA00 are wired as a linear network (“chain”), the
device location can be detected using Conditional
Read ROM in conjunction with the Chain function.
Conditional Search ROM [ECh]
The Conditional Search ROM command operates similarly to the Search ROM command except that only those
devices which fulfill certain conditions, participate in the
search. This function provides an efficient means for the
bus master to identify devices on a multidrop system that
have to signal an important event. After each pass of the
conditional search that successfully determined the
64-bit ROM code for a specific device on the multidrop
bus, that particular device can be individually accessed
as if a Match ROM had been issued, since all other
devices have dropped out of the search process and are
waiting for a reset pulse. The DS28EA00 responds to the
conditional search ROM command if a temperature
alarm condition exists. For more details see the
Temperature Alarm Registers section.
Conditional Read ROM [0Fh]
This command is used in conjunction with the Chain
function to detect the physical sequence of devices in a
linear network (chain). A DS28EA00 responds to
Conditional Read ROM if two conditions are met: a) the
device is in chain ON state, and b) the EN input (PIOB)
is at logic 0. This condition is met by exactly one device
during the sequence discovery process. Upon receiving the Conditional Read ROM command, this particular device transmits its 64-bit registration number. A
device in chain ON state, but with a logic 1 level at EN
does not respond to Conditional Read ROM. See the
Sequence Discovery Procedure section for more details
on the use of Conditional Read ROM and the Chain
commands.
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the control functions
without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive-Skip ROM sets
the DS28EA00 in the overdrive mode (OD = 1). All communication following this command has to occur at
overdrive speed until a reset pulse of minimum 480µs
duration resets all devices on the bus to standard
speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed has to be
issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the
search process. If more than one slave supporting
overdrive is present on the bus and the Overdrive-Skip
ROM command is followed by a Read command, data
collision occurs on the bus as multiple slaves transmit
simultaneously (open-drain pulldowns produce a wiredAND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a
64-bit ROM sequence transmitted at overdrive speed
allows the bus master to address a specific DS28EA00
on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS28EA00 that exactly matches
the 64-bit ROM sequence responds to the subsequent
control function command. Slaves already in overdrive
mode from a previous Overdrive-Skip ROM or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to
standard speed at the next reset pulse of minimum
480µs duration. The Overdrive-Match ROM command
can be used with a single device or multiple devices on
the bus.
______________________________________________________________________________________
19
DS28EA00
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the control
functions without providing the 64-bit ROM code. If
more than one slave is present on the bus and, for
example, a read command is issued following the Skip
ROM command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
BUS MASTER Tx
RESET PULSE
FROM FIGURE 11b
FROM CONTROL FUNCTIONS
FLOWCHART (FIGURE 9)
OD
RESET PULSE?
N
OD = 0
Y
BUS MASTER Tx ROM
FUNCTION COMMAND
33h
READ ROM
COMMAND?
DS28EA00 Tx
PRESENCE PULSE
N
Y
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
N
Y
ECh
CONDITIONAL SEARCH
COMMAND?
N
Y
N
TO FIGURE 11b
Y
N
TEMPERATURE
ALARM?
Y
DS28EA00 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
BIT 0 MATCH?
N
N
DS28EA00 Tx BIT 0
DS28EA00 Tx BIT 0
DS28EA00 Tx BIT 0
DS28EA00 Tx BIT 0
MASTER Tx BIT 0
MASTER Tx BIT 0
BIT 0 MATCH?
MASTER Tx BIT 1
BIT 1 MATCH?
N
N
DS28EA00 Tx BIT 1
DS28EA00 Tx BIT 1
DS28EA00 Tx BIT 1
DS28EA00 Tx BIT 1
MASTER Tx BIT 1
MASTER Tx BIT 1
BIT 1 MATCH?
N
Y
Y
DS28EA00 Tx
CRC BYTE
MASTER Tx BIT 63
BIT 63 MATCH?
N
N
BIT 0 MATCH?
Y
Y
Y
DS28EA00 Tx
SERIAL NUMBER
(6 BYTES)
N
BIT 1 MATCH?
Y
DS28EA00 Tx BIT 63
DS28EA00 Tx BIT 63
DS28EA00 Tx BIT 63
DS28EA00 Tx BIT 63
MASTER Tx BIT 63
MASTER Tx BIT 63
BIT 63 MATCH?
Y
Y
N
BIT 63 MATCH?
Y
TO FIGURE 11b
FROM FIGURE 11b
TO CONTROL FUNCTIONS
FLOWCHART (FIGURE 9)
Figure 11a. ROM Functions Flowchart
20
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
TO FIGURE 11a
FROM FIGURE 11a
0Fh
CONDITIONAL
READ ROM?
N
Y
CHAIN = ON?
CCh
SKIP ROM
COMMAND?
3Ch
OVERDRIVESKIP ROM?
N
Y
N
69h
OVERDRIVEMATCH ROM?
Y
Y
OD = 1
OD = 1
N
N
Y
MASTER Tx BIT 0
EN = LOW?
N
MASTER Tx
RESET?
Y
N
Y
BIT 0 MATCH?
DS28EA00 Tx
FAMILY CODE
(1 BYTE)
*
OD = 0
Y
MASTER Tx BIT 1
DS28EA00 Tx
SERIAL NUMBER
(6 BYTES)
DS28EA00 Tx
CRC BYTE
N
MASTER Tx
RESET?
N
Y
BIT 1 MATCH?
N
*
OD = 0
Y
MASTER Tx BIT 63
BIT 63 MATCH?
FROM FIGURE 11a
N
*
OD = 0
Y
TO FIGURE 11a
*THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
Figure 11b. ROM Functions Flowchart
______________________________________________________________________________________
21
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
1-Wire Signaling
device is in overdrive mode and tRSTL is between 80µs
and 480µs, the device resets, but the communication
speed is undetermined.
After the bus master has released the line, it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor, or in the case of a DS2482x00 or DS2480B driver, by active circuitry. When the
threshold VTH is crossed, the DS28EA00 waits for tPDH
and then transmits a presence pulse by pulling the line
low for tPDL. To detect a presence pulse, the master
must test the logical state of the 1-Wire line at tMSP.
The tRSTH window must be at least the sum of tPDHMAX,
t PDLMAX , and t RECMIN . Immediately after t RSTH is
expired, the DS28EA00 is ready for data communication. In a mixed population network, tRSTH should be
extended to minimum 480µs at standard speed and
48µs at overdrive speed to accommodate other 1-Wire
devices.
The DS28EA00 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data.
Except for the presence pulse, the bus master initiates
all falling edges. The DS28EA00 can communicate at
two different speeds, standard speed and overdrive
speed. If not explicitly set into the overdrive mode, the
DS28EA00 communicates at standard speed. While in
overdrive mode the fast timing applies to all waveforms.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from
VILMAX past the threshold VTH. The time it takes for the
voltage to make this rise is seen in Figure 12 as “ε” and
its duration depends on the pullup resistor (RPUP) used
and the capacitance of the 1-Wire network attached.
The voltage VILMAX is relevant for the DS28EA00 when
determining a logical level, not triggering any events.
Figure 12 shows the initialization sequence required to
begin any communication with the DS28EA00. A reset
pulse followed by a presence pulse indicates the
DS28EA00 is ready to receive data, given the correct
ROM and control function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for tRSTL + tF to compensate for the edge.
A tRSTL duration of 480µs or longer exits the overdrive
mode, returning the device to standard speed. If the
DS28EA00 is in overdrive mode and tRSTL is no longer
than 80µs, the device remains in overdrive mode. If the
Read/Write Time Slots
Data communication with the DS28EA00 takes place in
time slots, which carry a single bit each. Write time slots
transport data from bus master to slave. Read time
slots transfer data from slave to master. Figure 13 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the
data line low. As the voltage on the 1-Wire line falls
below the threshold VTL, the DS28EA00 starts its internal timing generator that determines when the data line
is sampled during a write time slot and how long data is
valid during a read time slot.
MASTER Tx "RESET PULSE"
MASTER Rx "PRESENCE PULSE"
ε
tMSP
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tRSTL
tPDH
tF
tPDL
tREC
tRSTH
RESISTOR
MASTER
DS28EA00
Figure 12. Initialization Procedure “Reset and Presence Pulses”
22
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
RESISTOR
MASTER
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tREC
tSLOT
RESISTOR
MASTER
READ-DATA TIME SLOT
tMSR
tRL
VPUP
VIHMASTER
VTH
MASTER
SAMPLING
WINDOW
VTL
VILMAX
0V
δ
tF
tREC
tSLOT
RESISTOR
MASTER
DS28EA00
Figure 13. Read/Write Timing Diagram
______________________________________________________________________________________
23
DS28EA00
1-Wire Digital Thermometer with
Sequence Detect and PIO
Master-to-Slave
For a write-one time slot, the voltage on the data line
must have crossed the VTH threshold before the writeone low time tW1LMAX is expired. For a write-zero time
slot, the voltage on the data line must stay below the
VTH threshold until the write-zero low time tW0LMIN is
expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during
the entire tW0L or tW1L window. After the VTH threshold
has been crossed, the DS28EA00 needs a recovery
time tREC before it is ready for the next time slot.
device to lose synchronization with the master and,
consequently, result in a search ROM command coming to a dead end or cause a device-specific function
command to abort. For better performance in network
applications, the DS28EA00 uses a new 1-Wire frontend, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave
device itself.
The 1-Wire front-end of the DS28EA00 differs from traditional slave devices in four characteristics:
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
line impedance than a digitally switched transistor,
converting the high-frequency ringing known from
traditional devices into a smoother low-bandwidth
transition. The slew-rate control is specified by the
parameter tFPD, which has different values for standard and overdrive speed.
Slave-to-Master
A read-data time slot begins like a write-one time slot.
The voltage on the data line must remain below VTL
until the read low time tRL is expired. During the tRL
window, when responding with a 0, the DS28EA00
starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the
DS28EA00 does not hold the data line low at all, and
the voltage starts rising as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS28EA00 on the other side
define the master sampling window (t MSRMIN to
tMSRMAX) in which the master must perform a read from
the data line. For the most reliable communication, tRL
should be as short as permissible, and the master
should read close to but no later than tMSRMAX. After
reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery time
tREC for the DS28EA00 to get ready for the next time slot.
Note that tREC specified herein applies only to a single
DS28EA00 attached to a 1-Wire line. For multidevice
configurations, tREC needs to be extended to accommodate the additional 1-Wire device input capacitance.
Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or
DS2480B 1-Wire line drivers can be used.
4) There is a time window specified by the rising edge
hold-off time t REH during which glitches are
ignored, even if they extend below V TH - V HY
threshold (Figure 14, Case B, tGL < tREH). Deep
voltage droops or glitches that appear late after
crossing the VTH threshold and extend beyond the
tREH window cannot be filtered out and are taken as
the beginning of a new time slot (Figure 14, Case C,
tGL ≥ tREH).
Improved Network Behavior
(Switchpoint Hysteresis)
Devices that have the parameters VHY and tREH specified in their electrical characteristics use the improved
1-Wire front-end.
In a 1-Wire environment, line termination is possible
only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from
end points and branch points can add up, or cancel
each other to some extent. Such reflections are visible
as glitches or ringing on the 1-Wire communication line.
Noise coupled onto the 1-Wire line from external
sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave
Precondition: The PIOB pin (EN) of the first device in
the chain is at logic 0. The PIOA pin (DONE) of the first
device connects to the PIOB of the second device in
the chain, etc., as shown in Figure 15. The 1-Wire master detects the physical sequence of the devices in the
chain by performing the following procedure.
Starting Condition: The master issues a Skip ROM
command followed by a Chain ON command, which
puts all devices in the chain ON state. The pullup
24
2) There is additional lowpass filtering in the circuit
that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not
apply at overdrive speed.
3) There is a hysteresis at the low-to-high switching
threshold VTH. If a negative glitch crosses VTH but
does not go below VTH - VHY, it is not recognized
(Figure 14, Case A). The hysteresis is effective at
any 1-Wire speed.
Sequence Discovery Procedure
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
tREH
tREH
VPUP
VTH
VHY
CASE A
CASE B
CASE C
0V
tGL
tGL
Figure 14. Noise Suppression Scheme
through RCO of the PIOA pin charges the PIOA/PIOB
connections to logic 1 level at all devices except for the
first device in the chain. If a local VDD supply is not
available, the master needs to activate a low-impedance bypass to the 1-Wire pullup resistor immediately
after the inverted chain control byte until the PIOA/PIOB
connections have reached a voltage equivalent to the
logic 1 level.
First Cycle: The master sends a Conditional Read ROM
command, which causes the first device in the chain to
respond with its 64-bit registration number. The master
memorizes the registration number and the fact that this
is the first device in the chain. Next, the master transmits
a Chain DONE command. Through the PIOA pin of the
just discovered device, this asserts logic 0 at the PIOB
pin of the second device in the chain and also prevents
the just discovered device from responding again.
Second Cycle: The master sends a Conditional Read
ROM command. Since the second DS28EA00 is the
only device in the chain with a low level at PIOB, it
responds with its registration number. The master
stores the registration number with the sequence number of 2. The first device cannot respond since it is in
chain DONE state. Next, the master transmits a Chain
DONE command.
Additional Cycles: To identify the registration numbers
of the remaining devices and their physical sequence,
the master repeats the steps of Conditional Read ROM
and Chain DONE. If there is no response to Conditional
Read ROM, all devices in the chain are identified.
Ending Condition: At the end of the discovery process
all devices in the chain are in the chain DONE state.
The master should end the sequence discovery by
issuing a Skip ROM command followed by a Chain OFF
command. This puts all the devices into the chain OFF
state and transfers control of the PIOB and PIOA pins to
the PIO Access Read and Write function commands.
VDD
1-Wire
MASTER
#1
#2
#3
VDD
PX. Y
VDD
IO
VDD
IO
DS28EA00
IO
DS28EA00
DS28EA00
MICROCONTROLLER
PIOB
PIOA
GND
PIOB
*
PIOA
GND
PIOB
*
PIOA
GND
*CAPACITANCE OF THE CABLING BETWEEN ADJACENT DEVICES IN THE CHAIN.
Figure 15. DS28AE00 Wired for Sequence Discovery (“Chain Function”)
______________________________________________________________________________________
25
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
Command-Specific 1-Wire Communication Protocol—Legend
SYMBOL
RST
DESCRIPTION
1-Wire reset pulse generated by master
PD
1-Wire presence pulse generated by slave
SELECT
Command and data to satisfy the ROM function protocol
SKIPR
ROM function command: “Skip ROM”
CDRR
ROM function command: “Conditional Read ROM”
WSP
Command: “Write Scratchpad”
RSP
Command: “Read Scratchpad”
CPSP
Command: “Copy Scratchpad”
CTEMP
RPM
Command: “Convert Temperature”
Command: “Read Power Mode”
RCLE
Command: “Recall EEPROM”
PIOR
Command: “PIO Access Read”
PIOW
Command: “PIO Access Write”
CHAIN
Command : “Chain”
<n Bytes>
Transfer of n bytes
CRC
Transfer of a CRC byte
<xxh>
00 Loop
Transfer of a specific byte value “xx” (hexadecimal notation)
Indefinite loop where the master reads 00 bytes
FF Loop
Indefinite loop where the master reads FF bytes
AA Loop
Indefinite loop where the master reads AA bytes
xx Loop
Indefinite loop where the slave transmits the inverted invalid control byte
CONVERSION
PROGRAMMING
A temperature conversion takes place; activity on the 1-Wire bus is permitted only with local VDD supply
Data transfer to backup EEPROM; activity on the 1-Wire bus is permitted only with local VDD supply
Command-Specific 1-Wire Communication Protocol—Color Codes
Master-to-Slave
26
Slave-to-Master
Programming
Conversion
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
Write Scratchpad
RST PD SELECT WSP <3 Bytes> RST PD
Read Scratchpad
RST PD SELECT RSP <8 Bytes> CRC FF Loop
Copy Scratchpad (Parasite Powered)
RST PD SELECT CPS
Wait tPROGMAX
FF Loop
During the wait, the master should activate a low-impedance
bypass to the 1-Wire pullup resistor.
Copy Scratchpad (Local VDD Powered)
RST PD SELECT CPS <00h>
FF Loop
The master reads 00h bytes until the write cycle is completed.
Convert Temperature (Parasite Powered)
RST PD SELECT CTEMP
Wait tCONVMAX
FF Loop
During the wait, the master should activate a low-impedance
bypass to the 1-Wire pullup resistor.
Convert Temperature (Local VDD Powered)
RST PD SELECT CTEMP <00h>
FF Loop
The master reads 00h bytes until the conversion is completed.
Read Power Mode (Parasite Powered)
RST PD SELECT RPM <00h>
Read Power Mode (Local VDD Powered)
RST PD SELECT RPM <FFh>
Recall EEPROM
RST PD SELECT
RCLE
<00h>
FF Loop
The master reads 00h bytes until the recall is completed.
PIO Access Read
RST PD SELECT
PIOR
See the command description for behavior if the device is in chain
ON or chain DONE state.
<PIO Status Byte>
Continues until master sends reset pulse.
PIO Access Write (Success)
RST PD SELECT
PIOW
<PIO Output Data>
<PIO Output Data>
<AAh>
<PIO Status Byte>
Loop until master sends reset pulse.
______________________________________________________________________________________
27
DS28EA00
1-Wire Communication Examples
1-Wire Digital Thermometer with
Sequence Detect and PIO
DS28EA00
1-Wire Communication Examples (continued)
PIO Access Write (Invalid Data Byte)
RST PD SELECT
PIOW
<PIO Output Data>
<Invalid Data Byte>
FF Loop
The PIO Access Write command is ignored by the device while in chain ON or chain DONE state.
Change Chain State (Success)
RST PD SELECT CHAIN <Chain Control Byte> <Chain Control Byte> AA Loop
Change Chain State (Transmission Error)
RST PD SELECT CHAIN <Any Byte>
<Byte ≠ Inverted Previous Byte>
00 Loop
Change Chain State (Invalid Control Byte)
RST PD SELECT CHAIN <Invalid Control Byte> <Inverted Previous Byte>
xx Loop
Sequence Discovery Example
RST PD
SKIPR CHAIN <5Ah> <A5h>
Wait for chain to charge
RST PD
CDRR
<Registration Number> CHAIN <96h> <69h> <AAh>
RST PD
CDRR
<Registration Number> CHAIN <96h> <69h> <AAh>
RST PD
CDRR
<8 Bytes FFh>
RST PD
SKIPR
Chain <3Ch> <C3h> <AAh>
Put all devices into
chain ON state.
<AAh>
No response: all devices have
been discovered
Identify the first device and
put it into chain DONE state.
Identify the next device and
put it into chain DONE state.
Repeat this sequence until
no device responds.
Put all devices into chain OFF state.
For the sequence discovery to function properly, the logic state at PIOB (EN) must not change during the transmission of
the Conditional Read ROM command code, and, if the device responds, must stay at logic 0 until the entire 64-bit registration number is transmitted.
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
IO
1
N.C.
2
N.C.
3
GND
4
+
DS28EA00
8
VDD
7
PIOB
6
PIOA
5
N.C.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
8 µSOP
U8+1
21-0036
μSOP
28
______________________________________________________________________________________
1-Wire Digital Thermometer with
Sequence Detect and PIO
PAGES
CHANGED
REVISION
NUMBER
REVISION
DATE
0
1/07
Initial release.
—
1
6/07
Changed the storage temperature range in the Absolute Maximum Ratings
section from -40°C to +85°C to -55°C to +125°C.
2
2
4/09
Created newer template-style data sheet.
DESCRIPTION
All
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
DS28EA00
Revision History