IS49FL004T 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory SEPTEMBER 2013 FEATURES • Single Power Supply Operation - Low voltage range: 3.0 V - 3.6 V • Firmware HUB (FWH)/Low Pin Count (LPC) - IS49FL004: One hundred and twenty-eight uniform 4 Kbyte sectors, or eight uniform 64 Kbyte blocks (sector group) Mode - 33 MHz synchronous operation with PCI bus - 5-signal communication interface for in-system read and write operations - Standard SDP Command Set - Data# Polling and Toggle Bit features - Register-based read and write protection for each block (FWH mode only) - 4 ID pins for multiple Flash chips selection (FWH mode only) - 5 GPI pins for General Purpose Input Register - TBL# pin for hardware write protection to Boot Block - WP# pin for hardware write protection to whole memory array except Boot Block • Top Boot Block • Address/Address Multiplexed (A/A Mux) - IS49FL004: 64 Kbyte top Boot Block Mode - 11-pin multiplexed address and 8-pin data I/O interface - Supports fast programming on EPROM programmers • Standard Intel Firmware Hub/LPC Interface - Read compatible to Intel® 82802 Firmware Hub devices - Conforms to Intel LPC Interface Specification Revision 1.1 • Memory Configuration - IS49FL004: 512K x 8 (4 Mbit) • Cost Effective Sector/Block Architecture • Automatic Erase and Program Operation - Build-in automatic program verification for extended product endurance - Typical 25 µs/byte programming time - Typical 50 ms sector/block/chip erase time - Standard SDP Command Set - Data# Polling and Toggle Bit features • Two Configurable Interfaces - In-System hardware interface: Auto detection of Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle for in-system read and write operations - Address/Address-Multiplexed (A/A Mux) interface for programming on EPROM Programmers during manufacturing • Lower Power Consumption - Typical 2 mA active read current - Typical 7 mA program/erase current • High Product Endurance - Guarantee 100,000 program/erase cycles per single sector (preliminary) - Minimum 20 years data retention • Compatible Pin-out and Packaging - 32-pin (8 mm x 14 mm) VSOP - 32-pin PLCC • Hardware Data Protection Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 1 IS49FL004T GENERAL DESCRIPTION The IS49FL004 is 4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform insystem or off-system read, erase and program operations. The 12.0 Volt VPP power supply are not required for the program and erase operations of devices. The devices conform to Intel® Low Pin Count (LPC) Interface specification revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applications. The IS49FL004 support two configurable interfaces: In-system hardware interface which can automatic de- tect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed (A/ A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great flexibility and simplicity for design, procurement, and material inventory. The memory array of IS49FL004 is divided into uniform 4 Kbyte sectors, or uniform 64 Kbyte blocks (sector group consists of sixteen adjecent sectors). The sector or block erase feature allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera- tion. The program operation of IS49FL004 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of the devices is executed by issuing the sector, block, or chip erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6. The IS49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers (FWH mode only). The IS49FL004 are manufactured on pFLASH™’s advanced nonvolatile technology. The devices are offered in 32-pin VSOP and PLCC packages with optional environmental friendly Halogen-free package. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 2 IS49FL004T GPI0 A6 WP# WP# A5 32 31 30 GPI4 VCC VCC NC GPI3 GPI2 GPI4 1 CLK 2 NC 3 GPI3 4 GPI2 A10 GPI0 R/C# CLK 5 VCC A7 NC A/A Mux GPI1 RST# RST# RST# FWH A9 LPC GPI1 A8 A/A Mux LPC FWH CONNECTION DIAGRAMS A/A Mux LPC FWH 29 IC IC IC 6 28 GND GND GND 7 27 NC NC NC A4 8 26 NC NC RES A3 9 25 VCC VCC VCC ID2 RES A2 10 24 OE# INIT# INIT# ID1 RES A1 11 23 WE# ID0 RES A0 12 22 NC NC NC FWH0 LAD0 I/O0 13 21 I/O7 RES RES I/O4 I/O5 I/O6 RES RES RES RES RES RES 20 LAD3 19 FWH3 18 GND LAD2 FWH2 17 GND I/O1 16 GND A/A Mux LPC LAD1 FWH 15 FWH1 14 I/O3 TBL# ID3 I/O2 TBL# NC LFRAME# FWH4 32-PIN PLCC FWH NC NC NC GND IC GPI4 CLK VCC NC RST# GPI3 GPI2 GPI1 GPI0 WP# TBL# LPC NC NC NC GND IC GPI4 CLK VCC NC RST# GPI3 GPI2 GPI1 GPI0 WP# TBL# A/A Mux NC NC NC GND IC A10 R/C# VCC NC RST# A9 A8 A7 A6 A5 A4 A/A Mux 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# WE# NC I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 LPC INIT# LFRAME# NC RES RES RES RES LAD3 GND LAD2 LAD1 LAD0 RES RES RES RES FWH INIT# FWH4 NC RES RES RES RES FWH3 GND FWH2 FWH1 FWH0 ID0 ID1 ID2 ID3 32-PIN (8mm x 14mm) VSOP Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 3 IS49FL004T PIN DESCRIPTIONS In te rfa c e S YM B O L T YP E D E S C R IP T IO N PP FW H LPC A [1 0 :0 ] I X A d d re s s Inp uts : F o r i np uti ng the m ulti p le x a d d re s s e s a nd c o m m a nd s i n P P m o d e . R o w a nd c o lum n a d d re s s e s a re la tc he d d uri ng a re a d o r w ri te c yc le c o ntro lle d b y R /C # p i n. R /C # I X R o w /C o lum n S e le c t: To i nd i c a te the ro w o r c o lum n a d d re s s i n P P m o d e . W he n thi s p i n g o e s lo w, the ro w a d d re s s i s la tc he d . W he n thi s p i n g o e s hi g h, the c o lum n a d d re s s i s la tc he d . I/O X D a ta Inp uts /O utp uts : U s e d fo r A /A M ux m o d e o nly, to i np ut c o m m a nd /d a ta d uri ng w ri te o p e ra ti o n a nd to o utp ut d a ta d uri ng re a d o p e ra ti o n. T he d a ta p i ns flo a t to tri -s ta te w he n O E # i s d i s a b le d . WE# I X W ri te E na b le : A c ti va te the d e vi c e fo r w ri te o p e ra ti o n. W E # i s a c ti ve lo w. OE # I X O utp ut E na b le : C o ntro l the d e vi c e 's o utp ut b uffe rs d uri ng a re a d c yc le . O E # i s a c ti ve lo w. I/O [7 :0 ] IC I X X X Inte rfa c e C o nfi g ura ti o n S e le c t: T hi s p i n d e te rm i ne s w hi c h m o d e i s s e le c te d . W he n p ulls hi g h, the d e vi c e e nte rs i nto A /A M ux m o d e . W he n p ulls lo w, F W H /L P C m o d e i s s e le c te d . T hi s p i n m us t b e s e tup d uri ng p o w e r-up o r s ys te m re s e t, a nd s ta ys no c ha ng e d uri ng o p e ra ti o n. Thi s p i n i s i nte rna lly p ulle d d o w n w i th a re s i s to r b e tw e e n 2 0 -1 0 0 K RS T# I X X X R e s e t: To re s e t the o p e ra ti o n o f the d e vi c e a nd re turn to s ta nd b y m o d e . IN IT # I X X Ini ti a li ze : Thi s i s a s e c o nd re s e t p i n fo r i n-s ys te m us e . IN IT # o r R S T # p i n p ulls lo w w i ll i ni ti a te a d e vi c e re s e t. G P I[4 :0 ] I X X F W H /L P C G e ne ra l P urp o s e Inp uts : U s e d to s e t the G P I_ R E G fo r s ys te m d e s i g n p urp o s e o nly. T he va lue o f G P I_ R E G c a n b e re a d thro ug h F W H i nte rfa c e . The s e p i ns s ho uld b e s e t a t d e s i re d s ta te b e fo re the s ta rt o f the P C I c lo c k c yc le fo r re a d o p e ra ti o n a nd s ho uld re m a i n no c ha ng e unti l the e nd o f the re a d c yc le . U nus e d G P I p i ns m us t no t b e flo a te d . TB L # I X X To p B lo c k L o c k : W he n p ulls lo w, i t e na b le s the ha rd w a re w ri te p ro te c ti o n fo r to p b o o t b lo c k . W he n p ulls hi g h, i t d i s a b le s the ha rd w a re w ri te p ro te c ti o n. WP# I X X W ri te P ro te c t: W he n p ulls lo w, i t e na b le s the ha rd w a re w ri te p ro te c ti o n to the m e m o ry a rra y e xc e p t the to p b o o t b lo c k . W he n p ulls hi g h, i t d i s a b le s ha rd w a re w ri te p ro te c ti o n. I/O X F W H A d d re s s a nd D a ta : T he m a jo r I/O p i ns fo r tra ns m i tti ng d a ta , a d d re s s e s a nd c o m m a nd c o d e i n F W H m o d e . I X F W H Inp ut: To i nd i c a te the s ta rt o f a F W H m e m o ry c yc le o p e ra ti o n. A ls o us e d to a b o rt a F H W m e m o ry c yc le i n p ro g re s s . F W H [3 :0 ] FW H4 I/O X L P C A d d re s s a nd D a ta : T he m a jo r I/O p i ns fo r tra ns m i tti ng d a ta , a d d re s s e s a nd c o m m a nd c o d e i n L P C m o d e . L F RA M E # I X L P C F ra m e : To i nd i c a te the s ta rt o f a L P C m e m o ry c yc le o p e ra ti o n. A ls o us e d to a b o rt a L P C m e m o ry c yc le i n p ro g re s s . CLK I X F W H /L P C C lo c k : To p ro vi d e a s ync hro no us c lo c k fo r F W H a nd L P C m o d e o p e ra ti o ns . L A D [3 :0 ] ID [3 :0 ] X I Id e nti fi c a ti o n Inp uts : T he s e fo ur p i ns a re p a rt o f the m e c ha ni s m tha t a llo w s m ulti p le F W H d e vi c e s to b e a tta c he d to the s a m e b us . The s tra p p i ng o f the s e p i ns i s us e d to i d e nti fy the c o m p o ne nt. T he b o o t d e vi c e m us t ha ve ID [3 :0 ] = 0 0 0 0 b a nd i t i s re c o m m e nd e d tha t a ll s ub s e q ue nt d e vi c e s s ho uld us e s e q ue nti a l up -c o unt s tra p p i ng . The s e p i ns a re i nte rna lly p ulle d -d o w n w i th a re s i s to r b e tw e e n 2 0 -1 0 0 K X V CC X X X D e vi c e P o w e r S up p ly GN D X X X G ro und NC X X X N o C o nne c ti o n X X R e s e rve d : R e s e rve d func ti o n p i ns fo r future us e . RE S Note: I = Input, O = Output Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 4 IS49FL004T BLOCK DIAGRAM ERASE/PROGRAM VOLTAGE GENERATOR TBL# W P# INIT# FWH[3:0] or LAD[3:0] FWH4 or LFRAME# CLK GPI[4:0] I/O B U F FE R S FWH/LPC MODE INTERFACE HI GH V O L T A G E SWITCH A[10:0] I/O[7:0] WE# PP MODE INTERFACE CONTROL LOGIC OE # R/C# DATA LATCH SENSE AMP IC ADDRESS LATCH RST# Y -G A T I N G Y-DECODER X-DECODER MEMORY ARRAY DEVICE OPERATION MODE SELECTION PRODUCT IDENTIFICATION The IS49FL004 can operate in two configurable interfaces: The In-System Hardware interface and Address/Address Multiplexed (A/A Mux) interface controlled by IC pin. If the IC pin is set to logic high (VIH), the devices enter into A/A Mux interface mode. If the IC pin is set logic low (VIL), the devices will be in in-system hardware interface mode. During the in-system hardware interface mode, the devices can automatically detect the Firmware Hub (FWH) or Low Pin Count (LPC) memory cycle sent from host system and response to the command accordingly. The IC pin must be setup during power-up or system reset, and stays no change during device operation. The product identification mode can be used to read the Manufacturer ID and the Device ID by a software Product ID Entry command in both in-system hardware interface and A/A Mux interface modes. The product indentification mode is activated by three-bus-cycle command. Refer to Table 1 for the Manufacturer ID and Device ID of IS49FL00x and Table 14 for the SDP Command Definition. When working in-system, typically on a PC or Notebook, the IS49FL004 are connected to the host system through a 5-pin communication interface operated based on a 33-MHz synchronous clock. The 5-pin interface is defined as FWH[3:0] and FWH4 pins under FWH mode or as LAD[3:0] and LFRAME# pins under LPC mode for easy understanding as to those existing compatible products. When working off-system, typically on a EPROM Programmer, the devices are operated through 11-pin multiplexed address - A[10:0] and 8-pin data I/O - I/O[7: 0] interfaces. The memory addresses of devices are input through two bus cycles as row and column addresses controlled by a R/C# pin. Table 1: Product Identification Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 In FWH mode, the product identification can also be read directly at FFBC0000h for Manufacturer ID - “9Dh” and FFBC0001h for Device ID in the 4 GByte system memory map. Description Manufacturer ID Device ID IS49FL004 4Mb Address Data 00000h 00002h 9Dh 7Fh 00001h 6Eh 5 IS49FL004T DEVICE OPERATION (CONTINUED) The IS49FL004 provide three levels of data protec- tion for the critical BIOS code of PC and Notebook. It includes memory hardware write protection, hardware data protection and software data protection. MEMORY HARDWARE WRITE PROTECTION The IS49FL004 has a 64 Kbyte top boot block. When work- ing in-system, the memory hardware write protection fea- ture can be activated by two control pins - Top Block Lock (TBL#) and Write Protection (WP#) for both FWH and LPC modes. When TBL# is pulled low (V ), the boot block is hardware write IL protected. A sector erase, block erase, or byte program command attempts to erase or program the boot block will be ignored. When WP# is pulled low (V ), the Block 0 ~ Block 6 of IS49FL004 (except the IL boot block) are hardware write protected. Any attempt to erase or program a sector or block within this area will be ignored. SOFTWARE DATA PROTECTION The devices feature a software data protection function to protect the device from an unintentional erase or program operation. It is performed by JEDEC standard Software Data Protection (SDP) command sequences. See Table 14 for SDP Command Definition. A program operation is initiated by three memory write cycles of unlock command sequence. A chip (only available in A/A Mux mode), sector or block erase operation is initiated by six memory write cycles of unlock command sequence. During SDP command sequence, any invalid command or sequence will abort the operation and force the device back to standby mode. BYTE PROGRAMMING In program operation, the data is programmed into the devices (to a logical “0”) on a byte-by-byte basis. In FWH and LPC modes, a program operation is activated by writing the three-byte command sequence and program address/data through four consecutive memory write Both TBL# and WP# pins must be set low (VIL) for pro- cycles. In A/A Mux mode, a program operation is actitection or high (VIH) for un-protection prior to a program vated by writing the three-byte command sequence and or erase operation. A logic level change on TBL# or WP# program address/data through four consecutive bus pin during a program or erase operation may cause un- cycles. The row address (A10 - A0) is latched on the falling edge of R/C# and the column address (A21 - A11) predictable results. is latched on the rising edge of R/C#. The data is latched The TBL# and WP# pins work in combination with the on the rising edge of WE#. Once the program operation block locking registers. When active, these pins write is started, the internal control logic automatically handles protect the appropriate blocks regardless of the associ- the internal programming voltages and timing. ated block locking registers setting. A data “0” can not be programmed back to a “1”. Only erase operation can convert “0”s to “1”s. The Data# PollHARDWARE DATA PROTECTION ing on I/O7 or Toggle Bit on I/O6 can be used to detect Hardware data protection protects the devices from un- when the programming operation is completed in FWH, intentional erase or program operation. It is performed LPC, and A/A Mux modes. by the devices automatically in the following three ways: (a) VCC Detection: if VCC is below 1.8 V (typical), the CHIP ERASE The entire memory array can be erased by chip erase program and erase functions are inhibited. (b) Write Inhibit Mode: holding any of the signal OE# operation available under the A/A Mux mode operated low, or WE# high inhibits a write cycle (A/A Mux mode by EPROM Programmer only. Pre-programs the device is not required prior to the chip erase operation. Chip only). (c) Noise/Glitch Protection: pulses of less than 5 ns (typi- erase starts immediately after a six-bus-cycle chip erase cal) on the WE# input will not initiate a write cycle (A/A command sequence. All commands will be ignored once the chip erase operation has started. The Data# Polling Mux mode only). on I/O7 or Toggle Bit on I/O6 can be used to detect the progress or completion of erase operation. The devices will return back to standy mode after the completion of chip erase. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 6 IS49FL004T DEVICE OPERATION (CONTINUED) SECTOR AND BLOCK ERASE I/O6 TOGGLE BIT The IS49FL004 con- tains one hundred and twenty-eight uniform 4 Kbyte sec- tors, or eight uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). A sector erase command is used to erase an individual sector. A block erase command is used to erase an individual block. See Table 12 - 13 for Sector/Block Address Tables. The IS49FL004 also provide a Toggle Bit feature to detect the progress or the completion of a program or erase operation. During a program or erase operation, an attempt to read data from the devices will result in I/ O6 toggling between “1” and “0”. When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase operation. In FWH/LPC mode, an erase operation is activated by writing the six-byte command sequence through six consecutive write memory cycles. In A/A Mux mode, an erase operation is activated by writing the six-byte command in six consecutive bus cycles. Pre-programs the sector or block is not required prior to an erase operation. RESET Any read, program, or erase operation to the devices can be reset by the INIT# or RST# pins. INIT# and RST# pins are internally hard-wired and have same function to the devices. The INIT# pin is only available in FWH and LPC modes. The RST# pin is available in all modes. It I/O7 DATA# POLLING is required to drive INIT# or RST# pins low during sysThe devices provide a Data# Polling feature to indicate tem reset to ensure proper initialization. the progress or the completion of a program or erase operation in all modes. During a program operation, an During a memory read operation, pulls low the INIT# or attempt to read the device will result in the complement RST# pin will reset the devices back to standby mode of the last loaded data on I/O7. Once the program cycle and then the FWH[3:0] of FWH interface or the LAD[3: is complete, the true data of the last loaded data is valid 0] of LPC interface will go to high impedance state. on all outputs. During an erase operation, an attempt to During a program or erase operation, pulls low the INIT# read the device will result a “0” on I/O7. After the erase or RST# pin will abort the program or erase operation cycle is complete, an attempt to read the device will and reset the devices back to standby mode. A reset latency will occur before the devices resume to standby result a “1” on I/O7. mode when such reset is performed. When a program or erase operation is reset before the completion of such operation, the memory contents of devices may become invalid due to an incomplete program or erase operation. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 7 IS49FL004T FWH MODE OPERATION FWH MODE MEMORY READ/WRITE OPERATION FWH ABORT OPERATION In FWH mode, the IS49FL004 are connected through a 5-pin communication interface - FWH[3:0] and FWH4 pins to work with Intel® Family of I/O Controller Hubs (ICH) chipset platforms. The FWH mode also support JEDEC standard Software Data Protection (SDP) product ID entry, byte program, sector erase, and block erase command sequences. The chip erase command sequence is only available in A/A Mux mode. The FWH4 signal indicates the start of a memory cycle or the termination of a cycle in FWH mode. Asserting FWH4 for one or more clock cycle with a valid START value on FWH[3:0] will initiate a memory read or memory write cycle. If the FWH4 is driven low again for one or more clock cycles during this cycle, this cycle will be terminated and the device will wait for the ABORT command “1111b” to release the FWH[3:0] bus. If the abort occurs during the program or erase operation such as The addresses and data are transmitted through the 4- checking the operation status with Data# Polling (I/O7) bit FWH[3:0] bus synchronized with the input clock on or Toggle Bit (I/O6) pins, the read status cycle will be CLK pin during a FWH memory cycle operation. The aborted but the internal program or erase operation will address or data on FWH[3:0] bus is latched on the ris- not be affected. Only the reset operation initiated by RST# ing edge of the clock. The pulse of FWH4 pin inserted or INIT# pin can terminate the program or erase operation. for one clock indicates the start of a FWH memory read or memory write cycle. Once the FWH memory cycle is started, asserted by FWH4, a START value “11xxb” is expected by IS49FL004 as a valid command cycle and is used to indicates the type of memory cycle (“1101b” for FWH memory read cycle or “1110b” for FWH memory write cycle). Addresses and data are transferred to and from the device decided by a series of “fields”. Field sequences and contents are strictly defined for FWH memory read and write operations. Refer to Table 2 and 3 for FWH Memory Read Cycle Definition and FWH Memory Write Cycle Definition. There are 7 clock fields in a FWH memory cycle that gives a 28 bit memory address A27 - A0 through FWH [3:0] pins, but only the last five address fields will be decoded by the FWH devices. The IS49FL004 decodes A18 - A0 with A19 ignored. The address A22 has the special function of directing reads and writes to the Flash array when A22 = 1 or to the register space with A22 = 0. The A27 - A23 and A21 - A20 are don’t care for the devices under FWH mode. The IS49FL004 are mapped within the top 4 Mbyte address range devoted to the FWH devices in the 4 Gbyte system memory space. Please see Table 11 for System Memory Map. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 8 IS49FL004T FWH MODE OPERATION (CONTINUED) Table 2: FWH Memory Read Cycle Definition Clock Cycle Field FWH[3:0] 1 START 1101 IDSEL 0000 to 1111 2 Direction Description IN Start of Cycle: "1101b" to indicate the start of a memory read cycle. IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycles: This is the 28-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and A3 - A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The IS49FL00x only support "0000b" for one byte operation. 11 TAR0 1111 IN then Float 12 TAR1 1111 (float) 13 RSYNC 0000 (READY) OUT Ready Sync: The FWH device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14-15 DATA YYYY OUT Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last). 16 TAR0 1111 OUT then Float 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus during this cycle. IN Turn-Around Cycle 0: The Intel ICH has driven the bus then float it to all "1"s and then floats the bus. Float then Turn-Around Cycle 1: The device takes control of the bus during this cycle. OUT Turn -Around Cycle 0: The FWH device has driven the bus then float it to all "1"s and then floats the bus. FWH MEMORY READ CYCLE WAVEFORMS CLK RST# or INIT# FWH4 Memor y Read Start FWH[3:0] 1101b 1 Clock IDSEL ID[3:0] IMSIZE Address xxxxb x1xxb 1 Clock Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 A[19:16] A[15:12] A[11:8] Load Address in 7 Clocks From Host to Device A[7:4] A[3:0] 0000b TAR 1111b Tri-State 2 Clocks RSYN C 0000b 1 Clock Data D[3:0] D[7:4] TAR 1111b Next Start 1101b Tri-State Data Out 2 Clocks 2 Clocks From Device to Host 1 Clock 9 IS49FL004T FWH MODE OPERATION (CONTINUED) Table 3: FWH Memory Write Cycle Definition Clock Cycle Field FWH[3:0] 1 START 1110 IDSEL 0000 to 1111 2 Direction Description IN Start of Cycle: "1110b" to indicate the start of a memory write cycle. IN ID Select Cycle: Indicates which FWH device should respond. If the IDSEL field matches the value set on ID[3:0] pins, then the particular FWH device will respond to subsequent commands. 3-9 IMADDR YYYY IN Address Cycles: This is the 28-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A27 - 24 on FWH[3:0] first, and A3 - A0 on FWH[3:0] last). 10 IMSIZE 0000 IN Memory Size Cycle: Indicates how many bytes will be or transferred during multi-byte operations. The IS49FL00x only support "0000b" for one byte operation. 11-12 DATA YYYY IN Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on FWH[3:0] last). 13 TAR0 1111 IN then Float 14 TAR1 1111 (float) 15 RSYNC 0000 (READY) OUT 16 TAR0 1111 OUT then Float 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Intel ICH resumes control of the bus during this cycle. IN Turn-Around Cycle 0: The Intel ICH has driven the bus then float it to all "1"s and then floats the bus. Float then Turn-Around Cycle 1: The device takes control of the bus during this cycle. OUT Ready Sync: The FWH device indicates that it has received the data or command. Turn-Around Cycle 0: The FWH device has driven the bus then float it to all "1"s and then floats the bus. FWH MEMORY WRITE CYCLE WAVEFORMS CLK RST# or INIT# FWH4 Memor y Write Start FWH[3:0] 1110b 1 Clock IDSEL ID[3:0] Address xxxxb x1xxb 1 Clock Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 A[19:16] A[15:12] IMSIZE A[11:8] A[7:4] Load Address in 7 Clocks From Host to Device A[3:0] 0000b Data D[3:0] TAR D[7:4] 1 Clock Load Data in 2 Clocks 1111b Tri-State 2 Clocks RSYN C 0000b Next Start TAR 1111b Tri-State 1 Clock 2 Clocks From Device to Host 1110b 1 Clock 10 IS49FL004T FWH MODE OPERATION (CONTINUED) FWH BYTE PROGRAM WAVEFORMS CLK RST# or INIT# FWH4 Memor y Write Cycle FWH[3:0] 1110b 1 Clock Address IDSEL ID[3:0] xxxxb x1xxb 1 Clock xxxxb 0101b Data IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks 0000b 1010b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYN C 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 2nd Start IDSEL 1110b ID[3:0] 1 Clock IMSIZE Address xxxxb x1xxb 1 Clock xxxxb 0010b 1010b 1010b 1010b Load "2AAAh" in 7 Clocks 0000b Data 0101b TAR 0101b 1 Clock Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks RSYN C 1 Clock Host to Device TAR 1111b 0000b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 3rd Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address xxxxb x1xxb xxxxb 0101b 0101b 0101b 0101b Load "5555h" in 7 Clocks 0000b Data 0000b TAR 1010b 1 Clock Load "A0h" in 2 Clocks 1111b Tri-State 2 Clocks RSYN C 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# FWH4 FWH[3:0] 4th Start IDSEL 1110b ID[3:0] 1 Clock 1 Clock IMSIZE Address xxxxb x1xxb A[19:16] A[15:12] A[11:8] A[7:4] Load Address in 7 Clocks 0000b Data D[3:0] TAR D[7:4] 1 Clock Load Data in 2 Clocks Host to Device Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 A[3:1] 1111b Tri-State 2 Clocks RSYN C 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host 11 IS49FL004T FWH SECTOR ERASE WAVEFORMS CLK RST # or INIT# FWH4 Memory Write Cycle IDSE L F W H [ 3: 0 ] 1110b 1 Clock ID[3:0] Address xxxxb x1xxb 1 Clock xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks Host to Device 0000b Dat a 1010b TAR 1010b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock TA R 1111b Tri-State 2 Clocks Device to Host CLK RST # or INIT# FWH4 2nd Start F W H [ 3: 0 ] 1110b 1 C lock Address IDSE L ID[3:0] xxxxb x1xxb 1 C lock xxxxb 0010b IMSIZE 1010b 1010b 1010b L o a d "2AAAh" in 7 C locks 0 0 00 b Dat a 0101b TAR 0101b 1 C lock Load "55h" in 2 Clocks Host to Device 1111b Tri-State 2 C locks RSYNC 1 C lock TA R 1111b 0 00 0 b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 3rd Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0101b IMSIZE 0101b 0101b 01 0 1 b L o a d "5555h" in 7 C locks 0000b Dat a 0000b 10 0 0 b 1 C lock Load "80h" in 2 Clocks TAR 1111b Tri-State 2 C locks RSYNC 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 4th Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0101b IMSIZE 0101b 0101b 0 10 1 b L o a d "5555" in 7 Clocks 0000b Dat a 0101b 1010b 1 C lock Load "AAh" in 2 Clocks Host to Device TAR 1111b Tri-State 2 C locks RSYNC 1 C lock TA R 1111b 0 00 0 b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 5th Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0010b IMSIZE 0010b 1010b 10 1 0 b L o a d "2AAAh" in 7 C locks 0000b Dat a 0101b 01 0 1 b 1 C lock Load "55h" in 2 Clocks Host to Device TAR 1111b Tri-State 2 C locks RSYNC 0 0 00 b 1 C lock TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 6th Start FW H [ 3 : 0 ] 1110b 1 C lock ID[3:0] IMSIZE Address IDSE L xxxxb x1xxb 1 C lock xxxxb SA[19:16] SA[15:12 ] xxxxb xxxxb Loa d Sector Address in 7 C locks Host to Device 0000b Internal Erase Start Dat a 0000b 0011b 1 C lock Load "30h" in 2 Clocks TAR 1111b Tri-State 2 Clocks RSYNC 0 00 0 b 1 Clock TA R 1111b Tri-State 2 Clocks Device to Host SA = Sector Address Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 12 IS49FL004T FWH BLOCK ERASE WAVEFORMS CLK RST # or INIT# FWH4 Memory Write Cycle IDSE L F W H [ 3: 0 ] 1110b 1 Clock ID[3:0] Address xxxxb x1xxb 1 Clock xxxxb 0101b IMSIZE 0101b 0101b 0101b Load "5555h" in 7 Clocks 0000b Dat a 1010b TAR 1010 b 1 Clock Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks RSYNC 0000b 1 Clock Host to Device TA R 1111b Tri-State 2 Clocks Device to Host CLK RST # or INIT# FWH4 2nd Start F W H [ 3: 0 ] 1110b 1 C lock Address IDSE L ID[3:0] xxxxb x1xxb 1 C lock xxxxb 0010b IMSIZE 1010b 1010b 1010b L o a d "2AAAh" in 7 C locks Host to Device 0 0 00 b Dat a 0101b TAR 0101b 1 C lock Load "55h" in 2 Clocks 1111b Tri-State 2 C locks RSYNC 1 C lock TA R 1111b 0 00 0 b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 3rd Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0101b IMSIZE 0101b 0101b 01 0 1 b L o a d "5555h" in 7 C locks 0000b Dat a 0000b TAR 1 0 00 b 1 C lock Load "80h" in 2 Clocks 1111b Tri-State 2 C locks RSYNC 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 4th Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0101b IMSIZE 0101b 0101b 0 1 01 b Loa d "5555" in 7 Clocks Host to Device 0000b Dat a 0101b 1010b 1 C lock Load "AAh" in 2 Clocks TAR 1111b Tri-State 2 C locks RSYNC 1 C lock TA R 1111b 0 00 0 b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 F W H [ 3: 0 ] 5th Start IDSE L 1110b ID[3:0] 1 C lock Address xxxxb x1xxb 1 C lock xxxxb 0010b IMSIZE 0010b 1010b 10 1 0 b L o a d "2AAAh" in 7 C locks Host to Device 0000b Dat a 0101b 0 1 01 b 1 C lock Load "55h" in 2 Clocks TAR 1111b Tri-State 2 C locks RSYNC 0 0 00 b 1 C lock TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# FWH4 FW H [ 3 : 0 ] 6th Start IDSE L 1110 b ID[3:0] 1 Clock IMSIZE Address xxxxb x1xxb 1 Clock xxxxb BA[19:16] BA[15:14 ] + xxb xxxxb xxxxb Load Block Address in 7 Clocks Host to Device 0000b Internal Erase Start Dat a 0000b 0101b 1 C lock Load "50h" in 2 Clocks TAR 1111b Tri-State 2 C locks RSYNC 0000 b 1 C lock TA R 1111b Tri-State 2 Clocks Device to Host BA = Block Address Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 13 IS49FL004T FWH MODE OPERATION (CONTINUED) FWH GPI REGISTER READ WAVEFORMS CLK RST# or INIT# FWH4 FWH[3:0] Memor y Read Cycle IDSEL 1101b ID[3:0] 1 Clock 1 Clock Address xxxxb x0xxb 1100b 0000b IMSIZE 0001b 0000b 0000b 0000b 1 Clock Load Address "xBC0100h" in 7 Clocks From Host to Device TAR 1111b Tri-State RSYN C Data D[7:4] Next Start TAR 1111b Tri-State 0000b D[3:0] 2 Clocks 1 Clock Data Out 2 Clocks 2 Clocks From Device to Host TAR RSYN C 1101b 1 Clock FWH BLOCK LOCKING REGISTER READ WAVEFORMS CLK RST# or INIT# FWH4 FWH[3:0] Memor y Read Cycle IDSEL 1101b ID[3:0] 1 Clock Address xxxxb x0xxb 1 Clock Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 A[19:16] 0000b IMSIZE 0000b 0000b Load Address "xBx0002h" in 7 Clocks From Host to Device 0010b 0000b 1 Clock 1111b Tri-State 2 Clocks 0000b 1 Clock Data D[3:0] Next Start TAR D[7:4] 1111b Tri-State Data Out 2 Clocks 2 Clocks From Device to Host 1101b 1 Clock 14 IS49FL004T LPC MODE OPERATION LPC MODE MEMORY READ/WRITE OPERATION In LPC mode, the IS49FL004 use the 5-pin LPC interface includes 4-bit LAD[3:0] and LFRAME# pins to communicate with the host system. The addresses and data are transmitted through the 4-bit LAD[3:0] bus synchronized with the input clock on CLK pin during a LPC memory cycle operation. The address or data on LAD[3: 0] bus is latched on the rising edge of the clock. The pulse of LFRAME# signal inserted for one or more clocks indicates the start of a LPC memory read or write cycle. Once the LPC memory cycle is started, asserted by LFRAME#, a START value “0000b” is expected by the devices as a valid command cycle. Then a CYCTYPE + DIR value (“010xb” for memory read cycle or “011xb” for memory write cycle) is used to indicates the type of memory cycle. Refer to Table 4 and 5 for LPC Memory Read and Write Cycle Definition. There are 8 clock fields in a LPC memory cycle that gives a 32 bit memory address A31 - A0 through LAD[3: 0] with the most-significant nibble first. The memory space of IS49FL004 are mapped directly to top of 4 Gbyte system memory space. See Table 11 for System Memory Map. The IS49FL004 is mapped to the address location of (FFFFFFFFh - FFF80000h), the A31- A19 must be loaded with “1” to select and activate the device during a LPC memory operation. Only A18 - A0 is used to decode and access the 512 Kbyte memory. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 15 IS49FL004T LPC MODE OPERATION (CONTINUED) Table 4: LPC Memory Read Cycle Definition Clock Cycle Field LAD[3:0] Direction 1 START 0000 IN Start of Cycle: "0000b" indicates the start of a LPC memory cycle. 2 CYCTYPE + DIR IN Cycle Type: Indicates the type of a LPC memory read cycle. CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR: Bit 1 = "0b" indicates the type of cycle for Read. Bit 0 is reserved. Address Cycles: This is the 32-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3 - A0 on LAD[3:0] last). 010x Description 3 - 10 ADDR YYYY IN 11 TAR0 1111 IN then Float 12 TAR1 1111 (float) 13 SYNC 0000 OUT Sync: The device indicates the least-significant nibble of data byte will be ready in next clock cycle. 14 - 15 DATA YYYY OUT Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last). 16 TAR0 1111 OUT then Float 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Chipset resumes control of the bus during this cycle. IN Turn-Around Cycle 0: The Chipset has driven the bus to all "1"s and then float the bus. Float then Turn-Around Cycle 1: The device takes control of the bus during this cycle. OUT Turn-Around Cycle 0: The device has driven the bus to all "1"s and then floats the bus. LPC MEMORY READ CYCLE WAVEFORMS CLK RST# or INIT# LF RAME # LAD[3:0] Start Memor y Read Cycle 0000b 010Xb 1 Clock 1 Clock Address 1111b 1111b Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 1111b 11b + A[17:16] TAR A[15:12] Load Address in 8 Clocks From Host to Device A[11:8] A[7:4] A[3:0] 1111b Tri-State 2 Clocks SYN C Data D[7:4] Next Start TAR 0000b D[3:0] 1 Clock Data Out 2 Clocks 2 Clocks From Device to Host 1111b 0000b Tri-State 1 Clock 16 IS49FL004T LPC MODE OPERATION (CONTINUED) Table 5: LPC Memory Write Cycle Definition Clock Cycle Field LAD[3:0] Direction 1 START 0000 IN Start of Cycle: "0000b" to indicate the start of a LPC memory cycle. 2 CYCTYPE + DIR IN Cycle Type: Indicates the type of a LPC memory write cycle. CYCTYPE: Bits 3 - 2 must be "01b" for memory cycle. DIR: Bit 1 = "1b" indicates the type of cycle for Write. Bit 0 is reserved. 011x Description 3 - 10 ADDR YYYY IN Address Cycles: This is the 32-bit memory address. The addresses transfer most-significant nibble first and leastsignificant nibble last. (i.e., A31 - 28 on LAD[3:0] first, and A3 - A0 on LAD[3:0] last). 11 - 12 DATA YYYY IN Data Cycles: The 8-bits data transferred with least-significant nibble first and most-significant nibble last. (i.e., I/O3 - I/O0 on LAD[3:0] first, then I/O7 - I/O4 on LAD[3:0] last). 13 TAR0 1111 IN then Float 14 TAR1 1111 (float) 15 SYNC 0000 OUT Sync: The device indicates that it has received the data or command. 16 TAR0 1111 OUT then Float Turn-Around Cycle 0: The device has driven the bus to all "1"s and then floats the bus. 17 TAR1 1111 (float) Float then Turn-Around Cycle 1: The Chipset resumes control of the bus during this cycle. IN Turn-Around Cycle 0: The Chipset has driven the bus to all "1"s and then float the bus. Float then Turn-Around Cycle 1: The device takes control of the bus during this cycle. OUT LPC MEMORY WRITE CYCLE WAVEFORMS CLK RST# or INIT# LF RAME # LAD[3:0] Start Memor y Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 1111b A[19:16] Data A[15:12] A[11:8] Load Address in 8 Clocks From Host to Device A[7:4] A[3:0] D[3:0] TAR D[7:4] Load Data in 2 Clocks 1111b Tri-State 2 Clocks SYNC 0000b Next Start TAR 1111b Tri-State 1 Clock 2 Clocks From Device to Host 0000b 1 Clock 17 IS49FL004T LPC MODE OPERATION (CONTINUED) LPC BYTE PROGRAM WAVEFORMS CLK RST# or INIT# LFRAME# 1st Start LAD[3:0] 0000b 1 Clock Memor y Write Cycle 011Xb Address 1111b 1111b 1 Clock 1111b 11xxb Data 0101b 0101b 0101b 0101b Load "5555h" in 8 Clocks 1010b TAR 1010b Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 2nd Start Memor y Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0010b 1010b 1010b 1010b Load "2AAAh" in 8 Clocks 0101b TAR 0101b Load "55h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# 3rd Start LAD[3:0] Memor y Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Data 0101b 0101b 0101b 0101b Load "5555h" in 8 Clocks 0000b TAR 1010b Load "A0h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TAR 1111b Tri-State 2 Clocks Device to Host CLK RST# or INIT# LFRAME# LAD[3:0] 4th Start Memor y Write Cycle 0000b 011Xb 1 Clock 1 Clock Address 1111b 1111b 1111b A[19:16] Data A[15:12] A[11:8] A[7:4] Load Address in 8 Clocks D[3:0] TAR D[7:4] Load Data in 2 Clocks Host to Device Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 A[3:1] 1111b Tri-State 2 Clocks Sync 0000b 1 Clock TAR 1111b Tri-State 2 Clocks Device to Host 18 IS49FL004T LPC SECTOR ERASE WAVEFORMS CLK RST # or INIT# LFRAME# 1st Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Dat a 0101b 0101b 0101b 0101b Load "5555h" in 8 Clocks TAR 1010b 1010 b Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TA R 1111b Tri-State 2 Clocks Device to Host CLK RST # or INIT# LFRAME# LAD[3:0 ] 2nd Start Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0010b 1010b 1010b 1 0 10 b L o a d "2AAAh" in 8 C locks 0101b TAR 0101b Load "55h" in 2 Clocks 1111b Tri-State 2 C locks Sync 0 00 0 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 3rd Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0101b 0101b 01 0 1 b 0101b L o a d "5555h" in 8 C locks 0000b 1 0 00 b Load "80h" in 2 Clocks TAR 1111b Tri-State 2 C locks Sync 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# LAD[3:0 ] 4th Start Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0101b 0101b 0 1 01 b 0101b Loa d "5555" in 8 Clocks 0101b 1010b Load "AAh" in 2 Clocks TAR 1111b Tri-State 2 C locks Sync 0 00 0 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 5th Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0010b 1010b 10 1 0 b 1010b L o a d "2AAAh" in 8 C locks 0101b 0 1 01 b TAR 1111b Tri-State Load "55h" in 2 Clocks 2 C locks Dat a TAR Sync 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 6th Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 Clock 1 Clock Internal Erase Start Address 1 1 11 b 1111b 1 1 11 b SA[19:16] SA[15:12 ] xxxxb Load Sector Address in 8 Clocks Host to Device xxxxb xxxxb 0000b 0011b Load "30h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000 b 1 Clock TA R 1111b Tri-State 2 C locks Device to Host SA = Sector Address Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 19 IS49FL004T LPC BLOCK ERASE WAVEFORMS CLK RST # or INIT# LFRAME# 1st Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 Clock 1 Clock Address 1111b 1111b 1111b 11xxb Dat a 0101b 0101b 0101b 0101b Load "5555h" in 8 Clocks TAR 1010b 1010 b Load "AAh" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0000b 1 Clock Host to Device TA R 1111b Tri-State 2 Clocks Device to Host CLK RST # or INIT# LFRAME# LAD[3:0 ] 2nd Start Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0010b 1010b 1010b 1 0 10 b L o a d "2AAAh" in 8 C locks 0101b TAR 0101b Load "55h" in 2 Clocks 1111b Tri-State 2 C locks Sync 0 00 0 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 3rd Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0101b 0101b 01 0 1 b 0101b L o a d "5555h" in 8 C locks 0000b 1 0 00 b Load "80h" in 2 Clocks TAR 1111b Tri-State 2 C locks Sync 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# LAD[3:0 ] 4th Start Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0101b 0101b 0 1 01 b 0101b Loa d "5555" in 8 Clocks 0101b 1010b Load "AAh" in 2 Clocks TAR 1111b Tri-State 2 C locks Sync 0 00 0 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 5th Start LAD[3:0 ] Memory Write Cycle 0000b 011X b 1 C lock 1 C lock Address 1 11 1 b 1111b 1 1 11 b 11xxb Dat a 0010b 1010b 10 1 0 b 1010b L o a d "2AAAh" in 8 C locks 0101b 0 1 01 b TAR 1111b Tri-State Load "55h" in 2 Clocks 2 C locks Dat a TAR Sync 0 0 00 b 1 C lock Host to Device TA R 1111b Tri-State 2 C locks Device to Host CLK RST # or INIT# LFRAME# 6th Start LAD[3:0 ] Memory Write Cycle 0 0 00 b 011X b 1 Clock 1 Clock Internal Erase Start Address 1111b 1111b 1 1 11 b BA[19:16] BA[15:14 ] + xxb xxxxb xxxxb Load Block Address in 8 Clocks Host to Device xxxxb 0000b 0101b Load "50h" in 2 Clocks 1111b Tri-State 2 Clocks Sync 0 00 0 b 1 Clock TA R 1111b Tri-State 2 Clocks Device to Host BA = Block Address Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 20 IS49FL004T LPC MODE OPERATION (CONTINUED) LPC GPI REGISTER READ WAVEFORMS CLK RST# or INIT# LF RAME # LAD[3:0] Start Memor y Read Cycle 0000b 010Xb 1 Clock Address 1111b 1111b 1 Clock Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 1011b 1100b TAR 0000b 0001b Load Address "FFBC0100h" in 8 Clocks From Host to Device 0000b 0000b 1111b Tri-State 2 Clocks SYN C 0000b 1 Clock Data D[3:0] D[7:4] Next Start TAR 1111b Tri-State Data Out 2 Clocks 2 Clocks From Device to Host 0000b 1 Clock 21 IS49FL004T REGISTERS The IS49FL004 have two registers include the Gen- eral Purpose Inputs Register (GPI_REG - available in FWH and LPC modes) and the Block Locking Register (BL_REG - available in FWH mode only). The GPI_REG can be read at FFBC0100h in the 4 Gbyte system memory map. And the BL_REG can be read through FFBx0002h where x = F - 0h. See Table 8 and 9 for the address of BL_REG. GENERAL PURPOSE INPUTS REGISTER BLOCK LOCKING REGISTERS The devices support block read-lock, write-lock, and lockdown features through a set of Block Locking Registers. Each memory block has an associated 8-bit read/writable block locking register. Only Bit 2 to Bit 0 are used in current version and Bit 7 to Bit 3 are reserved for future use. The default value of BL_REG is “01h” at power up. The definition of BL_REG is listed in Table 7. The FWH Register Configuration Map of IS49FL004 is shown in Table 9. Unused register will be read as 00h. The IS49FL004 contain an 8-bit General Purpose Inputs Register (GPI_REG) available in FWH and LPC modes. Only Bit 4 to Bit 0 are used in current version and Bit 7 to Bit 5 are reserved for future use. The GPI_REG is a pass-through register with the value set by GPI[4:0] pin during power-up. The GPI_REG is used for system design purpose only, the devices do not use this register. This register is read only and can be read at address location FFBC0100h in the 4 GByte system memory map through a memory read cycle. Refer to Table 6 for General Purpose Input Register Definition. Table 6. General Purpose Inputs Register Definition Bit Bit Name 7:5 Function 32-PLCC Pin# 32-VSOP Pin# Reserved - - 4 GPI4 GPI_REG Bit 4 30 6 3 GPI3 GPI_REG Bit 3 3 11 2 GPI2 GPI_REG Bit 2 4 12 1 GPI1 GPI_REG Bit 1 5 13 0 GPI0 GPI_REG Bit 0 6 14 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 22 IS49FL004T REGISTERS (CONTINUED) Table 7. Block Locking Register Definition Bit 7:3 Function Reserved 2 Read-Lock "1" = Prevents read operations in the block where set. "0" = Normal operation for reads in the block where clear. Default state. 1 Lock-Down "1" = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. LockDown only can be set, but not cleared. The block will remain locked-down until reset (with RST# or INIT#), or until the device is power-on reset. "0" = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. Default state. 0 Write-Lock "1" = Prevents program or erase operations in the block where set. Default state. "0" = Normal operation for programming and erase in the block where clear. Data Bit[7:3] Bit 2 Bit 1 Bit 0 00h 00000 0 0 0 Full access. 01h 00000 0 0 1 Write locked. Default state at power-up. 02h 00000 0 1 0 Locked open (full access locked down). 03h 00000 0 1 1 Write-locked down. 04h 00000 1 0 0 Read locked. 05h 00000 1 0 1 Read and write locked. 06h 00000 1 1 0 Read-locked down. 07h 00000 1 1 1 Read-locked and write-locked down. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 Resulting Block State 23 IS49FL004T REGISTERS (CONTINUED) Table 9. IS49FL004 Block Locking Register Address Register Block Size (Kbytes) Protected Block Address Range Memory Map Address T_BLOCK_LK 64 70000h - 7FFFFh FFBF0002h T_MINUS01_LK 64 60000h - 6FFFFh FFBE0002h T_MINUS02_LK 64 50000h - 5FFFFh FFBD0002h T_MINUS03_LK 64 40000h - 4FFFFh FFBC0002h T_MINUS04_LK 64 30000h - 3FFFFh FFBB0002h T_MINUS05_LK 64 20000h - 2FFFFh FFBA0002h T_MINUS06_LK 64 10000h - 1FFFFh FFB90002h T_MINUS07_LK 64 00000h - 0FFFFh FFB80002h Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 24 IS49FL004T A/A MUX MODE OPERATION are latched on the falling edge of R/C# pin. The column addresses (internal address A21 - A11) are latched on The IS49FL004 offers a Address/Address Multi- the rising edge of R/C# pin. The IS49FL004 uses A18 plexed (A/A Mux) mode for off-system operation, typi- - A0 internally to decode and access the 256 Kbytes cally on an EPROM Programmer, similar to a traditional memory space. Flash memory except the address input is multiplexed. In the A/A Mux mode, the programmer must drive the During a read operation, the OE# signal is used to conOE# pin to low (VIL) for read or WE# pins to low for write trol the output of data to the 8 I/O pins - I/O[7:0]. During operation. The devices have no Chip Enable (CE#) pin a write operation, the WE# signal is used to latch the for chip selection and activation as traditional Flash input data from I/O[7:0]. See Table 10 for Bus Operation memory. The R/C#, OE# and WE# pins are used to Modes. activate the device and control the power. The 11 multiplex address pins - A[10:0] and a R/C# pin are used to load the row and column addresses for the target memory location. The row addresses (internal address A10 - A0) A/A MUX MODE READ/WRITE OPERATION Table 10. A/A Mux Mode Bus Operation Modes Mode RST# OE# WE# Read VIH V IL VIH Write VIH V IH VIL X D IN Standby VIH V IH VIH X High Z Output Disable VIH V IH X X High Z Reset VIL X X X High Z Product Identification VIH VIL VIH Address X (1) A2 - A21 = X, A1 = VIL, A0 = VIL and A1 = VIH, A0 = VIH A2 - A21 = X, A1 = VIL, A0 = VIH I/O D OUT Manufacturer ID Device ID (2) (2) Notes: 1. X can be VIL or VIH. 2. Refer to Table 1 for the Manufacturer ID and Device ID of devices. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 25 IS49FL004T SYSTEM MEMORY MAP Table 11. System Memory Map Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 26 IS49FL004T MEMORY BLOCKS AND ADDRESSES (CONTINUED) Table 13. IS49FL004 Sector/Block Address Table Hardware Protection Block Block Size (Kbytes) Sector Sector Size (Kbytes) Address Range TBL# Block 7 (Boot Block) 64 " " 70000h - 7FFFFh Block 6 64 " " 60000h - 6FFFFh Block 5 64 " " 50000h - 5FFFFh Block 4 64 " " 40000h - 4FFFFh Block 3 64 " " 30000h - 3FFFFh Block 2 64 " " 20000h - 2FFFFh Block 1 64 " " 10000h - 1FFFFh Sector 15 4 0F000h - 0FFFFh : : : Sector 1 4 01000h - 01FFFh Sector 0 4 00000h - 00FFFh WP# Block 0 64 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 27 IS49FL004T COMMAND DEFINITION Table 14. Software Data Protection Command Definition Command Sequence Read Bus Cycle 1st Bus Cycle Addr(2) Data 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cylce Addr Data 6th Bus Cycle Addr Data 1 Addr D OUT 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h 5555h 10h Sector Erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h SA (3) 30h Block Erase 6 5555h AAh 2AAAh 55h 5555h 80h 5555h AAh 2AAAh 55h BA (4) 50h Byte Program 4 5555h AAh 2AAAh 55h 5555h A0h Addr DIN Product ID Entry 3 5555h AAh 2AAAh 55h 5555h 90h 2AAAh 55h 5555h F0h Chip Erase (1) Product ID Exit (5) 3 5555h AAh Product ID Exit (5) 1 XXXXh F0h Notes: 1. Chip erase is available in A/A Mux Mode only. 2. Address A[15:0] is used for SDP command decoding internally and A15 must be “0” in FWH/LPC and A/A Mux modes. AMS - A16 = Don’t care where AMS is the most-significant address of IS49FL00x. 3. SA = Sector address to be erased. 4. BA = Block address to be erased. 5. Either one of the Product ID Exit command can be used. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 28 IS49FL004T DEVICE OPERATIONS FLOWCHARTS AUTOMATIC PROGRAMMING Start Load Data AA h to Address 5555h Load Data 55h to Address 2AAA h Load Data A 0h to Address 5555h Address Increment Load Program Data to Progra m Address I/O7 = Data? or I/O6 Stop Toggle? No Y es Last Address? No Y es Program mi n g Completed Chart 1. Automatic Programming Flowchart Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 29 IS49FL004T DEVICE OPERATIONS FLOWCHARTS (CONTINUED) AUTOMATIC ERASE Start Write Chip, Sector, or Block Era s e C o m m a n d Data = FFh? or I/O6 Stop Toggle? No Y es Erasur e Complete d CHIP ERASE COMMAND SECTOR ERASE COMMAND Notes: 1. Please see Table 12 to Table 13 for Sector/Block Address Tables. 2. Only erase one sector or one block per erase operation. 3. When the TBL# pin is pulled low (VIL), the boot block will not be erased. BLOCK ERASE COMMAND Load Data AA h to Address 5555h Load Data AA h to Address 5555h Load Data AA h to Address 5555h Load Data 55h to Address 2AAA h Load Data 55h to Address 2AAA h Load Data 55h to Address 2AAA h Load Data 80h to Address 5555h Load Data 80h to Address 5555h Load Data 80h to Address 5555h Load Data AA h to Address 5555h Load Data AA h to Address 5555h Load Data AA h to Address 5555h Load Data 55h to Address 2AAA h Load Data 55h to Address 2AAA h Load Data 55h to Address 2AAA h Load Data 30h to (1,2,3) SA Load Data 50h to (1,2,3) BA Load Data 10h to Address 5555h (3) Chart 2. Automatic Erase Flowchart Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 30 IS49FL004T DEVICE OPERATIONS FLOWCHARTS (CONTINUED) SOFTWARE PRODUCT IDENTIFICATION ENTRY SOFTWARE PRODUCT IDENTIFICATION EXIT Load Data AA h to Address 5555h Load Data AA h to Address 5555h Load Data 55h to Address 2AAA h Load Data 55h to Address 2AAA h Load Data 90h to Address 5555h Load Data F0h to Address 5555h Enter Product Identification Mode (1,2) Exit Product Identification Mode (3) Load Data F0h to Address XXXX h or Exit Product Identification Mode (3) Notes: 1. After entering Product Identification Mode, the Manufacturer ID and the Device ID of IS49FL00x can be read. 2. Product Identification Exit command is required to end the Product Identification mode and return to standby mode. 3. Either Product Identification Exit command can be used, the device returns to standby mode. Chart 3. Software Product Identification Entry/Exit Flowchart Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 31 IS49FL004T ABSOLUTE MAXIMUM RATINGS (1) Temperature Under Bias -55oC to +125oC Storage Temperature -65oC to +150oC Standard Package 240oC 3 Seconds Lead-free Package 260oC 3 Seconds Surface Mount Lead Soldering Temperature Input Voltage with Respect to Ground on All Pins (2) -0.5 V to VCC + 0.5 V All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V VCC (2) -0.5 V to +6.0 V Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. DC AND AC OPERATING RANGE Part Number IS49FL004 Operating Temperature 0o C to 85oC Vcc Power Supply 3.0 V - 3.6 V Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 32 IS49FL004T DC CHARACTERISTICS Symbol Parameter Condition Min Typ Max Units 100 A II Input Leakage Current for IC, V = 0 V to V , V = V IN CC CC CC max ID[3:0] pins ILI Input Leakage Current VIN = 0 V to VCC, VCC = VCC max A ILO Output Leakage Current VI/O = 0 V to VCC , VCC = VCC max A Standby VCC Current FWH4 or LFRAME# = VIH, (FWH/LPC Mode) f = 33 MHz; VCC = VCC max ISB 500 A 10 mA 2 15 mA 7 20 mA FWH4 or LFRAME# = VIL, Ready Mode VCC Current IRY (FWH/LPC Mode) f = 33 MHz; IOUT = 0 mA, VCC = VCC max FWH4 or LFRAME# = VIL, VCC Active Read Current ICC1 ICC2 (FWH/LPC Mode) (1) f = 33 MHz; IOUT = 0 mA, VCC = VCC max VCC Program/Erase Current VIL Input Low Voltage -0.5 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage IOL = 2.0 mA, VCC = VCC min 0.1 VCC V VOH Output High Voltage IOH = -100 mA, VCC = VCC min V 0.9 VCC Note: 1. Characterized but not 100% tested. AC CHARACTERISTICS PIN IMPEDANCE (VCC = 3.3 V, f = 1 MHz, T = 25°C ) Typ Max Units Conditions C I/O (1) I/O Pin Capacitance 12 pF VI/O = 0 V C IN (1) Input Capacitance 12 pF VIN = 0 V LPIN (2) Pin Inductance 20 nH Notes: 1. These parameters are characterized but not 100% tested. 2. Refer to PCI specification. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 33 IS49FL004T AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE AC INPUT/OUTPUT CHARACTERISTICS Symbol Parameter Condition 0 < VOUT < 0.3 VCC IOH (AC) Switching current high 0.3 VCC < VOUT < 0.9 VCC Min Max -12 VCC mA -17.1 (VCC - VOUT) mA Equation C (1) 0.7 VCC < VOUT < VCC (Test point) VOUT = 0.7 VCC VCC > VOUT > 0.6 VCC IOL (AC) Switching current low 0.6 VCC > VOUT > 0.1 VCC Units mA -32 VCC 16 VCC mA -17.1 (VCC - VOUT) mA Equation D (1) 0.18 VCC > VOUT > 0 (Test point) VOUT = 0.18 VCC mA ICL Low clamp current -3 < VIN < -1 ICH High clamp current VCC + 4 > VIN > VCC + 1 slewr (2) Output rise slew rate 0.2 VCC - 0.6 VCC load 1 4 V/ns slewf (2) Output fall slew rate 0.6 VCC - 0.2 VCC load 1 4 V/ns 38 VCC -25 + (VIN + 1) / 0.015 mA 25 + (VIN - VCC - 1) / 0.015 mA Notes: 1. See PCI specification. 2. PCI specification output load is used. FWH/LPC INTERFACE CLOCK CHARACTERISTICS Symbol Parameter Min Max Units tCYC Clock Cycle Time 30 ns tHIGH Clock High Time 11 ns tLOW Clock Low Time 11 ns Clock Slew Rate 1 INIT# or RST# Slew Rate Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 50 4 V/ns mV/ns 34 IS49FL004T AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE CLOCK WAVEFORM tC Y C tH I G H tL O W 0.5 V C C 0.6 V C C 0.4 V C C (minimum ) 0.3 V C C 0.2 V C C FWH/LPC INTERFACE MEASUREMENT CONDITION PARAMETERS Symbol Value Units V TH1 0.6 V CC V V TL1 0.2 V CC V V TEST 0.4 V CC V V MAX1 0.4 V CC V Input Signal Edge Rate 1 V/ns Note: 1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive that this. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameter. FWH/LPC MEMORY READ/WRITE OPERATIONS CHARACTERISTICS Symbol Parameter Min TCYC Clock Cycle Time 30 ns TSU Input Set Up Time 7 ns TH Input Hold Time 0 ns TVAL Clock to Data Out 2 TON Clock to Active Time (float to active delay) 2 TOFF Clock to Inactive Time (active to float delay) Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 Max 11 Units ns ns 28 ns 35 IS49FL004T AC CHARACTERISTICS (CONTINUED) FWH/LPC INPUT TIMING PARAMETERS V TH CLK V TEST tS U FWH[3:0 ] or LAD[3:0 ] tH V TL V MAX INPUT VALID (Valid Input Data) FWH/LPC OUTPUT TIMING PARAMETERS V TH CLK V TEST V TL tV A L FWH[3:0] or LAD[3:0] (Valid Outpu t Data) tO F F FWH[3:0] or LAD[3:0] (Floa t Outpu t Data) tO N Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 36 IS49FL004T AC CHARACTERISTICS (CONTINUED) FWH/LPC RESET OPERATION CHARACTERISTICS Symbol Parameter Min Max Units 1 ms Reset Active Time to Clock Stable 100 s TRSTP Reset Pulse Width 100 ns TRSTF Reset Active to Output Float Delay TRST (1) Reset Inactive Time to Input Active TPRST Reset Active Time to VCC Stable TKRST 50 1 ns s Note: 1. There will be a 10 µs reset latency if a reset procedure is performed during a programming or erase operation. FWH/LPC RESET AC WAVEFORMS TPRST VCC CLK TKRST TRSTP RST#/INIT # TRST T RSTF FWH[3:0 ] or LAD[3:0] FWH4 or LFRAME# A/A MUX MODE INPUT TEST MEASUREMENT CONDITION PARAMETERS 3.0 V Input 1.5 V AC Mea sure me n t Level 0.0 V A/A MUX MODE TEST LOAD CONDITION TO TESTER TO DUT CL 30 pF Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 37 IS49FL004T AC CHARACTERISTICS (CONTINUED) A/A MUX MODE READ OPERATIONS CHARACTERISTICS Symbol Parameter Min Max 270 Units ns t RC Read Cycle Time t ACC Address to Output Delay t RST RST# High to Row Address Set-up Time 1 ms t AS R/C# Address Set-up Time 45 ns t AH R/C# Address Hold Time 45 ns t OE OE# to Output Delay t DF OE# to Output High Z 0 t OH Output Hold from OE# or Address, whichever occured first 0 ns t VCS VCC Set-up Time 50 s 120 ns 50 ns 30 ns A/A MUX MODE READ OPERATIONS AC WAVEFORMS RST# tR C tR S T ADDRESS ROW ADDRESS tA S tA H COLUMN ADDRESS tA S tA H R/ C# tA C C OE# tO E tD F WE# tO H HIGH Z OUTPUT OUTPUT VA LI D tV C S V CC Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 38 IS49FL004T AC CHARACTERISTICS (CONTINUED) A/A MUX MODE WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS Symbol Parameter Min Max Units t RST RST# High to Row Address Set-up Time 1 ms t AS R/C# Address Set-up Time 50 ns t AH R/C# Address Hold Time 50 ns t CWH R/C# to WE# High Time 50 ns t OES OE# High Set-up Time 20 ns t OEH OE# High Hold Time 20 ns t DS Data Set-up Time 50 ns t DH Data Hold Time 5 ns t WP Write Pulse Width 100 ns t WPH Write Pulse Width High 100 ns t BP Byte Programming Time 40 s t EC Chip, Sector or Block Erase Cycle Time 80 ms t VCS VCC Set-up Time 50 s A/A MUX MODE WRITE OPERATIONS AC WAVEFORMS RST# tR C tR S T ADDRESS ROW ADDRESS tA S tA H COLUMN ADDRESS tA S tA H R/ C# tC W H tV C S tO E H OE# tO E S WE# OUTPUT HIGH Z tD S tD H INPUT DATA V CC Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 39 IS49FL004T AC CHARACTERISTICS (CONTINUED) A/A MUX MODE BYTE PROGRAM OPERATIONS AC WAVEFORMS 4-Byte Progra m Command ADDRESS 5555 2AAA tC W H tW P 5555 BYTE ADDRESS R/ C # tW P H tB P WE# OE# tD H tD S DATA AA 55 INPUT DATA A0 VA LI D DATA A/A MUX MODE CHIP ERASE OPERATIONS AC WAVEFORMS 6-Byte Chip Eras e Command ADDRESS 2AAA 5555 5555 2AAA 5555 5555 R/ C # tC W H tW P tW P H tD S tD H tE C WE# OE# DATA IN AA 55 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 80 AA 55 10 40 IS49FL004T AC CHARACTERISTICS (CONTINUED) A/A MUX MODE SECTOR/BLOCK ERASE OPERATIONS AC WAVEFORMS 6-Byte Block Eras e Command ADDRESS 2AAA 5555 5555 2AAA 5555 SECTOR OR BLOCK ADDRESS R/ C # tC W H tW P tW P H tD S tD H tE C WE# OE# DATA IN AA 80 55 AA 55 30/50 A/A MUX MODE TOGGLE BIT AC WAVEFORMS ADDRESS ROW COLUMN R/ C# WE# tO E H OE# tO E I/O6 D D Note: 1. Toggling OE# will operate Toggle Bit. 2. I/O6 may start and end from “1” or “0” in random. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 41 IS49FL004T AC CHARACTERISTICS (CONTINUED) A/A MUX MODE DATA# POLLING AC WAVEFORMS ADDRESS ROW COLUMN R/ C# WE# tO E H OE# tO E I/O7 D D# D# D# D Note: Toggling OE# will operate Data# Polling. PROGRAM/ERASE PERFORMANCE Parameter Unit Typ Max Sector/Block Erase Time ms 50 80 From writing erase command to erase completion Chip Erase Time ms 50 80 From writing erase command to erase completion s 25 40 Excludes the time of four-cycle program command execution Byte Programming Time Remarks Note: These parameters are characterized but not 100% tested. RELIABILITY CHARACTERISTICS (1) Parameter Endurance Data Retention ESD - Human Body Model ESD - Machine Model Latch-Up Min Typ Unit Test Method 100,000 (2) Cycles JEDEC Standard A117 20 Years JEDEC Standard A103 2,000 >4,000 Volts JEDEC Standard A114 200 >400 Volts JEDEC Standard A115 100 + ICC1 mA JEDEC Standard 78 Notes: 1. These parameters are characterized but not 100% tested. 2. Preliminary specification only and will be formalized after cycling qualification test. Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 42 IS49FL004T PACKAGE TYPE INFORMATION 32V 32-Pin Thin Small Outline Package (VSOP - 8 mm x 14 mm)( measure in millimeters) 1.05 0.95 Pin 1 I.D. 0.27 0.17 8.10 7.90 0.50 BSC 0.15 0.05 12.50 12.30 14.20 13.80 1.20 MAX 0.20 0 .1 0 0° 5° 0.25 0.70 0.50 32J 32-Pin Plastic Leaded Chip Carrier (measured in millimeters) 1 2 .5 7 1 2 .3 2 1 1 .5 1 1 1 .3 5 0 . 7 4X 3 0 ° 1 5 .1 1 1 4 .8 6 3.56 3.18 Pin 1 I.D. 2.41 1.93 1 4 .0 5 1 3 .8 9 SEATING PLANE 13.46 12.45 0.53 0.33 1.27 Typ. 0.81 0.66 TOP VIEW Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 SIDE VIEW 43 IS49FL004T PRODUCT ORDERING INFORMATION IS49FL00x T -33 J C E Environmental Attribute E = Lead-free Package Temperature Range C = 0°C to +85°C Package Type J = 32-pin Plastic J-Leaded Chip Carrier (32J) V = 32-pin (8 mm x 14 mm) VSOP (32V) Speed Option Boot Block Location T = Top Boot Block Device Number IS49FL004 (4 Mbit) Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 44 IS49FL004T ORDERING INFORMATION: Density 4M Frequency (MHz) Order Part Number Package IS49FL004T-33JCE 32-pin PLCC IS49FL004T-33VCE 32-pin (8 mm x 14 mm) VSOP 33 Integrated Silicon Solution, Inc.- www.issi.com Rev. A1 9/19/2013 45