BOARDCOM DEMO-VMMK-2X03 0.9-11 ghz e-phemt wideband amplifier in wafer level package Datasheet

VMMK-2203
0.9-11 GHz E-pHEMT Wideband Amplifier in Wafer Level Package
Data Sheet
Description
Features
Avago Technologies has combined its industry leading
E-pHEMT technology with a revolutionary wafer level
package (WLP).
• 1 x 0.5 mm Surface Mount Package
The VMMK-2203 is an easy-to-use GaAs MMIC amplifier
that offers excellent gain and noise figure from 0.9 to 11
GHz. The input and output are matched to 50 Ω so no
external matching is needed. Bias is supplied through a
simple external choke and DC blocking network.
The wafer level package is small and ultra thin, yet can be
handled and placed with standard 0402 pick and place
assembly. This product is easy to use since it requires only
a single positive DC voltage for bias and no matching coefficients are required for impedance matching to 50 Ω
systems.
WLP 0402, 1mm x 0.5mm x 0.25 mm
• Ultrathin (0.25mm)
• Gain Block
• Ultra-wide Bandwidth
• 5V Supply
• RoHS6 + Halogen Free
Specifications (6GHz, 5V, 25mA Typ.)
• Noise Figure: 2.0dB typical
• Associated Gain: 16.5dB
• Output IP3: +14dBm
• Output P1dB: +5dBm
Applications
• Low Noise and Driver for Cellular/PCS and WCDMA
Base Stations
DY
• 2.4 GHz, 3.5GHz, 5-6GHz WLAN and WiMax notebook computer, access point and mobile wireless
applications
• 802.16 & 802.20 BWA systems
Pin Connections (Top View)
• WLL and MMDS Transceivers
• Point-to-Point Radio
Input
Input
Note:
“D” = Device Code
“Y” = Month Code
DY
Amp
Output
/ Vdd
Output
/ Vdd
• UWB
• Antennas
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 40V
ESD Human Body Model = 450V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Table 1. Absolute Maximum Ratings [1]
Sym
Parameters/Condition
Unit
Absolute Max
Vd
Supply Voltage (RF Output) [2]
V
8
Id
Device Current [2]
mA
50
Pin, max
CW RF Input Power (RF Input) [3]
dBm
+13
Pdiss
Total Power Dissipation
mW
400
Tch
Max channel temperature
°C
150
θjc
Thermal Resistance [4]
°C/W
107
Notes
1. Operation in excess of any of these conditions may result in permanent damage to this device.
2. Bias is assumed DC quiescent conditions
3. With the DC (typical bias) and RF applied to the device at board temperature Tb = 25°C
4. Thermal resistance is measured from junction to board using IR method
Table 2. DC and RF Specifications
TA= 25°C, Frequency = 6 GHz, Vd = 5V, Zin = Zout = 50Ω (unless otherwise specified)
Sym
Parameters/Condition
Unit
Minimum
Typ.
Maximum
Id
Device Current
mA
20.0
25
30.0
NF[1]
Noise Figure
dB
–
2
2.5
Ga [1]
Associated Gain
dB
15
16.5
18
OIP3 [2,3]
Output 3rd Order Intercept
dBm
+14
–
Output P-1dB[2]
Output Power at 1dB Gain
Compression (Pin = 0dBm)
dBm
+5
–
IRL [2]
Input Return Loss
dB
–
-11
–
ORL [2]
Output Return Loss
dB
–
-16
–
Notes:
1. Measure Data obtained using 300um G-S probe on production wafer
2. Measure Data obtained using 300um G-S-G probe on PCB substrate
3. OIP3 test condition: F1 = 6.0GHz, F2 = 6.01GHz, Pin = -20dB
2
Product Consistency Distribution Charts at 6.0 GHz, Vd = 5 V
LSL
USL
.02
.022
.024
.026
.028
.03
Id @ 5V, Mean=25mA, LSL=20mA, USL=30mA
LSL
USL
15
16
17
18
Gain @ 6GHz, Mean=16.5, LSL=15dB, USL=18dB
USL
1.7
1.8
1.9
2
2.1
NF @ 6GHz, Mean=2dB, USL=2.5dB
3
2.2
2.3
2.4
2.5
Note: Distribution data based on 500 part sample size from 3 lots during
initial characterization.
Measurements were obtained using 300um G-S production wafer probe.
Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits.
VMMK-2203 Typical Performance
(TA = 25°C, Vdd = 5V, Idd = 25mA, Zin = Zout = 50 Ω unless noted)
20
3
18
2
NF (dB)
S21 (dB)
16
14
1
12
10
0
2
4
6
8
Frequency (GHz)
10
0
12
Figure 1. Small-signal Gain [1]
S22 (dB)
-15
10
12
6
8
Frequency (GHz)
10
12
6
8
Frequency (GHz)
10
12
-20
-30
-40
-20
0
2
4
6
8
Frequency (GHz)
10
-50
12
Figure 3. Input Return Loss [1]
0
2
4
Figure 4. Output Return Loss [1]
10
20
8
18
OIP3 (dBm)
6
4
2
16
14
12
0
2
Figure 5. Output P-1dB [1]
4
6
8
Frequency (GHz)
10
12
10
0
2
Figure 6. Output IP3 [1]
Notes:
1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package
2. Output IP3 data taken at Pin= -20dBm
4
6
8
Frequency (GHz)
-10
-10
P1dB (dBm)
4
0
-5
0
2
Figure 2. Noise Figure [1]
0
S11 (dB)
0
4
VMMK-2203 Typical Performance (continue)
(TA = 25°C, Vdd = 5V, Idd = 25mA, Zin = Zout = 50 Ω unless noted)
30
4
25
3
NF (dB)
Id (mA)
20
15
2
10
1
5
0
0
1
2
3
Vd (V)
4
5
0
6
Figure 7. Total Current [1]
16
S12 (dB)
S21 (dB)
4
14
10
12
5V
3V
-20
-30
-40
0
2
4
6
8
Frequency (GHz)
10
-50
12
Figure 9. Gain over Vd [1]
0
2
4
6
8
Frequency (GHz)
10
12
Figure 10. Isolation over Vd [1]
0
0
5V
3V
-10
S22 (dB)
-5
-10
-15
-20
-30
-40
0
2
4
6
8
Frequency (GHz)
Figure 11. Input Return Loss Over Vdd [1]
10
12
-50
5V
3V
0
2
4
6
8
Frequency (GHz)
Figure 12. Output Return Loss Over Vdd [1]
Notes:
1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package
5
6
8
Frequency (GHz)
-10
12
S11 (dB)
2
0
5V
3V
18
-20
0
Figure 8. Noise Figure over Vd [1]
20
10
5V
3V
10
12
VMMK-2203 Typical Performance (continue)
10
20
5
15
OIP3 (dBm)
P1dB (dBm)
(TA = 25°C, Zin = Zout = 50 Ω unless noted)
0
5
-5
-10
OP1dB_5V
OP1dB_3V
0
2
OIP3_5V
OIP3_3V
4
6
8
Frequency (GHz)
10
20
5
18
4
16
3
14
25C
85C
-40C
12
10
0
2
2
4
6
8
Frequency (GHz)
10
6
8
Frequency (GHz)
10
12
10
12
25 C
85 C
-40 C
2
0
12
0
2
4
6
8
Frequency (GHz)
Figure 16. Noise Figure over Temp [3]
15
25
25 C
85 C
-40 C
12
20
OIP3 (dBm)
9
6
15
10
25 C
85 C
-40 C
5
3
0
2
4
6
8
Frequency (GHz)
Figure 17. Output P1dB Over Temp [3]
10
12
0
0
2
4
6
8
Frequency (GHz)
Figure 18. Output IP3 Over Temp [2,3]
Notes:
1. Data taken on a G-S-G probe substrate fully de-embedded to the reference plane of the package
2. Output IP3 data taken at Pin=-15dBm
3. Over temp data taken on a test fixture (Figure 20) without de-embedding
6
4
1
Figure 15. Gain over Temp [3]
0
0
Figure 14. Output IP3 Over Vdd [1,2]
NF (dB)
S21 (dB)
0
12
Figure 13. Output P-1dB over Vdd [1]
P1dB (dBm)
10
10
12
Typical Scattering Parameters
(Data obtained using 300um G-S-G PCB substrate, losses calibrated out to the package reference plane)
TA = 25°C, VDD = 5V, Idq = 25mA, Zin = Zout = 50Ω
7
Freq
GHz
S11
S21
S12
S22
db
mag
Phase
db
mag
phase
db
mag
phase
db
mag
Phase
0.1
-0.623
0.931
-17.303
15.410
5.895
24.706
-43.098
0.007
58.201
-14.226
0.194
-60.924
0.2
-1.806
0.812
-30.763
16.296
6.528
11.177
-39.251
0.011
49.500
-18.666
0.117
-67.718
0.3
-3.217
0.691
-40.107
16.744
6.874
3.676
-37.202
0.014
38.074
-21.230
0.087
-71.757
0.4
-4.789
0.576
-42.585
16.937
7.028
0.281
-36.138
0.016
30.992
-25.224
0.055
-69.531
0.5
-6.014
0.500
-45.376
17.138
7.193
-4.222
-35.494
0.017
23.868
-27.013
0.045
-72.073
0.9
-9.520
0.334
-46.030
17.440
7.447
-19.422
-34.943
0.018
10.054
-32.841
0.023
-83.598
1
-10.053
0.314
-45.287
17.468
7.471
-22.849
-34.846
0.018
8.211
-34.657
0.019
-82.547
2
-11.859
0.255
-36.749
17.573
7.562
-54.672
-34.992
0.018
-7.465
-41.210
0.009
161.055
3
-11.242
0.274
-40.341
17.447
7.453
-85.386
-35.810
0.016
-16.631
-31.341
0.027
84.468
4
-10.554
0.297
-54.521
17.046
7.117
-115.626
-36.954
0.014
-23.677
-23.890
0.064
49.757
5
-10.446
0.300
-70.762
16.351
6.570
-144.946
-38.862
0.011
-26.344
-18.666
0.117
27.200
6
-10.989
0.282
-88.565
15.548
5.989
-172.420
-40.724
0.009
-25.092
-15.376
0.170
10.065
7
-11.965
0.252
-105.725
14.741
5.458
161.832
-42.158
0.008
-15.494
-13.046
0.223
-5.275
8
-13.267
0.217
-123.379
14.054
5.043
137.412
-43.098
0.007
-4.492
-11.179
0.276
-18.954
9
-14.919
0.180
-142.510
13.539
4.753
113.475
-42.853
0.007
8.295
-9.538
0.334
-31.497
10
-16.701
0.146
-166.823
13.159
4.550
89.158
-42.384
0.008
19.326
-8.011
0.398
-43.146
11
-17.972
0.126
163.087
12.879
4.405
63.721
-40.724
0.009
23.652
-6.616
0.467
-55.112
12
-17.781
0.129
128.897
12.543
4.238
36.160
-39.332
0.011
26.908
-5.338
0.541
-68.500
13
-16.496
0.150
97.602
11.875
3.924
6.410
-37.924
0.013
22.544
-4.465
0.598
-83.481
14
-14.943
0.179
72.431
10.617
3.395
-24.069
-37.788
0.013
14.404
-4.124
0.622
-98.826
15
-13.731
0.206
54.358
8.757
2.741
-53.104
-37.589
0.013
8.991
-4.278
0.611
-112.509
16
-12.597
0.235
40.489
6.512
2.116
-78.994
-37.856
0.013
6.710
-4.834
0.573
-123.438
17
-11.805
0.257
29.853
4.131
1.609
-101.974
-38.273
0.012
7.867
-5.430
0.535
-132.619
18
-10.906
0.285
20.369
1.789
1.229
-122.236
-38.416
0.012
4.077
-5.883
0.508
-139.697
19
-10.128
0.312
12.841
-0.460
0.948
-140.763
-38.862
0.011
3.017
-6.200
0.490
-145.124
20
-9.549
0.333
5.210
-2.569
0.744
-158.032
-39.412
0.011
-1.898
-6.375
0.480
-150.506
VMMK-2203 Application and Usage
(Please always refer to the latest Application Note AN5378 in website)
Biasing and Operation
The VMMK-2203 is biased with a positive supply connected
to the output pin through an external user supplied
bias-tee as shown in Figure 19. The recommended supply
voltage is between 3 and 5V. The corresponding drain
currents are approximately 15 and 25 mA. Biasing the
device at 5V results in higher gain, lower noise figure,
higher IP3 and P1dB. In a typical application, the bias-tee
can be constructed using lumped elements. The value of
the output inductor can have a major effect on both low
and high frequency operation. The demo board uses an
8.2 nH inductor that has self resonant frequency higher
than the maximum desired frequency of operation.
Vdd
0.1 uF
100 pF
Size: 1.1 mm x 0.6 mm (0402 component)
Input
8.2 nH
Output
Amp
100 pF
Input
Pad
Ground
Pad
50 Ohm line
Output
Pad
100 pF
50 Ohm line
Figure 19. Usage of the VMMK-2203
At frequencies higher than 6 GHz, it may be advantageous to use a quarter-wave long microstrip line to act as
a high impedance at the desired frequency of operation.
This technique proves a good solution but only over relatively narrow bandwidths. Another approach for using
the VMMK-2203 in broadband is to put in series two
different value inductors with the smaller value inductor
placed closest to the device and favoring the higher frequencies. The larger value inductor will then offer better
low frequency performance by not loading the output
of the device. The parallel combination of the 100pF and
0.1uF capacitors provides a low impedance in the band of
operation and at lower frequencies. They should be placed
as close as possible to the inductor. The low frequency
bypass provides good rejection of power supply noise
and also provides a low impedance termination for
third order low frequency mixing products that will be
generated when multiple in-band signals are injected into
any amplifier.
Refer the Absolute Maximum Ratings table for allowed DC
and thermal conditions.
8
Figure 20. Evaluation/Test Board (available to qualified customer request)
S Parameter Measurements
The S-parameters are measured on a .016 inch thick
RO4003 printed circuit test board, using G-S-G (ground
signal ground) probes. Coplanar waveguide is used to
provide a smooth transition from the probes to the device
under test. The presence of the ground plane on top of
the test board results in excellent grounding at the device
under test. A combination of SOLT (Short - Open - Load
- Thru) and TRL (Thru - Reflect - Line) calibration techniques are used to correct for the effects of the test board,
resulting in accurate device S-parameters. The reference
plane for the S Parameters is at the edge of the package.
The product consistency distribution charts shown on
page 2 represent data taken by the production wafer probe
station using a 300um G-S wafer probe. The ground-signal
probing that is used in production allows the device to be
probed directly at the device with minimal common lead
inductance to ground. Therefore there will be a slight difference in the nominal gain obtained at the test frequency
using the 300um G-S wafer probe versus the 300um G-S-G
printed circuit board substrate method.
fy the device
rial with one
tal. Soldering
sion than FR5
materials with
ge of the base
evice circuitry
GaAs package
to damaging
s RO4003 and
al and should
ng
source leads
leads of the
unt. The recern is shown
ned footprint
t borders the
en.
re any plated
ng and tests
hin .003”) and
ure 5 provides
VMMK-3XXX
kness RO4350
e also applies
t frequencies
-1XXX FETs at
ductance may
may be placed
bility. Consult
ation.
of the VMMK
that the VIAs
om under the
of the VIAs is
e VIAs should
Outline Drawing
1.004 MIN, 1.085 MAX
PIN ONE INDICATOR
0.125
0.125
GROUND PAD
0.500 MIN, 0.585 MAX
0.470
OUTPUT PAD
0.390
0.160
INPUT PAD
0.160
Notes:
Solderable area of the device shown in yellow.
Dimensions in mm.
Tolerance ± 0.015 mm
Suggested PCB Material and Land Pattern
Recommended SMT Attachment
The VMMK Packaged Devices are compatible with high
volume surface mount PCB assembly processes.
1.2 (0.048)
0.400 (0.016)
0.100 (0.004)
0.076 max
(0.003) 2pl see discussion
0.381 (0.015) 2pl
1. Follow ESD precautions while handling packages.
0.100 (0.004)
0.500 (0.020)
Part of
Input
Circuit
Manual Assembly for Prototypes
2. Handling should be along the edges with tweezers or
from topside if using a vacuum collet.
0.500 (0.020)
0.200
(0.008)
Part of
Output
Circuit
0.200
(0.008)
0.7 (0.028)
0.254 dia PTH
(0.010) 4pl
Solder Mask
0.400 dia
(0.016) 4pl
Notes:
Figure 5. Recommended PCB layout for VMMK devices
1. 0.010” Rogers RO4350
As a general rule, if a VIA is within .004” (100u) of the edge
of the soldermask but not under the device, then the VIA
should be filled. Any VIA which is covered by the solder
mask and is beyond .004” (100u) of the solder mask edge
can be uncapped and unfilled as it is not at risk of wicking
away solder from the device.
If for any reason it is required to include a VIA or VIAs
under a VMMK device, then the VIAs should be filled and
capped. A capped VIA is a “plated over” filled VIA. If a filled
but uncapped VIA is placed under the device, there will
not be enough solderable surface area for device attachment. If an unfilled and uncapped VIA is placed directly
under the ground pad, then the liquid solder will flow
into the open VIA hole during the reflow process and
deplete the solder volume to varying degrees from
9under the ground pad. Depletion of the solder volume
due to unfilled VIAs may lead to a weak solder joint, poor
grounding of the device, and/or stresses compromising
3. Recommended attachment is solder paste. Please
see recommended solder reflow profile. Conductive
epoxy is not recommended. Hand soldering is not
recommended.
4. Apply solder paste using either a stencil printer or
dot placement. The volume of solder paste will be
dependent on PCB and component layout and should
be controlled to ensure consistent mechanical and
electrical performance. Excessive solder will degrade RF
performance.
5. Follow solder paste and vendor’s recommendations
when developing a solder reflow profile. A standard
profile will have a steady ramp up from room
temperature to the pre-heat temp to avoid damage
due to thermal shock.
6. Packages have been qualified to withstand a peak
temperature of 260°C for 20 to 40 sec. Verify that the
profile will not expose device beyond these limits.
7. Clean off flux per vendor’s recommendations.
8. Clean the module with Acetone. Rinse with alcohol.
Allow the module to dry before testing.
Ordering Information
Part Number
Devices Per
Container
Container
VMMK-2203-BLKG
100
Antistatic Bag
VMMK-2203-TR1G
5000
7” Reel
Package Dimension Outline
D
Die dimension:
E
A
Dim
Range
Unit
D
1.004 - 1.085
mm
E
0.500 - 0.585
mm
A
0.225 - 0.275
mm
Note:
All dimensions are in mm
Reel Orientation
Device Orientation
USER FEED DIRECTION
REEL
4 mm
TOP VIEW
Note:
“D” = Device Code
”Y” = Month Code
•DY
•DY
10
CARRIER
TAPE
•DY
•DY
USER
FEED
DIRECTION
8 mm
END VIEW
Tape Dimensions
T
Do
Note: 1
Po
B
A
A
P1
Scale 5:1
Bo
W
Note: 2
F
E
5° (Max)
B
D1
BB SECTION
Note: 2
P2
Ao
R0.1
5° (Max)
Ko
Ao = 0.73±0.05 mm
Scale 5:1
Bo = 1.26±0.05 mm
AA SECTION
mm
Ko = 0.35 +0.05
+0
Unit: mm
Symbol
Spec.
K1
Po
P1
P2
Do
D1
E
F
10Po
W
T
–
4.0±0.10
4.0±0.10
2.0±0.05
1.55±0.05
0.5±0.05
1.75±0.10
3.50±0.05
40.0±0.10
8.0±0.20
0.20±0.02
Notice:
1. 10 Sprocket hole pitch cumulative tolerance is ±0.1mm.
2. Pocket position relative to sprocket hole measured as true position
of pocket not pocket hole.
3. Ao & Bo measured on a place 0.3mm above the bottom of the
pocket to top surface of the carrier.
4. Ko measured from a plane on the inside bottom of the pocket to
the top surface of the carrier.
5. Carrier camber shall be not than 1m per 100mm through a length
of 250mm.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-2001EN - December 16, 2014