1 A, Low Dropout,
CMOS Linear Regulator
ADP1706/ADP1707/ADP1708
TYPICAL APPLICATION CIRCUITS
ADP1706
VIN = 5V
1
EN
2
GND
3
IN
OUT 6
4
IN
OUT 5
SENSE 7
VOUT = 3.3V
4.7µF
4.7µF
Figure 1. ADP1706 with Fixed Output Voltage, 3.3 V
ADP1707
VIN = 5V
1
EN
2
GND
3
IN
OUT 6
4
IN
OUT 5
VTRK
TRK 8
SENSE 7
VOUT
4.7µF
4.7µF
VOUT (V)
3
2
1
0
APPLICATIONS
1 2 3 4 5
VTRK (V)
Figure 2. ADP1707 with Output Voltage Tracking
ADP1708
VIN = 5V
4.7µF
ADJ
R2
1
EN
2
GND
3
IN
OUT 6
4
IN
OUT 5
8
SENSE 7
R1
VOUT = 0.8V(1 + R1/R2)
4.7µF
06640-002
Notebook computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
10nF
SS 8
06640-003
Maximum output current: 1 A
Input voltage range: 2.5 V to 5.5 V
Low shutdown current: <1 μA
Low dropout voltage: 345 mV @ 1 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2.5%
16 fixed output voltage options with soft start:
0.75 V to 3.3 V (ADP1706)
16 fixed output voltage options with tracking
0.75 V to 3.3 V (ADP1707)
Adjustable output voltage option:
0.8 V to 5.0 V (ADP1708)
Stable with small 4.7 μF ceramic output capacitor
Excellent load/line transient response
Current limit and thermal overload protection
Logic-controlled enable
Available in an 8-lead, exposed paddle SOIC and
3 mm × 3 mm, 8-lead exposed paddle LFCSP
06640-001
FEATURES
Figure 3. ADP1708 with Adjustable Output Voltage, 0.8 V to 5.0 V
GENERAL DESCRIPTION
The ADP1706/ADP1707/ADP1708 are CMOS, low dropout
linear regulators that operate from 2.5 V to 5.5 V and provide
up to 1 A of output current. Using an advanced proprietary
architecture, they provide high power supply rejection and
achieve excellent line and load transient response with a small
4.7 μF ceramic output capacitor.
The ADP1706/ADP1707 are available in 16 fixed output voltage options. The ADP1708 is available in an adjustable version,
which allows output voltages that range from 0.8 V to 5.0 V via
an external divider. The ADP1706 allows an external soft start
capacitor to be connected to program the start-up time; the
ADP1707 and ADP1708 contain internal soft start capacitors
that give a typical start-up time of 100 μs. The ADP1707
includes a tracking feature that allows the output to follow an
external voltage rail or reference.
The ADP1706/ADP1707/ADP1708 are available in an 8-lead,
exposed paddle SOIC package and an 8-lead, 3 mm × 3 mm
exposed paddle LFCSP, making them not only very compact
solutions but also providing excellent thermal performance for
applications requiring up to 1 A of output current in a small,
low profile footprint.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADP1706/ADP1707/ADP1708
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start Function (ADP1706) ................................................ 10
Applications....................................................................................... 1
Adjustable Output Voltage (ADP1708)................................... 11
Typical Application Circuits............................................................ 1
Track Mode (ADP1707) ............................................................ 11
General Description ......................................................................... 1
Enable Feature ............................................................................ 11
Revision History ............................................................................... 2
Application Information................................................................ 12
Specifications..................................................................................... 3
Capacitor Selection .................................................................... 12
Absolute Maximum Ratings............................................................ 5
Voltage Tracking Applications.................................................. 12
Thermal Resistance ...................................................................... 5
Current Limit and Thermal Overload Protection ................. 12
ESD Caution.................................................................................. 5
Thermal Considerations............................................................ 13
Pin Configurations and Function Descriptions ........................... 6
PCB Layout Considerations...................................................... 15
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 16
Theory of Operation ...................................................................... 10
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP1706/ADP1707/ADP1708
SPECIFICATIONS
VIN = (VOUT + 0.6 V) or 2.5 V (whichever is greater), IOUT = 10 mA, CIN = COUT = 4.7 μF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
(ADP1706 and ADP1707)
Adjustable Output Voltage Accuracy
(ADP1708) 1
Symbol
VIN
IGND
IGND-SD
VOUT
VOUT
LINE REGULATION
∆VOUT/∆VIN
LOAD REGULATION 2
DROPOUT VOLTAGE 3
∆VOUT/∆IOUT
VDROPOUT
Test Conditions
TJ = –40°C to +125°C
IOUT = 0 mA
IOUT = 100 mA
IOUT = 100 mA, TJ = −40°C to +125°C
IOUT = 1 A
IOUT = 1 A, TJ = −40°C to +125°C
EN = GND
EN = GND, TJ = −40°C to +125°C
Min
2.5
IOUT = 10 mA
IOUT = 100 μA to 1 A
100 μA < IOUT < 1 A, TJ = −40°C to +125°C
IOUT = 10 mA
IOUT = 100 μA to 1 A
100 μA < IOUT < 1 A, TJ = −40°C to +125°C
VIN = (VOUT + 0.6 V) to 5.5 V,
TJ = −40°C to +125°C
IOUT = 10 mA to 1 A, TJ = −40°C to +125°C
IOUT = 100 mA, VOUT ≥ 3.3 V
IOUT = 100 mA, VOUT ≥ 3.3 V,
TJ = −40°C to +125°C
IOUT = 1 A, VOUT ≥ 3.3 V
IOUT = 1 A, VOUT ≥ 3.3 V, TJ = −40°C to +125°C
IOUT = 100 mA, 2.5 V ≤ VOUT < 3.3 V
IOUT = 100 mA, 2.5 V ≤ VOUT < 3.3 V,
TJ = −40°C to +125°C
IOUT = 1 A, 2.5 V ≤ VOUT < 3.3 V
IOUT = 1 A, 2.5 V ≤ VOUT < 3.3 V,
TJ = −40°C to +125°C
−1
−1.5
−2.5
0.792
0.788
0.780
−0.1
Max
5.5
1.0
Unit
V
μA
μA
μA
mA
mA
μA
μA
+1
+1.5
+2.5
0.808
0.812
0.820
+0.1
%
%
%
V
V
V
%/ V
0.001
%/mA
mV
mV
50
310
390
1.2
1.55
0.1
0.8
33
55
345
60
mV
mV
mV
mV
630
mV
mV
1.8
μs
ms
A
1.6
+40
°C
°C
μA
mV
+60
mV
0.4
1
100
V
V
μA
nA
μA
600
35
365
START-UP TIME 4
ADP1707 and ADP1708
ADP1706
CURRENT LIMIT THRESHOLD 5
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
TSSD
TSSD-HYS
TJ rising
SOFT START SOURCE CURRENT (ADP1706)
VOUT to VTRK ACCURACY (ADP1707)
SSI-SOURCE
VTRK-ERROR
SS = GND
0 V ≤ VTRK ≤ (0.5 × VOUT (NOM)), VOUT (NOM) ≤ 1.8 V,
TJ = −40°C to +125°C
0 V ≤ VTRK ≤ (0.5 × VOUT (NOM)), VOUT (NOM) > 1.8 V,
TJ = −40°C to +125°C
0.6
−40
2.5 V ≤ VIN ≤ 5.5 V
2.5 V ≤ VIN ≤ 5.5 V
EN = IN or GND
1.8
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Leakage Current
ADJ INPUT BIAS CURRENT (ADP1708)
SENSE INPUT BIAS CURRENT
Typ
tSTART-UP
CSS = 10 nF
ILIMIT
VIH
VIL
VI-LEAKAGE
ADJI-BIAS
SNSI-BIAS
1.1
Rev. 0 | Page 3 of 20
100
7.3
1.5
150
15
1.1
−60
0.1
30
4
ADP1706/ADP1707/ADP1708
Parameter
OUTPUT NOISE
Symbol
OUTNOISE
POWER SUPPLY REJECTION RATIO
PSRR
Test Conditions
10 Hz to 100 kHz, VOUT = 0.75 V
10 Hz to 100 kHz, VOUT = 3.3 V
1 kHz, VOUT = 0.75 V
1 kHz, VOUT = 3.3 V
1
Min
Typ
125
450
70
56
Max
Unit
μV rms
μV rms
dB
dB
Accuracy when OUT is connected directly to ADJ. When OUT voltage is set by external feedback resistors, absolute accuracy in adjust mode depends on the tolerances
of resistors used.
Based on an end-point calculation using 10 mA and 1 A loads. See Figure 11 for typical load regulation performance for loads less than 10 mA.
3
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.5 V.
4
Start-up time is defined as the time between the rising edge of EN to OUT being at 95% of its nominal value.
5
Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
2
Rev. 0 | Page 4 of 20
ADP1706/ADP1707/ADP1708
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
IN to GND
OUT to GND
EN to GND
SS/ADJ/TRK to GND
SENSE to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
–0.3 V to IN
–0.3 V to +6 V
–0.3 V to +6 V
–0.3 V to +6 V
–65°C to +150°C
–40°C to +125°C
JEDEC J-STD-020
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
8-Lead SOIC (Exposed Paddle)
8-Lead 3 mm × 3 mm LFCSP (Exposed Paddle)
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 20
θJA
58
66
Unit
°C/W
°C/W
ADP1706/ADP1707/ADP1708
SS
7
SENSE
6
OUT
5
OUT
IN 3
IN 4
ADP1707
TOP VIEW
(Not to Scale)
8
TRK
7
SENSE
6
OUT
5
OUT
IN 3
IN 4
ADP1708
TOP VIEW
(Not to Scale)
8
ADJ
7
SENSE
6
OUT
5
OUT
TOP VIEW
(Not to Scale)
EN 1
PIN 1
INDICATOR
GND 2
ADP1707
IN 3
IN 4
8 SS
7 SENSE
6 OUT
5 OUT
TOP VIEW
(Not to Scale)
8 TRK
7 SENSE
6 OUT
5 OUT
Figure 7. 8-Lead LFCSP, ADP1707
06640-005
EN 1
ADP1706
Figure 5. 8-Lead LFCSP, ADP1706
Figure 6. 8-Lead SOIC, ADP1707
GND 2
GND 2
IN 4
06640-006
EN 1
PIN 1
INDICATOR
IN 3
Figure 4. 8-Lead SOIC, ADP1706
GND 2
EN 1
06640-007
IN 4
TOP VIEW
(Not to Scale)
8
06640-009
IN 3
ADP1706
EN 1
PIN 1
INDICATOR
GND 2
ADP1708
IN 3
IN 4
Figure 8. 8-Lead SOIC, ADP1708
TOP VIEW
(Not to Scale)
8 ADJ
7 SENSE
6 OUT
5 OUT
06640-008
EN 1
GND 2
06640-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 9. 8-Lead LFCSP, ADP1708
Table 4. Pin Function Descriptions
ADP1706
Pin No.
1
ADP1707
Pin No.
1
ADP1708
Pin No.
1
Mnemonic
EN
2
3, 4
5, 6
7
2
3, 4
5, 6
7
2
3, 4
5, 6
7
GND
IN
OUT
SENSE
8
N/A
N/A
8
N/A
N/A
SS
TRK
N/A
EP
N/A
EP
8
EP
ADJ
EP
Description
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the
regulator. For automatic startup, connect EN to IN.
Ground.
Regulator Input Supply. Bypass IN to GND with a 4.7 μF or greater capacitor.
Regulated Output Voltage. Bypass OUT to GND with a 4.7 μF or greater capacitor.
Sense. Measures the actual output voltage at the load and feeds it to the error
amplifier. Connect SENSE as close as possible to the load to minimize the effect
of IR drop between the regulator output and the load.
Soft Start. A capacitor connected to this pin determines the soft start time.
Track. The output follows the voltage applied at the TRK pin. See the Theory of
Operation section for a more detailed description.
Adjust. A resistor divider from OUT to ADJ sets the output voltage.
The exposed pad on the bottom of the SOIC package and the LFCSP package. EP
enhances thermal performance and is electrically connected to GND inside the
package. User is recommended to connect EP to the ground plane on the board.
Rev. 0 | Page 6 of 20
ADP1706/ADP1707/ADP1708
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.8 V, IOUT = 100 mA, CIN = 4.7 μF, COUT = 4.7 μF, TA = 25°C, unless otherwise noted.
1400
3.32
ILOAD = 100µA
3.31
ILOAD = 1A
ILOAD = 10mA
1200
3.30
1000
ILOAD = 100mA
3.28
ILOAD = 300mA
ILOAD = 500mA
800
600
ILOAD = 300mA
3.27
ILOAD = 500mA
400
ILOAD = 1A
3.26
06640-010
3.25
3.24
–40
10
60
ILOAD = 100mA
ILOAD = 10mA
200
0
–40
110
ILOAD = 100µA
10
06640-013
IGND (µA)
VOUT (V)
3.29
60
TJ (°C)
110
TJ (°C)
Figure 10. Output Voltage vs. Junction Temperature
Figure 13. Ground Current vs. Junction Temperature
1400
3.315
3.310
1200
3.305
1000
IGND (µA)
VOUT (V)
3.300
3.295
3.290
800
600
3.285
400
3.280
1
10
100
06640-014
3.270
0.1
200
06640-011
3.275
0
0.1
1000
1
10
ILOAD (mA)
Figure 11. Output Voltage vs. Load Current
2100
ILOAD = 100µA
1800
ILOAD = 10mA
ILOAD = 100mA
ILOAD = 1A
ILOAD = 500mA
ILOAD = 300mA
1500
ILOAD = 100mA
IGND (µA)
ILOAD = 300mA
ILOAD = 500mA
3.28
1200
ILOAD = 10mA
ILOAD = 100µA
900
600
3.26
300
3.25
3.8
4.2
4.6
5.0
0
3.6
5.4
06640-015
ILOAD = 1A
3.27
06640-012
VOUT (V)
3.30
3.29
1000
Figure 14. Ground Current vs. Load Current
3.32
3.31
100
ILOAD (mA)
4.0
4.4
4.8
5.2
VIN (V)
VIN (V)
Figure 12. Output Voltage vs. Input Voltage
Figure 15. Ground Current vs. Input Voltage
Rev. 0 | Page 7 of 20
ADP1706/ADP1707/ADP1708
400
350
LOAD SWITCHED FROM 50mA TO 950mA
AND BACK TO 50mA
250
50mV/DIV
VDROPOUT (mV)
300
200
150
VOUT
VIN = 3.8V
VOUT = 1.6V
CIN = 4.7µF
COUT = 4.7µF
06640-017
50
0
10
1000
100
06640-020
100
TIME (20µs/DIV)
ILOAD (mA)
Figure 19. Load Transient Response, CIN = 4.7 μF, COUT = 4.7 μF
Figure 16. Dropout Voltage vs. Load Current
3.4
3.3
LOAD SWITCHED FROM 50mA TO 950mA
AND BACK TO 50mA
3.2
2.9
2.8
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
2.7
2.6
2.5
3.0
3.2
3.4
3.6
= 10mA
= 100mA
= 300mA
= 500mA
= 750mA
= 1A
3.8
VOUT
VIN = 3.8V
VOUT = 1.6V
CIN = 22μF
COUT = 22μF
4.0
06640-021
50mV/DIV
3.0
06640-018
VOUT (V)
3.1
TIME (20μs/DIV)
VIN (V)
Figure 17. Output Voltage vs. Input Voltage (in Dropout)
2500
2V/DIV
ILOAD = 1A
ILOAD = 750mA
ILOAD = 500mA
ILOAD = 300mA
ILOAD = 100mA
ILOAD = 10mA
2000
VIN STEP FROM 4V TO 5V
1000
VOUT
500
0
3.0
VOUT = 3.3V
CIN = 4.7μF
COUT = 4.7μF
ILOAD = 1A
3.2
3.4
3.6
3.8
4.0
TIME (100μs/DIV)
VIN (V)
Figure 18. Ground Current vs. Input Voltage (in Dropout)
Figure 21. Line Transient Response
Rev. 0 | Page 8 of 20
06640-022
20mV/DIV
1500
06640-019
IGND (µA)
Figure 20. Load Transient Response, CIN = 22 μF, COUT = 22 μF
ADP1706/ADP1707/ADP1708
–40
18
VRIPPLE = 50mV
ILOAD = 10mA
COUT = 4.7μF
FREQUENCY = 10kHz
16
VOUT = 2.4V
–45
12
PSRR (dB)
RAMP-UP TIME (ms)
14
10
8
6
VOUT = 1.6V
–50
4
0
5
10
15
20
–55
2.7
25
3.2
3.7
Figure 22. Output Voltage Ramp-Up Time vs. Soft Start Capacitor Value
–10
–20
VRIPPLE = 50mV
VIN = 5V
VOUT = 3.3V
COUT = 4.7μF
–35
–40
PSRR (dB)
PSRR (dB)
Figure 25. ADP1708 Power Supply Rejection Ratio vs. Input Voltage
ILOAD = 300mA
ILOAD = 200mA
ILOAD = 100mA
ILOAD = 10mA
ILOAD = 1mA
ILOAD = 100µA
–30
4.7
VIN (V)
CSS (nF)
0
4.2
06640-026
0
VOUT = 0.8V
06640-023
2
–40
–50
VRIPPLE = 50mV
VIN = 5V
ILOAD = 10mA
COUT = 4.7μF
FREQUENCY = 10kHz
–45
–60
–90
10
06640-024
–80
100
1k
10k
100k
1M
–55
0.8
10M
Figure 23. ADP1706 Power Supply Rejection Ratio vs. Frequency
–10
–20
VRIPPLE = 50mV
VIN = 5V
VOUT = 0.8V
COUT = 4.7μF
PSRR (dB)
–40
–50
–60
–70
06640-025
–80
–90
10
100
1k
10k
100k
1.8
2.3
2.8
3.3
3.8
4.3
Figure 26. ADP1708 Power Supply Rejection Ratio vs. Output Voltage
ILOAD = 300mA
ILOAD = 200mA
ILOAD = 100mA
ILOAD = 10mA
ILOAD = 1mA
ILOAD = 100µA
–30
1.3
VOUT (V)
FREQUENCY (Hz)
0
06640-027
–50
–70
1M
10M
FREQUENCY (Hz)
Figure 24. ADP1708 Power Supply Rejection Ratio vs. Frequency
Rev. 0 | Page 9 of 20
ADP1706/ADP1707/ADP1708
THEORY OF OPERATION
The ADP1706/ADP1707/ADP1708 are low dropout linear
regulators that use an advanced, proprietary architecture to
provide high power supply rejection ratio (PSRR) and excellent
line and load transient response with a small 4.7 μF ceramic
output capacitor. All devices operate from a 2.5 V to 5.5 V input
rail and provide up to 1 A of output current. Supply current in
shutdown mode is typically 100 nA.
IN
providing a smooth ramp-up to the nominal output voltage.
The soft start time is calculated by
TSS = VREF × (CSS/ISS)
(1)
where:
TSS is the soft start period.
VREF is the 0.8 V reference voltage.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (1.2 μA).
When the ADP1706 is disabled (using EN), the soft start capacitor
is discharged to GND through an internal 100 Ω resistor.
OUT
SENSE
CURRENT LIMIT
THERMAL PROTECT
EN
SHUTDOWN
The ADP1706/ADP1707 are available in 16 fixed output voltage
options between 0.75 V and 3.3 V. The ADP1706 allows for
connection of an external soft start capacitor, which controls
the output voltage ramp during startup. The ADP1707 features
a TRK pin that allows the output voltage to follow the voltage at
this pin. The ADP1708 is available in an adjustable version with
an output voltage that can be set to between 0.8 V and 5.0 V by
an external voltage divider. All devices are controlled by an
enable pin (EN).
VIN = 5V
VOUT = 3.3V
COUT = 4.7μF
CSS = 10nF
ILOAD = 1A
1
TIME (2ms/DIV)
Figure 28. OUT Ramp-Up with External Soft Start Capacitor
The ADP1707 and ADP1708 have no pins for soft start;
therefore, the function is switched to an internal soft start
capacitor, which sets the soft start ramp-up period to approximately 48 μs. Note that the ramp-up period is the time it takes
OUT to go from 0% to 90% of the nominal value and is
different from the start-up time in Table 1, which is the time
between the rising edge of EN to OUT being at 90% of the
nominal value. For the worst-case output voltage of 5 V, using
the suggested 4.7 μF output capacitor, the resulting input
inrush current is approximately 490 mA, which is less than
the maximum 1 A load current.
SOFT START FUNCTION (ADP1706)
For applications that require a controlled startup, the ADP1706
provides a programmable soft start function. The programmable soft start is useful for reducing inrush current upon startup
and for providing voltage sequencing. To implement a soft start,
connect a small ceramic capacitor from SS to GND. Upon
startup, a 1.2 μA current source charges this capacitor. The
ADP1706 start-up output voltage is limited by the voltage at SS,
Rev. 0 | Page 10 of 20
EN
2
1
VIN = 5V
VOUT = 1.6V
COUT = 4.7μF
ILOAD = 10mA
OUT
TIME (20µs/DIV)
Figure 29. OUT Ramp-Up with Internal Soft Start
06640-029
Internally, the ADP1706/ADP1707/ADP1708 consist of a
reference, an error amplifier, a feedback voltage divider, and a
PMOS pass transistor. Output current is delivered via the
PMOS pass device, which is controlled by the error amplifier.
The error amplifier compares the reference voltage with the
feedback voltage from the output and amplifies the difference. If
the feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current
to pass and increasing the output voltage. If the feedback
voltage is higher than the reference voltage, the gate of the
PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
1V/DIV
Figure 27. Internal Block Diagram
06640-028
2V/DIV
OUT
2V/DIV
GND
2
1V/DIV
SOFT
START
REFERENCE
06640-016
EN
ADJ/
TRK/
SS
ADP1706/ADP1707/ADP1708
ADJUSTABLE OUTPUT VOLTAGE (ADP1708)
ENABLE FEATURE
The ADP1708 can have its output voltage set over a 0.8 V to
5.0 V range. The output voltage is set by connecting a resistive
voltage divider from OUT to ADJ. The output voltage is
calculated by
The ADP1706/ADP1707/ADP1708 use the EN pin to enable
and disable the OUT pin under normal operating conditions.
As shown in Figure 31, when a rising voltage on EN crosses the
active threshold, OUT turns on. When a falling voltage on EN
crosses the inactive threshold, OUT turns off.
VOUT = 0.8 V (1 + R1/R2)
(2)
where:
R1 is the resistor from OUT to ADJ.
R2 is the resistor from ADJ to GND.
EN
500mV/DIV
The maximum bias current into ADJ is 100 nA, so for less
than 0.5% error due to the bias current, use values less than
60 kΩ for R2.
TRACK MODE (ADP1707)
VIN = 5V
VOUT = 1.6V
COUT = 4.7μF
ILOAD = 10mA
TIME (10ms/DIV)
4.0
Figure 31. ADP1706 Typical EN Pin Operation
3.5
As shown in Figure 31, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
3.0
The EN pin active/inactive thresholds are derived from the IN
voltage. Therefore, these thresholds vary when changing the
input voltage. Figure 32 shows typical EN active/inactive
thresholds when the input voltage varies from 2.5 V to 5.5 V.
2.0
1.5
1.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.3
5.0
VTRK (V)
Figure 30. ADP1707 Output Voltage vs. Tracking Voltage
For example, consider an ADP1707 with a nominal output
voltage of 3.3 V. If the voltage applied to its TRK pin is greater
than 3.3 V, OUT maintains a nominal output voltage of 3.3 V.
If the voltage applied to TRK is reduced below 3.3 V, OUT
tracks this voltage. OUT can track the TRK pin voltage from
the nominal value all the way down to 0 V. A voltage divider is
present from TRK to the error amplifier input with a divider
ratio equal to the divider from OUT to the error amplifier,
which sets the output voltage equal to the tracking voltage.
Both divider ratios are set by postpackage trim, depending on
the desired output voltage.
Rev. 0 | Page 11 of 20
1.2
1.1
EN ACTIVE
HYSTERESIS
1.0
0.9
0.8
0.7
EN INACTIVE
0.6
06640-032
0
1.4
06640-030
VIN = 3.8V
VOUT = 3.3V
ILOAD = 10mA
0.5
TYPICAL EN THRESHOLDS (V)
VOUT (V)
2.5
0
06640-031
OUT
The ADP1707 includes a tracking mode feature. As shown in
Figure 30, if the voltage applied at the TRK pin is less than the
nominal output voltage, OUT is equal to the voltage at TRK.
Otherwise, OUT regulates to its nominal output value.
0.5
2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
VIN (V)
Figure 32. Typical EN Pin Thresholds vs. Input Voltage
ADP1706/ADP1707/ADP1708
APPLICATION INFORMATION
CAPACITOR SELECTION
Input Bypass Capacitor
Output Capacitor
Connecting a 4.7 μF capacitor from the IN pin to GND reduces
the circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces, or high source impedance,
is encountered. If greater than 4.7 μF of output capacitance is
required, it is recommended that the input capacitor be increased
to match it.
VOUT RESPONSE TO LOAD STEP
FROM 50mA TO 950mA
Input and Output Capacitor Properties
Any good quality ceramic capacitors can be used with the
ADP1706/ADP1707/ADP1708, as long as they meet the
minimum capacitance and maximum ESR requirements.
Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U
dielectrics are not recommended, due to their poor temperature
and dc bias characteristics.
VOLTAGE TRACKING APPLICATIONS
RATIO VOLTAGE TRACKING
ADP1706-2.5
VIN = 3.8V
VOUT = 1.6V
CIN = 4.7μF
COUT = 4.7μF
06640-033
5V
IN
OUT
EN
SS
R1
GND
2.5V
2.5V
1.2V
ADP1707-1.2
TIME (2μs/DIV)
RATIO
TRACKING
VOUT
R2
OUT
TRK
IN
EN
GND
Figure 33. Output Transient Response, COUT = 4.7 μF
I/O POWER RAIL
CORE RAIL
1.2V
TIME
06640-042
50mV/DIV
The ADP1706/ADP1707/ADP1708 are designed for operation
with small, space-saving ceramic capacitors, but they function
with most commonly used capacitors as long as care is taken with
the effective series resistance (ESR) value. The ESR of the output
capacitor affects stability of the LDO control loop. A minimum of
4.7 μF capacitance with an ESR of 500 mΩ or less is recommended
to ensure stability of the ADP1706/ADP1707/ADP1708. Transient
response to changes in load current is also affected by output
capacitance. Using a larger value of output capacitance improves
the transient response of the ADP1706/ADP1707/ADP1708 to
large changes in load current. Figure 33 and Figure 34 show the
transient responses for output capacitance values of 4.7 μF and
22 μF, respectively.
Figure 35 shows an application where the ADP1707 tracking
feature is used. An ADP1706 powers the I/O of a microprocessor and an ADP1707 powers the core. At startup, the output of
the ADP1706 ramps to 2.5 V, which is divided down via a
voltage divider (R1 and R2) to a lower voltage at the TRK pin of
the ADP1707. The output of the ADP1707 thus follows the
TRK pin and ramps up steadily to 1.2 V. This implementation
ensures that the core of the processor powers up after the I/O.
VOUT RESPONSE TO LOAD STEP
FROM 50mA TO 950mA
VIN = 3.8V
VOUT = 1.6V
CIN = 22μF
COUT = 22μF
TIME (2μs/DIV)
Figure 34. Output Transient Response, COUT = 22 μF
06640-034
50mV/DIV
Figure 35. Voltage Tracking Feature Using ADP1707
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP1706/ADP1707/ADP1708 are protected against
damage due to excessive power dissipation by current and
thermal overload protection circuits. The ADP1706/ADP1707/
ADP1708 are designed to reach current limit when the output
load reaches 1.5 A (typical). When the output load exceeds
1.5 A, the output voltage is reduced to maintain a constant
current limit.
Rev. 0 | Page 12 of 20
ADP1706/ADP1707/ADP1708
Thermal overload protection is included, which limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to
rise above 150°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
135°C (typical), the output is turned on again and output
current is restored to its nominal value.
Consider the case where a hard short from OUT to ground
occurs. At first, the ADP1706/ADP1707/ADP1708 reach
current limit so that only 1.5 A is conducted into the short. If
self-heating of the junction becomes great enough to cause its
temperature to rise above 150°C, thermal shutdown activates,
turning off the output and reducing the output current to
zero. As the junction temperature cools and drops below
135°C, the output turns on and conducts 1.5 A into the short,
again causing the junction temperature to rise above 150°C.
This thermal oscillation between 135°C and 150°C causes a
current oscillation between 1.5 A and 0 A that continues as
long as the short remains at the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation should be externally limited
so junction temperatures do not exceed 125°C.
The junction temperature of the ADP1706/ADP1707/ADP1708
can be calculated by
TJ = TA + (PD × θJA)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN – VOUT) × ILOAD] + (VIN × IGND)
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation
simplifies to the following:
TJ = TA + {[(VIN – VOUT) × ILOAD] × θJA}
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
Table 5. Typical θJA Values
1
(5)
As shown in Equation 5, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, a minimum copper size requirement exists for the PCB
to ensure the junction temperature does not rise above 125°C.
Figure 36 to Figure 41 show junction temperature calculations
for different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
120
100
80
60
40
20
1mA
10mA
0
0.5
1.0
100mA
300mA
1.5
2.0
500mA
750mA
2.5
3.0
1A
(LOAD CURRENT)
3.5
4.0
4.5
VIN – VOUT (V)
θJA (°C/W), LFCSP
65.9
62.3
61.2
59.7
59.4
Device soldered to minimum size pin traces.
Rev. 0 | Page 13 of 20
Figure 36. 500 mm2 of PCB Copper, TA = 25°C, SOIC
06640-035
TJ (°C)
To guarantee reliable operation, the junction temperature of
the ADP1706/ADP1707/ADP1708 must not exceed 125°C. To
ensure that the junction temperature stays below this maximum
value, the user needs to be aware of the parameters that contribute to junction temperature changes. These parameters include
ambient temperature, power dissipation in the power device,
and thermal resistance between the junction and ambient air (θJA).
The θJA value is dependent on the package assembly compounds
used and the amount of copper to which the GND pins of the
package are soldered on the PCB. Table 5 shows typical θJA values
of the 8-lead SOIC and 8-lead LFCSP for various PCB copper sizes.
θJA (°C/W), SOIC
57.6
53.1
52.3
51.3
51.3
(4)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are the input and output voltages, respectively.
THERMAL CONSIDERATIONS
Copper Size (mm2)
01
50
100
300
500
(3)
5.0
ADP1706/ADP1707/ADP1708
140
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
120
100
100
80
80
TJ (°C)
60
40
0
0.5
1mA
10mA
1.0
100mA
300mA
1.5
2.0
500mA
750mA
2.5
3.0
1A
(LOAD CURRENT)
3.5
4.0
4.5
20
06640-036
20
0
0.5
5.0
1mA
10mA
1.0
100mA
300mA
1.5
2.0
VIN – VOUT (V)
3.0
3.5
4.0
5.0
4.5
Figure 40. 100 mm2 of PCB Copper, TA = 25°C, LFCSP
140
140
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
120
100
100
80
80
TJ (°C)
TJ (°C)
2.5
1A
(LOAD CURRENT)
VIN – VOUT (V)
Figure 37. 100 mm2 of PCB Copper, TA = 25°C, SOIC
60
40
60
40
0
0.5
1mA
10mA
1.0
100mA
300mA
1.5
2.0
500mA
750mA
2.5
3.0
1A
(LOAD CURRENT)
3.5
4.0
4.5
20
06640-037
20
0
0.5
5.0
VIN – VOUT (V)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
120
100
80
60
20
1.0
100mA
300mA
1.5
2.0
500mA
750mA
2.5
3.0
1A
(LOAD CURRENT)
3.5
4.0
4.5
06640-038
40
1mA
10mA
1.0
100mA
300mA
1.5
2.0
500mA
750mA
2.5
3.0
1A
(LOAD CURRENT)
3.5
4.0
4.5
Figure 41. 0 mm2 of PCB Copper, TA = 25°C, LFCSP
140
0
0.5
1mA
10mA
VIN – VOUT (V)
Figure 38. 0 mm2 of PCB Copper, TA = 25°C, SOIC
TJ (°C)
500mA
750mA
06640-039
40
60
5.0
VIN – VOUT (V)
Figure 39. 500 mm2 of PCB Copper, TA = 25°C, LFCSP
Rev. 0 | Page 14 of 20
06640-040
TJ (°C)
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
5.0
ADP1706/ADP1707/ADP1708
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP1706/ADP1707/ADP1708. However, as can be seen from
Table 5, a point of diminishing returns is eventually reached,
beyond which an increase in the copper size does not yield
significant heat dissipation benefits.
Use of 0402 or 0603 size capacitors and resistors achieves the
smallest possible footprint solution on boards where area is
limited.
The ADP1706/ADP1707/ADP1708 feature an exposed pad on
the bottom of both the SOIC and LFCSP packages to improve
thermal performance. Because the exposed pad is electrically
connected to GND inside the package, it is recommended that
it also be connected to the ground plane on the PCB with a
sufficient amount of copper.
ANALOG
DEVICES
ADP1706/ADP1707/ADP1708
SOIC8
GND
C3
C1
U1
•
•
R1
R2
Place the input capacitor as close as possible to the IN and
GND pins.
Place the output capacitor as close as possible to the OUT
and GND pins.
For the ADP1706, place the soft start capacitor as close as
possible to the SS pin.
Connect the load as close as possible to the OUT and
SENSE pins.
Rev. 0 | Page 15 of 20
VIN
GND
VOUT
EN
ADJ/TRK/SS
Figure 42. Example PCB Layout
GND
06640-041
•
GND
J1
Here are a few general tips when designing PCBs:
•
C2
ADP1706/ADP1707/ADP1708
OUTLINE DIMENSIONS
5.00 (0.197)
4.90 (0.193)
4.80 (0.189)
4.00 (0.157)
3.90 (0.154)
3.80 (0.150)
8
5
TOP VIEW
1
4
3.098 (0.122)
2.41 (0.095)
6.20 (0.244)
6.00 (0.236)
5.80 (0.228)
BOTTOM VIEW
1.27 (0.05)
BSC
(PINS UP)
1.75 (0.069)
1.35 (0.053)
1.65 (0.065)
1.25 (0.049)
0.10 (0.004)
MAX
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.020)
0.31 (0.012)
0.50 (0.020)
0.25 (0.010)
0.25 (0.0098)
0.17 (0.0067)
45°
1.27 (0.050)
0.40 (0.016)
8°
0°
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506-A
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 43. 8-Lead Standard Small Outline Package, with Expose Pad [SOIC_N_EP]
Narrow Body
(RD-8-2)
Dimensions shown in millimeters and (inches)
3.25
3.00 SQ
2.75
0.60 MAX
5
TOP
VIEW
PIN 1
INDICATOR
2.95
2.75 SQ
2.55
8
12° MAX
1
1.89
1.74
1.59
PIN 1
INDICATOR
0.05 MAX
0.01 NOM
0.30
0.23
0.18
0.20 REF
Figure 44. 8-Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
Rev. 0 | Page 16 of 20
061507-B
SEATING
PLANE
0.50
0.40
0.30
0.70 MAX
0.65 TYP
1.60
1.45
1.30
EXPOSED
PAD
(BOTTOM VIEW)
4
0.90 MAX
0.85 NOM
0.50
BSC
0.60 MAX
ADP1706/ADP1707/ADP1708
ORDERING GUIDE
Model
ADP1706ARDZ-0.75R7 1
ADP1706ARDZ-0.8-R71
ADP1706ARDZ-0.85R71
ADP1706ARDZ-0.9-R71
ADP1706ARDZ-0.95R71
ADP1706ARDZ-1.0-R71
ADP1706ARDZ-1.05R71
ADP1706ARDZ-1.1-R71
ADP1706ARDZ-1.15R71
ADP1706ARDZ-1.2-R71
ADP1706ARDZ-1.3-R71
ADP1706ARDZ-1.5-R71
ADP1706ARDZ-1.8-R71
ADP1706ARDZ-2.5-R71
ADP1706ARDZ-3.0-R71
ADP1706ARDZ-3.3-R71
ADP1706ACPZ-0.75R71
ADP1706ACPZ-0.8-R71
ADP1706ACPZ-0.85R71
ADP1706ACPZ-0.9-R71
ADP1706ACPZ-0.95R71
ADP1706ACPZ-1.0-R71
ADP1706ACPZ-1.05R71
ADP1706ACPZ-1.1-R71
ADP1706ACPZ-1.15R71
ADP1706ACPZ-1.2-R71
ADP1706ACPZ-1.3-R71
ADP1706ACPZ-1.5-R71
ADP1706ACPZ-1.8-R71
ADP1706ACPZ-2.5-R71
ADP1706ACPZ-3.0-R71
ADP1706ACPZ-3.3-R71
ADP1707ARDZ-0.75R71
ADP1707ARDZ-0.8-R71
ADP1707ARDZ-0.85R71
ADP1707ARDZ-0.9-R71
ADP1707ARDZ-0.95R71
ADP1707ARDZ-1.0-R71
ADP1707ARDZ-1.05R71
ADP1707ARDZ-1.1-R71
ADP1707ARDZ-1.15R71
ADP1707ARDZ-1.2-R71
ADP1707ARDZ-1.3-R71
ADP1707ARDZ-1.5-R71
ADP1707ARDZ-1.8-R71
ADP1707ARDZ-2.5-R71
ADP1707ARDZ-3.0-R71
ADP1707ARDZ-3.3-R71
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output Voltage (V)
0.75
0.8
0.85
0.9
0.95
1.0
1.05
1.1
1.15
1.2
1.3
1.5
1.8
2.5
3.0
3.3
0.75
0.8
0.85
0.9
0.95
1.0
1.05
1.1
1.15
1.2
1.3
1.5
1.8
2.5
3.0
3.3
0.75
0.8
0.85
0.9
0.95
1.0
1.05
1.1
1.15
1.2
1.3
1.5
1.8
2.5
3.0
3.3
Rev. 0 | Page 17 of 20
Package Description
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Package Option
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
RD-8-2
Branding
L62
L63
L64
L6J
L68
L65
L67
L66
L69
L6A
L6C
L6D
L6H
L6E
L6F
L6G
ADP1706/ADP1707/ADP1708
Model
ADP1707ACPZ-0.75R71
ADP1707ACPZ-0.8-R71
ADP1707ACPZ-0.85R71
ADP1707ACPZ-0.9-R71
ADP1707ACPZ-0.95R71
ADP1707ACPZ-1.0-R71
ADP1707ACPZ-1.05R71
ADP1707ACPZ-1.1-R71
ADP1707ACPZ-1.15R71
ADP1707ACPZ-1.2-R71
ADP1707ACPZ-1.3-R71
ADP1707ACPZ-1.5-R71
ADP1707ACPZ-1.8-R71
ADP1707ACPZ-2.5-R71
ADP1707ACPZ-3.0-R71
ADP1707ACPZ-3.3-R71
ADP1708ARDZ-R71
ADP1708ACPZ-R71
ADP1706-3.3-EVALZ1
ADP1707-3.3-EVALZ1
ADP1708-EVALZ1
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Output Voltage (V)
0.75
0.8
0.85
0.9
0.95
1.0
1.05
1.1
1.15
1.2
1.3
1.5
1.8
2.5
3.0
3.3
0.8 to 5.0
0.8 to 5.0
3.3
3.3
Adjustable, but set to 1.6 V
Z = RoHS Compliant Part.
Rev. 0 | Page 18 of 20
Package Description
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead SOIC_N_EP
8-Lead LFCSP_VD
Evaluation Board
Evaluation Board
Evaluation Board
Package Option
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
CP-8-2
RD-8-2
CP-8-2
Branding
L6P
L6Q
L6R
L6S
L6T
L6U
L6V
L6W
L6X
L6Y
L6Z
L70
L71
L72
L73
L74
L7P
ADP1706/ADP1707/ADP1708
NOTES
Rev. 0 | Page 19 of 20
ADP1706/ADP1707/ADP1708
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06640-0-6/07(0)
Rev. 0 | Page 20 of 20