DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator Features General Description • Low RMS Phase Jitter: <1 ps (typ.) • High Stability: ±25 ppm, ±50 ppm • Wide Temperature Range: - Industrial –40°C to +85°C - Ext. Commercial –20°C to +70°C • High Supply Noise Rejection: –50 dBc • Four Format-Configurable Outputs: - LVPECL, LVDS, HCSL, LVCMOS • Available Pin-Selectable Frequency Table - 1 Pin per Bank for 2 Frequency Sets • Wide Frequency Range: - 2.3 MHz – 460 MHz • 20-Pin QFN Footprint (5.0 mm x 3.2 mm) • Excellent Shock and Vibration Immunity • High Reliability - 20x better MTF than quartz-based devices • Wide Supply Range of 2.25V to 3.6V • Lead Free and RoHS-Compliant • AEC-Q100 Automotive Qualified The DSC400 is a four output crystal-less™ clock generator. It utilizes proven PureSilicon™ MEMS technology to provide excellent jitter and stability while incorporating additional device functionality. The nominal frequencies of the outputs can be identical or independently derived from common PLLs. Each output may be configured independently to support a single-ended LVCMOS interface or a differential interface. Differential options include LVPECL, LVDS, or HCSL. The DSC400 provides two independent select lines for choosing between two sets of pre-configured frequencies per bank. It also has two OE pins to allow for enabling and disabling outputs. The DSC400 is packaged in a 20-pin QFN (5 mm x 3.2 mm) and is available in extended commercial and industrial temperature grades. Block Diagram CONTROL CIRCUITRY Applications • Communications and Networks • Ethernet - 1G, 10GBASE-T/KR/LR/SR, and FCoE • Storage Area Networks - SATA, SAS, Fibre Channel • Passive Optical Networks - EPON, 10G-EPON, GPON, 10G-PON • HD/SD/SDI Video and Surveillance • Automotive • Media and Video • Embedded and Industrial 2016 Microchip Technology Inc. CLK0+ CLK0BANK 1 MEMS PLL PLL OE1 OE2 OUTPUT CONTROL AND DIVIDERS CLK3+ CLK3- CLK1+ CLK1- BANK 2 FSB1 FSB2 CLK2+ CLK2- DS20005612A-page 1 DSC400 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Supply Voltage .......................................................................................................................................... –0.3V to +4.0V Input Voltage .......................................................................................................................................–0.3V to VDD+0.3V ESD Protection (HBM) ...............................................................................................................................................4 kV ESD Protection (MM) ................................................................................................................................................400V ESD Protection (CDM) ............................................................................................................................................1.5 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Specifications: VDD = 3.3V; TA = +25°C unless otherwise specified. Parameters Supply Voltage (Note 1) Core Supply Current (Note 2) Frequency Stability Sym. Min. Typ. Max. Units VDD 2.25 — 3.6 V IDDCORE — 40 44 mA OE(1:2) = 0. All outputs disabled. ppm All temperature and VDD ranges. ppm One year at +25°C ∆f — — ±25 — — ±50 Conditions — Aging - First Year ∆fY1 — — ±5 Aging - After First Year ∆fY2+ — — <±1 Start-up Time (Note 3) tSU — — 5 ms Input Logic Levels VIH 0.75 x VDD — — V VIL — — 0.25 x VDD Output Disable Time (Note 4) tDA — — 5 ns OE(1:2) transition from 1 to 0 Output Enable Time (Note 4) tEN — — 20 ns OE(1:2) transition from 0 to 1 Pull-Up Resistor RPU — 40 — kΩ All input pins have an internal pull-up Note 1: 2: 3: 4: ppm/yr Year two and beyond at +25°C T = +25°C Input logic high Input logic low VDD pins should be filtered with a 0.1 µF capacitor connected between VDD and VSS. The addition of IDDCORE and IDDIO provides the total current consumption of the device. tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled. See the Output Waveform section for more information. DS20005612A-page 2 2016 Microchip Technology Inc. DSC400 TEMPERATURE SPECIFICATIONS (Note 1) Parameters Sym. Min. Typ. Max. Units Conditions TA –20 — +70 °C Ordering Option E Temperature Ranges Operating Temperature Range (T) TA –40 — +85 °C Ordering Option I Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –40 — +150 °C — Soldering Temperature — — — +260 °C 40 sec. max. Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability. 2016 Microchip Technology Inc. DS20005612A-page 3 DSC400 CLK3+ CLK3- CLK2+ CLK2- 20 19 18 17 16 15 OE1 1 14 VSS NC 2 13 VSS VSS 3 12 NC VSS 4 11 OE2 5 6 7 8 9 10 CLK0- CLK0+ CLK1- CLK1+ VDD2 FSB2 FIGURE 2-1: VDD1 PIN DESCRIPTIONS FSB1 2.0 Pin Configuration, 20-Pin QFN (5.0 mm x 3.2 mm) The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Pin Type 1 OE1 I 2 NC N/A Description Output Enable for Bank1 (CLK0 and CLK3); Active-High. See Table 3-1. Leave unconnected or connect to ground. 3 VSS PWR Ground. 4 VSS PWR Ground. 5 CLK0– O Complement output of differential pair 0 (off when in LVCMOS format). 6 CLK0+ O True output of differential pair 0 or LVCMOS output 0. 7 CLK1– O Complement output of differential pair 1 (off when in LVCMOS format). 8 CLK1+ O True output of differential pair 1 or LVCMOS output 1. 9 VDD2 PWR 10 FSB2 I Input for selecting pre-configured frequencies on Bank2 (CLK1 and CLK2). 11 OE2 I Output Enable for Bank2 (CLK1 and CLK2); Active-High. See Table 3-1. 12 NC N/A Power Supply for Bank2 (CLK1 and CLK2). Leave unconnected or connect to ground. 13 VSS PWR Ground. 14 VSS PWR Ground. 15 CLK2– O Complement output of differential pair 2 (off when in LVCMOS format). 16 CLK2+ O True output of differential pair 2 or LVCMOS output 2. 17 CLK3– O Complement output of differential pair 3 (off when in LVCMOS format). 18 CLK3+ O 19 VDD1 PWR 20 FSB1 I DS20005612A-page 4 True output of differential pair 3 or LVCMOS output 3. Power Supply for Bank1 (CLK0 and CLK3). Input for selecting pre-configured frequencies on Bank1 (CLK0 and CLK3). 2016 Microchip Technology Inc. DSC400 3.0 OPERATIONAL DESCRIPTION The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an external crystal to operate; it relies on the integrated MEMS resonator that interfaces with internal PLLs. This technology enhances performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher resistance to shock and vibration decreases the aging rate to allow for much improved product life in the system. 3.1 chosen from 2.3 MHz to 460 MHz for differential outputs and from 2.3 MHz to 170 MHz on LVCMOS outputs. 3.3 Power VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may each have a different supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1 µF capacitor to filter high-frequency noise. VSS is common to the entire device. Inputs There are four input signals in the device. Each has an internal (40 kΩ) pull-up to default the selection to a high (1). Inputs can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs In case more than one frequency set is desired, FSB1 and FSB2 are used to independently select one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3) and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in Table 1-1 in the Product Identification System section. If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to disable the banks of outputs. Outputs are disabled in tri-state (Hi-Z) mode. See Table 3-1 for more information. TABLE 3-1: OUTPUT ENABLE SELECTION TABLE OE1 OE2 Bank 1 (CLK0 & CLK3) Bank 2 (CLK1 & CLK2) 0 0 Hi-Z Hi-Z 0 1 Hi-Z Running 1 0 Running Hi-Z 1 1 Running Running 3.2 Outputs The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL: • Bank1 is composed of outputs CLK0 and CLK3. • Bank2 is composed of outputs CLK1 and CLK2. Each output may be pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL. In case the output is configured to be single-ended LVCMOS, the frequency is generated on the true output (CLKx+) and the complement output (CLKx–) is shut off in a low state. Frequencies can be 2016 Microchip Technology Inc. DS20005612A-page 5 DSC400 4.0 TERMINATION SCHEMES 4.1 LVPECL VDD 130 Ω 130 Ω 100 Ω 82 Ω FIGURE 4-1: TABLE 4-1: Parameter 82 Ω Typical LVPECL Termination Scheme. LVPECL OUTPUTS (Note 1) Symbol Min. Typ. Max. Units Output Logic Levels VOH VDD – 1.08 — — V VOL — — VDD – 1.55 Peak-to-Peak Output Swing — — 800 — mV Single-Ended Output Transition Time (Note 2) tR — 250 — ps Rise Time. 20% to 80%; RL = 50Ω to VDD–2V tF — 250 — Frequency Condition Output Logic High, RL = 50Ω to VDD–2V Output Logic Low, RL = 50Ω to VDD–2V Fall Time. 20% to 80%; RL = 50Ω to VDD–2V f0 2.3 — 460 MHz Output Duty Cycle SYM 48 — 52 % IO Supply Current (Note 3) IDDIO — 35 38 mA Period Jitter (Note 4) JPER — 2.5 — psRMS CLK(0:3) = 156.25 MHz Integrated Phase Noise JPH — 0.25 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.38 — 100 kHz to 20 MHz @ 156.25 MHz Single Frequency Differential Per Output at 125 MHz — 1.7 2 12 kHz to 20 MHz @ 156.25 MHz Note 1: LVPECL applicable to extended commercial temperature only. 2: See the Output Waveform section for more information. 3: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 4: Period jitter includes crosstalk from adjacent output. DS20005612A-page 6 2016 Microchip Technology Inc. DSC400 4.2 LVDS 100 Ω 100 Ω Load (receiver IC) FIGURE 4-2: Typical LVDS Termination Scheme. If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and placed as close as possible to the receiver. TABLE 4-2: Parameter LVDS OUTPUTS Symbol Min. Typ. Max. Units Output Offset Voltage VOS 1.125 — 1.4 V Delta Offset Voltage ∆VOS — — 50 mV — VPP — 350 — mV Single-Ended Output Transition Time (Note 1) tR — 200 — ps Rise Time, 20% to 80%, RL= 50Ω, CL= 2 pF tF — 200 — Frequency f0 2.3 — 460 MHz Output Duty Cycle SYM 48 — 52 % IO Supply Current (Note 2) IDDIO — 9 12 mA Period Jitter JPER — 2.5 — psRMS — Integrated Phase Noise JPH — 0.28 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.4 — 100 kHz to 20 MHz @ 156.25 MHz Peak-to-Peak Output Swing Condition R = 100Ω Differential Fall Time, 20% to 80%, RL= 50Ω, CL= 2 pF — 1.7 2.0 Note 1: See the Output Waveform section for more information. Single Frequency Differential Per Output at 125 MHz. 12 kHz to 20 MHz @156.25 MHz 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 2016 Microchip Technology Inc. DS20005612A-page 7 DSC400 4.3 HCSL RS 100 Ω RS FIGURE 4-3: 50 Ω 50 Ω Typical HCSL Termination Scheme. RS is a series resistor implemented to match the trace impedance. Depending on the board layout, the value may range from 0Ω to 30Ω. TABLE 4-3: Parameter HCSL OUTPUTS Symbol Min. Typ. Max. Units Output Logic Levels VOH 0.725 — — V VOL — — 0.1 Peak-to-Peak Output Swing — — 750 — mV Single-Ended Output Transition Time (Note 1) tR 200 — 400 ps Rise Time, 20% to 80%, RL= 50Ω, CL= 2 pF tF 200 — 400 Frequency Condition Output Logic High, RL = 50Ω Output Logic Low, RL = 50Ω Fall Time, 20% to 80%, RL= 50Ω, CL= 2 pF f0 2.3 — 460 MHz Output Duty Cycle SYM 48 — 52 % IO Supply Current (Note 2) IDDIO — 20 22 mA Period Jitter JPER — 2.5 — psRMS — Integrated Phase Noise JPH — 0.25 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.37 — 100 kHz to 20 MHz @ 156.25 MHz — 1.7 2.0 Note 1: See the Output Waveform section for more information. Single Frequency Differential Per Output at 125 MHz. 12 kHz to 20 MHz @156.25 MHz 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device. DS20005612A-page 8 2016 Microchip Technology Inc. DSC400 4.4 LVCMOS 50 Ω RS FIGURE 4-4: Typical LVCMOS Termination Scheme. RS is a series resistor implemented to match the trace impedance to that of the clock output. Depending on the board layout, the value may range from 0Ω to 27Ω. TABLE 4-4: Parameter LVCMOS OUTPUTS Symbol Min. Typ. Max. Units VOH 0.9 x VDD — — V Output Logic High, I = ±6 mA VOL — — 0.1 x VDD Output Transition Time (Note 1) tR — 1.1 2.0 ns Rise Time, 20% to 80%, CL= 15 pF tF — 1.3 2.0 Frequency f0 2.3 — 170 — — 100 Output Logic Levels Condition Output Logic Low, I = ±6 mA Fall Time, 20% to 80%, CL= 15 pF MHz All Temperature Ranges, Except Automotive Automotive Temperature Range Output Duty Cycle SYM 44 — 55 % IO Supply Current (Note 2) IDDIO — 11 14 mA Period Jitter JPER — 3 — psRMS CLK(0:3) = 125 MHz Integrated Phase Noise JPH — 0.3 — psRMS 200 kHz to 20 MHz @ 125 MHz — 0.38 — 100 kHz to 20 MHz @ 125 MHz — 1.7 2.0 Note 1: See the Output Waveform section for more information. — Per Output at 125 MHz, CL = 15 pF 12 kHz to 20 MHz @125 MHz 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 2016 Microchip Technology Inc. DS20005612A-page 9 DSC400 5.0 OUTPUT WAVEFORM tR Clk Clk tF 80% 50% 20% tEN 1/f0 tDA OE VIH VIL FIGURE 5-1: Differential Output (LVDS, LVPECL, HCSL). tR tF VOH Clk VOL tEN 1/f0 tDA OE VIH VIL FIGURE 5-2: DS20005612A-page 10 LVCMOS Output. 2016 Microchip Technology Inc. DSC400 6.0 CONNECTION DIAGRAM The connection diagram below includes recommended capacitors to be placed on each VDD for noise filtering. VDD Clock 3 Output 0.1μF Clock 2 Output CLK2‒ CLK2+ CLK3‒ OE1 CLK3+ FSB1 Output Enable 1 VDD1 Frequency Select 1 VSS Frequency Select 2 FSB2 OE2 VDD2 VSS CLK1+ NC CLK1‒ VSS CLK0+ VSS CLK0‒ NC VDD 0.1μF Output Enable 2 Clock 1 Output Clock 0 Output FIGURE 6-1: DSC400 Connection Diagram. 2016 Microchip Technology Inc. DS20005612A-page 11 DSC400 7.0 SOLDER REFLOW PROFILE Temperature 8 minutes max. 3° C m / se ax c . 260°C 20-40 seconds 217°C / 6°C 200°C 3° C/ se cm ax . 25°C 60-180 seconds Preheat 60-150 seconds Reflow x. ma sec 150°C Cooldown Time MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/sec. max. Preheat Time 150°C to 200°C 60-180 sec. Time Maintained above 217°C 60-150 sec. Peak Temperature Time within 5°C of Actual Peak 255°C to 260°C 20-40 sec. Ramp-Down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 minutes max. DS20005612A-page 12 2016 Microchip Technology Inc. DSC400 8.0 PACKAGE MARKING INFORMATION 20-Lead QFN 5.0 mm x 3.2 mm Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 2016 Microchip Technology Inc. DS20005612A-page 13 DSC400 NOTES: DS20005612A-page 14 2016 Microchip Technology Inc. DSC400 APPENDIX A: REVISION HISTORY Revision A (September 2016) • Converted Micrel data sheet DSC400 to Microchip DS20005612A. • Minor text changes throughout. 2016 Microchip Technology Inc. DS20005612A-page 15 DSC400 NOTES: DS20005612A-page 16 2016 Microchip Technology Inc. DSC400 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Device X X PART NO. X X Qxxxx X X DSC400: Device: Configurable Four Output, Low Jitter Crystal-less Clock Generator X Examples: a) DSC400-2143QxxxxKE1T: Configurable Four Output, Low Jitter Crystal-less Clock Generator; LVPECL CLK3; LVCMOS CLK2; HCSL CLK1; LVDS CLK0; Frequency Code; 20-Pin QFN; –20°C to +70°C Temp. Range; ±50 ppm Stability; Tape & Reel CLK3 Output Format: 0 1 2 3 4 = = = = = OFF LVCMOS LVPECL LVDS HCSL CLK2 Output Format: 1 2 3 4 = = = = LVCMOS LVPECL LVDS HCSL CLK1 Output Format: 0 1 2 3 4 = = = = = OFF LVCMOS LVPECL LVDS HCSL CLK0 Output Format: 1 2 3 4 = = = = LVCMOS LVPECL LVDS HCSL Frequency Code: Qxxxx = This code is assigned by the factory. See the table in this section for more information. Package: K = 20-Pin QFN Temperature Range: E I = = –20°C to +70°C –40°C to +85°C Stability: 1 2 = = ±50 ppm ±25 ppm Packing: T = Tape & Reel 1.0 X CLK3 CLK2 CLK1 CLK0 Freq. Package Temp. Stability Packing Output Output Output Output Code Range Format Format Format Format b) DSC400-4132QxxxxKI2T: Configurable Four Output, Low Jitter Crystal-less Clock Generator; HCSL CLK3; LVCMOS CLK2; LVDS CLK1; LVPECL CLK0; Frequency Code; 20Pin QFN; –40°C to +85°C Temp. Range; ±25 ppm Stability; Tape & Reel c) DSC400-0202QxxxxKE2T: Configurable Four Output, Low Jitter Crystal-less Clock Generator; OFF CLK3; LVPECL CLK2; OFF CLK1; LVPECL CLK0; Frequency Code; 20-Pin QFN; –20°C to +70°C Temp. Range; ±25 ppm Stability; Tape & Reel d) DSC400-1111QxxxxKI1T: Configurable Four Output, Low Jitter Crystal-less Clock Generator; LVCMOS CLK3 through CLK0; Frequency Code; 20-Pin QFN; –40°C to +85°C Temp. Range; ±50 ppm Stability; Tape & Reel FACTORY CONFIGURATION CODE ASSIGNMENT OF QXXXX The DSC400 is meant for customers to define their own frequency requirements at the four available outputs. The Qxxxx number identifies these specific customer requirements and is assigned by the factory. TABLE 1-1: EXAMPLE OF HOW FSB1 & FSB2 ARE APPLIED & THE QXXXX ASSIGNMENT Outputs Bank1 2016 Microchip Technology Inc. Qxxxx Number 1 (default) 0 CLK0 125 MHz 150 MHz CLK3 50 MHz Outputs Bank2 FSB1 25 MHz Q0001 FSB2 1 (default) 0 CLK1 156.25 MHz 100 MHz CLK2 156.25 MHz 100 MHz DS20005612A-page 17 DSC400 NOTES: DS20005612A-page 18 2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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