SPANSION MB9BFD17S This document states the current technical specifications regarding Datasheet

The following document contains information on Cypress products.
MB9BD10T Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BFD16S/T, MB9BFD17S/T, MB9BFD18S/T
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9BD10T-DS706-00031
CONFIDENTIAL
Revision 2.0
Issue Date February 10, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
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The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
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“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
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disclaimer on the first page refers the reader to the notice on this page.
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When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
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those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
CONFIDENTIAL
MB9BD10T Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9BFD16S/T, MB9BFD17S/T, MB9BFD18S/T
Data Sheet (Full Production)
 Description
The MB9BD10T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs, and Communication Interfaces (USB, CAN,
UART, CSIO, I2C, LIN, Ethernet-MAC).
The products which are described in this data sheet are placed into TYPE2 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9BD10T-DS706-00031
Revision 2.0
Issue Date February 10, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 Features
 32-bit ARM Cortex-M3 Core




Processor version: r2p1
Up to 144MHz Frequency Operation
Memory Protection Unit (MPU): improves the reliability of an embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
 24-bit System timer (Sys Tick): System timer for OS task management
 On-chip Memories
[Flash memory]
 Up to 1Mbyte
 Built-in Flash Accelerator System with 16Kbyte trace buffer memory
The read access to Flash memory can be achieved without wait cycle up to operation frequency of
72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory can
be obtained by Flash Accelerator System.
 Security function for code protection
[SRAM]
This Series contain a total of up to 128Kbyte on-chip SRAM. This is composed of two independent SRAM
(SRAM0, SRAM1) . SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is
connected to System bus.
 SRAM0 : Up to 64 Kbyte
 SRAM1 : Up to 64 Kbyte
 USB Interface (Max 2 channels)
USB interface is composed of Function and Host.
PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main
clock.
[USB function]
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
 EndPoint 0 is control transfer
 EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer
 EndPoint 3 to 5 can be selected Bulk-transfer or Interrupt-transfer
 EndPoint 1 to 5 is comprised Double Buffer
 EndPoint 0, 2 to 5:64 bytes
 EndPoint 1: 256 bytes
[USB host]
 USB2.0 Full/Low-speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer support
 USB Device connected/dis-connected automatically detect
 IN/OUT token handshake packet automatically
 Max 256-byte packet-length supported
 Wake-up function supported
 CAN Interface (Max 2 channels)
 Compatible with CAN Specification 2.0A/B
 Maximum transfer rate: 1 Mbps
 Built-in 32 message buffer
2
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Ethernet - MAC (Max 2 channels)
 Compliant with IEEE802.3 specification
 10 Mbps / 100 Mbps data transfer rates supported
 MII/RMII for external PHY device supported.
 MII: Max 1channel
 RMII: Max 2channels
 Full-Duplex and Half-Duplex mode supported.
 Wake-ON-LAN supported
 Built-in dedicated descriptor-system DMAC
 Built-in 2 Kbyte Transmit FIFO and 2 Kbyte Receive FIFO.
 Compliant IEEE1558-2008 (PTP)
PLL for USB/Ethernet is built-in, USB clock or Ethernet clock can be generated by multiplication of Main
clock.
 Multi-function Serial Interface (Max 8 channels)
 4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
 Operation mode is selectable from the followings for each channel.
 UART
 CSIO
 LIN
 I2C
[UART]
 Full-duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
 Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
 Full-duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detect function available
[LIN]
 LIN protocol Rev.2.1 supported
 Full-duplex double buffer
 Master/Slave mode supported
 LIN break field generate (can be changed 13 to 16-bit length)
 LIN break delimiter generate (can be changed 1 to 4-bit length)
 Various error detect functions available (parity errors, framing errors, and overrun errors)
2
[I C]
Standard-mode (Max 100kbps) / Fast-mode (Max 400kbps) supported
 External Bus Interface







Supports SRAM, NOR and NAND Flash device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY input
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
3
D a t a S h e e t
 DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
 8 independently configured and operated channels
 Transfer can be started by software or request from the built-in peripherals
 Transfer address area: 32-bit (4 Gbyte)
 Transfer mode: Block transfer/Burst transfer/Demand transfer
 Transfer data type: byte/half-word/word
 Transfer block count: 1 to 16
 Number of transfers: 1 to 65536
 A/D Converter (Max 32 channels)
[12-bit A/D Converter]
 Successive Approximation Register type
 Built-in 3unit
 Conversion time: 1.0 μs@ 5 V
 Priority conversion available (priority at 2levels)
 Scanning conversion mode
 Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
 Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each channel.




16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
 Multi-function Timer (Max 3units)
The Multi-function timer is composed of the following blocks.






16-bit free-run timer × 3ch./unit
Input capture × 4ch./unit
Output compare × 6ch./unit
A/D activation compare × 3ch./unit
Waveform generator × 3ch./unit
16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.






PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
 Quadrature Position/Revolution Counter (QPRC) (Max 3 channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.




The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
4
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
 Free-running
 Periodic (=Reload)
 One-shot
 Watch Counter
The Watch counter is used for wake up from Low Power Consumption mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
 Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, ”Hardware"
watchdog is active in any power saving mode except STOP mode.
 General Purpose I/O Port
This series can use its pins as General Purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.





Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 154 fast General Purpose I/O Ports@176 pin Package
Some pin is 5V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
 External Interrupt Controller Unit
 Up to 32 external interrupt input pin
 Include one non-maskable interrupt (NMI)
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
5
D a t a S h e e t
 Clock and Reset
[Clocks]
Five clock sources (2 external oscillator, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.





Main Clock
Sub Clock
High-speed internal CR Clock
Low-speed internal CR Clock
Main PLL Clock
: 4 MHz to 50 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
[Resets]
 Reset requests from INITX pin
 Power on reset
 Software reset
 Watchdog timers reset
 Low-voltage detector reset
 Clock supervisor reset
 Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
 External OSC clock failure (clock stop) is detected, reset is asserted.
 External OSC frequency anomaly is detected, interrupt or reset is asserted.
 Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low Power Mode
Three Low Power Consumption modes supported.
 SLEEP
 TIMER
 STOP
 Debug
 Serial Wire JTAG Debug Port (SWJ-DP)
 Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
 Power Supply
Four Power Supplies
 Wide range voltage
 I/O voltage for USB ch.0
 I/O voltage for USB ch.1
 I/O voltage for Ethernet
6
CONFIDENTIAL
: VCC
= 2.7 V to 5.5 V
: USBVCC0 = 3.0 V to 3.6 V (when USB ch.0 is used)
= 2.7 V to 5.5 V (when GPIO is used)
: USBVCC1 = 3.0 V to 3.6 V (when USB ch.1 is used)
= 2.7 V to 5.5 V (when GPIO is used)
:ETHVCC
= 3.0 V to 5.5 V (when Ethernet is used)
= 2.7 V to 5.5 V (when GPIO is used)
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Product Lineup
 Memory size
Product name
MB9BFD16S
MB9BFD16T
MB9BFD17S
MB9BFD17T
MB9BFD18S
MB9BFD18T
On-chip Flash memory
On-chip RAM
512 Kbyte
64 Kbyte
768 Kbyte
96 Kbyte
1 Mbyte
128 Kbyte
 Function
MB9BFD16S
MB9BFD17S
MB9BFD18S
Product name
Pin count
CPU
MB9BFD16T
MB9BFD17T
MB9BFD18T
144
Freq.
Power supply voltage range
USB2.0 (Function/Host)
CAN
Ethernet-MAC
DMAC
External Bus Interface
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
176/192
Cortex-M3
144MHz
VCC: 2.7V to 5.5V
(USBVCC0: 3.0V to 3.6V)
(USBVCC1: 3.0V to 3.6V)
(ETHVCC: 3.0V to 5.5V)
2ch. (Max)
2ch. (Max)
2ch.(Max) MII: 1ch. / RMII: 2ch.(Max)
8ch.
Addr: 19-bit (Max)
Addr: 25-bit (Max)
R/Wdata: 8-/16-bit (Max)
R/Wdata :8-/16-bit (Max)
CS: 8 (Max)
CS: 8 (Max)
Support: SRAM, NOR & NAND
Support: SRAM, NOR & NAND
Flash
Flash
8ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Base Timer
16ch.(Max)
(PWC/ Reload timer/PWM/PPG)
A/D activation
3ch.
compare
Input capture
4ch.
Free-run timer
3ch.
MF3 units (Max)
Timer Output compare
6ch.
Waveform
3ch.
generator
PPG
3ch.
QPRC
3ch. (Max)
Dual Timer
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog timer
1ch. (SW) + 1ch. (HW)
External Interrupts
32pins (Max)+ NMI × 1
I/O ports
122 pins (Max)
154 pins (Max)
12-bit A/D converter
24ch. (3 units)
32ch. (3 units)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz
Built-in
CR
Low-speed
100 kHz
Debug Function
SWJ-DP/ETM
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the General I/O port according to your function use.
See " Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics" for
accuracy of built-in CR.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
7
D a t a S h e e t
 Packages
Product name
Package
LQFP: FPT-144P-M08 (0.5mm pitch)
LQFP: FPT-176P-M07 (0.5mm pitch)
BGA: BGA-192P-M06 (0.8mm pitch)
MB9BFD16S
MB9BFD17S
MB9BFD18S
MB9BFD16T
MB9BFD17T
MB9BFD18T

-


: Supported
Note : See "Package Dimensions" for detailed information on each package
8
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Pin Assignment
 FPT-176P-M07
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
P90/TIOB08_0/RTO20_1/INT30_0/MAD19_0
P91/TIOB09_0/RTO21_1/INT31_0/MAD20_0
P92/TIOB10_0/RTO22_1/SIN5_1/MAD21_0
P93/TIOB11_0/RTO23_1/SOT5_1/MAD22_0
P94/TIOB12_0/RTO24_1/SCK5_1/INT26_0/MAD23_0
P95/TIOB13_0/RTO25_1/INT27_0/MAD24_0
PC0/E_RXER0_RXDV1
PC1/E_RX03_RX11
PC2/E_RX02_RX10
PC3/E_RX01/TIOA06_1
PC4/E_RX00/TIOA08_2
PC5/E_RXDV0/TIOA10_2
PC6/E_MDIO0/TIOA14_0
PC7/E_MDC0/CROUT_1
PC8/E_RXCK0_REFCK
PC9/E_COL0
PCA/E_CRS0
ETHVCC
VSS
PCB/E_COUT
PCC/E_MDIO1
PCD/E_TCK0_MDC1
PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2/UHCONX0
P60/SIN5_0/TIOA02_2/INT15_1
PF3/TIOA06_0/SIN6_2/INT06_0/AIN2_1
PF4/TIOB06_0/SOT6_2/INT07_0/BIN2_1
PF5/SCK6_2/INT08_0/ZIN2_1
USBVCC0
P80/UDM0
P81/UDP0
VCC
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
(TOP VIEW)
VCC
1
132
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
131
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
130
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
129
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
128
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
6
127
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
7
126
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
125
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
124
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
123
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
122
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
121
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
120
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
119
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
118
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
117
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
116
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
115
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
114
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
113
PB3/AN19/TIOB10_1/INT19_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
112
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
22
111
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
23
110
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
109
VSS
P5C/TIOA06_2/INT28_0/IC20_1
25
108
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
26
107
AVRH
VSS
27
106
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
28
105
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
29
104
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
30
103
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
31
102
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P34/FRCK0_0/TIOB04_1/TX0_1
32
101
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P35/IC03_0/TIOB05_1/RX0_1/INT08_1
33
100
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
34
99
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
35
98
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
36
97
P17/AN07/SIN2_2/INT04_1/MAD03_0
P39/DTTI0X_0/ADTG_2
37
96
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
38
95
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
39
94
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
40
93
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
41
92
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
P3E/RTO04_0/TIOA04_1
42
91
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
43
90
P10/AN00/MCSX7_0
VSS
44
89
VCC
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P70/TX0_0/TIOA04_2/MADATA05_0
P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P7A/ZIN1_0/INT24_1/MADATA15_0
P7B/TIOB07_0/INT10_0
P7C/TIOA07_0/INT11_0
P7D/TIOA14_1/FRCK2_1/INT12_0
P7E/TIOB14_1/IC21_1/INT24_0
P7F/TIOA15_1/IC22_1/INT25_0
PF0/TIOB15_1/SIN1_2/INT13_0/IC23_1
PF1/TIOA08_1/SOT1_2/INT14_0
PF2/TIOB08_1/SCK1_2/INT15_0
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
56
P47/X1A
61
55
P46/X0A
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
54
VCC
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
53
VSS
60
52
C
59
51
P45/TIOA05_0/RTO15_1
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
50
P44/TIOA04_0/RTO14_1
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
49
P43/TIOA03_0/RTO13_1/ADTG_7
58
48
P42/TIOA02_0/RTO12_1
57
47
INITX
46
P41/TIOA01_0/RTO11_1/INT13_1
P48/DTTI1X_1/INT14_1/SIN3_2
45
VCC
P40/TIOA00_0/RTO10_1/INT12_1
LQFP - 176
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at
I/O mode 1 (timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
9
D a t a S h e e t
 FPT-144P-M08
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
PC0/E_RXER0_RXDV1
PC1/E_RX03_RX11
PC2/E_RX02_RX10
PC3/E_RX01/TIOA06_1
PC4/E_RX00/TIOA08_2
PC5/E_RXDV0/TIOA10_2
PC6/E_MDIO0/TIOA14_0
PC7/E_MDC0/CROUT_1
PC8/E_RXCK0_REFCK
PC9/E_COL0
PCA/E_CRS0
ETHVCC
VSS
PCB/E_COUT
PCC/E_MDIO1
PCD/E_TCK0_MDC1
PCE/E_TXER0_TXEN1/RTS4_0/TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/INT30_1
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
P61/SOT5_0/TIOB02_2/UHCONX0
P60/SIN5_0/TIOA02_2/INT15_1
PF5/SCK6_2/INT08_0/ZIN2_1
USBVCC0
P80/UDM0
P81/UDP0
VCC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
(TOP VIEW)
VCC
1
108
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
2
107
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
106
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
105
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
104
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
6
103
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
7
102
P21/SIN0_0/INT06_1/BIN1_1
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
8
101
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
9
100
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P07/TRACED2/ADTG_0/SCK4_2
10
99
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P08/TRACED3/TIOA00_2/CTS4_2
11
98
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
12
97
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
13
96
P27/AN26/INT02_2/RTO04_1/MAD14_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
14
95
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
15
94
P29/AN24/MAD12_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
16
93
VSS
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
17
92
AVSS
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
18
91
AVRH
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
19
90
AVCC
LQFP - 144
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
20
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
21
88
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
22
87
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
23
86
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
24
85
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
71
72
VSS
PE3/X1
70
PE2/X0
68
69
MD0
PE0/MD1
P7A/ZIN1_0/INT24_1/MADATA15_0
P78/AIN1_0/TIOA15_0/MADATA13_0
P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0
P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0
P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0
P75/SIN3_0/ADTG_8/INT07_1/MADATA10_0
P74/SCK2_0/ZIN2_0/MADATA09_0
P73/SOT2_0/INT15_2/BIN2_0/MADATA08_0
P72/SIN2_0/INT14_2/AIN2_0/MADATA07_0
P70/TX0_0/TIOA04_2/MADATA05_0
P71/RX0_0/INT13_2/TIOB04_2/MADATA06_0
P4E/TIOB05_0/INT06_2/SIN7_1/ZIN1_2/MADATA04_0
P4D/TIOB04_0/FRCK1_1/SOT7_1/BIN1_2/MADATA03_0
P4C/TIOB03_0/IC13_1/SCK7_1/AIN1_2/MADATA02_0
P4B/TIOB02_0/IC12_1/ZIN0_1/MADATA01_0
P4A/TIOB01_0/IC11_1/BIN0_1/SCK3_2/MADATA00_0
P49/TIOB00_0/IC10_1/AIN0_1/SOT3_2
P48/DTTI1X_1/INT14_1/SIN3_2
INITX
P47/X1A
P46/X0A
VCC
C
VSS
P45/TIOA05_0/RTO15_1
P44/TIOA04_0/RTO14_1
P43/TIOA03_0/RTO13_1/ADTG_7
P42/TIOA02_0/RTO12_1
P41/TIOA01_0/RTO11_1/INT13_1
VCC
P40/TIOA00_0/RTO10_1/INT12_1
67
VCC
66
73
65
36
64
P10/AN00/MCSX7_0
VSS
63
74
62
35
61
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P3F/RTO05_0/TIOA05_1
60
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
75
59
76
34
58
33
P3E/RTO04_0/TIOA04_1
57
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P3D/RTO03_0/TIOA03_1
56
77
55
32
54
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P3C/RTO02_0/TIOA02_1
53
78
52
31
51
P15/AN05/SOT0_1/IC03_2/MAD01_0
P3B/RTO01_0/TIOA01_1
50
79
49
30
48
P16/AN06/SCK0_1/INT20_1/MAD02_0
P3A/RTO00_0/TIOA00_1
47
P17/AN07/SIN2_2/INT04_1/MAD03_0
80
46
81
29
45
28
P39/DTTI0X_0/ADTG_2
44
P18/AN08/SOT2_2/INT21_1/MAD04_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
43
82
42
27
41
P19/AN09/SCK2_2/INT22_1/MAD05_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
40
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
83
39
84
26
38
25
37
VSS
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
TIOA09_0 and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O mode 1
(timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.
10
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 BGA-192P-M06
(TOP VIEW)
1
A
2
3
UDP0 UDM0
4
5
6
7
8
9
USB
ETH
VSS PCD PCB VSS VCC
VCC0
10
11
12
13
14
PC8 VSS TCK VCC
B
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
C
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90
D
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 UDM1
E
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 VCC1
F
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
G
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
H
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
J
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
K
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
L
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
M
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
N
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
TRSTX
VSS
TDI PF6 UDP1
USB
P
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS
X0
X1
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at
I/O mode 1 (timer full mode) of the Base Timer. See "●Base Timer" in "Handling Devices" for details.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
11
D a t a S h e e t
 List of Pin Functions
 List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
LQFP-176
1
Pin No
LQFP-144
1
BGA-192
C1
2
2
B2
3
3
C2
4
4
C3
5
5
D5
6
6
D2
7
7
D1
8
8
D3
Pin Name
VCC
PA0
RTO20_0
TIOA08_0
FRCK1_0
PA1
RTO21_0
TIOA09_0
IC10_0
PA2
RTO22_0
TIOA10_0
IC11_0
PA3
RTO23_0
TIOA11_0
IC12_0
PA4
RTO24_0
TIOA12_0
RX0_2
IC13_0
INT03_0
PA5
RTO25_0
TX0_2
TIOA13_0
INT10_2
P05
TRACED0
TIOA05_2
SIN4_2
I/O circuit
type
Pin state
type
-
G
I
G
I
G
I
G
I
G
H
G
H
E
F
E
F
INT00_1
9
12
CONFIDENTIAL
9
D4
P06
TRACED1
TIOB05_2
SOT4_2
INT01_1
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
10
10
E2
11
11
E3
12
12
E4
13
13
E5
14
14
F1
15
15
F2
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin Name
P07
TRACED2
ADTG_0
SCK4_2
P08
TRACED3
TIOA00_2
CTS4_2
P09
TRACECLK
TIOB00_2
RTS4_2
DTTI2X_0
P50
INT00_0
AIN0_2
SIN3_1
RTO10_0
IC20_0
MOEX_0
P51
INT01_0
BIN0_2
SOT3_1
RTO11_0
IC21_0
MWEX_0
P52
INT02_0
ZIN0_2
SCK3_1
RTO12_0
IC22_0
MDQM0_0
I/O circuit
type
Pin state
type
E
G
E
G
E
G
E
H
E
H
E
H
13
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
16
16
F3
17
17
F4
18
18
F5
19
19
F6
20
20
G2
21
21
G3
22
22
G4
14
CONFIDENTIAL
Pin Name
P53
SIN6_0
TIOA01_2
INT07_2
RTO13_0
IC23_0
MDQM1_0
P54
SOT6_0
TIOB01_2
RTO14_0
MALE_0
P55
SCK6_0
ADTG_1
RTO15_0
MRDY_0
P56
SIN1_0
INT08_2
TIOA09_2
DTTI1X_0
MNALE_0
P57
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
RX1_1
TIOB11_2
INT09_2
MNREX_0
I/O circuit
type
Pin State
type
E
H
E
I
E
I
E
H
E
H
E
H
E
H
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
23
23
G5
24
24
G6
25
-
H1
26
-
H2
27
25
J1
28
-
H3
29
-
H4
30
-
H5
31
-
H6
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P5A
SOT7_0
TX1_1
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
TIOA06_2
INT28_0
IC20_1
P5D
TIOB06_2
INT29_0
DTTI2X_1
VSS
P30
AIN0_0
TIOB00_1
INT03_2
P31
BIN0_0
TIOB01_1
SCK6_1
INT04_2
P32
ZIN0_0
TIOB02_1
SOT6_1
INT05_2
P33
INT04_0
TIOB03_1
SIN6_1
ADTG_6
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
-
E
H
E
H
E
H
E
H
15
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
32
-
J5
33
-
J4
34
26
J3
35
27
J2
36
28
K1
37
29
K2
38
30
K3
39
31
K4
Pin name
P34
FRCK0_0
TX0_1
TIOB04_1
P35
IC03_0
RX0_1
TIOB05_1
INT08_1
P36
IC02_0
SIN5_2
INT09_1
TIOA12_2
MCSX2_0
P37
IC01_0
SOT5_2
INT10_1
TIOB12_2
MCSX3_0
P38
IC00_0
SCK5_2
INT11_1
MCLKOUT_0
P39
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA00_1
P3B
RTO01_0
I/O circuit
type
Pin state
type
E
I
E
H
E
H
E
H
E
H
E
I
G
I
G
I
G
I
TIOA01_1
40
16
CONFIDENTIAL
32
L1
P3C
RTO02_0
TIOA02_1
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
41
33
L2
42
34
L3
43
35
M2
44
45
36
37
M1
N1
46
38
N2
47
39
N3
48
40
M3
49
41
L4
50
42
M4
51
43
N4
52
53
54
44
45
46
P2
P3
P4
55
47
P5
56
48
P6
57
49
N5
58
50
M5
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P3D
RTO03_0
TIOA03_1
P3E
RTO04_0
TIOA04_1
P3F
RTO05_0
TIOA05_1
VSS
VCC
P40
TIOA00_0
RTO10_1
INT12_1
P41
TIOA01_0
RTO11_1
INT13_1
P42
TIOA02_0
RTO12_1
P43
TIOA03_0
RTO13_1
ADTG_7
P44
TIOA04_0
RTO14_1
P45
TIOA05_0
RTO15_1
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
DTTI1X_1
INT14_1
SIN3_2
I/O circuit
type
Pin state
type
G
I
G
I
G
I
-
G
H
G
H
G
I
G
I
G
I
G
I
-
D
M
D
N
B
C
E
H
17
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
59
51
L5
60
52
K5
61
53
N6
62
54
M6
63
55
L6
64
56
K6
65
57
J6
66
58
N8
18
CONFIDENTIAL
Pin name
P49
TIOB00_0
IC10_1
AIN0_1
SOT3_2
P4A
TIOB01_0
IC11_1
BIN0_1
SCK3_2
MADATA00_0
P4B
TIOB02_0
IC12_1
ZIN0_1
MADATA01_0
P4C
TIOB03_0
IC13_1
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
FRCK1_1
SOT7_1
BIN1_2
MADATA03_0
P4E
TIOB05_0
INT06_2
SIN7_1
ZIN1_2
MADATA04_0
P70
TIOA04_2
TX0_0
MADATA05_0
P71
INT13_2
TIOB04_2
RX0_0
MADATA06_0
I/O circuit
type
Pin state
type
E
I
E
I
E
I
E
I
E
I
E
H
E
I
E
H
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
67
59
M8
68
60
L8
69
61
K8
70
62
P8
71
63
J8
72
64
P9
73
65
N9
74
66
M9
-
-
E1
G1
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P72
SIN2_0
INT14_2
AIN2_0
MADATA07_0
P73
SOT2_0
INT15_2
BIN2_0
MADATA08_0
P74
SCK2_0
ZIN2_0
MADATA09_0
P75
SIN3_0
ADTG_8
INT07_1
MADATA10_0
P76
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P78
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
VSS
I/O circuit
type
Pin state
type
E
H
E
H
E
I
E
H
E
H
E
H
E
I
E
H
-
19
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
75
67
L9
76
-
K9
77
-
P10
78
-
N10
79
-
L10
80
-
K10
81
-
M10
82
-
N11
83
-
M11
84
68
N13
85
69
N12
86
70
P12
87
71
P13
88
89
-
72
73
-
N14
M14
L7
K7
20
CONFIDENTIAL
Pin name
P7A
ZIN1_0
INT24_1
MADATA15_0
P7B
TIOB07_0
INT10_0
P7C
TIOA07_0
INT11_0
P7D
TIOA14_1
FRCK2_1
INT12_0
P7E
TIOB14_1
IC21_1
INT24_0
P7F
TIOA15_1
IC22_1
INT25_0
PF0
TIOB15_1
SIN1_2
INT13_0
IC23_1
PF1
TIOA08_1
SOT1_2
INT14_0
PF2
TIOB08_1
SCK1_2
INT15_0
PE0
MD1
MD0
PE2
X0
PE3
X1
VSS
VCC
VSS
VSS
I/O circuit
type
Pin state
type
E
H
E
H
E
H
E
H
E
H
E
H
I*
H
I*
H
I*
H
C
P
J
D
A
A
A
B
-
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
90
74
M13
91
75
M12
92
76
L13
93
77
L12
94
78
L11
95
79
K13
96
80
K12
97
81
K14
-
-
P7
P11
L14
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P10
AN00
MCSX7_0
P11
AN01
SIN1_1
RX1_2
INT02_1
FRCK0_2
MCSX6_0
P12
AN02
SOT1_1
TX1_2
IC00_2
MCSX5_0
P13
AN03
SCK1_1
IC01_2
MCSX4_0
P14
AN04
SIN0_1
INT03_1
IC02_2
MAD00_0
P15
AN05
SOT0_1
IC03_2
MAD01_0
P16
AN06
SCK0_1
INT20_1
MAD02_0
P17
AN07
SIN2_2
INT04_1
MAD03_0
VSS
VSS
VSS
I/O circuit
type
Pin state
type
F
K
F
L
F
K
F
K
F
L
F
K
F
L
F
L
-
21
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
Pin name
I/O circuit
type
Pin state
type
F
L
F
L
F
L
F
L
F
L
F
L
F
L
P18
AN08
98
82
K11
99
83
J13
100
84
J12
101
85
J11
102
86
J10
103
87
J9
SOT2_2
INT21_1
MAD04_0
P19
AN09
SCK2_2
INT22_1
MAD05_0
P1A
AN10
SIN4_1
INT05_1
TIOA13_2
IC00_1
MAD06_0
P1B
AN11
SOT4_1
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
AN12
SCK4_1
INT26_1
TIOA14_2
IC02_1
MAD08_0
P1D
AN13
CTS4_1
INT27_1
TIOB14_2
IC03_1
MAD09_0
P1E
104
22
CONFIDENTIAL
88
H10
AN14
RTS4_1
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
105
89
H9
106
107
108
109
90
91
92
93
J14
H14
G14
F14
110
-
H13
111
-
H12
112
-
H11
113
-
G13
114
-
G12
115
-
G11
-
-
G7
J7
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P1F
AN15
ADTG_5
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
AVCC
AVRH
AVSS
VSS
PB0
AN16
TIOA09_1
SIN7_2
INT16_0
PB1
AN17
TIOB09_1
SOT7_2
INT17_0
PB2
AN18
TIOA10_1
SCK7_2
INT18_0
PB3
AN19
TIOB10_1
INT19_0
PB4
AN20
TIOA11_1
SIN0_2
INT20_0
PB5
AN21
TIOB11_1
SOT0_2
INT21_0
AIN2_2
VSS
VSS
I/O circuit
type
Pin state
type
F
L
-
F
L
F
L
F
L
F
L
F
L
F
L
-
23
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
116
-
G10
117
-
G9
118
94
F10
119
95
F11
120
96
F12
121
97
F13
122
98
E10
123
99
E11
24
CONFIDENTIAL
Pin name
PB6
AN22
TIOA12_1
SCK0_2
INT22_0
BIN2_2
PB7
AN23
TIOB12_1
INT23_0
ZIN2_2
P29
AN24
MAD12_0
P28
AN25
ADTG_4
INT09_0
RTO05_1
MAD13_0
P27
AN26
INT02_2
RTO04_1
MAD14_0
P26
AN27
SCK2_1
RTO03_1
MAD15_0
P25
AN28
SOT2_1
TX1_0
RTO02_1
MAD16_0
P24
AN29
SIN2_1
RX1_0
INT01_2
RTO01_1
MAD17_0
I/O circuit
type
Pin state
type
F
L
F
L
F
K
F
L
F
L
F
K
F
K
F
L
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
124
100
E12
125
101
E13
126
102
D12
127
103
D13
128
104
C13
129
105
E14
130
106
D14
131
107
C14
132
133
108
109
B14
A13
134
110
B13
135
111
A12
136
112
C12
137
113
B12
138
114
B11
139
-
C11
-
-
A8
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
P23
AN30
SCK0_0
TIOA07_1
RTO00_1
P22
AN31
SOT0_0
TIOB07_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
P20
INT05_0
CROUT_0
UHCONX1
AIN1_1
MAD18_0
PF6
FRCK2_0
NMIX
USBVCC1
P82
UDM1
P83
UDP1
VSS
VCC
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
TDO
SWO
P90
TIOB08_0
RTO20_1
INT30_0
MAD19_0
VSS
I/O circuit
type
Pin state
type
F
K
F
K
E
H
E
H
I*
J
-
H
O
H
O
-
E
E
E
E
E
E
E
E
E
E
E
H
25
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
140
-
D11
141
-
B10
142
-
C10
143
-
D10
144
-
B9
145
115
C9
146
116
B8
147
117
D9
148
118
E9
149
119
F9
150
120
C8
-
-
A5
26
CONFIDENTIAL
Pin name
P91
TIOB09_0
RTO21_1
INT31_0
MAD20_0
P92
TIOB10_0
RTO22_1
SIN5_1
MAD21_0
P93
TIOB11_0
RTO23_1
SOT5_1
MAD22_0
P94
TIOB12_0
RTO24_1
SCK5_1
INT26_0
MAD23_0
P95
TIOB13_0
RTO25_1
INT27_0
MAD24_0
PC0
E_RXER0_RXDV1
PC1
E_RX03_RX11
PC2
E_RX02_RX10
PC3
E_RX01
TIOA06_1
PC4
E_RX00
TIOA08_2
PC5
E_RXDV0
TIOA10_2
VSS
I/O circuit
type
Pin state
type
E
H
E
I
E
I
E
H
E
H
K
Q
K
Q
K
Q
K
Q
K
Q
K
Q
-
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
151
121
D8
152
122
E8
153
123
A10
154
124
F8
155
125
B7
156
157
126
127
A9
A11
158
128
A7
159
129
C7
160
130
A6
161
131
D7
162
132
E7
163
133
F7
164
134
B6
-
-
N7
G8
H7
H8
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin name
PC6
E_MDIO0
TIOA14_0
PC7
E_MDC0
CROUT_1
PC8
E_RXCK0_REFCK
PC9
E_COL0
PCA
E_CRS0
ETHVCC
VSS
PCB
E_COUT
PCC
E_MDIO1
PCD
E_TCK0_MDC1
PCE
E_TXER0_TXEN1
RTS4_0
TIOB06_1
PCF
E_TX03_TX11
CTS4_0
TIOB08_2
PD0
E_TX02_TX10
SCK4_0
TIOB10_2
INT30_1
PD1
E_TX01
SOT4_0
TIOB14_0
INT31_1
VSS
VSS
VSS
VSS
I/O circuit
type
Pin state
type
K
Q
L
Q
K
Q
K
Q
K
Q
-
L
Q
K
Q
K
Q
L
Q
L
Q
L
R
L
R
-
27
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
165
135
C6
166
136
D6
167
137
E6
168
138
B5
169
139
C5
170
-
B4
171
-
C4
172
140
B3
173
141
A4
174
142
A3
175
143
A2
144
-
B1
M7
176
*
: 5V tolerant I/O
28
CONFIDENTIAL
Pin name
PD2
E_TX00
SIN4_0
TIOA03_2
INT00_2
PD3
E_TXEN0
TIOB03_2
P62
E_PPS0_PPS1
SCK5_0
ADTG_3
P61
SOT5_0
TIOB02_2
UHCONX0
P60
SIN5_0
TIOA02_2
INT15_1
PF3
TIOA06_0
SIN6_2
INT06_0
AIN2_1
PF4
TIOB06_0
SOT6_2
INT07_0
BIN2_1
PF5
SCK6_2
INT08_0
ZIN2_1
USBVCC0
P80
UDM0
P81
UDP0
VSS
VSS
I/O circuit
type
Pin state
type
L
R
L
Q
E
Q
E
I
E
H
I*
H
I*
H
I*
H
H
O
H
O
-
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port
number. For these pins, there are multiple pins that provide the same function for the same channel. Use the
extended port function register (EPFR) to select the pin.
Module
Pin name
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN31
Function
A/D converter external trigger input
pin
A/D converter analog input pin
(ANxx describes ADC ch.xx)
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
10
18
37
167
119
105
31
49
70
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
10
18
29
137
95
89
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
100
101
E2
F5
K2
E6
F11
H9
H6
L4
P8
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
H13
H12
H11
G13
G12
G11
G10
G9
F10
F11
F12
F13
E10
E11
E12
E13
29
D a t a S h e e t
Module
Pin name
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base Timer
5
Base Timer
6
30
CONFIDENTIAL
Function
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
LQFP-176
Pin No
LQFP-144
BGA-192
46
38
11
59
28
12
47
39
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
64
33
9
170
148
25
171
161
26
38
30
11
51
12
39
31
16
52
17
40
32
139
53
138
41
33
135
54
136
42
34
57
55
58
43
35
8
56
9
118
131
-
N2
K3
E3
L5
H3
E4
N3
K4
F3
K5
H4
F4
M3
L1
C5
N6
H5
B5
L4
L2
C6
M6
H6
D6
M4
L3
J6
L6
J5
N8
N4
M2
D3
K6
J4
D4
B4
E9
H1
C4
D7
H2
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
Base Timer
7
TIOA07_0
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
TIOA08_1
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
Base Timer
8
Base Timer
9
Base Timer
10
Base Timer
11
Base Timer
12
Base Timer
13
Function
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
77
124
71
76
125
72
2
82
149
139
83
162
3
110
19
140
111
20
4
112
150
141
113
163
5
114
21
142
115
22
6
116
34
143
117
35
7
23
100
144
24
101
100
63
101
64
2
119
132
3
19
20
4
120
133
5
21
22
6
26
27
7
23
84
24
85
P10
E12
J8
K9
E13
P9
B2
N11
F9
C11
M11
E7
C2
H13
F6
D11
H12
G2
C3
H11
C8
B10
G13
F7
D5
G12
G3
C10
G11
G4
D2
G10
J3
D10
G9
J2
D1
G5
J12
B9
G6
J11
31
D a t a S h e e t
Module
Pin name
Base Timer
14
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
Base Timer
15
CAN 0
CAN 1
Debugger
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
32
CONFIDENTIAL
Function
Base timer ch.14 TIOA pin
Base timer ch.14 TIOB pin
Base timer ch.15 TIOA pin
Base timer ch.15 TIOB pin
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
CAN interface ch.1 TX output pin
CAN interface ch.1 RX output pin
Serial wire debug interface clock input
pin
Serial wire debug interface data input /
output pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state input/output pin
Trace CLK output pin of ETM
Trace data output pin of ETM
J-TAG test reset input pin
LQFP-176
Pin No
LQFP-144
BGA-192
151
78
102
164
79
103
73
80
104
74
81
105
65
32
7
66
33
6
122
23
92
123
22
91
121
86
134
87
65
88
66
89
57
7
58
6
98
23
76
99
22
75
D8
N10
J10
B6
L10
J9
N9
K10
H10
M9
M10
H9
J6
J5
D1
N8
J4
D2
E10
G5
L13
E11
G4
M12
135
111
A12
137
113
B12
138
135
136
138
137
12
8
9
10
11
134
114
111
112
114
113
12
8
9
10
11
110
B11
A12
C12
B11
B12
E4
D3
D4
E2
E3
B13
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
External
Bus
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
MOEX_0
MWEX_0
Function
External bus interface address bus
External bus interface chip select
output pin
External bus interface byte mask
signal output pin
External bus interface read enable
signal for SRAM
External bus interface write enable
signal for SRAM
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
94
95
96
97
98
99
100
101
102
103
104
105
118
119
120
121
122
123
127
139
140
141
142
143
144
23
24
34
35
93
92
91
90
15
16
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
103
23
24
26
27
77
76
75
74
15
16
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
F10
F11
F12
F13
E10
E11
D13
C11
D11
B10
C10
D10
B9
G5
G6
J3
J2
L12
L13
M12
M13
F2
F3
13
13
E5
14
14
F1
33
D a t a S h e e t
Module
External
Bus
Pin name
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
MALE_0
MRDY_0
MCLKOUT_0
34
CONFIDENTIAL
Function
External bus interface ALE signal to
control NAND Flash output pin
External bus interface CLE signal to
control NAND Flash output pin
External bus interface read enable
signal to control NAND Flash
External bus interface write enable
signal to control NAND Flash
External bus interface data bus
(Address / data multiplex bus)
External bus interface Address Latch
enable output signal for multiplex
External bus interface external RDY
input signal
External bus interface external clock
output pin
LQFP-176
Pin No
LQFP-144
BGA-192
19
19
F6
20
20
G2
22
22
G4
21
21
G3
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
K5
N6
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
17
17
F4
18
18
F5
36
28
K1
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
Function
External interrupt request 00 input
pin
External interrupt request 01 input
pin
External interrupt request 02 input
pin
External interrupt request 03 input
pin
External interrupt request 04 input
pin
External interrupt request 05 input
pin
External interrupt request 06 input
pin
External interrupt request 07 input
pin
External interrupt request 08 input
pin
External interrupt request 09 input
pin
External interrupt request 10 input
pin
External interrupt request 11 input
pin
External interrupt request 12 input
pin
External interrupt request 13 input
pin
External interrupt request 14 input
pin
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
13
8
165
14
9
123
15
91
120
6
94
28
31
97
29
127
100
30
170
126
64
171
70
16
172
33
19
119
34
22
76
35
7
77
36
71
78
46
72
81
47
66
82
58
67
13
8
135
14
9
99
15
75
96
6
78
81
103
84
102
56
62
16
140
19
95
26
22
27
7
28
63
38
64
39
58
50
59
E5
D3
C6
F1
D4
E11
F2
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
D12
K6
C4
P8
F3
B3
J4
F6
F11
J3
G4
K9
J2
D1
P10
K1
J8
N10
N2
P9
M10
N3
N8
N11
M5
M8
35
D a t a S h e e t
Module
Pin name
External
Interrupt
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
36
CONFIDENTIAL
Function
External interrupt request 15 input
pin
External interrupt request 16 input
pin
External interrupt request 17 input
pin
External interrupt request 18 input
pin
External interrupt request 19 input
pin
External interrupt request 20 input
pin
External interrupt request 21 input
pin
External interrupt request 22 input
pin
External interrupt request 23 input
pin
External interrupt request 24 input
pin
External interrupt request 25 input
pin
External interrupt request 26 input
pin
External interrupt request 27 input
pin
External interrupt request 28 input
pin
External interrupt request 29 input
pin
External interrupt request 30 input
pin
External interrupt request 31 input
pin
Non-Maskable Interrupt input pin
LQFP-176
Pin No
LQFP-144
BGA-192
83
169
68
110
20
111
21
112
23
113
24
114
96
115
98
116
99
117
74
79
75
80
101
143
102
144
103
25
104
26
105
139
163
140
164
128
139
60
20
21
23
24
80
82
83
66
67
85
86
87
88
89
133
134
104
M11
C5
L8
H13
G2
H12
G3
H11
G5
G13
G6
G12
K12
G11
K11
G10
J13
G9
M9
L10
L9
K10
J11
D10
J10
B9
J9
H1
H10
H2
H9
C11
F7
D11
B6
C13
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
Function
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
134
135
136
137
138
8
9
10
11
12
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
110
111
112
113
114
8
9
10
11
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
B13
A12
C12
B12
B11
D3
D4
E2
E3
E4
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
37
D a t a S h e e t
Module
Pin name
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
38
CONFIDENTIAL
Function
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
LQFP-176
Pin No
LQFP-144
BGA-192
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
H3
H4
H5
H6
J5
J4
J3
J2
K1
K2
K3
K4
L1
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
K5
N6
M6
L6
K6
E5
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
G6
H1
H2
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
GPIO
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Function
General-purpose I/O port 6
General-purpose I/O port 7
General-purpose I/O port 8
General-purpose I/O port 9
General-purpose I/O port A
General-purpose I/O port B
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
Pin No
LQFP-144
BGA-192
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
174
175
130
131
139
140
141
142
143
144
2
3
4
5
6
7
110
111
112
113
114
115
116
117
139
138
137
57
58
59
60
61
62
63
64
65
66
67
142
143
106
107
2
3
4
5
6
7
-
C5
B5
E6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
K9
P10
N10
L10
K10
A3
A2
D14
C14
C11
D11
B10
C10
D10
B9
B2
C2
C3
D5
D2
D1
H13
H12
H11
G13
G12
G11
G10
G9
39
D a t a S h e e t
Module
Pin name
GPIO
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
40
CONFIDENTIAL
Function
General-purpose I/O port C
General-purpose I/O port D
General-purpose I/O port E
General-purpose I/O port F*
LQFP-176
Pin no
LQFP-144
BGA-192
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
86
87
81
82
83
170
171
172
128
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
70
71
140
104
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
C6
D6
N13
P12
P13
M10
N11
M11
B4
C4
B3
C13
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
Multifunction
Serial
0
SIN0_0
SIN0_1
SIN0_2
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SOT0_2
(SDA0_2)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
SCK0_2
(SCL0_2)
SIN1_0
SIN1_1
SIN1_2
SOT1_0
(SDA1_0)
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
SCK1_1
(SCL1_1)
SCK1_2
(SCL1_2)
LQFP-176
Pin No.
LQFP-144
BGA-192
126
94
114
102
78
-
D12
L11
G12
125
101
E13
95
79
K13
115
-
G11
124
100
E12
96
80
K12
116
-
G10
19
91
81
19
75
-
F6
M12
M10
Multi-function serial interface ch.1
output pin.
This pin operates as SOT1 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA1 when it is used in an I2C
(operation mode 4).
20
20
G2
92
76
L13
82
-
N11
Multi-function serial interface ch.1
clock I/O pin.
This pin operates as SCK1 when it is
used in a CSIO (operation mode 2)
and as SCL1 when it is used in an
I2C (operation mode 4).
21
21
G3
93
77
L12
83
-
M11
Function
Multi-function serial interface ch.0
input pin
Multi-function serial interface ch.0
output pin.
This pin operates as SOT0 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA0 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.0
clock I/O pin.
This pin operates as SCK0 when it is
used in a CSIO (operation mode 2)
and as SCL0 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.1
input pin
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
41
D a t a S h e e t
Module
Pin name
Multifunction
Serial
2
SIN2_0
SIN2_1
SIN2_2
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
Multifunction
Serial
3
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
SIN3_1
CONFIDENTIAL
Multi-function serial interface ch.2
input pin
Multi-function serial interface ch.2
output pin.
This pin operates as SOT2 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA2 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.2
clock I/O pin.
This pin operates as SCK2 when it is
used in a CSIO (operation mode 2)
and as SCL2 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.3
input pin
SIN3_2
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
42
Function
SOT3_2
(SDA3_2)
Multi-function serial interface ch.3
output pin.
This pin operates as SOT3 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA3 when it is used in an I2C
(operation mode 4).
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multi-function serial interface ch.3
clock I/O pin.
This pin operates as SCK3 when it is
used in a CSIO (operation mode 2)
and as SCL3 when it is used in an
I2C (operation mode 4).
LQFP-176
Pin No.
LQFP-144
BGA-192
67
123
97
59
99
81
M8
E11
K14
68
60
L8
122
98
E10
98
82
K11
69
61
K8
121
97
F13
99
83
J13
70
62
P8
13
13
E5
58
50
M5
71
63
J8
14
14
F1
59
51
L5
72
64
P9
15
15
F2
60
52
K5
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
Multifunction
Serial
4
SIN4_0
SIN4_1
SIN4_2
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
Multifunction
Serial
5
Function
Multi-function serial interface ch.4
input pin
Multi-function serial interface ch.4
output pin.
This pin operates as SOT4 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA4 when it is used in an I2C
(operation mode 4).
Pin No
LQFP-144
BGA-192
165
100
8
135
84
8
C6
J12
D3
164
134
B6
101
85
J11
9
9
D4
163
133
F7
102
86
J10
10
10
E2
161
104
12
162
103
11
169
141
34
131
88
12
132
87
11
139
26
D7
H10
E4
E7
J9
E3
C5
B10
J3
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_1
SIN5_2
Multi-function serial interface ch.4
clock I/O pin.
This pin operates as SCK4 when it is
used in a CSIO (operation mode 2)
and as SCL4 when it is used in an
I2C (operation mode 4).
SOT5_0
(SDA5_0)
Multi-function serial interface ch.5
output pin.
This pin operates as SOT5 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA5 when it is used in an I2C
(operation mode 4).
168
138
B5
142
-
C10
35
27
J2
Multi-function serial interface ch.5
clock I/O pin.
This pin operates as SCK5 when it is
used in a CSIO (operation mode 2)
and as SCL5 when it is used in an
I2C (operation mode 4).
167
137
E6
143
-
D10
36
28
K1
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
Multi-function serial interface ch.4
RTS output pin
Multi-function serial interface ch.4
CTS input pin
Multi-function serial interface ch.5
input pin
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
43
D a t a S h e e t
Module
Pin name
Multifunction
Serial
6
SIN6_0
SIN6_1
SIN6_2
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SOT6_2
(SDA6_2)
Multifunction
Serial
7
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
SIN7_0
SIN7_1
SIN7_2
SOT7_0
(SDA7_0)
SOT7_1
(SDA7_1)
SOT7_2
(SDA7_2)
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
44
CONFIDENTIAL
Function
Multi-function serial interface ch.6
input pin
Multi-function serial interface ch.6
output pin.
This pin operates as SOT6 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA6 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.6
clock I/O pin.
This pin operates as SCK6 when it is
used in a CSIO (operation mode 2)
and as SCL6 when it is used in an
I2C (operation mode 4).
Multi-function serial interface ch.7
input pin
Multi-function serial interface ch.7
output pin.
This pin operates as SOT7 when it is
used in a UART/CSIO/LIN
(operation modes 0 to 3) and as
SDA7 when it is used in an I2C
(operation mode 4).
Multi-function serial interface ch.7
clock I/O pin.
This pin operates as SCK7 when it is
used in a CSIO (operation mode 2)
and as SCL7 when it is used in an
I2C (operation mode 4).
LQFP-176
Pin No
LQFP-144
BGA-192
16
31
170
16
-
F3
H6
B4
17
17
F4
30
-
H5
171
-
C4
18
18
F5
29
-
H4
172
140
B3
22
64
110
22
56
-
G4
K6
H13
23
23
G5
63
55
L6
111
-
H12
24
24
G6
62
54
M6
112
-
H11
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Pin No
Module
Pin name
Function
Multifunction
Timer
0
DTTI0X_0
Input signal controlling wave form
generator outputs RTO00 to RTO05
of multi-function timer 0.
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
16-bit free-run timer ch.0 external
clock input pin
16-bit input capture ch.0 input pin of
multi-function timer 0.
(ICxx describes chanel number)
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG00 when it
is used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG02 when it
is used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
Wave form generator output pin of
multi-function timer 0.
This pin operates as PPG04 when it
is used in PPG0 output modes.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
LQFP-176
LQFP-144
BGA-192
37
29
K2
104
88
H10
32
105
91
36
100
92
35
101
93
34
102
94
33
103
95
89
75
28
84
76
27
85
77
26
86
78
87
79
J5
H9
M12
K1
J12
L13
J2
J11
L12
J3
J10
L11
J4
J9
K13
38
30
K3
124
100
E12
39
31
K4
123
99
E11
40
32
L1
122
98
E10
41
33
L2
121
97
F13
42
34
L3
120
96
F12
43
35
M2
119
95
F11
45
D a t a S h e e t
Module
Multifunction
Timer
1
CONFIDENTIAL
Pin No
LQFP-144
BGA-192
Input signal controlling wave form
generator outputs RTO10 to RTO15
of multi-function timer 1.
19
19
F6
58
50
M5
16-bit free-run timer ch.1 external
clock input pin
2
63
3
59
4
60
5
61
6
62
2
55
3
51
4
52
5
53
6
54
B2
L6
C2
L5
C3
K5
D5
N6
D2
M6
13
13
E5
46
38
N2
14
14
F1
47
39
N3
15
15
F2
48
40
M3
16
16
F3
49
41
L4
17
17
F4
50
42
M4
18
18
F5
51
43
N4
Function
DTTI1X_0
DTTI1X_1
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
IC13_1
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
46
LQFP-176
Pin name
16-bit input capture ch.1 input pin of
multi-function timer 1.
(ICxx describes chanel number)
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG1 output modes.
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG10 when it
is used in PPG1 output modes.
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG1 output modes.
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG12 when it
is used in PPG1 output modes.
RTO14_1
(PPG14_1)
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG1 output modes.
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output pin of
multi-function timer 1.
This pin operates as PPG14 when it
is used in PPG1 output modes.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Module
Pin name
Function
Multifunction
Timer
2
DTTI2X_0
DTTI2X_1
FRCK2_0
FRCK2_1
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
IC23_0
IC23_1
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
LQFP-144
BGA-192
Input signal controlling wave form
generator outputs RTO20 to RTO25
of multi-function timer 2.
12
12
E4
26
-
H2
16-bit free-run timer ch.2 external
clock input pin
128
78
13
25
14
79
15
80
16
81
104
13
14
15
16
-
C13
N10
E5
H1
F1
L10
F2
K10
F3
M10
2
2
B2
139
-
C11
3
3
C2
140
-
D11
4
4
C3
141
-
B10
5
5
D5
142
-
C10
6
6
D2
143
-
D10
7
7
D1
144
-
B9
16-bit input capture ch.2 input pin of
multi-function timer 2.
(ICxx describes chanel number)
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG20 when it
is used in PPG2 output modes.
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG20 when it
is used in PPG2 output modes.
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG22 when it
is used in PPG2 output modes.
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG22 when it
is used in PPG2 output modes.
RTO24_1
(PPG24_1)
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG24 when it
is used in PPG2 output modes.
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Wave form generator output pin of
multi-function timer 2.
This pin operates as PPG24 when it
is used in PPG2 output modes.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Pin No
LQFP-176
47
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
28
-
H3
59
51
L5
13
13
E5
29
-
H4
60
52
K5
BIN0_2
14
14
F1
ZIN0_0
30
-
H5
Module
Pin name
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
QPRC ch.0 AIN input pin
AIN0_2
BIN0_0
BIN0_1
ZIN0_1
Quadrature
Position/
Revolution
Counter
1
Function
QPRC ch.0 BIN input pin
61
53
N6
ZIN0_2
15
15
F2
AIN1_0
73
65
N9
127
103
D13
AIN1_2
62
54
M6
BIN1_0
74
66
M9
126
102
D12
63
55
L6
AIN1_1
BIN1_1
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
BIN1_2
ZIN1_0
75
67
L9
125
101
E13
ZIN1_2
64
56
K6
AIN2_0
67
59
M8
170
-
B4
ZIN1_1
Quadrature
Position/
Revolution
Counter
2
AIN2_1
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
AIN2_2
115
-
G11
BIN2_0
68
60
L8
171
-
C4
116
-
G10
BIN2_1
QPRC ch.2 BIN input pin
BIN2_2
ZIN2_0
ZIN2_1
QPRC ch.2 ZIN input pin
ZIN2_2
USB0
USB1
48
CONFIDENTIAL
69
61
K8
172
140
B3
117
-
G9
UDM0
USB ch.0 function/host D – pin
174
142
A3
UDP0
USB ch.0 function/host D + pin
175
143
A2
UHCONX0
USB ch.0.
USB external pull-up control pin
168
138
B5
UDM1
USB ch.1 function/host D – pin
130
106
D14
UDP1
USB ch.1 function/host D + pin
131
107
C14
UHCONX1
USB ch.1.
USB external pull-up control pin
127
103
D13
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No
LQFP-144
BGA-192
Ch.0 collision detection
154
124
F8
E_COUT
Clock output pin for EtherPHY
158
128
A7
E_CRS0
Ch.0 carrer detection
155
125
B7
Module
Pin name
Ethernet
E_COL0
Function
E_MDC0
Ch.0 management clock
152
122
E8
E_MDIO0
Ch.0 management data input/output
151
121
D8
E_MDIO1
Ch.1 management data input/output
159
129
C7
Ch.0 PTP counter monitor/
Ch.1 PTP counter monitor
167
137
E6
E_RX00
Ch.0 received data0
149
119
F9
E_RX01
Ch.0 received data1
148
118
E9
E_RX02_RX10
Ch.0 received data2/
Ch.1 received data0
147
117
D9
E_RX03_RX11
Ch.0 received data3/
Ch.1 received data1
146
116
B8
E_RXCK0_REFCK
Ch.0 received clock input/
reference clock
153
123
A10
E_RXDV0
Ch.0 received data enable
150
120
C8
Ch.0 received data error detection/
Ch.1 received data enable
145
115
C9
Ch.0 transition clock input/
Ch.1 mangement clock
160
130
A6
E_TX00
Ch.0 transition data0
165
135
C6
E_TX01
Ch.0 trasition data1
164
134
B6
E_TX02_TX10
Ch.0 transition data2/
Ch.1 transition data0
163
133
F7
E_TX03_TX11
Ch.0 transition data3/
Ch.1 transition data1
162
132
E7
Ch.0 transition data enable
166
136
D6
Ch.0 transition data error detection/
Ch.1 transition data enable
161
131
D7
E_PPS0_PPS1
E_RXER0_RXDV1
E_TCK0_MDC1
E_TXEN0
E_TXER0_TXEN1
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
49
D a t a S h e e t
Module
RESET
Pin name
INITX
Mode
MD0
MD1
POWER
VCC
VCC
VCC
VCC
VCC
USBVCC0
USBVCC1
GND
50
CONFIDENTIAL
ETHVCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Function
External Reset Input pin.
A reset is valid when INITX="L".
Mode 0 pin.
During normal operation, MD0="L"
must be input. During serial
programming to Flash memory,
MD0="H" must be input.
Mode 1 pin.
During serial programming to Flash
memory, MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
3.3V Power supply port for USB I/O
Power supply pin for Ethernet I/O
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
LQFP-176
Pin No
LQFP-144
BGA-192
57
49
N5
85
69
N12
84
68
N13
1
45
54
89
133
1
37
46
73
109
C1
N1
P4
M14
A13
173
141
A4
129
105
E14
156
27
44
53
88
109
132
157
176
-
126
25
36
45
72
93
108
127
144
-
A9
J1
M1
P3
N14
F14
B14
A11
B1
E1
G1
P7
P11
L14
A8
A5
N7
M7
L7
K7
J7
G7
H7
H8
G8
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
LQFP-176
Pin No.
LQFP-144
BGA-192
Main clock (oscillation) input pin
86
70
P12
X0A
Sub clock (oscillation) input pin
55
47
P5
X1
Main clock (oscillation) I/O pin
87
71
P13
X1A
Sub clock (oscillation) I/O pin
56
48
P6
Bulit-in high-speed CR-osc clock
output port
127
103
D13
Module
Pin name
CLOCK
X0
CROUT_0
CROUT_1
Function
152
122
E8
AVCC
A/D converter analog power supply
pin
106
90
J14
AVRH
A/D converter analog reference
voltage input pin
107
91
H14
Analog
GND
AVSS
A/D converter GND pin
108
92
G14
C pin
C
Power stabilization capacity pin
52
44
P2
Analog
POWER
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D a t a S h e e t
 I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
When the main oscillation is
selected.
 Oscillation feedback resistor
: Approximately 1MΩ
 With Standby mode control
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
Digital input






When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50kΩ
 IOH = -4mA, IOL = 4mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
 CMOS level hysteresis input
 Pull-up resistor
: Approximately 50 kΩ
B
Pull-up resistor
Digital input
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Digital input
 Open drain output
 CMOS level hysteresis input
Control pin
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the sub oscillation is
selected.
 Oscillation feedback resistor
: Approximately 5 MΩ
 With Standby mode control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
: Approximately 50 kΩ
 IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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53
D a t a S h e e t
Type
Circuit
Remarks





E
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -4 mA, IOL = 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control







F
P-ch
P-ch
N-ch
R
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -4 mA, IOL = 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Type
Circuit
Remarks





G
P-ch
P-ch
Digital output
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -12 mA, IOL = 12 mA
 +B input is available
Digital output
R
Pull-up resistor control
Digital input
Standby mode control
H
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select the USB
I/O / GPIO function.
When the USB I/O is selected.
 Full-speed, Low-speed
control
UDP (+) output
EBP
USB Full-speed/Low-speed control
UDP (+) input
Differential
EBM
Differential input
USB/GPIO select
When the GPIO is selected.
 CMOS level output
 CMOS level hysteresis input
 With standby mode control
 IOH = -20.5 mA,
IOL = 18.5 mA
UDM (-) input
UDM (-) output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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D a t a S h e e t
Type
Circuit
Remarks






I
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
5 V tolerant
With standby mode control
IOH = -4 mA, IOL = 4 mA
Available to control of PZR
registers.
 When this pin is used as an
I2C pin, the digital output Pch transistor is always off
Digital output
Digital output
R
Digital input
Standby mode control
J
CMOS level hysteresis input
Mode input
56
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Type
Circuit
Remarks





K
P-ch
P-ch
N-ch
Digital output
CMOS level output
TTL level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -4 mA, IOL = 4 mA
Digital output
R
Pull-up resistor control
Digital input
Standby mode control





L
P-ch
P-ch
N-ch
Digital output
Digital output
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
 IOH = -8 mA, IOL = 8 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
 +B input is available
R
Pull-up resistor control
Digital input
Standby mode control
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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D a t a S h e e t
 Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1.
Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
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D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2.
Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
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D a t a S h e e t
3.
Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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D a t a S h e e t
 Handling Devices
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at
low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a
bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near
this device.
 Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Using an external clock
When using an external clock, the clock signal should be input to the X0,X0A pin only and the X1,X1A pin
should be kept open.
 Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
 Handling when using Multi-function serial pin as I2C pin
If it is using multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I 2C
bus system with power OFF.
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D a t a S h e e t
 C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
Cs
VSS
GND
 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.
Turning on : VCC → USBVCC0
VCC → USBVCC1
VCC → ETHVCC
VCC → AVCC → AVRH
Turning off : USBVCC0 → VCC
USBVCC1 → VCC
ETHVCC → VCC
AVRH → AVCC → VCC
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D a t a S h e e t
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
 Differences in features among the products with different memory sizes and between
Flash products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash products and
MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
 Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for
external startup trigger input (TGIN).
Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the
Base Timer to be "0b00" in order to disable trigger input.
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D a t a S h e e t
 Block Diagram
MB9BFD16/D17/D18
TRSTX,TCK,
TDI,TMS
TDO
TRACED[3:0],
TRACECLK
SWJ-DP
ETM
TPIU
ROM
Table
SRAM0
32/48/64Kbyte
MPU NVIC
Multi-layer AHB (Max 144MHz)
Cortex-M3 Core I
144MHz(Max)
D
Sys
AHB-APB Bridge:
APB0(Max 72MHz)
Dual-Timer
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
On-chip Flash
512Kbyte/
768Kbyte/
1024Kbyte
Flash I/F
Security
Trace Buffer
(16Kbyte)
SRAM1
32/48/64Kbyte
USBVCC0
USB 2.0
(Host/
Func)
PHY
USB 2.0
(Host/
Func)
PHY
UDP0,UDM0
UHCONX0
USBVCC1
UDP1,UDM1
UHCONX1
CSV
DMAC
8ch.
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
Main
Osc
Sub
Osc
PLL
Source Clock
CR
4MHz
AHB-AHB
Bridge
(Slave)
X1
CR
100kHz
12-bit A/D Converter
AHB-AHB
Bridge
(Master)
X0
Unit 0
AN[31:00]
Unit 1
ADTG[8:0]
CAN
TX0,
RX0
CAN
TX1,
RX1
EthernetMAC0
MII/
RMII
EthernetMAC1
RMII
Selector
CLK
E_TXx,
E_RXx,
E_MDx
Unit 2
MAD[24:00]
Base Timer
16-bit 16ch./
32-bit 8ch.
AIN[2:0]
BIN[2:0]
QPRC
3ch.
ZIN[2:0]
A/D Activation
Compare
3ch.
IC0[3:0]
IC1[3:0]
IC2[3:0]
FRCK[2:0]
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare
6ch.
DTTI[2:0]X
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
USB-Ethernet Clk Ctrl
AHB-APB Bridge : APB2 (Max 72MHz)
TIOB[15:00]
AHB-APB Bridge : APB1 (Max 72MHz)
TIOA[15:00]
External Bus I/F
CAN Prescaler
LVD Ctrl
IRQ-Monitor
MADATA[15:00]
PLL
Power On
Reset
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
MCLKOUT
LVD
Regulator
C
CRC
Accelerator
Watch Counter
External Interrupt
Controller
32-pin + NMI
Waveform Generator
3ch.
MODE-Ctrl
16-bit PPG
3ch.
GPIO
Multi-function Timer ×3
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
INT[31:00]
NMIX
MD[1:0]
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
PFx
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
RTS4
Note: The following items vary depending on the package.
A) Number of external bus interface pin
B) Number of 12-bit A/D converter channel
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D a t a S h e e t
 Memory Size
See "Memory size" of "Product Lineup" to confirm the memory size.
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 Memory Map
 Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0x4006_9000
0x4006_7000
0xFFFF_FFFF
0x4006_6000
Reserved
0xE010_0000
0xE000_0000
0x4006_4000
0x4006_3000
Cortex-M3 Private
Peripherals
0x4006_2000
0x4006_1000
0x4006_0000
Ethernet-MAC1
Ethernet-Control-Reg.
Ethernet-MAC0
CAN ch.1
CAN ch.0
Reserved
DMAC
USB ch.1
0x4005_0000
Reserved
USB ch.0
0x4004_0000
0x4003_F000
0x7000_0000
0x6000_0000
0x4200_0000
0x4000_0000
Reserved
External Device
Area
0x4003_B000
Reserved
0x4003_8000
0x4003_7000
32Mbyte
Bit band alias
0x4003_6000
0x4400_0000
Peripherals
0x4003_A000
0x4003_9000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
Reserved
0x4003_1000
0x4003_0000
32Mbyte
Bit band alias
0x4002_F000
0x4002_E000
Reserved
0x4002_8000
0x2400_0000
0x2200_0000
0x2008_0000
0x2000_0000
0x1FFF_0000
0x0010_2000
See the next page
“●Memory Map (2)” for
the memory size details.
0x0010_0000
SRAM1
SRAM0
Reserved
Security/CR Trim
Watch Counter
CRC
MFS
CAN Prescaler
USB-Ethernet Clk Ctrl
LVD Ctrl
Reserved
GPIO
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
Reserved
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
On-chip Flash
EXT-bus I/F
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
A/DC
QPRC
Base Timer
PPG
Reserved
MFT unit2
MFT unit1
MFT unit0
Reserved
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Flash I/F
67
D a t a S h e e t
 Memory Map(2)
MB9BFD18S/T
MB9BFD17S/T
0x2008_0000
MB9BFD16S/T
0x2008_0000
0x2008_0000
Reserved
Reserved
0x2001_0000
Reserved
0x2001_C000
SRAM1
64Kbyte
0x2000_8000
SRAM1
48Kbyte
0x2000_0000
SRAM1
32Kbyte
0x2000_0000
0x2000_0000
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_8000
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
0x0010_2000
CR trimming
Security
0x0010_1000
0x0010_0000
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-19(64KBx10)
0x0000_0000
SA4-7(8KBx4)
0x0008_0000
SA10-15(64KBx6)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
Flash 512Kbyte
SA8-9(48KBx2)
Flash 768Kbyte
Flash 1Mbyte
SA10-23(64KBx14)
SA8-9(48KBx2)
0x0000_0000
SA4-7(8KBx4)
*: See "MB9BD10T/610T/510T/410T/310T/210T/110T Series Flash programming Manual" for sector structure
of Flash.
68
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Peripheral Address Map
Start address
End address
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4002_3FFF
Multi-function timer unit2
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
0x4002_6000
0x4002_6FFF
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Function
0x4003_2000
0x4003_2FFF
Reserved
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_5FFF
Low-Voltage Detector
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
CAN Prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External bus I/F
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
USB ch.1
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
Reserved
0x4006_2000
0x4006_2FFF
0x4006_3000
0x4006_3FFF
0x4006_4000
0x4006_5FFF
Ethernet-MAC ch.0
0x4006_6000
0x4006_6FFF
Ethernet-MAC setting Register
0x4006_7000
0x4006_8FFF
Ethernet-MAC ch.1
0x4006_9000
0x41FF_FFFF
Reserved
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Bus
AHB
APB0
APB1
APB2
AHB
Peripherals
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
Base Timer
Quadrature Position/Revolution Counter (QPRC)
USB-Ethernet clock generator
CAN ch.0
CAN ch.1
69
D a t a S h e e t
 Pin Status in Each CPU State
The terms used for pin status have the following meanings.
 INITX=0
This is the period when the INITX pin is the "L" level.
 INITX=1
This is the period when the INITX pin is the "H" level.
 SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "0".
 SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is
set to "1".
 Input enabled
Indicates that the input function can be used.
 Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
 Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
 Setting disabled
Indicates that the setting is disabled.
 Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
 Analog input is enabled
Indicates that the analog input is enabled.
 Trace output
Indicates that the trace function can be used.
70
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 List of Pin Status
Pin
status
type
A
B
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low-voltage
internal reset sleep mode
state
state
detection state
state
state
Power supply
Function group Power supply
Power supply stable
Power supply stable
unstable
stable
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
Input
Input
Input
Input
Input
Input
Main crystal
enabled
enabled
enabled
enabled
enabled
enabled
oscillator input
pin
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
Main crystal
oscillator output
pin
Hi-Z/
Internal input
fixed at "0"/
or Input
enable
Hi-Z/
Internal
input fixed
at "0"
Hi-Z/
Internal
input fixed
at "0"
Maintain
previous
state
INITX input pin
Pull-up/
Input
enabled
Input enabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
GPIO
selected
Setting
disabled
Pull-up/
Input
enabled
Input
enabled
Pull-up/
Input
enabled
Setting
disabled
Trace selected
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected, or
resource other
than above
selected
Hi-Z
Hi-Z/
Input
enabled
Hi-Z/
Input
enabled
C
D
E
F
Mode input pin
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Maintain
previous
state/ Hi-Z
at oscillation
stop*1/
Internal
input fixed
at "0"
Pull-up/
Input
enabled
Input
enabled
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
Trace output
Maintain
previous
state
Hi-Z/
Internal
input fixed
at "0"
71
D a t a S h e e t
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low-voltage
internal reset sleep mode
state
state
detection state
state
state
Pin
Power supply
status Function group Power supply
Power supply stable
Power supply stable
unstable
stable
type
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
Trace selected
Setting
Setting
Setting
Maintain
Maintain
Trace output
disabled
disabled
disabled
previous
previous
state
state
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
G
or resource other
Input
Input
Internal
than above
enabled
enabled
input fixed
selected
at "0"
External interrupt
Setting
Setting
Setting
Maintain
Maintain
Maintain
enabled selected
disabled
disabled
disabled
previous
previous
previous
state
state
state
H
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
or resource other
Input
Input
Internal
than above
enabled
enabled
input fixed
selected
at "0"
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Maintain
Maintain
Hi-Z/
resource selected
Input
Input
previous
previous
Internal
I
enabled
enabled
state
state
input fixed
at "0"
NMIX selected
Setting
Setting
Setting
Maintain
Maintain
Maintain
disabled
disabled
disabled
previous
previous
previous
state
state
state
J
GPIO selected,
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
or resource other
Input
Input
Internal
than above
enabled
enabled
input fixed
selected
at "0"
72
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low-voltage
internal reset sleep mode
state
state
detection state
state
state
Pin
Power supply
status Function group Power supply
Power supply stable
Power supply stable
unstable
stable
type
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
Analog input
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
selected
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at "0"/
at "0"/
at "0"/
at "0"/
at "0"/
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
K
enabled
enabled
enabled
enabled
enabled
GPIO selected,
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
or resource other
disabled
disabled
disabled
previous
previous
Internal
than above
state
state
input fixed
selected
at "0"
External interrupt
Setting
Setting
Setting
Maintain
Maintain
Maintain
enabled selected
disabled
disabled
disabled
previous
previous
previous
state
state
state
Analog input
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
selected
Internal
Internal
Internal
Internal
Internal
input fixed
input fixed
input fixed
input fixed
input fixed
at "0"/
at "0"/
at "0"/
at "0"/
at "0"/
L
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
GPIO selected,
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
or resource other
disabled
disabled
disabled
previous
previous
Internal
than above
state
state
input fixed
selected
at "0"
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
M
Sub crystal
oscillator input
pin
Input
enabled
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
73
D a t a S h e e t
Power-on reset
Device
Run mode or
INITX input
Timer mode or sleep mode
or low-voltage
internal reset sleep mode
state
state
detection state
state
state
Pin
Power supply
status Function group Power supply
Power supply stable
Power supply stable
unstable
stable
type
INITX=0
INITX=1
INITX=1
INITX=1
SPL=0
SPL=1
GPIO selected
Setting
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
disabled
previous
previous
Internal
state
state
input fixed
at "0"
Sub crystal
Hi-Z/
Hi-Z/
Hi-Z/
Maintain
Maintain
Maintain
oscillator output
Internal input
Internal
Internal
previous
previous
previous
N
pin
fixed at "0"/
input fixed
input fixed
state
state/ Hi-Z
state/ Hi-Z
or Input
at "0"
at "0"
at oscillation at oscillation
stop*2/
stop*2/
enable
Internal
Internal
input fixed
input fixed
at "0"
at "0"
GPIO selected
Hi-Z
Hi-Z/
Hi-Z/
Maintain
Maintain
Hi-Z/
Input
Input
previous
previous
Internal
enabled
enabled
state
state
input fixed
at "0"
USB I/O pin
Setting
Setting
Setting
Maintain
Hi-Z at
Hi-Z at
O
disabled
disabled
disabled
previous
transmission/ transmission/
state
Input
Input
enabled/
enabled/
Internal input Internal input
fixed at "0"
fixed at "0"
at reception
at reception
Input
Input
Input
Input
Input
Input
Mode input pin
enabled
enabled
enabled
enabled
enabled
enabled
P
Maintain
Maintain
Hi-Z/
Setting
Setting
Setting
GPIO selected
previous
previous
Input
disabled
disabled
disabled
state
state
enabled
Ethernet input or
Maintain
Setting
Setting
Setting
output
previous
disabled
disabled
disabled
selected*3
state
Maintain
Maintain
Q
previous
previous
GPIO selected,
Hi-Z/
Hi-Z/
Hi-Z/
state
state
or resource other
Internal
Hi-Z
Input
Input
than above
input fixed
enabled
enabled
selected
at "0"
Ethernet input or
output pin
Maintain
Setting
Setting
Setting
selected*3
previous
disabled
disabled
disabled
state
External interrupt
Maintain
Maintain
R
enabled selected
previous
previous
state
state
GPIO selected,
Hi-Z/
Hi-Z/
Hi-Z/
or resource other
Internal
Hi-Z
Input
Input
than above
input fixed
enabled
enabled
selected
at "0"
*1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
*3: When selected by EPFR14.E_SPLC register.
74
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D a t a S h e e t
 Electrical Characteristics
1.
Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1,*2
Power supply voltage (for USB ch.0)*1,*3
Power supply voltage (for USB ch.1)*1,*3
Power supply voltage (for Ethernet)*1,*4
Analog power supply voltage*1,*5
Analog reference voltage*1,*5
Vcc
USBVcc0
USBVcc1
ETHVcc
AVcc
AVRH
Rating
Min
Max
Unit
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss - 0.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
Vss + 6.5
V
V
V
V
V
V
Vss - 0.5
Vcc + 0.5
(≤ 6.5V)
V
Remarks
Except for USB
pin and
Ethernet-MAC pin
USBVcc0 + 0.5
V USB ch.0 pin
(≤ 6.5V)
Input voltage*
VI
USBVcc1 + 0.5
Vss - 0.5
V USB ch.1 pin
(≤ 6.5V)
ETHVcc + 0.5
Vss - 0.5
V Ethernet-MAC pin
(≤ 6.5V)
Vss - 0.5
Vss + 6.5
V 5V tolerant
AVcc
+
0.5
Analog pin input voltage*1
VIA
Vss - 0.5
V
(≤ 6.5V)
Vcc + 0.5
Output voltage*1
VO
Vss - 0.5
V
(≤ 6.5V)
Clamp maximum current
ICLAMP
-2
+2
mA *9
Clamp total maximum current
Σ[ICLAMP]
+20
mA *9
10
mA 4 mA type
20
mA 8 mA type
"L" level maximum output current*6
IOL
20
mA 12 mA type
39
mA P80,P81,P82,P83
4
mA 4 mA type
8
mA 8 mA type
"L" level average output current*7
IOLAV
12
mA 12 mA type
18.5
mA P80,P81,P82,P83
"L" level total maximum output current
∑IOL
100
mA
"L" level total average output current*8
∑IOLAV
50
mA
- 10
mA 4 mA type
20
mA 8 mA type
"H" level maximum output current*6
IOH
- 20
mA 12 mA type
- 39
mA P80,P81,P82,P83
-4
mA 4 mA type
-8
mA 8 mA type
7
"H" level average output current*
IOHAV
- 12
mA 12 mA type
- 20.5
mA P80,P81,P82,P83
"H" level total maximum output current
∑IOH
- 100
mA
"H" level total average output current*8
∑IOHAV
- 50
mA
Power consumption
PD
1000
mW
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: USBVcc0 and USBVcc1 must not drop below Vss - 0.5 V.
*4: ETHVcc must not drop below Vss - 0.5 V.
*5: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
Vss - 0.5
1
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
75
D a t a S h e e t
*6: The maximum output current is the peak value for a single pin.
*7: The average output is the average current for a single pin over a period of 100 ms.
*8: The total average output current is the average current for all pins over a period of 100 ms.
*9:

See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.

Use within recommended operating conditions.

Use at DC voltage (current) the +B input.

The +B signal should always be applied a limiting resistance placed between the +B signal and the device.

The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the device pin does not exceed rated values, either instantaneously or for prolonged periods.

Note that when the device drive current is low, such as in the low-power consumpsion modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and
this may affect other devices.

Note that if a +B signal is input when the device power supply is off (not fixed at 0V), the power supply is
provided from the pins, so that incomplete operation may result.

The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
Limiting
resistor
P-ch
Digital output
+B input (0V to 16V)
N-ch
Digital input
R
AVCC
Analog input
<WARNING>
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
76
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MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
2.
Recommended Operating Conditions
(Vss = AVss = 0.0V)
Parameter
Symbol
Conditions
Power supply voltage
Vcc
-
Power supply voltage
(3V power supply) for
USB ch.0
USBVcc0
-
Power supply voltage
(3V power supply) for
USB ch.1
USBVcc1
Value
Min
Max
2.7*8
AVcc
AVRH
-
2.7
2.7
5.5
3.6
(≤ Vcc)
5.5
(≤ Vcc)
3.6
(≤ Vcc)
5.5
(≤ Vcc)
3.6
(≤ Vcc)
5.5
(≤ Vcc)
5.5
(≤ Vcc)
5.5
AVcc
CS
-
1
10
3.0
2.7
3.0
2.7
3.0
Power supply voltage for
Ethernet
ETHVcc
-
4.5
2.7
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
Unit
Remarks
V
V
V
AVcc = Vcc
μF
for built-in
regulator *7
*1
V
*2
*3
V
*4
*5
V
*5
*6
When
mounted on
Ta
- 40
+ 85
°C
four-layer
PCB
*1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3: When P83/UDP1 and P82/UDM1 pin are used as USB (UDP1, UDM1).
*4: When P83/UDP1 and P82/UDM1 pin are used as GPIO (P83, P82).
*5: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as
Ethernet-MAC pin.
*6: When the pins in "Ethernet-MAC pins" except P62/E_PPS0_PPS1/SCK5_0/ADTG_3 pin are used as
function pins other than Ethernet-MAC pin.
*7: See "●C pin" in "Handling Devices" for the connection of the smoothing capacitor.
*8 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
Operating
temperature
FPT-144P-M08,
FPT-176P-M07,
BGA-192P-M06
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure. No warranty is made
with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their representatives beforehand.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
77
D a t a S h e e t
 Ethernet-MAC pins
Pin Name
P62/E_PPS0_PPS1/SCK5_0/ADTG_3
PC0/E_RXER0_RXDV1
PC1/E_RX03_RX11
PC2/E_RX02_RX10
PC3/E_RX01/TIOA06_1
PC4/E_RX00/TIOA08_2
PC5/E_RXDV0/TIOA10_2
PC6/E_MDIO0/TIOA14_0
PC7/E_MDC0/CROUT_1
PC8/E_RXCK0_REFCK
PC9/E_COL0
PCA/E_CRS0
PCB/E_COUT
PCC/E_MDIO1
PCD/E_TCK0_MDC1
PCE/E_TXER0_TXEN1/RTS4_0/
TIOB06_1
PCF/E_TX03_TX11/CTS4_0/TIOB08_2
PD0/E_TX02_TX10/SCK4_0/TIOB10_2/
INT30_1
Ethernet-MAC
function
Except for
Ethernet-MAC
function
E_PPS0_PPS1*
E_RXER0_RXDV1
E_RX03_RX11
E_RX02_RX10
E_RX01
E_RX00
E_RXDV0
E_MDIO0
E_MDC0
E_RXCK0_REFCK
E_COL0
E_CRS0
E_COUT
E_MDIO1
E_TCK0_MDC1
P62 /SCK5_0/ADTG_3
PC0
PC1
PC2
PC3/TIOA06_1
PC4/TIOA08_2
PC5/TIOA10_2
PC6/TIOA14_0
PC7/CROUT_1
PC8
PC9
PCA
PCB
PCC
PCD
E_TXER0_TXEN
PCE/RTS4_0/TIOB06_1
Power
Supply
type
Vcc
ETHVcc
PCF/CTS4_0/TIOB08_2
PD0/SCK4_0/TIOB10_2/
E_TX02_TX10
INT30_1
PD1/SOT4_0/TIOB14_0/
PD1/E_TX01/SOT4_0/TIOB14_0/INT31_1 E_TX01
INT31_1
PD2/E_TX00/SIN4_0/TIOA03_2/INT00_2 E_TX00
PD2/TIOA03_2/INT00_2
PD3/E_TXEN0/TIOB03_2
E_TXEN0
PD3/TIOB03_2
*: It is used to confirm the PTP counter cycle in Ethernet-MAC by wave forms.
78
CONFIDENTIAL
E_TX03_TX11
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
3.
DC Characteristics
(1) Current Rating
(Vcc = AVcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Parameter Symbol
Pin
name
Conditions
PLL
RUN mode
RUN
mode
current
Icc
High-speed
CR
RUN mode
VCC
Sub
RUN mode
Low-speed
CR
RUN mode
CPU : 144 MHz,
Peripheral : 72 MHz,
Flash 2 Wait,
TraceBuffer : ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
CPU : 72 MHz,
Peripheral : 72 MHz,
Flash 0 Wait,
TraceBuffer : OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
CPU/ Peripheral : 4 MHz*2,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral : 32 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral : 100 kHz,
Flash 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
Value
Unit Remarks
Typ*3 Max*4
100
180
mA *1, *5
65
135
mA *1, *5
6
57.8
mA *1
1.3
51.7
mA *1, *6
1.3
51.7
mA *1
PLL
Peripheral : 72 MHz
30
89
mA *1, *5
SLEEP mode
High-speed
CR
Peripheral : 4 MHz*2
4.5
55.9 mA *1
SLEEP
SLEEP mode
mode
Iccs
Sub
current
Peripheral : 32 kHz
1.2
51.6 mA *1, *6
SLEEP mode
Low-speed
CR
Peripheral : 100 kHz
1.2
51.6 mA *1
SLEEP mode
*1: When all ports are fixed, Ethernet is stopped.
*2: When setting it to 4MHz by trimming.
*3: Ta=+25°C, VCC=5.5 V
*4: Ta=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
79
D a t a S h e e t
(Vcc = AVcc = USBVcc0 = USBVcc1 = ETHVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Pin
name
Parameter Symbol
TIMER
mode
current
Main
TIMER
mode
ICCT
VCC
STOP
mode
current
ICCH
Value
Unit Remarks
Typ*2 Max*2
Conditions
Sub
TIMER
mode
STOP mode
Ta = + 25°C,
When LVD is off
Ta = + 85°C,
When LVD is off
Ta = + 25°C,
When LVD is off
Ta = + 85°C,
When LVD is off
Ta = + 25°C,
When LVD is off
Ta = + 85°C,
When LVD is off
4
10
mA
*1, *3
-
55
mA
*1, *3
1.1
5
mA
*1, *4
-
50
mA
*1, *4
1
5
mA
*1
-
50
mA
*1
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
· Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
Value
Typ
Max
4
7
Unit
μA
Remarks
At not detect
· Flash Memory Current
(VCC = 2.7V to 5.5V, VSS = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
12
14
Unit
Remarks
mA
· A/D Converter Current
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, Ta = - 40°C to + 85°C)
Parameter
Power supply
current
Reference power
supply current
80
CONFIDENTIAL
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
Value
Typ
Max
Unit
At 1unit
operation
0.57
0.72
mA
At stop
0.06
35
μA
At 1unit
operation
AVRH=5.5V
1.1
1.96
mA
At stop
0.06
4
μA
Conditions
Remarks
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(2) Pin Characteristics
(Vcc = USBVcc0 = USBVcc1 = ETHVcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Parameter Symbol Pin name
"H" level
input
voltage
(hysteresis
input)
"L" level
input
voltage
(hysteresis
input)
"H" level
output voltage
VIHS
VILS
VOH
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
TTL
Schmitt
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
TTL
Schmitt
input pin
Min
Value
Typ
Max
Unit Remarks
-
Vcc
(ETHVcc) ×
0.8
-
Vcc
(ETHVcc) +
0.3
V
-
Vcc × 0.8
-
Vss + 5.5
V
-
2.0
-
ETHVcc +
0.3
V
-
Vss - 0.3
-
Vcc
(ETHVcc) ×
0.2
V
-
Vss - 0.3
-
Vcc × 0.2
V
-
Vss - 0.3
-
0.8
V
Vcc
(ETHVcc) 0.5
-
Vcc
(ETHVcc)
V
*1
ETHVcc 0.5
-
ETHVcc
V
*1
Vcc - 0.5
-
Vcc
V
USBVcc 0.4
-
USBVcc
V
Vcc (ETHVcc) ≥
4.5 V,
IOH = - 4 mA
4mA type
Vcc (ETHVcc) <
4.5 V,
IOH = - 2 mA
ETHVcc ≥ 4.5 V,
IOH = - 8 mA
8mA type
ETHVcc < 4.5 V,
IOH = - 4 mA
Vcc ≥ 4.5 V,
IOH = - 12 mA
12mA type
Vcc < 4.5 V,
IOH = - 8 mA
USBVcc ≥ 4.5 V,
P80, P81, IOH = - 20.5 mA
P82, P83 USBVcc < 4.5 V,
IOH = - 13.0 mA
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Conditions
*1
*1
*2
81
D a t a S h e e t
Parameter
Symbol
Pin
name
4mA type
"L" level
output voltage
8mA type
VOL
12mA type
P80, P81,
P82, P83
Input leak
current
Pull-up
resistance
value
IIL
-
RPU
Pull-up pin
Min
Value
Typ
Max
Vss
-
0.4
V
*1
Vss
-
0.4
V
*1
Vss
-
0.4
V
Vss
-
0.4
V
-
-5
-
+5
μA
Vcc ≥ 4.5 V
25
50
100
Vcc < 4.5 V
30
80
200
Conditions
Vcc (ETHVcc) ≥
4.5 V,
IOL = 4 mA
Vcc (ETHVcc) <
4.5 V,
IOL = 2 mA
ETHVcc ≥ 4.5 V,
IOL = 8 mA
ETHVcc < 4.5 V,
IOL = 4 mA
Vcc ≥ 4.5 V,
IOL = 12 mA
Vcc < 4.5 V,
IOL = 8 mA
USBVcc ≥ 4.5 V,
IOL = 18.5 mA
USBVcc < 4.5 V,
IOL = 10.5 mA
Unit Remarks
*2
kΩ
Other than
VCC,
USBVCC0,
USBVCC1,
Input
CIN
ETHVCC,
5
15
pF
capacitance
VSS,
AVCC,
AVSS,
AVRH
*1: The power supply type varies depending on the pin position.
For example, power supply A (power supply B) shows that either of power supply A or power supply B
becomes a power supply voltage.
*2: USBVcc0 and USBVcc1 are described as USBVcc.
82
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
4.
AC Characteristics
(1) Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
name
Vcc ≥ 4.5V
Value
Min
Max
4
4
4
4
20
50
50
20
50
20
250
250
Unit
Remarks
When crystal oscillator
is connected
Input frequency
FCH
When using external
MHz
clock
X0,
When using external
Input clock cycle
tCYLH
ns
X1
clock
Input clock pulse
When using external
45
55
%
width
clock
Input clock rise
tCF,
When using external
5
ns
time and fall time
tCR
clock
FCM
144
MHz Master clock
Base clock
FCC
144
MHz
(HCLK/FCLK)
Internal operating
clock*1 frequency
FCP0
72
MHz APB0 bus clock*2
FCP1
72
MHz APB1 bus clock*2
FCP2
72
MHz APB2 bus clock*2
Base clock
tCYCC
6.94
ns
(HCLK/FCLK)
Internal operating
tCYCP0
13.8
ns
APB0 bus clock*2
1
clock* cycle time
tCYCP1
13.8
ns
APB1 bus clock*2
tCYCP2
13.8
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data
sheet.
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
Vcc ≥ 4.5V
Vcc < 4.5V
PWH/tCYLH,
PWL/tCYLH
MHz
X0
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
83
D a t a S h e e t
(2) Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Input frequency
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Conditions
name
Unit
1/tCYLL
X0A,
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
(3) Internal CR Oscillation Characteristics
 High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Ta = + 25°C
Clock frequency
FCRH
Ta =
0°C to + 70°C
Ta =
- 40°C to + 85°C
Ta =
- 40°C to + 85°C
Min
Value
Typ
Max
3.96
4
4.04
3.84
4
4.16
Unit
Remarks
When trimming*
MHz
3.8
4
4.2
3
4
5
When not trimming
Frequency
tCRWT
90
μs *2
stability time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR.
clock after the trim value is set. After setting the trim value, the period when the frequency stability
time passes can use the High-speed CR clock as a source clock.
 Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Clock frequency
84
CONFIDENTIAL
Symbol
Conditions
FCRL
-
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(4-1) Operating Conditions of Main and USB/Ethernet PLL (In the case of using main clock for input
of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
tLOCK
100
-
FPLLI
FPLLO
FCLKPLL
4
13
200
-
-
16 MHz
75 multiple
300 MHz
144 MHz
USB/Ethernet clock frequency*3
FCLKSPLL
-
-
50
-
Remarks
μs
MHz
After the M frequency
division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
*3: For more information about USB/Ethernet clock, see "CHAPTER 2-3: USB/Ethernet Clock Generation" in
"FM3 Family PERIPHERAL MANUAL Communication Macro Part".
(4-2) Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Min Typ Max
Remarks
PLL oscillation stabilization wait time*1
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
FPLLI
3.8
4
4.2 MHz
PLL multiple rate
50
71 multiple
PLL macro oscillation clock frequency
FPLLO
190
300 MHz
Main PLL clock frequency*2
FCLKPLL
144 MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family
PERIPHERAL MANUAL".
Note: Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency
has been trimmed.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
PLL input
clock
K
divider
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB/Ethernet PLL connection
Main clock (CLKMO)
K
divider
PLL input
clock
USB/Ethernet
PLL
PLL macro
oscillation clock
M
divider
USB/Ethernet
clock
N
divider
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
85
D a t a S h e e t
(5) Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Reset input time
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Power supply rising time
Power supply shut down time
Time until releasing
Power-on reset
Symbol
Pin
name
Value
Max
0
-
ms
1
-
ms
0.46
0.76
ms
Tr
Toff
VCC
Tprt
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
Tr
Tprt
Internal RST
CPU Operation
RST Active
Toff
Release
start
Glossary
 VCC_minimum : Minimum VCC of recommended operating conditions
 VDH_minimum : Minimum release voltage of Low-Voltage detection reset.
See "7. Low-Voltage Detection Characteristics"
86
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(7) External Bus Timing
 External bus clock output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Output frequency
Symbol
Pin name
Conditions
tCYCLE
MCLKOUT*1
Vcc ≥ 4.5 V
Vcc < 4.5 V
Value
Min
Max
Unit
50*2
32*3
MHz
MHz
-
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in
"FM3 Family PERIPHERAL MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more
than 4.
*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more
than 4.
MCLKOUT
 External bus signal input/output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Signal input characteristics
Signal output characteristics
Symbol
VIH
VIL
VOH
-
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Conditions
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
87
D a t a S h e e t
 Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
MOEX
Vcc ≥ 4.5 V
tOEW
MOEX
MCLK×n-3
Min pulse width
Vcc < 4.5 V
-9
Vcc ≥ 4.5 V
MCSX ↓ → Address
MCSX[7:0],
tCSL – AV
output delay time
MAD[24:0]
Vcc < 4.5 V
-12
MOEX ↑ →
MOEX,
Vcc ≥ 4.5 V
tOEH - AX
0
Address hold time
MAD[24:0]
Vcc < 4.5 V
MCLK×m-9
MCSX ↓ →
Vcc ≥ 4.5 V
tCSL - OEL
MOEX ↓ delay time
Vcc < 4.5 V MCLK×m-12
MOEX,
MCSX[7:0]
MOEX ↑ →
Vcc ≥ 4.5 V
tOEH - CSH
0
MCSX ↑ time
Vcc < 4.5 V
MCLK×m-9
MCSX ↓ →
MCSX,
Vcc ≥ 4.5 V
tCSL - RDQML
MDQM ↓ delay time
MDQM[1:0]
Vcc < 4.5 V MCLK×m-12
20
Data set up →
MOEX,
Vcc ≥ 4.5 V
tDS - OE
MOEX ↑ time
MADATA[15:0]
Vcc < 4.5 V
38
MOEX ↑ →
MOEX,
Vcc ≥ 4.5 V
tDH - OE
0
Data hold time
MADATA[15:0]
Vcc < 4.5 V
Vcc ≥ 4.5 V
MWEX
tWEW
MWEX
MCLK×n-3
Min pulse width
Vcc < 4.5 V
MWEX ↑ → Address
MWEX,
Vcc ≥ 4.5 V
tWEH - AX
0
output delay time
MAD[24:0]
Vcc < 4.5 V
MCLK×n-9
Vcc ≥ 4.5 V
MCSX ↓ →
tCSL - WEL
MWEX ↓ delay time
Vcc < 4.5 V MCLK×n-12
MWEX,
MCSX[7:0]
MWEX ↑ →
Vcc ≥ 4.5 V
tWEH - CSH
0
MCSX ↑ delay time
Vcc < 4.5 V
MCLK×n-9
MCSX ↓ →
MCSX,
Vcc ≥ 4.5 V
tCSL-WDQML
MDQM ↓ delay time
MDQM[1:0]
Vcc < 4.5 V MCLK×n-12
MCLK-9
MCSX ↓ →
MCSX,
Vcc ≥ 4.5 V
tCSL - DV
Data output time
MADATA[15:0]
Vcc < 4.5 V
MCLK-12
MWEX ↑ →
MWEX,
Vcc ≥ 4.5 V
tWEH - DX
0
Data hold time
MADATA[15:0]
Vcc < 4.5 V
Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
88
CONFIDENTIAL
Max
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
MCSX[7:0]
tCSL-AV
MAD[24:0]
tOEH-AX
Address
tWEH-AX
tCSL-AV
Address
tCSL-OEL
MOEX
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
tCSL-WEL
tWEW
MWEX
tDS-OE
MADATA[15:0]
tDH-OE
RD
tWEH-DX
WD
Invalid
tCSL-DV
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
89
D a t a S h e e t
 Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK,
MAD[24:0]
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
tCSL
MCLK,
MCSX[7:0]
MCSX delay time
tCSH
tREL
MCLK,
MOEX
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
tDS
tDH
tWEL
MCLK,
MWEX
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
tDQMH
MCLK ↑ →
MCLK,
tOD
Data output time
MADATA[15:0]
MCLK ↑ →
MCLK,
tOD
Data hold time
MADATA[15:0]
Note: When the external load capacitance = 30 pF.
Value
Min
1
1
1
1
1
Max
9
12
9
12
9
12
9
12
9
12
Unit
ns
ns
ns
ns
ns
19
37
-
ns
0
-
ns
1
1
1
1
MCLK+1
1
9
12
9
12
9
12
9
12
MCLK+18
MCLK+24
18
24
ns
ns
ns
ns
ns
ns
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
MAD[24:0]
Address
tREL
tREH
tDQML
tDQMH
MOEX
tDQML
tDQMH
tWEL
tWEH
MDQM[1:0]
MWEX
MADATA[15:0]
tDS
tDH
RD
tOD
WD
Invalid
tODS
90
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Multiplexed
Vcc ≥ 4.5 V
tALE-CHMADV
0
address delay time
Vcc < 4.5 V
MALE,
MADATA[15:0]
Vcc ≥ 4.5 V MCLK×n+0
Multiplexed
tCHMADH
address hold time
Vcc < 4.5 V MCLK×n+0
Note: When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Max
10
20
MCLK×n+10
MCLK×n+20
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
91
D a t a S h e e t
 Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
Pin name
Conditions
MCLK,
ALE
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK ↑ →
Multiplexed
tCHMADV
Address delay time
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
tCHMADX
Data output time
Note: When the external load capacitance = 30 pF.
Vcc ≥ 4.5 V
Min
Value
Max
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
92
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 NAND Flash Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Vcc ≥ 4.5 V
MNREX
tNREW
MNREX
Min pulse width
Vcc < 4.5 V
Vcc ≥ 4.5 V
Data setup →
MNREX,
tDS – NRE
MNREX↑time
MADATA[15:0] Vcc < 4.5 V
Vcc ≥ 4.5 V
MNREX↑→
MNREX,
tDH – NRE
Data hold time
MADATA[15:0] Vcc < 4.5 V
Vcc ≥ 4.5 V
MNALE↑→
MNALE,
tALEH - NWEL
MNWEX delay time
MNWEX
Vcc < 4.5 V
Vcc ≥ 4.5 V
MNALE↓→
MNALE,
tALEL - NWEL
MNWEX delay time
MNWEX
Vcc < 4.5 V
Vcc ≥ 4.5 V
MNCLE↑→
MNCLE,
tCLEH - NWEL
MNWEX delay time
MNWEX
Vcc < 4.5 V
Vcc ≥ 4.5 V
MNWEX↑→
MNCLE,
tNWEH - CLEL
MNCLE delay time
MNWEX
Vcc < 4.5 V
Vcc ≥ 4.5 V
MNWEX
tNWEW
MNWEX
Min pulse width
Vcc < 4.5 V
Vcc ≥ 4.5 V
MNWEX↓→
MNWEX,
tNWEL – DV
Data output time
MADATA[15:0] Vcc < 4.5 V
Vcc ≥ 4.5 V
MNWEX↑→
MNWEX,
tNWEH – DX
Data hold time
MADATA[15:0] Vcc < 4.5 V
Note: When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
Value
Unit
Min
Max
MCLK×n-3
-
ns
20
38
-
ns
0
-
ns
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
0
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
0
ns
ns
ns
ns
ns
ns
ns
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Read
93
D a t a S h e e t
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
94
CONFIDENTIAL
Write
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
MCLK ↑
MRDY input
setup time
Symbol
tRDYI
Pin name Conditions
MCLK,
MRDY
Value
Min
Vcc ≥ 4.5 V
19
Vcc < 4.5 V
37
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
95
D a t a S h e e t
(8) Base Timer Input Timing
 Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
 Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "Block Diagram" in this data sheet.
96
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(9) CSIO/UART Timing
 CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
Vcc < 4.5V
Min
Max
Vcc ≥ 4.5V
Min
Max
Unit
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
97
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
tIVSHI
tSHIXI
VIH
VIL
VIH
VIL
SIN
Master mode
tSLSH
SCK
VIH
tF
SOT
SIN
VIL
tSHSL
VIL
VIH
VIH
tR
tSLOVE
VOH
VOL
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
98
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 CSIO (SPI = 0, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Vcc < 4.5V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
Vcc ≥ 4.5V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
99
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
VIL
SIN
tSLIXI
VIH
VIL
Master mode
tSHSL
SCK
VIH
SIN
VIH
VIL
tR
SOT
tSLSH
VIL
VIL
tF
tSHOVE
VOH
VOL
tIVSLE
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
100
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Vcc < 4.5 V
Min
Max
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
30
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock "L" pulse width
tSLSH
SCKx
Serial clock "H" pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK fall time
SCK rise time
tF
tR
Vcc ≥ 4.5 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
Unit
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
101
D a t a S h e e t
tSCYC
VOH
VOL
SCK
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
tSOVLI
VIH
VIL
Master mode
tSLSH
SCK
VIH
tR
VIH
tSHOVE
VOH
VOL
VOH
VOL
tIVSLE
SIN
VIH
VIL
tF
*
SOT
VIL
tSHSL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
102
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
name
Vcc < 4.5 V
Min
Max
Vcc ≥ 4.5 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
30
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock "L" pulse width
tSLSH
SCKx
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK fall time
SCK rise time
tF
tR
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
2tCYCP 30
2tCYCP 10
tCYCP +
10
-
50
-
30
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to CLK synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance = 30 pF.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
103
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tSHSL
tR
SCK
VIL
tSLSH
VIH
VIH
tF
VIL
VIL
VIH
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
 UART external clock input (EXT = 1)
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
SCK rise time
tSLSH
tSHSL
tF
tR
CL = 30 pF
tR
SCK
VIL
104
CONFIDENTIAL
Value
Symbol Conditions
Min
Max
tCYCP + 10
tCYCP + 10
-
5
5
tSHSL
VIH
VIL
ns
ns
ns
ns
tF
tSLSH
VIH
Unit Remarks
VIL
VIH
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(10) External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol Pin name
Conditions
Value
Unit
Min
Max
ADTG
FRCKx
-
2tCYCP*
-
ns
-
2tCYCP*
-
ns
ICxx
Input pulse width
tINH,
tINL
DTTIxX
Remarks
A/D converter
trigger input
Free-run timer input
clock
Input capture
Wave form
generator
Except
Timer mode, 2tCYCP + 100*
ns
INTxx,
External interrupt
Stop mode
NMIX
NMI
Timer mode,
500
ns
Stop mode
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected
to, see "Block Diagram" in this data sheet.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
105
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Value
Conditions
Min
Max
AIN pin "H" width
tAHL
AIN pin "L" width
tALL
BIN pin "H" width
tBHL
BIN pin "L" width
tBLL
BIN rise time from
PC_Mode2 or
tAUBU
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBUAD
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tADBD
AIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
tBDAU
BIN pin "L" level
PC_Mode3
AIN rise time from
PC_Mode2 or
2tCYCP*
tBUAU
BIN pin "H" level
PC_Mode3
BIN fall time from
PC_Mode2 or
tAUBD
AIN pin "H" level
PC_Mode3
AIN fall time from
PC_Mode2 or
tBDAD
BIN pin "L" level
PC_Mode3
BIN rise time from
PC_Mode2 or
tADBU
AIN pin "L" level
PC_Mode3
ZIN pin "H" width
tZHL
QCR:CGSC="0"
ZIN pin "L" width
tZLL
QCR:CGSC="0"
AIN/BIN rise and fall time
tZABE
QCR:CGSC="1"
from determined ZIN level
Determined ZIN level from
tABEZ
QCR:CGSC="1"
AIN/BIN rise and fall time
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see
"Block Diagram" in this data sheet.
Unit
ns
tALL
tAHL
AIN
tAUBU
tADBD
tBUAD
tBDAU
BIN
tBHL
106
CONFIDENTIAL
tBLL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
tBLL
tBHL
BIN
tBUAU
tBDAD
tAUBD
tADBU
AIN
tAHL
tALL
ZIN
ZIN
AIN/BIN
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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107
D a t a S h e e t
2
(12) I C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
SCL clock frequency
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
Bus free time between
"STOP condition" and
"START condition"
Symbol Conditions
Standard-mode Fast-mode
Unit Remarks
Min
Max
Min Max
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
μs
μs
4.7
-
0.6
-
μs
0
3.45*2
0
0.9*3
μs
tSUDAT
250
-
100
-
ns
tSUSTO
4.0
-
0.6
-
μs
tBUF
4.7
-
1.3
-
μs
tSUSTA
tHDDAT
CL = 30 pF,
R = (Vp/IOL)*1
8 MHz ≤
2 tCYCP*4
2 tCYCP*4
ns *5
tCYCP ≤ 40 MHz
40 MHz <
Noise filter
tSP
3 tCYCP*4
3 tCYCP*4
ns *5
tCYCP ≤ 60 MHz
60 MHz <
4 tCYCP*4
4 tCYCP*4
ns *5
tCYCP ≤ 72 MHz
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies
the requirement of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see "Block Diagram" in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
*5: The number of steps of the noise filter can be changed with register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
108
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(13) ETM Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Data hold
TRACECLK
frequency
Pin name
Conditions
tETMH
TRACECLK,
TRACED[3:0]
Vcc ≥ 4.5 V
2
9
Vcc < 4.5 V
2
15
Vcc ≥ 4.5 V
-
50
MHz
Vcc < 4.5 V
-
32
MHz
Vcc ≥ 4.5 V
20
-
ns
Vcc < 4.5 V
31.25
-
ns
1/ tTRACE
TRACECLK
TRACECLK
cycle time
Value
Unit
Min Max
Symbol
tTRACE
Remarks
ns
Note: When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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109
D a t a S h e e t
(14) JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
Value
Min
Max
Unit
15
-
ns
15
-
ns
Vcc ≥ 4.5 V
-
25
Vcc < 4.5 V
-
45
Remarks
ns
Note: When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
110
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(15) Ethernet-MAC Timing
 RMII transmission (100Mbps/10Mbps)
(ETHVcc = 3.0V to 3.6V, 4.5V to 5.5V*1)
(Vss = 0V, Ta = - 40°C to + 85°C, CL=25pF)
Parameter
Reference Clock
Cycle time*2
Reference Clock
High pulse width duty
Reference Clock
Low pulse width duty
Symbol
Pin name
Conditions
tREFCYC
E_RXCK0_REFCK
20 ns (typical)
tREFCYCH
E_RXCK0_REFCK
tREFCYCL
E_RXCK0_REFCK
tREFCYCH /
tREFCYC
tREFCYCL /
tREFCYC
Value
Min Max
Unit
-
-
ns
35
65
%
35
65
%
E_TX01,
E_TX00,
E_TXEN0
tRMIITX
12
ns
E_TX03_TX11,
REFCK ↑ → Transmitted data
E_TX02_TX10,
Delay time (ch.1)
E_TXER0_TXEN1
*1: When ETHV=4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the
output current.
*2: The reference clock is fixed to 50MHz in the RMII specifications. The clock accuracy should meet the
PHY-device specifications.
REFCK ↑ → Transmitted data
Delay time (ch.0)
tREFCYC
E_RXCK0_REFCK
VIHS
tREFCYCH
E_TX03_TX11
E_TX02_TX10
E_TX01
E_TX00
E_TXEN0
E_TXER0_TXEN1
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
VIHS
VILS
tREFCYCL
VOH
VOL
tRMIITX
111
D a t a S h e e t
 RMII receiving (100Mbps/10Mbps)
(ETHVcc = 3.0V to 3.6V, 4.5V to 5.5V)
(Vss = 0V, Ta = - 40°C to + 85°C, CL=25pF)
Parameter
Reference Clock
Cycle time*
Reference Clock
High pulse width duty
Reference Clock
Low pulse width duty
Symbol
Pin name
Conditions
tREFCYC
E_RXCK0_REFCK
20 ns (typical)
tREFCYCH
E_RXCK0_REFCK
tREFCYCL
E_RXCK0_REFCK
Unit
-
-
ns
35
65
%
35
65
%
-
4
-
ns
-
2
-
ns
tREFCYCH /
tREFCYC
tREFCYCL /
tREFCYC
E_RX01,
E_RX00,
E_RXDV0
tRMIIRXS
E_RX03_RX11,
Received data → REFCK↑
E_RX02_RX10,
Setup time(ch.1)
E_RXER0_RXDV1
E_RX01,
REFCK ↑ → Received data
E_RX00,
Hold time(ch.0)
E_RXDV0
tRMIIRXH
E_RX03_RX11,
REFCK ↑ → Received data
E_RX02_RX10,
Hold time (ch.1)
E_RXER0_RXDV1
*: The reference clock is fixed to 50 MHz in the RMII specifications.
The clock accuracy should meet the PHY-device specifications.
Value
Min
Max
Received data → REFCK↑
Setup time(ch.0)
tREFCYC
E_RXCK0_REFCK
VIHS
E_RX03_RX11
E_RX02_RX10
E_RX01
E_RX00
E_RXDV0
E_RXER0_RXDV1
112
CONFIDENTIAL
tREFCYCH
VIHS
VILS
tRMIIRXS
VIHS
VILS
tREFCYCL
VIHS
VILS
tRMIIRXH
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Management Interface
(ETHVcc = 3.0V to 3.6V, 4.5V to 5.5V)
(Vss = 0V, Ta = - 40°C to + 85°C, CL=25pF)
Parameter
Symbol
Pin name
Value
Conditions
Min
Max
Unit
Management Clock
E_MDC0
Cycle time* (ch.0)
tMDCYC
400
Management Clock
E_TCK0_MDC1
Cycle time* (ch.1)
Management Clock
High pulse width duty
E_MDC0
(ch.0)
tMDCYCH /
tMDCYCH
45
55
tMDCYC
Management Clock
High pulse width duty
E_TCK0_MDC1
(ch.1)
Management Clock
Low pulse width duty
E_MDC0
(ch.0)
tMDCYCL /
tMDCYCL
45
55
tMDCYC
Management Clock
Low pulse width duty
E_TCK0_MDC1
(ch.1)
MDC ↓ → MDIO
E_MDIO0
Delay time (ch.0)
tMDO
60
MDC ↓ → MDIO
E_MDIO1
Delay time (ch.1)
MDIO → MDC ↑
E_MDIO0
Setup time (ch.0)
tMDIS
20
MDIO → MDC ↑
E_MDIO1
Setup time (ch.1)
MDC ↑ → MDIO
E_MDIO0
Hold time (ch.0)
tMDIH
0
MDC ↑ → MDIO
E_MDIO1
Hold time (ch.1)
*: The clock time should be set to a value greater than the minimum value by setting the Ether-MAC setting
register.
ns
%
%
ns
ns
ns
tMDCYC
E_MDC0 (output)
E_TCK0_MDC1 (output)
VOH
VOL
tMDCYCH
E_MDIO0 (input)
E_MDIO1 (input)
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
tMDCYCL
VIHS
VILS
VIHS
VILS
VIHS
VILS
VIHS
VILS
tMDIS
tMDIH
tMDIS
tMDIH
tMDO
tMDO
E_MDIO0 (output)
E_MDIO1 (output)
VOH
VOL
VOH
VOL
VOH
VOL
113
D a t a S h e e t
 MII transmission (100Mbps/10Mbps)
(ETHVcc = 3.0V to 3.6V, 4.5V to 5.5V*1)
(Vss = 0V, Ta = - 40°C to + 85°C, CL=25pF)
Parameter
Transmission Clock
Cycle time*2
Transmission Clock
High pulse width duty
Transmission Clock
Low pulse width duty
Symbol
tTXCYC
Pin name
Conditions
100 Mbps,
40 ns (typical)
10 Mbps,
400 ns (typical)
tTXCYCH /
tTXCYC
tTXCYCL /
tTXCYC
E_TCK0_MDC1
tTXCYCH
E_TCK0_MDC1
tTXCYCL
E_TCK0_MDC1
Value
Min
Max
Unit
-
-
ns
-
-
ns
35
65
%
35
65
%
E_TX03_TX11,
E_TX02_TX10,
TXCK ↑ → Transmitted data
E_TX01,
tMIITX
24
ns
Delay time
E_TX00,
E_TXEN0,
E_TXER0_TXEN1
*1: When ETHV=4.5 V to 5.5 V, it is recommended to add a series resistor at the output pin to suppress the
output current.
*2: The transmission clock is fixed to 25 MHz or 2.5 MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tTXCYC
E_TCK0_MDC1
VIHS
E_TX03_TX11
E_TX02_TX10
E_TX01
E_TX00
E_TXEN0
E_TXER0_TXEN1
114
CONFIDENTIAL
VIHS
VILS
tTXCYCH
tTXCYCL
VOH
VOL
tMIITX
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 MII receiving (100Mbps/10Mbps)
(ETHVcc = 3.0V to 3.6V, 4.5V to 5.5V)
(Vss = 0V, Ta = - 40°C to + 85°C, CL=25pF)
Parameter
Receiving Clock
Cycle time*
Receiving Clock
High pulse width duty
Receiving Clock
Low pulse width duty
Symbol
tRXCYC
Pin name
Conditions
100 Mbps,
40 ns (typical)
10 Mbps,
400 ns (typical)
tRXCYCH /
tRXCYC
tRXCYCL /
tRXCYC
E_RXCK0_REFCK
tRXCYCH
E_RXCK0_REFCK
tRXCYCL
E_RXCK0_REFCK
Value
Min Max
-
-
ns
-
-
ns
35
65
%
35
65
%
-
ns
-
ns
E_RX03_RX11,
E_RX02_RX10,
Received data → REFCK ↑
E_RX01,
tMIIRXS
5
Setup time
E_RX00,
E_RXDV0,
E_RXER0_RXDV1
E_RX03_RX11,
E_RX02_RX10,
REFCK ↑ → Received data
E_RX01,
tMIIRXH
2
Hold time
E_RX00,
E_RXDV0,
E_RXER0_RXDV1
*: The receiving clock 100 Mbps is fixed to 25 MHz or 2.5 MHz in the MII specifications.
The clock accuracy should meet the PHY-device specifications.
tRXCYC
E_RXCK0_REFCK
VIHS
E_RX03_RX11
E_RX02_RX10
E_RX01
E_RX00
E_RXDV0
E_RXER0_RXDV1
VIHS
tRXCYCH
VIHS
VILS
tMIIRXS
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Unit
VILS
tRXCYCL
VIHS
VILS
tMIIRXH
115
D a t a S h e e t
5.
12-bit A/D Converter
 Electrical characteristics for the A/D converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Min
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
VZT
ANxx
-
VFST
ANxx
-
-
-
Ts
-
Compare clock cycle*3
Tcck
State transition time to
operation permission
Value
Typ
-
Max
Unit
12
± 4.5
± 2.5
± 15
bit
LSB
LSB
AVRH = 2.7 V to
mV
5.5 V
AVRH ± 15 mV
1.0*1
1.2*1
*2
*2
-
-
μs
-
50
-
2000
ns
Tstt
-
-
-
1.0
μs
Analog input capacity
CAIN
-
-
-
12.9
pF
Analog input resistance
RAIN
-
-
-
Conversion time
Sampling time
Remarks
2
3.8
4
ns
kΩ
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
Interchannel disparity
LSB
Analog port input
ANxx
5
μA
current
Analog input voltage
ANxx
AVSS
AVRH
V
Reference voltage
AVRH
2.7
AVCC
V
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz sampling time: 300 ns
compare time: 700 ns
AVcc < 4.5 V, HCLK=120 MHz sampling time: 500 ns
compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3
Family PERIPHERAL MANUAL Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data
sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
116
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
Rext
ANxx
Analog input pin
Analog
signal source
Comparator
RAIN
CAIN
(Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9
Ts : Sampling time
RAIN : input resistance of A/D = 2 kΩ at 4.5 ≤ AVCC ≤ 5.5
input resistance of A/D = 3.8 kΩ at 2.7 ≤ AVCC < 4.5
CAIN : input capacity of A/D = 12.9 pF at 2.7 ≤ AVCC ≤ 5.5
Rext : Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc : Compare time
Tcck : Compare clock cycle
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
117
D a t a S h e e t
 Definition of 12-bit A/D Converter Terms
 Resolution
 Integral Nonlinearity
 Differential Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion
characteristics.
: Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
Actual conversion
characteristics
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVss
Actual conversion characteristics
AVRH
AVss
AVRH
Analog input
Integral Nonlinearity of digital output N =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Differential Nonlinearity of digital output N =
1LSB =
N
VZT
VFST
VNT
118
CONFIDENTIAL
:
:
:
:
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
6.
USB characteristics
The USB characteristics of ch.0 and those of ch.1 are the same.
USBVcc0 and USBVcc1 are described as USBVcc below.
(Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Input "H" level voltage
Input "L" level voltage
Input
charact- Differential input
eristics sensitivity
Different common mode
range
Pin
Conditions
name
Min
Value
Max
Unit Remarks
VIH
-
2.0
VIL
-
Vss - 0.3
USBVcc + 0.3 V
0.8
V
*1
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
Minimum differential input
sensitivity [V]
External
pull-down
Output "H" level voltage
VOH
2.8
3.6
V *3
resistance=
15kΩ
UDP0, External
UDM0
pull-up
Output "L" level voltage
VOL
0.0
0.3
V *3
resistance=
Output
1.5kΩ
charact- Crossover voltage
VCRS
1.3
2.0
V *4
eristics
Rise time
tFR
Full-Speed
4
20
ns *5
Fall time
tFF
Full-Speed
4
20
ns *5
Rise/ fall time matching
tFRFM
Full-Speed
90
111.11
% *5
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rise time
tLR
Low-Speed
75
300
ns *7
Fall time
tLF
Low-Speed
75
300
ns *7
Rise/ fall time matching
tLRFM
Low-Speed
80
125
% *7
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within V IL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within
0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
119
D a t a S h e e t
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to ground and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
120
CONFIDENTIAL
Falling time
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30Ω (recommendation value 27 Ω)series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure " Low-Speed Load (Compliance Load)" for conditions of external load.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
121
D a t a S h e e t
 Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
 Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
 Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
122
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
7.
Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(Ta = - 40°C to + 85°C)
Parameter
Detected voltage
Released voltage
Symbol Conditions
VDL
VDH
-
Min
Value
Typ
Max
2.25
2.30
2.45
2.50
2.65
2.70
Unit
V
V
Remarks
When voltage drops
When voltage rises
(2) Interrupt of Low-Voltage Detection
(Ta = - 40°C to + 85°C)
Parameter
Symbol Conditions
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
LVD stabilization
wait time
TLVDW
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
-
Min
Value
Typ Max
Unit
2.58
2.67
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
2.8
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.02
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
-
-
4032 ×
tCYCP*
μs
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
*: tCYCP indicates the APB2 bus clock cycle time.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
123
D a t a S h e e t
8.
Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(Vcc = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Parameter
Sector erase
time
Large Sector
Value
Typ*
Max*
0.7
3.7
Unit
s
Small Sector
Half word (16-bit)
write time
0.3
1.1
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time.
Includes write time prior to internal
Chip erase time
13.6
68
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000
cycle of erase/write.
12
384
μs
(2) Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
1,000
20*
10,000
100,000
*: At average + 85°C
124
CONFIDENTIAL
Remarks
10*
5*
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
9.
Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
 Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Parameter
Symbol
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Value
Typ
Max*
tCYCC
Unit
ns
40
80
μs
453
737
μs
Sub TIMER mode
453
737
μs
STOP mode
453
737
μs
Low-speed CR TIMER mode
Ticnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
 Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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125
D a t a S h e e t
 Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
126
CONFIDENTIAL
 The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode.
 When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
 Return Count Time
(VCC = 2.7V to 5.5V, Ta = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
321
461
μs
321
461
μs
441
701
μs
Sub TIMER mode
441
701
μs
STOP mode
441
701
μs
SLEEP mode
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Low-speed CR TIMER mode
Trcnt
Remarks
*: The maximum value depends on the accuracy of built-in CR.
 Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Start
127
D a t a S h e e t
 Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
*: Internal resource reset
Notes:
128
CONFIDENTIAL
Start
is not included in return factor by the kind of Low-Power consumption mode.
 The return factor is different in each Low-Power consumption modes.
See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3
Family PERIPHERAL MANUAL.
 When interrupt recoveries, the operation mode that CPU recoveries depends on the state before
the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption
Mode" in "FM3 Family PERIPHERAL MANUAL".
 The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on
Reset Timing in 4. AC Characteristics in ■Electrical Characteristics" for the detail
on the time during the power-on reset/low -voltage detection reset.
 When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main
clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or
the main PLL clock stabilization wait time.
 The internal resource reset means the watchdog reset and the CSV reset.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9BFD16SPMC-GE1
512 Kbyte
64 Kbyte
MB9BFD17SPMC-GE1
768 Kbyte
96 Kbyte
MB9BFD18SPMC-GE1
1 Mbyte
128 Kbyte
MB9BFD16TPMC-GE1
512 Kbyte
64 Kbyte
MB9BFD17TPMC-GE1
768 Kbyte
96 Kbyte
MB9BFD18TPMC-GE1
1 Mbyte
128 Kbyte
MB9BFD16TBGL-GE1
512 Kbyte
64 Kbyte
MB9BFD17TBGL-GE1
768 Kbyte
96 Kbyte
MB9BFD18TBGL-GE1
1 Mbyte
128 Kbyte
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Package
Packing
Plastic · LQFP 144-pin
(0.5mm pitch), (FPT-144P-M08)
Plastic · LQFP 176-pin
(0.5mm pitch), (FPT-176P-M07)
Tray
Plastic · PFBGA 192-pin
(0.8mm pitch), (BGA-192P-M06)
129
D a t a S h e e t
 PACKAGE DIMENSIONS
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.5 0
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
132
0.145±0.055
(.006±.002)
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
LEAD No.
45
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
2004-2010 FUJITSU SEMICONDUCTOR LIMITED F176013S-c-1-3
130
CONFIDENTIAL
"A"
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.08(.003) M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
144-pin plastic LQFP
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20 g
Code
(Reference)
P-LFQFP144-20×20-0.50
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
Lead pitch
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008 (Mounting height)
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
131
D a t a S h e e t
192-ball plastic FBGA
Ball pitch
0.80 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.45 mm Max.
Weight
0.34 g
(BGA-192P-M06)
192-ball plastic FBGA
(BGA-192P-M06)
10.40(.409)REF
12.00±0.10(.472±.004)
0.20(.008) S B
B
0.80(.031)
REF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
12.00±0.10
(.472±.004)
(INDEX AREA)
10.40(.409)
REF
0.20(.008) S A
0.35±0.10
(.014±.004)
(Stand off)
1.25±0.20
(.049±.008)
(Seated height)
P N M L K J H G F E D C B A
INDEX
192-ø0.45±0.10
(192-ø.018±.004)
ø0.08(.003) M S A B
S
0.10(.004) S
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED B192006S-c-1-3
132
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
 Major Changes
Page
Section
Revision 1.0
DESCRIPTION
1
FEATURES
3
• Multi-function Serial Interface
(Max 8channels)
PRODUCT LINEUP
7
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
PIN ASSIGNMENT
9 to 11
I/O CIRCUIT TYPE
55
HANDLING DEVICES
62 to 64
BLOCK DIAGRAM
65
ELECTRICAL CHARACTERISTICS
77
2. Recommended Operating Conditions
80
3. DC Characteristics
(1) Current Rating
83
85
113
4. AC Characteristics
(1) Main Clock Input Characteristics
(4-1) Operating Conditions of Main and
USB/Ethernet PLL (In the case of using main clock
for input of PLL)
(4-2) Operating Conditions of Main PLL (In the
case of using high-speed internal CR)
• Management Interface
5. 12-bit A/D Converter
• Electrical characteristics for the A/D converter
116
119
123
124
Revision 1.1
Revision 2.0
2
2
3
6. USB Characteristics
7. Low-voltage Detection Characteristics
(2) Interrupt of Low-Voltage Detection
8. Flash Memory Write/Erase Characteristics
Erase/write cycles and data hold time
Features
USB Interface
Ethernet-MAC
Features
USB Interface
Features
External Bus Interface
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
CONFIDENTIAL
Change Results
Preliminary → Data Sheet
Corrected the description.
Revised the following description.
"4 channels with 16-byte FIFO"
→"4 channels with 16steps×9-bit FIFO"
Added the following description.
"ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO"
Added the description of "Note".
Added the following description to "Type H".
IOH = -20.5mA, IOL = 18.5mA
• Revised the description of "•Power supply pins".
• Revised the description of "•C pin".
• Added the description of "•Base Timer".
Corrected the figure.
• TIOA: input → input/output
• TIOB: output → input
• Corrected the value of "Analog reference voltage (AVRH)".
Min: AVSS → 2.7V
• Added the "Smoothing capacitor (CS)".
• Added the footnote.
• Revised the value of "TBD".
• Revised the unit.
• Deleted "and estimated values."
Added "Internal operating clock frequency (FCM): Master clock".
• Added "Main PLL clock frequency (FCLKPLL)".
• Added "USB/Ethernet clock frequency (FCLKSPLL)".
Revised the value of "MDC ↑ → MDIO Hold time".
Min: 20 → 0
• Deleted "(Preliminary value)".
• Added the Symbol.
• Revised the value of "TBD".
• Revised the maximum value of "Power supply current (analog +
digital)":
A/D 1unit operation: Typ: 0.47 → 0.57
When A/D stops: Typ: 0.01 → 0.06
• Revised the value of "Reference power supply current (between
AVRH to AVSS)"
When A/D stops: Typ: 0.01 → 0.06
• Deleted the following Pin name.
- "Sampling time"
- "Compare clock cycle"
- "State transition time to operation permission"
- "Analog input capacity"
- "Analog input resistance"
• Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Corrected the condition of " Output L level voltage".
External pull-down → External pull-up
Corrected the value of "LVD stabilization wait time (TLVDW)".
Max: 2240 × tcyc → 4032 × tCYCP
Deleted "(targeted value)".
Company name and layout design change
Added the description of PLL for USB and Ethernet
Added the size of each EndPoint
Added the description of Maximum area size
133
D a t a S h e e t
Page
Section
9, 10
Pin Assignment
52 to 57
I/O Circuit Type
62
Handling Devices
62
Handling Devices
Crystal oscillator circuit
63
65
67
68
75, 76
77
79, 80
84
86
88 to 90
97 to 104
116
125 to 128
129
134
CONFIDENTIAL
Handling Devices
C Pin
Block Diagram
Memory Map
· Memory map(1)
Memory Map
· Memory map(2)
Electrical Characteristics
1. Absolute Maximum Ratings
Electrical Characteristics
2. Recommended Operation Conditions
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Electrical Characteristics
4. AC Characteristics
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
9. Return Time from Low-Power Consumption
Mode
Ordering Information
Change Results
Added SWCLK and SWDIO and SWO
· Added the description of I2C to the type of E, F, I, L
· Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
"Evaluate oscillation of your using crystal oscillator by your mount
board."
Changed the description
Modified the block diagram
Modified the area of "Extarnal Device Area"
Added the summary of Flash memory sector and the note
· Added the Clamp maximum current
· Added the output current of P80, P81, P82, P83
· Added about +B input
· Modified the minimum value of Analog reference voltage
· Added Smoothing capacitor
· Added the note about less than the minimum power supply voltage
· Changed the table format
· Added Main TIMER mode current
· Added Flash Memory Current
· Moved A/D Converter Current
Added Frequency stability time at Built-in high-speed CR
· Added Time until releasing Power-on reset
· Changed the figure of timing
Modified Data output time
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
· Added Conversion time at AVcc < 4.5 V
· Modified Stage transition time to operation permission
· Modified the minimum value of Reference voltage
Added Return Time from Low-Power Consumption Mode
Change to full part number
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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D a t a S h e e t
136
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015
D a t a S h e e t
February 10, 2015, MB9BD10T-DS706-00031-2v0-E
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137
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Spansion All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM , Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
138
CONFIDENTIAL
MB9BD10T-DS706-00031-2v0-E, February 10, 2015