Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 1/8 CYStech Electronics Corp. P-Channel Logic Level Enhancement Mode Power MOSFET MTEJ0P20L3 BVDSS -200V ID RDSON@VGS=-10V, ID=-1A -1.2A 0.95Ω (typ) RDSON@VGS=-6V, ID=-0.5A 1.0Ω (typ) Features • Low Gate Charge • Simple Drive Requirement • Pb-free lead plating & halogen-free package Equivalent Circuit Outline SOT-223 MTEJ0P20L3 D S D G：Gate D：Drain S：Source G Absolute Maximum Ratings (TC=25°C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current @ VGS=-10V, TC=25°C Continuous Drain Current @ VGS=-10V, TC=100°C Continuous Drain Current @ VGS=-10V, TA=25°C Continuous Drain Current @ VGS=-10V, TA=70°C Pulsed Drain Current *1 Avalanche Current Avalanche Energy @ L=10mH, ID=-1.6A, RG=25Ω Repetitive Avalanche Energy @ L=0.05mH *2 Total Power Dissipation @TA=25℃ Total Power Dissipation @TA=100℃ Operating Junction and Storage Temperature Range MTEJ0P20L3 Symbol Limits VDS VGS -200 ±30 -1.6 -1 -1.2 -0.96 -6.4 -1.6 13 2 2.5 1 -55~+150 ID IDM IAS EAS EAR Pd Tj, Tstg Unit V A mJ W °C CYStek Product Specification Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 2/8 CYStech Electronics Corp. Note : *1. Pulse width limited by maximum junction temperature *2. Duty cycle ≤ 1% Thermal Data Parameter Thermal Resistance, Junction-to-case, max Thermal Resistance, Junction-to-ambient, max Symbol Rth,j-c Rth,j-a Value 25 50 (Note) Unit °C/W °C/W 2 Note : Surface mounted on a 1 in pad of 2 oz. copper, t≤10s; 110°C/W when mounted on minimum copper pad. Characteristics (Tc=25°C, unless otherwise specified) Symbol Static BVDSS VGS(th) IGSS IDSS RDS(ON) *1 GFS *1 Dynamic Qg *1, 2 Qgs *1, 2 Qgd *1, 2 td(ON) *1, 2 tr *1, 2 td(OFF) *1, 2 tf *1, 2 Ciss Coss Crss Source-Drain Diode IS *1 ISM *3 VSD *1 trr Qrr Min. Typ. Max. -200 -2 - -3 0.95 1 2 -4 ±100 -1 -25 1.3 1.3 - - 14 4 4.8 8 4 22 6 812 37 18 - - -0.8 80 100 -1.6 -6.4 -1.2 - Unit Test Conditions S VGS=0, ID=-250μA VDS =VGS, ID=-250μA VGS=±30, VDS=0 VDS =-160V, VGS =0 VDS =-160V, VGS =0, TJ=125°C VGS =-10V, ID=-1A VGS =-6V, ID=-0.5A VDS =-5V, ID=-0.5A nC ID=-1A, VDS=-160V, VGS=-10V ns VDS=-100V, ID=-1A, VGS=-10V, RG=6Ω pF VGS=0V, VDS=-25V, f=1MHz V nA μA Ω A V ns nC IS=-1A, VGS=0V IF=-1A, dIF/dt=100A/μs Note : *1.Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2% *2.Independent of operating temperature *3.Pulse width limited by maximum junction temperature. MTEJ0P20L3 CYStek Product Specification Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 3/8 CYStech Electronics Corp. Typical Characteristics Brekdown Voltage vs Ambient Temperature Typical Output Characteristics 1.4 10V 9V 8V 7V 6V 5V 4.5 -ID, Drain Current(A) -BVDSS, Normalized Drain-Source Breakdown Voltage 5.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -VGS=4V 1.2 1 0.8 0.6 ID=-250μA, VGS=0V 0.5 0.4 0.0 0 3 6 -VDS, Drain-Source Voltage(V) -60 9 Static Drain-Source On-State resistance vs Drain Current 180 1.6 VGS=0V 1.4 VGS=-4.5V -VSD, Source-Drain Voltage(V) RDS(on), Static Drain-Source On-State Resistance(Ω) 20 60 100 140 Tj, Junction Temperature(°C) Reverse Drain Current vs Source-Drain Voltage 1.6 VGS=-6V 1.2 1 0.8 0.6 VGS=-10V 0.4 1.4 1.2 Tj=25°C 1 0.8 0.6 Tj=150°C 0.4 0.2 0.2 0 0.01 0.1 1 -ID, Drain Current(A) 0 10 1 2 3 4 5 -IDR , Reverse Drain Current(A) Drain-Source On-State Resistance vs Junction Tempearture Static Drain-Source On-State Resistance vs Gate-Source Voltage 2.4 1.8 R DS(ON), Normalized Static DrainSource On-State Resistance 2 R DS(ON), Static Drain-Source OnState Resistance(mΩ) -20 ID=-1A 1.6 1.4 1.2 1 0.8 0.6 VGS=-10V, ID=-1A 2 1.6 1.2 0.8 RDS(ON) @Tj=25°C : 0.95Ωtyp. 0.4 0.4 0 MTEJ0P20L3 2 4 6 8 -VGS, Gate-Source Voltage(V) 10 -60 -20 20 60 100 140 Tj, Junction Temperature(°C) 180 CYStek Product Specification Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 4/8 CYStech Electronics Corp. Typical Characteristics(Cont.) Threshold Voltage vs Junction Tempearture Capacitance vs Drain-to-Source Voltage -VGS(th), Normalized Threshold Voltage 1000 Capacitance---(pF) Ciss 100 C oss Crss ID=-250μA 1.2 1 0.8 0.6 0.4 10 0.1 1.4 1 10 -VDS , Drain-Source Voltage(V) -60 100 -20 20 10 140 180 10 -VGS, Gate-Source Voltage(V) RDS(ON) Limited -ID, Drain Current (A) 100 Gate Charge Characteristics Maximum Safe Operating Area 10μs 1 100μs 1ms 0.1 TA=25°C, Tj=150°C, VGS=-10V, RθJA=50°C/W Single Pulse 10ms DC 8 6 4 2 VDS=-160V ID=-1A 100ms 0 0.01 0.1 1 10 100 -VDS, Drain-Source Voltage(V) 0 1000 Maximum Drain Current vs Junction Temperature 4 8 12 16 Qg, Total Gate Charge(nC) 20 Typical Transfer Characteristics 1.4 5 VDS=-10V 1.2 4 1 -ID, Drain Current(A) -ID, Maximum Drain Current(A) 60 Tj, Junction Temperature(°C) 0.8 0.6 0.4 0.2 TA=25°C, VGS=-10V, RθJA=50°C/W 0 3 2 1 0 25 MTEJ0P20L3 50 75 100 125 150 Tj, JunctionTemperature(°C) 175 0 2 4 6 8 -VGS, Gate-Source Voltage(V) 10 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 5/8 Typical Characteristics(Cont.) Forward Transfer Admittance vs Drain Current Single Pulse Maximum Power Dissipation 50 Peak Transient Power (W) GFS, Forward Transfer Admittance(S) 10 1 0.1 VDS=-5V 0.01 0.1 1 -ID, Drain Current(A) 30 20 10 Pulsed Ta=25°C 0.01 0.001 TJ(MAX) =150°C TA=25°C θJA=50°C/W 40 10 0 0.0001 0.001 0.01 0.1 Pulse Width(s) 1 10 Transient Thermal Response Curves r(t), Normalized Effective Transient Thermal Resistance 1 0.1 D=0.5 1.RθJA(t)=r(t)*RθJA 2.Duty Factor, D=t1/t2 3.TJM -TA=PDM*RθJA(t) 4.RθJA=50°C/W 0.2 0.1 0.05 0.02 0.01 Single Pulse 0.01 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 t1, Square Wave Pulse Duration(s) Ordering Information Device MTEJ0P20L3-0-T3-G MTEJ0P20L3 Package SOT-223 (Pb-free lead plating and halogen-free package) Shipping 2500 pcs / Tape & Reel CYStek Product Specification CYStech Electronics Corp. Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 6/8 Reel Dimension Carrier Tape Dimension MTEJ0P20L3 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 7/8 Recommended wave soldering condition Product Peak Temperature Soldering Time Pb-free devices 260 +0/-5 °C 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Sn-Pb eutectic Assembly Average ramp-up rate 3°C/second max. (Tsmax to Tp) Preheat 100°C −Temperature Min(TS min) −Temperature Max(TS max) 150°C −Time(ts min to ts max) 60-120 seconds Time maintained above: −Temperature (TL) 183°C − Time (tL) 60-150 seconds Peak Temperature(TP) 240 +0/-5 °C Time within 5°C of actual peak 10-30 seconds temperature(tp) Ramp down rate 6°C/second max. 6 minutes max. Time 25 °C to peak temperature Pb-free Assembly 3°C/second max. 150°C 200°C 60-180 seconds 217°C 60-150 seconds 260 +0/-5 °C 20-40 seconds 6°C/second max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface. MTEJ0P20L3 CYStek Product Specification Spec. No. : C897L3 Issued Date : 2013.03.21 Revised Date : Page No. : 8/8 CYStech Electronics Corp. SOT-223 Dimension A Marking: B Device Name C 1 2 EJ0P20 Date Code 3 D E F H G Style: Pin 1.Gate 2.Drain 3.Source a1 I a2 3-Lead SOT-223 Plastic Surface Mounted Package CYStek Package Code: L3 *: Typical Inches Min. Max. 0.1142 0.1220 0.2638 0.2874 0.1299 0.1457 0.0236 0.0315 *0.0906 0.2480 0.2638 DIM A B C D E F Millimeters Min. Max. 2.90 3.10 6.70 7.30 3.30 3.70 0.60 0.80 *2.30 6.30 6.70 DIM G H I a1 a2 Inches Min. Max. 0.0551 0.0709 0.0098 0.0138 0.0008 0.0039 *13o 0o 10 o Millimeters Min. Max. 1.40 1.80 0.25 0.35 0.02 0.10 *13o 0o 10 o Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material: • Lead: Pure tin plated. • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. MTEJ0P20L3 CYStek Product Specification