STMicroelectronics M36DR432AD10ZA6T 32 mbit 2mb x16, dual bank, page flash memory and 4 mbit 256kb x16 sram, multiple memory product Datasheet

M36DR432AD
M36DR432BD
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory
and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product
FEATURES SUMMARY
■ Multiple Memory Product
Figure 1. Package
– 1 bank of 32 Mbit (2Mb x16) Flash Memory
– 1 bank of 4 Mbit (256Kb x16) SRAM
■ SUPPLY VOLTAGE
– VDDF = VDDS =1.65V to 2.2V
– VPPF = 12V for Fast Program (optional)
■
ACCESS TIMES: 85ns, 100ns, 120ns
■
LOW POWER CONSUMPTION
■
ELECTRONIC SIGNATURE
FBGA
– Manufacturer Code: 0020h
Stacked LFBGA66 (ZA)
12 x8mm
– Top Device Code, M36DR432AD: 00A0h
– Bottom Device Code, M36DR432BD: 00A1h
FLASH MEMORY
■ MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit, 28 Mbit
– Parameter Blocks (Top or Bottom location)
■
PROGRAMMING TIME
– 10µs by Word typical
■
ERASE SUSPEND and RESUME MODES
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
20 YEARS DATA RETENTION
– Double Word Program Option
■
ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 Words
– Defectivity below 1ppm/year
– Page Access: 35ns
– Random Access: 85ns, 100ns, 120ns
■
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
■
SRAM
■ 4 Mbit (256Kb x16)
■
LOW VDDS DATA RETENTION: 1.0V
■
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WPF for Block Lock-Down
■
COMMON FLASH INTERFACE (CFI)
– 64 bit Unique Device Identifier
– 64 bit User Programmable OTP Cells
February 2003
1/52
M36DR432AD, M36DR432BD
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A18-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Enable (WF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flash Reset/Power-Down (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VDDF Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VPPF Programming Voltage (11.4V to 12.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSSF Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Chip Enable (ES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRAM Write Enable (WS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Output Enable (GS).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDDS Supply Voltage (1.65V to 2.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Flash Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Flash Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . 13
Flash Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Standby.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Flash Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Dual Bank Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Command Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/52
M36DR432AD, M36DR432BD
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quadruple Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Enter Bypass Mode Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Exit Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Double Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Quadruple Word Program in Bypass Mode Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bank Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Flash Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19
Flash Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Flash Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Polling and Toggle Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3/52
M36DR432AD, M36DR432BD
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Absolute Maximum Ratings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. SRAM DC Characteristics (TA = –40 to 85°C; VDDF = V DDS = 1.65V to 2.2V) . . . . . . . . 28
Figure 8. Flash Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Flash Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Flash Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Flash Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Flash Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. Flash Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Flash Reset/Power-Down AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. Flash Reset/Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Flash Data Polling DQ7 AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22. Flash Data Polling and Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Flash Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16. Flash Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL . . . . . . 38
Figure 18. SRAM Read AC Waveforms, ES or GS Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. SRAM Read AC Characteristics). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low . . . . . . . . . . . . . . . . . . . . . . 40
Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . . . . . 41
Figure 23. SRAM Write AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. SRAM Low V DDS Data Retention AC Waveforms, ES Controlled . . . . . . . . . . . . . . . . . 42
Table 25. SRAM Low VDDS Data Retention Characteristics (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . 43
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline 44
Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . . . 44
4/52
M36DR432AD, M36DR432BD
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 28. Bank A, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 29. Bank B, Top Boot Block Addresses M36DR432AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Bank B, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 31. Bank A, Bottom Boot Block Addresses M36DR432BD . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5/52
M36DR432AD, M36DR432BD
SUMMARY DESCRIPTION
The M36DR432AD/BD is a low-voltage Multiple
Memory Product which combines two memory devices: a 32 Mbit (2Mbit x16) non-volatile Flash
memory and a 4 Mbit SRAM.
The memory is available in a Stacked LFBGA66
12x8mm - 8x8 active ball array, 0.8mm pitch package and supplied with all the bits erased (set to
‘1’).
Figure 2. Logic Diagram
VDDF VPPF VDDS
21
16
A0-A20
DQ0-DQ15
WF
GF
RPF
E1S
M36DR432AD
M36DR432BD
E2S
Address Inputs
A18-A20
Address Inputs for Flash Chip only
DQ0-DQ15
Data Input/Outputs, Command Inputs
VDDF
Flash Power Supply
VPPF
Flash Optional Supply Voltage for Fast
Program & Erase
VSSF
Flash Ground
VDDS
SRAM Power Supply
VSSS
SRAM Ground
NC
Not Connected Internally
EF
Chip Enable
GF
Output Enable
WF
Write Enable
RPF
Reset/Power-Down
WPF
Write Protect input
GS
SRAM control functions
WS
E1S
Chip Enable
E2S
Chip Enable
GS
Output Enable
WS
Write Enable
UBS
Upper Byte Enable
LBS
Lower Byte Enable
UBS
LBS
VSSF
6/52
A0-A17
Flash control functions
EF
WPF
Table 1. Signal Names
VSSS
AI07309b
H
NC
NC
A7
A4
A17
A5
A18
NC
G
GS
UBS
F
LBS
WPF
E
A19
DQ12
RPF
VSSS
D
VPPF
DQ13
NC
WF
A0
A6
DQ11
EF
A3
DQ9
DQ15
C
A9
A10
A13
A8
A
A16
A14
5
B
4
3
A15
2
A11
NC
NC
1
A20
#2
#1
VSSF
A2
DQ8
DQ10
E2S
DQ6
WS
A12
6
GF
A1
DQ0
DQ2
VDDS
DQ4
DQ14
VSSF
7
NC
E1S
DQ1
DQ3
VDDF
DQ5
DQ7
NC
8
NC
NC
#3
NC
NC
#4
AI90204
M36DR432AD, M36DR432BD
Figure 3. TFBGA Connections (Top view through package)
7/52
M36DR432AD, M36DR432BD
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A17). Addresses
A0-A17
are common inputs for the Flash and the SRAM
components. The Address Inputs select the cells
in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command Interface
of the internal state machine. During a write operation, the address inputs for the Flash memory are
latched on the falling edge of the Flash Chip Enable (EF) or Write Enable (WF), whichever occurs
last, whereas for the SRAM array they are latched
on the falling edge of the SRAM Chip Enable lines
(E1S or E2S) or Write Enable (WS). In the rest of
the datasheet, only the Active Low SRAM Chip
Enable line will be discussed. It will be referred to
as ES.
Address Inputs (A18-A20). Addresses A18-A20
are inputs for the Flash component only. They are
latched during a write operation on the falling edge
of Flash Chip Enable (EF) or Write Enable (WF),
whichever occurs last.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address during a Bus Read operation or input a command or
the data to be programmed during a Write Bus operation.
The input is data to be programmed in the Flash or
SRAM memory array or a command to be written
to the C.I. of the Flash memory. Both are latched
on the rising edge of Flash Write Enable (WF) and,
SRAM Chip Enable lines (ES) or Write Enable
(WS). The output is data from the Flash memory
array or SRAM array, the Electronic Signature
Manufacturer or Device codes, the Block Protection status, the Configuration Register status or
the Status Register Data (Polling bit DQ7, Toggle
bits DQ6 and DQ2, Error bit DQ5 or Erase Timer
bit DQ3) depending on the address. Outputs are
valid when Flash Chip Enable (EF) and Output Enable (GF) or SRAM Chip Enable lines (ES) and
Output Enable (GS) are active.
The output is high impedance when both the Flash
chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RPF) is at VIL.
Flash Chip Enable (EF). The Chip Enable input
activates the Flash memory control logic, input
buffers, decoders and sense amplifiers. When
Chip Enable is at VIH the memory is deselected
and the power consumption is reduced to the
standby level.
Flash Output Enable (GF). gates the outputs
through the data buffers during a read operation.
8/52
When Output Enable, GF, is at V IH the outputs are
High impedance.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memory’s Command Interface.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each Flash block. When Write Protect is at VIL,
the locked-down blocks cannot be locked or unlocked. When Write Protect is at VIH, the LockDown is disabled and the Locked-Down blocks
can be locked or unlocked. Refer to Table 8, Read
Protection Register.
Flash Reset/Power-Down (RPF). The Reset/
Power-Down input provides hardware reset of the
Flash memory, and/or Power-Down functions, depending on the Flash Configuration Register status. Reset or Power-Down of the memory is
achieved by pulling RPF to VIL for at least tPLPH.
The Reset/Power-Down function is set in the Configuration Register (see Set Configuration Register Command). If it is set to ‘0’ the Reset function
is enabled, if it is set to ‘1’ the Power-Down function is enabled. After a Reset or Power-Up the
power save function is disabled and all blocks are
locked.
The memory Command Interface is reset on Power Up to Read Array. Either Chip Enable or Write
Enable must be tied to VIH during Power Up to allow maximum security and the possibility to write a
command on the first rising edge of Write Enable.
After a Reset, when the device is in Read, Erase
Suspend Read or Standby, valid data will be output tPHQ7V1 after the rising edge of RPF. If the device is in Erase or Program, the operation will be
aborted and the reset recovery will take a maximum of tPLQ7V. The memory will recover from Reset/Power-Down tPHQ7V2 after the rising edge of
RPF. See Tables 18 and 19, and Figure 12.
VDDF Supply Voltage (1.65V to 2.2V). VDDF provides the power supply to the internal core and I/O
pins of the memory device. It is the main power
supply for all operations (read, program and
erase).
VPPF Programming Voltage (11.4V to 12.6V).
VPPF provides a high voltage power supply for fast
factory programming. VPPF is required to use the
Double Word and Quadruple Word Program commands.
VSSF Ground. VSSF ground is the reference for
the core supply. It must be connected to the system ground.
SRAM Chip Enable (ES). The Chip Enable inputs for SRAM activate the memory control logic,
input buffers and decoders. ES at V IH deselects
M36DR432AD, M36DR432BD
the memory and reduces the power consumption
to the standby level. ES can also be used to control writing to the SRAM memory array, while WS
remains at VIL. It is not allowed to set EF at VIL and
ES at VIL at the same time.
SRAM Write Enable (WS). The Write Enable input controls writing to the SRAM memory array.
WS is active Low.
SRAM Output Enable (GS). The Output Enable
gates the outputs through the data buffers during
a read operation of the SRAM chip. GS is active
Low.
SRAM Upper Byte Enable (UBS). Enables the
upper bytes for SRAM (DQ8-DQ15). UBS is active
Low.
SRAM Lower Byte Enable (LBS). Enables the
lower bytes for SRAM (DQ0-DQ7). LBS is active
Low.
VDDS Supply Voltage (1.65V to 2.2V). VDDS is the
SRAM power supply for all operations.
Note: Each device in a system should have
VDDF and VPPF decoupled with a 0.1µF capacitor close to the pin. See Figure 7, AC Measurement Load Circuit. The PCB trace widths
should be sufficient to carry the required VPPF
program and erase currents.
9/52
M36DR432AD, M36DR432BD
FUNCTIONAL DESCRIPTION
The Flash and SRAM components have separate
power supplies and grounds and are distinguished
by three chip enable inputs: EF for the Flash mem-
ory and ES (E1S and E2S, respectively) for the
SRAM.
Figure 4. Functional Block Diagram
VDDF
VPPF
EF
GF
WF
RPF
Flash Memory
32 Mbit (2Mb x 16)
WPF
A18-A20
A0-A17
VSSF
VDDS
DQ0-DQ15
E1S
E2S
GS
WS
SRAM
4 Mbit (256Kb x 16)
UBS
LBS
VSSS
AI07310b
10/52
M36DR432AD, M36DR432BD
Table 2. Main Operation Modes
Flash Memory
Operation Mode
GF
WF
RPF
WPF
Read
VIL
VIL
VIH
VIH
VIH
SRAM must be disabled
Data Output
Page Read
VIL
VIL
VIH
VIH
VIH
SRAM must be disabled
Data Output
Write
VIL
VIH
VIL
VIH
VIH
SRAM must be disabled
Data Input
Standby
VIH
X
X
VIH
VIH
Any SRAM mode is allowed
Hi-Z
X
X
X
VIL
VIH
Any SRAM mode is allowed
Hi-Z
VIL
VIH
VIH
VIH
VIH
Any SRAM mode is allowed
Hi-Z
Reset/
Power-Down
SRAM
Output Disable
ES
GS
WS
UBS, LBS(1)
EF
DQ15-DQ0
Read
Flash must be disabled
VIL
VIL
VIH
VIL
Data out
Word Read
Write
Flash must be disabled
VIL
VIH
VIL
VIL
Data in Word
Write
VIH
X
X
X
Hi-Z
X
X
X
VIH
Hi-Z
VIH
X
X
X
Hi-Z
X
X
X
VIH
Hi-Z
VIL
VIH
VIH
X
Hi-Z
Standby/Power
Down
Any Flash mode is allowable
Data Retention
Any Flash mode is allowable
Output Disable
Any Flash mode is allowable
Note: 1. X = Don’t care (V IL or VIH).
2. If UBS and LBS are tied together the bus is at 16 bit. For an 8 bit bus configuration use UBS and LBS separately.
11/52
M36DR432AD, M36DR432BD
FLASH MEMORY COMPONENT
The Flash Memory is a 32 Mbit (2Mbit x16) nonvolatile Flash memory that may be erased electrically at block level and programmed in-system on
a Word-by-Word basis using a 1.65V to 2.2V VDDF
supply for the circuitry and a 1.65V to 2.2V VDDQF
supply for the Input/Output pins (in the stacked device, VDDF and VDDQF are tied internally). An optional 12V VPPF power supply is provided to speed
up customer programming.
The Flash device features an asymmetrical block
architecture with an array of 71 blocks divided into
two banks, Banks A and B, providing Dual Bank
operations. While programming or erasing in Bank
A, read operations are possible in Bank B or vice
versa. Only one bank at a time is allowed to be in
program or erase mode. The bank architecture is
summarized in Table 3, and the Block Addresses
are shown in Appendix A. The Parameter Blocks
are located at the top of the memory address
space for the M36DR432AD and, at the bottom for
the M36DR432BD.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the timings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC standards.
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling instant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any accidental programming or erasure. All blocks are locked
at Power Up and Reset.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is divided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, parameter block 0, can be permanently protected by
the user. Figure 5, shows the Flash Security Block
and Protection Register Memory Map.
Table 3. Flash Bank Architecture
12/52
Bank Size
Parameter Blocks
Main Blocks
Bank A
4 Mbits
8 blocks of 4 KWords
7 blocks of 32 KWords
Bank B
28 Mbits
-
56 blocks of 32 KWords
M36DR432AD, M36DR432BD
Figure 5. Flash Security Block and Protection Register Memory Map
PROTECTION REGISTER
88h
SECURITY BLOCK
User Programmable OTP
85h
84h
Parameter Block # 0
Unique device number
81h
80h
Protection Register Lock
2
1
0
AI06185
Flash Bus Operations
The following operations can be performed using
the appropriate bus cycles: Flash Read Array
(Random and Page Modes), Flash Write, Flash
Output Disable, Flash Standby and Flash Reset/
Power-Down, see Table 2, Main Operation
Modes.
Flash Read. Flash Read operations are used to
output the contents of the Memory Array, the Electronic Signature, the Status Register, the CFI, the
Block Protection Status or the Configuration Register status. Read operation of the Flash memory
array is performed in asynchronous page mode,
that provides fast access time. Data is internally
read and stored in a page buffer. The page has a
size of 4 words and is addressed by A0-A1 address inputs. Read operations of the Electronic
Signature, the Status Register, the CFI, the Block
Protection Status, the Configuration Register status and the Security Code are performed as single
asynchronous read cycles (Random Read). Both
Flash Chip Enable EF and Flash Output Enable
GF must be at VIL in order to read the output of the
memory.
Flash Write. Write operations are used to give
commands to the memory or to latch Input Data to
be programmed. A write operation is initiated
when Chip Enable EF and Write Enable WF are at
VIL with Output Enable GF at VIH. Addresses are
latched on the falling edge of WF or EF whichever
occurs last. Commands and Input Data are
latched on the rising edge of WF or EF whichever
occurs first. Noise pulses of less than 5ns typical
on EF, WF and GF signals do not start a write cycle.
Flash Output Disable. The data outputs are high
impedance when the Output Enable GF is at VIH
with Write Enable WF at VIH.
Flash Standby. The memory is in standby when
Chip Enable EF is at V IH and the P/E.C. is idle.
The power consumption is reduced to the standby
level and the outputs are high impedance, independent of the Output Enable GF or Write Enable
WF inputs.
Automatic Flash Standby. In Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically enters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while outputs still drive the bus.
Flash Power-Down. The memory is in PowerDown when the Configuration Register is set for/
Power-Down and RPF is at VIL. The power consumption is reduced to the Power-Down level, and
Outputs are high impedance, independent of the
Chip Enable EF, Output Enable GF or Write Enable WF inputs.
Dual Bank Operations. The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in different banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
Flash Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. An internal Program/Erase Controller han13/52
M36DR432AD, M36DR432BD
dles all timings and verifies the correct execution
of the Program and Erase commands. Two bus
write cycles are required to unlock the Command
Interface. They are followed by a setup or confirm
cycle. The increased number of write cycles is to
ensure maximum data security.
The Program/Erase Controller provides a Status
Register whose output may be read at any time to
monitor the progress or the result of the operation.
The Command Interface is reset to Read mode
when power is first applied or exiting from Reset.
Command sequences must be followed exactly.
Any invalid combination of commands will reset
the device to Read mode
Flash Read/Reset Command. The Read/Reset
command returns the device to Read mode. One
Bus Write cycle is required to issue the Read/Reset command and return the device to Read mode.
Subsequent Read operations will read the addressed location and output the data. The write cycle can be preceded by the unlock cycles but it is
not mandatory.
Flash Read CFI Query Command. The
Read
CFI Query command is used to read data from the
Common Flash Interface (CFI) and the Electronic
Signature (Manufacturer or the Device Code, see
Table 5). The Read CFI Query Command consists
of one Bus Write cycle. Once the command is issued the device enters Read CFI mode. Subsequent Bus Read operations read the Common
Flash Interface or Electronic Signature. Once the
device has entered Read CFI mode, only the
Read/Reset command should be used and no other. Issuing the Read/Reset command returns the
device to Read mode.
See Appendix B, Common Flash Interface, Tables
33, 34, and 35 for details on the information contained in the Common Flash Interface memory area.
Auto Select Command. The Auto Select command uses the two unlock cycles followed by one
write cycle to any bank address to setup the command. Subsequent reads at any address will output the Block Protection status, Protection
Register and Protection Register Lock or the Configuration Register status depending on the levels
of A0 and A1 (see Tables 6, 7 and 8). Once the
Auto Select command has been issued only the
Read/Reset command should be used and no other. Issuing the Read/Reset command returns the
device to Read mode.
Set Configuration Register Command. The
Flash component contains a Configuration Register, see Table 7, Configuration Register.
It is used to define the status of the Reset/PowerDown functions. The value for the Configuration
Register is always presented on A0-A15, the other
14/52
address bits are ignored. Address input A10 defines the status of the Reset/Power-Down functions. If it is set to ‘0’ the Reset function is enabled,
if it is set to ‘1’ the Power-Down function is enabled. At Power Up the Configuration Register bit
is set to ‘0’.
The Set Configuration Register command is used
to write a new value to the Configuration Register.
The command uses the two unlock cycles followed
by one write cycle to setup the command and a
further write cycle to write the data and confirm the
command.
Program Command. The Program command
uses the two unlock cycles followed by a write cycle to setup the command and a further write cycle
to latch the Address and Data and start the Program Erase Controller. Read operations within the
same bank output the Status Register after programming has started.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole bank from ’0’ to ’1’. If the Program
command is used to try to set a bit from ‘0’ to ‘1’
Status Register Error bit DQ5 will be set to ‘1’, only
if VPPF is in the range of 11.4V to 12.6V.
Double Word Program Command. This feature
is offered to improve the programming throughput
by writing a page of two adjacent words in parallel.
The VPPF supply voltage is required to be from
11.4V to 12.6V for the Double Word Program command.
The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
two cycles are required to latch the address and
data of the two Words and start the Program Erase
Controller.
The addresses must be the same except for the
A0. The Double Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Double Word Program command
cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Double Word Program command is used to try to
set a bit from ‘0’ to ‘1’ Status Register Error bit DQ5
will be set to ‘1’.
Quadruple Word Program Command. The
Quadruple Word Program command improves the
programming throughput by writing a page of four
adjacent words in parallel. The four words must
differ only for the addresses A0 and A1. The VPPF
supply voltage is required to be from 11.4V to
12.6V for the Quadruple Word Program command.
M36DR432AD, M36DR432BD
The command uses the two unlock cycles followed
by a write cycle to setup the command. A further
four cycles are required to latch the address and
data of the four Words and start the Program
Erase Controller.
The Quadruple Word Program command can be
executed in Bypass mode to skip the two unlock
cycles.
Note that the Quadruple Word Program command
cannot change a bit set to ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits
in a block or in the whole bank from ’0’ to ’1’. If the
Quadruple Word Program command is used to try
to set a bit from ‘0’ to ‘1’ Status Register Error bit
DQ5 will be set to ‘1’.
Enter Bypass Mode Command. The
Bypass
mode is used to reduce the overall programming
time when large memory arrays need to be programmed.
The Enter Bypass Mode command uses the two
unlock cycles followed by one write cycle to set up
the command. Once in Bypass mode, it is imperative that only the following commands be issued:
Exit Bypass, Program, Double Word Program or
Quadruple Word Program.
Exit Bypass Mode Command. The Exit Bypass
Mode command uses two write cycles to setup
and confirm the command. The unlock cycles are
not required. After the Exit Bypass Mode command, the device resets to Read mode.
Program in Bypass Mode Command. The
Program in Bypass Mode command can be issued when the device is in Bypass mode (issue a
Enter Bypass Mode command). It uses the same
sequence of cycles as the Program command with
the exception of the unlock cycles.
Double Word Program in Bypass Mode Command. The Double Word Program in Bypass
Mode command can be issued when the device is
in Bypass mode (issue a Enter Bypass Mode command). It uses the same sequence of cycles as the
Double Word Program command with the exception of the unlock cycles.
Quadruple Word Program in Bypass Mode
Command. The Quadruple Word Program in Bypass Mode command can be issued when the device is in Bypass mode (issue a Enter Bypass
Mode command). It uses the same sequence of
cycles as the Quadruple Word Program command
with the exception of the unlock cycles.
Block Lock Command. The Block Lock command is used to lock a block and prevent Program
or Erase operations from changing the data in it.
All blocks are locked at power-up or reset.
Three Bus Write cycles are required to issue the
Block Lock command.
The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block Lock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the Lock Status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/
power-up. They are cleared by a Blocks Unlock
command. Refer to the section, Block Locking, for
a detailed explanation.
Block Unlock Command. The Blocks Unlock
command is used to unlock a block, allowing the
block to be programmed or erased.
Three Bus Write cycles are required to issue the
Blocks Unlock command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block UnLock
command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Table 10 shows
the lock status after issuing a Block Unlock command. Refer to the section, Block Locking, for a
detailed explanation.
Block Lock-Down Command. A locked or unlocked block can be locked-down by issuing the
Block Lock-Down command. A locked-down block
cannot be programmed or erased, or have its protection status changed when WPF is Low, VIL.
When WPF is High, V IH, the Lock-Down function is
disabled and the locked blocks can be individually
unlocked by the Block Unlock command.
Three Bus Write cycles are required to issue the
Block Lock-Down command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Block LockDown command and latches the block address.
The lock status can be monitored for each block
using the Auto Select command. Locked-Down
blocks revert to the locked (and not locked-down)
state when the device is reset on power-down. Table 10 shows the Lock Status after issuing a Block
Lock-Down command. Refer to the section, Block
Locking, for a detailed explanation.
Block Erase Command. The Block Erase command can be used to erase a block. It sets all the
bits within the selected block to ’1’. All previous
data in the block is lost. If the block is protected
then the Erase operation will abort, the data in the
block will not be changed and the device will return
to Read Array mode. It is not necessary to pre-pro■
15/52
M36DR432AD, M36DR432BD
gram the block as the Program/Erase Controller
does it automatically before erasing.
Six Bus Write cycles are required to issue the
command.
■ The first two write cycles unlock the Command
Interface.
■ The third write cycles sets up the command
■ the fourth and fifth write cycles repeat the unlock
sequence
■ the sixth write cycle latches the block address
and confirms the command.
Additional Block Erase confirm cycles can be issued to erase other blocks without further unlock
cycles. All blocks must belong to the same bank; if
a new block belonging to the other bank is given,
the operation is aborted.
The additional Block Erase confirm cycles must be
given within the DQ3 erase timeout period. Each
time a new confirm cycle is issued the timeout period restarts. The status of the internal timer can
be monitored through the level of DQ3, see Status
Register section for more details.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
After the command has been issued the Flash
Read/Reset command will be accepted during the
DQ3 timeout period, after that only the Erase Suspend command will be accepted.
On successful completion of the Block Erase command, the device returns to Read Array mode.
Bank Erase Command. The Bank Erase command can be used to erase a bank. It sets all the
bits within the selected bank to ’1’. All previous
data in the bank is lost. The Bank Erase command
will ignore any protected blocks within the bank. If
all blocks in the bank are protected then the Bank
Erase operation will abort and the data in the bank
will not be changed. It is not necessary to pre-program the bank as the Program/Erase Controller
does it automatically before erasing.
As for the Block Erase command six Bus Write cycles are required to issue the command.
■ The first two write cycles unlock the Command
Interface.
■ The third write cycles sets up the command
■ the fourth and fifth write cycles repeat the unlock
sequence
■ the sixth write cycle latches the block address
and confirms the command.
Once the command is issued the device outputs
the Status Register data when any address within
the bank is read.
16/52
On successful completion of the Bank Erase command, the device returns to Read Array mode.
Erase Suspend Command. The Erase Suspend
command is used to pause a Block Erase operation. In a Dual Bank memory it can be used to read
data within the bank where an Erase operation is
in progress. It is also possible to program data in
blocks not being erased.
One bus write cycle is required to issue the Erase
Suspend command. The Program/Erase Controller suspends the Erase operation within 20µs of
the Erase Suspend command being issued and
bits 7, 6 and/ or 2 of the Status Register are set to
‘1’. The device is then automatically set to Read
mode. The command can be addressed to any
bank.
During Erase Suspend the memory will accept the
Erase Resume, Program, Read CFI Query, Auto
Select, Block Lock, Block Unlock and Block LockDown commands.
Erase Resume Command. The Erase Resume
command can be used to restart the Program/
Erase Controller after an Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command must
be issued to an address within the bank being
erased. The unlock cycles are not required.
Protection Register Program Command. The
Protection Register Program command is used to
Program the Protection Register (One-Time-Programmable (OTP) segment and Protection Register Lock). The OTP segment is programmed 16
bits at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits
to ‘0’.
Four write cycles are required to issue the Protection Register Program command.
■ The first two bus cycles unlock the Command
Interface.
■ The third bus cycle sets up the Protection
Register Program command.
■ The fourth latches the Address and the Data to
be written to the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The OTP segment can be protected by programming bit 1 of the Protection Register Lock. The
segment can be protected by programming bit 1 of
the Protection Register Lock. Bit 1 of the Protection Register Lock also protects bit 2 of the Protection Register Lock. Programming bit 2 of the
Protection Register Lock will result in a permanent
protection of Parameter Block #0 (see Figure 5,
Flash Security Block and Protection Register
Memory Map). Attempting to program a previously
M36DR432AD, M36DR432BD
protected Protection Register will result in a Status
Register error. The protection of the Protection
Register and/or the Security Block is not reversible.
Commands
No of Cycles
Table 4. Flash Commands
1+
Bus Operations
1st
2nd
Add
Data
X
F0h
Add
Data
3rd
Add
Data
4th
Add
5th
Data
Add
Data
6th
Add
Data
7th
Add
Data
Read Memory Array until a new write cycle is initiated.
Read/Reset
3+ 555h
AAh 2AAh
CFI Query
1+
98h
Auto Select
3+ 555h
AAh 2AAh
55h
555h
90h
Set Configuration
Register
4 555h
AAh 2AAh
55h
555h
60h CRD
03h
Program
4 555h
AAh 2AAh
55h
555h
A0h
PA
PD
Double Word
Program
5 555h
AAh 2AAh
55h
555h
40h
PA1
PD1
PA2
PD2
Quadruple Word
Program
5 555h
AAh 2AAh
55h
555h
50h
PA1
PD1
PA2
PD2
Enter Bypass
Mode
3 555h
AAh 2AAh
55h
555h
20h
Exit Bypass
Mode
2
X
90h
X
00h
Program in
Bypass Mode
2
X
A0h
PA
PD
Double Word
Program in
Bypass Mode
3
X
40h
PA1
PD1
PA2
PD2
Quadruple Word
Program in
Bypass Mode
3
X
50h
PA1
PD1
PA2
PD2
PA3
PD3
Block Lock
4 555h
AAh 2AAh
55h
555h
60h
BA
01h
Block Unlock
4 555h
AAh 2AAh
55h
555h
60h
BA
D0h
Block Lock-Down
4 555h
AAh 2AAh
55h
555h
60h
BA
2Fh
Block Erase
6+ 555h
AAh 2AAh
55h
555h
80h
555h
AAh 2AAh
55h
BA
30h
Bank Erase
6 555h
AAh 2AAh
55h
555h
80h
555h
AAh 2AAh
55h
BA
10h
Erase Suspend
1
X
B0h
Read until Toggle stops, then read all the data needed from any Blocks not being
erased then Resume Erase.
Erase Resume
1
BA
30h
Read Data Polling or Toggle Bits until Erase completes or Erase is suspended
another time
55h
Protection
4 555h
Register Program
55h
555h
F0h Read Memory Array until a new write cycle is initiated.
Read CFI and Electronic Signature until a Read/Reset command is issued.
AAh 2AAh
55h
Read Protection Register, Block Protection or
Configuration Register Status until a Read/Reset
command is issued.
Read Data Polling or Toggle Bit until
Program completes.
PA3
PD3
PA4
PD4
Read Data Polling or Toggle Bit until Program completes.
PA
C0h
PA
PA4
PD4
PD
Note: X = Don’t Care, BA = Block Address, PA = Program address, PD = Program Data, CRD = Configuration Register Data. For Coded
cycles address inputs A12-A20 are don’t care.
17/52
M36DR432AD, M36DR432BD
Table 5. Read Electronic Signature
Code
Device
EF
GF
WF
A0
A1
A7-A2
A8-A20
DQ15-DQ0
VIL
VIL
VIH
VIL
VIL
0
X
0020h
M36DR432AD
VIL
VIL
VIH
VIH
VIL
0
X
00A0h
M36DR432BD
VIL
VIL
VIH
VIH
VIL
0
X
00A1h
Manufacturer Code
Device Code
Note: X = Don’t care.
Table 6. Flash Read Block Protection
EF
GF
WF
A0
A1
A20-A12
A7-A2
Other
Addresses
DQ0
DQ1
DQ15-DQ2
Locked Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
1
0
0000h
Unlocked Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
0
0
0000h
Locked-Down
Block
VIL
VIL
VIH
VIL
VIH
Block Address
0
X
X
1
0000h
Block Status
Note: X = Don’t care.
Table 7. Configuration Register
EF
GF
WF
A0
A1
A7-A2
Other Addresses
DQ10
DQ9-DQ0
DQ15-DQ11
Reset
VIL
VIL
VIH
VIH
VIH
0
X
0
Don’t Care
Reset/Power-Down
VIL
VIL
VIH
VIH
VIH
0
X
1
Don’t Care
RPF Function
Note: X = Don’t care.
18/52
M36DR432AD, M36DR432BD
Table 8. Read Protection Register
Word
EF
GF
WF
A20-A8
A7-0
DQ15-8
DQ7-3
DQ2
DQ1
DQ0
Lock
VIL
VIL
VIH
X
80h
XXh
00000b
Security
prot.data
OTP
prot.data
0
Unique ID 0
VIL
VIL
VIH
X
81h
ID data
ID data
ID data
ID data
ID data
Unique ID 1
VIL
VIL
VIH
X
82h
ID data
ID data
ID data
ID data
ID data
Unique ID 2
VIL
VIL
VIH
X
83h
ID data
ID data
ID data
ID data
ID data
Unique ID 3
VIL
VIL
VIH
X
84h
ID data
ID data
ID data
ID data
ID data
OTP 0
VIL
VIL
VIH
X
85h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 1
VIL
VIL
VIH
X
86h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 2
VIL
VIL
VIH
X
87h
OTP data
OTP data
OTP data
OTP data
OTP data
OTP 3
VIL
VIL
VIH
X
88h
OTP data
OTP data
OTP data
OTP data
OTP data
Note: X= Don’t care.
Table 9. Program, Erase Times and Program, Erase Endurance Cycles
M36DR432AD, M36DR432BD
Parameter
Typ
Typical after
100k W/E Cycles
Unit
Max
2.5
0.3
1
s
4
0.8
3
s
Bank Erase (Preprogrammed, Bank A)
3
6
s
Bank Erase (Preprogrammed, Bank B)
20
30
s
Chip Program (1)
20
25
s
Chip Program (Double Word, VPPF = 12V) (1)
8
s
Min
Parameter Block (4 KWord) Erase (Preprogrammed)
Main Block (32 KWord) Erase (Preprogrammed)
Word Program (2)
100
10
µs
Double Word Program (VPPF = 12V)
100
8
µs
Quadruple Word Program (VPPF = 12V)
100
8
µs
Program/Erase Cycles (per Block)
100,000
cycles
Note: 1. Excludes the time needed to execute the sequence for program command.
2. Same timing value if V PPF = 12V
Flash Block Locking
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency. This locking
scheme has two levels of protection.
■ Lock/Unlock - this first level allows softwareonly control of block locking.
■
Lock-Down - this second level requires
hardware interaction before locking can be
changed.
The protection status of each block can be set to
Locked, Unlocked, and Lock-Down. Table 10, defines all of the possible protection states (WPF,
DQ1, DQ0).
Reading a Block’s Lock Status
The lock status of every block can be read in the
Auto Select mode of the device. Subsequent
reads at the address specified in Table 6, will output the protection status of that block. The lock
status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by
the Lock command and cleared by the Unlock
command. It is also automatically set when enter-
19/52
M36DR432AD, M36DR432BD
ing Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It
cannot be cleared by software, only by a hardware
reset or power-down.
The following sections explain the operation of the
locking system.
Locked State
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or
(1,0,1)). Locked blocks are fully protected from
any program or erase. Any program or erase operations attempted on a locked block will reset the
device to Read Array mode. The Status of a
Locked block can be changed to Unlocked or
Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks return to the Locked state after a hardware
reset or when the device is powered-down. The
status of an unlocked block can be changed to
Locked or Locked-Down using the appropriate
software commands. A locked block can be unlocked by issuing the Unlock command.
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their protection status cannot be changed using software commands alone.
A Locked or Unlocked block can be Locked-Down
by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the
device is reset or powered-down.
20/52
The Lock-Down function is dependent on the WPF
input pin. When WPF=0 (VIL), the blocks in the
Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When
WPF=1 (VIH) the Lock-Down function is disabled
(1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the
software command, where they can be erased and
programmed. These blocks can then be re-locked
(1,1,1) and unlocked (1,1,0) as desired while WPF
remains High. When WPF is Low, blocks that were
previously Locked-Down return to the Lock-Down
state (0,1,x) regardless of any changes made
while WPF was High. Device reset or power-down
resets all blocks, including those in Lock-Down, to
the Locked state.
Locking Operations During Erase Suspend
Changes to block lock status can be performed
during an erase suspend by using the standard
locking command sequences to unlock, lock or
lock-down a block. This is useful in the case when
another block needs to be updated while an erase
operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then
check the status register until it indicates that the
erase operation has been suspended. Next write
the desired Lock command sequence to a block
and the lock status will be changed. After completing any desired lock, read, or program operations,
resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase
suspend of the same block, the locking status bits
will be changed immediately, but when the erase
is resumed, the erase operation will complete.
M36DR432AD, M36DR432BD
Table 10. Flash Lock Status
Current
Protection Status(1)
(WPF, DQ1, DQ0)
Next Protection Status(1)
(WPF, DQ1, DQ0)
Current State
Program/Erase
Allowed
After
Block Lock
Command
After
Block Unlock
Command
After Block
Lock-Down
Command
After
WPF transition
1,0,0
yes
1,0,1
1,0,0
1,1,1
0,0,0
1,0,1(2)
no
1,0,1
1,0,0
1,1,1
0,0,1
1,1,0
yes
1,1,1
1,1,0
1,1,1
0,1,1
1,1,1
no
1,1,1
1,1,0
1,1,1
0,1,1
0,0,0
yes
0,0,1
0,0,0
0,1,1
1,0,0
0,0,1(2)
no
0,0,1
0,0,0
0,1,1
1,0,1
0,1,1
no
0,1,1
0,1,1
0,1,1
1,1,1 or 1,1,0 (3)
Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read
in the Auto Select command with A1 = VIH and A0 = VIL.
2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WPF status.
3. A WPF transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110.
Flash Status Register
The Status Register provides information on the
current or previous Program or Erase operations.
Bus Read operations from any address within the
bank, always read the Status Register during Program and Erase operations.
The various bits convey information about the status and any errors of the operation.
The bits in the Status Register are summarized in
Table 12, Status Register Bits. Refer to Tables 11
and 12 in conjunction with the following text descriptions.
Data Polling Bit (DQ7). When Program operations are in progress, the Data Polling bit outputs
the complement of the bit being programmed on
DQ7. For a Double Word Program operation, it is
the complement of DQ7 for the last Word written to
the Command Interface.
During an Erase operation, it outputs a ’0’. After
completion of the operation, DQ7 will output the bit
last programmed or a ’1’ after erasing.
Data Polling is valid and only effective during P/
E.C. operation, that is after the fourth WF pulse for
programming or after the sixth WF pulse for erase.
It must be performed at the address being programmed or at an address within the block being
erased. See Figure 22 for the Data Polling flowchart and Figure 13 for the Data Polling waveforms.
DQ7 will also flag an Erase Suspend by switching
from ’0’ to ’1’ at the start of the Erase Suspend. In
order to monitor DQ7 in the Erase Suspend mode
an address within a block being erased must be
provided. DQ7 will output ’1’ if the read is attempted on a block being erased and the data value on
other blocks. During a program operation in Erase
Suspend, DQ7 will have the same behavior as in
the normal program.
Toggle Bit (DQ6). When Program or Erase operations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6
will toggle following the toggling of either GF or EF.
The operation is completed when two successive
reads give the same output data. The next read
will output the bit last programmed or a ’1’ after
erasing.
The Toggle Bit DQ6 is valid only during P/E.C. operations, that is after the fourth WF pulse for programming or after the sixth WF pulse for Erase.
DQ6 will be set to ’1’ if a read operation is attempted on an Erase Suspend block. When erase is
suspended DQ6 will toggle during programming
operations in a block different from the block in
Erase Suspend.
See Figure 16 for Toggle Bit flowchart and Figure
14 for Toggle Bit waveforms.
Toggle Bit (DQ2). Toggle Bit DQ2, together with
DQ6, can be used to determine the device status
during erase operations.
During Erase Suspend a read from a block being
erased will cause DQ2 to toggle. A read from a
block not being erased will output data. DQ2 will
be set to '1' during program operation and to ‘0’ in
erase operation. If a read operation is addressed
to a block where an erase error has occurred, DQ2
will toggle.
21/52
M36DR432AD, M36DR432BD
Error Bit (DQ5). The Error Bit can be used to
identify if an error occurs during a program or
erase operation.
The Error Bit is set to ‘1’ when a program or erase
operation has failed. When it is set to ‘0’ the program or erase operation was successful.
If any Program command is used to try to set a bit
from ‘0’ to ‘1’ Status Register Error bit DQ5 will be
set to ‘1’, only if VPP is in the range of 11.4V to
12.6V.
The Error Bit is reset by a Read/Reset command.
Erase Timer Bit (DQ3). The Erase Timer bit is
used to indicate the timeout period for an erase
operation.
When the last block Erase command has been entered to the Command Interface and it is waiting
for the erase operation to start, the Erase Timer Bit
is set to ‘0’. When the erase timeout period is finished, DQ3 returns to ‘1’, (80µs to 120µs).
22/52
DQ0, DQ1 and DQ4 are reserved for future use
and should be masked.
Table 11. Polling and Toggle Bits
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
N/A
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
1
Program
M36DR432AD, M36DR432BD
Table 12. Status Register Bits
DQ
7
Name
Data
Polling
Logic Level
’1’
Erase complete or erase block
in Erase Suspend.
’0’
Erase in progress
DQ
Program complete or data of
non erase block during Erase
Suspend.
DQ
Program in progress(2)
’-1-0-1-0-1-0-1-’
DQ
6
Toggle Bit
’-1-1-1-1-1-1-1-’
5
4
3
Erase or Program in progress
Program complete
Erase complete or Erase
Suspend on currently addressed
block
Note
Indicates the P/E.C. status, check
during Program or Erase, and on
completion before checking bits DQ5
for Program or Erase success.
Successive reads output
complementary data on DQ6 while
Programming or Erase operations are
in progress. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
’1’
Program or Erase Error
’0’
Program or Erase in progress
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started.
Only possible command entry is Erase
Suspend
’0’
Erase Timeout Period in
progress
An additional block to be erased in
parallel can be entered to the P/E.C
provided that it belongs to the same
bank
Error Bit
This bit is set to ’1’ in the case of
Programming or Erase failure.
Reserved
Erase Time
Bit
’-1-0-1-0-1-0-1-’
2
Definition
Toggle Bit
1
DQ
1
Reserved
0
Reserved
Erase Suspend read in the
Erase Suspended Block.
Erase Error due to the currently
addressed block (when DQ5 =
’1’).
Program in progress or Erase
complete.
Indicates the erase status and allows
to identify the erased block.
Erase Suspend read on non
Erase Suspend block.
Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.
2. In case of double word program DQ7 refers to the last word input.
23/52
M36DR432AD, M36DR432BD
SRAM COMPONENT
The SRAM is a 4 Mbit (256Kb x16) low-power consumption memory array with low V DDS data retention.
SRAM Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Array, Output Disable, Power Down (see Table 2).
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V IH with
Output Enable (GS) at VIL, Chip Enable ES and
UBS, LBS combinations are asserted.
Valid data will be available at the output pins within
tAVQV after the last stable address, provided that
GS is Low and ES is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t ELQV or
tGLQV) rather than the address. Data out may be
indeterminate at t ELQX and tGLQX, but data lines
will always be valid at tAVQV (see Table 23, Figures
17 and 18).
Write. Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and ES pins are at VIL. Either the Chip Enable input (ES) or the Write Enable input (WS)
must be de-asserted during address transitions for
subsequent write cycles. Write begins with the
concurrence of Chip Enable being active and WS
at VIL. A Write begins at the latest transition
24/52
among ES going to VIL and WS going to VIL.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by
the rising edge of ES or the rising edge of WS,
whichever occurs first.
If the Output is enabled (ES=VIL and GS=VIL),
then WS will return the outputs to high impedance
within t WLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the
rising edge of ES, whichever occurs first, and remain valid for t WHDX and tEHAX (see Table 24, Figure 20, 22, 24).
Standby/Power-Down. The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 23, Figure
19) whenever either Chip Enable is de-asserted
(ES=VIH).
Data Retention. The SRAM data retention performances as V DDS go down to VDR are described
in Table 25 and Figure 24. In ES controlled data
retention mode, minimum standby current mode is
entered when ES ≥ VDDS – 0.2V.
Output Disable. The data outputs are high impedance when the Output Enable (GS) is at VIH
with Write Enable (WS) at VIH.
M36DR432AD, M36DR432BD
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 13. Absolute Maximum Ratings(1)
Symbol
Value
Unit
Ambient Operating Temperature (3)
–40 to 85
°C
TBIAS
Temperature Under Bias
–40 to 125
°C
TSTG
Storage Temperature
–55 to 150
°C
VIO (2)
Input or Output Voltage
–0.5 to VDD(3)+0.5
V
VDDF
Supply Voltage
–0.5 to 2.7
V
VDDS
SRAM Chip Supply Voltage
–0.5 to 2.4
V
VPPF
Program Voltage
–0.5 to 13
V
TA
Parameter
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns.
2. Depends on range.
3. VDD = VDDS = V DDF.
25/52
M36DR432AD, M36DR432BD
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14, Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when relying on the quoted parameters.
Table 14. Operating and AC Measurement Conditions
SRAM
Flash
70
85
100, 120
Parameter
Units
Min
Max
Min
Max
Min
Max
VDDF Supply Voltage
-
-
1.8
2.2
1.65
2.2
V
VDDS Supply Voltage
1.65
2.2
-
-
-
-
V
11.4
12.6
11.4
12.6
V
– 40
85
– 40
85
°C
VPPF Supply Voltage
Ambient Operating Temperature
Load Capacitance (CL)
– 40
85
30
5
Input Rise and Fall Times
30
30
2
Input Pulse Voltages(1)
Input and Output Timing Ref. Voltages(1)
4
pF
4
ns
0 to VDD
0 to VDD
0 to VDD
V
VDD/2
VDD/2
VDD/2
V
Note: 1. VDD = VDDS = V DDF
Figure 6. AC Measurement I/O Waveform
Figure 7. AC Measurement Load Circuit
VDD
VDD
VDD
VDD/2
25kΩ
0V
DEVICE
UNDER
TEST
AI90206
Note: VDD means VDDF = VDDS
0.1µF
25kΩ
CL = 50pF
AI90207
CL includes JIG capacitance
Note: VDD means VDDF = VDDS
Table 15. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
26/52
Test Condition
Min
Max
Unit
VIN = 0V
12
pF
VOUT = 0V
15
pF
M36DR432AD, M36DR432BD
Table 16. Flash DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
0V ≤ VIN ≤ VDD
±1
µA
0V ≤ VOUT ≤ VDD
±5
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
(Read Mode)
EF = VIL, GF = VIH, f =
6MHz
3
6
mA
ICC2
Supply Current
(Power-Down)
RPF = VSS ± 0.2V
2
10
µA
ICC3
Supply Current (Standby)
EF = VDD ± 0.2V
10
50
µA
ICC4 (1)
Supply Current
(Program or Erase)
Word Program, Block Erase
in progress
10
20
mA
ICC5 (1)
Supply Current
(Dual Bank)
Program/Erase in progress
in one Bank, Read in the
other Bank
13
26
mA
VPPF = 12V ± 0.6V
2
5
mA
VPPF ≤ VDD
0.2
5
µA
VPPF = 12V ± 0.6V
100
400
µA
IPPF1
VPPF Supply Current
(Program or Erase)
IPPF2
VPPF Supply Current
(Standby or Read)
VIL
Input Low Voltage
–0.5
0.4
V
VIH
Input High Voltage
VDD – 0.4
VDD + 0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
CMOS
IOH = –100µA
VPPF(2,3)
VPPF Supply Voltage
(Program or Erase)
VDD –0.1
Double Word Program
V
–0.4
VDD + 0.4
V
11.4
12.6
V
Note: 1. Sampled only, not 100% tested.
2. VPPF may be connected to 12V power supply for a total of less than 100 hrs.
3. For standard program/erase operation VPPF is don’t care.
27/52
M36DR432AD, M36DR432BD
Table 17. SRAM DC Characteristics
(TA = –40 to 85°C; VDDF = VDDS = 1.65V to 2.2V)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
IOZ
Output Leakage
Current
0V ≤ VOUT ≤ VDDS, output disabled
-1
+1
+1
µA
IIX
Input Load Current
0V ≤ VIN ≤ VDDS
-1
±1
+1
µA
VDD Standby
Current
ES ≥ VDDS – 0.2V, VIN ≥ VDDS – 0.2V
or VIN ≤ 0.2V, f=0
VDDS = 2.2V
1
10
µA
IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels
VDDS = 2.2V
4
7
mA
IOUT = 0 mA, f = 0Hz
CMOS levels
1
5
mA
IDDS
IDD
Supply Current
VIL
Input Low Voltage
VDDS = 1.65V
–0.5
0.4
V
VIH
Input High Voltage
VDDS = 2.2V
1.4
VDDS +0.2V
V
VOL
Output Low Voltage
VDDS = 1.65V
IOL = 0.1µA
0.2
V
VOH
Output High Voltage
VDDS = 1.65V
IOH = –0.1µA
1.4
V
Note: 1. IDDES and IDDWS are specified with device deselected. If device is read while in erase suspend, current draw is sum of IDDES
and IDDR. If the device is read while in program suspend, current draw is the sum of IDDWS and IDDR.
2. VIN = VIL or VIH
28/52
Note: Write Enable (WF) = High.
DQ0-DQ15
GF
EF
A0-A20
tAVQV
tGLQV
tGLQX
tELQX
tELQV
VALID
tAVAV
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI07312
M36DR432AD, M36DR432BD
Figure 8. Flash Random Read AC Waveforms
29/52
30/52
DQ0-DQ15
GF
EF
A0-A1
A2-A20
tAVQV
tELQV
VALID
VALID
tGLQV
VALID
tAVQV1
VALID
VALID
VALID
VALID
tEHQX
VALID
tGHQX
VALID
tEHQZ
tGHQZ
AI07313
M36DR432AD, M36DR432BD
Figure 9. Flash Page Read AC Waveforms
M36DR432AD, M36DR432BD
Table 18. Flash Read AC Characteristics
M36DR432AD, M36DR432BD
Symbol
Alt
Parameter
Test Condition
85
Min
Max
100
Min
120
Max
Min
Unit
Max
tAVAV
tRC
Address Valid to Next
Address Valid
EF = VIL, GF = VIL
tAVQV
tACC
Address Valid to
Output Valid (Random)
EF = VIL, GF = VIL
85(3)
100
120
ns
tAVQV1
tPAGE
Address Valid to
Output Valid (Page)
EF = VIL, GF = VIL
30(3)
35
45
ns
tELQX (1)
tLZ
Chip Enable Low to
Output Transition
GF = VIL
tELQV (2)
tCE
Chip Enable Low to
Output Valid
GF = VIL
tGLQX (1)
tOLZ
Output Enable Low to
Output Transition
EF = VIL
tGLQV (2)
tOE
Output Enable Low to
Output Valid
EF = VIL
tEHQX
tOH
Chip Enable High to
Output Transition
GF = VIL
tEHQZ (1)
tHZ
Chip Enable High to
Output Hi-Z
GF = VIL
tGHQX
tOH
Output Enable High to
Output Transition
EF = VIL
tGHQZ (1)
tDF
Output Enable High to
Output Hi-Z
EF = VIL
tAXQX
tOH
Address Transition to
Output Transition
EF = VIL, GF = VIL
85(3)
100
0
0
85(3)
0
0
0
0
0
0
0
0
0
0
ns
ns
35
0
ns
ns
35
25
ns
ns
35
25
20(3)
ns
120
25
20(3)
ns
0
100
25(3)
0
120
ns
ns
Note: 1. Sampled only, not 100% tested.
2. GF may be delayed by up to tELQV - tGLQV after the falling edge of EF without increasing tELQV.
3. To be characterized.
31/52
M36DR432AD, M36DR432BD
Figure 10. Flash Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
VALID
tWLAX
tAVWL
tWHEH
EF
tELWL
tWHGL
GF
tGHWL
tWLWH
WF
tWHWL
tDVWH
DQ0-DQ15
tWHDX
VALID
VDDF
tVDHEL
AI07314
Note: Addresses are latched on the falling edge of WF, Data is latched on the rising edge of WF.
Table 19. Flash Write AC Characteristics, Write Enable Controlled
M36DR432AD, M36DR432BD
Symbol
Alt
Parameter
85
Min
100
Max
Min
120
Max
Min
Unit
Max
85(1)
100
120
ns
Chip Enable Low to Write Enable Low
0
0
0
ns
tWP
Write Enable Low to Write Enable High
50(1)
50
50
ns
tDVWH
tDS
Input Valid to Write Enable High
40(1)
50
50
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
0
ns
tWPH Write Enable High to Write Enable Low
30
30
30
ns
tAVAV
tWC
Address Valid to Next Address Valid
tELWL
tCS
tWLWH
tWHWL
tAVWL
tAS
Address Valid to Write Enable Low
0
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
50
50
ns
Output Enable High to Write Enable Low
0
0
0
ns
tGHWL
tVDHEL
tVCS
VDD High to Chip Enable Low
50
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
30
30
30
ns
tPLQ7V
RPF Low to Reset Complete During
Program/Erase
Note: 1. To be characterized.
32/52
15
15
15
µs
M36DR432AD, M36DR432BD
Figure 11. Flash Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
VALID
tELAX
tAVEL
tEHWH
WF
tWLEL
tEHGL
GF
tGHEL
tELEH
EF
tEHEL
tDVEH
DQ0-DQ15
tEHDX
VALID
VDDF
tVDHWL
AI07315
Note: Addresses are latched on the falling edge of EF, Data is latched on the rising edge of EF.
Table 20. Flash Write AC Characteristics, Chip Enable Controlled
M36DR432AD, M36DR432BD
Symbol
Alt
Parameter
85
Min
100
Max
Min
120
Max
Min
Unit
Max
85(1)
100
120
ns
Write Enable Low to Chip Enable Low
0
0
0
ns
tCP
Chip Enable Low to Chip Enable High
50(1)
50
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
40(1)
50
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
50
50
ns
Output Enable High Chip Enable Low
0
0
0
ns
tAVAV
tWC
Address Valid to Next Address Valid
tWLEL
tWS
tELEH
tGHEL
tVDHWL
tVCS
VDD High to Write Enable Low
50
50
50
µs
tEHGL
tOEH
Chip Enable High to Output Enable Low
30
30
30
ns
tPLQ7V
RPF Low to Reset Complete During
Program/Erase
15
15
15
µs
Note: 1. To be characterized
33/52
M36DR432AD, M36DR432BD
Figure 12. Flash Reset/Power-Down AC Waveform
READ
PROGRAM / ERASE
WF
DQ7
DQ7
VALID
VALID
RPF
tPLPH
tPLQ7V
tPHQ7V
AI07316
Table 21. Flash Reset/Power-Down AC Characteristics
M36DR432AD, M36DR432BD
Symbol
Alt
Parameter
Test Condition
85
Min
100
Max
Min
120
Max
Min
Unit
Max
tPHQ7V1
RPF High to Data Valid
(Read Mode)
150
150
150
ns
tPHQ7V2
RPF High to Data Valid
(Reset/Power-Down
enabled)
50
50
50
µs
During Program
10
10
10
µs
During Erase
20
20
20
µs
RPF Low to Reset
Complete
tPLQ7V
tPLPH
34/52
tRP
RPF Pulse Width
50
50
50
ns
DQ0-DQ6/
DQ8-DQ15
DQ7
WF
GF
EF
A0-A20
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
AI07317
MEMORY
ARRAY
READ CYCLE
M36DR432AD, M36DR432BD
Figure 13. Flash Data Polling DQ7 AC Waveforms
35/52
36/52
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,
DQ7-DQ15
DQ6,DQ2
WF
GF
EF
A0-A20
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI06196
M36DR432AD, M36DR432BD
Figure 14. Flash Data Toggle DQ6, DQ2 AC Waveforms
M36DR432AD, M36DR432BD
Table 22. Flash Data Polling and Toggle Bits AC Characteristics
Symbol
M36DR432AD,
M36DR432BD
Parameter
Write Enable High to DQ7 Valid (Program, WF Controlled)
Unit
Min
Max
8
100
µs
0.8
4
s
8
100
µs
0.8
4
s
0
ns
8
100
µs
0.8
4
s
8
100
µs
0.8
4
s
tWHQ7V
Write Enable High to DQ7 Valid (Block Erase, WF Controlled)
Chip Enable High to DQ7 Valid (Program, EF Controlled)
tEHQ7V
tQ7VQV
Chip Enable High to DQ7 Valid (Block Erase, EF Controlled)
Q7 Valid to Output Valid (Data Polling)
Write Enable High to Output Valid (Program)
tWHQV
tEHQV
Write Enable High to Output Valid (Block Erase)
Chip Enable High to Output Valid (Program)
Chip Enable High to Output Valid (Block Erase)
Note: All other timings are defined in Read AC Characteristics
Figure 15. Flash Data Polling Flowchart
Figure 16. Flash Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
DQ6
=
TOGGLES
YES
YES
NO
NO
NO
DQ5
=1
READ DQ6
READ DQ7
DQ6
=
TOGGLES
YES
NO
FAIL
DQ5
=1
YES
YES
DQ7
=
DATA
NO
NO
YES
PASS
AI06197
FAIL
PASS
AI06198
37/52
M36DR432AD, M36DR432BD
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = V IL
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ15
DATA VALID
DATA VALID
AI90217
Note: ES = Low, GS = Low, WS = High.
Figure 18. SRAM Read AC Waveforms, ES or GS Controlled
tAVAV
VALID
A0-A17
tAVQV
tAXQX
tELQV
tEHQZ
ES
tELQX
tBLQV
tBHQZ
UBS, LBS
tBLQX
tGLQV
tGHQZ
GS
tGLQX
DQ0-DQ15
DATA VALID
AI07311
Note: Write Enable (WS) = High.
38/52
M36DR432AD, M36DR432BD
Figure 19. SRAM Standby AC Waveforms
ES
tPU
IDD
tPD
AI07320
Table 23. SRAM Read AC Characteristics)
SRAM
Symbol
Alt
Parameter
70
Min
Unit
Max
tAVAV
tRC
Read Cycle Time
tAVQV
tAA
Address Valid to Output Valid
tAXQX
tOH
Address Transition to Output Transition
tBHQZ
tBHZ
UBS, LBS Disable to Hi-Z Output
25
ns
tBLQV
tBA
UBS, LBS Access Time
45
ns
tBLQX
tBLZ
UBS, LBS Enable to Low-Z Output
tEHQZ
tHZ
Chip Enable High to Output Hi-Z
25
ns
tELQV
tACE
Chip Enable Low to Output Valid
70
ns
tELQX
tLZ
tGHQZ
tOHZ
Output Enable High to Output Hi-Z
25
ns
tGLQV
tEO
Output Enable Low to Output Valid
35
ns
tGLQX
tOLZ
Output Enable Low to Output Transition
tPD
(1)
tPU (1)
Chip Enable Low to Output Transition
70
70
10
ns
5
ns
5
ns
70
0
ns
ns
5
Chip Enable High to Power Down
Chip Enable Low to Power Up
ns
ns
ns
Note: 1. Sampled only. Not 100% tested.
39/52
M36DR432AD, M36DR432BD
Figure 20. SRAM Write AC Waveforms, WS Controlled with GS Low
tAVAV
VALID
A0-A17
tAVWH
tELWH
tAVEL
tWHAX
ES
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
tWHQX
tWLQZ
tDVWH
DQ0-DQ15
tWHDX
INPUT VALID
AI07321
Note: Output Enable (GS) = Low.
Figure 21. SRAM Write AC Waveforms, WS Controlled with GS High
tAVAV
VALID
A0-A17
tAVWH
tELWH
tAVEL
tWHAX
ES
tBLWH
UBS, LBS
tAVWL
tWLWH
WS
GS
tDVWH
DQ0-DQ15
tWHDX
INPUT VALID
AI07322
40/52
M36DR432AD, M36DR432BD
Figure 22. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low
tAVAV
VALID
A0-A17
tEHAX
ES
tAVWH
tBLWH
UBS, LBS
tAVWL
tWLEH
WS
tWHQX
DQ0-DQ15
tWLQZ
tDVWH
tWHDX
INPUT VALID
AI07323
Figure 23. SRAM Write AC Waveforms, ES Controlled
tAVAV
VALID
A0-A17
tAVEL
tELWH
tEHAX
ES
tBLWH
UBS, LBS
tWLWH
WS
tDVWH
DQ0-DQ15
tWHDX
INPUT VALID
AI07324
Note: Output Enable (GS) = High.
41/52
M36DR432AD, M36DR432BD
Table 24. SRAM Write AC Characteristics
SRAM
Symbol
Alt
Parameter
70
Min
tAVAV
tWC
tAVEL
Unit
Max
Write Cycle Time
70
ns
tAS (1)
Address Valid to Chip Enable Low
0
ns
tAVWH
tAW
Address Valid to Write Enable High
60
ns
tAVWL
tAS (1)
Address Valid to Write Enable Low
0
ns
tBLWH
tBW
UBS, LBS Valid to End of Write
tDVWH
tDW
Input Valid to Write Enable High
30
ns
tEHAX
tWR (2)
Chip Enable High to Address Transition
0
ns
tELWH,
tCW (3)
Chip Select to End of Write
60
ns
tWHAX
tWR (2)
Write Enable High to Address Transition
0
ns
tWHDX
tDH
Write Enable High to Input Transition
0
ns
tWHQX
tOW
Write Enable High to Output Transition
10
ns
tWLQZ
tWHZ
Write Enable Low to Output Hi-Z
tWLWH
tWP (4)
Note: 1.
2.
3.
4.
60
Write Enable Pulse Width
25
50
ns
ns
ns
tAS is measured from the address valid to the beginning of write.
tWR is measured from the end or write to the address change. tWR applied in case a write ends as ES or WS goes High.
tCW is measured from ES going Low end of write.
A Write occurs during the overlap (t WP) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the earliest transition when ES goes High and WS goes High. The tWP is measured from the beginning of write to the end of write.
Figure 24. SRAM Low VDDS Data Retention AC Waveforms, ES Controlled
tCDR
VDDS
ES
DATA RETENTION MODE
tR
1.65 V
VDR ≥ 1.0 V
ES ≥ VDDS – 0.2V
AI07325
42/52
M36DR432AD, M36DR432BD
Table 25. SRAM Low VDDS Data Retention Characteristics (1, 2)
Symbol
Parameter
Test Condition
Min
Typical
Max
Unit
0.5
10
µA
2.2
V
IDDDR
Supply Current (Data Retention)
VDDS = 1.0V, ES ≥ VDDS – 0.2V
no input may exceed VDDS + 2V
VDR
Supply Voltage (Data Retention)
ES ≥ VDDS – 0.2V
1
tCDR
Chip Disable to Data Retention
Time
ES ≥ VDDS – 0.2V
0
ns
tRC
ns
tR
Operation Recovery Time
Note: 1. All other Inputs VIH ≤ VDDS – 0.2V or VIL ≤ 0.2V.
2. Sampled only. Not 100% tested.
43/52
M36DR432AD, M36DR432BD
PACKAGE MECHANICAL
Figure 25. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Bottom View Package Outline
D
D2
D1
SE
b
BALL "A1"
e
E E1
FE
FD
SD
ddd
e
A
A2
A1
BGA-Z12
Note: Drawing is not to scale.
Table 26. Stacked LFBGA 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
Max
Typ
Min
1.400
A1
Max
0.0551
0.250
A2
0.0098
1.100
0.0433
b
0.400
0.350
0.450
0.0157
0.0138
0.0177
D
12.000
–
–
0.4724
–
–
D1
5.600
–
–
0.2205
–
–
D2
8.800
–
–
0.3465
–
–
ddd
44/52
inches
0.100
0.0039
E
8.000
–
–
0.3150
–
–
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.600
–
–
0.0630
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
M36DR432AD, M36DR432BD
PART NUMBERING
Table 27. Ordering Information Scheme
Example:
M36 D R 4
32A
D
10 ZA
6
T
Device Type
M36 = MMP (Flash + SRAM)
Architecture
D = Dual Bank, Page Mode
Operating Voltage
R = VDDF = VDDS = 1.65V to 2.2V
SRAM Chip Size & Organization
4 = 4 Mbit (256Kb x 16 bit)
Flash Specification Details
32A = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Top Configuration
32B = 32 Mbit (x16), Dual Bank: 1/8-7/8 partitioning, Bottom Configuration
SRAM Specification Details
D = Asynchronous SRAM, 0.16µm, 70ns speed
Speed
85 = 85ns (to be characterized)
10 = 100ns
12 = 120ns
Package
ZA = LFBGA66: 0.8mm pitch
Temperature Range
6 = –40 to 85°C
Option
T = Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
45/52
M36DR432AD, M36DR432BD
APPENDIX A. BLOCK ADDRESSES
Table 28. Bank A, Top Boot Block Addresses
M36DR432AD
38
32
130000h-137FFFh
37
32
128000h-12FFFFh
36
32
120000h-127FFFh
#
Size
(KWord)
Address Range
14
4
1FF000h-1FFFFFh
35
32
118000h-11FFFFh
13
4
1FE000h-1FEFFFh
34
32
110000h-117FFFh
12
4
1FD000h-1FDFFFh
33
32
108000h-10FFFFh
32
100000h-107FFFh
11
4
1FC000h-1FCFFFh
32
10
4
1FB000h-1FBFFFh
31
32
0F8000h-0FFFFFh
9
4
1FA000h-1FAFFFh
30
32
0F0000h-0F7FFFh
8
4
1F9000h-1F9FFFh
29
32
0E8000h-0EFFFFh
32
0E0000h-0E7FFFh
7
4
1F8000h-1F8FFFh
28
6
32
1F0000h-1F7FFFh
27
32
0D8000h-0DFFFFh
5
32
1E8000h-1EFFFFh
26
32
0D0000h-0D7FFFh
4
32
1E0000h-1E7FFFh
25
32
0C8000h-0CFFFFh
32
0C0000h-0C7FFFh
3
32
1D8000h-1DFFFFh
24
2
32
1D0000h-1D7FFFh
23
32
0B8000h-0BFFFFh
1
32
1C8000h-1CFFFFh
22
32
0B0000h-0B7FFFh
0
32
1C0000h-1C7FFFh
21
32
0A8000h-0AFFFFh
20
32
0A0000h-0A7FFFh
19
32
098000h-09FFFFh
Table 29. Bank B, Top Boot Block Addresses
M36DR432AD
#
Size
(KWord)
18
32
090000h-097FFFh
Address Range
17
32
088000h-08FFFFh
32
080000h-087FFFh
55
32
1B8000h-1BFFFFh
16
54
32
1B0000h-1B7FFFh
15
32
078000h-07FFFFh
53
32
1A8000h-1AFFFFh
14
32
070000h-077FFFh
52
32
1A0000h-1A7FFFh
13
32
068000h-06FFFFh
32
060000h-067FFFh
51
32
198000h-19FFFFh
12
50
32
190000h-197FFFh
11
32
058000h-05FFFFh
49
32
188000h-18FFFFh
10
32
050000h-057FFFh
48
32
180000h-187FFFh
9
32
048000h-04FFFFh
32
040000h-047FFFh
47
32
178000h-17FFFFh
8
46
32
170000h-177FFFh
7
32
038000h-03FFFFh
45
32
168000h-16FFFFh
6
32
030000h-037FFFh
44
32
160000h-167FFFh
5
32
028000h-02FFFFh
32
020000h-027FFFh
43
32
158000h-15FFFFh
4
42
32
150000h-157FFFh
3
32
018000h-01FFFFh
41
32
148000h-14FFFFh
2
32
010000h-017FFFh
40
32
140000h-147FFFh
1
32
008000h-00FFFFh
138000h-13FFFFh
0
32
000000h-007FFFh
39
46/52
32
M36DR432AD, M36DR432BD
Table 30. Bank B, Bottom Boot Block
Addresses M36DR432BD
18
32
0D0000h-0D7FFFh
17
32
0C8000h-0CFFFFh
#
Size
(KWord)
Address Range
16
32
0C0000h-0C7FFFh
55
32
1F8000h-1FFFFFh
15
32
0B8000h-0BFFFFh
54
32
1F0000h-1F7FFFh
14
32
0B0000h-0B7FFFh
53
32
1E8000h-1EFFFFh
13
32
0A8000h-0AFFFFh
52
32
1E0000h-1E7FFFh
12
32
0A0000h-0A7FFFh
51
32
1D8000h-1DFFFFh
11
32
098000h-09FFFFh
50
32
1D0000h-1D7FFFh
10
32
090000h-097FFFh
49
32
1C8000h-1CFFFFh
9
32
088000h-08FFFFh
48
32
1C0000h-1C7FFFh
8
32
080000h-087FFFh
47
32
1B8000h-1BFFFFh
7
32
078000h-07FFFFh
46
32
1B0000h-1B7FFFh
6
32
070000h-077FFFh
45
32
1A8000h-1AFFFFh
5
32
068000h-06FFFFh
44
32
1A0000h-1A7FFFh
4
32
060000h-067FFFh
43
32
198000h-19FFFFh
3
32
058000h-05FFFFh
42
32
190000h-197FFFh
2
32
050000h-057FFFh
41
32
188000h-18FFFFh
1
32
048000h-04FFFFh
40
32
180000h-187FFFh
0
32
040000h-047FFFh
39
32
178000h-17FFFFh
38
32
170000h-177FFFh
37
32
168000h-16FFFFh
36
32
160000h-167FFFh
#
Size
(KWord)
Address Range
35
32
158000h-15FFFFh
14
32
038000h-03FFFFh
34
32
150000h-157FFFh
13
32
030000h-037FFFh
33
32
148000h-14FFFFh
12
32
028000h-02FFFFh
32
32
140000h-147FFFh
11
32
020000h-027FFFh
31
32
138000h-13FFFFh
10
32
018000h-01FFFFh
30
32
130000h-137FFFh
9
32
010000h-017FFFh
29
32
128000h-12FFFFh
8
32
008000h-00FFFFh
28
32
120000h-127FFFh
7
4
007000h-007FFFh
27
32
118000h-11FFFFh
6
4
006000h-006FFFh
26
32
110000h-117FFFh
5
4
005000h-005FFFh
25
32
108000h-10FFFFh
4
4
004000h-004FFFh
24
32
100000h-107FFFh
3
4
003000h-003FFFh
23
32
0F8000h-0FFFFFh
2
4
002000h-002FFFh
22
32
0F0000h-0F7FFFh
1
4
001000h-001FFFh
21
32
0E8000h-0EFFFFh
0
4
000000h-000FFFh
20
32
0E0000h-0E7FFFh
19
32
0D8000h-0DFFFFh
Table 31. Bank A, Bottom Boot Block
Addresses M36DR432BD
47/52
M36DR432AD, M36DR432BD
APPENDIX B. COMMON FLASH INTERFACE
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the Read CFI Query Command is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 32, 33,
34 and 35 show the address used to retrieve each
data. The Query data is always presented on the
lowest order data outputs (DQ0-DQ7), the other
outputs (DQ8-DQ15) are set to 0.
The CFI data structure contains also a security
area starting at address 81h. This area can be accessed only in read mode and it is impossible to
change after it has been written by ST. Issue a
Read command to return to Read mode.
Table 32. Query Structure Overview
Offset
Sub-section Name
Description
00h
Reserved
Reserved for algorithm-specific information
10h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
System Interface Information
Device timing & voltage information
27h
Device Geometry Definition
Flash device layout
P
Primary Algorithm-specific Extended Query table
Additional information specific to the Primary
Algorithm (optional)
A
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Table 33. CFI Query Identification String
Offset
Data
Description
00h
0020h
01h
00A1h - bottom
00A0h - top
02h-0Fh
reserved
10h
0051h
Query Unique ASCII String "QRY"
11h
0052h
Query Unique ASCII String "QRY"
12h
0059h
Query Unique ASCII String "QRY"
13h
0002h
14h
0000h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
15h
offset = P = 0040h
16h
0000h
17h
0000h
18h
0000h
19h
value = A = 0000h
1Ah
0000h
Manufacturer Code
Device Code
Reserved
Address for Primary Algorithm extended Query table
48/52
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported (note: 0000h means none exists)
Address for Alternate Algorithm extended Query table
note: 0000h means none exists
M36DR432AD, M36DR432BD
Table 34. CFI Query System Interface Information
Offset
Data
1Bh
0017h
VDDF Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
1Ch
0022h
VDDF Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 millivolts
0000h
VPPF [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPPF pin is present
1Eh
00C0h
VPPF [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4
HEX value in volts
bit 3 to 0
BCD value in 100 millivolts
Note: This value must be 0000h if no VPPF pin is present
1Fh
0004h
Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs
(if supported; 0000h = not supported)
20h
0003h
Typical timeout for maximum-size multi-byte program or page write, 2n µs
(if supported; 0000h = not supported)
21h
000Ah
Typical timeout per individual block erase, 2n ms
(if supported; 0000h = not supported)
22h
0000h
Typical timeout for full chip erase, 2n ms
(if supported; 0000h = not supported)
23h
0003h
Maximum timeout for byte/word program, 2n times typical (offset 1Fh)
(0000h = not supported)
24h
0004h
Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h)
(0000h = not supported)
25h
0002h
Maximum timeout per individual block erase, 2n times typical (offset 21h)
(0000h = not supported)
26h
0000h
Maximum timeout for chip erase, 2n times typical (offset 22h)
(0000h = not supported)
1Dh
Description
49/52
M36DR432AD, M36DR432BD
Table 35. Device Geometry Definition
Offset Word
Mode
Data
27h
0016h
28h
0001h
29h
0000h
2Ah
0000h
2Bh
0000h
2Ch
0002h
Description
Device Size = 2n in number of bytes
Flash Device Interface Code description: Asynchronous x16
Maximum number of bytes in multi-byte program or page = 2n
Number of Erase Block Regions within device
bit 7 to 0 = x = number of Erase Block Regions
Note:1. x = 0 means no erase blocking, i.e. the device erases at once in "bulk."
2. x specifies the number of regions within the device containing one or more
contiguous Erase Blocks of the same size. For example, a 128KB device
(1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is
considered to have 5 Erase Block Regions. Even though two regions both
contain 16KB blocks, the fact that they are not contiguous means they are
separate Erase Block Regions.
3. By definition, symmetrically block devices have only one blocking region.
M36DR432AD
M36DR432AD Erase Block Region Information
2Dh
003Eh
2Eh
0000h
2Fh
0000h
30h
0001h
31h
0007h
32h
0000h
33h
0020h
34h
0000h
M36DR432AD
M36DR432AD
2Dh
0007h
2Eh
0000h
2Fh
0020h
30h
0000h
31h
003Eh
32h
0000h
33h
0000h
34h
0001h
50/52
bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes
in size. The value z = 0 is used for 128 byte block size.
e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K
bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase
Block Region:
e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number]
y = 0 means no blocking (# blocks = y+1 = "1 block")
Note: y = 0 value must be used with number of block regions of one as indicated
by (x) = 0
M36DR432AD, M36DR432BD
REVISION HISTORY
Table 36. Document Revision History
Date
Version
Revision Details
15-Jan-2003
1.0
First issue.
15-Jan-2003
1.1
Bottom Device Code corrected on page 1.
25-Feb-2003
2.0
Document promoted from Preliminary Data to full Datasheet status.
28-Feb-2003
2.1
VDDQF signal removed from datasheet. SRAM Input Rise and Fall Times added to,
and VDDF and VDDS parameters differentiated in Table 14, Operating and AC
Measurement Conditions. VDDS added to the SIGNAL DESCRIPTIONS section.
51/52
M36DR432AD, M36DR432BD
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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