TI1 CLVC8T245MRHLTEP 8-bit dual-supply bus transceiver with configurable voltage translation and tri-state output Datasheet

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SN74LVC8T245-EP
SCES770A – DECEMBER 2008 – REVISED MARCH 2017
SN74LVC8T245-EP 8-Bit Dual-Supply Bus Transceiver With
Configurable Voltage Translation and Tri-State Outputs
1 Features
3 Description
•
This 8-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The
SN74LVC8T245-EP is optimized to operate with VCCA
and VCCB set at 1.65 V to 5.5 V. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 5.5 V. The B port is designed
to track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V,
2.5-V, 3.3-V, and 5.5-V voltage nodes.
1
•
•
•
•
Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
VCC Isolation Feature – If Either VCC Input Is at
GND, All Are in the High-Impedance State
Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C) Temperature
Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
The
SN74LVC8T245-EP
is
designed
for
asynchronous communication between two data
buses. The logic levels of the direction-control (DIR)
input and the output-enable (OE) input activate either
the B-port outputs or the A-port outputs or place both
output ports into the high-impedance mode. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated, and from the B
bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is
always active and must have a logic HIGH or LOW
level applied to prevent excess ICC and ICCZ.
The SN74LVC8T245-EP is designed so that the
control pins (DIR and OE) are supplied by VCCA.
Device Information(1)
PART NUMBER
SN74LVC8T245-EP
(1)
Additional temperature ranges are available – contact factory.
PACKAGE
BODY SIZE (NOM)
TSSOP (24)
4.40 mm × 7.80 mm
SOIC (24)
7.50 mm × 15.40 mm
VQFN (24)
3.50 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
DIR
2
22
OE
A1
3
21
B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC8T245-EP
SCES770A – DECEMBER 2008 – REVISED MARCH 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
4
4
5
6
6
7
7
8
8
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information PW, DW and RHL....................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Switching Characteristics ..........................................
Operating Characteristics........................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 15
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
15
14 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2008) to Revision A
Page
•
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
•
Changed Ordering Information table to Device Information table ......................................................................................... 1
•
Added SOIC and VQFN packages to data sheet................................................................................................................... 1
•
Added the temperature conditions for MIN, TYP, and MAX in the Electrical Characteristics table ....................................... 6
•
Changed TA = –55°C to 125°C values for II, Ioff, IOZ, ICCA, ICCB, and ICCA + ICCB in the Electrical Characteristics table .......... 6
2
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SCES770A – DECEMBER 2008 – REVISED MARCH 2017
5 Description (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
6 Pin Configuration and Functions
PW or DW Package
24-Pin TSSOP or SOIC
(Top View)
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCCB
23
1
24
23 VCCB
22 OE
2
3
21 B1
20 B2
4
5
19 B3
18 B4
6
7
17 B5
16 B6
8
9
15 B7
14 B8
10
11
12
13
GND
24
2
VCCA
1
GND
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
RHL Package
24-Pin VQFN
(Top View)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A1
3
I/O
Input/output A1. Referenced to VCCA.
A2
4
I/O
Input/output A2. Referenced to VCCA.
A3
5
I/O
Input/output A3. Referenced to VCCA.
A4
6
I/O
Input/output A4. Referenced to VCCA.
A5
7
I/O
Input/output A5. Referenced to VCCA.
A6
8
I/O
Input/output A6. Referenced to VCCA.
A7
9
I/O
Input/output A7. Referenced to VCCA.
A8
10
I/O
Input/output A8. Referenced to VCCA.
B1
21
I/O
Input/output B1. Referenced to VCCB.
B2
20
I/O
Input/output B2. Referenced to VCCB.
B3
19
I/O
Input/output B3. Referenced to VCCB.
B4
18
I/O
Input/output B4. Referenced to VCCB.
B5
17
I/O
Input/output B5. Referenced to VCCB.
B6
16
I/O
Input/output B6. Referenced to VCCB.
B7
15
I/O
Input/output B7. Referenced to VCCB.
B8
14
I/O
Input/output B8. Referenced to VCCB.
DIR
2
I
Direction-control signal.
GND
11, 12, 13
G
Ground.
22
I
Tri-state output-mode enables. Pull OE high to place all outputs in tri-state mode. Referenced to
VCCA.
VCCA
1
P
A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V.
VCCB
23, 24
P
B-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V.
OE
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–0.5
6.5
V
I/O ports (A port)
–0.5
6.5
I/O ports (B port)
–0.5
6.5
Control inputs
–0.5
6.5
A port
–0.5
6.5
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
VCCA
VCCB
Supply voltage
VI
Input voltage (2)
VO
Voltage applied to any output
in the high-impedance or power-off state (2)
VO
Voltage applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through each VCCA, VCCB, and GND
±100
mA
88
°C/W
150
°C
RθJA
Package thermal impedance (4)
Tstg
Storage temperature
(1)
(2)
(3)
(4)
–65
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 6.5-V maximum if the output current rating is observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions (1) (2) (3) (4)
VCCI
VCCA
VCCB
VCCO
Supply voltage
1.65 to 1.95 V
High-level
input voltage
VIH
MAX
5.5
1.65
5.5
1.7
3 to 3.6 V
VCCI × 0.7
1.65 to 1.95 V
VIL
Data inputs (5)
VCCI × 0.35
2.3 to 2.7 V
0.7
3 to 3.6 V
0.8
4.5 to 5.5 V
High-level
input voltage
Control inputs
(referenced to VCCA) (6)
VCCI × 0.3
2.3 to 2.7 V
1.7
3 to 3.6 V
VCCA × 0.7
VCCA ×
0.35
1.65 to 1.95 V
Low-level
input voltage
Control inputs
(referenced to VCCA) (6)
2.3 to 2.7 V
0.7
3 to 3.6 V
0.8
4.5 to 5.5 V
VI
VI/O
Input voltage
Control inputs
0
5.5
Input/output
voltage
Active state
0
VCCO
Tri-state
0
5.5
–8
3 to 3.6 V
–24
4.5 to 5.5 V
–32
1.65 to 1.95 V
IOL
Δt/Δv
Input transition
rise or fall rate
TA
Operating free-air temperature
Data inputs
8
3 to 3.6 V
24
4.5 to 5.5 V
32
1.65 to 1.95 V
20
2.3 to 2.7 V
20
3 to 3.6 V
10
4.5 to 5.5 V
(1)
(2)
(3)
(4)
(5)
(6)
V
mA
4
2.3 to 2.7 V
Low-level output current
V
–4
2.3 to 2.7 V
High-level output current
V
VCCA × 0.3
1.65 to 1.95 V
IOH
V
2
4.5 to 5.5 V
VIL
V
VCCA ×
0.65
1.65 to 1.95 V
VIH
V
V
2
4.5 to 5.5 V
Low-level
input voltage
UNIT
VCCI × 0.65
2.3 to 2.7 V
Data inputs (5)
MIN
1.65
mA
ns/V
5
–55
125
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure
proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
All unused control inputs must be held at VCCA or GND to ensure proper device operation and minimize power consumption.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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7.4 Thermal Information PW, DW and RHL
SN74LVC8T245-EP
THERMAL METRIC (1)
PW
DW
RHL
24 PINS
24 PINS
24 PINS
90.6
68.1
36.2
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
27.6
35.6
27.9
°C/W
RθJB
Junction-to-board thermal resistance
45.3
37.8
13.5
°C/W
ψJT
Junction-to-top characterization parameter
1.3
13
0.5
°C/W
ψJB
Junction-to-board characterization parameter
44.8
37.5
13.4
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
3.6
°C/W
RθJA
(1)
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
VOH
VOL
TEST CONDITIONS
VI = VIH
1.65 V
1.65 V
1.2
IOH = –8 mA,
VI = VIH
2.3 V
2.3 V
1.9
IOH = –24 mA,
VI = VIH
3V
3V
2.4
IOH = –32 mA,
VI = VIH
4.5 V
4.5 V
3.8
IOL = 100 μA,
VI = VIL
1.65 V to 4.5 V
1.65 V to 4.5 V
IOL = 4 mA,
VI = VIL
1.65 V
1.65 V
0.45
IOL = 8 mA,
VI = VIL
2.3 V
2.3 V
0.3
IOL = 24 mA,
VI = VIL
3V
3V
IOL = 32 mA,
VI = VIL
4.5 V
4.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
–1
1
–2
2
0V
0 V to 5.5 V
–1
1
–11
11
0 V to 5.5 V
0V
–1
1
–11
11
1.65 V to 5.5 V
1.65 V to 5.5 V
–1
1
–6
6
1.65 V to 5.5 V
1.65 V to 5.5 V
5V
0V
20
0V
5V
–10
1.65 V to 5.5 V
1.65 V to 5.5 V
5V
0V
–10
0V
5V
20
1.65 V to 5.5 V
1.65 V to 5.5 V
40
VI or VO = 0 to 5.5 V
IOZ
A or B
port
VO = VCCO or GND,
OE = VIH
VI = VCCI or GND,
VI = VCCI or GND,
VI = VCCI or GND,
IO = 0
IO = 0
IO = 0
A port
One A port at VCCA – 0.6 V,
DIR at VCCA, B port = open
DIR
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
ΔICCB
B port
One B port at VCCB – 0.6 V,
DIR at GND, A port = open
3 V to 5.5 V
3 V to 5.5 V
Ci
Control
inputs
VI = VCCA or GND
3.3 V
3.3 V
Cio
A or B
port
VO = VCCA/B or GND
3.3 V
3.3 V
6
MAX
IOH = –4 mA,
A or B
port
(1)
(2)
MIN
1.65 V to 4.5 V
Ioff
ΔICCA
TA = –55°C to 125°C
TYP MAX
1.65 V to 4.5 V
VI = VCCA or GND
ICCA +
ICCB
TA = 25°C
MIN
VI = VIH
DIR
ICCB
VCCB
IOH = –100 μA,
II
ICCA
VCCA
UNIT
VCCO – 0.1
V
0.1
V
0.55
0.55
μA
μA
μA
20
μA
20
μA
μA
50
3 V to 5.5 V
3 V to 5.5 V
μA
50
50
μA
4
5
pF
8.5
10
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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7.6 Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
1.7
B
A
OE
MIN MAX
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN MAX
25.9
1.3
13.2
1
11.4
0.8
11.1
ns
0.9
28.8
0.8
27.6
0.7
27.4
0.7
27.4
ns
A
1.5
33.6
1.5
33.4
1.5
33.3
1.4
33.2
ns
OE
B
2.4
36.2
1.9
17.1
1.7
16
1.3
14.3
ns
OE
A
0.4
28
0.4
27.8
0.4
27.7
0.4
27.7
ns
OE
B
1.8
40
1.5
20
1.2
16.6
0.9
14.8
ns
7.7 Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
B
1.5
25.4
1.2
13
0.8
10.2
0.6
8.8
ns
B
A
1.2
13.3
1
13.1
1
12.9
0.9
12.8
ns
OE
A
1.4
13
1.4
13
1.4
13
1.4
13
ns
OE
B
2.3
33.6
1.8
15
1.7
14.3
0.9
10.9
ns
OE
A
1
17.2
1
17.3
1
17.2
1
17.3
ns
OE
B
1.7
32.2
1.5
18.1
1.2
14.1
1
11.2
ns
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7.8 Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
VCCB = 1.8 V
± 0.15 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
1.5
B
A
OE
VCCB = 2.5 V
± 0.2 V
MIN MAX
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN MAX
25.2
1.1
12.8
0.8
10.3
0.5
10.4
ns
0.8
11.2
0.8
10.2
0.7
10.1
0.6
10
ns
A
1.6
12.2
1.6
12.2
1.6
12.2
1.6
12.2
ns
OE
B
2.1
33
1.7
14.3
1.5
12.6
0.8
10.3
ns
OE
A
0.8
14.1
0.8
13.6
0.8
13.2
0.8
13.6
ns
OE
B
1.8
31.7
1.4
18.4
1.1
12.9
0.9
10.9
ns
7.9 Switching Characteristics
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN MAX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
B
1.5
25.4
1
12.8
0.7
10
0.4
8.2
ns
B
A
0.7
11
0.4
8.8
0.3
8.5
0.3
8.3
ns
OE
A
0.3
9.4
0.3
9.4
0.3
9.4
0.3
9.4
ns
OE
B
2
32.7
1.6
13.7
1.4
12
0.7
9.7
ns
OE
A
0.7
10.9
0.7
10.9
0.7
10.9
0.7
10.9
ns
OE
B
1.5
31.6
1.3
18.4
1
13.7
0.9
10.7
ns
7.10 Operating Characteristics
TA = 25°C
PARAMETER
CpdA
(1)
CpdB
(1)
(1)
8
TEST
CONDITIONS
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
B-port input, A-port output
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
VCCA =
VCCB = 5 V
TYP
TYP
TYP
TYP
2
2
2
3
12
13
13
16
13
13
14
16
2
2
2
3
UNIT
pF
pF
Power dissipation capacitance per transceiver
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8 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVC8T245-EP is an 8-bit, dual supply non-inverting voltage level translation. Pin Ax and direction
control pin are support by VCCA and pin Bx is support by VCCB. The A port is able to accept I/O voltages ranging
from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data
transmission from A to B and a low on DIR allows data transmission from B to A.
9.2 Functional Block Diagram
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
Figure 2. Logic Diagram (Positive Logic)
9.3 Feature Description
9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for
translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V and 5 V).
9.3.2 Ioff Supports Partial-Power-Down Mode Operation
Ioff prevents backflow current by disabling I/O output circuits when device is in partial-power-down mode.
9.4 Device Functional Modes
The SN74LVC8T245-EP is voltage level translator that can operate from 1.65 V to 5.5 V (VCCA) and 1.65 V to 5.5
V (VCCB). The signal translation between 1.65 V and 5.5 V requires direction control and output enable control.
When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data
transmission is from B to A. When OE is high, both output ports will be high-impedance.
Table 1. Function Table (1)
(Each 8-Bit Section)
CONTROL INPUTS
(1)
10
OUTPUT CIRCUITS
OPERATION
OE
DIR
A PORT
B PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os are always active.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LVC8T245-EP device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The maximum output current can be up to 32 mA when
device is powered by 5 V.
10.2 Typical Application
1.8V
5V
0.1 F
0.1 F
VCCA
1 µF
VCCB
DIR
OE
1.8V
Controller
5V
System
SN74LVC8T245
Data
GND
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
GND
Data
GND
Figure 3. Typical Application Circuit
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Typical Application (continued)
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
Input voltage range
1.65 V to 5.5 V
Output voltage
1.65 V to 5.5 V
10.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVC8T245-EP device to determine the input
voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low,
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVC8T245-EP device is driving to determine the output
voltage range.
10.2.3 Application Curve
Voltage (V)
Output (5 V)
Input (1.8 V)
Time (200 ns/div)
Figure 4. Translation Up (1.8 V to 5 V) at 2.5 MHz
12
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11 Power Supply Recommendations
The SN74LVC8T245-EP device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA
accepts any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The
A port and B port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional
translation between any of the 1.8-V, 2.5 -V, 3.3-V and 5-V voltage nodes.
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12 Layout
12.1 Layout Guidelines
To
•
•
•
ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of
signals depending on the system requirements.
12.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCB
VCCA
Bypass Capacitor
Bypass Capacitor
VCCA
1
VCCA
VCCB
16
2
DIR
VCCB
15
From
Controller
3
A1
OE
14
From
Controller
4
A2
B1
13
To
System
From
Controller
5
A3
B2
12
To
System
From
Controller
6
A4
B3
11
To
System
From
Controller
7
A5
B4
10
To
System
From
Controller
8
A6
B5
12
To
System
From
Controller
9
A7
B6
11
To
System
From
Controller
10
A8
B7
10
To
System
11
GND
B8
10
To
System
12
GND
GND
13
Keep OE high until VCCA and
VCCB are powered up
SN74LVC8T245
Figure 5. SN74LVC8T245-EP Layout
14
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SCES770A – DECEMBER 2008 – REVISED MARCH 2017
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CLVC8T245MRHLTEP
PREVIEW
VQFN
RHL
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
P8T245M
SN74LVC8T245MDWREP
PREVIEW
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
LVC8T245M
SN74LVC8T245MPWREP
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
NH245MEP
V62/09615-01XE
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
NH245MEP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2017
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC8T245-EP :
• Catalog: SN74LVC8T245
• Automotive: SN74LVC8T245-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CLVC8T245MRHLTEP
VQFN
RHL
24
250
180.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
SN74LVC8T245MDWREP
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVC8T245MRHLTEP
VQFN
RHL
SN74LVC8T245MDWREP
SOIC
DW
24
250
210.0
185.0
35.0
24
2000
367.0
367.0
45.0
Pack Materials-Page 2
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