Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 ISO732x-Q1 Robust EMC, Low Power, Dual-Channel Digital Isolators 1 Features • • 1 • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM Classification Level 3A – Device CDM Classification Level C6 Signaling Rate: 25 Mbps Integrated Noise Filter on the Inputs Default Output High and Low Options Low Power Consumption: Typical ICC per Channel at 1 Mbps: – ISO7320-Q1: 1.2 mA (5-V Supplies), 0.9 mA (3.3-V Supplies) – ISO7321-Q1: 1.7 mA (5-V Supplies), 1.2 mA (3.3-V Supplies) Low Propagation Delay: 33 ns Typical (5-V Supplies) 3.3-V and 5-V Level Translation 65-kV/μs Transient Immunity, Typical (5-V Supplies) Robust Electromagnetic Compatibility (EMC) – System-level ESD, EFT, and Surge Immunity – Low Emissions Isolation Barrier Life: > 25 Years Operates from 3.3-V and 5-V Supplies Narrow Body SOIC-8 Package Safety and Regulatory Approvals: – 4242-VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 – 3000-VRMS Isolation for 1 minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 61010-1 Standards – Planned CQC Certification per GB4943.1-2011 – Power Supplies – Battery Packs 3 Description The ISO732x-Q1 family of devices provides galvanic isolation up to 3000 VRMS for 1 minute per UL 1577 and 4242 VPK per VDE V 0884-10. These devices have two isolated channels comprised of logic input and output buffers separated by silicon dioxide (SiO2) insulation barriers. The ISO7320-Q1 has both channels in the same direction while ISO7321-Q1 has the two channels in opposite direction. In case of input power or signal loss, the default output is low for orderable part numbers with suffix F and high for orderable part numbers without suffix F. See Device Functional Modes for more information. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The ISO732x-Q1 family of devices has integrated noise filters for harsh industrial environment where short noise pulses may be present at the device input pins. The ISO732x-Q1 family of devices has TTL input thresholds and operate from 3-V to 5.5-V supply levels. Through innovative chip design and layout techniques, electromagnetic compatibility of the ISO732x-Q1 family of devices has been significantly enhanced to enable system-level ESD, EFT, Surge and Emissions compliance. Device Information(1) PART NUMBER ISO7320-Q1 SOIC (8) ISO7321-Q1 Opto-Coupler Replacement in: – Industrial FieldBus – ProfiBus – ModBus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control BODY SIZE (NOM) 4.90 mm × 3.91 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic VCCI 2 Applications • PACKAGE Isolation Capacitor VCCO INx OUTx GNDI GNDO VCCI and GNDI are supply and ground connections respectively for the input channels. VCCO and GNDO are supply and ground connections respectively for the output channels. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 4 4 4 4 5 5 6 6 6 7 7 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics—5-V Supply ..................... Supply Current Characteristics—5-V Supply ............ Electrical Characteristics—3.3 V............................... Supply Current Characteristics—3.3-V Supply ......... Power Dissipation Characteristics ............................ Switching Characteristics—5-V Supply................... Switching Characteristics—3.3-V Supply................ Typical Characteristics ............................................ 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 15 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application .................................................. 16 10 Power Supply Recommendations ..................... 18 11 Layout................................................................... 18 11.1 Layout Guidelines ................................................. 18 11.2 Layout Example .................................................... 19 12 Device and Documentation Support ................. 20 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Related Links ........................................................ Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 20 13 Mechanical, Packaging, and Orderable Information ........................................................... 20 Parameter Measurement Information ................ 10 Detailed Description ............................................ 11 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES November 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 5 Pin Configuration and Functions 1 INA 2 INB 3 GND1 4 ISO7321-Q1 D Package 8-Pin SOIC Top View 8 VCC2 VCC1 1 7 OUTA OUTA 2 6 OUTB INB 3 5 GND2 GND1 4 Isolation VCC1 Isolation ISO7320-Q1 D Package 8-Pin SOIC Top View 8 VCC2 7 INA 6 OUTB 5 GND2 Pin Functions PIN NAME NO. I/O DESCRIPTION ISO7320-Q1 ISO7321-Q1 INA 2 7 I Input, channel A INB 3 3 I Input, channel B GND1 4 4 — Ground connection for VCC1 GND2 5 5 — Ground connection for VCC2 OUTA 7 2 O Output, channel A OUTB 6 6 O Output, channel B VCC1 1 1 — Power supply, VCC1 VCC2 8 8 — Power supply, VCC2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 3 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage (2) VCC Voltage VCC1 , VCC2 (2) INx, OUTx MIN MAX –0.5 6 –0.5 (3) VCC+ 0.5 UNIT V V IO Output current ±15 mA TJ Junction temperature 150 °C Tstg Storage temperature 150 °C (1) –65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. Maximum voltage must not exceed 6 V. (2) (3) 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±4000 Charged-device model (CDM), per AEC Q100-011 ±1500 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions MIN NOM Supply voltage, IOH High-level output current IOL Low-level output current VIH High-level input voltage 2 5.5 VIL Low-level input voltage 0 0.8 tui Input pulse duration 1 / tui TJ (1) TA (1) 3 MAX VCC1, VCC2 5.5 –4 40 0 -40 mA V V ns Junction temperature Ambient temperature V mA 4 Signaling rate UNIT 25 25 Mbps 136 °C 125 °C To maintain the recommended operating conditions for TJ, see the Thermal Information table. 6.4 Thermal Information ISO732x-Q1 THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 121 °C/W RθJCtop Junction-to-case (top) thermal resistance 67.9 °C/W RθJB Junction-to-board thermal resistance 61.6 °C/W ψJT Junction-to-top characterization parameter 21.5 °C/W ψJB Junction-to-board characterization parameter 61.1 °C/W RθJCbot Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 6.5 Electrical Characteristics—5-V Supply VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER MIN TYP IOH = –4 mA; see Figure 11 TEST CONDITIONS VCCO (1)– 0.5 4.7 IOH = –20 μA; see Figure 11 VCCO (1) – 0.1 5 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IN = VCC IIL Low-level input current IN = 0 V CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13. (1) IOL = 4 mA; see Figure 11 IOL = 20 μA; see Figure 11 MAX V 0.2 0.4 0 0.1 460 V mV 10 μA μA –10 25 UNIT 65 kV/μs VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured. 6.6 Supply Current Characteristics—5-V Supply All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX ICC1 0.4 0.9 ICC2 2 3.2 ICC1 0.8 1.4 ICC2 3.2 4.4 ICC1 1.4 2.3 ICC2 4.9 6.8 UNIT ISO7320-Q1 DC to 1 Mbps Supply current for VCC1 and VCC2 DC Input: VI = VCC or 0 V, AC Input: CL = 15 pF 10 Mbps CL = 15 pF 25 Mbps CL = 15 pF DC to 1 Mbps DC Input: VI = VCC or 0 V, AC Input: CL = 15 pF ICC1 , ICC2 1.7 2.8 10 Mbps CL = 15 pF ICC1 , ICC2 2.5 3.7 25 Mbps CL = 15 pF ICC1 , ICC2 3.7 5.4 mA ISO7321-Q1 Supply current for VCC1 and VCC2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 mA 5 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 6.7 Electrical Characteristics—3.3 V VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER MIN TYP IOH = –4 mA; see Figure 11 TEST CONDITIONS VCCO (1)– 0.5 3 IOH = –20 μA; see Figure 11 VCCO (1)– 0.1 3.3 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IN = VCC IIL Low-level input current IN = 0 V CMTI Common-mode transient immunity VI = VCC or 0 V; see Figure 13 (1) IOL = 4 mA; see Figure 11 IOL = 20 μA; see Figure 11 MAX V 0.2 0.4 0 0.1 450 V mV 10 μA μA –10 25 UNIT 50 kV/μs VCCO is supply voltage, VCC1 or VCC2, for the output channel being measured. 6.8 Supply Current Characteristics—3.3-V Supply All inputs switching with square wave clock signal for dynamic ICC measurement. VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX ICC1 0.2 0.5 ICC2 1.5 2.5 ICC1 0.5 0.8 ICC2 2.2 3.2 ICC1 0.9 1.4 ICC2 3.3 4.7 UNIT ISO7320-Q1 DC to 1 Mbps Supply current for VCC1 and VCC2 DC Input: VI = VCC or 0 V, AC Input: CL = 15 pF 10 Mbps CL = 15 pF 25 Mbps CL = 15 pF DC to 1 Mbps DC Input: VI = VCC or 0 V, AC Input: CL = 15 pF ICC1 , ICC2 1.2 2 10 Mbps CL = 15 pF ICC1 , ICC2 1.7 2.5 25 Mbps CL = 15 pF ICC1 , ICC2 2.5 3.6 mA ISO7321-Q1 Supply current for VCC1 and VCC2 mA 6.9 Power Dissipation Characteristics VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 12.5 MHz 50% duty-cycle square wave (unless otherwise noted) MAX UNIT PD Maximum power dissipation by ISO7320-Q1 PARAMETER 56 mW PD1 Maximum power dissipation by side-1 of ISO7320-Q1 15 mW PD2 Maximum power dissipation by side-2 of ISO7320-Q1 41 mW PD Maximum power dissipation by ISO7321-Q1 67 mW PD1 Maximum power dissipation by side-1 of ISO7321-Q1 33.5 mW PD2 Maximum power dissipation by side-2 of ISO7321-Q1 33.5 mW 6 TEST CONDITIONS Submit Documentation Feedback MIN TYP Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 6.10 Switching Characteristics—5-V Supply VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time See Figure 11 PWD (1) Pulse width distortion |tPHL – tPLH| See Figure 11 tsk(o) (2) tsk(pp) (3) Channel-to-channel output skew time MIN TYP MAX 20 33 57 ns 4 ns ISO7320-Q1 2 ISO7321-Q1 17 Part-to-part skew time UNIT ns 23 ns tr Output signal rise time See Figure 11 2.4 ns tf Output signal fall time See Figure 11 2.1 ns tfs Fail-safe output delay time from input power loss See Figure 12 7.5 μs (1) (2) (3) Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.11 Switching Characteristics—3.3-V Supply VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted) PARAMETER tPLH, tPHL PWD tsk(o) (1) (2) tsk(pp) (3) TEST CONDITIONS Propagation delay time See Figure 11 Pulse width distortion |tPHL – tPLH| Channel-to-channel output skew time MIN TYP MAX 22 37 66 ns 3 ns See Figure 11 ISO7320-Q1 3 ISO7321-Q1 16 Part-to-part skew time UNIT 28 ns ns tr Output signal rise time See Figure 11 3.1 tf Output signal fall time See Figure 11 2.6 ns tfs Fail-safe output delay time from input power loss See Figure 12 7.4 μs (1) (2) (3) ns Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 7 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 6.12 Typical Characteristics 7 4 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 5 4 3 2 1 3 2.5 2 1.5 1 0.5 0 0 0 5 10 15 20 Data Rate (Mbps) TA = 25°C 25 30 0 CL = 15 pF 10 TA = 25°C Figure 1. ISO7320-Q1 Supply Current vs Data Rate 15 20 Data Rate (Mbps) 25 30 D002 No Load Figure 2. ISO7320-Q1 Supply Current vs Data Rate 3 3.5 2.5 3 Supply Current (mA) Supply Current (mA) 5 D001 4 2.5 2 1.5 1 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 0.5 2 1.5 1 ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 0.5 0 0 0 5 10 TA = 25°C 15 20 Data Rate (Mbps) 25 30 0 CL = 15 pF 10 TA = 25°C Figure 3. ISO7321-Q1 Supply Current vs Data Rate 15 20 Data Rate (Mbps) 25 30 D004 No Load Figure 4. ISO7321-Q1 Supply Current vs Data Rate 0.9 VCC at 3.3 V VCC at 5 V VCC at 3.3 V VCC at 5 V 0.8 Low-Level Output Voltage (V) 5 5 D003 6 High-Level Output Voltage (V) ICC1 at 3.3 V ICC1 at 5 V ICC2 at 3.3 V ICC2 at 5 V 3.5 Supply Current (mA) Supply Current (mA) 6 4 3 2 1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 -15 -10 -5 High-Level Output Current (mA) 0 TA = 25°C 5 10 Low-Level Output Current (mA) 15 D006 TA = 25°C Figure 5. High-Level Output Voltage vs High-Level Output Current 8 0 D005 Figure 6. Low-Level Output Voltage vs Low-Level Output Current Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 2.48 2.46 43 VCC Rising VCC Falling 41 Propagation Delay Time (ms) Power Supply Under-Voltage Threshold (V) Typical Characteristics (continued) 2.44 2.42 2.4 2.38 2.36 37 35 33 31 0 50 100 Free-Air Temperature (qC) 25 -40 150 140 Peak-to-Peak Output Jitter (ps) 27 25 23 21 19 tGS at 3.3 V tGS at 5 V 30 65 Free-Air Temperature (qC) 100 135 D008 Figure 8. Propagation Delay Time vs Free-Air Temperature 160 17 -5 D007 29 15 -40 tPHL at 3.3 V tPLH at 5 V tPLH at 3.3 V tPHL at 5 V 29 27 2.34 -50 Figure 7. Power Supply Under Voltage Threshold vs FreeAir Temperature Input Glitch Suppression Time (ms) 39 120 100 80 60 40 20 Output Jitter at 3.3 V Output Jitter at 5 V 0 -5 30 65 Free-Air Temperature (qC) 100 135 0 5 D009 Figure 9. Input Glitch Suppression Time vs Free-Air Temperature 10 15 Data Rate (Mbps) 20 25 D010 Figure 10. Peak-to-Peak Output Jitter vs Data Rate Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 9 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com Isolation Barrier 7 Parameter Measurement Information IN Input Generator (1) VI 50 W VCCI VI OUT 50% 50% 0V VO CL tPLH (2) tPHL 90% 10% 50% VO VOH 50% VOL tr tf (1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not needed in actual application. (2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 11. Switching Characteristic Test Circuit and Voltage Waveforms VI VCC VCC VI Isolation Barrier IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) IN 2.7 V OUT 0V t fs VO fs high VO CL 50% fs low V OL See Note A A. VOH CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 12. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 μ F ±1% Isolation Barrier VCCI GNDI VCCO C = 0.1 μ F ±1% Pass-fail criteria – output must remain stable. OUT + CL Note A VOH or VOL GNDO – + VCM – (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 13. Common-Mode Transient Immunity Test Circuit 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 8 Detailed Description 8.1 Overview The isolator in Figure 14 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency (HF) channel with a bandwidth from 100 kbps up to 25 Mbps, and a low-frequency (LF) channel covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transient pulses, which then are converted into CMOS levels by a comparator. The transient pulses at the input of the comparator can be either above or below the common mode voltage VREF depending on whether the input bit transitions from 0 to 1 or 1 to 0. The comparator threshold is adjusted based on the expected bit transition. A decision logic (DCL) at the output of the HF channel comparator measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high-frequency to the low-frequency channel. 8.2 Functional Block Diagram Isolation Barrier OSC Low t Frequency Channel (DC...100 kbps) PWM VREF LPF 0 Polarity and Threshold Selection IN OUT 1 S High t Frequency Channel (100 kbps...25 Mbps) VREF DCL Polarity and Threshold Selection Figure 14. Conceptual Block Diagram of a Digital Capacitive Isolator Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is required to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 11 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 8.3 Feature Description ORDERABLE DEVICE CHANNEL DIRECTION ISO7320CQDQ1 and ISO7320CQDRQ1 ISO7321FCQDQ1 and ISO7321FCQDRQ1 (1) MAX DATA RATE DEFAULT OUTPUT High Same ISO7320FCQDQ1 and ISO7320FCQDRQ1 ISO7321CQDQ1 and ISO7321CQDRQ1 RATED ISOLATION Low 3000 VRMS / 4242 VPK (1) 25 Mbps High Opposite Low See the Regulatory Information section for detailed Isolation Ratings 8.3.1 High Voltage Feature Description 8.3.1.1 Insulation and Safety-Related Specifications for D-8 Package over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4 mm CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 DTI Minimum internal gap (internal clearance) Distance through insulation VIO = 500 V, TA = 25°C 400 V 13 µm 12 Ω 11 Ω 10 RIO Isolation resistance, input to output (1) CIO Isolation capacitance, input to output (1) VIO = 0.4 sin (2πft), f = 1 MHz 1.5 pF CI Input capacitance (2) VI = VCC / 2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1.8 pF (1) (2) VIO = 500 V, 100°C ≤ TA ≤ 125°C 10 All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 8.3.1.2 Insulation Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER (1) SPECIFICATION UNIT VIOWM Maximum isolation working voltage TEST CONDITIONS 400 VRMS VIORM Maximum repetitive peak voltage per DIN V VDE V 0884-10 566 VPK Input-to-output test voltage per DIN V VDE V 0884-10 VPR After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 680 Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC 906 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 1062 VPK VIOTM Maximum transient overvoltage per DIN V VDE V 0884-10 VTEST = VIOTM t = 60 sec (qualification) t= 1 sec (100% production) 4242 VPK VIOSM Maximum surge isolation voltage per DIN V VDE V 0884-10 Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.3 x VIOSM = 7800 VPK (qualification) 6000 VPK VISO Withstand isolation voltage per UL 1577 VTEST = VISO = 3000 VRMS, t = 60 sec (qualification); VTEST = 1.2 x VISO = 3600 VRMS, t = 1 sec (100% production) 3000 VRMS RS Insulation resistance VIO = 500 V at TS >109 Ω Pollution degree (1) 2 Climatic Classification 40/125/21 Table 1. IEC 60664-1 Ratings Table PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group II Rated mains voltage ≤ 150 VRMS I–IV Rated mains voltage ≤ 300 VRMS I–III 8.3.1.3 Regulatory Information VDE CSA Approved under CSA Certified according to DIN V VDE Component Acceptance Notice V 0884-10 (VDE V 08845A, IEC 60950-1, and IEC 10):2006-12 61010-1 UL Recognized under UL 1577 Component Recognition Program Basic Insulation Maximum Transient Overvoltage, 4242 VPK Maximum Surge Isolation Voltage, 6000 VPK Maximum Repetitive Peak Voltage, 566 VPK 400 VRMS Basic Insulation and 200 VRMS Reinforced Insulation working voltage per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2; Single protection, 3000 VRMS 300 VRMS Basic Insulation working voltage per CSA 61010-1-12 and IEC 61010-1 3rd Ed. Certificate number: 40016131 Master contract number: 220991 (1) CQC File number: E181974 Plan to certify according to GB4943.1-2011 (1) Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certification Planned Production tested ≥ 3600 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 13 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 8.3.1.4 Safety Limiting Values Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum safety temperature MIN TYP MAX RθJA = 121 °C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 188 RθJA = 121 °C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 287 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 400 Safety Limiting Current (mA) VCC1 = VCC2 = 3.6 V VCC1 = VCC2 = 5.5 V 300 200 100 0 0 50 100 150 Ambient Temperature (qC) 200 D011 Figure 15. Thermal Derating Curve per VDE 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 8.4 Device Functional Modes Table 2 lists the functional modes for the ISO732x-Q1 family of devices. Table 2. Function Table (1) OUTA, OUTB (1) (2) (3) VCCI VCCO PU PU INA, INB ISO732xCQDQ1 AND ISO732xCQDRQ1 ISO732xFCQDQ1 AND ISO732xFCQDRQ1 H H H L L L Open H (2) L (3) PD PU X H (2) L (3) X PD X Undetermined Undetermined VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level; Open = Not connected In fail-safe condition, output defaults to high level In fail-safe condition, output defaults to low level 8.4.1 Device I/O Schematics Input (Devices Without Suffix F) VCCI VCCI Input (Devices With Suffix F) VCCI VCCI VCCI VCCI VCCI 5 mA 500 W 500 W INx INx 5 mA Output VCCO 40 W OUTx Figure 16. Device I/O Schematics Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 15 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO732x-Q1 family of devices uses single-ended TTL-logic switching technology. The supply voltage range is from 3 V to 5.5 V for both supplies, VCC1 and VCC2. When designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the data controller (essentially, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application The ISO7321-Q1 device can be used with Texas Instruments' Piccolo™ microcontroller, CAN transceiver, transformer driver, and voltage regulator to create an isolated CAN interface. VS 3.3 V 0.1 F 2 VCC D2 3 1:1.33 MBR0520L 1 SN6501-Q1 GND D1 10 F 0.1 F IN OUT 5 10 F TPS76333-Q1 3 1 EN GND 3.3VISO 2 10 F MBR0520L 4, 5 ISO Barrier 0.1 F 0.1 F 0.1 F 1 29,57 VCC1 VDDIO CANRXA 26 TMS320F28035PAGQ CANTXA 25 VSS 6,28 8 3 VCC2 VCC INA 7 2 OUTA ISO7321-Q1 3 OUTB INB GND1 4 0.1 F 6 4 R 1 D GND2 5 RS 8 CANH SN65HVD231Q CANL GND 2 10 (optional) 10 (optional) 7 6 Vref 5 SM712 4.7 nF / 2 kV Multiple pins and discrete components omitted for clarity purpose. Figure 17. Isolated CAN Interface 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 Typical Application (continued) 9.2.1 Design Requirements 9.2.1.1 Typical Supply Current Equations For the equations in this section, the following is true: • ICC1 and ICC2 are typical supply currents measured in mA • f is the data rate measured in Mbps • CL is the capacitive load measured in pF 9.2.1.1.1 ISO7320-Q1 At VCC1 = VCC2 = 5 V ICC1 = 0.3838 + (0.0431 × f) ICC2 = 2.74567 + (0.08433 × f) + (0.01 x f × CL) (1) (2) At VCC1 = VCC2 = 3.3 V ICC1 = 0.2394 + (0.02355 × f) ICC2 = 2.10681 + (0.04374 × f) + (0.007045 × f × CL) (3) (4) 9.2.1.1.2 ISO7321-Q1 At VCC1 = VCC2 = 5 V ICC1 and ICC2 = 1.5877 + (0.066 × f) + (0.00123 × f × CL) (5) At VCC1 = VCC2 = 3.3 V ICC1 and ICC2 = 1.187572 + (0.019399 × f) + (0.0019029 × f × CL) (6) 9.2.2 Detailed Design Procedure 9.2.2.1 Electromagnetic Compatibility (EMC) Considerations Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO732xQ1 family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include: • Robust ESD protection cells for input and output signal pins and inter-chip bond pads. • Low-resistance connectivity of ESD cells to supply and ground pins. • Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events. • Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. • PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs. • Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 17 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com Typical Application (continued) 9.2.3 Application Curves The following typical eye diagrams of the ISO732x-Q1 family of devices indicate low jitter and wide open eye at the maximum data rate of 25 Mbps. Figure 18. Eye Diagram at 25 Mbps, 5 V and 25°C Figure 19. Eye Diagram at 25 Mbps, 3.3 V and 25°C 10 Power Supply Recommendations To help ensure reliable operation at data rates and supply voltages, a 0.1-µF bypass capacitor is recommended at the input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501-Q1. For such applications, detailed power supply design and transformer selection recommendations are available in the SN6501-Q1 datasheet (SLLSEF3) . 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 20). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see the application note, Digital Isolator Design Guide, SLLA284. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 Layout Guidelines (continued) 11.1.1 PCB Material For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This type of PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and self-extinguishing flammability-characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r ~ 4.5 Power plane 10 mils Low-speed traces Figure 20. Recommended Layer Stack Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 19 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Digital Isolator Design Guide, SLLA284 • Isolation Glossary, SLLA353 • SN6501-Q1 Transformer Driver for Isolated Power Supplies, SLLSEF3 • SN65HVD231Q-Q1 3.3-V CAN Transceiver, SGLS398 • TMS320F28035 Piccolo™ Microcontrollers, SPRS584 • TPS76333-Q1 Low-Power 150-mA Low-Dropout Linear Regulators, SGLS247 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7320-Q1 Click here Click here Click here Click here Click here ISO7321-Q1 Click here Click here Click here Click here Click here 12.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks DeviceNet, Piccolo, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 PACKAGE OUTLINE D0008B SOIC - 1.75 mm max height SCALE 2.800 SOIC C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4 5 B .150-.157 [3.81-3.98] NOTE 4 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .069 MAX [1.75] .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] .004-.010 [ 0.11 -0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A .041 [1.04] TYPICAL 4221445/B 04/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15], per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 21 ISO7320-Q1 ISO7321-Q1 SLLSER4 – NOVEMBER 2015 www.ti.com EXAMPLE BOARD LAYOUT D0008B SOIC - 1.75 mm max height SOIC 8X (.061 ) [1.55] SEE DETAILS SYMM 8X (.055) [1.4] SEE DETAILS SYMM 1 1 8 8X (.024) [0.6] 8 SYMM 8X (.024) [0.6] 5 4 6X (.050 ) [1.27] SYMM 5 4 6X (.050 ) [1.27] (.213) [5.4] (.217) [5.5] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4221445/B 04/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com 22 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 ISO7320-Q1 ISO7321-Q1 www.ti.com SLLSER4 – NOVEMBER 2015 EXAMPLE STENCIL DESIGN D0008B SOIC - 1.75 mm max height SOIC 8X (.061 ) [1.55] 8X (.055) [1.4] SYMM SYMM 1 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] 8 SYMM 8X (.024) [0.6] 5 4 6X (.050 ) [1.27] SYMM 5 4 (.217) [5.5] (.213) [5.4] HV / ISOLATION OPTION .162 [4.1] CLEARANCE / CREEPAGE IPC-7351 NOMINAL .150 [3.85] CLEARANCE / CREEPAGE SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:6X 4221445/B 04/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ISO7320-Q1 ISO7321-Q1 23 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7320CQDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7320Q ISO7320CQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7320Q ISO7320FCQDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7320FQ ISO7320FCQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7320FQ ISO7321CQDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7321Q ISO7321CQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7321Q ISO7321FCQDQ1 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7321FQ ISO7321FCQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 7321FQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 6-Dec-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7320CQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7320FCQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7321CQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7321FCQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7320CQDRQ1 SOIC D 8 2500 367.0 367.0 38.0 ISO7320FCQDRQ1 SOIC D 8 2500 367.0 367.0 38.0 ISO7321CQDRQ1 SOIC D 8 2500 367.0 367.0 38.0 ISO7321FCQDRQ1 SOIC D 8 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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