3 A, 36 V, Synchronous Step-Down DC-to-DC Regulator ADP2443 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT ADP2443 VIN BST PVIN CBST L VOUT SW EN CIN RTOP RRAMP COUT RAMP PGOOD FB RT/SYNC RT COMP VREG CVREG GND RC SS PGND RBOT CC CSS 14794-001 Continuous output current: 3 A Input voltage: 4.5 V to 36 V Integrated MOSFETs: 98 mΩ/35 mΩ Reference voltage: 0.6 V ± 1% Fast minimum on time: 50 ns Programmable switching frequency: 200 kHz to 1.8 MHz Synchronizes to external clock: 200 kHz to 1.8 MHz Precision enable and power good Cycle-by-cycle current limit with hiccup protection External compensation Programmable soft start time Startup into a precharged output Supported by ADIsimPower design tool Figure 1. APPLICATIONS Intermediate power rail conversion Multicell battery powered systems Process control and industrial automation Healthcare and medical Networking and servers GENERAL DESCRIPTION The ADP2443 targets high performance applications that require high efficiency and design flexibility. External compensation and an adjustable soft start function provide design flexibility. The power-good output and precision enable input provide simple and reliable power sequencing. Rev. 0 The ADP2443 operates over the −40°C to +125°C operating junction temperature range and is available in a 24-lead, 4 mm × 4 mm LFCSP package. 100 95 90 85 80 75 70 VOUT = 5V VOUT = 3.3V 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) 14794-002 The ADP2443 uses an emulated current mode, constant frequency pulse-width modulation (PWM) control scheme for excellent stability and transient response. The switching frequency of the ADP2443 can be programmed from 200 kHz to 1.8 MHz. The synchronization function allows the switching frequency be synchronized with an external clock to minimize the system noise. Other key features include undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP), short-circuit protection (SCP), and thermal shutdown (TSD). EFFICIENCY (%) The ADP2443 is synchronous step-down, dc-to-dc regulator with an integrated 98 mΩ, high-side power metal oxide semiconductor field effect transistor (MOSFET) and a 35 mΩ, synchronous rectifier MOSFET to provide a high efficiency solution in a compact 4 mm × 4 mm LFCSP package. The regulators operate from an input voltage range of 4.5 V to 36 V. The output voltage can be adjusted down to 0.6 V and deliver up to 3 A of continuous current. The fast 50 ns minimum on time allows the regulators convert high input voltage to low output voltage at high frequency. Figure 2. Efficiency vs. Output Current, VIN = 24 V, fSW = 300 kHz Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. 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ADP2443 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 15 Applications ....................................................................................... 1 Input Capacitor Selection .......................................................... 15 Typical Application Circuit ............................................................. 1 Output Voltage Setting .............................................................. 15 General Description ......................................................................... 1 Voltage Conversion Limitations ............................................... 15 Revision History ............................................................................... 2 Inductor Selection ...................................................................... 15 Functional Block Diagram .............................................................. 3 Output Capacitor Selection....................................................... 17 Specifications..................................................................................... 4 Programming Input Voltage UVLO ........................................ 17 Absolute Maximum Ratings ............................................................ 6 Slope Compensation Setting ..................................................... 17 Thermal Resistance ...................................................................... 6 Compensation Design ............................................................... 17 ESD Caution .................................................................................. 6 ADIsimPower Design Tool ....................................................... 18 Pin Configuration and Function Descriptions ............................. 7 Design Example .............................................................................. 19 Typical Performance Characteristics ............................................. 8 Output Voltage Setting .............................................................. 19 Theory of Operation ...................................................................... 13 Frequency Setting ....................................................................... 19 Control Scheme .......................................................................... 13 Inductor Selection ...................................................................... 19 Precision Enable/Shutdown ...................................................... 13 Output Capacitor Selection....................................................... 20 Internal Regulator (VREG) ....................................................... 13 Slope Compensation Setting ..................................................... 20 Bootstrap Circuitry .................................................................... 13 Compensation Components ..................................................... 20 Oscillator ..................................................................................... 13 Soft Start Time Program ........................................................... 20 Synchronization .......................................................................... 13 Input Capacitor Selection .......................................................... 20 Soft Start ...................................................................................... 14 Recommended External Components .................................... 21 Power Good ................................................................................. 14 Printed Circuit Board Layout Recommendations ..................... 22 Peak Current-Limit and Short-Circuit Protection................. 14 Typical Applications Circuits ........................................................ 23 Overvoltage Protection (OVP) ................................................. 14 Outline Dimensions ....................................................................... 24 Undervoltage Lockout (UVLO) ............................................... 14 Ordering Guide .......................................................................... 24 Thermal Shutdown ..................................................................... 14 REVISION HISTORY 9/2016—Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADP2443 FUNCTIONAL BLOCK DIAGRAM VREG 4µA ADP2443 EN EN_BUF 0.13µA 5V REGULATOR 1.2V PVIN PGOOD UVLO DEGLITCH GND 0.66V BOOST REGULATOR 0.54V 0.7V BST OVP NFET DRIVER CONTROL LOGIC AND MOSFET DRIVER WITH ANTICROSS PROTECTION FB ISS 0.6V SW VREG AMP AMP CMP NFET DRIVER SS PGND COMP RAMP SLOPE COMPENSATION AND RAMP GENERATOR ACS HICCUP MODE OSC OCP OCP INEG CLK NEGATIVE CURRENT CMP Figure 3. Rev. 0 | Page 3 of 24 IMAX 14794-003 RT/SYNC ADP2443 Data Sheet SPECIFICATIONS VPVIN = 12 V, TJ = −40°C to +125°C for minimum/maximum specifications, TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameters PVIN PVIN Voltage Range Quiescent Current Shutdown Current PVIN Undervoltage Lockout Threshold FB Regulation Voltage Bias Current ERROR AMPLIFIER (EA) Transconductance Source Current Sink Current INTERNAL REGULATOR (VREG) VREG Voltage Dropout Voltage Regulator Current Limit SW High-Side On Resistance 1 Low-Side On Resistance1 Low-Side Valley Current Limit Low-Side Negative Current Limit Leakage Current SW Minimum On Time SW Minimum Off Time BST Bootstrap Voltage OSCILLATOR (RT/SYNC) Switching Frequency Switching Frequency Range Synchronization Range SYNC Minimum Pulse Width SYNC Minimum Off Time SYNC Input Voltage High Low SS SS Pin Pull-Up Current PGOOD Power-Good Range FB Rising Threshold FB Rising Hysteresis FB Falling Threshold FB Falling Hysteresis Power-Good Deglitch Time Power-Good Leakage Current Power-Good Output Low Voltage Symbol VPVIN IQ ISHDN VFB IFB gm ISOURCE ISINK Test Conditions/Comments Min Max Unit 0.868 36 1.1 V mA 28 4.3 3.9 57 4.45 µA V V 4.5 No switching, RAMP connected to PVIN through a resistor EN = GND PVIN rising PVIN falling 3.8 −40°C < TJ < +125°C 0.594 0.6 0.05 0.606 0.2 V µA 485 515 50 50 545 µS µA µA 4.9 5 320 100 5.1 V mV mA 98 35 4.7 2.5 1.5 50 200 147 58 5.1 3 7.9 65 235 mΩ mΩ A A µA ns ns 4.65 5 5.2 V 540 200 200 100 100 600 660 1800 1800 kHz kHz kHz ns ns VFB = 0.45 V VFB = 0.75 V VVREG VPVIN = 12 V, IVREG = 10 mA VPVIN = 12 V, IVREG = 30 mA RDSON_HS RDSON_LS BST pin voltage (VBST) − VSW = 5 V VVREG = 5 V 3.9 2 VSW = 0 V, EN = GND tMIN_ON tMIN_OFF VBOOT fSW Typ RT = 280 kΩ 1.3 ISS Rev. 0 | Page 4 of 24 V V 3.0 3.4 3.8 µA 108 110 5 90 5 16 0.1 220 112 % % % % Clock cycles µA mV 88 Both rising and falling VPGOOD = 5 V IPGOOD = 1 mA 0.4 92 1 300 Data Sheet Parameters EN EN Rising Threshold EN Input Hysteresis EN Current ADP2443 Symbol Test Conditions/Comments EN voltage < 1.1 V, sink current EN voltage > 1.2 V, source current THERMAL SHUTDOWN Threshold Hysteresis 1 Min Typ Max Unit 1.16 1.2 100 0.13 4 1.24 V mV µA µA 150 25 Pin to pin measurement. Rev. 0 | Page 5 of 24 °C °C ADP2443 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter PVIN, EN, PGOOD, RAMP SW BST FB, SS, COMP, RT/SYNC VREG PGND to GND Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating −0.3 V to +40 V −1 V to +40 V VSW + 6 V −0.3 V to +6 V −0.3 V to +6 V −0.3 V to +0.3 V −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 3. Thermal Resistance Package Type CP-24-121 1 θJA 42.6 θJC 6.8 Unit °C/W Thermal impedance simulated value is based on a 4-layer, JEDEC standard board. ESD CAUTION Rev. 0 | Page 6 of 24 Data Sheet ADP2443 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP2443 20 EN 19 PVIN 22 RT/SYNC 21 PGOOD 24 SS 23 RAMP TOP VIEW (Not to Scale) 18 PVIN COMP 1 FB 2 17 PVIN 25 GND VREG 3 16 PVIN 15 BST GND 4 14 SW NOTES 1. EXPOSED GND PAD. THE EXPOSED GND PAD MUST BE SOLDERED TO A LARGE, EXTERNAL, COPPER GND PLANE TO REDUCE THERMAL RESISTANCE. 2. EXPOSED SW PAD. THE EXPOSED SW PAD MUST BE CONNECTED TO THE SW PINS OF THE ADP2443 BY USING SHORT, WIDE TRACES, OR SOLDERED TO A LARGE EXTERNAL SW COPPER PLANE TO REDUCE THERMAL RESISTANCE. 14794-004 PGND 11 13 PGND PGND 12 PGND 9 SW 7 PGND 8 PGND 10 26 SW SW 5 SW 6 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 Mnemonic COMP FB VREG 4 5, 6, 7, 14 8 to 13 15 16 to 19 GND SW PGND BST PVIN 20 EN 21 22 PGOOD RT/SYNC 23 24 25 RAMP SS EP, GND 26 EP, SW Description Error Amplifier Output. Connect an RC network from COMP to GND. Feedback Voltage Sense Input. Connect this pin to a resistor divider from the output voltage (VOUT). Output of the Internal 5 V Regulator. The control circuits are powered from the voltage on this pin. Place a 1 µF, X7R or X5R ceramic capacitor between this pin and GND. Analog Ground. Return of internal control circuit. Switch Node Output. Connect these pins to the output inductor. Power Ground. Return of low-side power MOSFET. Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST. Power Input. Connect these pins to the input power source and connect a bypass capacitor between these pins and PGND. Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the device automatically, connect the EN pin to the PVIN pin. Power-Good Output (Open-Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended. Frequency Setting (RT). Connect a resistor between RT and GND to program the switching frequency between 200 kHz to 1.8 MHz. Synchronization Input (SYNC). Connect this pin to an external clock to synchronize the switching frequency between 200 kHz and 1.8 MHz. See the Oscillator section and the Synchronization section for more information. Slope Compensation Setting. Connect a resistor from RAMP to PVIN to set the slope compensation. Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. Exposed GND Pad. The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal resistance. Exposed SW Pad. The exposed SW pad must be connected to the SW pins of the ADP2443 by using short, wide traces, or soldered to a large external SW copper plane to reduce thermal resistance. Rev. 0 | Page 7 of 24 ADP2443 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 90 80 80 EFFICIENCY (%) 70 60 70 60 50 VOUT = 5V, L = 6.8µH VOUT = 3.3V, L = 4.7µH VOUT = 1.2V, L = 2.2µH 30 0 0.5 1.0 1.5 2.0 2.5 VOUT = 5V, L = 6.8µH VOUT = 3.3V, L = 4.7µH VOUT = 1.2V, L = 2.2µH 40 3.0 OUTPUT CURRENT (A) 30 14794-005 40 0 1.5 2.0 2.5 3.0 Figure 8. Efficiency at VIN = 12 V, fSW = 600 kHz 100 100 90 90 80 80 EFFICIENCY (%) 70 60 70 60 50 50 VOUT = 5V, L = 10µH VOUT = 3.3V, L = 10µH VOUT = 1.2V, L = 4.7µH 30 0 0.5 1.0 1.5 2.0 2.5 VOUT = 5V, L = 10µH VOUT = 3.3V, L = 10µH VOUT = 1.2V, L = 4.7µH 40 3.0 OUTPUT CURRENT (A) 30 14794-006 40 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT CURRENT (A) Figure 6. Efficiency at VIN = 24 V, fSW = 300 kHz 14794-009 EFFICIENCY (%) 1.0 OUTPUT CURRENT (A) Figure 5. Efficiency at VIN = 24 V, fSW = 600 kHz Figure 9. Efficiency at VIN = 12 V, fSW = 300 kHz 100 90 90 80 80 EFFICIENCY (%) 100 70 60 50 70 60 50 VOUT = 5V, L = 3.3µH VOUT = 3.3V, L = 2.2µH 40 30 0 0.5 1.0 1.5 2.0 2.5 OUTPUT CURRENT (A) VOUT = 5V, L = 3.3µH VOUT = 3.3V, L = 2.2µH VOUT = 1.2V, L = 1µH 40 3.0 14794-007 EFFICIENCY (%) 0.5 14794-008 50 Figure 7. Efficiency at VIN = 24 V, fSW = 1.2 MHz 30 0 0.5 1.0 1.5 2.0 2.5 OUTPUT CURRENT (A) Figure 10. Efficiency at VIN = 12 V, fSW = 1.2 MHz Rev. 0 | Page 8 of 24 3.0 14794-010 EFFICIENCY (%) TA = 25oC, VIN = 24 V, VOUT = 5 V, L = 6.8 µH, COUT = 47 µF × 2, fSW = 600 kHz, unless otherwise noted. ADP2443 1000 50 950 40 30 20 TJ = +125°C TJ = +25°C TJ = –40°C 10 0 12 16 20 24 28 32 900 850 800 TJ = +125°C TJ = +25°C TJ = –40°C 750 36 INPUT VOLTAGE (V) 700 12 16 20 24 28 32 36 INPUT VOLTAGE (V) Figure 11. Shutdown Current vs. Input Voltage (VPVIN) 14794-014 QUIESCENT CURRENT (µA) 60 14794-011 SHUTDOWN CURRENT (µA) Data Sheet Figure 14. Quiescent Current vs. Input Voltage (VPVIN) 4.5 1.25 4.4 EN THRESHOLD (V) 4.2 4.1 4.0 1.15 1.10 1.05 RISING FALLING 3.9 RISING FALLING 3.7 –40 –20 0 20 40 60 80 100 1.00 120 TEMPERATURE (°C) 0.95 –40 –20 0 20 40 60 80 100 120 100 120 TEMPERATURE (°C) Figure 12. PVIN UVLO Threshold vs. Temperature 14794-015 3.8 14794-012 PVIN UVLO THRESHOLD (V) 1.20 4.3 Figure 15. EN Threshold vs. Temperature 606 3.60 3.55 SS PULL-UP CURRENT (µA) 602 600 598 3.50 3.45 3.40 3.35 3.30 596 594 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 3.20 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 13. Feedback Voltage vs. Temperature Figure 16. SS Pin Pull-Up Current vs. Temperature Rev. 0 | Page 9 of 24 14794-016 3.25 14794-013 FEEDBACK VOLTAGE (mV) 604 ADP2443 Data Sheet 620 5.10 610 5.00 FREQUENCY (kHz) 4.95 4.90 600 590 RT = 280kΩ –20 0 20 40 60 80 100 570 –40 14794-017 4.80 –40 120 TEMPERATURE (°C) –20 20 40 60 80 100 120 100 120 TEMPERATURE (°C) Figure 17. VREG Voltage vs. Temperature Figure 20. Frequency vs. Temperature 6.0 140 5.5 CURRENT LIMIT THRESHOLD (A) 120 100 80 60 40 20 5.0 4.5 4.0 3.5 RDSON_HS RDSON_LS –20 0 20 40 60 80 100 3.0 –40 14794-018 0 –40 120 TEMPERATURE (°C) 0 20 40 60 80 TEMPERATURE (°C) Figure 21. Current-Limit Threshold vs. Temperature Figure 18. MOSFET On Resistor vs. Temperature VOUT (AC) –20 14794-021 MOSFET ON RESISTOR (mΩ) 0 14794-020 580 4.85 T T 1 EN 3 IL VOUT SW 1 PGOOD 4 2 2 4 CH1 10.0mV B W CH2 10.0V CH4 1.0A BW M2.00µs A CH2 T 50.00% 10.0V 14794-019 IL CH1 2.00V BW CH3 20.0V BW CH2 5.00V BW CH4 1.00A BW M2.00ms A CH3 T 25.30% Figure 22. Voltage Precharged Output Figure 19. Working Mode Waveform Rev. 0 | Page 10 of 24 11.2V 14794-022 VREG VOLTAGE (V) 5.05 Data Sheet ADP2443 T T EN EN 3 3 VOUT VOUT 1 PGOOD 2 1 IOUT 4 PGOOD IOUT CH1 2.00V BW CH3 20.0V BW CH2 5.00V BW CH4 2.00A BW M2.00ms T 27.20% A CH3 11.2V CH1 2.00V BW CH2 5.00V BW M1.00ms CH3 5.00V BW CH4 2.00A BW T 30.00% Figure 23. Soft Start with Full Load A CH3 2.60V 14794-026 2 14794-023 4 Figure 26. Shutdown with Full Load T T VOUT (AC) VOUT (AC) 1 1 PVIN SW IOUT 3 B CH1 100mV M200µs CH4 1.00A BW T 20.00% W A CH4 1.44A CH1 20.0mV BW CH2 20.0V BW M2.00ms A CH3 CH3 10.0V BW T 20.10% Figure 24. Load Transient Response, 0.3 A to 2.7 A 21.0V 14794-027 2 14794-024 4 Figure 27. Line Transient Response, VIN = 12 V to 30 V, IOUT = 3 A T T VOUT VOUT 1 1 SW SW 2 2 IL IL CH1 2.00V BW CH2 20.0V BW CH4 5.00A BW M10.0ms T 20.00% A CH1 3.04V CH1 2.00V BW CH2 20.0V BW M10.0ms CH4 5.00A BW T 80.10% Figure 25. Output Short Entry A CH1 Figure 28. Output Short Recovery Rev. 0 | Page 11 of 24 3.04V 14794-028 4 14794-025 4 Data Sheet 4 3 3 2 VOUT = 12V VOUT = 9V VOUT = 5V VOUT = 1.2V 1 0 65 70 75 80 85 90 95 100 105 0 65 2 VOUT = 5V VOUT = 3.3V VOUT = 1.2V 85 90 95 100 AMBIENT TEMPERATURE (°C) 105 110 14794-030 LOAD CURRENT (A) 3 80 75 80 85 90 95 100 105 Figure 31. Load Current vs. Ambient Temperature at VIN = 36 V, fSW = 600 kHz, Measured on ADP2443-EVALZ 4 75 70 AMBIENT TEMPERATURE (°C) Figure 29. Load Current vs. Ambient Temperature at VIN = 24 V, fSW = 600 kHz, Measured on ADP2443-EVALZ 0 70 VOUT = 12V VOUT = 9V VOUT = 5V VOUT = 2.5V 1 AMBIENT TEMPERATURE (°C) 1 2 14794-031 LOAD CURRENT (A) 4 14794-029 LOAD CURRENT (A) ADP2443 Figure 30. Load Current vs. Ambient Temperature at VIN = 12 V, fSW = 600 kHz, Measured on ADP2443-EVALZ Rev. 0 | Page 12 of 24 Data Sheet ADP2443 THEORY OF OPERATION The ADP2443 operates with an input voltage from 4.5 V to 36 V and regulates the output voltage down to 0.6 V. Additional features that maximize design flexibility include programmable switching frequency, programmable soft start, external compensation, precision enable, and a power-good output. CONTROL SCHEME The ADP2443 uses a fixed frequency, current mode PWM control architecture to achieve high efficiency and low noise operation. The ADP2443 operates at a fixed frequency set by an external resistor from RT/SYNC to GND. It uses the low side NFET current for the PWM control as shown in Figure 32. The valley current information is captured at the end of the off period and combines with the slope ramp to form the emulated current ramp voltage. The slope ramp voltage is controlled by the resistor between RAMP and PVIN. At the start of each oscillator cycle, the highside NFET turns on and the inductor current increases until the emulated current ramp voltage crosses the COMP voltage, which turns off the high-side NFET and turns on the low-side NFET, which in turn places a negative voltage across the inductor, causing a reduction in the inductor current. The low-side NFET stays on for the remainder of the cycle. PVIN IRAMP CLK VRAMP S Q PWM L IN DH VOUT CRAMP RRAMP SW COUT R DL – ACS The on-board 5 V regulator provides a stable supply for the internal circuits. It is recommended that a 1 µF ceramic capacitor be placed between the VREG pin and GND. The internal regulator includes a current-limit circuit to protect the output if the maximum external load current is exceeded. BOOTSTRAP CIRCUITRY The ADP2443 includes a regulator to provide the gate drive voltage for the high-side N-MOSFET. It uses differential sensing to generate a 5 V bootstrap voltage between the BST and SW pins. It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor be placed between the BST pin and the SW pin. OSCILLATOR The switching frequency of ADP2443 is controlled by the RT/SYNC pin. A resistor from RT/SYNC to GND programs the switching frequency according to the following equation: f SW (kHz) = 2200 2000 gm 1800 1600 1400 1200 1000 800 600 400 200 0 RBOT 0 0.6V 14794-032 RC RT (kΩ) A 280 kΩ resistor sets the frequency to 600 kHz, and a 560 kΩ resistor sets the frequency to 300 kHz. Figure 33 shows the typical relationship between fSW and RT. RTOP VCOMP 168,000 CC Figure 32. PWM Control Scheme 100 200 300 400 500 600 700 RT (kΩ) 800 900 14794-033 PVIN INTERNAL REGULATOR (VREG) SWITCHING FREQUENCY (kHz) The ADP2443 is synchronous step-down, dc-to-dc regulator that uses an emulated current-mode architecture with an integrated high-side power switch and a low-side synchronous rectifier. The regulator targets high performance applications that require high efficiency and design flexibility. Figure 33. Switching Frequency vs. RT SYNCHRONIZATION PRECISION ENABLE/SHUTDOWN The EN input pin has a precision analog threshold of 1.2 V (typical) with 100 mV of hysteresis. When the enable voltage exceeds 1.2 V, the regulator turns on; when it falls below 1.1 V (typical), the regulator turns off. To force the regulator to start automatically when input power is applied, connect EN to PVIN. The precision EN pin has an internal pull-down current source (0.13 µA) that provides a default turn-off when the EN pin is open. When the EN pin voltage exceeds 1.2 V (typical), the ADP2443 is enabled and the internal pull-up current increases to 4 µA, which allows users to program the PVIN UVLO and hysteresis. To synchronize the ADP2443, connect an external clock to the RT/SYNC pin. The frequency of the external clock can be in the range of 200 kHz to 1.8 MHz. During synchronization, the regulator operates in continuous conduction mode (CCM) and the rising edge of the switching waveform runs 180° out of phase to the rising edge of the external clock. When the ADP2443 is operating in synchronization mode, a resistor must be connected from the RT/SYNC pin to GND to program the internal oscillator to run at 80% to 120% of the external synchronization clock. Rev. 0 | Page 13 of 24 ADP2443 Data Sheet SOFT START The ADP2443 uses the SS pin to program the soft start time. Place a capacitor between SS and GND; an internal current charges this capacitor to establish the soft start ramp. Calculate the soft start time (tSS) using the following equation: 0.6 V × CSS I SS CYCLE-BY-CYCLE THRESHOLD where: CSS is the soft start capacitance. ISS is the typical soft start pull-up current (3.4 µA). PVIN CURRENT-LIMIT COMPARATOR IRAMP VRAMP If the output voltage is precharged before power up, the ADP2443 prevents the low-side MOSFET from turning on until the soft start voltage exceeds the voltage on the FB pin. RRAMP HICCUP CONTROL BLOCK CRAMP PWM POWER GOOD SW Figure 35. Current-Limit Circuit CYCLE-BY-CYCLE PEAK CURRENT-LIMIT THRESHOLD VRAMP The power-good circuitry monitors the output voltage on the FB pin and compares it to the rising and falling thresholds that are specified in Table 1. If the rising output voltage exceeds the target value, the PGOOD pin is held low. The PGOOD pin continues to be held low until the falling output voltage returns to the target value. If the output voltage falls below the target output voltage, the PGOOD pin is held low. The PGOOD pin continues to be held low until the rising output voltage returns to the target value. The power-good rising and falling thresholds are shown in Figure 34. There is always a 16-cycle waiting period (deglitch) before the PGOOD pin is pulled from low to high or from high to low. VOUT FALLING VOUT RISING VOUT (%) 16-CYCLE DEGLITCH 14794-034 PGOOD 16-CYCLE DEGLITCH PWM VALLEY CURRENT-LIMIT THRESHOLD Figure 36. Cycle-By-Cycle Current-Limit Waveform OVERVOLTAGE PROTECTION (OVP) The ADP2443 includes an OVP feature to protect the regulator against an output short to a higher voltage supply or when a strong load disconnect transient occurs. If the feedback voltage increases to 0.7 V, the internal high-side MOSFET and low-side MOSFET are turned off until the voltage at the FB pin decreases to 0.63 V. At that time, the ADP2443 resumes normal operation. UNDERVOLTAGE LOCKOUT (UVLO) 110% 105% 100% 95% 90% 16-CYCLE DEGLITCH 14794-035 – ACS The power-good pin (PGOOD) is an active high, open-drain output that requires an external resistor to pull it up to a voltage. A logic high on the PGOOD pin indicates that the voltage on the FB pin (and therefore the output voltage) is within regulation. 16-CYCLE DEGLITCH VFB 14794-036 t SS = The overcurrent counter increments during this process; otherwise the overcurrent counter decreases. If the overcurrent counter reaches 10 or the FB voltage drops below 0.2 V after the soft start, the device enters hiccup mode. During hiccup mode, the high-side NFET and low-side NFET are both turned off. The device remains in this mode for seven soft start cycles and then attempts to restart with soft start. If the current-limit fault is cleared, the device resumes normal operation; otherwise, it reenters hiccup mode. Figure 34. PGOOD Rising and Falling Thresholds PEAK CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION The ADP2443 uses the emulated current ramp voltage for cycleby-cycle current limit protection to prevent current runaway. When the emulated current ramp voltage reaches the valley current limit threshold plus the ramp voltage, the high-side MOSFET turns off and the low-side MOSFET turns on until the next cycle. UVLO circuitry is integrated in the ADP2443 to prevent the occurrence of power-on glitches. If the VPVIN voltage drops below 3.9 V typical, the device shuts down and both the power switch and synchronous rectifier turn off. When the VPVIN voltage rises again above 4.3 V typical, the soft start period is initiated and the device is enabled. THERMAL SHUTDOWN If the ADP2443 junction temperature rises above 150°C, the internal thermal shutdown circuit turns off the regulator for self protection. Extreme junction temperatures can be the result of high current operation, poor PCB layout thermal design, and/or high ambient temperature. A 25°C hysteresis is included in the thermal shutdown circuit so that, if an overtemperature event occurs, the ADP2443 does not return to normal operation until the on-chip temperature drops below 125°C. Upon recovery, a soft start is initiated before normal operation begins. Rev. 0 | Page 14 of 24 Data Sheet ADP2443 APPLICATIONS INFORMATION INPUT CAPACITOR SELECTION The input capacitor reduces the input voltage ripple caused by the switch current on PVIN. Place the input capacitor as close as possible to the PVIN pin. A ceramic capacitor in the 10 μF to 47 μF range is recommended. The loop that is composed of this input capacitor, the high-side N-MOSFET, and the low-side NMOSFET must be kept as small as possible. The voltage rating of the input capacitor must be greater than the maximum input voltage. The rms current rating of the input capacitor must be larger than the value calculated from the following equation: ICIN_RMS = IOUT × The maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and the maximum duty cycle. The minimum off time is typically 200 ns. Calculate the maximum output voltage, limited by the minimum off time at a given input voltage and frequency, using the following equation: VOUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) × IOUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2) D × (1 − D ) OUTPUT VOLTAGE SETTING The output voltage of the ADP2443 is set by an external resistor divider. The resistor values are calculated using VOUT = 0.6 × 1 + RTOP RBOT INDUCTOR SELECTION The inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple current. Using a small inductor results in a faster transient response but degrades efficiency, due to a larger inductor ripple current; whereas using a large inductor value results in s smaller ripple current and better efficiency, but also results in a slower transient response. Table 5 lists the recommended resistor divider values for various output voltages. Table 5. Resistor Divider Values for Various Output Voltages RTOP ± 1% (kΩ) 10 10 15 20 47.5 10 22 44.2 39.2 52.3 RBOT ± 1% (kΩ) 15 10 10 10 15 2.21 3 3.57 2.49 2.74 As a guideline, the inductor ripple current, ΔIL, is typically set to one-third of the maximum load current. Calculate the inductor value using the following equation: L = (VIN − VOUT ) × D ∆I L × f SW VOLTAGE CONVERSION LIMITATIONS The minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. The minimum on time of the ADP2443 is typically 50 ns. Calculate the minimum output voltage at a given input voltage and frequency using the following equation: VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) × IOUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN where: VOUT_MIN is the minimum output voltage. tMIN_ON is the minimum on time. fSW is the switching frequency. RDSON_HS is the high-side MOSFET on resistance. where: VOUT_MAX is the maximum output voltage. tMIN_OFF is the minimum off time. IOUT_MAX is the maximum output current. As Equation 1 and Equation 2 show, reducing the switching frequency alleviates the minimum on time and minimum off time limitations. To limit output voltage accuracy degradation due to FB bias current (0.1 µA maximum) to less than 0.5% (maximum), ensure that RBOT < 30 kΩ. VOUT (V) 1.0 1.2 1.5 1.8 2.5 3.3 5.0 8.0 10.0 12.0 RDSON_LS is the low-side MOSFET on resistance. IOUT_MIN is the minimum output current. RL is the series resistance of output inductor. (1) where: VIN is the input voltage. VOUT is the output voltage. D is the duty cycle. ΔIL is the inductor current ripple. fSW is the switching frequency. D = VOUT VIN Calculate the peak inductor current using IPEAK = IOUT + ∆I L 2 The saturation current (ISAT) of the inductor must be larger than the peak inductor current. For ferrite core inductors with a quick saturation characteristic, the saturation current rating of the inductor must be greater than the current limit threshold of the switch, which prevents the inductor from reaching saturation. Rev. 0 | Page 15 of 24 ADP2443 Data Sheet Shielded ferrite core materials are recommended for low core loss and low EMI. Table 6 lists recommended inductors. Calculate the rms current of the inductor from the following equation: IRMS = I OUT 2 + ∆I L 2 12 Table 6. Recommended Inductors Vendor Toko CoilCraft Würth Elektronik Part Number FDVE0630-R75M FDVE0630-1R0M FDVE1040-1R5M FDVE1040-2R2M FDVE1040-3R3M FDVE1040-4R7M FDVE1040-5R6M FDVE1040-6R8M FDVE1040-100M XAL5030-601ME XAL5030-801ME XAL6030-102ME XAL6030-122ME XAL6030-182ME XAL6030-222ME XAL6030-332ME XAL6060-472ME XAL6060-562ME XAL6060-682ME XAL6060-822ME XAL6060-103ME XAL6060-153ME XAL6060-223ME 744 333 0068 744 333 0082 744 333 0100 744 333 0150 744 333 0220 744 333 0330 744 333 0470 744 333 0680 744 333 0820 744 333 100 0 744 373 490 068 744 373 490 082 744 373 490 10 744 373 490 15 744 373 490 22 744 373 490 33 744 373 490 47 744 373 490 68 744 373 490 82 744 373 491 00 744 373 492 20 Value (µH) 0.75 1.0 1.5 2.2 3.3 4.7 5.6 6.8 10 0.6 0.8 1.0 1.2 1.8 2.2 3.3 4.7 5.6 6.8 8.2 10 15 22 0.68 0.82 1.0 1.5 2.2 3.3 4.7 6.8 8.2 10 0.68 0.82 1.0 1.5 2.2 3.3 4.7 6.8 8.2 10 22 ISAT (A) 10.9 9.5 13.7 11.4 9.8 8.2 7.9 7.1 6.1 19.8 18.5 23 22 18.2 15.9 12.2 10.5 9.9 9.2 8.4 7.6 5.8 5.6 38 36 27.5 27 22 15.5 15 11 8 8 26 25 19.5 14.5 14 12 11 9.5 9 8 6.5 Rev. 0 | Page 16 of 24 IRMS (A) 10.7 9.5 14.6 11.6 9.0 8.0 7.3 7.1 5.2 17.7 13 18 16 14 10 8 11 10 9 8 7 6 5 20 20 20 18 16.5 14 13 11.5 11.5 9 12 11.3 10 8 7.5 6 5 3.5 3.3 3.2 2.1 DC Resistance (DCR) (mΩ) 6.2 8.5 4.6 6.8 10.1 13.8 18.0 20.2 34.1 4.52 5.65 6.18 7.5 10.5 14.0 20.8 16.4 17.8 20.8 26.4 29.8 43.8 60.6 1.35 1.35 1.35 2.5 3.7 5.4 8.2 13.2 13.2 20.7 4.5 4.9 6.5 9 12 20.9 30.8 51.5 63 69 170 Data Sheet ADP2443 OUTPUT CAPACITOR SELECTION PROGRAMMING INPUT VOLTAGE UVLO The output capacitor selection affects the output ripple voltage load step transient and the loop stability of the regulator. The ADP2443 has a precision enable input to program the UVLO threshold of the input voltage (see Figure 37). For example, during a load step transient where the load is suddenly increased, the output capacitor supplies the load until the control loop can ramp up the inductor current. The delay caused by the control loop causes the output to undershoot. Calculate the output capacitance that is required to satisfy the voltage droop requirement using the following equation: ADP2443 PVIN 4µA RTOP_EN EN 0.13µA EN CMP K UV × ∆I STEP 2 × L COUT_UV = 2 × (V IN − VOUT ) × ∆VOUT _ UV Figure 37. Programming the Input Voltage UVLO Use the following equation to calculate RTOP_EN and RBOT_EN: where: KUV is a factor, with a typical setting of KUV = 2. ΔISTEP is the load step. ΔVOUT_UV is the allowable undershoot on the output voltage. RTOP _ EN = Another example occurs when a load is suddenly removed from the output, and the energy stored in the inductor rushes into the output capacitor, causing the output to overshoot. R BOT _ EN = (VOUT + ∆VOUT _ OV ) − VOUT 2 where: KOV is a factor, with a typical setting of KOV = 2. ΔVOUT_OV is the allowable overshoot on the output voltage. The output ripple is determined by the effective series resistance (ESR) and the value of the capacitance. Use the following equation to select a capacitor that can meet the output ripple requirements: COUT_RIPPLE = ∆I L 8 × f SW × ∆VOUT _ RIPPLE VIN _ RISING − RTOP _ EN × 0.13 µA − 1.2 V The slope compensation is necessary in a current mode control architecture to prevent subharmonic oscillation and to maintain a stable output. The ADP2443 uses the emulated current mode and the slope compensation is implemented by connecting a resistor (RRAMP) between the RAMP pin and PVIN pin. Theoretically, an extra slope of VOUT/(2 × L) is enough to stabilize the system. To guarantee that any noise is decimated in one cycle and the system is stable from subharmonic oscillation, the ADP2443 uses an extra slope of VOUT/L. ∆VOUT _ RIPPLE RRAMP = ∆I L L × 1012 3.9 where L is the inductor value. where RESR is the equivalent series resistance of the output capacitor in ohms (Ω). COMPENSATION DESIGN Select the largest output capacitance given by COUT_UV, COUT_OV, and COUT_RIPPLE to meet both load transient and output ripple performance. The selected output capacitor voltage rating must be greater than the output voltage. The rms current rating of the output capacitor must be greater than the value that is calculated by using the following equation: ICOUT_RMS = ∆I L 12 1.2 V × RTOP _ EN Calculate the ramp resistor value, RRAMP, using the following equation: where ΔVOUT_RIPPLE is the allowable output ripple voltage. RESR = 1.1 V × 0.13 µA + 1.2 V × 3.87 µA SLOPE COMPENSATION SETTING K OV × ∆I STEP 2 × L 2 1.1 V × VIN _ RISING − 1.2 V × VIN _ FALLING where: VIN_RISING is the VIN rising threshold. VIN_FALLING is the VIN falling threshold. Calculate the output capacitance that is required to meet the overshoot requirement using the following equation: COUT_OV = 14794-037 1.2V RBOT_EN The ADP2443 uses an emulated current mode control architecture that combines the fast line transient response of traditional peak current mode with the capability to convert a high input voltage to a very low output voltage. Furthermore, the small signal characteristics of the emulated current mode are almost identical to those of traditional peak current mode. Therefore, the compensation network design method used in traditional peak current mode can also be applied to the emulated current mode control. The power stage can be simplified as a voltage controlled current source supplying current to the output capacitor and load resistor. It is composed of one domain pole and a zero. Rev. 0 | Page 17 of 24 ADP2443 Data Sheet 1 RC CC s GVD ( s ) R CC CCP s (1 C s) CC CCP The control to output transfer function is based on the following equations: s 1 2π f Z V (s) GVD (s) OUT AVI R VCOMP (s) s 1 2π f P The following design guideline shows how to select the RC, CC, and CCP compensation components for ceramic output capacitor applications: 1. where: AVI = 10 A/V. R is the load resistance. fZ 2. RC 1 2 π R ESR COUT 3. where: RESR is the ESR of the output capacitor. COUT is the output capacitance. fP Determine the cross frequency, fC. Generally, fC is between fSW/12 and fSW/6. Calculate RC using the following equation: 2 VOUT C OUT f C 0.6 V g m AVI Place the compensation zero at the domain pole, fP; then determine CC using the following equation: CC (R R ESR ) C OUT 1 2π (R R ESR ) COUT 4. The ADP2443 uses a transconductance amplifier for the error amplifier and to compensate the system. Figure 38 shows the simplified, peak current mode control, small signal circuit. VOUT COUT RBOT AVI VCOMP RC CCP R RESR 14794-038 CC Figure 38. Simplified Peak Current Mode Control, Small Signal Circuit The compensation components, RC and CC, contribute a zero, and the optional CCP and RC contribute an optional pole. The closed-loop transfer equation is as follows: TV (s) R BOT R BOT RTOP g m CC CCP CCP is optional. It can be used to cancel the zero caused by the ESR of the output capacitor. C CP R ESR C OUT RC ADIsimPOWER DESIGN TOOL VOUT RTOP gm RC The ADP2443 is supported by the ADIsimPower™ design tool set. ADIsimPower is a collection of tools that produce complete power designs that are optimized for a specific design goal. The tools enable the user to generate a full schematic and bill of materials and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and component count, while taking into consideration the operating conditions and limitations of the IC and all real external components. For more information about the ADIsimPower design tools, refer to www.analog.com/ADIsimPower. The tool set is available from this website, and users can request an unpopulated board. Rev. 0 | Page 18 of 24 Data Sheet ADP2443 DESIGN EXAMPLE ADP2443 CIN 10µF 50V RRAMP 1.5MΩ RT 280kΩ CVREG 1µF CSS 22nF PVIN EN BST SW RAMP PGOOD RT/SYNC VREG SS GND CBST 0.1µF VOUT = 5V COUT 47µF 16V RTOP 22kΩ 1% FB COMP PGND L 6.8µH CCP 3.3pF RC 20kΩ CC 2.7nF RBOT 3kΩ 1% 14794-039 VIN = 24V Figure 39. Schematic for Design Example This section describes the procedures for selecting the external components based on the example specifications that are listed in Table 7. See Figure 39 for the schematic of this design example. Table 7. Step-Down DC-to-DC Regulator Requirements Parameter Input Voltage Output Voltage Output Current Output Voltage Ripple Load Transient Switching Frequency Symbol VIN VOUT IOUT ∆VOUT_RIPPLE ILOAD fSW Specification VIN = 24.0 V ± 10% VOUT = 5 V IOUT = 3 A ∆VOUT_RIPPLE = 50 mV ±5%, 0.5 A to 2.5 A, 2 A/μs fSW = 600 kHz This calculation results in L = 7.33 μH. Choose the standard inductor value of 6.8 μH. The peak-to-peak inductor ripple current can be calculated by using the following equation: I L (V IN VOUT ) D L f SW This calculation results in ΔIL = 0.97 A. Use the following equation to calculate the peak inductor current: I PEAK I OUT I L 2 OUTPUT VOLTAGE SETTING This calculation results in IPEAK = 3.49 A. Choose a 22 kΩ resistor as the top feedback resistor (RTOP), and calculate the bottom feedback resistor (RBOT) by using the following equation: Use the following equation to calculate the rms current flowing through the inductor: R BOT RTOP I RMS I OUT 2 0. 6 V 0 . 6 OUT 12 This calculation results in IRMS = 3.013 A. To set the output voltage to 5 V, the resistors values are as follows: RTOP = 22 kΩ and RBOT = 3 kΩ. Based on the calculated current value, select an inductor with a minimum rms current rating of 3.013 A and a minimum saturation current rating of 3.49 A. FREQUENCY SETTING To set the switching frequency to 600 kHz, connect a 280 kΩ resistor from the RT/SYNC pin to GND. INDUCTOR SELECTION The peak-to-peak inductor ripple current, ΔIL, is set to 30% of the maximum output current. Use the following equation to estimate the inductor value: L I L 2 However, to protect the inductor from reaching its saturation point under the current-limit condition, the inductor must be rated for at least a 5.1 A saturation current for reliable operation. Based on the requirements described previously, select a 6.8 μH inductor, such as the FDVE1040-6R8M from Toko, which has a 20.2 mΩ DCR and an 7.1 A saturation current. (V IN VOUT ) D I L f SW where: VIN = 24 V. VOUT = 5 V. D = 0.208. ΔIL = 0.9 A. fSW = 600 kHz. Rev. 0 | Page 19 of 24 ADP2443 Data Sheet OUTPUT CAPACITOR SELECTION COMPENSATION COMPONENTS The output capacitor is required to meet both the output voltage ripple and load transient response requirements. For better load transient and stability performance, set the cross frequency, fC, to fSW/10. In this case, fSW is running at 600 kHz; therefore, the fC is set to 60 kHz. To meet the output voltage ripple requirement, use the following equation to calculate the ESR and capacitance value of the output capacitor: 8 × f SW × ∆VOUT _ RIPPLE CC = ∆VOUT _ RIPPLE ∆I L C OUT _ OV = (VOUT + ∆VOUT _ OV )2 − VOUT 2 MAGNITUDE (dB) This calculation results in COUT_OV = 21.2 μF, and COUT_UV = 5.7 μF. According to the calculation, the output capacitance must be greater than 21.2 μF, and the ESR of the output capacitor must be smaller than 51.5 mΩ. It is recommended that one 47 μF/X5R/16 V ceramic capacitor be used, such as the GRM32ER61C476KE15K from Murata, with an ESR of 2 mΩ. SLOPE COMPENSATION SETTING The ramp resistor, RRAMP, determines the slope compensation. Use the following equation to calculate the RRAMP value: 3. 9 6.8 μH × 1012 3. 9 19.5 kΩ = 3.3 pF 180 48 144 36 108 24 2 × (VIN − VOUT ) × ∆VOUT _ UV = 0.002 Ω × 32 µF = 2739 pF 60 K UV × ∆I STEP 2 × L L × 1012 19.5 kΩ Figure 40 shows the Bode plot at a 3 A load current. The cross frequency is 59 kHz, and the phase margin is 66°. K OV × ∆I STEP 2 × L where ∆VOUT_UV = 5% VOUT is the undershoot voltage. RRAMP = 1.667 Ω + 0.002 Ω × 32 µF = 19.5 kΩ Choose standard components, as follows: RC = 20 kΩ, CC = 2700 pF, and CCP = 3.3 pF. where: KOV = KUV = 2 are the coefficients for estimation purposes. ∆ISTEP = 2 A is the load transient step. ∆VOUT_OV = 5% VOUT is the overshoot voltage. C OUT _ UV = 0.6 V × 515 µs × 10 A/V CCP = This calculation results in COUT_RIPPLE = 4.04 μF, and RESR = 51.5 mΩ. To meet the ±5% overshoot and undershoot transient requirements, use the following equations to calculate the capacitance: 2 × π × 5 V × 32 µF × 60 kHz 72 PHASE 12 36 0 0 MAGNITUDE –12 –36 –24 –72 –36 –108 –48 –144 –60 1k PHASE (Degrees) R ESR = RC = ∆I L –180 10k 100k FREQUENCY (Hz) 1M 14794-040 COUT _ RIPPLE = The 47 µF ceramic output capacitor has a derated value of 32 µF. Figure 40. Bode Plot at 3 A SOFT START TIME PROGRAM The soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overshoot during soft start and limiting the inrush current. Set the soft start time to 4 ms. = 1.74 MΩ CSS = Choose a standard component value, as follows: RRAMP = 1.5 MΩ. t SS _ EXT × I SS 0.6 V = 4 ms × 3.4 µA 0.6 V = 22.7 nF Choose a standard component value, as follows: CSS = 22 nF. INPUT CAPACITOR SELECTION A minimum 10 μF ceramic capacitor must be placed near the PVIN pin. In this application, it is recommended that one 10 μF, X5R, 50 V ceramic capacitor be used. Rev. 0 | Page 20 of 24 Data Sheet ADP2443 RECOMMENDED EXTERNAL COMPONENTS Table 8. Recommended External Components for Typical Applications with a 3 A Output Current fSW (kHz) 300 VIN (V) 12 24 600 12 24 1200 12 24 1 VOUT (V) 1 1.2 1.5 1.8 2.5 3.3 5 1 1.2 1.5 1.8 2.5 3.3 5 8 12 1 1.2 1.5 1.8 2.5 3.3 5 1.2 1.5 1.8 2.5 3.3 5 8 12 1.2 1.5 1.8 2.5 3.3 5 2.5 3.3 5 8 12 L (µH) 3.3 3.3 4.7 4.7 6.8 8.2 10 3.3 4.7 4.7 6.8 8.2 10 15 22 22 1.5 2.2 2.2 3.3 3.3 4.7 4.7 2.2 2.2 3.3 4.7 4.7 6.8 10 10 1 1 1.5 1.5 2.2 2.2 2.2 2.2 3.3 4.7 4.7 COUT (µF) 1 470 + 100 330 + 100 330 220 3 × 100 2 × 100 2 × 47 470 + 100 470 + 100 330 330 220 3 × 100 2 × 100 2 × 47 47 220 + 47 220 + 47 3 × 100 3 × 100 100 + 47 2 × 47 47 220 + 47 3 × 100 3 × 100 2 × 100 2 × 47 100 47 47 2 × 100 2 × 47 100 + 47 100 47 47 100 47 47 47 47 RTOP (kΩ) 10 10 15 20 47.5 10 22 10 10 15 20 47.5 10 22 44.2 52.3 10 10 15 20 47.5 10 22 10 15 20 47.5 10 22 44.2 52.3 10 15 20 47.5 10 22 47.5 10 22 44.2 52.3 RBOT (kΩ) 15 10 10 10 15 2.21 3 15 10 10 10 15 2.21 3 3.57 2.74 15 10 10 10 15 2.21 3 10 10 10 15 2.21 3 3.57 2.74 10 10 10 15 2.21 3 15 2.21 3 3.57 2.74 RRAMP (kΩ) 845 845 1000 1000 1500 2700 2700 845 1000 1000 1500 2700 2700 3300 5600 5600 383 562 562 845 845 1000 1000 562 562 845 1000 1000 1500 2700 2700 255 255 383 383 562 562 562 562 845 1000 1000 RC (kΩ) 33.2 29.4 30.9 24.9 28 24.9 18.7 33.2 40.2 30.9 37.4 34.8 37.4 28 22.1 10.5 31.6 37.4 34 41.2 28 24.9 18.7 37.4 34 41.2 37.4 24.9 28 22.1 21 36.5 22.6 41.2 37.4 24.9 37.4 37.4 24.9 37.4 44.2 42.2 CC (pF) 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 5600 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 2700 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 CCP (pF) 120 100 100 82 12 10 6.8 120 100 100 82 68 10 6.8 3.9 2.7 56 47 10 8.2 6.8 4.7 3.3 47 10 8.2 6.8 4.7 3.3 1.8 1.2 6.8 5.6 4.7 3.3 2.2 1.5 3.3 2.2 1.5 1 0.5 680 μF: 4 V, KEMET T520Y687M004ATE010; 470 μF: 6.3 V, KEMET T520X477M006ATE010; 330 μF: 6.3 V, KEMET T520D337M006ATE009; 220 μF: 6.3 V, KEMET T520D227M006ATE009; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 16 V, X5R, Murata GRM32ER61C476KE15K. Rev. 0 | Page 21 of 24 ADP2443 Data Sheet PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good PCB layout is essential for obtaining the best performance from the ADP2443. Poor PCB layout can degrade the output regulation, as well as the electromagnetic interface (EMI) and electromagnetic compatibility (EMC) performance. Figure 42 shows an example of a good PCB layout for the ADP2443. For optimum layout, refer to the following guidelines: ADP2443 VIN PVIN CIN BST SW EN CBST RRAMP RAMP PGOOD RT/SYNC VREG RT FB COMP SS RC CSS PGND VIA RT EN PGOOD RT/SYNC RAMP SS PVIN PVIN CSS CC COPPER PLANE RRAMP COMP PVIN GND FB PVIN VREG INPUT BYPASS CAP INPUT BULK CAP PVIN CVREG BST GND CBST SW SW SW SW PGND PGND PGND PGND PGND POWER GROUND PLANE 14794-042 OUTPUT CAPACITOR PGND SW SW INDUCTOR RBOT CC Figure 41. High Current Path in the PCB Circuit BOTTOM LAYER TRACE RTOP VOUT COUT 14794-041 GND L RTOP CVREG ANALOG GROUND PLANE RC CCP Use separate analog ground planes and power ground planes. Connect the ground reference of sensitive analog circuitry, such as output voltage divider components, compensation components, frequency setting components, and soft start capacitor, to analog ground (GND). In addition, connect the ground reference of the power components, such as input and output capacitors, to power ground (PGND). Connect both ground planes to the exposed GND pad of the ADP2443. Place the input capacitor, inductor, and output capacitor as close as possible to the IC, and use short traces. Ensure that the high current loop traces are as short and as wide as possible. Make the high current path from the input capacitor through the inductor, the output capacitor, and the power ground plane back to the input capacitor as short as possible. To accomplish this, ensure that the input and output capacitors share a common power ground plane. In addition, ensure that the high current path from the power ground plane through the inductor and output capacitor back to the power ground plane is as short as possible by tying the PGND pins of the ADP2443 to the PGND plane as close as possible to the input and output capacitors. RBOT Connect the exposed GND pad of the ADP2443 to a large, external copper ground plane to maximize its power dissipation capability and minimize junction temperature. In addition, connect the exposed SW pad to the SW pins of the ADP2443, using short, wide traces; or connect the exposed SW pad to a large copper plane of the switching node for high current flow. Place the feedback resistor divider as close as possible to the FB pin to prevent noise pickup. Minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. To reduce noise pickup further, place an analog ground plane on either side of the FB trace and ensure that the trace is as short as possible to reduce the parasitic capacitance pickup. VOUT Figure 42. Recommended PCB Layout Rev. 0 | Page 22 of 24 Data Sheet ADP2443 TYPICAL APPLICATIONS CIRCUITS ADP2443 CIN 10µF 50V RRAMP 1MΩ RPGOOD 100kΩ SW EN L 4.7µH VOUT = 3.3V FB COMP SS RT 280kΩ GND CSS 22nF PGND CCP 4.7pF RC 26.7kΩ CC 2.7nF COUT2 47µF 6.3V COUT1 47µF 6.3V RTOP 10kΩ 1% RAMP PGOOD VREG RT/SYNC CVREG 1µF CBST 0.1µF BST PVIN RBOT 2.21kΩ 1% 14794-043 VIN = 24V Figure 43. Typical Application Circuit, VIN = 24 V, VOUT = 3.3 V, IOUT = 3A, fSW = 600 kHz ADP2443 CIN 10µF 50V RRAMP 499kΩ RTOP_EN 84.5kΩ RBOT_EN 5.36kΩ PVIN BST SW EN COUT2 100µF 6.3V FB VREG COMP RT/SYNC RT 340kΩ VOUT = 1.2V COUT1 220µF 6.3V RTOP 10kΩ 1% PGOOD RAMP CVREG 1µF L 2.2µH CBST 0.1µF GND SS CSS 47nF PGND CCP 56pF RC 34.8kΩ CC 3.3nF RBOT 10kΩ 1% 14794-044 VIN = 24V Figure 44. Programming Input Voltage UVLO Rising Threshold at 20 V, Falling Threshold at 18 V, VIN = 24 V, VOUT = 1.2 V, IOUT = 3 A, fSW = 500 kHz ADP2443 BST PVIN CIN 10µF 50V RRAMP 845kΩ CVREG RPGOOD 1µF 100kΩ SW EN RT 140kΩ CSS 22nF COUT 47µF 16V FB COMP RT/SYNC SS GND VOUT = 5V RTOP 22kΩ 1% RAMP PGOOD VREG L CBST 3.3µH 0.1µF CCP 1.5pF PGND RC 40.2kΩ CC 1.2nF RBOT 3kΩ 1% Figure 45. Typical Application Circuit, VIN = 24 V, VOUT = 5 V, IOUT = 3 A, fSW = 1.2 MHz Rev. 0 | Page 23 of 24 14794-045 VIN = 24V ADP2443 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR 0.20 MIN 0.20 MIN 2.80 2.70 2.60 0.20 MIN 19 PIN 1 INDICATOR 1.50 1.40 1.30 0.45 24 18 1 EXPOSED PAD 0.50 BSC 0.35 0.25 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 1.05 0.95 0.85 6 13 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD . 04-28-2014-C 4.10 4.00 SQ 3.90 Figure 46. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP2443ACPZN-R7 ADP2443-EVALZ 1 Temperature Range −40°C to +125°C Output Voltage Adjustable Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14794-0-9/16(0) Rev. 0 | Page 24 of 24 Package Description 24-Lead LFCSP Evaluation Board Package Option CP-24-12