TI1 HPA01164RUTR 4-bit bidirectional voltage-level translator with automatic direction sensing and 15-kv esd protection Datasheet

Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
TXB0104 4-Bit Bidirectional Voltage-level Translator With Automatic Direction Sensing
and ±15-kV ESD Protection
1 Features
3 Description
•
This 4-bit non-inverting translator uses two separate
configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V,
1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
VCCA should not exceed VCCB.
1
•
•
•
•
•
•
1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on B
Port (VCCA ≤ VCCB)
VCC Isolation Feature – If Either VCC Input Is at
GND, All Outputs Are in the High-Impedance
State
OE Input Circuit Referenced to VCCA
Low Power Consumption, 5-μA Max ICC
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port
– 2500-V Human-Body Model (A114-B)
– 1500-V Charged-Device Model (C101)
– B Port
– ±15-kV Human-Body Model (A114-B)
– 1500-V Charged-Device Model (C101)
2 Applications
•
•
•
•
Headset
Smartphone
Tablet
Desktop PC
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state. To ensure
the high-impedance state during power up or power
down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
The TXB0104 is designed so that the OE input circuit
is supplied by VCCA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
TXB0104
PACKAGE
BODY SIZE (NOM)
UQFN (12)
2.00 mm x 1.70 mm
SOIC (14)
8.65 mm x 3.91 mm
BGA
MICROSTAR
JUNIOR (12)
2.00 mm x 2.50 mm
TSSOP (14)
5.00 mm x 4.40 mm
VQFN (14)
3.50 mm x 3.50 mm
DSBGA (12)
1.40 mm x 1.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram for TXB010X
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
5
5
5
6
6
7
7
7
7
8
8
8
8
9
9
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements: VCCA = 1.2 V .........................
Timing Requirements: VCCA = 1.5 V ± 0.1 V ............
Timing Requirements: VCCA = 1.8 V ± 0.15 V ..........
Timing Requirements: VCCA = 2.5 V ± 0.2 V ............
Timing Requirements: VCCA = 3.3 V ± 0.3 V ..........
Switching Characteristics: VCCA = 1.2 V .................
Switching Characteristics: VCCA = 1.5 V ± 0.1 V ....
Switching Characteristics: VCCA = 1.8 V ± 0.15 V ..
Switching Characteristics: VCCA = 2.5 V ± 0.2 V ....
Switching Characteristics: VCCA = 3.3 V ± 0.3 V ....
6.16 Operating Characteristics...................................... 10
6.17 Typical Characteristics .......................................... 11
7
8
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1 Trademarks ........................................................... 19
12.2 Electrostatic Discharge Caution ............................ 19
12.3 Glossary ................................................................ 19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2012) to Revision G
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision E (February 2010) to Revision F
•
2
Page
Page
Added notes to pin out graphics............................................................................................................................................. 3
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions
YZT PACKAGE
(TOP VIEW)
GXU/ZXU PACKAGE
(TOP VIEW)
A
3 2 1
B C
D
C
B
A
4
3
2
1
A1
2
13
B1
A2
3
12
B2
A3
4
11
B3
A4
5
10
B4
NC
GND
6
9
7
8
NC
OE
A1
A2
A3
A4
NC
1
14
OE
VCCB
RUT PACKAGE
(TOP VIEW)
VCCA
13 B1
2
3
Exposed
Center
Pad
4
5
6
12 B2
11 B3
10 B4
9 NC
7
8
1
12
11 VCCB
A1 2
10 B1
A2 3
9 B2
A3 4
8 B3
A4 5
6
7 B4
GND
14
OE
1
GND
VCCA
VCCB
D OR PW PACKAGE
(TOP VIEW)
VCCA
RGY PACKAGE
(TOP VIEW)
A. N.C. − No internal connection
B. For RGY, if the exposed center pad is used, it must only be connected as a secondary ground or left
electrically open.
C. Pullup resistors are not required on both sides for Logic I/O.
D. If pull up or pull down resistors are needed, the resistor value must be over 50 kΩ.
E. 50 kΩ is a safe recommended value, if the customer can accept higher VOL or lower VOH, smaller pullup or
pulldown resistor is allowed, the draft estimation is VOL = VCCOUT × 4.5 k/(4.5 k + RPU) and VOH = VCCOUT ×
RDW/(4.5 k + RDW).
F. If pullup resistors are needed, please refer to the TXS0104 or contact TI.
G. For detailed information, please refer to application note SCEA043.
Pin Functions
PIN
BALL
FUNCTION
NAME
D, PW, OR
RGY NO.
RUT NO.
GXU/
ZXU NO.
YZT NO.
VCCA
1
1
B2
B2
A-port supply voltage 1.2 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB.
A1
2
2
A1
A3
Input/output 1. Referenced to VCCA.
A2
3
3
A2
B3
Input/output 2. Referenced to VCCA.
A3
4
4
A3
C3
Input/output 3. Referenced to VCCA.
A4
5
5
A4
D3
Input/output 4. Referenced to VCCA.
NC
6
–
–
–
GND
7
6
B4
D2
No connection. Not internally connected.
Ground
OE
8
12
B3
C2
3-state output-mode enable. Pull OE low to place all outputs in 3-state
mode. Referenced to VCCA.
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
3
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
Pin Functions (continued)
PIN
BALL
RUT NO.
NC
9
–
–
–
B4
10
7
C4
D1
Input/output 4. Referenced to VCCB.
B3
11
8
C3
C1
Input/output 3. Referenced to VCCB.
B2
12
9
C2
B1
Input/output 2. Referenced to VCCB.
B1
13
10
C1
A1
Input/output 1. Referenced to VCCB.
VCCB
14
11
B1
A2
B-port supply voltage 1.65 V ≤ VCCB ≤ 5.5 V.
NAME
GXU/
ZXU NO.
FUNCTION
D, PW, OR
RGY NO.
YZT NO.
No connection. Not internally connected.
Pin Assignments (GXU / ZXU Package)
A
B
C
4
A4
GND
B4
3
A3
OE
B3
2
A2
VCCA
B2
1
A1
VCCB
B1
Pin Assignments (YZT Package)
4
3
2
1
D
A4
GND
B4
C
A3
OE
B3
B
A2
VCCA
B2
A
A1
VCCB
B1
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
MIN
MAX
–0.5
4.6
–0.5
6.5
A port
Supply voltage range
UNIT
V
VI
Input voltage range
–0.5
4.6
B port
–0.5
6.5
VO
Voltage range applied to any output in the high-impedance or A port
power-off state
B port
–0.5
4.6
-0.5
6.5
VO
Voltage range applied to any output in the high or low
state (2)
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
–50
50
mA
Continuous current through VCCA, VCCB, or GND
–100
100
mA
(1)
(2)
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 Handling Ratings
Tstg
Storage temperature range
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1), A Port
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1), B Port
2.5
–15
15
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), A Port
1.5
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), B Port
1.5
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2)
VCCA
VCCA
VCCB
Supply voltage
MIN
MAX
1.2
3.6
1.65
5.5
Data inputs
1.2 V to 3.6 V
1.65 V to 5.5 V
VCCI × 0.65 (3)
VCCI
OE
1.2 V to 3.6 V
1.65 V to 5.5 V
VCCA × 0.65
5.5
Data inputs
1.2 V to 5.5 V
1.65 V to 5.5 V
0
VCCI × 0.35 (3)
OE
1.2 V to 3.6 V
1.65 V to 5.5 V
0
VCCA × 0.35
0
3.6
1.2 V to 3.6 V
1.65 V to 5.5 V
0
5.5
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Voltage range applied to any A-port
output in the high-impedance
B-port
or power-off state
(1)
(2)
(3)
VCCB
UNIT
V
V
V
V
The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND.
VCCA must be less than or equal to VCCB and must not exceed 3.6 V.
VCCI is the supply voltage associated with the input port.
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
5
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)(1)(2)
A-port inputs
Δt/Δv
TA
Input transition
rise or fall rate
B-port inputs
VCCA
VCCB
1.2 V to 3.6 V
1.65 V to 5.5 V
40
1.65 V to 3.6 V
40
4.5 V to 5.5 V
30
1.2 V to 3.6 V
MIN
Operating free-air temperature
MAX
–40
UNIT
ns/V
85
°C
6.4 Thermal Information
TXB0104
THERMAL METRIC
(1)
D
GXU/ZXU
PW
RGY
RUT
YZT
14 PINS
12 PINS
14 PINS
14 PINS
12 PINS
12 PINS
90.7
127.1
121.0
52.8
119.8
89.2
RθJC(top) Junction-to-case (top) thermal
resistance
50.5
92.8
50.0
67.7
42.6
0.9
RθJB
Junction-to-board thermal
resistance
45.4
62.2
62.8
28.9
52.5
14.4
ψJT
Junction-to-top characterization
parameter
14.7
2.3
6.4
2.6
0.7
3.0
ψJB
Junction-to-board characterization
parameter
45.1
62.2
62.2
29.0
52.3
14.4
─
─
─
─
─
─
RθJA
Junction-to-ambient thermal
resistance
RθJC(bot) Junction-to-case (bottom) thermal
resistance
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
TA = 25°C
MIN
1.2 V
VOHA
IOH = –20 μA
VOLA
IOL = 20 μA
VOHB
IOH = –20 μA
II
Ioff
IOZ
ICCA
ICCB
(1)
(2)
6
–40°C to 85°C
MAX
MIN
MAX
UNIT
1.1
V
VCCA
– 0.4
1.4 V to 3.6 V
1.2 V
0.3
1.4 V to 3.6 V
0.4
VCCB
– 0.4
1.65 V to 5.5 V
IOL = 20 μA
VOLB
TYP
V
0.4
V
1.2 V to 3.6 V
1.65 V to 5.5 V
–1
1
–2
2
μA
VI or VO = 0 to 3.6 V
0V
0 V to 5.5 V
–1
1
–2
2
B port
VI or VO = 0 to 5.5 V
0 V to 3.6 V
0V
–1
1
–2
2
A or B port
OE = GND
1.2 V to 3.6 V
1.65 V to 5.5 V
–1
1
–2
2
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
5
3.6 V
0V
2
OE
VI = VCCI or GND
A port
VI = VCCI or GND,
IO = 0
VI = VCCI or GND,
IO = 0
1.65 V to 5.5 V
V
μA
μA
0.06
0V
5.5 V
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
5
3.6 V
0V
–2
0V
5.5 V
2
μA
–2
3.4
μA
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
Electrical Characteristics(1)(2) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
TA = 25°C
MIN
ICCA + ICCB
VI = VCCI or GND,
IO = 0
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
VI = VCCI or GND,
IO = 0,
OE = GND
1.2 V
1.65 V to 5.5 V
ICCZA
1.4 V to 3.6 V
1.65 V to 5.5 V
VI = VCCI or GND,
IO = 0,
OE = GND
1.2 V
1.65 V to 5.5 V
ICCZB
1.4 V to 3.6 V
1.65 V to 5.5 V
1.2 V to 3.6 V
1.65 V to 5.5 V
Ci
Cio
OE
A port
1.2 V to 3.6 V
B port
TYP
–40°C to 85°C
MAX
MIN
MAX
3.5
10
UNIT
μA
0.05
5
μA
3.3
5
1.65 V to 5.5 V
3
4
5
6
11
14
μA
pF
pF
6.6 Timing Requirements: VCCA = 1.2 V
TA = 25°C, VCCA = 1.2 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
20
20
20
20
Mbps
50
50
50
50
ns
Data rate
tw
Pulse duration
Data inputs
UNIT
6.7 Timing Requirements: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MAX
MIN
40
Data inputs
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
40
25
VCCB = 5 V
± 0.5 V
MIN
40
25
40
25
UNIT
MAX
25
Mbps
ns
6.8 Timing Requirements: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse duration
VCCB = 2.5 V
± 0.2 V
MAX
MIN
60
Data inputs
17
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
60
VCCB = 5 V
± 0.5 V
MIN
60
17
17
UNIT
MAX
60
17
Mbps
ns
6.9 Timing Requirements: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
Pulse duration
MAX
VCCB = 3.3 V
± 0.3 V
MIN
100
Data inputs
10
MAX
VCCB = 5 V
± 0.5 V
MIN
100
10
100
10
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
UNIT
MAX
Mbps
ns
7
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
6.10 Timing Requirements: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
MIN
MAX
Data rate
tw
VCCB = 5 V
± 0.5 V
MIN
100
Pulse duration
Data inputs
UNIT
MAX
100
10
Mbps
10
ns
6.11 Switching Characteristics: VCCA = 1.2 V
TA = 25°C, VCCA = 1.2 V
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
A
B
6.9
5.7
5.3
5.5
B
A
7.4
6.4
6
5.8
A
1
1
1
1
B
1
1
1
1
A
18
15
14
14
B
20
17
16
16
A-port rise and fall times
4.2
4.2
4.2
4.2
ns
trB, tfB
B-port rise and fall times
2.1
1.5
1.2
1.1
ns
tSK(O)
Channel-to-channel skew
0.4
0.5
0.5
1.4
ns
20
20
20
20
Mbps
PARAMETER
tpd
ten
OE
tdis
OE
trA, tfA
Max data rate
UNIT
ns
μs
ns
6.12 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
B
1.4
12.9
1.2
10.1
A
0.9
14.2
0.7
12
VCCB = 5 V
± 0.5 V
UNIT
MAX
MIN
MAX
1.1
10
0.8
9.9
0.4
11.7
0.3
13.7
A
1
1
1
1
B
1
1
1
1
ns
μs
A
5.9
31
5.7
25.9
5.6
23
5.7
22.4
B
5.4
30.3
4.9
22.8
4.8
20
4.9
19.5
trA, tfA
A-port rise and fall times
1.4
5.1
1.4
5.1
1.4
5.1
1.4
5.1
ns
trB, tfB
B-port rise and fall times
0.9
4.5
0.6
3.2
0.5
2.8
0.4
2.7
ns
tSK(O)
Channel-to-channel skew
Max data rate
0.5
0.5
40
40
0.5
40
0.5
40
ns
ns
Mbps
6.13 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARAMETER
tpd
ten
8
FROM
(INPUT)
TO
(OUTPUT)
A
B
OE
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.6
11
1.4
7.7
1.3
6.8
1.2
6.5
A
1.5
12
1.3
8.4
1
7.6
0.9
7.1
A
1
1
1
1
B
1
1
1
1
Submit Documentation Feedback
ns
μs
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
Switching Characteristics: VCCA = 1.8 V ± 0.15 V (continued)
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARAMETER
tdis
FROM
(INPUT)
VCCB = 1.8 V
± 0.15 V
TO
(OUTPUT)
OE
MIN
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
VCCB = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
A
5.9
31
5.1
21.3
5
19.3
5
17.4
B
5.4
30.3
4.4
20.8
4.2
17.9
4.3
16.3
UNIT
ns
trA, tfA
A-port rise and fall times
1
4.2
1.1
4.1
1.1
4.1
1.1
4.1
ns
trB, tfB
B-port rise and fall times
0.9
3.8
0.6
3.2
0.5
2.8
0.4
2.7
ns
tSK(O)
Channel-to-channel skew
0.5
ns
0.5
Max data rate
0.5
60
0.5
60
60
60
Mbps
6.14 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
B
1.1
A
1.2
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
6.3
1
5.2
0.9
4.7
6.6
1.1
5.1
0.9
4.4
A
1
1
1
B
1
1
1
ns
μs
A
5.1
21.3
4.6
15.2
4.6
13.2
B
4.4
20.8
3.8
16
3.9
13.9
A-port rise and fall times
0.8
3
0.8
3
0.8
3
ns
trB, tfB
B-port rise and fall times
0.7
2.6
0.5
2.8
0.4
2.7
ns
tSK(O)
Channel-to-channel skew
trA, tfA
0.5
Max data rate
0.5
100
0.5
100
100
ns
ns
Mbps
6.15 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
B
0.9
4.7
0.8
4
A
1
4.9
0.9
3.8
A
1
1
B
1
1
A
4.6
15.2
4.3
12.1
B
3.8
16
3.4
13.2
ns
μs
ns
trA, tfA
A-port rise and fall times
0.7
2.5
0.7
2.5
ns
trB, tfB
B-port rise and fall times
0.5
2.1
0.4
2.7
ns
tSK(O)
Channel-to-channel skew
Max data rate
0.5
100
0.5
100
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
ns
Mbps
9
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
6.16 Operating Characteristics
TA = 25°C
VCCA
1.2 V
1.2 V
1.5 V
1.8 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
to
5V
VCCB
PARAMETER
TEST CONDITIONS
5V
CpdA
CpdB
CpdA
CpdB
10
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
B-port input, A-port output
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = VCCA
(outputs enabled)
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = GND
(outputs disabled)
1.8 V
1.8 V
1.8 V
TYP
TYP
TYP
TYP
UNIT
TYP
TYP
TYP
7.8
10
9
8
8
8
9
12
11
11
11
11
11
11
38.1
28
28
28
29
29
29
25.4
19
18
18
19
21
22
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.03
0.01
0.01
0.01
0.01
0.01
0.01
0.04
Submit Documentation Feedback
pF
pF
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
6.17 Typical Characteristics
VCCB= 3.3 V
VCCB= 3.3 V
Figure 1. Input capacitance for OE pin (CI) vs Power Supply
(VCCA)
Figure 2. Capacitance for A port I/O pins (CiO) vs Power
Supply (VCCA)
VCCA= 1.8 V
Figure 3. Capacitance for B port I/O pins (CiO) vs Power Supply (VCCB)
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
11
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
7 Parameter Measurement Information
2 × VCCO
From Output
Under Test
50 kW
From Output
Under Test
15 pF
15 pF
1 MW
Open
50 kW
TEST
tPZL/tPLZ
tPHZ/tPZH
LOAD CIRCUIT FOR
ENABLE/DISABLE
TIME MEASUREMENT
LOAD CIRCUIT FOR MAX DATA RATE,
PULSE DURATION PROPAGATION
DELAY OUTPUT RISE AND FALL TIME
MEASUREMENT
S1
S1
2 × VCCO
Open
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
tPHL
tw
Output
VCCO/2
0.9 y VCCO
0.1 y VCCO
VOH
tf
tr
VCCI
VCCO/2
VOL
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A.
B.
C.
D.
E.
F.
G.
VCCI/2
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuits and Voltage Waveforms
12
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
8 Detailed Description
8.1 Overview
The TXB0104 device is a 4-bit, directionless voltage-level translator specifically designed for translating logic
voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept
I/O voltages from 1.65 V to 5.5 V. The device is a buffered architecture with edge-rate accelerators (one-shots)
to improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open-drain
signal translation, please refer to TI’s TXS010X products.
8.2 Functional Block Diagram
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
13
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
8.3 Feature Description
8.3.1 Architecture
The TXB0104 architecture (see Figure 5) does not require a direction-control signal to control the direction of
data flow from A to B or from B to A. In a dc state, the output drivers of the TXB0104 can maintain a high or low,
but are designed to be weak, so that they can be overdriven by an external driver when data on the bus starts
flowing the opposite direction.
The output one-shots detect rising or falling edges on the A or B ports. During a rising edge, the one-shot turns
on the PMOS transistors (T1, T3) for a short duration, which speeds up the low-to-high transition. Similarly,
during a falling edge, the one-shot turns on the NMOS transistors (T2, T4) for a short duration, which speeds up
the high-to-low transition. The typical output impedance during output transition is 70 Ω at VCCO = 1.2 V to 1.8 V,
50 Ω at VCCO = 1.8 V to 3.3 V, and 40 Ω at VCCO = 3.3 V to 5 V.
VCCA
VCCB
One
Shot
T1
4k
One
Shot
T2
A
B
One
Shot
T3
4k
T4
One
Shot
Figure 5. Architecture of TXB0104 I/O Cell
8.3.2 Input Driver Requirements
Typical IIN vs VIN characteristics of the TXB0104 are shown in Figure 6. For proper operation, the device driving
the data I/Os of the TXB0104 must have drive strength of at least ±2 mA.
IIN
VT/4 kW
VIN
–(VD – VT)/4 kW
A. VT is the input threshold voltage of the TXB0104 (typically VCCI/2).
B. VD is the supply voltage of the external driver.
Figure 6. Typical IIN vs VIN Curve
14
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
Feature Description (continued)
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXB0104 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level
affects.
8.3.4 Enable and Disable
The TXB0104 has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the
high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between when OE goes low and when the
outputs acutally get disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the
one-shot circuitry to become operational after OE is taken high.
8.3.5 Pullup or Pulldown Resistors on I/O Lines
The TXB0104 is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0104 have low
dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be
kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0104.
For the same reason, the TXB0104 should not be used in applications such as I2C or 1-Wire where an opendrain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx
series of level translators.
8.4 Device Functional Modes
The TXB0104 device has two functional modes, enabled and disabled. To disable the device, set the OE input to
low, which places all I/Os in a high impedance state. Setting the OE input to high will enable the device.
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
15
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXB0104 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open-drain
signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are
recommended larger than 50 kΩ.
9.2 Typical Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. And make sure the VCCA ≤VCCB.
Table 1. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
1.2 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
- Use the supply voltage of the device that is driving the TXB0104 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value
must be less than the VIL of the input port.
• Output voltage range
- Use the supply voltage of the device that the TXB0104 device is driving to determine the output voltage
range.
- Don’t recommend to have the external pullup or pulldown resistors. If mandatory, it is recommended the
value should be larger than 50 kΩ.
• An external pulldown or pullup resistor decreases the output VOH and VOL. Use the below equations to draft
estimate the VOH and VOL as a result of an external pulldown and pullup resistor.
VOH = VCCx × RPD / (RPD + 4.5 kΩ)
VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ)
16
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
Where
• VCCx is the output port supply voltage on either VCCA or VCCB
• RPD is the value of the external pull down resistor
• RPU is the value of the external pull up resistor
• 4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line.
9.2.3 Application Curves
Figure 7. Level-Translation of a 2.5-MHz Signal
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
17
TXB0104
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
www.ti.com
10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first. The TXB0104 has circuitry that disables all
output ports when either VCC is switched off (VCCA/B = 0 V). The output-enable (OE) input circuit is designed so
that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To
ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to
GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The
minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies. And should be placed as close as possible to the VCCA,
VCCB pin and GND pin
• Short trace-lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one-shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the
source driver.
11.2 Layout Example
18
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
TXB0104
www.ti.com
SCES650G – APRIL 2006 – REVISED NOVEMBER 2014
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2006–2014, Texas Instruments Incorporated
Product Folder Links: TXB0104
19
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HPA01164RUTR
ACTIVE
UQFN
RUT
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(2KR ~ 2KV)
TXB0104D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXB0104
TXB0104DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXB0104
TXB0104DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXB0104
TXB0104DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
TXB0104
TXB0104PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YE04
TXB0104PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
YE04
TXB0104RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YE04
TXB0104RGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
YE04
TXB0104RUTR
ACTIVE
UQFN
RUT
12
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(2KR ~ 2KV)
TXB0104YZTR
ACTIVE
DSBGA
YZT
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(2K ~ 2K7)
TXB0104ZXUR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZXU
12
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
YE04
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TXB0104 :
• Automotive: TXB0104-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TXB0104DR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
D
14
2500
330.0
16.4
6.5
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.0
2.1
8.0
16.0
Q1
TXB0104PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
TXB0104RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
TXB0104RUTR
UQFN
RUT
12
3000
180.0
9.5
1.9
2.2
0.7
4.0
8.0
Q1
TXB0104YZTR
DSBGA
YZT
12
3000
180.0
8.4
1.49
1.99
0.75
4.0
8.0
Q2
TXB0104ZXUR
BGA MI
CROSTA
R JUNI
OR
ZXU
12
2500
330.0
8.4
2.3
2.8
1.0
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXB0104DR
SOIC
D
14
2500
367.0
367.0
38.0
TXB0104PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
TXB0104RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
TXB0104RUTR
UQFN
RUT
12
3000
189.0
185.0
36.0
TXB0104YZTR
DSBGA
YZT
12
3000
182.0
182.0
20.0
TXB0104ZXUR
BGA MICROSTAR
JUNIOR
ZXU
12
2500
336.6
336.6
28.6
Pack Materials-Page 2
D: Max = 1.89 mm, Min = 1.83 mm
E: Max = 1.39 mm, Min = 1.33 mm
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated