TI1 OPA830-EP Low-power, single-supply, wideband operational amplifier Datasheet

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OPA830-EP
SBOS655 – MARCH 2014
OPA830-EP Low-Power, Single-Supply, Wideband Operational Amplifier
1 Features
3 Description
•
The OPA830 is a low-power, single-supply,
wideband, voltage-feedback amplifier designed to
operate on a single +5V supply. Operation on ±5V or
+10V supplies is also supported. The input range
extends below the negative supply and to within 1.7V
of the positive supply. Using complementary
common-emitter outputs provides an output swing to
within 25mV of either supply while driving 150Ω. High
output drive current (±80mA) and low differential gain
and phase errors also make them ideal for singlesupply consumer video products.
1
•
•
•
•
•
•
•
High Bandwidth:
– 250MHz (G = +1)
– 110MHz (G = +2)
Low Supply Current:
– 3.9mA (VS = +5V)
Flexible Supply Range:
– ±1.4V to ±5.5V Dual Supply
– +2.8V to +11V Single Supply
Input Range Includes Ground On Single Supply
4.88V Output Swing on +5V Supply
High Slew Rate: 550V/μs
Low Input Voltage Noise: 9.2nV/√Hz
Pb-Free SOT23 Package
Low distortion operation is ensured by the high gain
bandwidth product (110MHz) and slew rate
(550V/μs), making the OPA830 an ideal input buffer
stage to 3V and 5V CMOS ADCs. Unlike other lowpower,
single-supply
amplifiers,
distortion
performance improves as the signal swing is
decreased. A low 9.2nV/√Hz input voltage noise
supports wide dynamic range operation.
2 Applications
•
•
•
•
•
•
Single-supply Analog-to-Digital Converter (ADC)
Input Buffers
Single-supply Video Line Drivers
CCD Imaging Channels
low-power Ultrasound
PLL Integrators
Portable Consumer Electronics
The OPA830 is available in an ultra-small SOT23-5
package.
Device Information
ORDER NUMBER
OPA830-EPDBV
PACKAGE
SOT-23 (5)
BODY SIZE
2.9 mm x 1.6 mm
xxx
xxx
xxx
xxx
DC-Coupled, +3V ADC Driver
+5V
3.75kΩ
+3V
374Ω
VIN
100Ω
THS1040
10−Bit
40MSPS
OPA830
22pF
625Ω
750Ω
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA830-EP
SBOS655 – MARCH 2014
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Terminal Configuration and Functions................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
1
1
1
2
3
3
Absolute Maximum Ratings ...................................... 3
Handling Ratings....................................................... 3
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics, VS = ±5V.......................... 4
Electrical Characteristics, VS = +5V.......................... 6
Typical Characteristics VS = ±5V .............................. 8
Typical Characteristics VS = ±5V, Differential
Configuration............................................................ 11
6.9 Typical Characteristics VS = +5V ............................ 12
6.10 Typical Characteristics VS = +5V, Differential
Configuration............................................................ 16
7
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
8
Applications and Implementation ...................... 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Input and ESD Protection ..................................... 29
10.3 Layout Example .................................................... 30
11 Device and Documentation Support ................. 32
11.1 Trademarks ........................................................... 32
11.2 Electrostatic Discharge Caution ............................ 32
11.3 Glossary ................................................................ 32
12 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
2
DATE
REVISION
NOTES
March 2014
*
Initial release
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2
Noninverting Input
3
+VS
SLM
4
Inverting Input
3
−VS
5
2
1
1
Output
4
5
5 Terminal Configuration and Functions
Terminal Orientation/Package Marking
SOT23−5
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
OUT
1
O
Amplifier Output
-VS
2
I
Negative Amplifier Power Supply Input
+IN
3
I
Non-inverting Amplifier Input
-IN
4
I
Inverting Amplifier Input
+VS
5
I
Positive Amplifier Power Supply Input
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Power Supply
Internal Power Dissipation
MAX
UNIT
12VDC
V
See Thermal Analysis
Differential Input Voltage
±2.5
Input Voltage Range (Single Supply)
–0.5
V
300
°C
150
°C
Lead Temperature (soldering, 10s)
TJ Junction Temperature
(1)
V
+VS + 0.3
These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those
indicated under Recommended Operating Conditions.
6.2 Handling Ratings
Tstg
Storage Temperature Range: D, DBV
Human Body Model (HBM) (2)
ESD
Rating (1)
Charge Device Model (CDM)
(3)
Machine Model (MM)
(1)
(2)
(3)
MIN
MAX
UNIT
–65
125
°C
2000
V
1500
V
200
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
±5
±5.5
V
5
11
V
105
°C
Dual supply voltage
Single supply voltage
TJ
Operating junction temperature
-40
6.4 Thermal Information
OPA830-EP
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
218.8
RθJCtop
Junction-to-case (top) thermal resistance
87.0
RθJB
Junction-to-board thermal resistance
45.2
ψJT
Junction-to-top characterization parameter
4.4
ψJB
Junction-to-board characterization parameter
44.4
RθJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
UNIT
DBV (5 TERMINAL)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics, VS = ±5V
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 52).
PARAMETER
CONDITIONS
OPA830TDBV
MIN
TYP
MAX
UNIT
AC PERFORMANCE (see Figure 52) (1)
G = +1, VO ≤ 0.2VPP
Small-Signal Bandwidth
310
G = +2, VO ≤ 0.2VPP, -40°C to 85°C
65
120
G = +5, VO ≤ 0.2VPP, -40°C to 85°C
15
25
G = +10, VO ≤ 0.2VPP, -40°C to 85°C
6
11
80
110
MHz
Gain-Bandwidth Product
G ≥ +10, -40°C to 85°C
Peaking at a Gain of +1
VO ≤ 0.2VPP
Slew Rate
G = +2, 2V Step, -40°C to 85°C
Rise Time
0.5V Step, -40°C to 85°C
3.3
5.9
ns
Fall Time
0.5V Step, -40°C to 85°C
3.5
6
ns
Settling Time to 0.1%
G = +2, 1V Step, -40°C to 85°C
42
66
ns
Harmonic Distortion
VO = 2VPP, f = 5MHz, -40°C to 85°C
RL = 150Ω, -40°C to 85°C
–67
−56
RL ≥ 500Ω, -40°C to 85°C
–71
−60
RL = 150Ω, -40°C to 85°C
–60
−48
RL ≥ 500Ω, -40°C to 85°C
–77
−59
Input Voltage Noise
f > 1MHz, -40°C to 85°C
9.5
11.5
nV/√Hz
Input Current Noise
f > 1MHz, -40°C to 85°C
3.7
5.7
pA/√Hz
2nd-Harmonic
3rd-Harmonic
NTSC Differential Gain
4
260
dB
600
V/μs
dBc
dBc
0.07%
NTSC Differential Phase
(1)
MHz
6
0.17
°
Limits set by simulation based on −40°C to 85°C.
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Electrical Characteristics, VS = ±5V (continued)
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 52).
PARAMETER
DC PERFORMANCE
(2)
CONDITIONS
OPA830TDBV
MIN
TYP
RL = 150Ω
Open-Loop Voltage Gain
64
Input Offset Voltage
74
±1.5
Average Offset Voltage Drift
Input Bias Current
VCM = 0V
5
Input Bias Current Drift
Input Offset Current
UNIT
MAX
VCM = 0V
±0.1
Input Offset Current Drift
dB
±8.6
mV
±35
μV/°C
13
μA
±12
nA/°C
μA
±1.49
±5
nA/°C
INPUT
Negative Input Voltage (3)
–5.5
Positive Input Voltage (3)
Common-Mode Rejection Ratio (CMRR)
Input-Referred
–5.1
V
2.8
3.2
V
72
80
dB
Input Impedance
Differential Mode
Common-Mode
10 || 2.1
kΩ || pF
400 || 1.2
kΩ || pF
OUTPUT
Output Voltage Swing
G = +2, RL = 1kΩ to GND
±4.84
±4.88
G = +2, RL = 150Ω to GND
±4.56
±4.64
±55
±85
mA
Current Output, Sinking and Sourcing
V
Short-Circuit Current
Output Shorted to Ground
150
mA
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
0.06
Ω
±1.4
V
POWER SUPPLY
Minimum Operating Voltage
Maximum Operating Voltage
Maximum Quiescent Current
VS = ±5V
Minimum Quiescent Current
VS = ±5V
Power-Supply Rejection Ratio (+PSRR)
Input-Referred
(2)
(3)
4.25
±5.5
V
5.9
mA
3.19
4.25
mA
59
66
dB
Current is considered positive out of terminal.
Tested <3dB below minimum specified CMRR at ± CMIR limits.
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6.6 Electrical Characteristics, VS = +5V
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 51).
PARAMETER
CONDITIONS
OPA830TDBV
MIN
TYP
MAX
UNIT
AC PERFORMANCE (see Figure 51) (1)
G = +1, VO ≤ 0.2VPP
Small-Signal Bandwidth
250
G = +2, VO ≤ 0.2VPP, -40°C to 85°C
68
110
G = +5, VO ≤ 0.2VPP, -40°C to 85°C
15
24
G = +10, VO ≤ 0.2VPP, -40°C to 85°C
6
11
79
110
260
550
MHz
Gain-Bandwidth Product
G ≥ +10, -40°C to 85°C
Peaking at a Gain of +1
VO ≤ 0.2VPP, -40°C to 85°C
Slew Rate
G = +2, 2V Step, -40°C to 85°C
Rise Time
0.5V Step, -40°C to 85°C
3.3
5.9
ns
Fall Time
0.5V Step, -40°C to 85°C
3.3
5.9
ns
Settling Time to 0.1%
G = +2, 1V Step, -40°C to 85°C
43
67
ns
Harmonic Distortion
VO = 2VPP, f = 5MHz
RL = 150Ω, -40°C to 85°C
–62
−53
RL ≥ 500Ω, -40°C to 85°C
–64
−56
RL = 150Ω, -40°C to 85°C
–58
−48
RL ≥ 500Ω, -40°C to 85°C
–84
−60
Input Voltage Noise
f > 1MHz, -40°C to 85°C
9.2
11.2
nV/√Hz
Input Current Noise
f > 1MHz, -40°C to 85°C
3.5
5.5
pA/√Hz
2nd-Harmonic
3rd-Harmonic
5
NTSC Differential Gain
0.09
64
Input Offset Voltage
dBc
°
72
±0.5
Average Offset Voltage Drift
VCM =2.5V
+5
Input Bias Current Drift
Input Offset Current
dBc
RL = 150Ω
Open-Loop Voltage Gain
Input Bias Current
dB
V/μs
0.08%
NTSC Differential Phase
DC PERFORMANCE (2)
MHz
VCM = 2.5V
±0.1
Input Offset Current Drift
dB
±6.7
mV
±28
μV/°C
13
μA
±12
nA/°C
±1.41
±5
μA
nA/°C
INPUT
Least Negative Input Voltage (3)
–0.5
Most Positive Input Voltage (3)
Common-Mode Rejection Ratio (CMRR)
Input-Referred
–0.2
V
2.75
3.2
V
72
80
dB
Input Impedance
Differential Mode
Common-Mode
10 || 2.1
kΩ || pF
400 || 1.2
kΩ || pF
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
G = +5, RL = 1kΩ to 2.5V
0.09
0.13
G = +5, RL = 150Ω to 2.5V
0.21
0.26
G = +5, RL = 1kΩ to 2.5V
4.87
4.91
G = +5, RL = 150Ω to 2.5V
4.72
4.78
Current Output, Sinking and Sourcing
V
±80
mA
Short-Circuit Output Current
Output Shorted to Either Supply
140
mA
Closed-Loop Output Impedance
G = +2, f ≤ 100kHz
0.06
Ω
(1)
(2)
(3)
6
±52
V
Limits set by simulation based on −40°C to 85°C.
Current is considered positive out of terminal.
Tested <3dB below minimum specified CMRR at ± CMIR limits.
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Electrical Characteristics, VS = +5V (continued)
At -40°C ≤ TJ ≤ 105°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 51).
PARAMETER
CONDITIONS
OPA830TDBV
MIN
TYP
MAX
UNIT
POWER SUPPLY
Minimum Operating Voltage
2.8
Maximum Operating Voltage
Maximum Quiescent Current
VS = ±5V
Minimum Quiescent Current
VS = ±5V
Power-Supply Rejection Ratio (+PSRR)
Input-Referred
3.9
V
11
V
5.5
mA
3.05
3.9
mA
59
66
dB
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6.7 Typical Characteristics VS = ±5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
6
3
0
0
Normalized Gain (dB)
3
Normalized Gain (dB)
G = −2
G = +1
RF = 0Ω
G = +2
−3
G = +5
−6
−9
G = +10
−12
G = −1
−3
−6
G = −5
−9
G = −10
−12
−15
−15
−18
−18
1
10
100
600
1
10
Frequency (MHz)
VO = 0.2VPP
100
400
Frequency (MHz)
RL = 150 Ω
See Figure 52
VO = 0.2VPP
Figure 1. Non-Inverting Small−Signal Frequency Response
RL = 150 Ω
Figure 2. Inverting Small−Signal Frequency Response
9
3
6
0
3
−3
VO = 2VPP
Gain (dB)
Gain (dB)
VO = 1VPP
0
VO = 1VPP
−3
VO = 4VPP
−6
VO = 0.5VPP
−6
−9
−12
VO = 4VPP
VO = 2VPP
−9
−15
VO = 0.5VPP
−12
−18
100
10
500
100
G = +2V/V
RL = 150 Ω
G = -1V/V
See Figure 52
1.5
0.2
1.0
0.1
0.5
Small−Signal ± 100mV
Left Scale
0
0
−0.1
−0.5
−0.2
−1.0
−0.3
−1.5
−0.4
−2.0
Small−Signal Output Voltage (100mV/div)
2.0
Large−Signal ± 1V
Right Scale
Large−Signal Output Voltage (500mV/div)
Small−Signal Output Voltage (100mV/div)
0.4
0.4
2.0
0.3
1.5
0.2
1.0
0.1
0.5
Small−Signal ± 100mV
Left Scale
0
−0.1
−1.0
−0.2
Large−Signal ± 1V
Right Scale
−0.3
−1.5
−2.0
−0.4
Time (10ns/div)
See Figure 52
G = -1V/V
Figure 5. Non-Inverting Pulse Response
8
0
−0.5
Time (10ns/div)
G = +2V/V
RL = 150 Ω
Figure 4. Inverting Large−Signal Frequency Response
Figure 3. Non-Inverting Large−Signal Frequency Response
0.3
400
Frequency (MHz)
Frequency (MHz)
Large−Signal Output Voltage (500mV/div)
10
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Figure 6. Inverting Pulse Response
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Typical Characteristics VS = ±5V (continued)
−50
−40
−55
−45
−50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
−60
3rd−Harmonic
−65
−70
2nd−Harmonic
−75
−55
Input Limited for VCM = 0V
−60
−65
2nd−Harmonic
−70
−75
−80
−80
3rd−Harmonic
−85
−85
100
−90
1000
2.0
2.5
3.0
Resistance (Ω )
f = 5MHz
See Figure 52
VO = 2VPP
G = +2V/V
VO = 2VPP
See Figure 52
Figure 7. Harmonic Distortion vs Load Resistance
4.0
4.5
5.0
5.5
RL = 500Ω
G = +2V/V
Figure 8. 5MHz Harmonic Distortion vs Supply Voltage
−50
−55
3rd−Harmonic
RL = 150Ω
−55
−60
−60
Harmonic Distortion (dBc)
−65
−70
−75
2nd− Harmonic
−80
3rd−Harmonic
−85
−90
−65
2nd−Harmonic
RL = 500Ω
−70
−75
−80
−85
−90
2nd−Harmonic
RL = 150Ω
3rd−Harmonic
RL = 500Ω
−95
−100
−105
−95
0.1
1
0.1
10
1
f = 5MHz
See Figure 52
RL = 500Ω
VO = 2VPP
G = +2V/V
G = +2V/V
See Figure 52
Figure 10. Harmonic Distortion vs Frequency
Figure 9. Harmonic Distortion vs Output Voltage
−40
95
6.0
90
5.5
PI
50Ω
PO
OPA830
20MHz
500Ω
−50
Output Current (50mA/div)
3rd Order Spurious Level (dBc)
−
−45
10
Frequency (MHz)
Output Voltage Swing (VPP)
750Ω
−55
750Ω
−60
10MHz
−65
−70
−75
5MHz
−80
85
80
4.5
75
4.0
Supply Current
Right Scale
50
−85
−90
−26
−20
−14
−8
−2
6
25
−50
3.5
3.0
−25
Single−Tone Load Power (2dBm/div)
Figure 11. Two−Tone, 3rd−Order Intermodulation Spurious
5.0
Source/Sink Output Current
Left Scale
Supply Current (4mA/div)
Harmonic Distortion (dBc)
3.5
Supply Voltage (±VS)
0
25
50
75
100
125
Ambient Temperature ( C)
Figure 12. Supply and Output Current vs Temperature
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Typical Characteristics VS = ±5V (continued)
8
120
CL = 10pF
7
110
CL = 100pF
6
5
100
90
CL = 1000pF
4
80
RS (Ω)
Normalized Gain to Capacitive Load (dB)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted.
3
2
1
0
50Ω
VO
OPA830
CL
−1
40
1kΩ(1)
750Ω
−2
750Ω
60
50
RS
VI
70
30
NOTE: (1) 1kΩ is optional.
20
−3
10
1
10
100
1
200
10
100
1k
Capacitive Load (pF)
Frequency (MHz)
0dB Peaking Targeted
Figure 14. Recommended RS vs Capacitive Load
6
6
5
5
4
4
3
3
2
2
1
1
VO (V)
Output Voltage (V)
Figure 13. Frequency Response vs Capacitive Load
0
−1
−2
−3
−3
−4
−4
−5
−5
10
100
1k
RL = 500Ω
RL = 50Ω
RL = 100Ω
Output
1W Internal
Current Limit
Power Limit
−6
−160
−120
Resistance (Ω )
G = +5V/V
−80
−40
0
40
80
120
160
IO (mA)
VS = ±5V
Figure 15. Output Swing vs Load Resistance
10
Output
Current Lim it
0
−1
−2
−6
1W Internal
Power Lim it
Figure 16. Output Voltage and Current Limitations
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6.8 Typical Characteristics VS = ±5V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω to GND, unless otherwise noted.
+5V
3
GD = 1
0
Normalized Gain (dB)
OPA830
−5V
RG
6 0 4Ω
6 0 4Ω
VI
RL
50 0 Ω
+5V
VO
RG
GD = 2
−3
−6
GD = 5
−9
G D = 10
−12
OPA830
−15
GD =
−5V
604Ω
RG
1
10
100
200
Frequency (MHz)
VO = 200mVPP
RL = 500Ω
Figure 18. Differential Small−Signal Frequency Response
Figure 17. Test Circuit
−45
9
−50
Harmonic Distortion (dBc)
6
VO = 5VPP
Gain (dB)
3
0
VO = 2VPP
−3
VO = 1VPP
−6
VO = 200mVPP
10
3rd−Harmonic
−60
−65
−70
−75
−80
−85
−90
2nd−Harmonic
−95
−9
1
−55
100
−100
100
200
150
GD = 2
VO = 4VPP
RL = 500Ω
250
300
350
400
450
500
GD = 2
f = 5MHz
Figure 20. Differential Distortion vs Load Resistance
Figure 19. Differential Large−Signal Frequency Response
−55
−40
−60
Harmonic Distrtion (dBc)
−50
Harmonic Distortion (dBc)
200
Resistance (Ω)
Frequency (MHz)
−60
3rd−Harmonic
−70
−80
−90
−100
−65
3rd−Harmonic
−70
−75
−80
−85
2nd−Harmonic
−90
−95
−100
2nd−Harmonic
−110
−105
0.1
1
10
100
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
GD = 2
VO = 4VPP
RL = 500Ω
Figure 21. Differential Distortion vs Frequency
GD = 2
RL = 500Ω
f = 5MHz
Figure 22. Differential Distortion vs Output Voltage
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6.9 Typical Characteristics VS = +5V
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
6
G = −2
0
Normalized Gain (dB)
3
0
G = +2
−3
G = +5
−6
−9
G = +10
−12
G = −1
−3
−6
G = −5
−9
G = −10
−12
−15
−15
−18
−18
1
10
100
500
1
10
Frequency (MHz)
VO = 0.2VPP
RL = 150Ω
See Figure 51
VO = 0.2VPP
Figure 23. Non-Inverting Small−Signal Frequency Response
3
6
0
Gain (dB)
Gain (dB)
0
VO = 0.5VPP
−3
See Figure 56
VO = 0.5VPP
VO = 1VPP
−6
−9
−12
VO = 2VPP
VO = 2VPP
−9
−15
−12
−18
10
100
500
10
100
Frequency (MHz)
G = +2V/V
RL = 150Ω
See Figure 51
G = -1V/V
4.0
2.7
3.5
2.6
3.0
Small−Signal ± 100mV
Left Scale
2.5
2.5
2.4
2.0
2.3
1.5
2.2
1.0
2.1
0.5
See Figure 56
2.9
4.5
2.8
4.0
2.7
3.5
2.6
3.0
Small−Signal ± 100mV
Left Scale
2.5
2.4
2.5
2.0
2.3
1.5
Large−Signal ± 1V
Right Scale
2.2
2.1
1.0
0.5
Time (10ns/div)
G = +2V/V
RL = 150Ω
Figure 26. Inverting Large−Signal Frequency Response
Small−Signal Output Voltage (100mV/div)
4.5
Large−Signal ± 1V
Right Scale
Large−Signal Output Voltage (500mV/div)
2.9
2.8
500
Frequency (MHz)
Figure 25. Non-Inverting Large−Signal Frequency Response
Small−Signal Output Voltage (100mV/div)
RL = 150Ω
−3
VO = 1VPP
−6
Time (10ns/div)
See Figure 51
G = -1V/V
Figure 27. Non-Inverting Pulse Response
12
400
Figure 24. Inverting Small−Signal Frequency Response
9
3
100
Frequency (MHz)
Large−Signal Output Voltage (500mV/div)
Normalized Gain (dB)
3
G = +1
RF = 0Ω
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Figure 28. Inverting Pulse Response
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Typical Characteristics VS = +5V (continued)
−50
−50
−55
−55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
−60
2nd−Harmonic
−65
−70
−75
−80
3rd−Harmonic
−85
3rd−Harmonic
R L = 150Ω
−60
2nd−Harmonic
RL = 500Ω
−65
−70
2nd−Harmonic
RL = 150Ω
−75
−80
−85
−90
−95
3rd−Harmonic
RL = 500Ω
−100
−105
−90
100
1000
0.1
1
Load Resistance (Ω )
f = 5MHz
See Figure 51
VO = 2VPP
G = +2V/V
G = +2V/V
Figure 29. Harmonic Distortion vs Load Resistance
See Figure 51
−55
−50
−60
Input Limited
−55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2VPP
Figure 30. Harmonic Distortion vs Frequency
−45
−60
−65
−70
−75
2nd−Harmonic
−80
−85
−90
2nd−Harmonic
−65
−70
−75
−80
3rd−Harmonic
−85
3rd−Harmonic
−95
−90
−100
0.1
1
1
10
10
Gain (V/V)
Output Voltage Swing (VPP)
f = 5MHz
See Figure 51
RL = 500Ω
G = +2V/V
f = 5MHz
See Figure 51
−55
RL = 500Ω
VO = 2VPP
Figure 32. Harmonic Distortion vs Non-nverting Gain
Figure 31. Harmonic Distortion vs Output Voltage
−45
PI
3rd Order Spurious Level (dBc)
−
−50
Harmonic Distortion (dBc)
10
Frequency (MHz)
−60
−55
2nd−Harmonic
50Ω
PO
OPA830
500Ω
20MHz
750Ω
−60
−65
−65
−70
750Ω
10MHz
−70
3rd−Harmonic
−75
−75
−80
5MHz
−85
−80
−90
−85
1
10
−95
−26 −24 −22 −20 −18 −16 −14 −12 −10 −8

Gain (V/V)
f = 5MHz
RL = 500Ω
−6
−4
−2
Single−Tone Load Power (dBm)
VO = 2VPP
Figure 33. Harmonic Distortion vs Inverting Gain
Figure 34. Two−Tone, 3rd−Order Intermodulation Spurious
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Typical Characteristics VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
100
Output Impedance (Ω)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
Voltage Noise
(9.2nV/√Hz)
10
Current Noise
(3.5pA/√Hz)
10
1
0.1
0.01
1
10
100
1k
10k
100k
1M
1k
10M
10k
100k
Normalized Gain to Capacitive Load (dB)
130
120
110
100
90
RS (Ω)
80
70
60
50
40
30
20
10
10
10M
100M
Figure 36. Closed−Loop Output Impedance vs Frequency
Figure 35. Input Voltage and Current Noise Density
1
1M
Frequency (Hz)
Frequency (Hz)
100
1k
8
CL = 10pF
7
6
CL = 100pF
5
CL = 1000pF
4
3
2
1
RS
VI
0
50Ω
VO
O P A830
CL
1kΩ(1)
750Ω
−1
−2
750Ω
NOTE: (1) 1kΩis optional.
−3
1
10
Capacitive Load (pF)
100
300
Frequency (MHz)
0dB Peaking Targeted
Figure 38. Frequency Response vs Capacitive Load
5.0
−20
4.5
−40
4.0
60
20 log (AOL)
50
−60
−80
40
30
−100
∠ (AOL)
20
−120
−140
10
0
−160
−10
−180
−20
100
1k
10k
100k
1M
10M
100M
−200
1G
Voltage Range (V)
0
70
Open−Loop Phase (°)
80
−
Open Loop Gain (dB)
Figure 37. Recommended RS vs Capacitive Load
Most Positive Output Voltage
3.5
Most Positive Input Voltage
3.0
2.5
2.0
1.5
1.0
Least Positive Output Voltage
0.5
0
−0.5
Least Positive Input Voltage
−1.0
−50
50
110
RL = 150Ω
RL = 150Ω
Figure 39. Open−Loop Gain and Phase
14
0
Ambient Temperature (10 C/div)
Frequency (Hz)
Figure 40. Voltage Ranges vs Temperature
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Typical Characteristics VS = +5V (continued)
At TA = 25°C, G = +2, RF = 750Ω, and RL = 150Ω to VS/2 and input VCM = 2.5V, unless otherwise noted.
4
2
10 × Input Offset Current (IOS)
0
0
−1
−2
−2
−4
Input Offset Voltage (VOS)
−3
−8
−50
−6
−8
−25
0
25
50
75
100
125
5.5
Quiescent Current
5.0
90
85
4.5
Output Current, Sinking
80
4.0
75
3.5
3.0
70
Output Current, Sourcing
Supply Current (0.5mA/div)
2
6.0
95
Output Current (5mA/div)
6
1
100
8
Input Bias Current (IB)
3
Input Bias and Offset Current (µV)
Input Offset Voltage (mV)
4
2.5
65
60
−50
2.0
−25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
RL = 150Ω
Figure 42. Supply and Output Current vs Temperature
90
5.5
80
5.0
4.5
70
CMRR
Output Voltage (V)
Common−Mode Rejection Ratio (dB)
Power−Supply Rejection Ratio (dB)
Figure 41. Typical DC Drift Over Temperature
60
50
40
30
PSRR
4.0
3.5
3.0
2.5
2.0
1.5
1.0
20
0.5
10
0
0
−0.5
1k
10k
100k
1M
10M
100M
10
100
Frequency (Hz)
1k
Load Resistance (Ω )
G = +5V/V
Figure 43. CMRR and PSRR vs Frequency
Figure 44. Output Swing vs Load Resistance
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6.10 Typical Characteristics VS = +5V, Differential Configuration
At TA = 25°C, G = +2, RF = 604Ω, and RL = 500Ω differential, unless otherwise noted.
+5V
3
GD = 1
1.2kΩ
R
0
2.5V
0.1µF
Normalized Gain (dB)
1.2kΩ
OPA830
60 4Ω
G
60 4Ω
VI
R
VO
L
+5V
R
GD = 2
−3
−6
GD = 5
−9
GD = 10
−12
G
1.2kΩ
1.2kΩ
−15
OPA830
2.5V
1
604Ω
GD =
RG
0.1µF
10
100
200
Frequency (MHz)
VO = 200mVPP
Figure 45. Test Circuit
RL = 500Ω
Figure 46. Differential Small−Signal Frequency Response
−40
9
−45
Harmonic Distortion (dBc)
6
VO = 3VPP
Gain (dB)
3
VO = 2VPP
0
−3
VO = 1VPP
−6
VO = 0.2VPP
10
3rd−Harmonic
−55
−60
−65
−70
−75
−80
2nd−Harmonic
−85
−9
1
−50
100
−90
100
200
150
GD = 2
VO = 4VPP
RL = 500Ω
300
350
400
450
500
GD = 2
f = 5MHz
−55
−30
−60
−40
3rd−Harmonic
Harmonic Distrtion (dBc)
Harmonic Distrtion (dBc)
250
Figure 48. Differential Distortion vs Load Resistance
Figure 47. Differential Large−Signal Frequency Response
−50
−60
−70
2nd−Harmonic
−80
−90
−100
−65
3rd−Harmonic
−70
−75
−80
−85
2nd−Harmonic
−90
−95
−110
−100
1
10
100
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
VO = 4VPP
GD = 2
RL = 500Ω
Figure 49. Differential Distortion vs Frequency
16
200
Resistance (Ω)
Frequency (MHz)
GD = 2
RL = 500Ω
f = 5MHz
Figure 50. Differential Distortion vs Output Voltage
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7 Detailed Description
7.1 Overview
The OPA830 is a unity-gain stable, very high-speed voltage-feedback op amp designed for single-supply
operation (+5V to +10V). The input stage supports input voltages below ground and to within 1.7V of the positive
supply. The complementary common-emitter output stage provides an output swing to within 25mV of ground
and the positive supply. The OPA830 is compensated to provide stable operation with a wide range of resistive
loads.
7.2 Functional Block Diagram
Vsupply+
Vin+
Vout
Vin-
Vsupply-
7.3 Feature Description
The OPA830 is a low-power, single-supply, wideband, voltage-feedback amplifier designed to operate on a
single +5V supply. Operation on ±5V or +10V supplies is also supported. The input range extends below the
negative supply and to within 1.7V of the positive supply. Using complementary common-emitter outputs
provides an output swing to within 25mV of either supply while driving 150Ω. High output drive current (±80mA)
and low differential gain and phase errors also make them ideal for single-supply consumer video products.
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8 Applications and Implementation
8.1 Application Information
The OPA830 is a unity-gain stable, very high-speed voltage-feedback operational amplifier designed for singlesupply operation (+5V to +10V). The input stage supports input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter output stage provides an output swing to within 25mV of
ground and the positive supply. The OPA830 is compensated to provide stable operation with a wide range of
resistive loads.
8.2 Typical Applications
8.2.1 Wideband Voltage-Feedback Operation
Figure 51 shows the AC-coupled, gain of +2 configuration used for the +5V Specifications and Typical
Characteristic Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground. Voltage
swings reported in the Electrical Characteristics are taken directly at the input and output terminals. For the
circuit of Figure 51, the total effective load on the output at high frequencies is 150Ω || 1500Ω. The 1.5kΩ
resistors at the non-inverting input provide the common-mode bias voltage. Their parallel combination equals the
DC resistance at the inverting input (RF), reducing the DC output offset due to input bias current.
VS = +5V
6.8µF
+
1.50kΩ
0.1µF
VIN
53.6Ω
0.1µF
2.5V
1.50kΩ
VOUT
OPA830
RL
150Ω
RG
750Ω
RF
750Ω
+VS/2
+VS
2
Figure 51. AC-Coupled, G = +2, +5V Single-Supply Specification and Test Circuit
Figure 52 shows the DC-coupled, gain of +2, dual power-supply circuit configuration used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to 150Ω with a series output resistor. Voltage swings reported
in the specifications are taken directly at the input and output terminals. For the circuit of Figure 52, the total
effective load will be 150Ω || 1.5kΩ. Two optional components are included in Figure 52. An additional resistor
(348Ω) is included in series with the non-inverting input. Combined with the 25Ω DC source resistance looking
back towards the signal generator, this gives an input bias current cancelling resistance that matches the 375Ω
source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the
usual power-supply decoupling capacitors to ground, a 0.01μF capacitor is included between the two powersupply terminals. In practical PC board layouts, this optional capacitor will typically improve the 2nd-harmonic
distortion performance by 3dB to 6dB.
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Typical Applications (continued)
+5V
0.1µF
6.8µF
+
50Ω Source
348Ω
VIN
VO
50Ω
150Ω
OPA830
0.01µF
RF
750Ω
RG
750Ω
+
6.8µF
0.1µF
−5V
Figure 52. DC-Coupled, G = +2, Bipolar Supply Specification and Test Circuit
8.2.1.1 Single-Supply ADC Interface
The ADC interface on the front page shows a DC-coupled, single-supply ADC driver circuit. Its large input and
output voltage ranges and low distortion support converters such as the THS1040 shown in the figure on page 1.
The input level-shifting circuitry was designed so that VIN can be between 0V and 0.5V, while delivering an
output voltage of 1V to 2V for the THS1040.
8.2.1.2 DC Level-Shifting
Figure 53 shows a DC-coupled non-inverting amplifier that level-shifts the input up to accommodate the desired
output voltage range. Given the desired signal gain (G), and the amount VOUT needs to be shifted up (ΔVOUT)
when VIN is at the center of its range, the following equations give the resistor values that produce the desired
performance. Assume that R4 is between 200Ω and 1.5kΩ.
NG = G + VOUT/VS
R1 = R4/G
R2 = R4/(NG − G)
R3 = R4/(NG −1)
(1)
(2)
(3)
(4)
Where:
NG = 1 + R4/R3
VOUT = (G)VIN + (NG − G)VS
(5)
(6)
Make sure that VIN and VOUT stay within the specified input and output voltage ranges.
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Typical Applications (continued)
+VS
R2
R1
VIN
VOUT
OPA830
R3
R4
Figure 53. DC Level-Shifting
The circuit on the front page is a good example of this type of application. It was designed to take VIN between
0V and 0.5V and produce VOUT between 1V and 2V when using a +5V supply. This means G = 2.00, and ΔVOUT
= 1.50V − G × 0.25V = 1.00V. Plugging these values into the above equations (with R4 = 750Ω) gives: NG = 2.2,
R1 = 375Ω, R2 = 3.75kΩ, and R3 = 625Ω. The resistors were changed to the nearest standard values for the front
page circuit.
8.2.1.3 AC-Coupled Output Video Line Driver
Low-power and low-cost video line drivers often buffer digital-to-analog converter (DAC) outputs with a gain of 2
into a doubly-terminated line. Those interfaces typically require a DC blocking capacitor. For a simple solution,
that interface often has used a very large value blocking capacitor (220μF) to limit tilt, or SAG, across the frames.
One approach to creating a very low high-pass pole location using much lower capacitor values is shown in
Figure 54. This circuit gives a voltage gain of 2 at the output terminal with a high-pass pole at 8Hz. Given the
150Ω load, a simple blocking capacitor approach would require a 133μF value. The two much lower valued
capacitors give this same low-pass pole using this simple SAG correction circuit of Figure 54.
+5V
1.87kΩ
Video DAC
47µF
75Ω
VO
OPA830
78.7Ω
75Ω Load
22µF
845Ω
325Ω
528Ω
650Ω
Figure 54. Video Line Driver with SAG Correction
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Typical Applications (continued)
8.2.1.4 Design Requirements
For the non-inverting amplifier with reduced peaking design, the design parameters needed in Figure 59 with
noise gain = 2 are listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
RT
20 Ω
RF
20 Ω
RC
40.2 Ω
8.2.1.5 Detailed Design Procedure
8.2.1.5.1 Demonstration Boards
Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the
OPA830 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered
with a user’s guide. The summary information for these fixtures is shown in Table 2.
Table 2. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING NUMBER
LITERATURE NUMBER
OPA830ID
SO-8
DEM-OPA-SO-1A
SBOU009
OPA830IDBV
SOT23-5
DEM-OPA-SOT-1A
SBOU010
The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the
OPA830 product folder.
+5V
100pF
1.87kΩ
0.1µF
137Ω
432Ω
VI
150pF
1.87kΩ
OPA830
4V I
1MHz, 2nd−Order
Butterworth Filter
1.5kΩ
500Ω
0.1 µF
Figure 55. Single-Supply, High-Frequency Active Filter
8.2.1.5.2 Macromodel and Applications Support
Computer simulation of circuit performance using SPICE is often a quick way to analyze the performance of the
OPA830 and its circuit designs. This is particularly true for video and RF amplifier circuits where parasitic
capacitance and inductance can play a major role on circuit performance. A SPICE model for the OPA830 is
available through the product folder on www.ti.com. The applications department is also available for design
assistance. These models predict typical small signal AC, transient steps, DC performance, and noise under a
wide variety of operating conditions. The models include the noise terms found in the electrical specifications of
the data sheet. These models do not attempt to distinguish between the package types in their small-signal AC
performance.
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8.2.1.5.3 Operating Suggestions
8.2.1.5.3.1 Optimizing Resistor Values
Since the OPA830 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used
for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise
and distortion) and parasitic capacitance considerations. For a non-inverting unity-gain follower application, the
feedback connection should be made with a direct short.
Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic
distortion performance of the OPA830. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF)
across the feedback resistor may cause unintentional band limiting in the amplifier response.
A good rule of thumb is to target the parallel combination of RF and RG (see Figure 52) to be less than about
400Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole
in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting
node, holding RF || RG < 400Ω will keep this pole above 200MHz. By itself, this constraint implies that the
feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by
RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.
In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor
and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal
to the required termination value. However, at low inverting gains, the resultant feedback resistor value can
present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching
resistor (RG) would require a 100Ω feedback resistor, which would contribute to output loading in parallel with the
external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the
input matching impedance with a third resistor to ground (see Figure 56). The total input impedance becomes the
parallel combination of RG and the additional shunt resistor.
8.2.1.5.3.2 Bandwidth vs Gain: Non-Inverting Operation
Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory,
this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing
GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth.
In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At
low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase
margin. The OPA830 is compensated to give a slightly peaked response in a non-inverting gain of 2 (see
Figure 52). This results in a typical gain of +2 bandwidth of 110MHz, far exceeding that predicted by dividing the
110MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more
closely approach the predicted value of (GBP/NG). At a gain of +10, the 11MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 110MHz.
Frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the
noise gain to 3. One way to do this, without affecting the +2 signal gain, is to add an 2.55kΩ resistor across the
two inputs, as shown in Figure 59. A similar technique may be used to reduce peaking in unity-gain (voltage
follower) applications. For example, by using a 750Ω feedback resistor along with a 750Ω resistor across the two
op amp inputs, the voltage follower response will be similar to the gain of +2 response of . Further reducing the
value of the resistor across the op amp inputs will further dampen the frequency response due to increased noise
gain. The OPA830 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared
with ±5V. This minimal reduction is because the internal bias control circuitry retains nearly constant quiescent
current as the total supply voltage between the supply terminals is changed.
8.2.1.5.3.3 Inverting Amplifier Operation
All of the familiar op amp application circuits are available with the OPA830 to the designer. See Figure 56 for a
typical inverting configuration where the I/O impedances and signal gain from Figure 51 are retained in an
inverting circuit configuration. Inverting operation is one of the more common requirements and offers several
performance benefits. It also allows the input to be biased at VS/2 without any headroom issues. The output
voltage can be independently moved to be within the output voltage range with coupling capacitors, or bias
adjustment resistors.
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+5V
0.1µF
+
6.8µF
2RT
1.5kΩ
150Ω
2RT
1.5kΩ
0.1µF
50Ω Source
0.1µF
RG
374Ω
OPA830
+VS
2
RF
750Ω
RM
57.6Ω
Figure 56. AC-Coupled, G = –2 Example Circuit
In the inverting configuration, three key design considerations must be noted. The first consideration is that the
gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired
(which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace, or other
transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the
desired gain. This is the simplest approach and results in optimum bandwidth and noise performance.
However, at low inverting gains, the resulting feedback resistor value can present a significant load to the
amplifier output. For an inverting gain of 2, setting RG to 50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This configuration has the interesting advantage of the noise gain becoming
equal to 2 for a 50Ω source impedance—the same as the non-inverting circuits considered above. The amplifier
output will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor
should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values,
as shown in Figure 56, and then achieve the input matching impedance with a third resistor (RM) to ground. The
total input impedance becomes the parallel combination of RG and RM.
The second major consideration, touched on in the previous paragraph, is that the signal source impedance
becomes part of the noise gain equation and hence influences the bandwidth. For the example in Figure 56, the
RM value combines in parallel with the external 50Ω source impedance (at high frequencies), yielding an effective
driving impedance of 50Ω || 57.6Ω = 26.8Ω. This impedance is added in series with RG for calculating the noise
gain. The resulting noise gain is 2.87 for Figure 56, as opposed to only 2 if RM could be eliminated as discussed
above. The bandwidth will therefore be lower for the gain of −2 circuit of Figure 56 (NG = +2.87) than for the gain
of +2 circuit of Figure 51.
The third important consideration in inverting amplifier design is setting the bias current cancellation resistors on
the non-inverting input (a parallel combination of RT = 750Ω). If this resistor is set equal to the total DC
resistance looking out of the inverting node, the output DC error, due to the input bias currents, will be reduced to
(Input Offset Current) times RF. With the DC blocking capacitor in series with RG, the DC source impedance
looking out of the inverting mode is simply RF = 750Ω for Figure 56. To reduce the additional high-frequency
noise introduced by this resistor and power-supply feed-through, RT is bypassed with a capacitor.
8.2.1.5.3.4 Output Current and Voltages
The OPA830 provides outstanding output voltage capability. For the +5V supply, under no-load conditions at
+25°C, the output voltage typically swings closer than 90mV to either supply rail.
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The minimum specified output voltage and current specifications over temperature are set by worst-case
simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to
the numbers shown in the ensured tables. As the output transistors deliver power, their junction temperatures will
increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains
(increasing the available output current). In steady-state operation, the available output voltage and current will
always be greater than that shown in the over-temperature specifications, since the output stage junction
temperatures will be higher than the minimum specified operating ambient.
To maintain maximum output stage linearity, no output short-circuit protection is provided. This will not normally
be a problem, since most applications include a series matching resistor at the output that will limit the internal
power dissipation if the output side of this resistor is shorted to ground. However, shorting the output terminal
directly to the adjacent positive power-supply terminal (8-terminal packages) will, in most cases, destroy the
amplifier. If additional short-circuit protection is required, consider a small series resistor in the power-supply
leads. This will reduce the available output voltage swing under heavy output loads.
8.2.1.5.3.5 Driving Capacitive Loads
One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional external capacitance which may be recommended to
improve ADC linearity. A high-speed, high open-loop gain amplifier like the OPA830 can be very susceptible to
decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output
terminal. When the primary considerations are frequency response flatness, pulse response fidelity, and/or
distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier output and the capacitive load
The Typical Characteristic curves show the recommended RS versus capacitive load and the resulting frequency
response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the
OPA830. Long PC board traces, unmatched cables, and connections to multiple devices can easily exceed this
value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the
output terminal (see the Layout Guidelines section).
The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For a gain
of +2, the frequency response at the output terminal is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will also reduce
the peaking (see Figure 59).
8.2.1.5.3.6 Distortion Performance
The OPA830 provides good distortion performance into a 150Ω load. Relative to alternative solutions, it provides
exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion
with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load includes the feedback network; in the non-inverting
configuration (see Figure 52) this is sum of RF + RG, while in the inverting configuration, only RF needs to be
included in parallel with the actual load. Running differential suppresses the 2nd-harmonic, as shown in the
differential typical characteristic curves.
8.2.1.5.3.7 Noise Performance
High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a
higher input noise voltage. The 9.2nV/√Hz input voltage noise for the OPA830 however, is much lower than
comparable amplifiers. The input-referred voltage noise and the two input-referred current noise terms
(2.8pA/√Hz) combine to give low output noise under a wide variety of operating conditions. Figure 57 shows the
op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be
noise voltage or current density terms in either nV/√Hz or pA/√Hz.
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ENI
EO
OPA830
RS
IBN
ERS
RF
√4kTRS
RG
4kT
RG
I BI
√4kTRF
4kT = 1.6E − 20J
at 290 K
Figure 57. Noise Analysis Model
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise
voltage contributors. Equation 7 shows the general form for the output noise voltage using the terms shown in
Figure 57:
EO =
(E
2
NI
)
(
+ (IBNRS ) + 4kTRS NG2 + IBIRF
2
) + 4kTRFNG
2
(7)
Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input-referred spot noise
voltage at the non-inverting input, as shown in Equation 8:
EN =
ENI2
+ (IBNRS )
2
æI R
+ 4kTRS + ç BI F
ç NG
è
2
ö
4kTRF
÷÷ +
NG
ø
(8)
Evaluating these two equations for the circuit and component values shown in Figure 51 will give a total output
spot noise voltage of 19.3nV/√Hz and a total equivalent input spot noise voltage of 9.65nV/√Hz. This is including
the noise added by the resistors. This total input-referred spot noise voltage is not much higher than the
9.2nV/√Hz specification for the op amp voltage noise alone.
8.2.1.5.4 DC Accuracy and Offset Control
The balanced input stage of a wideband voltage-feedback op amp allows good output DC accuracy in a wide
variety of applications. The power-supply current trim for the OPA830 gives even tighter control than comparable
products. Although the high-speed input stage does require relatively high input bias current (typically 5μA out of
each input terminal), the close matching between them may be used to reduce the output DC error caused by
this current. This is done by matching the DC source resistances appearing at the two inputs. Evaluating the
configuration of Figure 52 (which has matched DC input resistances), using worst-case +25°C input offset
voltage and current specifications, gives a worst-case output offset voltage equal to:
(NG = non-inverting signal gain at DC) ± (NG × VOS(MAX)) + (RF × IOS(MAX)) = ±(2 × 7mV) × (375Ω × 1μA) = ±14.38mV
(9)
A fine-scale output offset null, or DC operating point adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp circuit. Most of these techniques are based on adding a
DC current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact
on the desired signal path frequency response. If the signal path is intended to be non-inverting, the offset
control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal
path is intended to be inverting, applying the offset control to the non-inverting input may be considered. Bring
the DC offsetting current into the inverting input node through resistor values that are much larger than the signal
path resistors. This will insure that the adjustment circuit has minimal effect on the loop gain and hence the
frequency response.
8.2.1.5.5 Thermal Analysis
Maximum desired junction temperature will set the maximum allowed internal power dissipation, as described
below. In no case should the maximum junction temperature be allowed to exceed 150°C.
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Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum
of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power.
Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL
will depend on the required output signal and load; though, for resistive loads connected to mid-supply (VS/2),
PDL is at a maximum when the output is fixed at a voltage equal to VS/4 or 3VS/4. Under this condition,
PDL = VS2/(16 × RL), where RL includes feedback network loading.
Note that it is the power in the output stage, and not into the load, that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an OPA830 (SOT23-5 package) in the circuit of
Figure 51 operating at the maximum specified ambient temperature of 105°C and driving a 150Ω load at midsupply.
PD = 11V × 5.5mA + 52/(16 × (150Ω || 750Ω)) = 73mW
Maximum TJ = 105°C + (73mW × 218.8°C/W) = 120.9°C
(10)
(11)
Although this is still well below the specified maximum junction temperature, system reliability considerations may
require lower ensured junction temperatures. The highest possible internal dissipation will occur if the load
requires current to be forced into the output at high output voltages or sourced from the output at low output
voltages. This puts a high current through a large internal voltage drop in the output transistors.
8.2.1.6 Application Curve
The input is shifted slightly positive in Figure 54 using the voltage divider from the positive supply. This gives
about a 200mV input DC offset that will show up at the output terminal as a 400mV DC offset when the DAC
output is at zero current during the sync tip portion of the video signal. This acts to hold the output in its linear
operating region. This will pass on any power-supply noise to the output with a gain of approximately −20dB, so
good supply decoupling is recommended on the power-supply terminal. Figure 58 shows the frequency response
for the circuit of Figure 54. This plot shows the 8Hz low-frequency high-pass pole and a high-end cutoff at
approximately 100MHz.
3
Normalized Gain (dB)
0
−3
−6
−9
−12
−15
−18
−21
1
10
10 2
10 3
10 4
10 5
10 6
10 7
10 8
10 9
Frequency (Hz)
Figure 58. Video Line Driver Response to Matched Load
8.2.2 Non-Inverting Amplifier with Reduced Peaking
Figure 59 shows a non-inverting amplifier that reduces peaking at low gains. The resistor RC compensates the
OPA830 to have higher Noise Gain (NG), which reduces the AC response peaking (typically 5dB at G = +1
without RC) without changing the DC gain. VIN needs to be a low impedance source, such as an op amp. The
resistor values are low to reduce noise. Using both RT and RF helps minimize the impact of parasitic
impedances.
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+5V
RT
VIN
RC
RG
OPA830
VOUT
RF
Figure 59. Compensated Non-Inverting Amplifier
The Noise Gain can be calculated as follows:
R
G1 = 1 + F
RG
RT +
G2 = 1 +
(12)
R
F
G
1
RC
(13)
NG = G1 ´ G2
(14)
A unity-gain buffer can be designed by selecting RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG). This gives a
noise gain of 2, so the response will be similar to the Characteristics Plots with G = +2. Decreasing RC to 20.0Ω
will increase the noise gain to 3, which typically gives a flat frequency response, but with less bandwidth.
The circuit in Figure 51 can be redesigned to have less peaking by increasing the noise gain to 3. This is
accomplished by adding RC = 2.55kΩ across the op amp inputs.
8.2.3 Single-Supply Active Filter
The OPA830, while operating on a single +5V supply, lends itself well to high-frequency active filter designs.
Again, the key additional requirement is to establish the DC operating point of the signal near the supply midpoint
for highest dynamic range. Figure 55 shows an example design of a 1MHz low-pass Butterworth filter using the
Sallen-Key topology.
Both the input signal and the gain setting resistor are AC-coupled using 0.1μF blocking capacitors (actually giving
bandpass response with the low-frequency pole set to 32kHz for the component values shown). As discussed for
Figure 51, this allows the midpoint bias formed by the two 1.87kΩ resistors to appear at both the input and output
terminals. The midband signal gain is set to +4 (12dB) in this case. The capacitor to ground on the non-inverting
input is intentionally set larger to dominate input parasitic terms. At a gain of +4, the OPA830 on a single supply
will show 30MHz small- and large-signal bandwidth. The resistor values have been slightly adjusted to account
for this limited bandwidth in the amplifier stage. Tests of this circuit show a precise 1MHz, −3dB point with a
maximally-flat passband (above the 32kHz AC-coupling corner), and a maximum stop band attenuation of 36dB
at the amplifier’s −3dB bandwidth of 30MHz.
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9 Power Supply Recommendations
Power supply decoupling is a critical aspect with a high-frequency amplifier design process. Careful decoupling
provides higher quality ac performance (most notably improved distortion performance). The following guidelines
ensure the highest level of performance.
1. Minimize the distance (< 0.25") from the power-supply terminals to high-frequency 0.1μF decoupling
capacitors.
2. At the device terminals, the ground and power-plane layout should not be in close proximity to the signal I/O
terminals.
3. Avoid narrow power and ground traces to minimize inductance between the terminals and the decoupling
capacitors.
4. Each powersupply connection should always be decoupled with one of these capacitors. An optional supply
decoupling capacitor (0.1μF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic
distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at lower frequency, should
also be used on the main supply terminals. These may be placed somewhat farther from the device and may
be shared among several devices in the same area of the PC board.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA830 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
1. Minimize parasitic capacitance to any AC ground for all of the signal I/O terminals. Parasitic capacitance
on the output and inverting input terminals can cause instability: on the non-inverting input, it can react with
the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O terminals should be opened in all of the ground and power planes around those
terminals. Otherwise, ground and power planes should be unbroken elsewhere on the board.
2. Minimize the distance (< 0.25") from the power-supply terminals to high-frequency 0.1μF decoupling
capacitors. At the device terminals, the ground and power-plane layout should not be in close proximity to
the signal I/O terminals. Avoid narrow power and ground traces to minimize inductance between the
terminals and the decoupling capacitors. Each power-supply connection should always be decoupled with
one of these capacitors. An optional supply decoupling capacitor (0.1μF) across the two power supplies (for
bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling
capacitors, effective at lower frequency, should also be used on the main supply terminals. These may be
placed somewhat farther from the device and may be shared among several devices in the same area of the
PC board.
3. Careful selection and placement of external components will preserve the high-frequency
performance. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good highfrequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output terminal and inverting input terminal
are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if
any, as close as possible to the output terminal. Other network components, such as non-inverting input
termination resistors, should also be placed close to the package. Where double-side component mounting is
allowed, place the feedback resistor directly under the package on the other side of the board between the
output and inverting input terminals. Even with a low parasitic capacitance shunting the external resistors,
excessively high resistor values can create significant time constants that can degrade performance. Good
axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit
operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω
feedback used in the Typical Characteristics is a good starting point for design.
4. Connections to other wideband devices on the board may be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground
and power planes opened up around them. Estimate the total capacitive load and set RS from the typical
characteristic curve Recommended RS vs Capacitive Load. Low parasitic capacitive loads < 5pF) may not
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Layout Guidelines (continued)
need an RS since the OPA830 is nominally compensated to operate with a 2pF parasitic load. Higher
parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching series resistor into the trace from the output of
the OPA830 is used as well as a terminating shunt resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel combination of the shunt resistor and the input
impedance of the destination device; this total effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can
be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the typical characteristic curve Recommended RS vs Capacitive Load. This
will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination
device is low, there will be some signal attenuation due to the voltage divider formed by the series output into
the terminating impedance.
5. Socketing a high-speed part is not recommended. The additional lead length and terminal-to-terminal
capacitance introduced by the socket can create an extremely troublesome parasitic network which can
make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the OPA830 onto the board.
10.2 Input and ESD Protection
The OPA830 is built using a very high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the
Absolute Maximum Ratings table. All device terminals are protected with internal ESD protection diodes to the
power supplies, as shown in Figure 60.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 60. Internal ESD Protection
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30mA continuous current. Where higher currents are possible (that is, in systems
with ±15V supply parts driving into the OPA830), current-limiting series resistors should be added into the two
inputs. Keep these resistor values as low as possible, since high values degrade both noise performance and
frequency response.
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10.3 Layout Example
This demonstration fixture is a two-layer PCB with the power traces on the bottom layer. Even though both sides
have a ground plane, a window has been opened up around the DUT and its surrounding components. The
purpose of this window is to reduce the parasitic capacitances between sensitive nodes and the ground planes.
The footprint of the SMA connectors were designed to use straight connectors in either a vertical or horizontal
mounting position. Note that the center conductor of the SMA must be on the top side of the board when
mounted horizontally.
Decoupling Capacitors
C1, C2, C3 & C4
DUT Area, U1.
Pin1 located on top right.
+IN
‐IN
‐VS
OUT
+VS
Figure 61. Decoupling Capacitors and DUT Area
Negative Power Supply
Positive Power Supply
Non‐Inverting Input, J1
Output, J2
Inverting Input, J3
Figure 62. Power Supply, Non-Inverting, Inverting Input and Output
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Layout Example (continued)
G = 2.
R3, R4, R7, C6 not assembled.
Figure 63. Schematics Diagram
Table 3. Component Descriptions
PART
DESCRIPTION
C1, C4
2.2μF, 16V, Size 3548
C2, C3
0.1μF, 50V, Size 1206
C6
Feedback capacitor (optional); depends on application (not used on current feedback op
amps).
R1, R2, R7
Typically 50Ω
R4, R5, R6
Depends on application
JP1
Power Connector (On-Shore Technology ED555/3DS)
J1 – J4
SMA or SMB Connectors
R3
Set to get R3 ∥ R4 = desired input impedance for inverting operation
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA830TDBVREP
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 105
SLM
V62/14610-01XE
ACTIVE
SOT-23
DBV
5
3000
TBD
Call TI
Call TI
-40 to 105
SLM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
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Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
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Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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(5)
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(6)
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA830-EP :
• Catalog: OPA830
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
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