Features • Reference Oscillator up to 15 MHz • Two Programmable 16-bit Dividers Adjustable from 2 to 65535 • Fine Tuning Steps – AM ≥ 1 kHz – FM ≥ 2 kHz • Loop-push-pull Stage for AM/FM • High Signal/Noise Ratio AM/FM PLL with 1 Switch ATR4289 1. Description The ATR4289 is an integrated circuit in BiCMOS technology for frequency synthesizers. It performs all the functions of a PLL radio tuning system and is controlled by a 2-wire bus. The device is designed for all frequency synthesizer applications in radio receivers, as well as for radio data system (RDS) applications. Figure 1-1. OSCIN Block Diagram 14 Oscillator OSCOUT SCL SDA 5 Switching output R divider 15 11 FMOSC AMOSC PDAM 2 3 12 I2C bus interface AS SWO1 13 4 Current sources Phase detector 6 9 8 AM/FM switch 10 N divider 7 1 GND2 VDD PDAMO VA PDFMO PDFM 16 GND1 Rev. 4885A–AUDR–09/05 2. Pin Configuration Figure 2-1. Table 2-1. 2 Pinning SO16 VDD 1 16 GND1 SCL 2 15 OSCOUT SDA 3 14 OSCIN AS 4 13 VA SWO1 5 12 PDAMO FMOSC 6 11 PDAM GND 2 7 10 PDFMO AMOSC 8 9 PDFM Pin Description Pin Symbol Function 1 VDD Supply voltage 2 SCL Bus clock 3 SDA Bus data 4 AS Address selection 5 SWO1 Switching output 6 FMOSC FM oscillator input 7 GND2 Ground 2 (analog) 8 AMOSC AM oscillator input 9 PDFM FM current output 10 PDFMO FM analog output 11 PDAM AM current output 12 PDAMO AM analog output 13 VA 14 OSCIN 15 OSCOUT Oscillator output 16 GND1 Ground 1 (digital) Analog supply voltage Oscillator input ATR4289 4885A–AUDR–09/05 ATR4289 3. Functional Description The ATR4289 is controlled via the 2-wire bus. One module-address byte, two subaddress bytes and five data bytes enable programming. The module address contains a programmable address bit A 1, which (along with address select input AS, pin 4), enables the operation of two ATR4289 devices in one system. If bit A 1 is identical with the status of the address select input AS, the chip is selected. The subaddress determines which of the data bytes is transmitted first. If the subaddress of the R divider is transmitted, the sequence of the next data bytes is DB 0 (Status), DB 1 and DB 2. If the subaddress of the N divider is transmitted, the sequence of the next data bytes is DB 3 and DB 4. The bit organization of the module address, subaddress and 5 data bytes is shown in Table 7-1 on page 8. Each transmission on the bus begins with the START condition and has to be ended by the STOP condition (see Table 8-1 on page 8, “Transmission Protocol” ). The integrated circuit ATR4289 has two separate inputs for the AM and FM oscillators. Preamplified AM and FM signals are fed to the 16-bit R divider via the AM/FM switch. The AM/FM switch is software controlled. Tuning steps can be selected by the 16-bit R divider. Furthermore, the device provides a digital memory phase detector and two separate current sources for the AM and FM amplifier (charge pump) as given in the Table “Electrical Characteristics” on page 5. It allows independent gain adjustment, providing high current for high-speed tuning and low current for stable tuning. 3 4885A–AUDR–09/05 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Input voltage Output current Pins Symbol Value Unit 1 VDD –0.3 to +6 V 2, 3, 4, 6, 8, 14, 15 VI –0.3 to VDD + 0.3 V 3, 5 IO –1 to +5 mA Output drain voltage 5 VOD 15 V Analog supply voltage with 220Ω serial resistance 2 minutes(1) 13 VA VA 6 to 15 24 V V IAO –1 to +20 mA Ambient temperature range Tamb –30 to +85 °C Storage temperature range Tstg –40 to +125 °C Tj 125 °C ±VESD 1000 V Output current 9, 12 Junction temperature Electrostatic handling (modified MIL STD 883 D method 3015.7: all supply pins connected together) Note: 1. Corresponding to the application circuit (Figure 9-1 on page 9) 5. Thermal Resistance Parameters Junction ambient 4 Symbol Value Unit RthJA 160 K/W ATR4289 4885A–AUDR–09/05 ATR4289 6. Electrical Characteristics VDD = 5V, VA = 10V, Tamb = 25°C, unless otherwise specified Parameters Test Conditions Supply voltage Pins Symbol Min. Typ. Max. Unit 1 VDD 4.5 5.0 5.5 V 4.0 7.0 mA Quiescent supply current AM mode/FM mode 1 IDD FM input sensitivity, RG = 50Ω, FMOSC fi = 70 MHz to 120 MHz 6 VSFM 40 mVrms fi = 160 MHz 6 VSFM 150 mVrms AM input sensitivity, RG = 50Ω, AMOSC fi = 0.6 MHz to 35 MHz 8 VSAM 40 mVrms Oscillator input sensitivity, RG = 50Ω, OSCIN fi = 0.1 MHz to 15 MHz 14 VSOSC 100 mVrms Phase Detector PDFM Output current 1 10 ±IPDFM 1600 2000 2400 µA Output current 2 10 ±IPDFM 400 500 600 µA Leakage current 10 ±IPDFML 20 nA Output current 1 11 ±IPDAM 160 200 240 µA Output current 2 11 ±IPDAM 40 50 60 µA Leakage current 11 ±IPDAML 20 µA 400 mW Phase Detector PDAM Analog Output PDFMO, PDAMO 200 Saturation voltage LOW I = 15 mA 9, 12 VsatL Saturation voltage HIGH I = 15 mA 9, 12 VsatH 9.5 2, 3, 4 ViBUS 3.0 2, 3, 4 ViBUS 0 1.5 V 3 VO 0.4 V 2 fSCL 100 kHz Rise time SDA, SCL 2, 3 tr 1 µs 9.95 V Bus SCL, SDA, AS Input voltage HIGH Input voltage LOW Output voltage acknowledge LOW Clock frequency ISDA = 3 mA VDD 300 V ns Fall time SDA, SCL 2, 3 tf Period of SCL HIGH 2 tH 4.0 µs Period of SCL LOW 2 tL 4.7 µs Set-up Time Start condition tsSTA 4.7 µs Data tsDAT 250 µs tsSTOP 4.7 µs twSTA 4.7 µs Start condition thSTA 4.0 µs Data thDAT 0 µs Stop condition (1) Time space Hold Time Note: 1. This is a period of time where the bus must be free from data transmission before a new transmission can be started. 5 4885A–AUDR–09/05 Figure 6-1. FM Input Sensitivity, Tamb = +85°C 14.0 12.0 T = 85˚C VSFM (mA) 10.0 VDD = 5.5V 5.0V 4.5V 8.0 6.0 4.0 2.0 0.0 20.0 60.0 100.0 fiFM (MHz) Figure 6-2. FM Input Sensitivity, Tamb = –30°C 14.0 12.0 T = -30˚C VSFM (mA) 10.0 VDD = 5.5V 5.0V 4.5V 8.0 6.0 4.0 2.0 0.0 20.0 60.0 100.0 fiFM (MHz) Figure 6-3. AM Input Sensitivity, Tamb = +85°C 100.0 T = 85˚C fSYSCLK (kHz) VDD = 5.5V 5.0V 4.5V 10.0 1.0 0 1 10 100 VDD (V) 6 ATR4289 4885A–AUDR–09/05 ATR4289 Figure 6-4. AM Input Sensitivity, Tamb = –30°C 100.0 T = -30˚C fSYSCLK (kHz) VDD = 5.5V 5.0V 4.5V 10.0 1.0 0 1 10 100 VDD (V) Figure 6-5. Bus Timing SDA tr tf twSTA thSTA SCL P S thSTA tL thDAT tH tsSTA thDAT tsSTOP P P = Stop, S = Start 7 4885A–AUDR–09/05 7. Bit Organization Table 7-1. Bit Organization MSB Module address Subaddress (R-divider) Subaddress (N-divider) LSB 1 1 0 0 1 0 0/1 0 A7 A6 A5 A4 A3 A2 A1 A0 X X X 0 0 1 X X X X X X SWO1 Data byte 0 (Status) D7 D6 D5 1 1 X X AM/FM PD - ANA PD - POL PD - CUR D3 D2 D1 D0 D4 Data byte 1 2 15 R divider 28 Data byte 2 27 R divider 20 Data byte 3 215 N divider 28 Data byte 4 7 N divider 20 2 Table 7-2. Function Mode Bit Description Mode LOW HIGH D3 AM/FM FM operation AM operation D2 PD - ANA PD analog TEST D1 PD - POL Negative polarity Positive polarity D0 PD - CUR Output current 2 Output current 1 8. Transmission Protocol Table 8-1. Transmission Protocol MSB S Address A7 MSB LSB Address A0 8 A A0 S Note: LSB A Data 0 A Data 1 A A Data 3 A Data 4 A Data 2 A P R divider A A7 Subaddress Subaddress P N divider S = Start, P = Stop, A = Acknowledge ATR4289 4885A–AUDR–09/05 ATR4289 9. Application Figure 9-1. Application Circuit 6V to 15V 100 µF 16V 110Ω 3 kΩ 110Ω C6(1) C5(1) C1(1) FMOSC 27 pF R2(1) 27 pF R1(1) C2(1) 4 MHz 15 16 14 C3 13 12 11 10 9 6 7 8 ATR4289 100 nF 1 C4 2 3 4 100 µF 6.3V 5 1 nF 2.2 nF AMOSC 27Ω 5V 12 kΩ 12 kΩ (1) 100 nF Values depend on the step frequency and varicaps used 9 4885A–AUDR–09/05 9.1 Recommendations for Applications • C3 = 100 nF should be very close to pin 1 (VDD) and pin 16 (GND1) • GND2 (pin 7, analog ground) and GND1 (pin 16, digital ground) must be connected as shown in Figure 9-1 • 4 MHz crystal must be very close to pin 14 and pin 15 • Components of the charge pump (C1 / R1 for AM and C2 / R2 for FM) should be very close to pin 11 with respect to pin 10. Figure 9-2. PCB Layout C1 GND C4 VDD 10 C2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 C3 ATR4289 4885A–AUDR–09/05 ATR4289 10. Ordering Information Extended Type Number Package Remarks ATR4289-TBSY SO16 plastic Pb-free ATR4289-TBQY SO16 plastic Taping according to IEC-286-3, Pb-free 11. Package Information Package SO16 Dimensions in mm 5.2 4.8 10.0 9.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 8.89 16 0.2 3.8 9 technical drawings according to DIN specifications 1 8 11 4885A–AUDR–09/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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