Freescale MC711K4CFNE3 Freescale semiconductor, inc. Datasheet

68HC11M6
HC11M68HC
1M68HC11M
Freescale Semiconductor, Inc.
M68HC11K/D
M68HC11K Family
Technical Data
HCMOS
Microcontroller Unit
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MC68HC11K Family
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Technical Data
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herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
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reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
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DigitalDNA is a trademark of Motorola, Inc.
M68HC11K Family
© Motorola, Inc., 2001
Technical Data
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Revision History
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
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The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Revision History
Date
October, 2001
Revision
Level
N/A
Description
Original release
Technical Data
Page
Number(s)
N/A
M68HC11K Family
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Technical Data — M68HC11K Family
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25
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Section 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . 31
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 45
Section 4. Operating Modes
and On-Chip Memory . . . . . . . . . . . . . . . . . . . 63
Section 5. Resets and Interrupts . . . . . . . . . . . . . . . . . . 105
Section 6. Parallel Input/Output . . . . . . . . . . . . . . . . . . . 135
Section 7. Serial Communications
Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . 149
Section 8. Serial Peripheral Interface (SPI). . . . . . . . . . 167
Section 9. Timing System. . . . . . . . . . . . . . . . . . . . . . . . 181
Section 10. Analog-to-Digital (A/D) Converter . . . . . . . 221
Section 11. Memory Expansion
and Chip Selects. . . . . . . . . . . . . . . . . . . . . . 231
Section 12. Electrical Characteristics . . . . . . . . . . . . . . 253
Section 13. Mechanical Data . . . . . . . . . . . . . . . . . . . . . 273
Section 14. Ordering Information . . . . . . . . . . . . . . . . . 281
Section 15. Development Support . . . . . . . . . . . . . . . . . 283
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
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Technical Data — M68HC11K Family
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3
M68HC11K Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 2. Pin Description
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3
Power Supply (VDD, VSS, AVDD, and AVSS). . . . . . . . . . . . . . .36
2.4
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
Crystal Driver and External Clock Input (XTAL and EXTAL) . . 37
2.6
XOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.7
E-Clock Output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8
Interrupt Request (IRQ) and Non-Maskable Interrupt (XIRQ) . 38
2.9
Mode Selection, Instruction Cycle Reference,
and Standby Power (MODA/LIR and MODB/VSTBY) . . . . . .39
2.10
VRH and VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.11
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.1
Accumulators A, B, and D (ACCA, ACCB, and ACCD) . . . . 47
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.1
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.2
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.3
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.4
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.6.5
Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.6.6
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.3.6.7
Non-Maskable Interrupt (X) . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.6.8
Stop Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Technical Data
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Section 4. Operating Modes and On-Chip Memory
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
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4.5
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5.1
Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5.2
Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4.5.3
Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5.4
Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5.5
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.6.1
Control Registers and RAM . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6.2
ROM or EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.6.3
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.4
Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.7
EPROM/OTPROM (M68HC711K4 and M68HC711KS2). . . . . 90
4.7.1
Programming the EPROM with Downloaded Data. . . . . . . . 90
4.7.2
Programming the EPROM from Memory . . . . . . . . . . . . . . .91
4.8
EEPROM and the CONFIG Register . . . . . . . . . . . . . . . . . . . . 93
4.8.1
EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.8.1.1
EEPROM Programming Control Register . . . . . . . . . . . . 94
4.8.1.2
Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.1.3
System Configuration Options Register . . . . . . . . . . . . . . 97
4.8.2
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.8.2.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.8.2.2
EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.2.3
EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.2.4
EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.3
CONFIG Register Programming . . . . . . . . . . . . . . . . . . . . 100
4.8.4
RAM and EEPROM Security . . . . . . . . . . . . . . . . . . . . . . .100
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4.9
XOUT Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.9.1
System Configuration Register. . . . . . . . . . . . . . . . . . . . . . 102
4.9.2
System Configuration Options 2 Register . . . . . . . . . . . . . 103
Section 5. Resets and Interrupts
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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5.3
Sources of Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.2
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.3
Computer Operating Properly (COP) System . . . . . . . . . . 107
5.3.3.1
System Configuration Register . . . . . . . . . . . . . . . . . . . 108
5.3.3.2
System Configuration Options Register . . . . . . . . . . . . . 109
5.3.3.3
Arm/Reset COP Timer Circuitry Register. . . . . . . . . . . . 110
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.4.1
System Configuration Options Register . . . . . . . . . . . . . 111
5.3.4.2
System Configuration Options Register 2 . . . . . . . . . . . 112
5.4
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5.1
Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.1.1
Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . 120
5.5.1.2
Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.1.3
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5.2
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.6
Reset and Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.7
Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . .123
5.8
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.8.3
Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
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Section 6. Parallel Input/Output
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.8
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.9
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.10
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.11
Internal Pullup Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Section 7. Serial Communications Interface (SCI)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.3
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.4
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
7.5
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.6
Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.7
Short Mode Idle Line Detection . . . . . . . . . . . . . . . . . . . . . . .157
7.8
Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.9
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
7.9.1
SCI Baud Rate Control Register . . . . . . . . . . . . . . . . . . . . 158
7.9.2
Serial Communications Control Register 1 . . . . . . . . . . . . 160
7.9.3
Serial Communications Control Register 2 . . . . . . . . . . . . 161
7.9.4
Serial Communication Status Register 1 . . . . . . . . . . . . . . 162
7.9.5
Serial Communication Status Register 2 . . . . . . . . . . . . . . 164
7.9.6
Serial Communications Data Register . . . . . . . . . . . . . . . . 165
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Section 8. Serial Peripheral Interface (SPI)
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.3
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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8.4
SPI Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.1
Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.2
Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.3
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.4
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.4.5
SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
8.5
SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
8.5.1
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
8.5.2
Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.6
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
8.6.1
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . 174
8.6.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . 176
8.6.3
Serial Peripheral Data Register . . . . . . . . . . . . . . . . . . . . . 177
8.6.4
Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 178
8.6.5
System Configuration Options 2. . . . . . . . . . . . . . . . . . . . . 179
Section 9. Timing System
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
9.3
Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
9.4
Input Capture and Output Compare Overview . . . . . . . . . . . . 185
9.4.1
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
9.4.2
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 189
9.4.3
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 189
9.4.4
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 190
9.4.5
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 191
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Table of Contents
9.5
Input Capture (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9.5.1
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 192
9.5.2
Timer Input Capture 4/Output Compare 5 Register . . . . . . 193
9.5.3
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 194
9.5.4
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 194
9.5.5
Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Freescale Semiconductor, Inc...
9.6
Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
9.6.1
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 197
9.6.2
Timer Input Capture 4/Output Compare 5 Register . . . . . . 199
9.6.3
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 199
9.6.4
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 200
9.6.5
Timer Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 200
9.6.6
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 201
9.6.7
Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . 202
9.6.8
Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . 202
9.7
Pulse Accumulator (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.7.1
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 205
9.7.2
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 205
9.7.3
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 206
9.7.4
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 207
9.7.5
Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . .208
9.8
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.8.1
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 209
9.8.2
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 209
9.8.3
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 210
9.9
Pulse-Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . 211
9.9.1
PWM System Description. . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.9.2
Pulse-Width Modulation Control Registers. . . . . . . . . . . . . 213
9.9.2.1
Pulse-Width Modulation Timer Clock
Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
9.9.2.2
Pulse-Width Modulation Timer Polarity Register . . . . . . 215
9.9.2.3
Pulse-Width Modulation Timer Prescaler Register . . . .215
9.9.2.4
Pulse-Width Modulation Timer Enable Register . . . . . . 216
9.9.2.5
Pulse-Width Modulation Timer
Counters 1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . 217
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9.9.2.6
9.9.2.7
Pulse-Width Modulation Timer
Periods 1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . . 218
Pulse-Width Modulation Timer Duty
Cycle 1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . 219
Freescale Semiconductor, Inc...
Section 10. Analog-to-Digital (A/D) Converter
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
10.3.1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.3.2 Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
10.3.3 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.3.4 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
10.4 A/D Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 226
10.4.1 System Configuration Options Register . . . . . . . . . . . . . . . 226
10.4.2 A/D Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . 227
10.4.3 Analog-to-Digital Converter Result Registers. . . . . . . . . . . 229
10.5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.5.1 A/D Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.5.2 Operation in Stop and Wait Modes . . . . . . . . . . . . . . . . . .230
Section 11. Memory Expansion and Chip Selects
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
11.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
11.3.1 Memory Size and Address Line Allocation. . . . . . . . . . . . . 232
11.3.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
11.3.2.1
Port G Assignment Register . . . . . . . . . . . . . . . . . . . . . 234
11.3.2.2
Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .235
11.3.2.3
Memory Mapping Window Base Register . . . . . . . . . . . 236
11.3.2.4
Memory Mapping Window Control Registers. . . . . . . . .237
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11.4 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.4.1 Program Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
11.4.2 Input/Output Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . 241
11.4.3 General-Purpose Chip Selects. . . . . . . . . . . . . . . . . . . . . . 242
11.4.3.1
Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .243
11.4.3.2
General-Purpose Chip Select 1 Address Register. . . . .243
11.4.3.3
General-Purpose Chip Select 1 Control Register . . . . . 244
11.4.3.4
General-Purpose Chip Select 2 Address Register. . . . .245
11.4.3.5
General-Purpose Chip Select 2 Control Register . . . . . 245
11.4.4 One Chip Select Driving Another . . . . . . . . . . . . . . . . . . . . 246
11.4.4.1
General-Purpose Chip Select 1 Control Register . . . . . 247
11.4.4.2
General-Purpose Chip Select 2 Control Register . . . . . 247
11.4.5 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
11.5
Memory Expansion Examples . . . . . . . . . . . . . . . . . . . . . . . . 249
Section 12. Electrical Characteristics
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
12.3
Maximum Ratings for Standard Devices . . . . . . . . . . . . . . . . 254
12.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.7
Power Dissipation Characteristics . . . . . . . . . . . . . . . . . . . . . 257
12.8
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12.9
Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.10 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 265
12.11 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
12.12 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . 269
12.13 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
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Section 13. Mechanical Data
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.3
84-Pin Plastic-Leaded Chip Carrier (Case 780) . . . . . . . . . . . 275
13.4
84-Pin J-Cerquad (Case 780A) . . . . . . . . . . . . . . . . . . . . . . .276
13.5
80-Pin Quad Flat Pack (Case 841B) . . . . . . . . . . . . . . . . . . . 277
13.6
80-Pin Low-Profile Quad Flat Pack (Case 917A) . . . . . . . . . . 278
13.7
68-Pin Plastic Leaded Chip Carrier (Case 779) . . . . . . . . . . . 279
13.8
68-Pin J-Cerquad (Case 779A) . . . . . . . . . . . . . . . . . . . . . . .280
Section 14. Ordering Information
Section 15. Development Support
Index
Technical Data
16
M68HC11K Family
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Technical Data — M68HC11K Family
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
1-1
1-2
M68HC11K4 Family Block Diagram . . . . . . . . . . . . . . . . . . . . . 29
M68HC11KS Family Block Diagram. . . . . . . . . . . . . . . . . . . . . 30
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad . . . 32
Pin Assignments for M6811K 80-Pin QFP . . . . . . . . . . . . . . . . 33
Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad . . . . . 34
Pin Assignments for M6811KS 80-Pin LQFP . . . . . . . . . . . . . . 35
External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Common Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . 38
System Configuration Options 2 (OPT2) . . . . . . . . . . . . . . . . . 40
LIR Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MODB/VSTBY Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Stacking Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4-1
4-2
Register and Control Bit Assignments . . . . . . . . . . . . . . . . . . .65
Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . . . 80
M68HC11K4 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . 82
M68HC11KS2 Family Memory Map . . . . . . . . . . . . . . . . . . . . . 83
RAM and I/O Mapping Register (INIT) . . . . . . . . . . . . . . . . . . .84
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . . 88
EEPROM Mapping Register (INIT2). . . . . . . . . . . . . . . . . . . . . 89
EPROM Programming Control Register (EPROG). . . . . . . . . .91
EEPROM Programming Control Register (PPROG) . . . . . . . . 94
Block Protect Register (BPROT) . . . . . . . . . . . . . . . . . . . . . . . 96
System Configuration Options Register (OPTION) . . . . . . . . . 97
Block Protect Register (BPROT) . . . . . . . . . . . . . . . . . . . . . . 100
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
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Figure
Title
4-13
4-14
4-15
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . 101
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . 102
System Configuration Options 2 Register (OPT2) . . . . . . . . .103
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . 108
System Configuration Options Register (OPTION) . . . . . . . . 109
Arm/Reset COP Timer Circuitry Register (COPRST). . . . . . . 110
System Configuration Options Register (OPTION) . . . . . . . . 111
System Configuration Options Register 2 (OPT2) . . . . . . . . .112
System Configuration Options Register (OPTION) . . . . . . . . 121
Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO) . . . . . . . . . . . . . . . . 123
Processing Flow Out of Reset . . . . . . . . . . . . . . . . . . . . . . . . 125
Interrupt Priority Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupt Priority Resolution Within SCI System . . . . . . . . . . . 129
System Configuration Options Register (OPTION) . . . . . . . . 131
System Configuration Options 3 Register (OPT3) . . . . . . . . .132
Slow Mode Example for M68HC(7)11KS Devices Only . . . . .133
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . 138
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . 138
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . 139
Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . 139
Port C Data Register (PORTC). . . . . . . . . . . . . . . . . . . . . . . . 140
Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . 141
System Configuration Options 2 Register (OPT2) . . . . . . . . .141
Port D Data Register (PORTD). . . . . . . . . . . . . . . . . . . . . . . . 142
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . 142
Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . 143
Port F Data Register (PORTF) . . . . . . . . . . . . . . . . . . . . . . . . 144
Port F Data Direction Register (DDRF) . . . . . . . . . . . . . . . . . 144
Port G Data Register (PORTG) . . . . . . . . . . . . . . . . . . . . . . .145
Port G Data Direction Register (DDRG) . . . . . . . . . . . . . . . . . 145
Port H Data Register (PORTH). . . . . . . . . . . . . . . . . . . . . . . . 146
Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . 146
Technical Data
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List of Figures
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Title
6-17
6-18
Port Pullup Assignment Register (PPAR). . . . . . . . . . . . . . . . 147
System Configuration Register (CONFIG) . . . . . . . . . . . . . . . 147
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . .152
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 155
SCI Baud Generator Circuit Diagram . . . . . . . . . . . . . . . . . . .157
SCI Baud Rate Control Register High (SCBDH) . . . . . . . . . . 158
SCI Baud Rate Control Register Low (SCBDL) . . . . . . . . . . . 158
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . 160
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . 161
SCI Status Register 1 (SCSR1) . . . . . . . . . . . . . . . . . . . . . . .162
SCI Status Register 2 (SCSR2) . . . . . . . . . . . . . . . . . . . . . . .164
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
8-1
8-2
8-3
8-4
8-5
8-6
8-7
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Serial Peripheral Control Register (SPCR). . . . . . . . . . . . . . . 174
Serial Peripheral Status Register (SPSR) . . . . . . . . . . . . . . . 176
Serial Peripheral Data Register (SPDR). . . . . . . . . . . . . . . . . 177
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . 178
System Configuration Options 2 Register (OPT2) . . . . . . . . .179
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Timer Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Capture/Compare Block Diagram. . . . . . . . . . . . . . . . . . . . . . 187
Timer Counter Register (TCNT) . . . . . . . . . . . . . . . . . . . . . . .188
Timer Interrupt Flag 2 (TFLG2). . . . . . . . . . . . . . . . . . . . . . . . 189
Timer Interrupt Mask 2 (TMSK2) . . . . . . . . . . . . . . . . . . . . . . 189
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . 190
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . 191
Timer Input Capture Registers (TIC1–TIC3). . . . . . . . . . . . . .192
Timer Input Capture 4/Output
Compare 5 Register (TI4/O5) . . . . . . . . . . . . . . . . . . . . . . 193
Timer Interrupt Flag 1 Register (TFLG1) . . . . . . . . . . . . . . . . 194
Timer Interrupt Mask 1 Register (TMSK1) . . . . . . . . . . . . . . . 194
Timer Control 2 Register (TCTL2) . . . . . . . . . . . . . . . . . . . . . 195
9-10
9-11
9-12
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Figure
9-13
9-14
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9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
9-24
9-25
9-26
9-27
9-28
9-29
9-30
9-31
9-32
9-33
9-34
9-35
9-36
9-37
10-1
10-2
Title
Timer Output Compare
Registers (TOC1–TOC4) . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Timer Input Capture 4/Output
Compare 5 Register (TI4/O5) . . . . . . . . . . . . . . . . . . . . . . 199
Timer Interrupt Flag 1 Register (TFLG1) . . . . . . . . . . . . . . . . 199
Timer Interrupt Mask 1 Register (TMSK1) . . . . . . . . . . . . . . . 200
Timer Control Register 1 (TCTL1) . . . . . . . . . . . . . . . . . . . . . 200
Timer Compare Force Register (CFORC) . . . . . . . . . . . . . . . 201
Output Compare 1 Mask Register (OC1M) . . . . . . . . . . . . . . 202
Output Compare 1 Data Register (OC1D) . . . . . . . . . . . . . . . 202
Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . 205
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . 205
Timer Interrupt Flag 2 (TFLG2). . . . . . . . . . . . . . . . . . . . . . . . 206
Timer Interrupt Mask 2 (TMSK2) . . . . . . . . . . . . . . . . . . . . . . 207
Pulse Accumulator Count Register (PACNT) . . . . . . . . . . . . . 208
Timer Interrupt Flag 2 Register (TFLG2) . . . . . . . . . . . . . . . . 209
Timer Interrupt Mask 2 Register (TMSK2) . . . . . . . . . . . . . . . 209
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . . 210
Pulse-Width Modulation Timer Block Diagram . . . . . . . . . . . . 212
Pulse-Width Modulation Timer Clock Select (PWCLK) . . . . . 213
Pulse-Width Modulation Timer
Polarity Register (PWPOL) . . . . . . . . . . . . . . . . . . . . . . . . 215
Pulse-Width Modulation Timer
Prescaler Register (PWSCAL). . . . . . . . . . . . . . . . . . . . . . 215
Pulse-Width Modulation Timer
Enable Register (PWEN) . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Pulse-Width Modulation Timer
Counters 1 to 4 (PWCNT1 to PWCNT4) . . . . . . . . . . . . . .217
Pulse-Width Modulation Timer
Periods 1 to 4 (PWPER1 to PWPER4) . . . . . . . . . . . . . . . 218
Pulse-Width Modulation Timer
Duty Cycle 1 to 4 (PWDTY1 to PWDTY4) . . . . . . . . . . . . . 219
A/D Converter Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 222
A/D Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Technical Data
20
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M68HC11K Family
List of Figures
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List of Figures
Freescale Semiconductor, Inc...
Figure
Title
10-3
10-4
10-5
10-6
System Configuration Options Register (OPTION) . . . . . . . . 227
Analog-to-Digital Control/Status Register (ADCTL) . . . . . . . . 227
Analog-to-Digital Result Registers (ADR1–ADR4)) . . . . . . . . 229
Electrical Model of an A/D Input Pin (Sample Mode) . . . . . . . 230
11-1
11-2
11-3
11-4
Port G Assignment Register (PGAR) . . . . . . . . . . . . . . . . . . . 235
Memory Mapping Size Register (MMSIZ). . . . . . . . . . . . . . . . 235
Memory Mapping Window Base Register (MMWBR). . . . . . . 236
Memory Mapping Window Control
Registers (MM1CR and MM2CR) . . . . . . . . . . . . . . . . . . . 237
Chip-Select Control Register (CSCTL) . . . . . . . . . . . . . . . . . . 240
Chip-Select Control Register (CSCTL) . . . . . . . . . . . . . . . . . . 241
Memory Mapping Size Register (MMSIZ). . . . . . . . . . . . . . . . 243
General-Purpose Chip Select 1
Address Register (GPCS1A) . . . . . . . . . . . . . . . . . . . . . . .243
General-Purpose Chip Select 1
Control Register (GPCS1C). . . . . . . . . . . . . . . . . . . . . . . . 244
General-Purpose Chip Select 2
Address Register (GPCS2A) . . . . . . . . . . . . . . . . . . . . . . .245
General-Purpose Chip Select 2
Control Register (GPCS2C). . . . . . . . . . . . . . . . . . . . . . . . 245
General-Purpose Chip Select 1
Control Register (GPCS1C). . . . . . . . . . . . . . . . . . . . . . . . 247
General-Purpose Chip Select 2
Control Register (GPCS2C). . . . . . . . . . . . . . . . . . . . . . . . 247
Chip Select Clock Stretch Register (CSCSTR) . . . . . . . . . . . 249
Memory Expansion Example 1 — Memory Map
for a Single 8-Kbyte Window with Eight Banks
of External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Memory Expansion Example 2 Memory Map
for One 8-Kbyte Window with Eight Banks
and One 16-Kbyte Window with 16 Banks
of External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
12-1
12-2
Test Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258
Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
M68HC11K Family
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List of Figures
Figure
Freescale Semiconductor, Inc...
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
Title
POR External Reset Timing Diagram . . . . . . . . . . . . . . . . . . .260
STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 261
WAIT Recovery from Inerrupt Timing Diagram. . . . . . . . . . . . 262
Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Port Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270
Technical Data
22
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Technical Data — M68HC11K Family
List of Tables
Freescale Semiconductor, Inc...
Table
Title
1-1
M68HC11K Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2-1
2-2
I/O Ports and Peripheral Functions. . . . . . . . . . . . . . . . . . . . . . 42
Port Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3-1
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
Registers with Limited Write Access. . . . . . . . . . . . . . . . . . . . . 76
Synchronization Character Selection . . . . . . . . . . . . . . . . . . . . 79
Hardware Mode Select Summary. . . . . . . . . . . . . . . . . . . . . . . 80
Default Memory Map Addresses . . . . . . . . . . . . . . . . . . . . . . . 83
RAM Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Scope of EEPROM Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
EEPROM Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
XOUT Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Reset Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
COP Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
IRVNE Operation After Reset . . . . . . . . . . . . . . . . . . . . . . . . . 113
XOUT Clock Divide Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Interrupt and Reset Vector Assignments . . . . . . . . . . . . . . . . 118
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . .119
Highest Priority Interrupt Selection . . . . . . . . . . . . . . . . . . . . . 124
6-1
Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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Table
Title
7-1
7-2
SCI Receiver Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
SCI+ Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
8-1
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
SPI+ Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Main Timer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Timer Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Input Capture Edge Selection. . . . . . . . . . . . . . . . . . . . . . . . . 195
Timer Output Compare Actions . . . . . . . . . . . . . . . . . . . . . . .201
Pulse Accumulator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Pulse Accumulator Edge Control . . . . . . . . . . . . . . . . . . . . . . 206
Real-Time Interrupt Rate versus RTR[1:0] . . . . . . . . . . . . . . . 210
Clock A Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Clock B Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
10-1
A/D Converter Channel Selection. . . . . . . . . . . . . . . . . . . . . . 225
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
CPU Address and Address Expansion Signals . . . . . . . . . . . 233
Window Size Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Memory Expansion Window Base Address . . . . . . . . . . . . . . 236
Chip Select Control Parameter Summary. . . . . . . . . . . . . . . . 239
Program Chip Select Size. . . . . . . . . . . . . . . . . . . . . . . . . . . .240
General-Purpose Chip Select 1 Size Control . . . . . . . . . . . . . 244
General-Purpose Chip Select 2 Size Control . . . . . . . . . . . . . 246
One Chip Select Driving Another . . . . . . . . . . . . . . . . . . . . . . 248
CSCSTR Bits Versus Clock Cycles . . . . . . . . . . . . . . . . . . . . 249
14-1
M68HC11K Family Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Technical Data
24
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List of Tables
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Technical Data — M68HC11K Family
Section 1. General Description
Freescale Semiconductor, Inc...
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3
M68HC11K Family Members . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2 Introduction
The M68HC11K Family of high-performance microcontroller units
(MCUs) offers a non-multiplexed expanded bus, high speed and low
power consumption. The fully static design allows operation at
frequencies from dc to 4 MHz.
This manual contains information concerning standard and
custom-ROM (read-only memory) devices. Standard devices include
those replacing the ROM with:
•
Disabled ROM
•
Disabled EEPROM (electrically erasable, programmable
read-only memory)
•
EPROM (erasable, programmable read-only memory)
•
OTPROM (one-time progammable read-only memory)
Custom-ROM devices have a ROM array that is programmed at the
factory to customer specifications.
M68HC11K Family
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Freescale Semiconductor, Inc.
General Description
1.3 M68HC11K Family Members
M68HC11K Family devices feature up to 62 input/output (I/O) lines
distributed among eight ports, A through H. The KS Family removes
seven pins from port G and four pins from port H for a total of 51 I/O
lines. The KSx versions feature a slow mode for the clocks to allow
power conservation. Table 1-1 lists devices currently available in the
K Family along with their distinguishing features.
Freescale Semiconductor, Inc...
NOTE:
The KA2 and KA4 devices have been replaced by the pin-for-pin
compatible KS2.
Table 1-1. M68HC11K Family Devices
Device
Number
ROM
or EPROM RAM EEPROM
(Bytes) (Bytes)
(Bytes)(1)
I/O
(Pins)
Chip Slow
Select Mode
Packages
MC68HC(L)11K0
MC68HC(L)11K1
MC68HC(L)11K4
0
0
24 K
768
768
768
0
640
640
37
37
62
Yes
Yes
Yes
No
No
No
84-pin PLCC (2)
80-pin QFP(3)
MC68HC711K4
24 K
768
640
62
Yes
No
84-pin J-cerquad (4)
84-pin PLCC
80-pin QFP
MC68HC11KS2
32 K
1K
640
51
No
Yes
68-pin PLCC and 80-pin LQFP(5)
MC68HC711KS2
32 K
1K
640
51
No
Yes
68-pin J-cerquad, 68-pin PLCC,
and 80-pin LQFP
1. Where applicable, EPROM bytes appear in italics.
2. PLCC = Plastic leaded chip carrier
3. QFP = Quad flat pack
4. J-cerquad = Ceramic windowed version of PLCC
5. LQFP = Low-profile quad flat pack
Technical Data
26
M68HC11K Family
General Description
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General Description
Features
1.4 Features
Freescale Semiconductor, Inc...
M68HC11K Family features include:
•
8-bit opcodes and data
•
16-bit addressing
•
Two 8-bit accumulators, which can be concatenated to form one
16-bit accumulator
•
On-board memory:
– 24 Kbytes or 32 Kbytes of ROM, EPROM, or OTPROM
– 768 bytes or 1 Kbyte of static RAM (random-access memory)
– 640 bytes of EEPROM
– 128-byte register block
•
Dual-function I/O lines — Any pins used for the microcontroller’s
peripheral functions can be configured as general-purpose I/O
lines.
•
Non-multiplexed address and data buses
•
68HC11K4 offers:
– 1 Mbyte of address space, using on-chip memory mapping
logic
– Four programmable chip selects (expanded modes)
•
16-bit timer system:
– Three input capture (IC) channels, record event timing by
storing the value of the timing system’s 16-bit free-running
counter when an input signal transition occurs.
– Four output compare (OC) channels, provide timed outputs by
signaling when the free-running counter reaches a
predetermined number.
– One IC or OC channel (software selectable)
•
8-bit pulse accumulator
•
Four 8-bit pulse-width modulation (PWM) outputs
•
Enhanced asynchronous serial communications interface (SCI)
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General Description
•
Enhanced synchronous serial peripheral interface (SPI)
•
8-channel, 8-bit, analog-to-digital (A/D) converter
•
Computer operating properly (COP) watchdog system to guard
against infinite loops and other system problems
•
Real-time interrupt timer
•
Power-saving modes:
Freescale Semiconductor, Inc...
– Slow mode reduces power consumption by slowing down
internal operations.
– Wait mode shuts down various system features selected by
the user with power consumption typically dropping to
10–100 mW.
– Stop mode also shuts down system clocks, typically reducing
power consumption to about 1.5 mW.
•
Package availability for ROM devices:
– K versions:
84-pin plastic leaded chip carrier (PLCC)
80-pin quad flat pack (QFP)
– KS versions:
68-pin plastic leaded chip carrier (PLCC)
80-pin low-profile quad flat pack (LQFP)
•
Package availability for EPROM devices:
– K versions:
80-pin quad flat pack (QFP)
84-pin J-cerquad (ceramic windowed version of PLCC)
84-pin plastic leaded chip carrier (PLCC)
– KS versions:
68-pin J-cerquad (ceramic windowed version of PLCC)
80-pin low-profile quad flat pack (LQFP)
68-pin plastic leaded chip carrier (PLCC)
Technical Data
28
M68HC11K Family
General Description
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General Description
Structure
1.5 Structure
Figure 1-1 is a block diagram of the M68HC11K Family MCU.
Figure 1-2 is a block diagram of the M68HC11KS devices.
PA6
PA5
PA4
PA3
PA2
PA1
PA0
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC1
IC2
IC3
DDRA
PAI/OC1
PORT A
PA7
OSCILLATOR
E
XOUT(1) VRH
VRL
CLOCK LOGIC
A/D
CONVERTER
PULSE ACCUMULATOR
TIMER
SYSTEM
SPI
SS
SCK
MOSI
MISO
SCI
TxD
RxD
COP
PERIODIC INTERRUPT
24 KBYTES ROM/EPROM
AVDD
AVSS
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PORT E
MODE
CONTROL
XTAL
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PD5
PD4
PD3
PD2
PORT D
INTERRUPT
LOGIC
EXTAL
DDRD
XIRQ/VPP
(2)
PD1
PD0
768 BYTES RAM
640 BYTES EEPROM
VDD
EXPANSION
SELECTS
CSPROG
CSGP2
CSGP1
CSIO
PWMs
DDRH
PORT B
PORT F
PORT C
PORT G
PORT H
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PW4
PW3
PW2
PW1
DDRG
PH3
PH2
PH1
PH0
DDRC
PH7
PH6
PH5
PH4
DDRF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
DDRB
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
CHIP
R/W
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA BUS
ADDRESS BUS
MEMORY
XA18
XA17
XA16
XA15
XA14
XA13
CPU
VSS
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Freescale Semiconductor, Inc...
IRQ
MODB/
VSTBY
MODA/
LIR
RESET
Notes:
1. XOUT pin omitted on 80-pin QFP
2. VPP applies only to EPROM devices.
Figure 1-1. M68HC11K4 Family Block Diagram
M68HC11K Family
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General Description
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC1
IC2
IC3
XOUT
VRH
VRL
CLOCK LOGIC
A/D
CONVERTER
PULSE ACCUMULATOR
TIMER
SYSTEM
SPI
SS
SCK
MOSI
MISO
SCI
TxD
RxD
COP
PERIODIC INTERRUPT
MC68HC11KS2
32 KBYTES ROM/EPROM
AVDD
MC68HC11KS2
1 KBYTES RAM
AVSS
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORT E
PA6
PA5
PA4
PA3
PA2
PA1
PA0
DDRA
PAI/OC1
OSCILLATOR
WITH SLOW MODE
E
PD5
PD4
PD3
PD2
PORT D
MODE
CONTROL
PA7
PORT A
Freescale Semiconductor, Inc...
XIRQ/VPP(2)
INTERRUPT
LOGIC
XTAL
DDRD
IRQ
MODB/
VSTBY EXTAL
MODA/
LIR
RESET
PD1
PD0
VDD
CPU
VSS
640 BYTES EEPROM
DATA BUS
DDRG
DDRH
PORT B
PORT F
PORT C
PORT G
PORT H
PH3
PH2
PH1
PH0
PG7
PW4
PW3
PW2
PW1
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DDRC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
DDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
R/W
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDRESS BUS
PWMs
Notes:
1. The configuration shown in this diagram is the MC68HC11KS2.
2. VPP applies only to EPROM devices.
Figure 1-2. M68HC11KS Family Block Diagram
Technical Data
30
M68HC11K Family
General Description
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Technical Data — M68HC11K Family
Section 2. Pin Description
Freescale Semiconductor, Inc...
2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3
Power Supply (VDD, VSS, AVDD, and AVSS). . . . . . . . . . . . . . .36
2.4
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
Crystal Driver and External Clock Input
(XTAL and EXTAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.6
XOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.7
E-Clock Output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8
Interrupt Request (IRQ) and Non-Maskable
Interrupt (XIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.9
Mode Selection, Instruction Cycle Reference,
and Standby Power (MODA/LIR and MODB/VSTBY) . . . . . .39
2.10
VRH and VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.11
Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2 Introduction
The M68HC11K Family is available in a variety of packages, as shown
in Table 1-1. M68HC11K Family Devices. Most pins on this MCU serve
two or more functions, as described in this section. Pin assignments for
the various package types are shown in Figure 2-1, Figure 2-2,
Figure 2-3, and Figure 2-4.
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
For More Information On This Product,
Go to: www.freescale.com
31
Freescale Semiconductor, Inc.
PD5/SS
PD3/MOSI
75
PA7/PAI/OC1
78
PD4/SCK
PA6/OC2/OC1
79
76
PA5/OC3/OC1
80
77
PA3/IC4/OC5/OC1
PA4/OC4/OC1
81
PA2/IC1
82
PA1/IC2
83
PA0/IC3
84
VSS
VDD
2
1
PB7/ADDR15
4
3
PB4/ADDR12
7
PB5/ADDR13
PB3/ADDR11
8
PB6/ADDR14
PB2/ADDR10
9
5
PB1ADDR9
10
6
PB0/ADDR8
11
PH0/PW1
12
PH1/PW2
13
73
PD1/TXD
PH2/PW3
14
72
PD0/RXD
PH3/PW4
15
71
MODA/LIR
PH4/CSIO
16
70
MODB/VSTBY
PH5/CSGP1
17
69
RESET
PH6/CSGP2
18
68
XTAL
PH7/CSPROG
19
67
EXTAL
TEST16(1)
20
66
XOUT
XIRQ/VPP(2)
21
65
E
TEST15(1)
VDD
22
64
VDD
23
63
VSS
VSS
24
62
PC7/DATA7
TEST14(1)
25
61
PC6/DATA6
PG7/R/W
26
60
PC5/DATA5
PG6
27
59
PC4/DATA4
PG5/XA18
28
58
PC3/DATA3
PG4/XA17
29
57
PC2/DATA2
PG3/XA16
30
56
PC1/DATA1
PG2/XA15
31
55
PC0/DATA0
PG1/XA14
32
54
IRQ
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
AVDD
PE7/AN7
PE6/AN6
PE5/AN5
PE4/AN4
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
VRL
VRH
AVSS
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
PF0/ADDR0
74
PG0/XA13
Freescale Semiconductor, Inc...
Pin Description
PD2/MISO
Notes:
1. Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry.
2. VPP applies only to EPROM devices.
Figure 2-1. Pin Assignments for M68HC11K 84-Pin PLCC/J-Cerquad
Technical Data
32
M68HC11K Family
Pin Description
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
PC0/DATA0
IRQ
69
68
67
66
65
64
63
62
61
E
72
VDD
EXTAL
73
VSS
XTAL
74
70
RESET
75
71
MODA/LIR
MODB/VSTBY
PD0/RXD
76
PD1/TXD
78
77
PD2/MISO
79
1
60
PF0/ADDR0
PD4/SCK
2
59
PF1/ADDR1
PD5/SS
3
58
PF2/ADDR2
PA7/PAI/OC1
4
57
PF3/ADDR3
PA6/OC2/OC1
5
56
PF4/ADDR4
PA5/OC3/OC1
6
55
PF5/ADDR5
PA4/OC4/OC1
7
54
PF6/ADDR6
PA3/IC4/OC5/OC1
8
53
PF7/ADDR7
PA2/IC1
9
52
AVSS
PA1/IC2
10
51
VRH
PA0/IC3
11
50
VRL
VDD
12
49
PE0/AN0
VSS
13
48
PE1/AN1
PB7/ADDR15
14
47
PE2/AN2
PB6/ADDR14
15
46
PE3/AN3
PB5/ADDR13
16
45
PE4/AN4
PB4/ADDR12
17
44
PE5/AN5
PB3/ADDR11
18
43
PE6/AN6
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PH2/PW3
PH3/PW4
PH4/CSIO
PH5/CSGP1
PH6/CSGP2
PH7/CSPROG
XIRQ/VPP*
VDD
VSS
PG7/R/W
PG6
PG5/XA18
PG4/XA17
PG3/XA16
PG2/XA15
PG1/XA14
PG0/XA13
AVDD
PH1/PW2
PE7/AN7
41
22
42
20
PH0/PW1
19
PB1/ADDR9
21
PB2/ADDR10
PB0/ADDR8
Freescale Semiconductor, Inc...
PD3/MOSI
80
Pin Description
Introduction
* VPP applies only to EPROM devices.
Figure 2-2. Pin Assignments for M6811K 80-Pin QFP
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
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33
Freescale Semiconductor, Inc.
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TXD
PD0/RXD
65
64
63
62
61
PA7/PAI/OC1
2
66
PA6/OC2/OC1
3
VSS
PA5/OC3/OC1
4
67
PA4/OC4/OC1
5
VDD
PA3/IC4/OC5/OC1
6
VDD
PA2/IC1
7
68
PA1/IC2
8
1
PA0/IC3
9
PB7/ADDR15
10
60
MODA/LIR
PB6/ADDR14
11
59
MODB/VSTBY
PB5/ADDR13
12
58
RESET
PB4/ADDR12
13
57
XTAL
PB3/ADDR11
14
56
EXTAL
PB2/ADDR10
15
55
XOUT
PB1/ADDR9
16
54
E
PB0/ADDR8
17
53
PC7/DATA7
PH0/PW1
PH1/PW2
18
52
PC6/DATA6
19
51
PC5/DATA5
PH2/PW3
35
36
37
38
39
40
41
42
43
VRH
PF7/ADDR7
PF6/ADDR6
PF5/ADDR5
PF4/ADDR4
PF3/ADDR3
PF2/ADDR2
PF1/ADDR1
AVSS
VSS
44
34
26
33
PF0/ADDR0
PE7/AN7
VRL
45
PE0/AN0
25
32
PC0/DATA0
AVDD
PE1/AN1
PC1/DATA1
46
31
47
24
30
23
IRQ
PE2/AN2
PC2/DATA2
PG7/R/W
PE3/AN3
48
29
22
PE4/AN4
PC3/DATA3
XIRQ/VPP*
28
PC4/DATA4
49
27
50
21
PE5/AN5
20
PH3/PW4
PE6/AN6
Freescale Semiconductor, Inc...
Pin Description
* VPP applies only to EPROM devices.
Figure 2-3. Pin Assignments for M6811KS 68-Pin PLCC/J-Cerquad
Technical Data
34
M68HC11K Family
Pin Description
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
NC
NC
MODA/LIR
MODB/VSTBY
RESET
XTAL
EXTAL
XOUT
E
NC
PC7/DATA7
PC6/DATA6
PC5/DATA5
PC4/DATA4
PC3/DATA3
PC2/DATA2
PC1/DATA1
PC0/DATA0
PF0/ADDR0
PF1/ADDR1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD0/RXD
1
60
PF2/ADDR2
PD1/TXD
2
59
PF3/ADDR3
PD2/MISO
3
58
PF4/ADDR4
PD3/MOSI
4
57
PF5/ADDR5
PD4/SCK
5
56
PF6/ADDR6
PD5/SS
6
55
PF7/ADDR7
39
40
NC
NC
38
41
AVDD
20
PE7/AN7
PE6/AN6
PA0/IC3
37
42
IRQ
PE5/AN5
19
36
43
PA1/IC2
PG7/R/W
PA2/IC1
35
PE4/AN4
18
NC
44
34
17
NC
PE3/AN3
PA3/IC4/OC5/OC1
33
45
XIRQ/VPP*
PE2/AN2
16
32
46
PA4/OC4/OC1
PH3/PW4
PA5/OC3/OC1
31
PE1/AN1
15
30
47
PH2/PW3
14
PH1/PW2
PE0/AN0
PA6/OC2/OC1
29
NC
48
PH0/PW1
49
13
28
VDD
PA7/PAI/OC1
PB0/ADDR8
VRL
27
50
12
PB1/ADDR9
11
26
NC
PB2/ADDR10
NC
25
VRH
51
PB3/ADDR11
52
24
9
10
PB4/ADDR12
NC
VDD
23
AVSS
PB5/ADDR13
VSS
53
22
54
8
PB6/ADDR14
7
21
NC
VSS
PB7/ADDR15
Freescale Semiconductor, Inc...
Pin Description
Introduction
* VPP applies only to EPROM devices.
Figure 2-4. Pin Assignments for M6811KS 80-Pin LQFP
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
For More Information On This Product,
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35
Freescale Semiconductor, Inc.
Pin Description
2.3 Power Supply (VDD, VSS, AVDD, and AVSS)
Freescale Semiconductor, Inc...
The MCU operates from a single 5-volt (nominal) power supply. VDD is
the positive power input and VSS is ground. There are three VDD/VSS
pairs of pins on the K series devices and two sets on the KS devices. All
devices contain a separate pair of power inputs, AVDD and AVSS, for the
analog-to-digital (A/D) converter, so that the A/D circuitry can be
bypassed independently.
Very fast signal transitions occur on the MCU pins. The short rise and fall
times place high, short duration current demands on the power supply.
To prevent noise problems, provide good power supply bypassing at the
MCU. Also, use bypass capacitors that have good high-frequency
characteristics and situate them as close to the MCU as possible.
Bypass requirements vary, depending on how heavily the MCU pins are
loaded.
2.4 Reset (RESET)
This active-low, bidirectional control signal acts as an input to initialize
the MCU to a known start-up state. It also serves as an open-drain
output to indicate that an internal failure has been detected in either the
clock monitor or computer operating properly (COP) watchdog circuit.
The CPU distinguishes between internal and external reset conditions
by counting the number of E-clock cycles that occur between the start of
reset and the presence of a logic 1 voltage level on the reset pin. Less
than two cycles indicates an internal reset; greater than two, an external
reset. To prevent the device from misinterpreting the kind of reset that
occurs, do not connect an external resistor-capacitor (RC) power-up
delay circuit directly to the reset pin.
Technical Data
36
M68HC11K Family
Pin Description
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Pin Description
Crystal Driver and External Clock Input (XTAL and EXTAL)
VDD
VDD
VDD
IN
MC34064
MANUAL
RESET SWITCH
4.7 kΩ
4.7 kΩ
RESET
TO RESET
OF M68HC11
GND
4.7 kΩ
1.0 µΩ
Freescale Semiconductor, Inc...
IN
MC34164
RESET
GND
OPTIONAL POWER-ON DELAY AND MANUAL RESET SWITCH
Figure 2-5. External Reset Circuit
It is important to protect the MCU against corruption of RAM and
EEPROM during power transitions. This can be done with a low-voltage
interrupt (LVI) circuit which holds the RESET pin low when VDD drops
below the minimum operating level. Figure 2-5 shows a suggested reset
circuit that incorporates two LVI devices and an external switch.
2.5 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a
CMOS-compatible clock to control the internal clock generator circuitry.
The frequency applied to these pins is four times higher than the desired
E-clock rate.
When an external CMOS-compatible clock input is connected to the
EXTAL pin, the XTAL pin must be left unterminated.
CAUTION:
In all cases, use caution around the oscillator pins.
Load capacitances shown in Figure 2-6 are specified by the crystal
manufacturer and should include all stray layout capacitances.
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
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37
Freescale Semiconductor, Inc.
Pin Description
CL *
EXTAL
MCU
10 MΩ
4xE
CRYSTAL
CL *
XTAL
* This value includes all stray capacitances.
Freescale Semiconductor, Inc...
Figure 2-6. Common Crystal Connections
2.6 XOUT
The XOUT pin provides a buffered clock signal if enabled to synchronize
external devices with the MCU. See 4.9 XOUT Pin Control.
NOTE:
This signal is not present on the 80-pin M68HC(7)11K device QFP
package.
2.7 E-Clock Output (E)
The internally generated instruction cycle clock, or E clock, is available
on the E pin as a timing reference. Its frequency is one fourth the input
frequency at the XTAL and EXTAL pins. The E clock is low during the
address portion of a bus cycle and high during the data access portion
of the bus cycle. All clocks, including the E clock, are halted when the
MCU is in stop mode. The E-pin driver can be turned off in single-chip
modes to reduce radio frequency interference (RFI) and current
consumption.
2.8 Interrupt Request (IRQ) and Non-Maskable Interrupt (XIRQ)
The MCU provides two pins for applying asynchronous interrupt
requests. Interrupts applied to the IRQ pin can be masked by setting the
I bit in the condition code register (CCR), which can be set or cleared by
software at any time. Triggering is level sensitive by default, which is
Technical Data
38
M68HC11K Family
Pin Description
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Pin Description
Mode Selection, Instruction Cycle Reference, and Standby Power (MODA/LIR and MODB/VSTBY)
required for wire-OR configuration. Software can change the triggering
to edge sensitive.
Freescale Semiconductor, Inc...
XIRQ interrupts can be non-maskable after reset initialization. Out of
reset, the X bit in the CCR is set, masking XIRQ interrupts. Once
software clears the X bit, it cannot be reset, and the XIRQ interrupts
become non-maskable. The XIRQ input is level sensitive only. XIRQ is
often used as a power-loss detect interrupt.
Whenever IRQ or XIRQ is used with multiple interrupt sources, each
source must drive the interrupt input with an open-drain type of driver to
avoid contention between outputs. There should be a single pullup
resistor near the MCU interrupt pin (typically 4.7 kΩ). There must also be
an interlock mechanism at each interrupt source which holds the
interrupt line low until the MCU recognizes and acknowledges the
interrupt request. If any interrupt sources are still pending after the MCU
services a request, the interrupt line will remain low, interrupting the
MCU again as soon as the I bit in the MCU is cleared (normally upon
return from an interrupt). Interrupt mechanisms are explained further in
Section 5. Resets and Interrupts.
On EPROM devices, the XIRQ pin also functions as the high-voltage
supply, VPP, during EPROM or OTPROM programming.
CAUTION:
Ensure that the voltage level at this pin is equal to VDD during normal
operation to avoid programming accidents.
2.9 Mode Selection, Instruction Cycle Reference, and Standby Power
(MODA/LIR and MODB/VSTBY)
During reset, MODA and MODB select one of four operating modes:
1. Single-chip
2. Expanded
3. Bootstrap
4. Special test
For full descriptions of these modes, refer to 4.5 Operating Modes.
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
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39
Freescale Semiconductor, Inc.
Pin Description
In single-chip and bootstrap modes, the MODA pin typically is grounded
and has no function after reset. In expanded and special test modes,
MODA is normally connected to VDD through a 4.7-kΩ pullup resistor
and functions as the load instruction register (LIR) pin after reset. The
open-drain, active-low LIR output drives low during the first E-clock cycle
of each instruction (opcode fetch), providing a useful signal for system
debugging.
Freescale Semiconductor, Inc...
LIR can be driven high for a portion of each instruction cycle by setting
the LIRDV bit in the system configuration options 2 (OPT2) register (see
Figure 2-7 and Figure 2-8). This feature can help detect consecutive
instructions and prevent false triggering in high-speed applications.
Address: $0038
Read:
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
STRCH(1)
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
Write:
Reset:
1. STRCH is not available on K devices.
Figure 2-7. System Configuration Options 2 (OPT2)
LIRDV — LIR Driven Bit
0 = LIR not driven high
1 = LIR driven high for one quarter cycle to reduce transition time
LAST CYCLE OF
PREVIOUS INSTRUCTION
FIRST CYCLE OF NEW
INSTRUCTION
E
LIR
OPCODE FETCH
Note: If LIRDV is not set, the pullup resistor may
not return the level to a logic 1 before
the next data fetch.
Figure 2-8. LIR Timing
Technical Data
40
M68HC11K Family
Pin Description
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Pin Description
VRH and VRL
The MODB pin is grounded to select special modes, and has no function
after reset. To select the normal operating modes (single-chip and
expanded) the MODB pin is pulled to a logic high level. Connecting
MODB to a voltage source other than VDD enables it to function as a
battery backup input, VSTBY. When VDD drops more than one MOS
threshold (about 0.7 volts) below the voltage at VSTBY, the MCU’s RAM
and part of the reset logic are powered from VSTBY rather than VDD.
Reset must be driven low before VDD is removed and must remain low
until VDD has been restored to a valid level. The extra hardware required
to utilize VSTBY may be justified in certain applications where a
significant amount of external circuitry operates from VDD. Figure 2-9
shows a suggested circuit employing the VSTBY pin.
VDD
MAX
690
VDD
4.7 K
V Out
4.8 V
NICD
TO MODB/ V STBY
OF M68HC11
VBATT
+
Figure 2-9. MODB/VSTBY Connection
2.10 VRH and VRL
These pins provide the reference voltage for the analog-to-digital
converter.
2.11 Port Signals
The K series contains 62 input/output lines arranged in eight ports, A
through H; all ports are eight bits except port D, which is six bits. The KS
series drops seven lines from port G and four from port H, for a total of
M68HC11K Family
MOTOROLA
Technical Data
Pin Description
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41
Freescale Semiconductor, Inc.
Pin Description
Freescale Semiconductor, Inc...
51 I/O lines. All ports are fully bidirectional except port E, which is input
only.
Each port can serve as either general-purpose I/O or as part of the
microcontroller’s specialized functions, depending on the operating
mode or peripheral functions selected. The functions of ports B, C, and
F and port G bit 7 depend on the operating mode. They serve as
general-purpose I/O lines in single-chip and bootstrap modes and
provide the address and data buses in expanded and special test
modes. The other ports serve as general-purpose I/O out of reset; writes
to control registers enable their special functions. Section 6. Parallel
Input/Output describes general-purpose I/O operation in detail.
Table 2-1 summarizes the ports and references for peripheral functions.
Table 2-2 summarizes the port signals.
Table 2-1. I/O Ports and Peripheral Functions
I/O Port
Special Function(s)
Enabled by
Refer to
Port A
Timer and
pulse accumulator
Control registers
Section 9. Timing System
Port B
High-order
address bus
Expanded
operating modes
Section 4. Operating Modes and On-Chip Memory
Port C
Data bus
Expanded
operating modes
Section 4. Operating Modes and On-Chip Memory
Port D
Serial communication
interface and
Serial peripheral
interface
Control registers
Section 7. Serial Communications Interface (SCI)
and
Section 8. Serial Peripheral Interface (SPI)
Port E
A/D converter
Control registers
Section 10. Analog-to-Digital (A/D) Converter
Port F
Low-order
address bus
Expanded
operating modes
Section 4. Operating Modes and On-Chip Memory
Port G
bit 7
bits 6–0(1)
R/W line
and expansion
address lines
Expanded
operating modes
and
control registers(2)
Section 4. Operating Modes and On-Chip Memory
and
Section 11. Memory Expansion and Chip Selects
Control registers
Section 9. Timing System
and
Section 11. Memory Expansion and Chip Selects
Port H
Chip-select lines
(1)
and
bits 7–4
pulse-width
modulator
bits 3–0
1. Not available on KS devices
2. Control registers can enable these functions only in expanded operating modes.
Technical Data
42
M68HC11K Family
Pin Description
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Pin Description
Port Signals
Table 2-2. Port Signal Summary
Freescale Semiconductor, Inc...
Port/Bit
Single-Chip and
Bootstrap Modes
Expanded and
Special Test Modes
PA0
PA0/IC3
PA1
PA1/IC2
PA2
PA2/IC1
PA3
PA3/OC5/IC4/and-or OC1
PA4
PA4/OC4/and-or OC1
PA5
PA5/OC3/and-or OC1
PA6
PA6/OC2/and-or OC1
PA7
PA7/PAI/and-or OC1
PB[7:0]
PB[7:0]
ADDR[15:8]
PC[7:0]
PC[7:0]
DATA[7:0]
PD0
PD0/RxD
PD1
PD1/TxD
PD2
PD2/MISO
PD3
PD3/MOSI
PD4
PD4/SCK
PD5
PD5/SS
PE[7:0]
PE[7:0]/AN[7:0]
PF[7:0]
PF[7:0]
ADDR[7:0]
PG0
PG0
PG0/XA13
PG1
PG1
PG1/XA14
PG2
PG2
PG2/XA15
PG3
PG3
PG3/XA16
PG4
PG4
PG4/XA17
PG5
PG5
PG5/XA18
PG6
PG6
PG6
PG7
PG7
PG7/R/W
PH0
PH0/PW1
PH1
PH1/PW2
PH2
PH2/PW3
PH3
PH3/PW4
PH4
PH4
PH4/CSIO
PH5
PH5
PH5/CSGP1
PH6
PH6
PH6/CSGP2
PH7
PH7
PH7/CSPROG
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Section 3. Central Processor Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.1
Accumulators A, B, and D (ACCA, ACCB, and ACCD) . . . . 47
3.3.2
Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.3
Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.5
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.1
Carry/Borrow (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.2
Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.6.3
Zero (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.3.6.4
Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.6.5
Interrupt Mask (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3.6.6
Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
3.3.6.7
Non-Maskable Interrupt (X) . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.6.8
Stop Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5
Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.6.1
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.2
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.3
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.4
Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.5
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6.6
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.7
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
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3.2 Introduction
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This section presents information on M68HC11 central processor unit
(CPU) architecture, data types, addressing modes, the instruction set,
and special operations, such as subroutine calls and interrupts.
The CPU employs memory-mapped input/output (I/O). There are no
special instructions for I/O; all peripheral, I/O, and memory locations are
simply addresses in the 64-Kbyte memory map. This architecture also
enables access to operands from external memory locations with no
execution time penalty.
3.3 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not
addressed as memory locations. The seven registers are shown in
Figure 3-1.
7
15
A
0
7
B
0
0
D
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
IX
INDEX REGISTER X
IY
INDEX REGISTER Y
SP
STACK POINTER
PC
PROGRAM COUNTER
7
S
0
X
H
I
N
Z
V
C
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
Figure 3-1. Programming Model
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CPU Registers
3.3.1 Accumulators A, B, and D (ACCA, ACCB, and ACCD)
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Accumulators A and B are general-purpose 8-bit registers that hold
operands and results of arithmetic calculations or data manipulations.
Some instructions treat these two accumulators as a single double-byte
(16-bit) accumulator called accumulator D. Most operations can use
either accumulator A or B, with these exceptions:
•
The ABX and ABY instructions add the contents of 8-bit
accumulator B to the contents of 16-bit register X or Y, but there
are no equivalent instructions that use A instead of B.
•
The TAP and TPA instructions transfer data from accumulator A
to the condition code register or from the condition code register
to accumulator A. However, there are no equivalent instructions
that use B rather than A.
•
The DAA instruction adjusts accumulator A after binary-coded
decimal (BCD) arithmetic operations, but there is no equivalent
BCD instruction to adjust accumulator B.
•
The add, subtract, and compare instructions associated with both
A and B (ABA, SBA, and CBA) only operate in one direction,
making planning ahead important to ensure the correct operand is
in the correct accumulator.
3.3.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the
8-bit offset provided in an instruction to create an effective address. The
IX register can be used also as a counter or as a temporary storage
register.
3.3.3 Index Register Y (IY)
The IY register provides a 16-bit indexed mode function similar to that of
the IX register. Instructions using the IY register require an extra byte of
machine code and an extra cycle of execution time because of the way
the opcode map is implemented.
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3.3.4 Stack Pointer (SP)
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The stack pointer holds the 16-bit address of the next free location in the
M68HC11 CPU’s automatic program stack. This stack is a data structure
that grows downward from high memory to low memory. The stack can
be located anywhere in the address space and can be any size up to the
amount of memory available in the system. Most application programs
initialize the SP at the beginning of an application program with a load
stack (LDS) instruction. Thereafter, each time the CPU pushes a new
byte onto the stack, it decrements the SP. To pull a byte from the stack,
the CPU first increments the SP. Figure 3-2 is a summary of SP
operations.
A jump-to-subroutine (JSR) or branch-to-subroutine (BSR) instruction
pushes the address of the instruction immediately after the JSR or BSR
onto the stack, least significant byte first. The last instruction of the
subroutine is a return-from-subroutine (RTS), which pulls the previously
stored return address from the stack and loads it into the program
counter. Execution then continues at this recovered return address.
When the processor recognizes an interrupt, it finishes the current
instruction, pushes the return address (the current value in the program
counter) onto the stack, pushes all of the CPU registers onto the stack,
and continues at the address specified by the vector for the interrupt.
The interrupt service routine ends with a return-from-interrupt (RTI)
instruction, which pulls the saved registers off the stack in reverse order.
Program execution resumes at the return address with all register
contents restored.
There are instructions that push and pull the A and B accumulators and
the X and Y index registers to preserve program context. For example,
push accumulator A onto the stack when entering a subroutine that uses
accumulator A, and pull accumulator A off the stack just before leaving
the subroutine, to ensure that the contents of that register will be the
same after returning from the subroutine as it was before starting the
subroutine.
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CPU Registers
JSR, JUMP TO SUBROUTINE
RTI, RETURN FROM INTERRUPT
MAIN PROGRAM
INTERRUPT ROUTINE
PC
PC
DIRECT
$9D = JSR
dd
RTN NEXT MAIN INSTR.
$3B = RTI
SP+2
SP+3
SP+4
PC
$AD = JSR
ff
RTN NEXT MAIN INSTR.
SP+5
7
SP–1
SP
PC
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0
SP+6
➩ SP–2
MAIN PROGRAM
INDEXED, Y
STACK
$18 = PRE
$AD = JSR
RTN
ff
NEXT MAIN INSTR.
SP+7
SP+8
RTNH
RTNL
➩ SP+9
MAIN PROGRAM
PC
$3F = SWI
SP–6
WAI, WAIT FOR INTERRUPT
PC
7
STACK
SP–3
$3E = WAI
SP–2
SP
7
STACK
SP
SP+1
➩ SP+2
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
LEGEND:
RTNH
RTNL
SP
RTS, RETURN FROM
SUBROUTINE
MAIN PROGRAM
0
0
➩ SP–2
SP–1
$39 = RTS
SP–4
SP–1
MAIN PROGRAM
PC
SP–5
MAIN PROGRAM
BSR, BRANCH TO SUBROUTINE
STACK
➩ SP–9
SP–7
$BD = PRE
hh
RTN
ll
NEXT MAIN INSTR.
$8D = BSR
7
SP–8
MAIN PROGRAM
PC
0
SWI, SOFTWARE INTERRUPT
PC
INDEXED, Y
STACK
CCR
ACCB
ACCA
IXH
IXL
IYH
IYL
RTNH
RTNL
SP+1
MAIN PROGRAM
INDEXED, X
7
SP
RTNH
RTNL
0
RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN PROGRAM TO
BE EXECUTED UPON RETURN FROM SUBROUTINE
RTNH = MOST SIGNIFICANT BYTE OF RETURN ADDRESS
RTNL = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS
➩ = STACK POINTER POSITION AFTER OPERATION IS COMPLETE
dd = 8-BIT DIRECT ADDRESS ($0000–$00FF) (HIGH BYTE ASSUMED
TO BE $00)
ff = 8-BIT POSITIVE OFFSET $00 (0) TO $FF (255) IS ADDED TO INDEX
hh = HIGH-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
ll = LOW-ORDER BYTE OF 16-BIT EXTENDED ADDRESS
rr= SIGNED RELATIVE OFFSET $80 (–128) TO $7F (+127) (OFFSET
RELATIVE TO THE ADDRESS FOLLOWING THE MACHINE CODE
OFFSET BYTE)
Figure 3-2. Stacking Operations
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3.3.5 Program Counter (PC)
The 16-bit program counter contains the address of the next instruction
to be executed. Its initial value after reset is fetched from one of six
possible vectors, depending on operating mode and the cause of reset,
as described in 5.3 Sources of Resets.
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3.3.6 Condition Code Register (CCR)
This 8-bit register contains:
•
Five condition code indicators (C, V, Z, N, and H)
•
Two interrupt masking bits (IRQ and XIRQ)
•
A stop disable bit (S)
Most instructions update condition codes automatically, as described in
the following paragraphs. Certain instructions, such as pushes, pulls,
add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions
do not affect the condition codes. Table 3-1 shows which condition
codes are affected by each instruction.
3.3.6.1 Carry/Borrow (C)
The C bit is set if the CPU performs a carry or borrow during an
arithmetic operation. This bit also acts as an error flag for multiply and
divide operations. Shift and rotate instructions operate with and through
the carry bit to facilitate multiple-word shift operations.
3.3.6.2 Overflow (V)
The overflow bit is set if an operation results in a two’s complement
overflow of the 8-bit signed range –128 to +127. Otherwise, the V bit is
cleared.
3.3.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation
operation is 0. Otherwise, the Z bit is cleared. Compare instructions do
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CPU Registers
an internal implied subtraction and the condition codes, including Z,
reflect the results of that subtraction. A few operations (INX, DEX, INY,
and DEY) affect the Z bit and no other condition flags.
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3.3.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative, meaning that the most significant bit (MSB) of the
result is a 1. Otherwise, the N bit is cleared. To determine quickly if the
MSB of a particular byte is set, load it into an accumulator and then
check the status of the N bit.
3.3.6.5 Interrupt Mask (I)
When the interrupt mask bit is set, it disables all maskable interrupt
requests (IRQs). The CPU continues to operate uninterrupted while
interrupts remain pending until the I bit is cleared. Every reset sets the
I bit by default and only a software instruction can clear it. When the
processor recognizes an interrupt, it stacks the registers, sets the I bit,
and then fetches the interrupt vector. The final instruction of an interrupt
service routine is usually a return from interrupt (RTI), which restores the
registers to the values that were present before the interrupt occurred
and clears the I bit.
NOTE:
Although the I bit can be cleared earlier in the interrupt service routine,
avoid nesting interrupts in this way without a clear understanding of
latency and of the arbitration mechanism.
Refer to Section 5. Resets and Interrupts.
3.3.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the
arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise,
the H bit is cleared. Half carry is used during binary-coded decimal
(BCD) operations.
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3.3.6.7 Non-Maskable Interrupt (X)
Setting the XIRQ mask (X) bit disables non-maskable interrupts from the
XIRQ pin. Every reset sets the X bit by default and only a software
instruction can clear it. When the processor recognizes a non-maskable
interrupt, it stacks the registers, sets the X and I bits, and then fetches
the interrupt vector. An interrupt service routine usually ends with a
return from interrupt (RTI), which restores the registers to the values that
were present before the interrupt occurred and clears the X bit. Only
hardware or an acknowledge can set the X bit. Only software can clear
the X bit (for example, the TAP instruction which transfers data from
accumulator A to the condition code register). There is no hardware
action for clearing X.
3.3.6.8 Stop Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from
putting the M68HC11 into a low-power stop condition. If the S bit is set,
the CPU treats a STOP instruction as if it were a no-operation (NOP)
instruction and continues to the next instruction.
NOTE:
S is set by reset and STOP is disabled by default.
The STOP instruction can be cleared by using the TAP instruction which
transfers data from accumulator A to the condition code register.
3.4 Data Types
The MC68HC11 CPU supports these data types:
•
Bit data
•
8-bit and 16-bit signed and unsigned integers
•
16-bit unsigned fractions
•
16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. Because the M68HC11 is an 8-bit CPU,
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Opcodes and Operands
there are no special requirements for alignment of instructions or
operands.
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3.5 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Every
instruction requires a unique opcode for each of its addressing modes.
The resulting number of opcodes exceeds the 256 available in an 8-bit
binary number. A 4-page opcode map has been implemented to
accommodate the extra instructions. An additional byte, called a
prebyte, directs the processor from page 0 of the opcode map to one of
the other three pages. As its name implies, the additional byte precedes
the opcode.
A complete instruction consists of a prebyte, if any, an opcode, and zero
to three operands. The operands contain information the CPU needs for
executing the instruction. Complete instructions can be from one to five
bytes long.
3.6 Addressing Modes
Six addressing modes can be used to access memory:
1. Immediate
2. Direct
3. Extended
4. Indexed
5. Inherent
6. Relative
All modes except inherent mode use an effective address. The effective
address is the memory address where the argument is fetched or stored
or the address from which execution is to proceed. The effective address
can be specified within an instruction or it can be calculated.
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3.6.1 Immediate
In the immediate addressing mode, the byte(s) immediately following the
opcode contain the arguments. The number of bytes following the
opcode matches the size of the register or memory location being used.
Immediate instructions can be two, three, or (if a prebyte is required) four
bytes.
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3.6.2 Direct
In the direct addressing mode, the user specifies only the low-order byte
of the effective address in a single byte following the opcode. The
processor assumes the high-order byte of the address to be $00. Thus,
the CPU accesses addresses $00–$FF directly, using 2-byte
instructions. This reduces execution time by eliminating the additional
memory access required for the high-order address byte. Most
applications reserve this 256-byte area for frequently referenced data,
but various combinations of internal registers, RAM, or external memory
can occupy these addresses.
3.6.3 Extended
In the extended addressing mode, the two bytes following the opcode
byte contain the effective address of the argument. For this reason,
instructions are three bytes, or they are four bytes if a prebyte is
required.
3.6.4 Indexed
In the indexed addressing mode, the CPU computes the effective
address of the argument by adding an 8-bit unsigned offset to the value
contained in an index register (IX or IY). Any memory location in the
64-Kbyte address space can be accessed with this mode. The
instructions are from two to five bytes.
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Instruction Set
3.6.5 Inherent
In the inherent addressing mode, the opcode contains all required
information. The operands (if any) are registers, so no memory access
is required. This mode includes:
•
Control instructions with no arguments
•
Operations that only involve the index registers or accumulators
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These instructions are one or two bytes.
3.6.6 Relative
Only branch instructions use the relative addressing mode. If the branch
condition is true, the CPU adds the 8-bit signed offset following the
opcode to the contents of the program counter to form the effective
branch address. Otherwise, control proceeds to the next instruction.
These are usually 2-byte instructions.
3.7 Instruction Set
Table 3-1 presents a detailed listing of all the M68HC11 instructions in
all possible addressing modes.
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Table 3-1. Instruction Set (Sheet 1 of 7)
Mnemonic
Operation
Description
ABA
Add
Accumulators
Add B to X
Add B to Y
Add with Carry
to A
A+B⇒A
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ABX
ABY
ADCA (opr)
Addressing
Mode
INH
IX + (00 : B) ⇒ IX
IY + (00 : B) ⇒ IY
A+M+C⇒A
ADCB (opr)
Add with Carry
to B
B+M+C⇒B
ADDA (opr)
Add Memory to
A
A+M⇒A
ADDB (opr)
Add Memory to
B
B+M⇒B
ADDD (opr)
Add 16-Bit to D
D + (M : M + 1) ⇒ D
ANDA (opr)
AND A with
Memory
A•M⇒A
ANDB (opr)
AND B with
Memory
B•M⇒B
ASL (opr)
Arithmetic Shift
Left
C
ASLA
0
b0
b7
b0
b7
18
18
18
18
18
18
18
18
18
Instruction
Operand
—
3A
3A
89
99
B9
A9
A9
C9
D9
F9
E9
E9
8B
9B
BB
AB
AB
CB
DB
FB
EB
EB
C3
D3
F3
E3
E3
84
94
B4
A4
A4
C4
D4
F4
E4
E4
78
68
68
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
hh ll
ff
ff
Cycles
2
S
—
X
—
Condition Codes
H
I
N
Z
∆
—
∆
∆
V
∆
C
∆
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
6
6
7
—
—
—
—
—
—
—
—
∆
—
—
—
—
—
∆
—
—
∆
—
—
∆
—
—
∆
—
—
∆
—
∆
∆
∆
∆
—
—
∆
—
∆
∆
∆
∆
—
—
∆
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
A
INH
48
—
2
—
—
—
—
∆
∆
∆
∆
B
INH
58
—
2
—
—
—
—
∆
∆
∆
∆
INH
05
—
3
—
—
—
—
∆
∆
∆
∆
77
67
67
47
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
A
EXT
IND,X
IND,Y
INH
—
—
—
—
∆
∆
∆
∆
B
INH
57
—
2
—
—
—
—
∆
∆
∆
∆
REL
24
rr
3
—
—
—
—
—
—
—
—
DIR
IND,X
IND,Y
REL
15
1D
1D
25
dd mm
ff mm
ff mm
rr
6
7
8
3
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
0
Arithmetic Shift
Left B
C
ASLD
A
A
A
A
A
B
B
B
B
B
Arithmetic Shift
Left A
C
ASLB
b7
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
Opcode
1B
0
b0
Arithmetic Shift
Left D
0
C b7 A b0 b7 B b0
ASR
Arithmetic Shift
Right
ASRA
Arithmetic Shift
Right A
ASRB
Arithmetic Shift
Right B
BCC (rel)
Branch if Carry
Clear
Clear Bit(s)
b7
b7
b7
BCLR (opr)
(msk)
BCS (rel)
Branch if Carry
Set
b0
b0
b0
C
C
C
?C=0
M • (mm) ⇒ M
?C=1
18
18
Technical Data
56
M68HC11K Family
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-1. Instruction Set (Sheet 2 of 7)
Mnemonic
Operation
Description
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
Branch if = Zero
Branch if ∆ Zero
Branch if > Zero
Branch if
Higher
Branch if
Higher or Same
Bit(s) Test A
with Memory
?Z=1
?N⊕V=0
? Z + (N ⊕ V) = 0
?C+Z=0
BITB (opr)
Bit(s) Test B
with Memory
B•M
BLE (rel)
BLO (rel)
BLS (rel)
Branch if ∆ Zero
Branch if Lower
Branch if Lower
or Same
Branch if < Zero
Branch if Minus
Branch if not =
Zero
Branch if Plus
Branch Always
Branch if
Bit(s) Clear
? Z + (N ⊕ V) = 1
?C=1
?C+Z=1
Branch Never
Branch if Bit(s)
Set
?1=0
? (M) • mm = 0
Set Bit(s)
M + mm ⇒ M
Branch to
Subroutine
Branch if
Overflow Clear
Branch if
Overflow Set
Compare A to B
Clear Carry Bit
Clear Interrupt
Mask
Clear Memory
Byte
See Figure 3-2
Clear
Accumulator A
Clear
Accumulator B
Clear Overflow
Flag
Compare A to
Memory
0⇒A
0⇒B
Compare B to
Memory
B–M
BHS (rel)
Freescale Semiconductor, Inc...
BITA (opr)
BLT (rel)
BMI (rel)
BNE (rel)
BPL (rel)
BRA (rel)
BRCLR(opr)
(msk)
(rel)
BRN (rel)
BRSET(opr)
(msk)
(rel)
BSET (opr)
(msk)
BSR (rel)
BVC (rel)
BVS (rel)
CBA
CLC
CLI
CLR (opr)
CLRA
CLRB
CLV
CMPA (opr)
CMPB (opr)
Addressing
Mode
REL
REL
REL
REL
?C=0
A•M
A
A
A
A
A
B
B
B
B
B
?N⊕V=1
?N=1
?Z=0
?N=0
?1=1
? M • mm = 0
Opcode
27
2C
2E
22
Instruction
Operand
rr
rr
rr
rr
Cycles
3
3
3
3
S
—
—
—
—
X
—
—
—
—
Condition Codes
H
I
N
Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
—
—
—
—
C
—
—
—
—
REL
24
rr
3
—
—
—
—
—
—
—
—
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
REL
REL
85
95
B5
A5
A5
C5
D5
F5
E5
E5
2F
25
23
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
2
3
4
4
5
2
3
4
4
5
3
3
3
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REL
REL
REL
2D
2B
26
rr
rr
rr
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
REL
REL
DIR
IND,X
IND,Y
REL
DIR
IND,X
IND,Y
DIR
IND,X
IND,Y
REL
2A
20
13
1F
1F
21
12
1E
1E
14
1C
1C
8D
rr
rr
dd mm rr
ff mm rr
ff mm rr
rr
dd mm rr
ff mm rr
ff mm rr
dd mm
ff mm
ff mm
rr
3
3
6
7
8
3
6
7
8
6
7
8
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
18
18
18
18
18
?V=0
REL
28
rr
3
—
—
—
—
—
—
—
—
?V=1
REL
29
rr
3
—
—
—
—
—
—
—
—
A–B
0⇒C
0⇒I
INH
INH
INH
11
0C
0E
—
—
—
2
2
2
—
—
—
—
—
—
—
—
—
—
—
0
∆
—
—
∆
—
—
∆
—
—
∆
0
—
0⇒M
7F
6F
6F
4F
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
0
1
0
0
A
EXT
IND,X
IND,Y
INH
—
—
—
—
0
1
0
0
B
INH
5F
—
2
—
—
—
—
0
1
0
0
INH
0A
—
2
—
—
—
—
—
—
0
—
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
81
91
B1
A1
A1
C1
D1
F1
E1
E1
2
3
4
4
5
2
3
4
4
5
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
0⇒V
A–M
A
A
A
A
A
B
B
B
B
B
18
18
18
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
M68HC11K Family
MOTOROLA
Technical Data
Central Processor Unit (CPU)
For More Information On This Product,
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57
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 3-1. Instruction Set (Sheet 3 of 7)
$FF – B ⇒ B
B
Operation
Description
COM (opr)
Ones
Complement
Memory Byte
Ones
Complement
A
Ones
Complement
B
Compare D to
Memory 16-Bit
$FF – M ⇒ M
COMA
COMB
CPD (opr)
Freescale Semiconductor, Inc...
$FF – A ⇒ A
Addressing
Mode
EXT
IND,X
IND,Y
A
INH
Mnemonic
D–M:M +1
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
Cycles
6
6
7
2
S
—
X
—
Condition Codes
H
I
N
Z
—
—
∆
∆
—
—
—
—
∆
—
2
—
—
—
—
83
93
B3
A3
A3
8C
9C
BC
AC
AC
8C
9C
BC
AC
AC
19
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
—
5
6
7
7
7
4
5
6
6
7
5
6
7
7
7
2
—
—
—
—
—
—
7A
6A
6A
4A
hh ll
ff
ff
—
Opcode
73
63
18
63
43
Instruction
Operand
hh ll
ff
ff
—
53
1A
1A
1A
1A
CD
V
0
C
1
∆
0
1
∆
∆
0
1
—
∆
∆
∆
∆
—
—
∆
∆
∆
∆
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
6
6
7
2
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
∆
∆
—
CPX (opr)
Compare X to
Memory 16-Bit
IX – M : M + 1
CPY (opr)
Compare Y to
Memory 16-Bit
IY – M : M + 1
DAA
Decimal Adjust
A
Decrement
Memory Byte
Adjust Sum to BCD
Decrement
Accumulator
A
Decrement
Accumulator
B
Decrement
Stack Pointer
Decrement
Index Register
X
Decrement
Index Register
Y
Exclusive OR A
with Memory
A–1⇒A
A
EXT
IND,X
IND,Y
INH
B–1⇒B
B
INH
5A
—
2
—
—
—
—
∆
∆
∆
—
SP – 1 ⇒ SP
INH
34
—
3
—
—
—
—
—
—
—
—
IX – 1 ⇒ IX
INH
09
—
3
—
—
—
—
—
∆
—
—
IY – 1 ⇒ IY
INH
09
—
4
—
—
—
—
—
∆
—
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
2
3
4
4
5
2
3
4
4
5
41
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
∆
∆
∆
DEC (opr)
DECA
DECB
DES
DEX
DEY
EORA (opr)
M–1⇒M
A⊕M⇒A
18
18
EORB (opr)
Exclusive OR B
with Memory
B⊕M⇒B
FDIV
Fractional
Divide 16 by 16
Integer Divide
16 by 16
Increment
Memory Byte
D / IX ⇒ IX; r ⇒ D
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
D / IX ⇒ IX; r ⇒ D
INH
02
—
41
—
—
—
—
—
∆
0
∆
7C
6C
6C
4C
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
—
—
—
—
—
∆
∆
∆
—
5C
—
2
—
—
—
—
∆
∆
∆
—
IDIV
INC (opr)
INCA
INCB
Increment
Accumulator
A
Increment
Accumulator
B
A
A
A
A
A
B
B
B
B
B
CD
18
18
18
1A
18
M+1⇒M
A+1⇒A
A
EXT
IND,X
IND,Y
INH
B+1⇒B
B
INH
18
18
18
88
98
B8
A8
A8
C8
D8
F8
E8
E8
03
Technical Data
58
M68HC11K Family
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Instruction Set
Table 3-1. Instruction Set (Sheet 4 of 7)
Mnemonic
Operation
Description
INS
Increment
Stack Pointer
Increment
Index Register
X
Increment
Index Register
Y
Jump
SP + 1 ⇒ SP
INX
INY
Freescale Semiconductor, Inc...
JMP (opr)
Addressing
Mode
INH
IX + 1 ⇒ IX
INH
IY + 1 ⇒ IY
INH
See Figure 3-2
JSR (opr)
Jump to
Subroutine
See Figure 3-2
LDAA (opr)
Load
Accumulator
A
M⇒A
LDAB (opr)
Load
Accumulator
B
M⇒B
LDD (opr)
Load Double
Accumulator
D
M ⇒ A,M + 1 ⇒ B
LDS (opr)
Load Stack
Pointer
M : M + 1 ⇒ SP
LDX (opr)
Load Index
Register
X
M : M + 1 ⇒ IX
LDY (opr)
Load Index
Register
Y
M : M + 1 ⇒ IY
LSL (opr)
Logical Shift
Left
C
LSLA
Logical Shift
Left A
LSLB
Logical Shift
Left B
C
C
LSLD
LSRA
LSRB
b7
b7
b0
b0
b0
Logical Shift
Right
Logical Shift
Right A
Logical Shift
Right B
0
0
b7
b7
b7
b0
b0
b0
Cycles
3
S
—
X
—
Condition Codes
H
I
N
Z
—
—
—
—
V
—
C
—
08
—
3
—
—
—
—
—
∆
—
—
08
—
4
—
—
—
—
—
∆
—
—
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
hh ll
ff
ff
—
3
3
4
5
6
6
7
2
3
4
4
5
2
3
4
4
5
3
4
5
5
6
3
4
5
5
6
3
4
5
5
6
4
5
6
6
6
6
6
7
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
A
B
INH
58
—
2
—
—
—
—
∆
∆
∆
∆
INH
05
—
3
—
—
—
—
∆
∆
∆
∆
74
64
64
44
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
0
∆
∆
∆
A
EXT
IND,X
IND,Y
INH
—
—
—
—
0
∆
∆
∆
B
INH
54
—
2
—
—
—
—
0
∆
∆
∆
0
18
18
18
18
18
18
CD
18
18
18
1A
18
18
7E
6E
6E
9D
BD
AD
AD
86
96
B6
A6
A6
C6
D6
F6
E6
E6
CC
DC
FC
EC
EC
8E
9E
BE
AE
AE
CE
DE
FE
EE
EE
CE
DE
FE
EE
EE
78
68
68
48
0
0
b7 A b0 b7 B b0
0
18
Instruction
Operand
—
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
EXT
IND,X
IND,Y
INH
A
A
A
A
A
B
B
B
B
B
Logical Shift
Left Double
C
LSR (opr)
b7
Opcode
31
0
C
18
C
C
M68HC11K Family
MOTOROLA
Technical Data
Central Processor Unit (CPU)
For More Information On This Product,
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59
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 3-1. Instruction Set (Sheet 5 of 7)
Mnemonic
Operation
LSRD
Logical Shift
Right Double
MUL
NEG (opr)
Multiply 8 by 8
Two’s
Complement
Memory Byte
Two’s
Complement
A
Two’s
Complement
B
No operation
OR
Accumulator
A (Inclusive)
NEGA
Freescale Semiconductor, Inc...
NEGB
NOP
ORAA (opr)
ORAB (opr)
OR
Accumulator
B (Inclusive)
PSHA
ROL (opr)
Push A onto
Stack
Push B onto
Stack
Push X onto
Stack (Lo
First)
Push Y onto
Stack (Lo
First)
Pull A from
Stack
Pull B from
Stack
Pull X From
Stack (Hi
First)
Pull Y from
Stack (Hi
First)
Rotate Left
ROLA
Rotate Left A
ROLB
Rotate Left B
ROR (opr)
Rotate Right
RORA
Rotate Right A
RORB
Rotate Right B
RTI
Return from
Interrupt
Return from
Subroutine
PSHB
PSHX
PSHY
PULA
PULB
PULX
PULY
0
Instruction
Operand
—
Cycles
3
S
—
X
—
Condition Codes
H
I
N
Z
—
—
0
∆
V
∆
C
∆
3D
70
60
60
40
—
hh ll
ff
ff
—
10
6
6
7
2
—
—
—
—
—
—
—
—
—
∆
—
∆
—
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
2
—
—
—
—
∆
∆
∆
∆
—
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
2
2
3
4
4
5
2
3
4
4
5
3
—
—
—
—
—
—
—
—
—
∆
—
∆
—
0
—
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
Opcode
04
b7 A b0 b7 B b0 C
A∗B⇒D
0–M⇒M
0–A⇒A
A
INH
EXT
IND,X
IND,Y
INH
0–B⇒B
B
INH
50
A
A
A
A
A
B+M⇒B
B
B
B
B
B
A ⇒ Stk,SP = SP – 1 A
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
01
8A
9A
BA
AA
AA
CA
DA
FA
EA
EA
36
B ⇒ Stk,SP = SP – 1 B
INH
37
—
3
—
—
—
—
—
—
—
—
IX ⇒ Stk,SP = SP – 2
INH
3C
—
4
—
—
—
—
—
—
—
—
IY ⇒ Stk,SP = SP – 2
INH
3C
—
5
—
—
—
—
—
—
—
—
SP = SP + 1, A ⇐ Stk A
INH
32
—
4
—
—
—
—
—
—
—
—
SP = SP + 1, B ⇐ Stk B
INH
33
—
4
—
—
—
—
—
—
—
—
SP = SP + 2, IX ⇐ Stk
INH
38
—
5
—
—
—
—
—
—
—
—
SP = SP + 2, IY ⇐ Stk
INH
18
38
—
6
—
—
—
—
—
—
—
—
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
18
79
69
69
49
—
—
—
—
∆
∆
∆
∆
No Operation
A+M⇒A
18
18
18
18
A
EXT
IND,X
IND,Y
INH
B
INH
59
—
2
—
—
—
—
∆
∆
∆
∆
76
66
66
46
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
∆
∆
∆
A
EXT
IND,X
IND,Y
INH
—
—
—
—
∆
∆
∆
∆
B
INH
56
—
2
—
—
—
—
∆
∆
∆
∆
See Figure 3-2
INH
3B
—
12
∆
↓
∆
∆
∆
∆
∆
∆
See Figure 3-2
INH
39
—
5
—
—
—
—
—
—
—
—
C
C
C
b7
b7
b7
RTS
Addressing
Mode
INH
Description
b7
b7
b7
b0
b0
b0
b0 C
18
b0 C
b0 C
Technical Data
60
M68HC11K Family
Central Processor Unit (CPU)
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Central Processor Unit (CPU)
Instruction Set
Table 3-1. Instruction Set (Sheet 6 of 7)
Mnemonic
Operation
Description
SBA
Subtract B from
A
Subtract with
Carry from A
A–B⇒A
Freescale Semiconductor, Inc...
SBCA (opr)
A–M–C⇒A
Addressing
Mode
INH
Instruction
Operand
—
Cycles
2
S
—
X
—
Condition Codes
H
I
N
Z
—
—
∆
∆
—
—
—
—
∆
V
∆
C
∆
∆
∆
∆
SBCB (opr)
Subtract with
Carry from B
B–M–C⇒B
SEC
SEI
Set Carry
Set Interrupt
Mask
Set Overflow
Flag
Store
Accumulator
A
1⇒C
1⇒I
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
1⇒V
INH
0B
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
97
B7
A7
A7
D7
F7
E7
E7
DD
FD
ED
ED
CF
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
—
3
4
4
5
3
4
4
5
4
5
5
6
2
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
—
—
—
—
9F
BF
AF
AF
DF
FF
EF
EF
DF
FF
EF
EF
80
90
B0
A0
A0
C0
D0
F0
E0
E0
83
93
B3
A3
A3
3F
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
—
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
14
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
0
—
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
—
∆
∆
∆
∆
—
—
—
1
—
—
—
—
SEV
STAA (opr)
A⇒M
STAB (opr)
Store
Accumulator
B
B⇒M
STD (opr)
Store
Accumulator
D
A ⇒ M, B ⇒ M + 1
STOP
Stop Internal
Clocks
Store Stack
Pointer
—
STS (opr)
Store Index
Register X
IX ⇒ M : M + 1
STY (opr)
Store Index
Register Y
IY ⇒ M : M + 1
SUBA (opr)
Subtract
Memory from
A
A–M⇒A
SUBB (opr)
Subtract
Memory from
B
B–M⇒B
SUBD (opr)
Subtract
Memory from
D
D–M:M+1⇒D
SWI
Software
Interrupt
Transfer A to B
Transfer A to
CC Register
Transfer B to A
TEST (Only in
Test Modes)
See Figure 3-2
TBA
TEST
A
A
A
A
B
B
B
B
SP ⇒ M : M + 1
STX (opr)
TAB
TAP
A
A
A
A
A
B
B
B
B
B
Opcode
10
A
A
A
A
A
A
A
A
A
A
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
18
18
18
18
18
18
CD
18
18
1A
18
18
18
18
82
92
B2
A2
A2
C2
D2
F2
E2
E2
0D
0F
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
—
—
2
3
4
4
5
2
3
4
4
5
2
2
—
—
—
—
∆
∆
∆
∆
—
—
—
—
—
—
—
1
—
—
—
—
—
—
1
—
—
2
—
—
—
—
—
—
1
—
A⇒B
A ⇒ CCR
INH
INH
16
06
—
—
2
2
—
∆
—
↓
—
∆
—
∆
∆
∆
∆
∆
0
∆
—
∆
B⇒A
Address Bus Counts
INH
INH
17
00
—
—
2
*
—
—
—
—
—
—
—
—
∆
—
∆
—
0
—
—
—
M68HC11K Family
MOTOROLA
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Central Processor Unit (CPU)
Table 3-1. Instruction Set (Sheet 7 of 7)
Addressing
Mode
INH
Instruction
Operand
—
Cycles
2
S
—
X
—
Condition Codes
H
I
N
Z
—
—
—
—
7D
6D
6D
4D
hh ll
ff
ff
—
6
6
7
2
—
—
—
—
∆
—
—
—
—
INH
5D
—
2
—
—
—
SP + 1 ⇒ IX
INH
30
—
3
—
—
SP + 1 ⇒ IY
INH
30
—
4
—
IX – 1 ⇒ SP
INH
35
—
3
IY – 1 ⇒ SP
INH
35
—
Stack Regs & WAIT
INH
3E
IX ⇒ D, D ⇒ IX
INH
IY ⇒ D, D ⇒ IY
INH
Mnemonic
Operation
Description
TPA
Transfer CC
Register to A
Test for Zero or
Minus
CCR ⇒ A
Test A for Zero
or Minus
Test B for Zero
or Minus
Transfer Stack
Pointer to X
Transfer Stack
Pointer to Y
Transfer X to
Stack Pointer
Transfer Y to
Stack Pointer
Wait for
Interrupt
Exchange D
with X
Exchange D
with Y
A–0
A
EXT
IND,X
IND,Y
INH
B–0
B
TST (opr)
TSTA
TSTB
TSX
TSY
Freescale Semiconductor, Inc...
TXS
TYS
WAI
XGDX
XGDY
Cycle
*
**
M–0
Opcode
07
18
18
18
18
V
—
C
—
∆
0
0
∆
∆
0
0
—
∆
∆
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
—
—
**
—
—
—
—
—
—
—
—
8F
—
3
—
—
—
—
—
—
—
—
8F
—
4
—
—
—
—
—
—
—
—
Infinity or until reset occurs
12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
Operands
dd
= 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
ff
= 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh
= High-order byte of 16-bit extended address
ii
= One byte of immediate data
jj
= High-order byte of 16-bit immediate data
kk
= Low-order byte of 16-bit immediate data
ll
= Low-order byte of 16-bit extended address
mm
= 8-bit mask (set bits to be affected)
rr
= Signed relative offset $80 (–128) to $7F (+127)
(offset relative to address following machine code offset byte))
Operators
()
Contents of register shown inside parentheses
⇐
Is transferred to
⇑
Is pulled from stack
⇓
Is pushed onto stack
•
Boolean AND
+
Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕
Exclusive-OR
∗
Multiply
:
Concatenation
–
Arithmetic subtraction symbol or negation symbol (two’s complement)
Condition Codes
—
Bit not changed
0
Bit always cleared
1
Bit always set
∆
Bit cleared or set, depending on operation
↓
Bit can be cleared, cannot become set
Technical Data
62
M68HC11K Family
Central Processor Unit (CPU)
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Technical Data — M68HC11K Family
Section 4. Operating Modes and On-Chip Memory
4.1 Contents
Freescale Semiconductor, Inc...
4.2
4.3
4.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.5
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5.1
Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.5.2
Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4.5.3
Bootstrap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.5.4
Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5.5
Mode Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.6
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.6.1
Control Registers and RAM . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.6.2
ROM or EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
4.6.3
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.6.4
Bootloader ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
4.7
EPROM/OTPROM (M68HC711K4 and M68HC711KS2). . . . . 90
4.7.1
Programming the EPROM with Downloaded Data. . . . . . . . 90
4.7.2
Programming the EPROM from Memory . . . . . . . . . . . . . . .91
4.8
EEPROM and the CONFIG Register . . . . . . . . . . . . . . . . . . . . 93
4.8.1
EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.8.1.1
EEPROM Programming Control Register . . . . . . . . . . . . 94
4.8.1.2
Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.8.1.3
System Configuration Options Register . . . . . . . . . . . . . . 97
4.8.2
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.8.2.1
EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.8.2.2
EEPROM Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.2.3
EEPROM Row Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.2.4
EEPROM Byte Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.8.3
CONFIG Register Programming . . . . . . . . . . . . . . . . . . . . 100
4.8.4
RAM and EEPROM Security . . . . . . . . . . . . . . . . . . . . . . .100
4.9
XOUT Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.9.1
System Configuration Register. . . . . . . . . . . . . . . . . . . . . . 102
4.9.2
System Configuration Options 2 Register . . . . . . . . . . . . . 103
M68HC11K Family
MOTOROLA
Technical Data
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Operating Modes and On-Chip Memory
4.2 Introduction
Freescale Semiconductor, Inc...
This section presents the elements involved in configuring the
M68HC11K/KS Family microcontrollers (MCUs), including:
•
A list of the control registers, see 4.3 Control Registers
•
Special registers that control system initialization, see 4.4 System
Initialization
•
Description of the four operating modes and how they’re selected,
see 4.5 Operating Modes
•
Memory maps of the K Family, see 4.6 Memory Map
•
Information on programming EPROM (erasable, programmable
read-only memory) and EEPROM (electrically erasable,
programmable read-only memory), see 4.7 EPROM/OTPROM
(M68HC711K4 and M68HC711KS2) and 4.8 EEPROM and the
CONFIG Register
4.3 Control Registers
The heart of the M68HC11 Family of MCUs is a special register block
which controls the peripheral functions. In the K Family, this block is 128
bytes. The default location of this block is the first 128 bytes of memory,
but software can map it to any 4-Kbyte boundary (see 4.6.1 Control
Registers and RAM).
Certain bits and registers that control initialization and the basic
operation of the MCU are protected against writes in normal operating
modes except under special circumstances. Some bits cannot be written
at all; others can be written only once and/or within the first 64 bus cycles
after any reset. The special operating modes override these restrictions.
These bits and registers are discussed in 4.4 System Initialization.
Normal and special operating modes are discussed in 4.5 Operating
Modes. The write-restricted registers and bits are summarized in
Table 4-1.
Figure 4-1 lists the entire 128-byte register block in ascending order by
address, using the default memory block assignment $0000–$007F.
Technical Data
64
M68HC11K Family
Operating Modes and On-Chip Memory
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Operating Modes and On-Chip Memory
Control Registers
NOTE:
Addr.
Freescale Semiconductor, Inc...
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
Register Name
Port A Data Register Read:
(PORTA) Write:
See page 138. Reset:
Port A Data Direction Read:
Register (DDRA) Write:
See page 138. Reset:
Port B Data Direction Read:
Register (DDRB) Write:
See page 139. Reset:
Port F Data Direction Read:
Register (DDRF) Write:
See page 144. Reset:
Port B Data Register Read:
(PORTB) Write:
See page 139. Reset:
Port F Data Register Read:
(PORTF) Write:
See page 144. Reset:
Port C Data Register Read:
(PORTC) Write:
See page 140. Reset:
Port C Data Direction Read:
Register (DDRC) Write:
See page 141. Reset:
Port D Data Register Read:
(PORTD) Write:
See page 142. Reset:
Port D Data Direction Read:
Register (DDRD) Write:
See page 142. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Undefined after reset
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
0
0
0
0
0
0
0
0
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
0
0
0
0
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PF2
PF1
PF0
PC2
PC1
PC0
Undefined after reset
PF7
PF6
PF5
PF4
PF3
Undefined after reset
PC7
PC6
PC5
PC4
PC3
Undefined after reset
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
0
0
0
0
0
0
0
0
0
0
PD5
PD4
PD3
PD2
PD1
PD0
0
0
U
U
U
U
U
U
0
0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 1 of 11)
M68HC11K Family
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Operating Modes and On-Chip Memory
Addr.
$000A
Port E Data Register Read:
(PORTE) Write:
See page 143. Reset:
Timer Compare Force Read:
Register (CFORC) Write:
See page 201. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PD1
PD0
Undefined after reset
FOC1
FOC2
FOC3
FOC4
FOC5
0
0
0
0
0
0
0
0
0
0
0
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
0
0
0
0
0
0
0
0
0
0
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
0
0
0
0
0
0
0
0
0
0
0
Timer Counter Register Read:
$000E
High (TCNTH) Write:
See page 188. Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Timer Counter Register Read:
$000F
Low (TCNTL) Write:
See page 188. Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
$000B
Freescale Semiconductor, Inc...
Register Name
Output Compare 1 Read:
$000C Mask Register (OC1M) Write:
See page 202. Reset:
Output Compare 1 Data Read:
$000D
Register (OC1D) Write:
See page 202. Reset:
$0010
$0011
$0012
$0013
$0014
Timer Input Capture 1 Read:
Register High (TIC1H) Write:
See page 192. Reset:
Timer Input Capture 1 Read:
Register Low (TIC1L) Write:
See page 192. Reset:
Timer Input Capture 2 Read:
Register High (TIC2H) Write:
See page 192. Reset:
Timer Input Capture 2 Read:
Register Low (TIC2L) Write:
See page 192. Reset:
Timer Input Capture 3 Read:
Register High (TIC3H) Write:
See page 192. Reset:
Undefined after reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Undefined after reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Undefined after reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Undefined after reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Undefined after reset
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 2 of 11)
Technical Data
66
M68HC11K Family
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Control Registers
Addr.
$0015
$0016
Freescale Semiconductor, Inc...
$0017
$0018
$0019
$001A
$001B
$001C
$001D
Register Name
Timer Input Capture 3 Read:
Register Low (TIC3L) Write:
See page 192. Reset:
Timer Output Read:
Compare 1 High Write:
Register (TOC1H)
See page 197. Reset:
Timer Output Read:
Compare 1 Low Write:
Register (TOC1L)
See page 197. Reset:
Timer Output Read:
Compare 2 High Write:
Register (TOC2H)
See page 197. Reset:
Timer Output Read:
Compare 2 Low Write:
Register (TOC2L)
See page 197. Reset:
Timer Output Read:
Compare 3 High Write:
Register (TOC3H)
See page 197. Reset:
Timer Output Read:
Compare 3 Low Write:
Register (TOC3L)
See page 197. Reset:
Timer Output Read:
Compare 4 High Write:
Register (TOC4H)
See page 197. Reset:
Timer Output Read:
Compare 4 Low Write:
Register (TOC4L)
See page 197. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Undefined after reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 3 of 11)
M68HC11K Family
MOTOROLA
Technical Data
Operating Modes and On-Chip Memory
For More Information On This Product,
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67
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
Register Name
Timer Input Capture 4/ Read:
Output Compare 5 Reg. Write:
$001E
High (TI4H/O5H)
See page 199. Reset:
Timer Input Capture 4/ Read:
Output Compare 5 Reg. Write:
$001F
Low (TI4L/O5L)
See page 199. Reset:
Freescale Semiconductor, Inc...
$0020
$0021
Timer Control 1 Read:
Register (TCTL1) Write:
See page 200. Reset:
Timer Control 2 Read:
Register (TCTL2) Write:
See page 195. Reset:
Timer Interrupt Mask 1 Read:
$0022
Register (TMSK1) Write:
See page 200. Reset:
$0023
Timer Interrupt Flag 1 Read:
Register (TFLG1) Write:
See page 199. Reset:
Timer Interrupt Mask 2 Read:
$0024
Register (TMSK2) Write:
See page 209. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0
0
0
0
0
0
0
0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
0
0
0
0
0
0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
TOI
RTII
PAOVI
PAII
0
0
PR1(1)
PR0(1)
0
0
0
0
0
0
0
0
1. Can be written only once in first 64 cycles out of reset in normal modes
$0025
$0026
$0027
Timer Interrupt Flag 2 Read:
(TFLG2) Write:
See page 209. Reset:
Pulse Accumulator Read:
Control Register Write:
(PACTL)
See page 210. Reset:
Pulse Accumulator Read:
Count Register Write:
(PACNT)
See page 208. Reset:
TOF
RTIF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
0
PAEN
PAMOD
PEDGE
0
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Undefined after reset
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 4 of 11)
Technical Data
68
M68HC11K Family
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Control Registers
Addr.
Register Name
Serial Peripheral Read:
Control Register Write:
(SPCR)
See page 174. Reset:
$0028
Serial Peripheral Status Read:
$0029
Register (SPSR) Write:
See page 176. Reset:
Freescale Semiconductor, Inc...
$002A
Serial Peripheral Data Read:
Register (SPDR) Write:
See page 177. Reset:
EPROM Programming Read:
Control Register Write:
$002B
(EPROG)(1)
See page 91. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
0
0
0
1
U
U
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Undefined after reset
R
0
ELAT
EXCOL
EXROW
0
0
EPGM
0
0
0
0
0
0
0
0
0
0
0
0
HPPUE
GPPUE
FPPUE
BPPUE
0
0
0
0
1
1
1
1
0
0
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
0
0
0
0
0
0
0
0
1. Present only in EPROM (711) devices
Port Pullup Assignment Read:
$002C
Register (PPAR) Write:
See page 147. Reset:
$002D
$002E
Port G Assignment Read:
Register (PGAR) Write:
See page 235. Reset:
System Configuration Read:
Options 3 Register Write:
(OPT3)(2)
See page 132. Reset:
SM
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
CCF
0
SCAN
MULT
CD
CC
CB
CA
0
0
U
U
U
U
U
U
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2. Not available on M68HC11K4 devices
$002F
Reserved
Analog-to-Digital Read:
Control/Status Register Write:
$0030
(ADCTL)
See page 227. Reset:
$0031
Analog-to-Digital Read:
Results Register 1 Write:
(ADR1)
See page 229. Reset:
Undefined after reset
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 5 of 11)
M68HC11K Family
MOTOROLA
Technical Data
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
69
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
$0032
$0033
Freescale Semiconductor, Inc...
$0034
$0035
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Analog-to-Digital Read:
Results Register 2 Write:
(ADR2)
See page 229. Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Analog-to-Digital Read:
Results Register 3 Write:
(ADR3)
See page 229. Reset:
Bit 7
Bit 2
Bit 1
Bit 0
Analog-to-Digital Read:
Results Register 4 Write:
(ADR4)
See page 229.l Reset:
Bit 7
Bit 2
Bit 1
Bit 0
Block Protect Register Read:
(BPROT)(1) Write:
See page 96. Reset:
Undefined after reset
Bit 6
Bit 5
Bit 4
Bit 3
Undefined after reset
Bit 6
Bit 5
Bit 4
Bit 3
Undefined after reset
BULKP
LVPEN
BPRT4
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
1
1
1
1
1
1
1
1
1. Can be written only once to 0 in first 64 cycles out of reset in normal modes
$0036
Reserved
$0037
EEPROM Mapping Read:
Register (INIT2)(2) Write:
See page 89. Reset:
R
R
R
R
R
R
R
R
EE3
EE2
EE1
EE0
0
0
0
0
0
0
0
0
0
0
0
0
LSBF
SPR2
XDV1
XDV0
2. Can only be written once after reset in normal modes
$0038
System Configuration Read:
Options 2 Register Write:
(OPT2)
See pages 40, 103, Reset:
112, 141,
STRCH(3) IRVNE(4)
LIRDV
CWOM
0
0
0
—
0
0
0
0
ADPU
CSEL
IRQE(5)
DLY(5)
CME
FCME(5)
CR1(5)
CR0(5)
0
0
0
1
0
0
0
0
R
= Reserved
3. Not available on M68HC11KS devices
4. Can be written only once after reset in normal modes
$0039
System Configuration Read:
Options Register Write:
(OPTION)
See pages 97, 109, Reset:
111, 112, 121, 147
5. Can only be written once in first 64 cycles out of reset in normal modes
= Unimplemented
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 6 of 11)
Technical Data
70
M68HC11K Family
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Control Registers
Addr.
Register Name
Arm/Reset COP Timer Read:
Circuitry Register Write:
$003A
(COPRST)
See page 110. Reset:
EEPROM Programming Read:
Control Register Write:
$003B
(PPROG)
See page 91. Reset:
Freescale Semiconductor, Inc...
$003C
$003D
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
ODD
EVEN
BYTE
ROW
ERASE
EELAT
EEPGM
0
0
0
0
0
0
0
0
SMOD
MDA
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
—
—
0
0
1
1
0
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
0
Highest Priority I-Bit Read:
Interrupt and Misc. Write: RBOOT
Register (HPRIO)
—
See pages 80, 123 Reset:
RAM and I/O Mapping Read:
Register (INIT)(1) Write:
See page 84. Reset:
LVPI
1. Can only be written once in first 64 cycles out of reset in normal modes
Read:
Test 1 Register
(TEST1)
$003E
Write:
Reset:
$003F
TILOP
0
OCCR
CBYP
DISR
FCM
FCOP
0
0
0
0
0
0
0
0
0
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
1
—
—
1
—
—
—
System Configuration Read:
Register (CONFIG) Write: ROMAD
See pages 88, 101,
—
108, 147 Reset:
$0040
Reserved
R
R
R
R
R
R
R
R
Reserved
R
R
R
R
R
R
R
R
MXGS1
W2SZ1
W2SZ0
0
0
W1SZ1
W1SZ0
0
0
0
0
0
0
0
W2A15
W2A14
W2A13
0
W1A15
W1A14
W1A13
0
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
to
$0055
Memory Mapping Size Read: MXGS2
$0056
Register (MMSIZ)(2) Write:
See pages 235, 243 Reset:
0
Memory Mapping Read:
Window Base Register Write:
$0057
(MMWBR)(2)
See page 236. Reset:
2. Not available on M68HC11KS devices
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 7 of 11)
M68HC11K Family
MOTOROLA
Technical Data
Operating Modes and On-Chip Memory
For More Information On This Product,
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71
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
$0058
$0059
Freescale Semiconductor, Inc...
$005A
$005B
Register Name
Memory Mapping Read:
Window 1 Control Write:
Register (MM1CR)(1)
See page 237. Reset:
Memory Mapping Read:
Window 2 Control Write:
Register (MM2CR)(1)
See page 237. Reset:
Chip Select Clock Read:
Stretch Register Write:
(CSCSTR)(1)
See page 249. Reset:
Chip Select Control Read:
Register (CSCTL)(1) Write:
See pages 240, 241 Reset:
General-Purpose Chip Read:
Select 1 Address Write:
$005C
Register (GPCS1A)(1)
See page 243. Reset:
General-Purpose Chip Read:
Select 1 Control Write:
$005D
Register (GPCS1C)(1)
See pages 244, 247 Reset:
General-Purpose Chip Read:
Select 2 Address Write:
$005E
Register (GPCS2A)(1)
See page 245. Reset:
General-Purpose Chip Read:
Select 2 Control Write:
$005F
Register (GPCS2C)(1)
See pages 245, 247 Reset:
Bit 7
6
5
4
3
2
1
Bit 0
0
X1A18
X1A17
X1A16
X1A15
X1A14
X1A13
0
0
0
0
0
0
0
0
0
0
X2A18
X2A17
X2A16
X2A15
X2A14
X2A13
0
0
0
0
0
0
0
0
0
IOSA
IOSB
GP1SA
GP1SB
GP2SA
GP2SB
PCSA
PCSB
0
0
0
0
0
0
0
0
IOEN
IOPL
IOCSA
IOSZ
GCSPR
PCSEN
PCSZA
PCSZB
0
0
0
0
0
1
0
0
G1A18
G1A17
G1A16
G1A15
G1A14
G1A13
G1A12
G1A11
0
0
0
0
0
0
0
0
G1DG2
G1DPC
G1POL
G1AV
G1SZA
G1SZB
G1SZC
G1SZD
0
0
0
0
0
0
0
0
G2A18
G2A17
G2A16
G2A15
G2A14
G2A13
G2A12
G2A11
0
0
0
0
0
0
0
0
0
G2DPC
G2POL
G2AV
G2SZA
G2SZB
G2SZC
G2SZD
0
0
0
0
0
0
0
0
CON34
CON12
PCKA2
PCKA1
0
PCKB3
PCKB2
PCKB1
0
0
0
0
0
0
0
0
PCLK4
PCLK3
PCLK2
PCLK1
PPOL4
PPOL3
PPOL2
PPOL1
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
1. Not available on M68HC11KS devices
Pulse Width Modulation Read:
Timer Clock Select Write:
$0060
Register (PWCLK)
See page 213. Reset:
Pulse Width Modulation Read:
Timer Polarity Register Write:
$0061
(PWPOL)
See page 215. Reset:
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 8 of 11)
Technical Data
72
M68HC11K Family
Operating Modes and On-Chip Memory
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Control Registers
Addr.
Register Name
Pulse Width Modulation Read:
Timer Prescaler Write:
$0062
Register (PWSCAL)
See page 215. Reset:
Freescale Semiconductor, Inc...
Pulse Width Modulation Read:
Timer Enable Register Write:
$0063
(PWEN)
See page 216. Reset:
Pulse Width Modulation Read:
Timer Counter 1 Write:
$0064
Register (PWCNT1)
See page 217. Reset:
Pulse Width Modulation Read:
Timer Counter 2 Write:
$0065
Register (PWCNT2)
See page 217. Reset:
Pulse Width Modulation Read:
Timer Counter 3 Write:
$0066
Register (PWCNT3)
See page 217. Reset:
Pulse Width Modulation Read:
Timer Counter 4 Write:
$0067
Register (PWCNT4)
See page 217. Reset:
Pulse Width Modulation Read:
Timer Period 1 Register Write:
$0068
(PWPER1)
See page 218. Reset:
Pulse Width Modulation Read:
Timer Period 2 Register Write:
$0069
(PWPER2)
See page 218. Reset:
Pulse Width Modulation Read:
Timer Period 3 Register Write:
$006A
(PWPER3)
See page 218. Reset:
Pulse Width Modulation Read:
Timer Period 4 Register Write:
$006B
(PWPER4)
See page 218. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
TPWSL
DISCP
0
0
PWEN4
PWEN3
PWEN2
PWEN1
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 9 of 11)
M68HC11K Family
MOTOROLA
Technical Data
Operating Modes and On-Chip Memory
For More Information On This Product,
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73
Freescale Semiconductor, Inc.
Operating Modes and On-Chip Memory
Addr.
Register Name
Pulse Width Modulation Read:
Timer Duty Cycle 1 Write:
$006C
Register (PWDTY1)
See page 219. Reset:
Freescale Semiconductor, Inc...
Pulse Width Modulation Read:
Timer Duty Cycle 2 Write:
$006D
Register (PWDTY2)
See page 219. Reset:
Pulse Width Modulation Read:
Timer Duty Cycle 3 Write:
$006E
Register (PWDTY3)
See page 219. Reset:
Pulse Width Modulation Read:
Timer Duty Cycle 4 Write:
$006F
Register (PWDTY4)
See page 219. Reset:
SCI Baud Rate Control Read:
$0070 Register High (SCBDH) Write:
See page 158. Reset:
SCI Baud Rate Control Read:
$0071 Register Low (SCBDL) Write:
See page 158. Reset:
SCI Control Register 1 Read:
$0072
(SCCR1) Write:
See page 160. Reset:
SCI Control Register 2 Read:
$0073
(SCCR2) Write:
See page 161. Reset:
$0074
$0075
$0076
SCI Status Register 1 Read:
(SCSR1) Write:
See page 162. Reset:
SCI Status Register 2 Read:
(SCSR2) Write:
See page 164. Reset:
SCI Data Register Read:
(SCDR) Write:
See page 165. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
BTST
BSPL
0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
0
0
0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
1
0
0
LOOPS
WOMS
0
M
WAKE
ILT
PE
PT
U
U
0
0
0
0
0
0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
R8
T8
0
0
0
0
0
0
RAF
Undefined after reset
= Unimplemented
R
= Reserved
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 10 of 11)
Technical Data
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Control Registers
Addr.
$0077
Register Name
SCI Data Register Read:
(SCDR) Write:
See page 165. Reset:
$0078
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Undefined after reset
Reserved
R
R
R
R
R
R
R
R
Reserved
R
R
R
R
R
R
R
R
PH7(1)
PH6(1)
PH5(1)
PH4(1)
PH3
PH2
PH1
PH0
to
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$007B
$007C
$007D
$007E
$007F
Port H Data Register Read:
(PORTH) Write:
See page 146. Reset:
Undefined after reset
Port H Data Direction Read: DDH7(1)
Register (DDRH) Write:
See page 146. Reset:
0
Port G Data Register Read:
(PORTG) Write:
See page 145. Reset:
Port G Data Direction Read:
Register (DDRG) Write:
See page 145. Reset:
PG7
DDH6(1)
DDH5(1)
DDH4(1)
DDH3
DDH2
DDH1
DDH0
0
0
0
0
0
0
0
PG6(1)
PG5(1)
PG4(1)
PG3(1)
PG2(1)
PG1(1)
PG0(1)
Undefined after reset
DDG7
DDG6(1)
DDG5(1)
DDG4 (1)
DDG3(1)
DDG2 (1)
DDG1(1)
DDG0(1)
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
1. Not available on M68HC11KS devices
U = Undefined
Figure 4-1. Register and Control Bit Assignments (Sheet 11 of 11)
M68HC11K Family
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4.4 System Initialization
Registers and bits that control initialization and the basic operation of the
MCU are protected against writes except under special circumstances.
Table 4-1 lists registers that can be written only once after reset or that
must be written within the first 64 cycles after reset.
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Table 4-1. Registers with Limited Write Access
Operating
Mode
SMOD = 0
SMOD = 1
Register
Address
Register Name
Must be Written
in First 64 Cycles
$x024
Timer interrupt mask 2 (TMSK2)
Bits [1:0], once only
Bits [7:2]
$x035
Block protect register (BPROT)
Clear bits, once only
Set bits only
$x037
EEPROM mapping register (INIT2)
No, bits [7:4], once
only
$x038
System configuration options 2
register (OPT2)
No, bit 4, once only
See OPT2
description
$x039
System configuration
options (OPTION)
Bits [5:4], bits [2:0],
once only
Bits [7:6], bit 3
$x03C
Highest priority I-bit interrupt
and miscellaneous (HPRIO)
$x03D
RAM and I/O map register (INIT)
$x024
Timer interrupt mask 2 (TMSK2)
—
All, set or clear
$x035
Block protect register (BPROT)
—
All, set or clear
$x037
EEPROM mapping register (INIT2)
—
Bits [7:4]
$x038
System configuration options 2
register (OPT2)
—
See OPT2
description
$x039
System configuration options
(OPTION)
—
All, set or clear
$x03C
Highest priority I-bit interrupt and
miscellaneous (HPRIO)
—
See HPRIO
description
$x03D
RAM and I/O map register (INIT)
—
All, set or clear
$x03F
System configuration register
(CONFIG)
—
See CONFIG
description
—
Yes, once only
Technical Data
76
Write
Anytime
—
See HPRIO
description
—
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Operating Modes
4.5 Operating Modes
The two normal modes of operation in the M68HC11K Family are:
•
Single-chip mode — All port pins available for input/output (I/O);
only on-board memory accessible
•
Expanded mode — Access to internal and external memory; 25
I/O pins used for interface
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The two special modes of operation are:
•
Bootstrap mode — A variation of single-chip mode; executes a
bootloader program in an internal bootstrap read-only memory
(ROM)
•
Test mode — A variation of the expanded mode used in
production testing; allows privileged access to internal resources
The logic levels applied at reset to input pins MODA and MODB
determine the operating mode. See 4.5.5 Mode Selection.
4.5.1 Single-Chip Mode
In single-chip mode, the MCU functions as a self-contained
microcontroller. In this mode, all address and data activity occurs within
the MCU. Ports B, C, F, G, and H are available for general-purpose I/O
because the external address and data buses are not required.
4.5.2 Expanded Mode
In expanded mode, the MCU uses ports B, C, F, and G to access a
64-Kbyte address space. This includes:
•
The same on-chip memory addresses used in single-chip mode
•
External memory
•
Peripheral devices
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Port B provides the high-order address byte (Addr[15:8]), port F the
low-order address byte (Addr[7:0]), port C the data bus (Data[7:0]), and
port G pin 7 the read/write line (R/W) which controls direction of data
flow.
Additionally, the E clock output can be used to synchronize external
decoders for enable signals.
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Expanded mode also enables these two special features available only
on the K4 Family devices:
1. Memory expansion uses port G[5:0] to increase the available
external address space to 1 Mbyte.
2. Four chip-select lines on port H[7:4] simplify selection of external
memory devices.
Both of these features are described in Section 11. Memory Expansion
and Chip Selects.
4.5.3 Bootstrap Mode
Resetting the MCU in special bootstrap mode selects a reset vector to a
special ROM bootloader program at addresses $BE00–$BFFF. The
bootloader program is used to download code, such as programming
algorithms, into on-chip RAM through the SCI. To do this:
1. Send a synchronization character (see Table 4-2) to the SCI
receiver at the specified baud rate.
2. Download up to 768 bytes (1 Kbyte for KS2) of program data,
which the CPU places into RAM starting at $0080 and also echoes
back on the TxD signal. The bootloader program ends the
download after the RAM is full or when the received data line is
idle for at least four character times. See Table 4-2.
When loading is complete, the MCU jumps to location $0080 and begins
executing the code. Interrupt vectors are directed to RAM, which allows
the use of interrupts through a jump table. The SCI transmitter requires
an external pullup resistor since it is part of port D, which the bootloader
configures for wired-OR operation.
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Table 4-2. Synchronization Character Selection
Baud Rate at E Clocks
Synchronization
Character
Timeout
Delay
2 MHz
3 MHz
4 MHz
$FF
4 characters
7812
11,718
15,624
$FF
4 characters
1200
1800
2400
$F0
4.9 characters
9600
14,400
19,200
$FD
13 characters
3906
5859
7812
For a detailed description of bootstrap mode, refer to the Motorola
application note entitled MC68HC11 Bootstrap Mode, document order
number AN1060/D.
4.5.4 Special Test Mode
Special test mode, a variation of the expanded mode, is used primarily
during Motorola’s internal production testing. However, for those devices
containing EPROM, it can be used to program the EPROM for program
calibration data in EEPROM and support emulation and debugging
during development.
For more detailed information, refer to 4.7.1 Programming the EPROM
with Downloaded Data.
4.5.5 Mode Selection
The operating mode is selected by applying the appropriate logic states
to the MODA and MODB pins during reset. MODA selects single-chip
mode (0) or expanded mode (1). A logic high on MODB selects normal
modes, and vectors are fetched from memory area $FFC0–$FFFF. A
logic low on MODB selects special modes, and reset vectors are fetched
from memory area $BFC0–$BFFF. Values reflecting the selected mode
are latched into the RBOOT, SMOD, and MDA bits of the highest priority
I-bit interrupt and miscellaneous register (HPRIO) on the rising edge of
RESET.
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Table 4-3 summarizes the inputs, modes selected, and register bits
latched. The HPRIO register is illustrated in Figure 4-2.
Table 4-3. Hardware Mode Select Summary
Control Bits in HPRIO
Latched at Reset
Inputs
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Mode
MODB
MODA
RBOOT
SMOD
MDA
1
0
Single-chip
0
0
0
1
1
Expanded
0
0
1
0
0
Special bootstrap
1
1
0
0
1
Special test
0
1
1
Address: $003C
Bit 7
Read:
6
RBOOT(1) SMOD(1)
5
4
3
2
1
Bit 0
MDA(1)
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
—
0
0
1
1
0
Write:
Reset:
—
—
1. The values of the RBOOT, SMOD, and MDA bits at reset depend on the mode during
initialization.
Figure 4-2. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
RBOOT — Read Bootstrap ROM Bit
In special modes, this bit enables the bootloader ROM
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and located in map at $BE00–$BFFF
In normal modes this bit is clear and cannot be written.
SMOD — Special Mode Select Bit
This bit reflects the inverse of the MODB input pin at the rising edge
of RESET. If MODB is low during reset, SMOD is set; if MODB is high
during reset, SMOD is cleared. Software can clear the SMOD bit, but
cannot set it. Thus, it is possible for software to change the operating
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mode from special to normal, but not vice versa. To switch from a
special mode to a normal mode, write to the access-limited registers
(see Table 4-1) before clearing SMOD.
0 = Normal mode operation in effect
1 = Special mode operation in effect
MDA — Mode Select A Bit
The mode select A bit reflects the status of the MODA input pin at the
rising edge of RESET. Software can change the MDA bit only while
the SMOD bit is set, effectively switching the operating mode between
special bootstrap and special test modes. Once the SMOD bit is clear,
the MODA bit is read-only and the operating mode cannot be changed
without going through a reset sequence.
0 = Normal single-chip or special bootstrap mode in effect
1 = Normal expanded or special test mode in effect
After RESET is released, the mode select pins revert to their alternate
functions, described in 2.9 Mode Selection, Instruction Cycle
Reference, and Standby Power (MODA/LIR and MODB/VSTBY), and
no longer influence the MCU operating mode.
4.6 Memory Map
The operating mode determines memory mapping and whether memory
is addressed on-chip or off-chip. Figure 4-3 and Figure 4-4 illustrate the
M68HC11K4 Family and M68HC11KS Family memory maps for each of
the four modes of operation. Memory locations for on-chip resources are
the same for both expanded and single-chip modes.
M68HC11K Family
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$0000
0000
$0380
007F
0080
EXTERNAL
EXTERNAL
128-BYTE REGISTER BLOCK
(CAN BE REMAPPED TO ANY 4-KBYTE
BOUNDARY BY THE INIT REGISTER)
768 BYTES RAM
(CAN BE REMAPPED TO ANY 4-KBYTE
BOUNDARY BY THE INIT REGISTER)
$0D80
$1000
037F
0D80
EXTERNAL
640 BYTES EEPROM
(CAN BE REMAPPED TO ANY 4-KBYTE
BOUNDARY BY THE INIT2 REGISTER)
EXTERNAL
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0FFF
$A000
A000
24-KBYTE ROM/
EPROM
(CAN BE
RE-MAPPED TO
$2000–$7FFF
BY THE CONFIG
REGISTER)(1),(2)
BE00
BFC0
BFFF
FFC0
$FFC0
FFFF
$FFFF
SINGLE
CHIP
EXPANDED BOOTSTRAP
BOOT ROM
(ONLY PRESENT IN
SPECIAL BOOT MODE)
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL MODES
INTERRUPT
VECTORS
FFFF
SPECIAL
TEST
Note 1.EPROM can be enabled in special test mode by setting the ROMON bit in the CONFIG register after reset.
Figure 4-3. M68HC11K4 Family Memory Map
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Memory Map
$0000
0000
$0480
007F
0080
EXTERNAL
EXTERNAL
128-BYTE REGISTER BLOCK
(CAN BE REMAPPED TO ANY 4K
BOUNDARY BY THE INIT REGISTER)
1.0-KBYTE RAM
(CAN BE REMAPPED TO ANY 4-KBYTE
BOUNDARY BY THE INIT REGISTER)
$0D80
$1000
047F
0D80
EXTERNAL
640-BYTE EEPROM
(CAN BE REMAPPED TO ANY 4-KBYTE
BOUNDARY BY THE INIT2 REGISTER)
EXTERNAL
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0FFF
$8000
8000
32K ROM/
EPROM
(CAN BE
RE-MAPPED TO
$0000–$7FFF
BY THE CONFIG
REGISTER)(1),(2)
BE00
BFC0
BFFF
FFC0
$FFC0
FFFF
$FFFF
SINGLECHIP
EXPANDED BOOTSTRAP
BOOT ROM
(ONLY PRESENT IN
SPECIAL BOOT MODE)
SPECIAL MODES
INTERRUPT
VECTORS
NORMAL MODES
INTERRUPT
VECTORS
FFFF
SPECIAL
TEST
Note: 1.EPROM can be enabled in special test mode by setting the ROMON bit in the CONFIG register after reset.
Figure 4-4. M68HC11KS2 Family Memory Map
Table 4-4 shows the default memory map addresses for the M68HC11K
Family devices.
Table 4-4. Default Memory Map Addresses
[7]11K4
[7]11KS2
Registers
$0000–$007F
$0000–$007F
RAM
$0080–$037F
$0080–$047F
EEPROM
$0D80–$0FFF
$0D80–$0FFF
ROM/EPROM
$A000–$FFFF
$8000–$FFFF
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4.6.1 Control Registers and RAM
Out of reset, the 128-byte register block is mapped to $0000 and the
768-byte RAM (1 Kbyte on the [7]11KS2) is mapped to $0080. Both the
register block and the RAM can be placed at any other 4-Kbyte boundary
($x000 and $x080, respectively) by writing the appropriate value to the
INIT register.
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Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 4-5. RAM and I/O Mapping Register (INIT)
NOTE:
INIT is writable once in normal modes and writable at any time in special
modes.
RAM[3:0] — RAM Map Position Bits
These four bits determine the position of RAM in the memory map by
specifying the upper hexadecimal digit of the RAM address. Refer to
Table 4-5.
REG[3:0] — Register Block Position Bits
These four bits determine the position of the register block in memory
by specifying the upper hexadecimal digit of the block address. Refer
to Table 4-6.
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Table 4-5. RAM Mapping
RAM[3:0]
Address(1)
Address(2)
0000
$0080–$037F(3)
$0000–$02FF
0001
$1080–$137F
$1000–$12FF
0010
$2080–$237F
$2000–$22FF
0011
$3080–$337F
$3000–$32FF
0100
$4080–$437F
$4000–$42FF
0101
$5080–$537F
$5000–$52FF
0110
$6080–$637F
$6000–$62FF
0111
$7080–$737F
$7000–$72FF
1000
$8080–$837F
$8000–$82FF
1001
$9080–$937F
$9000–$92FF
1010
$A080–$A37F
$A000–$A2FF
1011
$B080–$B37F
$B000–$B2FF
1100
$C080–$C37F
$C000–$C2FF
1101
$D080–$D37F
$D000–$D2FF
1110
$E080–$E37F
$E000–$E2FF
1111
$F080–$F37F
$F000–$F2FF
1. RAM[3:0] = REG[3:0]: On the [7]11KS2, RAM address range is $x080–$x47F.
2. RAM[3:0] ≠ REG[3:0]: On the [7]11KS2, RAM address range is $x000–$x37F.
3. Default locations out of reset
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Table 4-6. Register Mapping
REG[3:0]
Address
0000
$0000–$007F(1)
0001
$1000–$107F
0010
$2000–$207F
0011
$3000–$307F
0100
$4000–$407F
0101
$5000–$507F
0110
$6000–$607F
0111
$7000–$707F
1000
$8000–$807F
1001
$9000–$907F
1010
$A000–$A07F
1011
$B000–$B07F
1100
$C000–$C07F
1101
$D000–$D07F
1110
$E000–$E07F
1111
$F000–$F07F
1. Default locations out of reset.
Since the direct addressing mode accesses RAM more quickly and
efficiently than other addressing modes, many applications will find the
default locations of registers and on-board RAM at the bottom of
memory to be the most advantageous.
When RAM and the registers are both mapped to different 4-K
boundaries, the registers are mapped at $x000–$x07F, and RAM is
moved to $x000–$x2FF ($x000–x3FF for the [7]11KS2).
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The presence and location of the 24-Kbyte (EP)ROM on the [7]11K4 is
determined by two bits in the system configuration register (CONFIG).
The CONFIG register is a special EEPROM register (see Figure 4-6).
(EP)ROM is present in the memory map when the ROMON bit is set and
removed from the memory map when the bit is cleared. The default
location of this memory is $A000–$FFFF, but it can be moved to
$2000–$7FFF in expanded mode by clearing the ROMAD bit. Both bits
are set out of reset in single-chip mode.
•
On the [7]11KS2, (EP)ROM is 32 K, mapped to $8000–$FFFF by
default, and moved to $0000–$7FFF by clearing the ROMAD bit.
In special test mode, the ROMON bit is forced to 0, removing (EP)ROM
from the memory map.
4.6.3 EEPROM
The M68HC11K Family devices contain 640 bytes of EEPROM. It is
initially located at $0D80 after reset if it is enabled by the EEON bit in the
CONFIG register (see Figure 4-6). It can be relocated to any 4-K
boundary ($xD80) by writing to the EEPROM mapping register (INIT2)
(see Figure 4-7).
NOTE:
On the M68HC11K devices, the EEPROM can be mapped to where it
will contain the vector space.
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Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
—
—
—
—
Read:
Write:
Reset:
Figure 4-6. System Configuration Register (CONFIG)
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NOTE:
CONFIG is writable once in normal modes and writable at any time in
special modes.
ROMAD — ROM Address Mapping Control Bit
Set out of reset in single-chip mode
0 = (EP)ROM set at $2000–$7FFF;
$0000–$7FFF in [7]11KS2;
$0000–$BFFF in [7]11KS8
(expanded mode only)
1 = (EP)ROM set at $A000–$FFFF;
$8000–$FFFF in [7]11KS2;
$4000–$FFFF in [7]11KS8
ROMON — ROM/PROM Enable Bit
Set by reset in single-chip mode; cleared by reset in special test mode
0 = (EP)ROM removed from the memory map
1 = (EP)ROM present in the memory map
EEON — EEPROM Enable Bit
0 = 640-byte EEPROM disabled
1 = 640-byte EEPROM enabled
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Address: $0037
Bit 7
6
5
4
3
2
1
Bit 0
EE3
EE2
EE1
EE0
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 4-7. EEPROM Mapping Register (INIT2)
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NOTE:
INIT2 is writable once in normal modes and writable at any time in
special modes.
EE[3:0] — EEPROM Map Position Bits
These four bits determine the most-significant hexadecimal digit in
the address range of the EEPROM, as shown in Table 4-7.
Table 4-7. EEPROM Map
EE[3:0]
Location
0000
$0D80–$0FFF
0001
$1D80–$1FFF
0010
$2D80–$2FFF
0011
$3D80–$3FFF
0100
$4D80–$4FFF
0101
$5D80–$5FFF
0110
$6D80–$6FFF
0111
$7D80–$7FFF
1000
$8D80–$8FFF
1001
$9D80–$9FFF
1010
$AD80–$AFFF
1011
$BD80–$BFFF
1100
$CD80–$CFFF
1101
$DD80–$DFFF
1110
$ED80–$EFFF
1111
$FD80–$FFFF
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4.6.4 Bootloader ROM
The bootloader program occupies 512 bytes of bootstrap ROM at
addresses $BE00–$BFFF. It is active only in special modes when the
RBOOT bit in the HPRIO register is set.
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4.7 EPROM/OTPROM (M68HC711K4 and M68HC711KS2)
The M68HC711K4 devices include 24 Kbytes of on-chip EPROM
(OTPROM in non-windowed packages). The M68HC711KS2 has
32 Kbytes of EPROM.
The two methods available to program the EPROM are:
•
Downloading data through the serial communication interface
(SCI) in bootstrap or special test mode
•
Programming individual bytes from memory
Before proceeding with programming:
•
Ensure that the CONFIG register ROMON bit is set.
•
Ensure that the IRQ pin is pulled to a high level.
•
Apply 12 volts to the XIRQ/VPP pin.
Program the EPROM only at room temperature. Place an opaque label
over the quartz window on windowed parts after programming.
4.7.1 Programming the EPROM with Downloaded Data
The MCU can download EPROM data through the SCI while in the
special test or bootstrap modes. This can be done either with custom
software, also downloaded through the SCI, or with a built-in utility
program in bootstrap ROM. In either case, the 12-volt nominal
programming voltage must be present on the XIRQ/VPP pin.
To use the bootstrap ROM utility, download a 3-byte program consisting
of a single jump instruction to $BF00, the starting address of the resident
EPROM programming utility. The utility program sets the X and Y index
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EPROM/OTPROM (M68HC711K4 and M68HC711KS2)
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registers to default values, then receives data from an external host and
programs it into the EPROM. The value in the X index register
determines programming delay time. The value in the Y index register is
a pointer to the first address in EPROM to be programmed. The default
starting address is $8000 for the M68HC11KS2.
When the utility program is ready to receive programming data, it sends
the host a $FF character and waits for a reply. When the host sees the
$FF character, it sends the EPROM programming data, starting with the
first location in the EPROM array. After the MCU receives the last byte
to be programmed and returns the corresponding verification data, it
terminates the programming operation by initiating a reset. Refer to the
Motorola application note entitled MC68HC11 Bootstrap Mode,
document order number AN1060/D.
4.7.2 Programming the EPROM from Memory
In this method, software programs the EPROM one byte at a time. Each
byte is read from memory, then latched and programmed into the
EPROM using the EPROM programming control register (EPROG). This
procedure can be done in any operating mode.
Address: $002B
Bit 7
6
5
4
3
2
1
Bit 0
R
0
ELAT
EXCOL
EXROW
0
0
EPGM
0
0
0
0
0
0
0
0
R
= Reserved
Read:
Write:
Reset:
Figure 4-8. EPROM Programming Control Register (EPROG)
MBE — Multiple-Byte Program Enable Bit
MBE is for factory use only and is accessible only in special test
mode. When MBE is set, the MCU ignores address bit 5, so that bytes
with ADDR5 = 0 and ADDR5 = 1 both get programmed with the same
data.
0 = Normal programming
1 = Multiple-byte programming enabled
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ELAT — EPROM Latch Control Bit
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Setting ELAT latches the address and data of writes to the EPROM.
The EPROM cannot be read. ELAT can be read at any time. ELAT
can be written any time except when PGM = 1, which disables writes
to ELAT.
0 = EPROM address and data bus configured for normal reads.
EPROM cannot be programmed.
1 = EPROM address and data bus are configured for
programming. Address and data of writes to EPROM are
latched. EPROM cannot be read.
EXCOL — Select Extra Columns Bit
EXCOL is for factory use only and is accessible only in special test
mode. When EXCOL equals 1, extra columns can be accessed at
bit 7 and bit 0. Addresses use bits [11:5]. Bits [4:1] are ignored.
0 = User array selected
1 = Extra columns selected and user array disabled
EXROW — Select Extra Rows Bit
EXROW is for factory use only and is only accessible in special test
mode. When EXROW equals 1, two extra rows are available.
Addresses use bits [5:0]. Bits [11:6] are ignored.
0 = User array selected
1 = Extra rows selected and user array is disabled
EPGM — EPROM Programming Enable Bit
EPGM applies programming voltage (VPP) to the EPROM. EPGM can
be read at any time. EPGM can be written only when ELAT = 1.
0 = Programming voltage to EPROM array is disconnected
1 = Programming voltage to EPROM array is connected; ELAT
cannot be changed.
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EEPROM and the CONFIG Register
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This procedure programs one byte into EPROM. On entry, accumulator
A contains the byte of data to be programmed and X contains the target
EPROM address.
EPROG LDAB
STAB
#$20
$002B
STAA
LDAB
STAB
$0,X
#$21
$002B
JSR
CLR
DLYEP
$002B
Set ELAT bit to enable EPROM latches.
(EPGM must be 0.)
Store data to EPROM address
Set EPGM bit with ELAT=1
to enable EPROM programming voltage
Delay 1-2 ms
Turn off programming voltage and set to
READ mode
4.8 EEPROM and the CONFIG Register
The 640-byte on-board EEPROM is enabled by the EEON bit in the
CONFIG register and located on a 4-K boundary determined by the
INIT2 register (4.6.3 EEPROM). An internal charge pump supplies the
programming voltage for the EEPROM, eliminating the need for an
external high-voltage supply.
When appropriate bits in the BPROT register are cleared, the PPROG
register controls programming and erasing the EEPROM. The PPROG
register can be read or written at any time, but logic enforces defined
programming and erasing sequences to prevent unintentional changes
to EEPROM data. When the EELAT bit in the PPROG register is cleared,
the EEPROM can be read as if it were a ROM.
The clock source driving the charge pump is software selectable. When
the clock select (CSEL) bit in the OPTION register is 0, the E clock is
used; when CSEL is 1, an on-chip resistor-capacitor (RC) oscillator is
used.
The EEPROM programming voltage power supply voltage to the
EEPROM array is not enabled until there has been a write to PPROG
with EELAT set and PGM cleared. This must be followed by a write to a
valid EEPROM location or to the CONFIG address, and then a write to
PPROG with both the EELAT and EPGM bits set. Any attempt to set
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both EELAT and EPGM during the same write operation results in
neither bit being set.
4.8.1 EEPROM Registers
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This section describes the EEPROM registers:
•
Block protect register (BPROT)
•
EEPROM programming control register (PPROG)
•
System configuration options register (OPTION)
The EEPROM programming control register (PPROG) controls
programming and erasing. The block protect register (BPROT) can
prevent inadvertent writes to (or erases of) blocks of EEPROM and the
CONFIG register. The CSEL bit in the system configuration options
register (OPTION) selects an on-chip oscillator clock for programming
and erasing when operating at frequencies below 1 MHz.
4.8.1.1 EEPROM Programming Control Register
Address: $003B
Bit 7
6
ODD
EVEN
0
0
Read:
5
4
3
2
1
Bit 0
BYTE
ROW
ERASE
EELAT
EEPGM
0
0
0
0
0
LVPI
Write:
Reset:
0
= Unimplemented
Figure 4-9. EEPROM Programming Control Register (PPROG)
ODD — Program Odd Rows in Half of EEPROM Bit
This bit is accessible only in test mode.
EVEN — Program Even Rows in Half of EEPROM Bit
This bit is accessible only in test mode.
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EEPROM and the CONFIG Register
LVPI — Low-Voltage Programming Inhibit Bit
LVPI is a read-only bit which always reads as 0. The functionality of
this status bit was changed from early versions of the M68HC11K
Family. The low-voltage programming inhibit function is disabled on
all recent devices.
BYTE — Byte/Other EEPROM Erase Mode Bit
0 = Row or bulk erase mode used
1 = Erase only one byte of EEPROM
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ROW — Row/All EEPROM Erase Mode Bit
0 = All 640 bytes of EEPROM erased
1 = Erase only one 16-byte row of EEPROM
NOTE:
ROW is valid only when BYTE = 0.
The BYTE and ROW bits work together to determine the scope of
erasing, as shown in Table 4-8.
Table 4-8. Scope of EEPROM Erase
BYTE
ROW
Action
0
0
Bulk erase; all 640 bytes
0
1
Row erase; 16 bytes
1
0
Byte erase
1
1
Byte erase
ERASE — Erase/Normal Control for EEPROM Bit
0 = Normal read or program mode
1 = Erase mode
EELAT — EEPROM Latch Control Bit
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or
erasing
EEPGM — EEPROM Program Command Bit
0 = Program or erase voltage switched off to EEPROM array
1 = Program or erase voltage switched on to EEPROM array
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4.8.1.2 Block Protect Register
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This register prevents inadvertent writes to both the CONFIG register
and EEPROM. The active bits in this register are initialized to 1 out of
reset and can be cleared only during the first 64 E-clock cycles after
reset in the normal modes. When these bits are cleared, the associated
EEPROM section and the CONFIG register can be programmed or
erased. EEPROM is only visible if the EEON bit in the CONFIG register
is set. The bits in the BPROT register can be written to 1 at any time to
protect EEPROM and the CONFIG register. In test or bootstrap modes,
write protection is inhibited and BPROT can be written repeatedly.
Address: $0035
Bit 7
6
5
4
3
2
1
Bit 0
BULKP
LVPEN
BPRT4
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 4-10. Block Protect Register (BPROT)
BULKP — Bulk Erase of EEPROM Protect Bit
0 = EEPROM can be bulk erased normally.
1 = EEPROM cannot be bulk or row erased.
LVPEN — Low-Voltage Programming Protect Enable Bit
The functionality of LVPEN/LVPI was changed from earlier versions
of the M68HC11K Family. Setting this bit has no effect on the LVPI bit
in the PPROG register.
0 = Low-voltage programming inhibit (LVPI) for EEPROM disabled
1 = Low-voltage programming inhibit (LVPI) for EEPROM disabled
BPRT[4:0] — Block Protect Bits for EEPROM Bits, see Table 4-9
0 = Protection disabled for associated block
1 = Protection enabled for associated block
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EEPROM and the CONFIG Register
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Table 4-9. EEPROM Block Protect
Bit Name
Block Protected
Block Size
BPRT0
$xD80–$xD9F
32 bytes
BPRT1
$xDA0–$xDDF
64 bytes
BPRT2
$xDE0–$xE5F
128 bytes
BPRT3
$xE60–$xF7F
288 bytes
BPRT4
$xF80–$xFFF
128 bytes
4.8.1.3 System Configuration Options Register
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE
DLY(1)
CME
FCME(1)
CR1(1)
CR0(1)
0
0
0
1
0
0
0
0
Read:
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in
special modes.
Figure 4-11. System Configuration Options Register (OPTION)
CSEL — Clock Select Bit
Selects the built-in RC clock source for on-chip EEPROM and A/D
charge pumps. This clock should be used when the E clock falls
below 1 MHz.
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
4.8.2 EEPROM Programming
To write to any EEPROM byte, it must first be erased, for instance, all of
its bits must be set. A single byte, a row, or the entire EEPROM in a
single procedure can be erased by adjusting the BYTE and ROW bits in
PPROG. Once the targeted area has been erased, each byte can be
individually written.
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The procedures for both writing and erasing involve these five steps:
1. Set the EELAT bit in PPROG. If erasing, also set the ERASE bit
and the appropriate BYTE and ROW bits.
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2. Write data to the appropriate EEPROM address. If erasing, any
data will work. To erase a row, write to any location in the row. To
erase the entire EEPROM, write to any location in the array. This
step is done before applying the programming voltage because
setting the EEPGM bit inhibits writes to EEPROM addresses.
3. Set the EEPGM bit in PPROG, keeping EELAT set. If erasing,
also set the ERASE bit and the appropriate BYTE and ROW bits.
4. Delay for 10 ms.
5. Clear the PPROG register to turn off the high voltage and
reconfigure the EEPROM address and data buses for normal
operation.
The following examples demonstrate programming a single EEPROM
byte, erasing the entire EEPROM, erasing a row (16 bytes), and erasing
a single byte.
4.8.2.1 EEPROM Programming
On entry, accumulator A contains the data to be written and X points to
the address to be programmed.
EEPROG
LDAB
STAB
#$02
$003B
STAA
LDAB
STAB
$0,X
#$03
$002B
JSR
CLR
DLY10
$003B
Set EELAT bit to enable EEPROM
latches.
Store data to EPROM address
Set EPGM bit with ELAT=1
to enable EEPROM programming voltage
Delay 10 ms
Turn off programming voltage and set
to READ mode
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EEPROM and the CONFIG Register
4.8.2.2 EEPROM Bulk Erase
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BULKE
LDAB
STAB
STAA
LDAB
STAB
#$06
$003B
$0,X
#$07
$002B
JSR
CLR
DLY10
$003B
LDAB
STAB
STAA
#$07
$003B
$0,X
LDAB
STAB
#$07
$002B
JSR
CLR
DLY10
$003B
LDAB
STAB
STAA
#$16
$003B
$0,X
LDAB
STAB
#$17
$002B
JSR
CLR
DLY10
$003B
Set EELAT and ERASE.
Store any data to any EEPROM address
Set EEPGM bit as well
to enable EEPROM programming voltage
Delay 10 ms
Turn off programming voltage and set
to READ mode
4.8.2.3 EEPROM Row Erase
ROWE
Set EELAT, ERASE and ROW.
Store any data to any EEPROM address
in row
Set EEPGM bit as well
to enable EEPROM programming voltage
Delay 10 ms
Turn off programming voltage and set
to READ mode
4.8.2.4 EEPROM Byte Erase
BYTEE
Set EELAT, ERASE and BYTE.
Store any data to targeted EEPROM
address
Set EEPGM bit as well
to enable EEPROM programming voltage
Delay 10 ms
Turn off programming voltage and set
to READ mode
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4.8.3 CONFIG Register Programming
The CONFIG register is implemented with EEPROM cells, so EEPROM
procedures are required to change it. CONFIG can be programmed or
erased (including byte erase) while the MCU is operating in any mode,
provided that PTCON in BPROT is clear.
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Address: $0035
Bit 7
6
5
4
3
2
1
Bit 0
BULKP
LVPEN
BPRT4
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
1
1
1
1
1
1
1
1
Read:
Write:
Reset:
Figure 4-12. Block Protect Register (BPROT)
PTCON — Protect for CONFIG Bit
0 = CONFIG register can be programmed or erased normally.
1 = CONFIG register cannot be programmed or erased.
To change the value in the CONFIG register, complete this procedure.
Do not initiate a reset until the procedure is complete.
•
Erase the CONFIG register.
•
Program the new value to the CONFIG address.
•
Initiate reset.
4.8.4 RAM and EEPROM Security
The NOSEC bit in the CONFIG register enables and disables an optional
security feature which protects the contents of EEPROM and RAM from
unauthorized access. This is done by restricting operation to single-chip
modes, preventing the memory locations from being monitored
externally. Single-chip modes do not allow visibility of the internal
address and data buses. Resident programs, however, have unlimited
access to the internal EEPROM and RAM and can read, write, or
transfer the contents of these memories.
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EEPROM and the CONFIG Register
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
1
—
—
—
Read:
Write:
Reset:
Figure 4-13. System Configuration Register (CONFIG)
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NOTE:
CONFIG is writable once in normal modes and writable at any time in
special modes.
NOSEC — RAM and EPROM Security Disabled Bit
0 = Enable security
1 = Disable security
M68HC11K Family devices are normally manufactured with NOSEC set
and the security option unavailable. However, on special request, a
mask option is selected during fabrication that enables the security
mode. The secure mode can be invoked on these parts by clearing
NOSEC. Contact a Motorola representative for information on the
availability of this feature.
The bootstrap program performs this sequence when the security
feature is present, enabled, and bootstrap mode is selected:
1. Output $FF, all 1s, on the SCI.
2. Clear the BPROT register by turning block protect off.
3. If the EEPROM is enabled, erase the EEPROM.
4. Verify that the EEPROM is erased. If EEPROM is not erased,
begin sequence again.
5. Write $FF, all 1s, to the entire block of RAM.
6. Erase the CONFIG register.
If all of the operations are successful, the bootload process continues as
if the device was never secured.
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4.9 XOUT Pin Control
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The XOUT pin provides a buffered XTAL signal to synchronize external
devices with the MCU. It is enabled by the CLKX bit in the system
configuration (CONFIG) register. The frequency of XOUT can be divided
by one-of-four divisors selected by the XDV[1:0] bits in the system
configuration options 2 (OPT2) register. The XOUT pin is not configured
on all packages. Refer to the pin assignments in Section 2. Pin
Description.
4.9.1 System Configuration Register
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
1
—
—
—
Read:
Write:
Reset:
Figure 4-14. System Configuration Register (CONFIG)
Writable once in normal modes and writable at any time in special modes
CLKX — XOUT Clock Enable Bit
The CLKX bit is a switch that enables a buffered clock running at the
same frequency as a referenced crystal. This buffered clock is
intended to synchronize external devices with the MCU.
0 = The XOUT pin is disabled.
1 = The X clock is driven out on the XOUT pin.
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XOUT Pin Control
4.9.2 System Configuration Options 2 Register
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
STRCH(1)
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
Read:
Write:
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Reset:
1. Not available on M68HC11K devices
Figure 4-15. System Configuration Options 2 Register (OPT2)
XDV[1:0] — XOUT Clock Divide Select Bits
These two bits select the divisor for the XOUT clock frequency, as
shown in Table 4-10. The divisor is set to 1 out of reset
(XOUT = XTAL). It takes a maximum of 16 cycles after writing these
bits for XOUT to stabilize. The phase relationship between XOUT and
XTAL cannot be predicted.
Table 4-10. XOUT Frequencies
XDV[1:0]
EXTAL
Divided By
Frequency at
EXTAL = 8 MHz
Frequency at
EXTAL = 12 MHz
Frequency at
EXTAL = 16 MHz
Frequency at
EXTAL = 16 MHz
0
0
1
8 MHz
12 MHz
16 MHz
20 MHz
0
1
4
2 MHz
3 MHz
4 MHz
5 MHz
1
0
6
1.33 MHz
2 MHz
2.67 MHz
3.33 MHz
1
1
8
1 MHz
1.5 MHz
2 MHz
2.5 MHz
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Section 5. Resets and Interrupts
5.1 Contents
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5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3
Sources of Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3.1
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.2
External Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.3.3
Computer Operating Properly (COP) System . . . . . . . . . . 107
5.3.3.1
System Configuration Register . . . . . . . . . . . . . . . . . . . 108
5.3.3.2
System Configuration Options Register . . . . . . . . . . . . . 109
5.3.3.3
Arm/Reset COP Timer Circuitry Register. . . . . . . . . . . . 110
5.3.4
Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.4.1
System Configuration Options Register . . . . . . . . . . . . . 111
5.3.4.2
System Configuration Options Register 2 . . . . . . . . . . . 112
5.4
Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.5
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5.1
Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.1.1
Non-Maskable Interrupt Request (XIRQ) . . . . . . . . . . . . 120
5.5.1.2
Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.5.1.3
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5.2
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.6
Reset and Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.7
Reset and Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . .123
5.8
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.8.1
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.8.2
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
5.8.3
Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
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5.2 Introduction
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When a reset or interrupt occurs, the microcontroller (MCU) retrieves the
starting address of a program or interrupt routine from a vector table in
memory and loads it in the program counter. A reset immediately stops
execution of the current instruction and reinitializes the control registers.
An interrupt preserves the current program status, performs an interrupt
service routine, and resumes operation as if there had been no
interruption.
5.3 Sources of Resets
The four sources of reset are:
NOTE:
•
Power-on reset (POR)
•
External reset (RESET)
•
Computer operating properly (COP) system
•
Clock monitor
Power-on reset and external reset share the same interrupt vectors.
The CPU fetches a restart vector during the first three clock cycles after
reset and begins executing instructions. Vector selection is based on the
type of reset and operating mode, as shown in Table 5-1.
Table 5-1. Reset Vectors
Operating
Mode
POR or RESET
Clock Monitor
COP Watchdog
Normal
$FFFE and $FFFF
$FFFC and $FFFD
$FFFA and $FFFB
Test or bootstrap
$BFFE and $BFFF
$BFFC and $BFFD
$BFFA and $BFFB
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Sources of Resets
5.3.1 Power-On Reset (POR)
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A positive transition on VDD generates a POR, which is used only for
power-up conditions. POR cannot be used to detect drops in power
supply voltages. The CPU delays 4064 internal clock cycles after the
oscillator becomes active to allow the clock generator to stabilize, then
checks the RESET pin. If RESET is at logical 0, the CPU remains in the
reset condition until the RESET pin goes to logical 1.
5.3.2 External Reset (RESET)
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic 1 in less than two
E-clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for four E-clock cycles, then released. Two E-clock cycles later, it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
NOTE:
It is not advisable to connect an external resistor capacitor (RC)
power-up delay circuit to the reset pin of M68HC11 devices because the
circuit charge time constant can cause the device to misinterpret the
type of reset that occurred.
5.3.3 Computer Operating Properly (COP) System
The MCU includes a COP system to help protect against software
failures. When the COP is enabled, software periodically reinitializes a
free-running watchdog timer before it times out and resets the system.
Such a system reset indicates that a software error has occurred.
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Three registers are involved in COP operation:
NOTE:
•
The CONFIG register contains a bit which determines whether the
COP system is enabled or disabled.
•
The OPTION register contains two bits which determine the COP
timeout period.
•
The COPRST register must be written by software to reset the
watchdog timer.
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
5.3.3.1 System Configuration Register
In normal modes, COP is enabled out of reset and does not depend on
software action. To disable the COP system, set the NOCOP bit in the
CONFIG register (see Figure 5-1). In special test and bootstrap
operating modes, the COP system is initially inhibited by the disable
resets (DISR) control bit in the TEST1 register. The DISR bit can
subsequently be written to 0 to enable COP resets.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
1
—
—
—
Read:
Write:
Reset:
Figure 5-1. System Configuration Register (CONFIG)
NOTE:
CONFIG is writable once in normal modes and writable at any time in
special modes.
NOCOP — COP System Disable Bit
0 = COP enabled
1 = COP disabled
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Sources of Resets
5.3.3.2 System Configuration Options Register
Two bits in the OPTION register select one of four values for the COP
timer.
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE
DLY
CME
FCME
CR1
CR0
0
0
0
1
0
0
0
0
Read:
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Write:
Reset:
Figure 5-2. System Configuration Options Register (OPTION)
CR[1:0] — COP Timer Rate Select Bits
The MCU derives the counter for the COP timer by dividing the
system E clock by 215 and applying a further scaling factor selected
by CR[1:0] as shown in Table 5-2. After reset, these bits are 0, and
that condition selects the fastest timeout period.
NOTE:
In normal operating modes, these bits can be written only once within 64
bus cycles after reset.
Table 5-2. COP Timeout
EXTAL Frequencies
EXTAL Freq.
8.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
24.0 MHz
Other EXTAL
E Clock Freq.
2.0 MHz
3.0 MHz
4.0 MHz
5.0 MHz
6.0 MHz
EXTAL ÷ 4
COP Timeout
Timeout
Control Bits
SPR[2:0]
0/+16.384 ms
0/+10.923 ms
0/+8.192 ms
0/+6.544 ms
0/+5.461 ms
0/+215 ÷ E
00
16.384 ms
10.923 ms
8.192 ms
6.554 ms
5.461 ms
215 ÷ E
01
65.536 ms
43.691 ms
32.768 ms
26.214 ms
21.845 ms
217 ÷ E
10
262.144 ms
174.763 ms
131.072 ms
104.858 ms
87.381 ms
219 ÷ E
11
1.049 sec
699.051 ms
524.288 ms
419.430 ms
349.525 ms
221 ÷ E
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5.3.3.3 Arm/Reset COP Timer Circuitry Register
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
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Figure 5-3. Arm/Reset COP Timer Circuitry Register (COPRST)
To prevent a COP reset, this sequence must be completed:
1. Write $55 to COPRST to arm the COP timer clearing mechanism.
2. Write $AA to COPRST to clear the COP timer.
NOTE:
Performing instructions between these two steps is possible as long as
both steps are completed in the correct sequence before the timer times
out.
5.3.4 Clock Monitor Reset
The clock monitor can serve as a backup for the COP system. Its circuit
is based on an internal RC time delay. If no MCU clock edges are
detected within this RC time delay, the clock monitor generates a system
reset. Because the COP needs a clock to function, it is disabled when
the clocks stop. Thus, the clock monitor system can detect clock failures
not detected by the COP system.
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Sources of Resets
5.3.4.1 System Configuration Options Register
The clock monitor function is enabled or disabled by the CME control bit
in the OPTION register (see Figure 5-4). The FCME bit in OPTION
overrides CME and enables the clock monitor until the next reset.
Address: $0030
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE
DLY
CME
FCME
CR1
CR0
0
0
0
1
0
0
0
0
Read:
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Write:
Reset:
Figure 5-4. System Configuration Options Register (OPTION)
NOTE:
In normal operating modes, these bits can be written only once within 64
bus cycles after reset.
CME — Clock Monitor Enable Bit
This control bit can be read or written at any time and controls whether
or not the internal clock monitor circuit triggers a reset sequence when
the system clock is slow or absent. When it is clear, the clock monitor
circuit is disabled. When it is set, the clock monitor circuit is enabled.
Reset clears the CME bit.
0 = Clock monitor disabled
1 = Clock monitor enabled
FCME — Force Clock Monitor Enable Bit
0 = Clock monitor follows the state of the CME bit.
1 = Clock monitor is enabled until the next reset.
Semiconductor wafer processing causes variations of the RC timeout
values between individual devices. An E-clock frequency below 10 kHz
generates a clock monitor error. An E-clock frequency of 200 kHz or
more prevents clock monitor errors. Using the clock monitor function
when the E clock is below 200 kHz is not recommended.
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5.3.4.2 System Configuration Options Register 2
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
STRCH(1)
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
Read:
Write:
Reset:
1. Not available on M68HC11K devices
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Figure 5-5. System Configuration Options Register 2 (OPT2)
LIRDV — LIR Driven Bit
This bit allows power savings in expanded modes by turning off the
LIR output (it has no meaning in single-chip or bootstrap modes). The
LIR pin is driven low to indicate that execution of an instruction has
begun. To detect consecutive instructions in a high-speed application,
this signal drives high for a quarter of a cycle to prevent false
triggering. An external pullup is required in expanded modes, while a
hardwired VSS connection is possible in single-chip modes. LIRDV is
reset to 0 in single-chip modes and to 1 in expanded modes.
1 = Enable LIR push-pull drive
0 = LIR not driven high on MODA/LIR pin
CWOM — Port C Wired-OR Mode Bit
For detailed information, refer to Section 6. Parallel Input/Output.
1 = Port C outputs are open drain.
0 = Port C operates normally.
STRCH — Stretch External Accesses Bit
When this bit is set, off-chip accesses of selected addresses are
extended by one E-clock cycle to allow access to slow peripherals.
The E clock stretches externally, but the internal clocks are not
affected, so that timers and serial systems are not corrupted. The
state of the ROMAD bit in the CONFIG register determines which
address range is affected.
1 = Off-chip accesses are selectively extended by one E-clock
cycle.
0 = Normal operation
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Sources of Resets
NOTE:
STRCH is cleared on reset; therefore, a program cannot execute out of
reset in a slow external ROM.
To use the STRCH feature, ROMON must be set on reset so that the
device starts with internal ROM included in the memory map. STRCH
should then be set.
STRCH has no effect in single-chip and bootstrap modes.
NOTE:
STRCH is not available on M68HC11K devices.
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IRVNE — Internal Read Visibility/Not E Bit
IRVNE can be written once in any user mode. In expanded modes,
IRVNE determines whether IRV is on or off (but has no meaning in
user expanded secure mode, as IRV must be disabled). In special test
mode, IRVNE is reset to 1. In normal modes, IRVNE is reset to 0.
1 = Data from internal reads is driven out of the external data bus.
0 = No visibility of internal reads on external bus
In single-chip modes, this bit determines whether the E clock drives
out from the chip.
1 = E pin is driven low.
0 = E clock is driven out from the chip.
Refer to Table 5-3 for a summary of the operation immediately
following reset.
Table 5-3. IRVNE Operation After Reset
IRVNE
after
Reset
E Clock
after
Reset
IRV
after
Reset
IRVNE
Affects
Only
IRVNE
Can Be
Written
Single-chip
0
On
Off
E
Once
Expanded
0
On
Off
IRV
Once
Bootstrap
0
On
Off
E
Unlimited
Special test
1
On
On
IRV
Unlimited
Mode
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LSBF — Least Significant Bit (LSB) First Enable Bit
For detailed information, refer to Section 8. Serial Peripheral
Interface (SPI).
1 = Data is transferred LSB first.
0 = Data is transferred MSB (most significant bit) first.
SPR2 — SPI Clock Rate Selected Bit
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This bit adds a divide-by-four to the SPI clock chain. For detailed
information, refer to Section 8. Serial Peripheral Interface (SPI).
XDV[1:0] — XOUT Clock Divide Select Bits
These bits control the frequency of the clock driven out of the
XOUT pin, if enabled by the CLKX bit on the CONFIG register. See
Table 5-4
Table 5-4. XOUT Clock Divide Select
XDV
[1:0]
XOUT = EXTAL
Divided By
Frequency at
EXTAL =
8 MHz
Frequency at
EXTAL =
12 MHz
Frequency at
EXTAL =
16 MHz
0 0
1
8 MHz
12 MHz
16 MHz
0 1
4
2 MHz
3 MHz
4 MHz
1 0
6
1.3 MHz
2 MHz
2.7 MHz
1 1
8
1 MHz
1.5 MHz
2 MHz
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Effects of Reset
5.4 Effects of Reset
When the MCU recognizes a reset condition, it forces the CPU registers
and control bits to established initial states. These in turn force the
on-chip peripheral systems to known startup states, as described here.
•
Central processor unit (CPU)
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– The stack pointer and other CPU registers are indeterminate
immediately after reset, except for three bits in the condition
code register (CCR).
– The X and I interrupt mask bits are set to mask any interrupt
requests, and the S bit in the CCR is set to inhibit the stop
mode.
•
Memory map
– The INIT register is initialized to $00, putting the control
registers at locations $0000–$007F.
– The 1.5 Kbytes of RAM are at locations $0080–$067F except
for the M68HC11KS Family, which has 1 Kbytes of RAM at
locations $0080–$047F.
– The INIT2 register is $00, locating the EEPROM at
$0D80–$0FFF.
•
Timer
– The timing system is initialized to a count of $0000.
– The prescaler bits are cleared, and all output compare
registers are initialized to $FFFF.
– All input capture registers are indeterminate after reset.
– The output compare 1 mask (OC1M) register is cleared so that
successful OC1 compares do not affect any input/output (I/O)
pins. The other four output compares are configured so that
they do not affect any I/O pins on successful compares.
– All input capture edge-detector circuits are configured for
capture disabled operation.
– The timer overflow interrupt flag and all eight timer function
interrupt flags are cleared.
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– All nine timer interrupts are disabled because their mask bits
have been cleared.
– The I4/O5 bit in the PACTL register is cleared to configure the
I4/O5 function as OC5; however, the OM5:OL5 control bits in
the TCTL1 register are clear so OC5 does not control the PA3
pin.
•
Real-time interrupt (RTI)
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– The RTI enable bit in TMSK2 is cleared, masking automatic
hardware interrupts.
– The rate control bits are cleared after reset and can be
initialized by software before the RTI system is enabled.
•
Pulse accumulator
– The pulse accumulator system is disabled at reset.
– The PAI input pin defaults to a general-purpose input pin
(PA7).
•
Computer operating properly (COP) watchdog system
– The COP watchdog system is enabled if the NOCOP control
bit in the CONFIG register is clear and disabled if NOCOP is
set.
– The OPTION register’s CR[1:0] bits are cleared, setting the
COP rate for the shortest duration timeout.
•
Serial communications interface (SCI)
– At reset, the SCI baud rate control register (7.9.1 SCI Baud
Rate Control Register) is initialized to $0004.
– All transmit and receive interrupts are masked and both the
transmitter and receiver are disabled so the port pins default to
being general-purpose I/O lines.
– The SCI frame format is initialized to an 8-bit character size.
– The send break and receiver wake-up functions are disabled.
– The TDRE and TC status bits in the SCI status register are
both set, indicating that there is no transmit data in either the
transmit data register or the transmit serial shift register.
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Interrupts
– The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related
status bits are cleared.
•
Serial peripheral interface (SPI)
– The SPI system is disabled by reset.
– The port pins associated with this function default to being
general-purpose I/O lines.
•
Analog-to-digital (A/D) converter
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– The ADPU bit in the OPTION register is cleared, disabling the
A/D system.
– The conversion complete flag in the ADCTL register is also
cleared.
•
System
– The external IRQ pin has the highest I-bit interrupt priority
because PSEL[4:0] in the HPRIO register are initialized with
the value %00110 (where % indicates a binary value).
– The RBOOT, SMOD, and MDA bits in the HPRIO register
reflect the status of the MODB and MODA inputs at the rising
edge of reset.
– The IRQ pin is configured for level-sensitive operation for
wired-OR systems.
– The DLY control bit in the OPTION register is set, enabling
oscillator startup delay after recovery from stop mode.
– The clock monitor system is disabled because the CME and
FCME bits in the OPTION register are cleared.
5.5 Interrupts
The MCU has 18 interrupt vectors that support 22 interrupt sources. The
19 maskable interrupts are generated by on-chip peripheral systems.
They are recognized when the I bit in the CCR is clear. The three
non-maskable interrupt sources are illegal opcode trap, software
interrupt, and XIRQ pin. Table 5-5 lists the interrupt sources and vector
assignments for each source.
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Table 5-5. Interrupt and Reset Vector Assignments
CC Register
Mask
Local
Mask
Reserved
—
—
SCI serial system:
• SCI transmit complete
• SCI transmit data register empty
• SCI idle line detect
• SCI receiver overrun
• SCI receive data register full
I bit
FFD8, D9
SPI serial transfer complete
I bit
SPIE
FFDA, DB
Pulse accumulator input edge
I bit
PAII
FFDC, DD
Pulse accumulator overflow
I bit
PAOVI
FFDE, DF
Timer overflow
I bit
TOI
FFE0, E1
Timer input capture 4/output compare 5
I bit
I4/O5I
FFE2, E3
Timer output compare 4
I bit
OC4I
FFE4, E5
Timer output compare 3
I bit
OC3I
FFE6, E7
Timer output compare 2
I bit
OC2I
FFE8, E9
Timer output compare 1
I bit
OC1I
FFEA, EB
Timer input capture 3
I bit
IC3I
FFEC, ED
Timer input capture 2
I bit
IC2I
FFEE, EF
Timer input capture 1
I bit
IC1I
FFF0, F1
Real-time interrupt
I bit
RTII
FFF2, F3
IRQ (external pin)
I bit
None
FFF4, F5
XIRQ pin
X bit
None
FFF6, F7
Software interrupt
None
None
FFF8, F9
Illegal opcode trap
None
None
FFFA, FB
COP failure
None
NOCOP
FFFC, FD
Clock monitor fail
None
CME
FFFE, FF
RESET
None
None
Vector Address
FFC0, C1 — FFD4, D5
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FFD6, D7
Interrupt Source
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TCIE
TIE
ILIE
RIE
RIE
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Interrupts
Many interrupt sources set associated flag bits when interrupts occur.
These flags are usually cleared during the course of normal interrupt
service. For example, the normal response to an RDRF interrupt request
in the SCI is to read the SCI status register to check for receive errors,
then read the received data from the SCI data register. It is precisely
these two steps which clear RDRF, so no extra steps are required.
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An interrupt can be recognized at any time after it is enabled by its local
mask, if any, and by the global mask bit in the CCR. The CPU responds
to an interrupt at the completion of the instruction being executed. Since
the number of clock cycles in the instruction varies, so does interrupt
latency. The CPU pushes the contents of its registers onto the stack in
the order shown in Table 5-6. After the CCR value is stacked, the I bit is
set (and the X bit as well if XIRQ is pending) to inhibit further interrupts.
The CPU fetches the interrupt vector for the highest priority pending
source, and execution continues at the address specified by the vector.
The interrupt service routine ends with the return-from-interrupt (RTI)
instruction, which tells the CPU to pull the saved registers from the stack
in reverse order so that normal program execution can resume.
Table 5-6. Stacking Order on Entry to Interrupts
Memory Location
CPU Registers
SP
PCL
SP – 1
PCH
SP –2
IYL
SP – 3
IYH
SP – 4
IXL
SP – 5
IXH
SP – 6
ACCA
SP – 7
ACCB
SP – 8
CCR
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5.5.1 Non-Maskable Interrupts
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Non-maskable interrupts can interrupt CPU operations at any time. The
most common use for such an interrupt is for serious system problems,
such as program runaway or power failure. The three sources of
non-maskable interrupt are:
•
XIRQ pin
•
Illegal opcode trap
•
Software interrupt instruction (SWI)
5.5.1.1 Non-Maskable Interrupt Request (XIRQ)
The XIRQ input is an updated version of the non-maskable NMI input of
earlier MCUs. Upon reset, both the X bit and I bit of the CCR are set to
inhibit all maskable interrupts and XIRQ. After minimum system
initialization, software can clear the X bit by a transfer from accumulator
A to condition code register (TAP) instruction, enabling XIRQ interrupts.
Thereafter, software cannot set the X bit and the XIRQ interrupt
becomes non-maskable.
I bit-related interrupts do not affect the X bit, which has a higher priority
than they do in the interrupt priority logic. When an I bit-related interrupt
occurs, the CPU sets the I bit after stacking the CCR byte, but the X bit
remains unaffected. When an X bit-related interrupt occurs, the CPU
sets both the X and I bits after stacking the CCR. The RTI instruction
restores the X and I bits to their pre-interrupt request state when it pulls
the CCR from the stack.
5.5.1.2 Illegal Opcode Trap
The MCU includes an illegal opcode detection circuit to avoid attempting
to process undefined opcodes or opcode sequences. This mechanism
works for all unimplemented opcodes on all four opcode map pages.
When the circuit detects an illegal opcode, it generates an interrupt. The
CPU responds by pushing the current value of the program counter,
which is actually the address of the first byte of the illegal opcode, on the
stack. The illegal opcode service routine can use this stacked address
as a pointer to the illegal opcode to correct it. To avoid repeated
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Interrupts
execution of the illegal opcode, which can lead to stack overflow, the
service routine should reinitialize the stack pointer.
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5.5.1.3 Software Interrupt (SWI)
SWI cannot be masked by virtue of the fact that it is a software
instruction. It is not inhibited by the global mask bits in the CCR.
Execution of SWI sets the I mask bit, so other interrupts are inhibited
until user software clears the I bit or SWI terminates with an RTI
instruction.
5.5.2 Maskable Interrupts
All maskable interrupts are generated by on-chip peripherals, with the
exception of the IRQ pin. This input can be connected through a
wired-OR network to external devices. When one of these devices pulls
IRQ low, a software accessible interrupt flag is set. When enabled, this
flag causes a constant request for interrupt service. After the flag is
cleared, the service request is released. IRQ is low-level sensitive by
default, but can be set for falling-edge sensitivity by the IRQE bit in the
OPTION register (see Figure 5-6).
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE(1)
DLY(1)
CME
FCME(1)
CR1(1)
CR0(1)
0
0
0
1
0
0
0
0
Read:
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in
special modes
Figure 5-6. System Configuration Options Register (OPTION)
IRQE — Configure IRQ for Edge-Sensitive Operation Bit
This bit can be written only once during the first 64 E-clock cycles after
reset in normal modes.
0 = Low-level recognition
1 = Falling-edge recognition
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5.6 Reset and Interrupt Priority
A hardware priority scheme determines which reset or interrupt is
serviced first when simultaneous requests occur.
The six highest-priority interrupt sources are not maskable. The priority
arrangement for these sources is:
1. POR or RESET pin
Freescale Semiconductor, Inc...
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ interrupt
5. Illegal opcode interrupt
6. Software interrupt (SWI)
The maskable interrupt sources have this priority arrangement:
1. IRQ
2. Real-time interrupt
3. Timer input capture 1
4. Timer input capture 2
5. Timer input capture 3
6. Timer output compare 1
7. Timer output compare 2
8. Timer output compare 3
9. Timer output compare 4
10. Timer input capture 4/output compare 5
11. Timer overflow
12. Pulse accumulator overflow
13. Pulse accumulator input edge
14. SPI transfer complete
15. SCI system
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Reset and Interrupt Processing
Any single maskable interrupt can be given priority over other maskable
interrupts by writing the appropriate value to the PSEL bits in the HPRIO
register (see Figure 5-7). An interrupt that is assigned highest priority is
still subject to global masking by the I bit in the CCR or by any associated
local bits. Interrupt vectors are not affected by priority assignment.
Freescale Semiconductor, Inc...
Address: $003C
Bit 7
6
5
4
3
2
1
Bit 0
RBOOT
SMOD
MDA
PSEL4
PSEL3
PSEL2
PSEL1
PSEL0
0
0
0
0
0
1
1
0
Read:
Write:
Reset:
Figure 5-7. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
NOTE:
To avoid race conditions, HPRIO is designed so that bits PSEL[4:0] can
be written only while the I-bit is set (interrupts are inhibited).
PSEL[4:0] — Priority Select Bits
These bits select one interrupt source to have the highest priority, as
explained in Table 5-7.
5.7 Reset and Interrupt Processing
This section presents flow diagrams of the reset and interrupt processes.
Figure 5-8 illustrates how the CPU begins from a reset and how interrupt
detection relates to normal opcode fetches. Figure 5-9 is an expansion
of a block in Figure 5-8 and illustrates interrupt priorities. Figure 5-10
shows the resolution of interrupt sources within the SCI subsystem.
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Table 5-7. Highest Priority Interrupt Selection
PSELx
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Interrupt Source Promoted
4
3
2
1
0
0
0
0
X
X
Reserved (default to IRQ)
0
0
1
0
0
Reserved (default to IRQ)
0
0
1
0
1
Reserved (default to IRQ)
0
0
1
1
0
IRQ
0
0
1
1
1
Real-time interrupt
0
1
0
0
0
Timer input capture 1
0
1
0
0
1
Timer input capture 2
0
1
0
1
0
Timer input capture 3
0
1
0
1
1
Timer output compare 1
0
1
1
0
0
Timer output compare 2
0
1
1
0
1
Timer output compare 3
0
1
1
1
0
Timer output compare 4
0
1
1
1
1
Timer output compare 5/input capture 4
1
0
0
0
0
Timer overflow
1
0
0
0
1
Pulse accumulator overflow
1
0
0
1
0
Pulse accumulator input edge
1
0
0
1
1
SPI serial transfer complete
1
0
1
0
0
SCI serial system
1
0
1
0
1
Reserved (default to IRQ)
1
0
1
1
0
Reserved (default to IRQ)
1
0
1
1
1
Reserved (default to IRQ)
1
1
X
X
X
Reserved (default to IRQ)
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Reset and Interrupt Processing
HIGHEST
PRIORITY
POWER-ON RESET
(POR)
DELAY 4064 E CYCLES
EXTERNAL RESET
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CLOCK MONITOR FAIL
(WITH CME = 1)
LOWEST
PRIORITY
COP WATCHDOG
TIMEOUT
(WITH NOCOP = 0)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, $FFFF
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFC, $FFFD
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFA, $FFFB
(VECTOR FETCH)
SET BITS S, I, AND X
RESET MCU
HARDWARE
1A
BEGIN INSTRUCTION
SEQUENCE
Y
BIT X IN
CCR = 1?
N
XIRQ
PIN LOW?
N
2A
Y
STACK CPU
REGISTERS
SET BITS I AND X
FETCH VECTOR
$FFF4, $FFF5
Figure 5-8. Processing Flow Out of Reset (Sheet 1 of 2)
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2A
Y
BIT I IN
CCR = 1?
N
ANY I-BIT
INTERRUPT
PENDING?
Y
STACK CPU
REGISTERS
N
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FETCH OPCODE
Y
STACK CPU
REGISTERS
ILLEGAL
OPCODE?
N
SET BIT I IN CCR
WAI
Y
INSTRUCTION?
FETCH VECTOR
$FFF8, $FFF9
STACK CPU
REGISTERS
N
Y
STACK CPU
REGISTERS
SWI
INSTRUCTION?
N
SET BIT I IN CCR
FETCH VECTOR
$FFF6, $FFF7
Y
RESTORE CPU
REGISTERS
FROM STACK
RTI
INSTRUCTION?
N
EXECUTE THIS
INSTRUCTION
N
ANY
INTERRUPT
PENDING?
Y
SET BIT I IN CCR
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
1A
Figure 5-8. Processing Flow Out of Reset (Sheet 2 of 2)
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Reset and Interrupt Processing
BEGIN
X BIT
IN CCR
SET ?
YES
NO
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YES
NO
HIGHEST
PRIORITY
INTERRUPT
?
NO
IRQ ?
XIRQ PIN
LOW ?
YES
SET X BIT IN CCR
FETCH VECTOR
$FFF4, FFF5
FETCH VECTOR
YES
FETCH VECTOR
$FFF2, FFF3
NO
RTII = 1 ?
YES
NO
IC1I = 1 ?
YES
YES
NO
TIMER
IC1F ?
YES
FETCH VECTOR
$FFEE, FFEF
TIMER
IC2F ?
YES
FETCH VECTOR
$FFEC, FFED
YES
FETCH VECTOR
$FFEA, FFEB
YES
FETCH VECTOR
$FFE8, FFE9
NO
YES
NO
OC1I = 1 ?
FETCH VECTOR
$FFF0, FFF1
NO
NO
IC3I = 1 ?
YES
NO
NO
IC2I = 1 ?
REAL-TIME
INTERRUPT
?
TIMER
IC3F ?
NO
YES
TIMER
OC1F ?
NO
2B
2A
Figure 5-9. Interrupt Priority Resolution (Sheet 1 of 2)
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2A
2B
Y
OC2I = 1?
OC3I = 1?
Y
FETCH VECTOR
$FFE6, $FFE7
FLAG
OC3F = 1
Y
FETCH VECTOR
$FFE4, $FFE5
Y
FETCH VECTOR
$FFE2, $FFE3
Y
FETCH VECTOR
$FFE0, $FFE1
Y
FETCH VECTOR
$FFDE, $FFDF
Y
FETCH VECTOR
$FFDC, $FFDD
Y
FETCH VECTOR
$FFDA, $FFDB
Y
FETCH VECTOR
$FFD8, $FFD9
N
N
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Y
N
N
OC4I = 1?
Y
FLAG
OC4F = 1?
N
N
OC5I = 1?
Y
FLAG
OC5F = 1?
N
N
Y
TOI = 1?
FLAG
TOF = 1?
N
N
PAOVI = 1?
Y
FLAG
PAOVF = 1
N
N
PAII = 1?
Y
FLAG
PAIF = 1?
N
N
SPIE = 1?
Y
FLAGS
SPIF = 1? OR
MODF = 1?
N
N
SCI
INTERRUPT?
N
FLAG
OC2F = 1?
Y
FETCH VECTOR
$FFD6, $FFD7
FETCH VECTOR
$FFF2, $FFF3
END
Figure 5-9. Interrupt Priority Resolution (Sheet 2 of 2)
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Low-Power Operation
BEGIN
FLAG
RDRF = 1?
Y
N
OR = 1?
Y
RIE = 1?
N
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N
TDRE = 1?
Y
TIE = 1?
RE = 1?
Y
TE = 1?
Y
N
Y
TCIE = 1?
Y
N
N
IDLE = 1?
Y
N
N
N
TC = 1?
Y
Y
Y
ILIE = 1?
N
N
RE = 1?
Y
N
NO
VALID SCI REQUEST
VALID SCI REQUEST
Figure 5-10. Interrupt Priority Resolution Within SCI System
5.8 Low-Power Operation
The MCU contains two software instructions, WAIT and STOP, to
reduce power consumption when processing is not required. Both
instructions suspend operation until a reset or interrupt occurs while
retaining register and RAM contents. The wait condition suspends
processing, reducing power consumption to an intermediate level. The
stop condition turns off all on-chip clocks as well and reduces power
consumption to an absolute minimum.
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5.8.1 Wait Mode
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The WAI opcode places the MCU in the wait condition, during which the
CPU registers are stacked and CPU processing is suspended until a
qualified interrupt is detected. The interrupt can be an external IRQ, an
XIRQ, or any of the internally generated interrupts, such as the timer or
serial interrupts. The on-chip crystal oscillator remains active throughout
the wait standby period.
The reduction of power in the wait condition depends on how many
internal clock signals driving on-chip peripheral functions can be shut
down. The CPU is always shut down during WAIT. While in the wait
state, the address/data bus repeatedly runs read cycles to the address
where the CCR contents were stacked. The MCU leaves the wait state
when it senses any interrupt that has not been masked.
The free-running timer system is shut down only if maskable interrupts
are disabled (I bit is set) and the COP system is disabled (NOCOP is
set). Other systems can be shut down through the software-controlled
configuration control bits, including the SPI system (SPE control bit), the
SCI transmitter (TE bit), and the SCI receiver (RE bit). Net power
reduction in WAIT depends on which of these features is disabled.
5.8.2 Stop Mode
The STOP instruction halts all system clocks, including the crystal
oscillator, thereby minimizing power consumption. The S bit in the CCR
must be cleared to place the MCU in the stop condition; otherwise, the
stop opcode is treated as a no-operation (NOP). To exit STOP and
resume normal processing, a logic low level must be applied to one of
the external interrupt pins (IRQ or XIRQ) or to the RESET pin. A pending
edge-triggered IRQ can also bring the CPU out of stop.
Because all clocks are stopped in this mode, all internal peripheral
functions also stop. RAM and register contents are preserved as long as
VDD power is maintained. The CPU state and I/O pin levels are static and
are not altered by STOP, so the MCU resumes processing seamlessly
after the system is reactivated by an interrupt. However, if a reset is used
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Low-Power Operation
to restart the system, a normal reset sequence results and all pins and
registers are reinitialized.
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To use the IRQ pin as a means of recovering from STOP, the I bit in the
CCR must be clear (IRQ not masked). The XIRQ pin can be used to
wake up the MCU from STOP regardless of the state of the X bit in the
CCR, although the state of this bit does affect the recovery sequence. If
X is clear (XIRQ not masked), the MCU executes a normal XIRQ service
routine. If X is set (XIRQ masked or inhibited), then processing continues
with the instruction that immediately follows the STOP instruction, and
no XIRQ interrupt service is requested or pending.
Executing a STOP instruction requires special consideration when the
clock monitor is enabled. Because the stop function halts all clocks, the
clock monitor function will generate a reset sequence if it is enabled at
the time the stop mode was initiated. To prevent this, clear the CME and
FCME bits in the OPTION register before executing a STOP instruction
to disable the clock monitor. After recovery from STOP, set the CME bit
to enable the clock monitor.
Systems using the internal oscillator require a delay after restart upon
leaving STOP to allow the oscillator to stabilize. If a stable external
oscillator is used, the DLY control bit in the OPTION register can be used
to bypass this startup delay (see Figure 5-11). Reset sets the DLY
control bit; it can be cleared during initialization. Do not use reset to
recover from STOP if the DLY is to be bypassed, since reset sets the
DLY bit again, causing the restart delay. This same delay will follow a
power-on reset, regardless of the state of the DLY control bit, but does
not apply to a reset while the clocks are running.
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPLE
DSEL
IRQE(1)
DLY(1)
CME
FCME(1)
CR1(1)
CR0(1)
0
0
0
1
0
0
0
0
Read:
Write:
Reset:
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time in
special modes
Figure 5-11. System Configuration Options Register (OPTION)
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DLY — Enable Oscillator Startup Delay Bit
This bit is set during reset and can be written only once during the first
64 E-clock cycles after reset in normal modes. This bit can be used to
inhibit the oscillator startup delay after reset when using an external
clock source.
0 = No stabilization delay on exit from STOP
1 = Stabilization delay enabled on exit from STOP
Freescale Semiconductor, Inc...
5.8.3 Slow Mode
Slow mode is a software selectable feature on M68HC(7)11KS devices
that allows the user to connect, under software control, an extra
divide-by-16 between the oscillator and the internal clock. This feature
permits a slow down of all the internal operations reducing power
consumption.
When WAI is used for power reduction, the slow mode helps further
reduce the power. Control of slow mode is performed in the system
configuration options 3 register (OPT3). See Figure 5-12.
Address: $002E
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
Read:
SM
Write:
Reset:
0
0
Figure 5-12. System Configuration Options 3 Register (OPT3)
SM — Slow-Mode Enable Bit
Read and write at any time
1 = When the SM bit is asserted, a 16-clock divider is connected
between the oscillator and the internal clock. This causes the
system clock to run 16 times slower than normal. All modules
of the MCU slow down, including the timer, SCI, SPI, and A/D.
It is also cleared in hardware when entering stop mode or when
reset, including POR, is asserted low.
0 = When the SM bit is negated, the divider is disconnected and the
system runs at normal bus speed.
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Low-Power Operation
NOTE:
The slow mode function should not be enabled while using the A/D
converter or during an erase/program operation of the EEPROM, unless
the internal RC oscillator is turned on.
The clock monitor function should not be used if the resultant E clock will
be slower than 200 kHz.
MUX
Freescale Semiconductor, Inc...
EXTAL
XTAL
XTAL
DIVIDE BY 16
DIVIDE BY 4
OSCILLATOR
SM TO 1 REQUIRES LOW/HI/LOW
ON XTAL — DIVIDE BY 16
RESETS — MUX-OUT LOW
SM BIT
CONTROL LOGIC
IMMEDIATE
CHANGE
8 CYCLES — DIVIDE BY 16 HIGH
8 CYCLES — DIVIDE BY 16 LOW
MUX DIVIDE BY 16 TO SYSTEM
SCI & XOUT
CIRCUITS
CPU & OTHER
MODULES
Figure 5-13. Slow Mode Example for M68HC(7)11KS Devices Only
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Technical Data — M68HC11K Family
Section 6. Parallel Input/Output
Freescale Semiconductor, Inc...
6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.7
Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.8
Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.9
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.10
Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.11
Internal Pullup Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Parallel Input/Output
6.2 Introduction
The M68HC11K series MCUs contain eight input/output (I/O) ports, A
through H. All ports can provide general-purpose I/O (GPIO) as well as
their specialized functions, as explained in 2.11 Port Signals and
summarized in Table 6-1.
Freescale Semiconductor, Inc...
Table 6-1. Port Configuration
Port
Input
Pins
Output
Pins
Bidirectional
Pins
Port A
—
—
8
Timer
Port B
—
—
8
High-order address
Port C
—
—
8
Data bus
Port D
—
—
6
SCI and SPI
Port E
8
—
—
A/D converter
Port F
—
—
8
Low-order address
Port G
—
—
8(1)
Memory expansion
Port H
—
—
8(2)
Chip selects and PWM
Shared Functions
1. KS devices do not contain port G[6:0], so they have only one bidirectional pin on this port.
2. KS devices do not contain port H[7:4], so they have only four bidirectional pins on this port.
Each of the ports has an associated data register (PORTx). Each port,
except port E, also has an associated data direction register (DDRx).
When a port is configured for GPIO, its DDR determines whether port
pins function as inputs or outputs. A port’s special functions override the
DDR when they are enabled.
Writes to any port, except port E, are stored in internal latches. The
latches drive the port pins only when they are configured as
general-purpose outputs.
When software reads a port pin configured for GPIO, the MCU returns
the physical pin level, not the port register value. This applies to both
inputs and outputs. The only exception applies to ports C and D in
wired-OR mode. When they are configured as outputs, a read returns
the pin driver levels.
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Parallel Input/Output
Introduction
Ports B, F, G, and H contain on-chip pullup devices which are enabled
by the port pullup assignment register (PPAR) described in 6.11 Internal
Pullup Resistors.
Freescale Semiconductor, Inc...
At reset, the ports are configured as high-impedance GPIO inputs
(except for ports B, C, F, and port G pin 7 in expanded modes). The
contents of the data latches is undefined. If any of the bidirectional pins
are changed to outputs before writing to the associated data registers,
the undefined contents will be driven on the pins. This is indicated by the
letter U in the register descriptions that follow.
NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
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6.3 Port A
Port A provides the I/O lines for the timer functions and pulse
accumulator. The eight port A bits (PA[7:0]) are configured as
high-impedance general-purpose inputs out of reset. Writes to DDRA
can change any of the bits to outputs. Writes to timer registers enable
the various timer functions (see Section 9. Timing System).
Freescale Semiconductor, Inc...
Address: $0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Undefined after reset
Alternate Pin Function:
PAI
OC2
OC3
OC4
IC4/OC5
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
—
—
—
Figure 6-1. Port A Data Register (PORTA)
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-2. Port A Data Direction Register (DDRA)
DDA[7:0] — Data Direction for Port A Bits
0 = Input
1 = Output
Technical Data
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Port B
6.4 Port B
The state of port B (PB[7:0]) at reset is mode dependent. In single-chip
or bootstrap modes, port B pins are high-impedance inputs with
selectable internal pullup resistors (see 6.11 Internal Pullup
Resistors). Writes to DDRB can change any of the bits to outputs. In
expanded or test modes, port B pins provide the high-order address
lines ADDR[15:8] for external memory devices.
Freescale Semiconductor, Inc...
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Read:
Write:
Reset:
Single-Chip/Boot:
Undefined after reset
PB7I
Expanded/Test: ADDR15
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
Figure 6-3. Port B Data Register (PORTB)
Address: $0002
Bit 7
6
5
4
3
2
1
Bit 0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-4. Port B Data Direction Register (DDRB)
DDB[7:0] — Data Direction for Port B Bits
0 = Input
1 = Output
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6.5 Port C
The state of port C at reset is mode dependent. In single-chip or
bootstrap modes, port C pins (PC[7:0]) are high-impedance inputs.
Writes to DDRC can change any of the bits to outputs. In expanded or
test modes, port C pins provide the data lines (DATA[7:0]) for external
memory devices. The MCU’s internal data bus can also be driven on port
C by setting the IRVNE bit in the system configuration options register
(OPT2). See Figure 6-7.
Freescale Semiconductor, Inc...
When port C functions as GPIO (single-chip mode), it can be configured
for wired-OR operation by setting the CWOM bit in the OPT2 register.
This disables port C’s P-channel drivers, effectively generating
open-drain-type outputs. To output a logic 0 on a wired-OR pin, the MCU
turns on its N-channel driver. To generate a logic 1, both P- and
N-channel drivers are turned off, presenting a high-impedance state
which requires an external pullup resistor to apply the appropriate
voltage level.
Address: $0006
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Read:
Write:
Reset:
Single-Chip/Boot:
Expanded/Test:
Undefined after reset
PC7I
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 6-5. Port C Data Register (PORTC)
Technical Data
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Port C
Address: $0007
Bit 7
6
5
4
3
2
1
Bit 0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-6. Port C Data Direction Register (DDRC)
Freescale Semiconductor, Inc...
DDC[7:0] — Data Direction for Port C Bits
0 = Input
1 = Output
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
STRCH(1)
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
Read:
Write:
Reset:
1. Not available on KS devices
Figure 6-7. System Configuration Options 2 Register (OPT2)
CWOM — Port C Wired-OR Mode Bit
0 = Port C operates normally.
1 = Port C outputs are open drain.
IRVNE — Internal Read Visibility/Not E Bit
In expanded modes, setting this bit drives MCU’s internal data bus on
port C.
0 = No internal read visibility on external data bus
1 = Data from internal reads is driven on port C.
In single-chip modes, setting this bit inhibits the E clock driver, and the
E pin is pulled low
0 = E clock drives the E pin.
1 = E pin is driven low.
NOTE:
IRVNE can be written only once after reset. The default value of IRVNE
after reset is low.
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6.6 Port D
The six port D bits, PD[5:0] function as the serial communication
interface (see Section 7. Serial Communications Interface (SCI)) and
the serial peripheral interface (see Section 8. Serial Peripheral
Interface (SPI)) when these functions are enabled by software. They are
high-impedance general-purpose inputs out of reset; DDRD can be used
to change any of the pins to outputs.
Freescale Semiconductor, Inc...
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
0
0
PD5
PD4
PD3
PD2
PD1
PD0
Reset:
0
0
U
U
U
U
U
U
Alternate Pin Function:
—
—
SS
SCK
MOSI
MISO
TxD
RxD
Read:
Write:
U = Undefined
Figure 6-8. Port D Data Register (PORTD)
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
0
0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-9. Port D Data Direction Register (DDRD)
DDD[5:0] — Data Direction for Port D Bits
0 = Input
1 = Output
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Parallel Input/Output
Port E
6.7 Port E
Port E, PE[7:0], is the only port that functions as input only, and its pins
are configured as high-impedance inputs out of reset. It also serves as
the analog input for the analog-to-digital converter when this function is
enabled by software (see Section 10. Analog-to-Digital (A/D)
Converter).
Freescale Semiconductor, Inc...
NOTE:
PORT E should not be read during the sample portion of an A/D
conversion.
Address: $000A
Bit 7
6
5
4
3
2
1
Bit 0
PE7
PE6
PE5
PE4
PE3
PE2
PD1
PD0
AN2
AN1
AN0
Read:
Write:
Reset:
Alternate Pin Function:
Undefined after reset
AN7
AN6
AN5
AN4
AN3
Figure 6-10. Port E Data Register (PORTE)
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6.8 Port F
The state of port F (PF[7:0]) at reset is mode dependent. In single-chip
or bootstrap modes, port F pins are high-impedance inputs with
selectable internal pullup resistors (see 6.11 Internal Pullup
Resistors). Writes to DDRF can change any of the bits to outputs. In
expanded or test modes, port F pins provide low-order address lines,
ADDR[7:0], for external memory devices.
Freescale Semiconductor, Inc...
Address: $0005
Bit 7
6
5
4
3
2
1
Bit 0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Read:
Write:
Reset:
Undefined after reset
Single-Chip/Boot:
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
Expanded/Test:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Figure 6-11. Port F Data Register (PORTF)
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 6-12. Port F Data Direction Register (DDRF)
DDF[7:0] — Data Direction for Port F Bits
0 = Input
1 = Output
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Port G
6.9 Port G
The state of port G pin 7 (PG7) at reset is mode dependent. In
single-chip or bootstrap modes, it is a high-impedance input; its data
direction can be changed through DDRG. In expanded and special test
modes, PG7 functions as the R/W line to control the direction of data flow
between the MCU and external memory devices.
Freescale Semiconductor, Inc...
Port G pins (PG[6:0]) reset to high-impedance inputs in any mode. Data
direction can be changed through DDRG. Port G bits [5:0] can serve as
memory expansion address lines (see 11.3 Memory Expansion) in
expanded and special test modes. M68HC11KS devices do not contain
these pins.
All eight port G pins have selectable internal pullup resistors (see 6.11
Internal Pullup Resistors).
Address: $007E
Bit 7
6
5
4
3
2
1
Bit 0
PG7
PG6(1)
PG5(1)
PG4(1)
PG3(1)
PG2(1)
PG1 (1)
PG0 (1)
0
0
0
0
0
0
0
0
R/W
—
XA18
XA17
XA16
XA15
XA14
XA13
Read:
Write:
Reset:
Alternate Pin Function:
1. Not available on KS devices
Figure 6-13. Port G Data Register (PORTG)
Address: $007F
Bit 7
6
5
4
3
2
1
Bit 0
DDG7
DDG6(1)
DDG5(1)
DDG4(1)
DDG3(1)
DDG2(1)
DDG1(1)
DDG0(1)
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
1. Not available on KS devices
Figure 6-14. Port G Data Direction Register (DDRG)
DDG[7:0] — Data Direction for Port G Bits
0 = Input
1 = Output
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6.10 Port H
The state of port H pin 7 (PH7) at reset is mode dependent. In single-chip
or bootstrap modes, it is a high-impedance input; its data direction can
be changed through DDRH. In expanded and special test modes PH7 is
the program chip select line, CSPROG at reset, but can be reconfigured
for GPIO (see 11.4 Chip Selects).
Freescale Semiconductor, Inc...
Port H pins (PH[6:0]) reset to high-impedance inputs in any mode. Data
direction can be changed through DDRH. Except for the M68HC11KS
devices, bits 6:4 can serve as chip select lines in expanded and special
test modes (see 11.4 Chip Selects). Pins 3:0 can be configured as
pulse-width modulator outputs (see 9.9 Pulse-Width Modulator
(PWM)) in any mode.
All eight port H pins have selectable internal pullup resistors (see
6.11 Internal Pullup Resistors).
Address: $007C
Read:
Bit 7
6
5
4
3
2
1
Bit 0
PH7 (1)
PH6 (1)
PH5 (1)
PH4 (1)
PH3
PH2
PH1
PH0
0
0
0
0
0
0
0
0
CSPG2
CSPG1
CSIO
PW4
PS3
PS2
PS1
Write:
Reset:
Alternate Pin Function: CSPROG
1. Not available on KS devices
Figure 6-15. Port H Data Register (PORTH)
Address: $007D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
DDH7(1)
DDH6(1)
DDH5(1)
DDH4(1)
DDH3
DDH2
DDH1
DDH0
0
0
0
0
0
0
0
0
Write:
Reset:
1. Not available on KS devices
Figure 6-16. Port H Data Direction Register (DDRH)
DDH[7:0] — Data Direction for Port H Bits
0 = Input
1 = Output
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Parallel Input/Output
Internal Pullup Resistors
6.11 Internal Pullup Resistors
M68HC11KS series devices contain selectable internal pullup resistors
for ports B, F, G, and H. The resistors for each port are enabled by
setting the corresponding bit in the PPAR register. PPAR itself must be
enabled by setting the PAREN bit in the system configuration register
(CONFIG). Refer to Figure 6-17 and Figure 6-18.
Freescale Semiconductor, Inc...
Address: $002C
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
HPPUE
GPPUE
FPPUE
BPPUE
0
0
0
0
1
1
1
1
Read:
Write:
Reset:
Figure 6-17. Port Pullup Assignment Register (PPAR)
xPPUE — Port x Pin Pullup Enable Bits
Only active when enabled by the PAREN bit in the CONFIG register
0 = Port x pin on-chip pullup devices disabled
1 = Port x pin on-chip pullup devices enabled
NOTE:
FPPUE and BPPUE do not apply in expanded mode because port F and
B are address outputs.
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
ROMAD
1
CLKX
PAREN
NOSEC
NOCOP
ROMON
EEON
—
1
—
—
1
—
—
—
Read:
Write:
Reset:
Figure 6-18. System Configuration Register (CONFIG)
NOTE:
CONFIG is writable once in normal modes and writable at any time in
special modes.
PAREN — Pullup Assignment Register Enable Bit
0 = PPAR register disabled
1 = PPAR register enabled; pullups can be enabled through PPAR
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Technical Data
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Technical Data — M68HC11K Family
Section 7. Serial Communications Interface (SCI)
Freescale Semiconductor, Inc...
7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.3
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.4
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
7.5
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.6
Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.7
Short Mode Idle Line Detection . . . . . . . . . . . . . . . . . . . . . . .157
7.8
Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.9
SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
7.9.1
SCI Baud Rate Control Register . . . . . . . . . . . . . . . . . . . . 158
7.9.2
Serial Communications Control Register 1 . . . . . . . . . . . . 160
7.9.3
Serial Communications Control Register 2 . . . . . . . . . . . . 161
7.9.4
Serial Communication Status Register 1 . . . . . . . . . . . . . . 162
7.9.5
Serial Communication Status Register 2 . . . . . . . . . . . . . . 164
7.9.6
Serial Communications Data Register . . . . . . . . . . . . . . . . 165
7.2 Introduction
The serial communications interface (SCI) is a universal asynchronous
receiver transmitter (UART) employing a standard non-return-to-zero
(NRZ) format. Several baud rates are available. The SCI transmitter and
receiver are independent, but they use the same data format and baud
rate.
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Serial Communications Interface (SCI)
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The M68HC11K series offers several enhancements to the basic
MC68HC11 SCI, including:
•
13-bit modulus prescaler in the baud generator
•
Receiver-active flag
•
Transmitter and receiver hardware parity
•
Accelerated idle line detection
7.3 Data Format
The SCI uses the standard non-return to zero mark/space data format
illustrated in Figure 7-1.
8-BIT DATA FORMAT
(BIT MIN SCC1 CLEAR)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT5
BIT6
BIT7
9-BIT DATA FORMAT
(BIT MIN SCC1 SET)
START
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
STOP
BIT
NEXT
START
BIT
PARITY
OR DATA
BIT
BIT 6
BIT 7
BIT 8
STOP
BIT
NEXT
START
BIT
Figure 7-1. SCI Data Formats
Data is transmitted in frames consisting of a start bit, a word of eight or
nine data bits, and a stop bit. The step-by-step transmission procedure
is:
1. The transmission line is idle before a message is transmitted. This
means that the line is in a logic 1 state for at least one frame time.
2. A start bit, logic 0, is transmitted, indicating the start of a frame.
3. An 8-bit or 9-bit word is transmitted, least significant bit (LSB) first.
4. A stop bit, logic 1, is transmitted to indicate the end of a frame.
5. An optional number of breaks can be transmitted. A break is the
transmission of a logic low state for one frame time. After the last
break character is sent, the line goes high for at least one bit time.
Technical Data
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Serial Communications Interface (SCI)
Transmit Operation
6. Steps 2-5 are repeated until the entire message is sent.
7. The line returns to idle status.
7.4 Transmit Operation
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Transmission starts by writing a data character to the 2-byte SCI data
register (SCDRH and SCDRL). The MCU parallel-loads the character
into a serial shift register which shifts the data out on the transmission
pin. This double-buffered operation allows transmission of the current
character while the MCU loads the next one. The output of the serial shift
register drives the TxD pin as long as the transmit enable (TE) bit of
serial communication control register 2 (SCCR2) is set.
Two flags in serial communication status register 1 (SCSR1) alert the
MCU of transmission status. The TDRE (transmit data register empty)
flag is set when the SCDR loads its contents into the shift register; this
flag can generate an interrupt if the TIE (transmit interrupt enable) bit in
SCCR2 is set. The TC (transmit complete) flag is set when transmission
is complete (line idle); this can also generate an interrupt if the TCIE
(transmit complete interrupt enable) bit in SCSR1 is set. The TDRE and
TC flags are normally set when software sets the TE bit to enable the
transmitter. See Figure 5-10. Interrupt Priority Resolution Within SCI
System for a flow diagram of SCI interrupts.
If interrupts are not enabled, the status flags can be read by software
(polled) to determine when the corresponding conditions exist. Status
flags are set automatically by hardware logic conditions, but must be
cleared by software. The software clearing sequence for these flags is
automatic. Functions that are normally performed in response to the
status flags also satisfy the conditions of the clearing sequence.
When software clears the TE bit, the TxD pin reverts to its
general-purpose I/O function (PD1). The transmitter completes
transmission of a character in progress before actually shutting down;
other characters waiting in the transmit queue are lost. The TC and
TDRE flags are set at the completion of this last character, even though
TE has been disabled. Only an MCU reset can abort transmission in
midcharacter.
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Serial Communications Interface (SCI)
Figure 7-2 is a block diagram of the SCI transmitter.
WRITE ONLY
TRANSMITTER
BAUD RATE
CLOCK
SCDR Tx BUFFER
DDD1(1)
4
3
2
1
0
PIN BUFFER
AND CONTROL
L
FORCE PIN
DIRECTION (OUT)
SCI CONTROL 1
TE
TC
TDRE
PT
PE
M
TRANSMITTER
CONTROL LOGIC
SCCR1
PD1
TxD
BREAK — JAM 0s
PARITY
GENERATOR
5
PREAMBLE — JAM 1s
6
JAM ENABLE
7
TRANSFER Tx BUFFER
8
SIZE 8/9
Freescale Semiconductor, Inc...
H
SHIFT ENABLE
10 (11) — BIT Tx SHIFT REGISTER
SCSR1
SCI STATUS 1
TDRE
TIE
TC
SCCR2
SCI Rx
REQUESTS
SBK
TIE
TCIE
TIE
TCIE
SCI CONTROL 2
SCI INTERRUPT
REQUEST
Note 1. Data direction register for port D
INTERNAL
DATA BUS
Figure 7-2. SCI Transmitter Block Diagram
Technical Data
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Serial Communications Interface (SCI)
Receive Operation
7.5 Receive Operation
During receive operations, data from the TxD pin is shifted into the serial
shift register. A completed word is parallel-loaded to a receive data
register (RDR), which can be read through SCDRH/L. This
double-buffered operation allows reception of the current character while
the MCU reads the previous character.
Freescale Semiconductor, Inc...
The SCI receiver has seven status flags, summarized in Table 7-1.
Table 7-1. SCI Receiver Flags
Name
RDRF
Receive data
register full
IDLE
Idle-line
detected
OR
Overrun error
NF
Noise error
Samples of data bit not unanimous
—
FE
Frame error
0 detected where stop bit expected
—
PF
Parity error
Calculated parity does not match data
parity bit
—
RAF
Set When
Interrupt
Enable Bit
Flag
Character transferred from shift register
to RDR
RIE
Active transmit line goes idle
ILIE
Character ready for RDR while previous
character unread
RIE
Receiver active A character is being received
—
Three of the flags can generate interrupt requests if the corresponding
enable bits in SCCR2 are set. The status flags are set by the SCI logic
in response to specific conditions in the receiver. These flags can be
read (polled) at any time by software. Each bit except RAF is cleared by
reading SCSR1 and SCDR sequentially.
•
The receive data register full (RDRF) flag is set when the last bit
of a character is received and data is transferred from the shift
register to the RDR.
•
The IDLE flag is set after a transition on the RxD line from an
active state to an idle state. This prevents repeated interrupts
during the time RxD remains idle.
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Serial Communications Interface (SCI)
•
The overrun error (OR) flag is set instead of the RDRF bit when
the next byte is ready to be transferred from the receive shift
register to the RDR and the RDR is already full. The data in the
shift register is lost and the data that was already in RDR is not
disturbed.
•
The noise flag (NF) is set if there is noise on any of the received
bits, including the start and stop bits. The data recovery circuit
takes three samples of each bit and indicates noise if any set of
three samples is not unanimous. NF is not set until the entire
character is received and transferred to the RDR, when RDRF is
set.
•
The framing error (FE) flag is set when no stop bit is detected in
the received data character. FE is set at the same time as RDRF.
If the byte received causes both framing and overrun errors, the
processor only recognizes the overrun error. The framing error
flag inhibits further data transfer into the RDR until the flag is
cleared.
•
The parity error (PE) flag indicates that the parity bit of a received
character does not match the parity calculated by hardware.
•
The receiver active flag (RAF) is a read-only bit that is set during
data reception and cleared when the line goes idle. This is the only
flag cleared by hardware.
Figure 7-3 is a block diagram of the SCI receiver.
Technical Data
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M68HC11K Family
Serial Communications Interface (SCI)
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Serial Communications Interface (SCI)
Receive Operation
RECEIVER
BAUD RATE
CLOCK
STOP
PIN BUFFER
AND CONTROL
PD0
RxD
DATA
RECOVERY
START
÷ 16
DDD0(1)
10 (11) - BIT
Tx SHIFT REGISTER
H
8
7
6
5
4
3
MSB
2
1
0
L
ALL
ONES
RAF
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DISABLE
DRIVER
SCSR2
PARITY
DETECT
SCI STATUS 2
SCCR1
PF
FE
NF
OR
IDLE
RDRF
PT
PE
ILT
WAKE
M
WAKEUP
LOGIC
SCI CONTROL 1
SCSR1
SCI STATUS 1
SCDR
Rx BUFFER
(READ ONLY)
RDRF
RIE
IDLE
ILIE
OR
SCCR2
RWU
RE
ILIE
RIE
RIE
SCI CONTROL 2
SCI Rx
SCI INTERRUPT
REQUESTS
REQUEST
Note 1. Data direction register for port D
INTERNAL
DATA BUS
Figure 7-3. SCI Receiver Block Diagram
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7.6 Wakeup Feature
The wakeup feature reduces SCI service overhead in multiple receiver
systems. If a system generates address information at the beginning of
every message, each receiver can determine whether or not it is the
intended recipient of a message by evaluating the first character(s)
through software.
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If the message is intended for a different receiver, the SCI can be placed
in a sleep mode so that the rest of the message will not generate
requests for service. It does this by setting the RWU (receiver wakeup)
bit in SCI control register 2 (SCCR2), which inhibits all receiver-related
status flags (RDRF, IDLE, OR, NF, FE, PF, and RAF). A new message
clears the receiver’s RWU bit, enabling it to evaluate the new address
information. Although RWU can be cleared by a software write to
SCCR2, this is rarely done because hardware clears RWU
automatically.
Two methods of wakeup are available:
•
Idle line wakeup — A sleeping receiver wakes up as soon as the
RxD line becomes idle (for example, in a logic 1 state for at least
one frame time). A system using this type of wakeup must provide
at least one character time of idle between messages to wake up
sleeping receivers and must not allow any idle time between
characters within a message.
•
Address mark wakeup — Uses the most significant bit (MSB) to
distinguish address characters (MSB = 1) from data characters
(MSB = 0). A sleeping receiver wakes up whenever it receives an
address character. Unlike the idle line method, address mark
wakeup allows idle periods within messages and does not require
idle time between messages. However, message processing is
less efficient because the start bit of each character must be
evaluated.
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Serial Communications Interface (SCI)
Short Mode Idle Line Detection
7.7 Short Mode Idle Line Detection
This feature can increase system communication speed by reducing the
amount of time between messages. Setting the ILT bit in SCCR1 allows
the SCI receiver to detect the consecutive 1s of an idle period before the
stop bit of an incoming character is received. If the last few bits of the
character are 1s, they are counted as the first high bits in the frame of 1s
comprising the idle period following the character.
Freescale Semiconductor, Inc...
NOTE:
Extra care may be needed to prevent premature detection of an idle line
condition.
7.8 Baud Rate Selection
The baud rate generator for the SCI includes a 13-bit modulus prescaler
driven by the system crystal clock (EXTAL). Writing to the SCI baud rate
register (SCBDH/L) selects the prescaler value. See Figure 7-4.
EXTAL
13-BIT COUNTER
RESET
13-BIT COMPARE
INTERNAL
PHASE 2
CLOCK
÷2
TRANSMITTER
BAUD RATE
CLOCK
SYNCH
SCBDH/L SCI BAUD RATE
CONTROL
÷16
RECEIVER
BAUD RATE
CLOCK
Figure 7-4. SCI Baud Generator Circuit Diagram
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7.9 SCI Registers
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The six addressable registers in the SCI are:
NOTE:
•
SCI baud rate control register (SCBDH and SCBDL)
•
Serial communications control register 1 (SCCR1)
•
Serial communications control register 2 (SCCR2)
•
Serial communication status register 1 (SCSR1)
•
Serial communication status register 2 (SCSR2)
•
Serial communications data register (SCDRH and SCDRL)
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
7.9.1 SCI Baud Rate Control Register
This register selects the 13-bit divisor shown in Figure 7-4 to generate
the SCI baud rate. (See Table 7-2.) Normally, this register is written once
during initialization, but it can be changed at any time.
Address: $0070
Bit 7
6
5
4
3
2
1
Bit 0
BTST
BSPL
0
SBR12
SBR11
SBR10
SBR9
SBR8
0
0
0
0
0
U
U
U
Read:
Write:
Reset:
U = Undefined
Figure 7-5. SCI Baud Rate Control Register High (SCBDH)
Address: $0071
Bit 7
6
5
4
3
2
1
Bit 0
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
0
0
0
0
0
U
U
U
Read:
Write:
Reset:
U = Undefined
Figure 7-6. SCI Baud Rate Control Register Low (SCBDL)
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Serial Communications Interface (SCI)
SCI Registers
BTST — Baud Register Test Bit
BTST is for factory use only and is only accessible in special test
mode.
BSPL — Baud Rate Counter Split Bit
BSOK is for factory use only and is only accessible in special test
mode.
Freescale Semiconductor, Inc...
SBR[12:0] — SCI Baud Rate Select Bits
These bits represent the value BR in:
SCI baud rate control
register value = (EXTAL/32)/target baud rate
Table 7-2. SCI+ Baud Rates
EXTAL Frequencies
EXTAL Freq.
8.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
24.0 MHz
E Clock Freq.
2.0 MHz
3.0 MHz
4.0 MHz
5.0 MHz
6.0 MHz
SCI Baud Rate Control Register Values
Target
Baud Rate
Decimal
Hex
Decimal
Hex
Decimal
Hex
Decimal
Hex
Decimal
Hex
110 baud
2273
$08E1
3409
$0D51
4545
$11C1
5682
$1632
6818
$1AA2
150 baud
1667
$0683
2500
$09C4
3333
$0D05
4167
$1047
5000
$1388
300 baud
833
$0341
1250
$04E2
1667
$0683
2083
$0823
2500
$09C4
600 baud
417
$01A1
625
$0271
833
$0341
1042
$0412
1250
$04E2
1200 baud
208
$00D0
313
$0139
417
$01A1
521
$0209
625
$0271
2400 baud
104
$0068
156
$009C
208
$00D0
260
$0104
313
$0139
4800 baud
52
$0034
78
$004E
104
$0068
130
$0082
156
$009C
9600 baud
26
$001A
39
$0027
52
$0034
65
$0041
78
$004E
19200 baud
13
$000D
20
$0014
26
$001A
33
$0021
39
$0027
38400 baud
—
—
—
—
13
$000D
16
$0010
20
$0014
76800 baud
—
—
—
—
—
—
8
$0008
10
$000A
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7.9.2 Serial Communications Control Register 1
Address $0072
Bit 7
6
5
4
3
2
1
Bit 0
LOOPS
WOMS
0
M
WAKE
ILT
PE
PT
U
U
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
U = Undefined
Figure 7-7. SCI Control Register 1 (SCCR1)
LOOPS — SCI Loop Mode Enable Bit
Both the transmitter and receiver must be enabled to use the loop
mode. When the loop mode is enabled, the TxD pin is driven high (idle
line state) if the transmitter is enabled.
0 = SCI transmit and receive operate normally.
1 = SCI transmit and receive are disconnected from TxD and RxD
pins, and transmitter output is fed back into the receiver input.
WOMS — Wired-OR Mode for SCI Pins PD[1:0] Bits
See also 8.6.1 Serial Peripheral Control Register for a description
of the DWOM (port D wired-OR mode) bit in the serial peripheral
control register (SPCR).
0 = TxD and RxD operate normally.
1 = TxD and RxD are open drains if operating as outputs.
M — Mode (SCI Word Size) Bit
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup Mode Bit
0 = Wake up by idle line recognition
1 = Wake up by address mark (most significant data bit set)
ILT — Idle Line Type Bit
0 = Short (SCI counts consecutive 1s after start bit.)
1 = Long (SCI counts one only after stop bit.)
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Serial Communications Interface (SCI)
SCI Registers
PE — Parity Enable Bit
0 = Parity disabled
1 = Parity enabled
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PT — Parity Type Bit
0 = Parity even (even number of 1s causes parity bit to be 0, odd
number of 1s causes parity bit to be 1)
1 = Parity odd (odd number of 1s causes parity bit to be 0, even
number of 1s causes parity bit to be 1)
7.9.3 Serial Communications Control Register 2
Address $0073
Bit 7
6
5
4
3
2
1
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-8. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
0 = TDRE interrupts disabled
1 = SCI interrupt is requested when the TDRE status flag is set.
TCIE — Transmit Complete Interrupt Enable Bit
0 = TC interrupts disabled
1 = SCI interrupt is requested when the TC status flag is set.
RIE — Receiver Interrupt Enable Bit
0 = RDRF and OR interrupts disabled
1 = SCI interrupt is requested when the RDRF flag or OR flag is set.
ILIE — Idle Line Interrupt Enable Bit
0 = IDLE interrupts disabled
1 = SCI interrupt is requested when the IDLE status flag is set.
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TE — Transmitter Enable Bit
When TE goes from 0 to 1, one unit of idle character time (logic 1) is
queued as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
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RE — Receiver Enable Bit
0 = Receiver disabled
1 = Receiver enabled
RWU — Receiver Wakeup Control
0 = Normal SCI receiver operation
1 = Wakeup is enabled and receiver interrupts are inhibited.
SBK — Send Break Bit
At least one character time of break is queued and sent each time
SBK is written to 1. Multiple breaks may be sent if the transmitter is
idle at the time the SBK bit is toggled on and off, as the baud rate clock
edge could occur between writing the 1 and writing the 0 to SBK.
0 = Break generator off
1 = Break codes generated as long as SBK = 1
7.9.4 Serial Communication Status Register 1
The SCSR provides flags for various SCI conditions which can be polled
or used to generate SCI system interrupts. To clear any set flag, read
SCSR while the flag is set and then write to SCDR.
Address $0074
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-9. SCI Status Register 1 (SCSR1)
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Serial Communications Interface (SCI)
SCI Registers
TDRE — Transmit Data Register Empty Flag
TDRE is set when the SCDR transfers its contents to the transmission
shift register.
0 = SCDR is full.
1 = SCDR is empty.
TC — Transmit Complete Flag
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TC is set when the final character in a message has been sent (no
data, preamble, or break transmissions pending).
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
RDRF is set when the shift register has received a complete character
and transferred it to the receive data register.
0 = RDR not full
1 = RDR full
IDLE — Idle Line Detected Flag
IDLE is set when a frame of all 1s is received after a message.
0 = RxD line is active.
1 = RxD line is idle.
OR — Overrun Error Flag
OR is set if a new character is received before a previously received
character is read from SCDR.
0 = No overrun
1 = Overrun detected
NF — Noise Error Flag
NF is set after the last bit in a frame is received if the samples in the
receiver’s data recovery circuit are not unanimous for any of the bits,
including start and stop bits.
0 = No noise detected
1 = Noise detected
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FE — Framing Error Flag
FE is set when a 0 is detected where a stop bit (logic 1) was expected.
0 = Stop bit detected
1 = Logic 0 detected at the end of a character
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PF — Parity Error Flag
PF is set if received data has incorrect parity. Clear PF by reading
SCSR1.
0 = Parity disabled
1 = Parity enabled
7.9.5 Serial Communication Status Register 2
Address $0075
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Bit 0
RAF
Read:
Write:
Reset:
0
= Unimplemented
Figure 7-10. SCI Status Register 2 (SCSR2)
RAF — Receiver Active Flag
RAF is a read-only bit.
0 = Receiver is inactive.
1 = A character is being received.
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Serial Communications Interface (SCI)
SCI Registers
7.9.6 Serial Communications Data Register
The SCDR is a parallel register that performs two functions. Received
data in the RDR is read from this address when the SCI is receiving, and
data to be transmitted is written to this address when the SCI is
transmitting.
Freescale Semiconductor, Inc...
Address $0076
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
Read:
Write:
Reset:
Undefined after reset
Address $0077
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
Read:
Write:
Reset:
Undefined after reset
Figure 7-11. SCI Data Register (SCDR)
R8 and T8 — Receiver Bit 8 and Transmitter Bit 8
Ninth data bit is received or transmitted when the system is configured
for 8-bit data using mark address wakeup.
R/T[7:0] — Receiver/Transmitter Bits [7:0]
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Section 8. Serial Peripheral Interface (SPI)
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
8.3
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
8.4
SPI Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.1
Master In Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.2
Master Out Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.3
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
8.4.4
Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
8.4.5
SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
8.5
SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
8.5.1
Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
8.5.2
Write Collision Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
8.6
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
8.6.1
Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . 174
8.6.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . 176
8.6.3
Serial Peripheral Data Register . . . . . . . . . . . . . . . . . . . . . 177
8.6.4
Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 178
8.6.5
System Configuration Options 2. . . . . . . . . . . . . . . . . . . . . 179
8.2 Introduction
The serial peripheral interface (SPI) provides synchronous
communication between the MCU and peripheral devices such as
transistor-transistor logic (TTL) shift registers, liquid crystal display
(LCD) drivers, analog-to-digital (A/D) converter subsystems, and other
processors. Synchronous communication requires a clock and, in the
M68HC11 series, a slave-select signal, but provides substantially faster
communication than the asynchronous SCI, which does not require this
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Serial Peripheral Interface (SPI)
extra hardware. The SPI system can send data at up to one half of the
E-clock rate when configured as master and the full E-clock rate when
configured as a slave.
8.3 SPI Functional Description
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The SPI is a 4-wire, full-duplex communication system. Characters are
eight bits, transmitted most significant bit (MSB) first. One master device
exchanges data with one or more slave devices. Each device selects its
mode by writing either a 1 (master) or 0 (slave) to the MSTR bit in the
serial peripheral control register (SPCR). As a master device transmits
data to a slave device via the MOSI (master out slave in) line, the slave
transmits data to the master via the MISO (master in slave out) line. The
master produces a common synchronization clock signal and drives it on
its SCK (serial clock) pin, which is configured as an output. The slave
SCK pin is configured as an input to receive the clock. An external logic
low signal is applied to the slave select pin (SS) of each slave device for
which a particular message is intended. Devices not selected (SS high)
ignore the transmission.
Received characters are double-buffered. Serial input bits are fed into a
shift register; when the last bit is received, the completed character is
parallel-loaded to a read data buffer. This allows the next message to be
received while the current message is being read. As long as the buffer
is read before the next received character is ready to be transferred to
the buffer, no overrun condition occurs.
Transmitted characters are not double-buffered, they are written directly
to the output shift register. This means that new data for transmission
cannot be written to the shift register until the previous transmission is
complete. An attempt to write during data transmission will not go
through; the transmission in progress will proceed undisturbed, and the
MCU will set the write collision (WCOL) status bit in the serial peripheral
status register (SPSR). After the last bit of a character is shifted out, the
SPI transfer complete flag (SPIF) of the SPSR is set. This will also
generate an interrupt if the SPIE (SPI interrupt enable) bit in the SPCR
is set.
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Serial Peripheral Interface (SPI)
SPI Functional Description
A single MCU register, the serial peripheral data register (SPDR) is used
both to read input data from the read buffer and to write output data to
the transmit shift register.
Figure 8-1 shows the SPI block diagram.
M
MISO
PD2
M
S
MOSI
PD3
MSB
DIVIDER
÷÷4 ÷16 ÷32
LSB
8/16-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK
S
CLOCK
LOGIC
M
SPR0
SCK
PD4
SS
PD5
MSTR
SPR1
SELECT
SPI CLOCK (MASTER)
PIN CONTROL LOGIC
S
MSTR
SPE
DWOM
÷2
SPE
SPR0
SPR1
CPHA
CPOL
MSTR
DWOM
SPE
SPIE
MODF
WCOL
SPI CONTROL
SPIF
Freescale Semiconductor, Inc...
INTERNAL
MCU CLOCK
8
SPI STATUS REGISTER
SPI CONTROL REGISTER
8
SPI INTERRUPT
REQUEST
8
INTERNAL
DATA BUS
Figure 8-1. SPI Block Diagram
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8.4 SPI Signal Descriptions
The four basic SPI signals (MISO, MOSI, SCK, and SS) are discussed
for both the master and slave modes in the following paragraphs.
Freescale Semiconductor, Inc...
Every SPI output line must have its corresponding port D data direction
register (DDRD) bit set. If this bit is clear, the line is disconnected from
the SPI logic and becomes a general-purpose input line. SPI input lines
are not affected by the data direction register.
8.4.1 Master In Slave Out (MISO)
The MISO is one of two unidirectional serial data lines in the SPI. It
functions as an input in a master device and as an output in a slave
device. The MISO line of a slave device is placed in the high-impedance
state if the slave is not selected.
8.4.2 Master Out Slave In (MOSI)
This unidirectional serial data line is an output in a master device and an
input in a slave device.
8.4.3 Serial Clock (SCK)
The serial clock (SCK) synchronizes data movement both in and out of
all devices. Master and slave devices exchange a byte of information
simultaneously during a sequence of eight clock cycles. SCK is
generated by the master device so its SCK pin functions as an output.
Slave devices receive this signal through their SCK pins, which are
configured as inputs.
The SPI clock rate select bits in the master device determine the SCK
clock rate. These bits are SPR[1:0] in the serial peripheral control
register (SPCR) and SPR2 in the system configuration options 2 register
(OPT2). These bits have no effect in a slave device.
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Serial Peripheral Interface (SPI)
SPI Signal Descriptions
8.4.4 Slave Select (SS)
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The slave select (SS) input is used to target specific devices in the SPI
system. It must be pulled low on a targeted slave device prior to any
communication with a master and must remain low for the duration of the
transaction. SS must always be high on any device in master mode.
Pulling SS low on a master mode device generates a mode fault error
(see 8.5.1 Mode Fault Error).
8.4.5 SPI Timing
Four possible timing relationships are available through control bits
CPOL (clock polarity) and CPHA (clock phase) in the SPCR. These bits
must be the same in both master and slave devices. The master device
always places data on the MOSI line approximately a half-cycle before
the SCK clock edge. This enables the slave device to latch the data. See
Figure 8-2.
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in
both master and slave devices.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
6
5
4
3
2
1
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
6
5
4
3
2
1
LSB
SS (TO SLAVE)
Figure 8-2. Data Clock Timing Diagram
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CPOL selects an active high or low clock edge. CPHA selects one of two
transfer formats. When CPHA is cleared, the shift clock is ORed with SS.
Each slave’s SS pin must be pulled high before it writes the next output
byte to its data register. If a slave writes to its data register while SS is
low, a write collision error occurs. When CPHA is set, SS may be left low
for several SPI characters. When there is only one SPI slave MCU, its
SS line may be tied to VSS if CPHA = 1 at all times.
The SPI configuration determines the characteristics of a transfer in
progress. For a master, a transfer begins when data is written to SPDR
and ends when SPIF is set. For a slave with CPHA cleared, a transfer
starts when SS goes low and ends when SS returns high. In this case,
SPIF is set at the middle of the eighth SCK cycle when data is
transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA set, transfer
begins when the SCK line goes to its active level, which is the edge at
the beginning of the first SCK cycle. The transfer ends when SPIF is set.
SCK in a slave must be inactive for at least two E-clock cycles between
byte transfers.
8.5 SPI System Errors
Two types of errors can be detected by the SPI system:
•
A mode fault error can occur when multiple devices attempt to act
in master mode simultaneously.
•
A write collision error results from an attempt to write data to the
SPDR while a transmission is in progress.
8.5.1 Mode Fault Error
A mode fault error occurs when the SS input line of an SPI system
configured as a master goes to active low, usually because two devices
have attempted to act as master at the same time. The resulting
contention between push-pull CMOS pin drivers can cause them
permanent damage. The mode fault disables the drivers in an attempt to
protect them. The MSTR control bit in the SPCR and all four DDRD
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SPI Registers
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control bits associated with the SPI are cleared, effectively forcing the
pins to be high-impedance inputs. The mode fault error flag (MODF) is
set in the serial peripheral status register (SPSR). An interrupt is
generated, subject to masking by the SPIE control bit and the I bit in the
CCR. To disable the mode fault circuit, write a 1 to DDRD bit 5. This
configures port D bit 5 as a general-purpose output rather than SS.
Other precautions may be necessary to prevent driver damage. For
instance, if two devices are made masters at the same time, mode fault
does not help protect either one unless one of them selects the other as
slave. The amount of damage possible depends on the length of time
both devices attempt to act as master.
8.5.2 Write Collision Error
A write collision error occurs when the SPDR is written while a
transmission is in progress. The SPDR is not double buffered in the
transmit direction, so writes to the SPDR go directly into the SPI shift
register, which would corrupt any transfer in progress. The MCU protects
against this by preventing the write and generating the write collision
error. The transmission continues undisturbed.
A write collision is normally a slave error because a slave has no control
over when a master initiates a transfer. A master knows when a transfer
is in progress, so there is no reason for a master to generate a
write-collision error, although the SPI logic can detect write collisions in
both master and slave devices.
8.6 SPI Registers
The three SPI registers provide control, status, and data storage
functions respectively:
•
Serial peripheral control register (SPCR)
•
Serial peripheral status register (SPSR)
•
Serial peripheral data register (SPDR)
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NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
8.6.1 Serial Peripheral Control Register
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Address: $0028
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR2
0
0
0
0
0
1
U
U
Read:
Write:
Reset:
U = Undefined
Figure 8-3. Serial Peripheral Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPI interrupt disabled
1 = SPI interrupt is enabled each time the SPIF or MODF status
flag in SPSR is set.
SPE — Serial Peripheral System Enable Bit
0 = SPI off
1 = SPI on — PD[5:2] function as SPI signals
DWOM — Port D Wired-OR Mode Bit
DWOM affects only the four SPI pins on port D, PD[5:2]. See also
7.9.2 Serial Communications Control Register 1 for a discussion
of the WOMS (wired-OR Mode for SCI pins) bit in the serial
communications control register 1 (SCCR1).
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
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Serial Peripheral Interface (SPI)
SPI Registers
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device has a steady state low
value. When CPOL is set, SCK idles high.
CPHA — Clock Phase Bit
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The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPHA bit
selects one of two different clocking protocols.
SPR[1:0] — SPI Clock Rate Select Bits
On a master device, these two bits in conjunction with SPR2 in the
OPT2 register select the baud rate to be used as SCK. See Table 8-1.
These bits have no effect in slave mode.
Table 8-1. SPI+ Baud Rates
EXTAL Frequencies
EXTAL Freq.
8.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
24.0 MHz
Other EXTAL
E Clock Freq.
2.0 MHz
3.0 MHz
4.0 MHz
5.0 MHz
6.0 MHz
EXTAL ÷ 4
Control Bits
SPR[2:0]
E Clock
Divide by
SPI Baud Rate
000
1.0 MHz
1.5 MHz
2.0 MHz
2.5 MHz
3.0 MHz
2
001
500 kHz
750 kHz
1.0 MHz
1.3 kHz
1.5 MHz
4
010
125 kHz
187.5 kHz
250 kHz
312.5 kHz
375.0 kHz
16
011
62.5 kHz
93.8 kHz
125 kHz
156.3 kHz
187.5 kHz
32
100
250 kHz
375 kHz
500 kHz
625 kHz
750.0 kHz
8
101
125 kHz
187.5 kHz
250 kHz
312.5 kHz
375.0 kHz
16
110
31.3 kHz
46.9 kHz
62.5 kHz
78.1 kHz
93.8 kHz
64
111
15.6 kHz
23.4 kHz
31.3 kHz
39.1 kHz
46.9 kHz
128
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8.6.2 Serial Peripheral Status Register
Address: $0029
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
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Figure 8-4. Serial Peripheral Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
SPIF is set upon completion of data transfer between the processor
and the external device. If SPIF goes high, and if SPIE is set, a serial
peripheral interrupt is generated. To clear the SPIF bit, read the SPSR
with SPIF set, then access the SPDR. Unless SPSR is read (with
SPIF set) first, attempts to write SPDR are inhibited.
WCOL — Write Collision Bit
Clearing the WCOL bit is accomplished by reading the SPSR (with
WCOL set) followed by an access of SPDR.
0 = No write collision
1 = Write collision
MODF — Mode Fault Bit
To clear the MODF bit, read the SPSR (with MODF set), then write to
the SPCR.
0 = No mode fault
1 = Mode fault
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Serial Peripheral Interface (SPI)
SPI Registers
8.6.3 Serial Peripheral Data Register
The SPDR is used when transmitting or receiving data on the serial bus.
Only a write to this register initiates transmission or reception of a byte,
and this only occurs in the master device. At the completion of
transferring a byte of data, the SPIF status bit is set in both the master
and slave devices.
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A read of the SPDR is actually a read of a buffer. To prevent an overrun
and the loss of the byte that caused the overrun, the first SPIF must be
cleared by the time a second transfer of data from the shift register to the
read buffer is initiated.
Address: $002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 8-5. Serial Peripheral Data Register (SPDR)
A write to SPDR goes directly to the transmission shift register.
A read of the SPDR retrieves data from the read data buffer.
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8.6.4 Port D Data Direction Register
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
0
0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
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Figure 8-6. Port D Data Direction Register (DDRD)
DDD5 Bit
Bit 5 of the port D data register (PD5) is dedicated as the slave select
(SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI
master mode, DDD5 affects PD5 as follows:
0 = PD5 is an error-detect input to the SPI.
1 = PD5 is configured as a general-purpose output line.
DDD[4:2] Bits
When the SPI is enabled, SPI input pins remain functioning
regardless of the state of the corresponding DDD[4:2] bits. For SPI
output pins, however, the corresponding DDD[4:2] bits must be set or
the pins will function as general-purpose inputs.
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Serial Peripheral Interface (SPI)
SPI Registers
8.6.5 System Configuration Options 2
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
LIRDV
CWOM
STRCH(1)
IRVNE
LSBF
SPR2
XDV1
XDV0
0
0
0
—
0
0
0
0
Read:
Write:
Reset:
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1. Not available on M68HC11K devices
Figure 8-7. System Configuration Options 2 Register (OPT2)
LSBF — Least Significant Bit First Enable Bit
Setting LSBF causes data to be transmitted LSB first (the default is
MSB first). LSBF does not affect bit positions in the data register;
reads and writes always have MSB in bit 7.
SPR2 — SPI Clock Rate Select Bit
SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the
two bits in the SPCR, this specifies the SPI clock rate. See Table 8-1.
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Technical Data — M68HC11K Family
Section 9. Timing System
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9.1 Contents
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
9.3
Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
9.4
Input Capture and Output Compare Overview . . . . . . . . . . . . 185
9.4.1
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
9.4.2
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 189
9.4.3
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 189
9.4.4
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 190
9.4.5
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 191
9.5
Input Capture (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
9.5.1
Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . 192
9.5.2
Timer Input Capture 4/Output Compare 5 Register . . . . . . 193
9.5.3
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 194
9.5.4
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 194
9.5.5
Timer Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 195
9.6
Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
9.6.1
Timer Output Compare Registers . . . . . . . . . . . . . . . . . . . 197
9.6.2
Timer Input Capture 4/Output Compare 5 Register . . . . . . 199
9.6.3
Timer Interrupt Flag 1 Register . . . . . . . . . . . . . . . . . . . . . 199
9.6.4
Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . 200
9.6.5
Timer Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . 200
9.6.6
Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . 201
9.6.7
Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . 202
9.6.8
Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . 202
9.7
Pulse Accumulator (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
9.7.1
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . 205
9.7.2
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 205
9.7.3
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 206
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9.7.4
9.7.5
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 207
Pulse Accumulator Count Register . . . . . . . . . . . . . . . . . .208
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9.8
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
9.8.1
Timer Interrupt Flag 2 Register . . . . . . . . . . . . . . . . . . . . . 209
9.8.2
Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . 209
9.8.3
Pulse Accumulator Control Register . . . . . . . . . . . . . . . . . 210
9.9
Pulse-Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . 211
9.9.1
PWM System Description. . . . . . . . . . . . . . . . . . . . . . . . . . 211
9.9.2
Pulse-Width Modulation Control Registers. . . . . . . . . . . . . 213
9.9.2.1
Pulse-Width Modulation Timer
Clock Select Register . . . . . . . . . . . . . . . . . . . . . . . . 213
9.9.2.2
Pulse-Width Modulation Timer Polarity Register . . . . . . 215
9.9.2.3
Pulse-Width Modulation Timer Prescaler Register . . . .215
9.9.2.4
Pulse-Width Modulation Timer Enable Register . . . . . . 216
9.9.2.5
Pulse-Width Modulation Timer
Counters1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . 217
9.9.2.6
Pulse-Width Modulation Timer
Periods 1 to 4 Registers . . . . . . . . . . . . . . . . . . . . . . 218
9.9.2.7
Pulse-Width Modulation Timer
Duty Cycle 1 to 4 Registers . . . . . . . . . . . . . . . . . . .219
9.2 Introduction
M68HC11 microcontrollers contain an extensive timing system to
support a wide variety of timer-related functions. This section discusses
the nature of the timing system and presents details of timer-related
functions including:
•
Input capture/output compare (IC/OC)
•
Real-time interrupt (RTI)
•
Pulse accumulator (PA)
•
Pulse width modulation (PWM)
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Timing System
Timer Structure
9.3 Timer Structure
As Figure 9-1 shows, the primary system clocks, including the E clock
and the internal PH2 bus clock, are derived from the oscillator output
divided by four.
÷ 1, 4, 6, 8
XDV[1:0].
EXTAL
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OSCILLATOR
XOUT
÷4
E CLOCK
(÷ 1, 2, 3, 4, 5......8191)
SBR[12:0]
÷4
÷2
SCI RECEIVER CLOCK
÷ 16
SCI TRANSMIT CLOCK
PH 2 (INTERNAL BUS
CLOCK)
SPI
PRESCALER
(÷ 2, 4, 8, 16, 32, 64, 128)
SPR[2:0]
TCNT
E ÷ 26
POSTSCALER
PRESCALER
(÷ 1, 4, 8, 16)
PR[1:0]
E÷2
13
POSTSCALER
TOF
÷4
PULSE ACCUMULATOR
PRESCALER
(÷ 1, 2, 4, 8)
RTR[1:0]
REAL-TIME INTERRUPT
E ÷ 215
PRESCALER
(÷ 1, 4, 16, 64)
CR[1:0]
IC/OC
S
R
CLEAR COP
TIMER
Q
S
Q
R
Q
Q
FORCE
COP
RESET
SYSTEM
RESET
Figure 9-1. Timer Clock Divider Chains
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The PH2 bus clock feeds four primary divider chains. The functions
supplied by each of these chains are:
1. Serial peripheral interface (SPI)
2. Input capture/output compare (IC/OC)
3. Pulse accumulator (PA)
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4. RTI and COP watchdog circuit
The SPI prescale factor is determined by bits SPR[2] in the system
configuration options 2 (OPT2) register and SPR[1:0] in the serial
peripheral control register (SPCR). See 8.6.1 Serial Peripheral Control
Register and 8.6.5 System Configuration Options 2.
The input capture and output compare functions are based on a 16-bit
free-running counter, which is driven by the PH2 clock divided by a
programmable prescaler. Bits PR[1:0] of the timer interrupt mask 2
(TMSK2) register enable the user to select one of four divisors: 1, 4, 8,
or 16. The output of this prescaler, referred to as the main timer, feeds
the divider chains for the pulse accumulator, RTI, and COP circuits as
well as the free-running counter. Table 9-1 shows main timer
frequencies and periods available from the most common crystal inputs.
Table 9-1. Main Timer Rates
EXTAL Frequencies
EXTAL Freq.
8.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
20.0 MHz
Other EXTAL
E Clock Freq.
2.0 MHz
3.0 MHz
4.0 MHz
5.0 MHz
5.0 MHz
EXTAL/4
E Clock Period
500 ns
333 ns
250 ns
200 ns
200 ns
1/E
Control Bits
PR[1:0]
Main Timer Period
(1 Count/Timer Overflow)
1÷E
00
500 ns
32.768 ms
333 ns
21.845 ms
250 ns
16.384 ms
200 ns
13.107 ms
167 ns
10.923 ms
216 ÷ E
01
2.0 µs
131.07 ms
1.3 µs
87.381 ms
1.0 µs
85.536 ms
800 ns
52.429 ms
667 ns
43.961 ms
4÷E
218 ÷ E
10
4.0 µs
262.14 ms
2.667 µs
174.76 ms
2.0 µs
131.07 ms
1.6 µs
104.86 ms
1.333 µs
87.381 ms
8÷E
219 ÷ E
11
8.0 µs
524.29 ms
5.333 µs
349.53 ms
4.0 µs
262.14 ms
3.2 µs
209.72 ms
2.667 µs
174.76 ms
16 ÷ E
220 ÷ E
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1 Count
Timer Overflow
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Timing System
Input Capture and Output Compare Overview
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The free-running counter begins incrementing from $0000 as the MCU
comes out of reset and continues to the maximum count, $FFFF. At the
maximum count, the counter rolls over to $0000, sets the timer overflow
flag (TOF) in the timer interrupt flag 2 (TFLG2) register, and continues to
increment. The value in this counter can be read in the timer counter
(TCNT) register, but cannot be written or changed except by reset.
The pulse accumulator, described in 9.7 Pulse Accumulator (PA),
derives its clock by post-scaling the main timer so that the output
frequency is always E clock divided by 64. This clock drives an 8-bit
counter while the pulse accumulator is operating in event counting
mode.
RTI is a programmable periodic interrupt circuit that can be used to pace
the execution of software routines, as described in 9.8 Real-Time
Interrupt (RTI). The clock driving this function is also derived from the
clock driving the free-running counter. The post-scaler output of this
chain runs at a frequency of E clock divided by 213.
The COP watchdog timer (5.3.3 Computer Operating Properly (COP)
System) further divides the RTI clock by four to drive its circuitry at a
frequency of E clock divided by 215.
9.4 Input Capture and Output Compare Overview
The M68HC11K series features:
•
Three input capture channels
•
Four output compare channels
•
One channel that can be selected to perform either input capture
or output compare
Each of the three input capture functions has its own 16-bit input capture
register (time capture latch) and each of the output compare functions
has its own 16-bit compare register. All timer functions, including the
timer overflow and RTI, have their own interrupt controls and separate
interrupt vectors.
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Figure 9-2 shows the capture/compare system block diagram. The port
A pin control block includes logic for timer functions and for
general-purpose I/O. This block contains the edge-detection logic for
pins PA[2:0] as well as the control logic that enables edge selection for
the input capture trigger.
•
PA[2:0] can serve either as input capture pins IC[1:3] or as
general-purpose input/output (GPIO).
•
PA[6:4] can serve either as drivers for output compare functions
OC[2:4] or GPIO.
•
PA3 can be used for GPIO, input capture 4, output compare 5, or
output compare 1.
•
Output compare 1 (OC1) has extra control logic which gives it
optional control of any combination of the PA[7:3] pins.
•
The PA7 pin can be used as a GPIO pin, as an input to the pulse
accumulator, or as an OC1 output pin.
Reading the port A register returns the actual pin level on any pin
functioning as an input, and the logic level of the internal pin driver (NOT
the pin level) on any pin functioning as an output. This is true whether
the pins are configured for timer functions or GPIO. Writing to port A pins
configured for timer functions has no visible effect; the writes are latched
but do not drive the pins.
Registers common to both the input capture and output compare
functions include:
NOTE:
•
Timer counter register (TCNT)
•
Timer interrupt flag 2 (TFLG2)
•
Timer interrupt mask 2 (TMSK2)
•
Data direction register A (DDRA)
•
Pulse accumulator control register (PACTL)
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
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Input Capture and Output Compare Overview
PRESCALER — DIVIDE BY
1, 4, 8, 16
SYSTEM
CLOCK
PR1
TCNT (HI)
TCNT (LO)
16-BIT FREE
RUNNING
COUNTER
PR0
TOI
9
TOF
INTERRUPT REQUESTS
16-BIT TIMER BUS
OC1I
16-BIT COMPARATOR =
TOC1 (HI)
TOC1
OC1F
(LO)
FOC1
Freescale Semiconductor, Inc...
OC2I
16-BIT COMPARATOR =
TOC2 (HI)
TOC2
(LO)
(LO)
(LO)
16-BIT LATCH
OC5
(LO)
I4/O5F
CLK
TIC1 (HI)
CLK
BIT 3
PA3
IC4/OC5
OC1
BIT 2
PA2
IC1
BIT 1
PA1
IC2
BIT 0
PA0
IC3
4
3
IC1F
IC2I
2
IC2F
TIC2 (LO)
16-BIT LATCH
TIC3 (HI)
CLK
PA4
OC4/OC1
FOC5
IC1I
TIC1 (LO)
16-BIT LATCH
TIC2 (HI)
CLK
BIT 4
IC4
I4/O5
16-BIT LATCH
PA5
OC3/OC1
5
FOC4
16-BIT COMPARATOR =
TI4/O5
BIT 5
6
OC4F
I4/O5I
TI4/O5 (HI)
PA6
OC2/OC1
FOC3
16-BIT COMPARATOR =
TOC4
BIT 6
7
OC3F
OC4I
TOC4 (HI)
PA7
OC1
FOC2
16-BIT COMPARATOR =
TOC3
BIT 7
OC2F
OC3I
TOC3 (HI)
PIN
FUNCTIONS
8
IC3I
IC3F
1
TIC3 (LO)
TFLG 1
STATUS
FLAGS
CFORC
TMSK 1
FORCE OUTPUT INTERRUPT
COMPARE
ENABLES
PORT A
PIN CONTROL
Figure 9-2. Capture/Compare Block Diagram
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9.4.1 Timer Counter Register
Bit 7
6
5
4
3
2
1
Bit 0
Address: $000E — TCNT (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Write:
Reset:
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Address: $000F — TCNT (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 9-3. Timer Counter Register (TCNT)
TCNT reflects the current value in the free-running counter. Input
capture functions use this number to mark the time of an external event,
and output compare functions use it to determine the time at which to
generate an event.
In normal modes, TCNT is a read-only register. Writes to TCNT in
normal modes have no effect. TCNT can be read and written in special
modes.
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Input Capture and Output Compare Overview
9.4.2 Timer Interrupt Flag 2 Register
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
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Reset:
Figure 9-4. Timer Interrupt Flag 2 (TFLG2)
Clear each flag by writing a 1 to the corresponding bit position.
TOF — Timer Overflow Flag
Set when TCNT changes from $FFFF to $0000.
9.4.3 Timer Interrupt Mask 2 Register
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-5. Timer Interrupt Mask 2 (TMSK2)
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2.
TOI — Timer Overflow Interrupt Enable Bit
0 = Timer overflow interrupt disabled
1 = An interrupt request is generated when TOF is set.
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PR[1:0] — Timer Prescaler Select Bits
These bits determine the main timer prescale divisor, as shown in
Table 9-2. The system bus (E clock) frequency is divided by this
number to produce the clock which drives the free-running counter.
Refer to Table 9-1 for specific timing values.
In normal modes, PR[1:0] can be written only once, and the write must
be within 64 cycles after reset.
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Table 9-2. Timer Prescale
PR[1:0]
Prescaler
00
1
01
4
10
8
11
16
9.4.4 Port A Data Direction Register
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-6. Port A Data Direction Register (DDRA)
DDA3 — Data Direction Control for Port A, Bit 3
0 = PA3 configured as an input
1 = PA3 configured as an output
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Input Capture (IC)
9.4.5 Pulse Accumulator Control Register
Address: $0026
Read:
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN
PAMOD
PEDGE
0
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Write:
Reset:
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Figure 9-7. Pulse Accumulator Control Register (PACTL)
I4/O5 — Input Capture 4/Output Compare 5 Bit
0 = Configure PA3 as OC5
1 = Configure PA3 as IC4
To configure PA3 as input compare 4, clear DDA3 and set I4/05. To
configure PA3 as output compare 5, set DDA3 and clear I4/05. If the
DDA3 bit is set (configuring PA3 as an output) and IC4 is enabled,
writing a one to TI4/O5 causes an input capture. Writing to TI4/O5 has
no effect when DDA3 is cleared and/or OC5 is enabled.
9.5 Input Capture (IC)
The input capture function records the time an external event occurs by
latching the value of the free-running counter into one of the timer input
capture (TIC) registers when a selected edge is detected at its
associated timer input pin. Software can store latched values and use
them to compute the period and duration of events. For example, by
storing the times of successive edges of an incoming signal, software
can determine the period and pulse width of a signal. To measure the
period, two successive edges of the same polarity are captured. To
measure pulse width, two alternate polarity edges are captured.
Capture requests are latched on the opposite half cycle of PH2 from
when the timer counter is being incremented. This synchronization
process introduces a delay between edge occurrence and counter value
detection. Because these delays offset each other when the time
between two edges is measured, they can be ignored. There is a similar
delay for output compare between the actual compare point and when
the output pin changes state.
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9.5.1 Timer Input Capture Registers
Bit 7
6
5
4
3
2
1
Bit 0
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Address: $0010 — TIC1 (High)
Read:
Bit 15
Bit 14
Write:
Reset:
Unaffected by reset
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Address: $0011 — TIC1 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Address: $0012 — TIC2 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Address: $0013 — TIC2 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Address: $0014— TIC3 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Write:
Reset:
Unaffected by reset
Address: $0015 — TIC3 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Unaffected by reset
Figure 9-8. Timer Input Capture Registers (TIC1–TIC3)
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Input Capture (IC)
9.5.2 Timer Input Capture 4/Output Compare 5 Register
Bit 7
6
5
4
3
2
1
Bit 0
Address: $001E — TI4/O5 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
Freescale Semiconductor, Inc...
Address: $001F — TI4/O5 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Figure 9-9. Timer Input Capture 4/Output
Compare 5 Register (TI4/O5)
TI4/05 functions as the input capture register for IC4 when PA3 is
configured for input capture 4.
When an edge on an input capture pin has been detected and
synchronized, the 16-bit free-running counter value is latched in the
associated input capture register pair in a single 16-bit parallel transfer.
The latch occurs on the opposite half-cycle of the phase two clock from
when the timer counter is incremented. This ensures a stable count
value whenever a capture occurs.
Input capture values can be retrieved from a TIC register with two
successive 8-bit reads. Reading the high-order byte inhibits a new
capture transfer for one bus cycle to ensure that the successive
low-order byte read corresponds with it. If a new input capture occurs
immediately after a high-order byte read, transfer is delayed for an
additional cycle, but the new value is not lost. To assure coherency
between the two bytes, use a double-byte read instruction such as LDD.
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9.5.3 Timer Interrupt Flag 1 Register
Address: $0023
Bit 7
6
5
4
3
2
1
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
Read:
Write:
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Reset:
Figure 9-10. Timer Interrupt Flag 1 Register (TFLG1)
Clear each flag by writing a 1 to the corresponding bit position.
ICxF — Input Capture x Flag
Set each time a selected active edge is detected on the
corresponding input capture line.
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set each time a selected active edge is detected on the IC4 line if IC4
is enabled.
9.5.4 Timer Interrupt Mask 1 Register
Address: $0022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-11. Timer Interrupt Mask 1 Register (TMSK1)
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1.
ICxI — Input Capture Interrupt Enable Bit
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware
interrupt sequence is requested.
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Input Capture (IC)
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
If I4/O5I is set when IC4 is enabled and the I4/O5F flag bit is set, a
hardware interrupt sequence is requested.
9.5.5 Timer Control 2 Register
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Address: $0021
Bit 7
6
5
4
3
2
1
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-12. Timer Control 2 Register (TCTL2)
EDGx[B:A] — Input Capture Edge Control Bits
These bit pairs determine the edge polarities on the input capture pins
that trigger the corresponding input capture functions. Each of the
input capture functions can be independently configured to detect
rising edges only, falling edges only, any edge (rising or falling), or to
disable the input capture function. The input capture functions
operate independently of each other and can capture the same TCNT
value if the input edges are detected within the same timer count
cycle.
Each EDGx bit pair is cleared (IC function disabled) by reset and must
be encoded according to the values in Table 9-3 to configure the
corresponding input capture edge detector circuit. IC4 functions only
if the I4/O5 bit in the PACTL register is set.
Table 9-3. Input Capture Edge Selection
EDGxB
EDGxA
ICx Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge
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9.6 Output Compare (OC)
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The output compare (OC) function generates a programmed action
when the 16-bit counter reaches a specified value. Each of the five
output compare functions contains a separate 16-bit timer output
compare (TOC) register and a dedicated 16-bit comparator. Each TOC
register is set to $FFFF on reset. When an OC channel is enabled, the
value in its TOC register is compared to the free-running counter value
during each E-clock cycle. When the values match, the channel’s output
compare flag is set in timer interrupt flag 1 (TFLG1). If the channel’s
interrupt is enabled in the timer interrupt mask register 1 (TMSK1), an
interrupt is generated. Also, the corresponding timer output pin is
toggled or driven to a specified logic level. This pin activity occurs on
each successful compare, whether or not the OCxF flag in the TFLG1
register was previously cleared.
The pin action for each of the OC channels [5:2] is controlled by a pair of
bits (OMx and OLx) in the TCTL1 register and affects only the channel’s
associated pin. A successful OC1 compare can affect any or all five of
the OC pins. The action taken when a match is found for OC1 is
controlled by two 8-bit registers:
•
Output compare 1 mask register (OC1M)
•
Output compare 1 data register (OC1D)
OC1M specifies which port A outputs are to be used, and OC1D
specifies the data placed on these port pins.
Although the M68HC11K series devices have four built-in pulse-width
modulation (PWM) channels (9.9 Pulse-Width Modulator (PWM)), the
output compare function can be used to produce an additional
pulse-width modulated waveform. To produce a pulse of a specific
duration:
•
Write a value to the output compare register that represents the
time the leading edge of the pulse is to occur.
•
Use OC1D to select either a high or low output, depending on the
polarity of the pulse being produced.
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Output Compare (OC)
•
After a match occurs, change the appropriate OC1D bit to the
opposite polarity, then add a value representing the width of the
pulse to the original value and write it to the output compare
register.
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Because the pin state changes occur at specific values of the
free-running counter, the pulse width can be controlled accurately to the
resolution of the free-running counter, independent of software
latencies. To generate an output signal of a specific frequency and duty
cycle, repeat this pulse-generating procedure.
9.6.1 Timer Output Compare Registers
Bit 7
6
5
4
3
2
1
Bit 0
Address: $0016 — TOC1 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $0017 — TOC1 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $0018 — TOC2 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $0019 — TOC2 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Figure 9-13. Timer Output Compare
Registers (TOC1–TOC4)
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Bit 7
6
5
4
3
2
1
Bit 0
Address: $001A— TOC3 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $001B — TOC3 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
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Write:
Reset:
Address: $001C— TOC4 (High)
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Write:
Reset:
Address: $001D — TOC4 (Low)
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Write:
Reset:
Figure 9-13. Timer Output Compare
Registers (TOC1–TOC4) (Continued)
All output compare registers are 16-bit read-write. Any of these registers
can be used as a storage location if it is not used for output compare or
input capture.
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Output Compare (OC)
9.6.2 Timer Input Capture 4/Output Compare 5 Register
Bit 7
6
5
4
3
2
1
Bit 0
Address: $001E — TI4/O5 (High)
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
1
1
1
1
1
1
1
1
Address: $001F — TI4/O5 (Low)
Freescale Semiconductor, Inc...
Read:
Write:
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Figure 9-14. Timer Input Capture 4/Output
Compare 5 Register (TI4/O5)
Functions as the output compare register for OC5 when PA3 is
configured for output compare 5. This register is 16-bit read-write. It can
be used as a storage location if it is not used for output compare or input
capture.
9.6.3 Timer Interrupt Flag 1 Register
Address: $0023
Bit 7
6
5
4
3
2
1
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-15. Timer Interrupt Flag 1 Register (TFLG1)
Clear each flag by writing a 1 to the corresponding bit position.
OCxF — Output Compare x Flag
Set each time the counter matches output compare x value.
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set each time the counter matches output compare 5 value if OC5 is
enabled.
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9.6.4 Timer Interrupt Mask 1 Register
Address: $0022
Bit 7
6
5
4
3
2
1
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0
0
0
0
0
0
0
0
Read:
Write:
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Reset:
Figure 9-16. Timer Interrupt Mask 1 Register (TMSK1)
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware
interrupt sequence is requested.
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
If I4/O5I is set when OC5 is enabled and the I4/O5F flag bit is set, a
hardware interrupt sequence is requested.
9.6.5 Timer Control 1 Register
Address: $0020
Bit 7
6
5
4
3
2
1
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-17. Timer Control Register 1 (TCTL1)
OM[2:5] and OL[2:5] — Output Mode and Output Level Bits
Use these bit pairs as indicated in Table 9-4 to specify the action
taken after a successful OCx compare.
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Output Compare (OC)
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Table 9-4. Timer Output Compare Actions
OMx
OLx
Action Taken on Successful Compare
0
0
Timer disconnected from output pin logic
0
1
Toggle OCx output line
1
0
Clear OCx output line to 0
1
1
Set OCx output line to 1
9.6.6 Timer Compare Force Register
Address: $000B
Bit 7
6
5
4
3
2
1
Bit 0
FOC1
FOC2
FOC3
FOC4
FOC5
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-18. Timer Compare Force Register (CFORC)
The CFORC register allows forced early compares. Writing a 1 to any bit
of FOC[1:5] forces the programmed pin actions for the corresponding
OC channel to occur at the next timer count transition after the write to
CFORC. The action taken as a result of a forced compare is identical to
the action taken when a match between the OCx register and the
free-running counter occurs, except that the corresponding interrupt and
status flag bits are not set.
CFORC should not be applied to an output compare function that is
programmed to toggle its output on a successful compare because a
normal compare that occurs immediately before or after the force can
result in an undesirable operation.
FOC[1:5] — Force Output Comparison Bits
0 = No action taken
1 = Output x action occurs at the next timer count transition
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9.6.7 Output Compare 1 Mask Register
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 9-19. Output Compare 1 Mask Register (OC1M)
OC1M specifies which bits of port A will respond to a successful
compare for output capture 1. The bits of the OC1M[7:3] register
correspond to PA[7:3].
OC1M[7:3] — Output Compare 1 Masks
0 = OC1 is disabled at the corresponding PA pin.
1 = OC1 is enabled at the corresponding PA pin.
9.6.8 Output Compare 1 Data Register
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-20. Output Compare 1 Data Register (OC1D)
Use this register in conjunction with OC1M to specify the data that is to
drive the affected pin of port A after a successful OC1 compare. When a
successful OC1 compare occurs, a data bit in OC1D is stored in the
corresponding bit of port A for each bit that is set in OC1M.
Technical Data
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Pulse Accumulator (PA)
OC1D[7:3] — Output Compare Data Bits
0 = Corresponding port A pin is cleared on successful OC1
compare if the corresponding OC1M bit is set.
1 = Corresponding port A pin is set on successful OC1 compare if
the corresponding OC1M bit is set.
Freescale Semiconductor, Inc...
9.7 Pulse Accumulator (PA)
The pulse accumulator can be used either to count events or measure
the duration of a particular event. In event counting mode, the pulse
accumulator’s 8-bit counter increments each time a specified edge is
detected on the pulse accumulator input pin, PA7. The maximum
clocking rate for this mode is E clock divided by two. In gated time
accumulation mode, an internal clock increments the 8-bit counter at a
rate of E clock divided by 64 while the input at PA7 remains at a
predetermined logic level. Table 9-5 shows pulse accumulator clock
periods for three common crystal frequencies.
Figure 9-21 is a block diagram of the pulse accumulator.
Table 9-5. Pulse Accumulator Timing
EXTAL Frequencies
EXTAL Freq.
8.0 MHz
12.0 MHz
16.0 MHz
20.0 MHz
24.0 MHz
Other
EXTAL
E Clock Freq.
2.0 MHz
3.0 MHz
4.0 MHz
5.0 MHz
6.0 MHz
EXTAL ÷
Maximum event
counting frequency
1.0 MHz
1.5 MHz
2.0 MHz
2.5 MHz
3.0 MHz
E÷2
Gated mode count
resolution
32.0 µs
21.3 µs
16.0 µs
12.8 µs
10.7 µs
26 ÷ E
Gated mode count
overflow
8.192 µs
5.461 µs
4.096 µs
3.277 µs
2.731 µs
214 ÷ E
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1
INTERRUPT
REQUESTS
PAIF
PAOVF
PAII
PAOVI
2
TMSK2
TFLG2
INTERRUPT ENABLES
STATUS FLAGS
PAI EDGE
Freescale Semiconductor, Inc...
E ÷ 64 CLOCK
FROM MAIN TIMER
PAEN
2:1
MUX
INPUT BUFFER
AND
EDGE DETECTION
PA7/
PAI/OC1
CLOCK
OVERFLOW
PACNT
8-BIT COUNTER
ENABLE
OUTPUT
BUFFER
PEDGE
PAEN
FROM
MAIN TIMER
OC1
PAMOD
PAEN
PACTL
CONTROL
FROM
DDA7
INTERNAL
DATA BUS
Figure 9-21. Pulse Accumulator
Registers involved in pulse accumulator operation include:
•
Data direction register A (DDRA)
•
Pulse accumulator control register (PACTL)
•
Timer interrupt mask 2 register (TMSK2)
•
Timer interrupt flag 2 (TFLG2)
•
Pulse accumulator count register (PACNT)
Technical Data
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Pulse Accumulator (PA)
9.7.1 Port A Data Direction Register
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 9-22. Port A Data Direction Register (DDRA)
The pulse accumulator uses port A, bit 7 as the PAI input, but the pin can
also be used as general-purpose I/O or as an output compare.
NOTE:
Even when port A, bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
DDA7 — Data Direction Control for Port A, Bit 7
0 = PA7 configured as an input
1 = PA7 configured as an output
9.7.2 Pulse Accumulator Control Register
Address: $0026
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN
PAMOD
PEDGE
0
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-23. Pulse Accumulator Control Register (PACTL)
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
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PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
Freescale Semiconductor, Inc...
PEDGE — Pulse Accumulator Edge Control Bit
In event counting mode, PEDGE selects either the rising or falling
edge of the input at PA7 to increment the pulse accumulator counter.
In gated accumulation mode, PEDGE determines which input level at
PA7 inhibits counter increments from the internal clock. Table 9-6
shows the relationship between PEDGE and PAMOD.
Table 9-6. Pulse Accumulator Edge Control
PAMOD
PEDGE
Action on Clock
0
0
PAI falling edge increments the counter.
0
1
PAI rising edge increments the counter.
1
0
A 0 on PAI inhibits counting.
1
1
A 1 on PAI inhibits counting.
9.7.3 Timer Interrupt Flag 2 Register
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-24. Timer Interrupt Flag 2 (TFLG2)
Clear each flag by writing a 1 to the corresponding bit position.
Technical Data
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Pulse Accumulator (PA)
9.7.4 Timer Interrupt Mask 2 Register
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-25. Timer Interrupt Mask 2 (TMSK2)
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2.
PAOVF — Pulse Accumulator Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count
rolls over from $FF to $00.
PAOVI — Interrupt Enable Bit
If PAOVI is set, an interrupt request is also generated. If PAOVI is
cleared, pulse accumulator overflow interrupts are inhibited, and
PAOVF must be polled by user software to determine when an
overflow has occurred. In either case, software must clear PAOVF by
writing a 1 to bit 5 in the TFLG2 register.
PAIF — Pulse Accumulator Input Edge Flag
The PAIF status bit is automatically set each time a selected edge is
detected at the PA7 pin.
PAII — Interrupt Enable Bit
If PAII is set, an interrupt request is also generated. If PAII is cleared,
pulse accumulator input interrupts are inhibited, and PAIF must be
polled by user software to determine when an input edge has been
detected. In either case, software must clear PAIF by writing a 1 to
bit 5 in the TFLG2 register.
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9.7.5 Pulse Accumulator Count Register
Address: $0027
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 9-26. Pulse Accumulator Count Register (PACNT)
In event counting mode, PACNT contains the count of external input
events at the PAI input. In gated accumulation mode, PACNT is
incremented by the pulse accumulator’s E ÷ 64 clock when the PAI input
is at the selected level. Counting is synchronized to the internal PH2
clock so that incrementing and reading occur during opposite half cycles.
The counter is not affected by reset and can be read or written to at any
time.
9.8 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) feature generates hardware interrupts at a
fixed periodic rate. The rate is determined by bits RTR[1:0] in the PACTL
register, which further divide a clock running at E ÷ 213 by 1, 2, 4 or 8.
The resulting periods for various common crystal frequencies are shown
in Table 9-7.
Every cycle of the RTI clock sets the RTIF bit in timer interrupt flag 2
(TFLG2) register. This flag can be polled to determine when RTI
timeouts occur, or an interrupt can be generated if the RTII bit in the
timer interrupt mask 2 (TMSK2) register is set. After reset, one entire
real-time interrupt period elapses before the RTIF flag is set for the first
time.
The clock source for the RTI function is a free-running clock that cannot
be stopped or interrupted except by reset. The time between successive
RTI timeouts is a constant that is independent of software latencies
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Real-Time Interrupt (RTI)
associated with flag clearing and service. For this reason, an RTI period
starts from the previous timeout, not from when RTIF is cleared.
9.8.1 Timer Interrupt Flag 2 Register
Freescale Semiconductor, Inc...
Address: $0025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-27. Timer Interrupt Flag 2 Register (TFLG2)
Clear each flag by writing a 1 to the corresponding bit position.
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI
period.
9.8.2 Timer Interrupt Mask 2 Register
Address: $0024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
0
0
PR1
PR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-28. Timer Interrupt Mask 2 Register (TMSK2)
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2.
RTII — Real-time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF is set to 1
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9.8.3 Pulse Accumulator Control Register
Address: $0026
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN
PAMOD
PEDGE
0
I4/O5
RTR1
RTR0
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 9-29. Pulse Accumulator Control Register (PACTL)
RTR[1:0] — Real-Time Interrupt Rate Select Bits
These two bits select a divisor (1, 2, 4, or 8) for the E ÷ 213 RTI clock.
Refer to Table 9-7.
Table 9-7. Real-Time Interrupt Rate versus RTR[1:0]
RTR[1:0]
Rate
XTAL =
12.0 MHz
XTAL = 223
XTAL =
8.0 MHz
XTAL =
4.9152 MHz
XTAL =
4.0 MHz
XTAL =
3.6864 MHz
0
0
213 ÷ E
2.730 ms
3.91 ms
4.10 ms
6.67 ms
8.19 ms
8.89 ms
0
1
214 ÷ E
5.461 ms
7.81 ms
8.19 ms
13.33 ms
16.38 ms
17.78 ms
1
0
215 ÷ E
10.92 ms
15.62 ms
16.38 ms
26.67 ms
32.77 ms
35.56 ms
1 1
216 ÷ E
21.84 ms
31.25 ms
32.77 ms
53.33 ms
65.54 ms
71.11 ms
E=
3.0 MHz
2.1 MHz
2.0 MHz
1.2288 MHz
1.0 MHz
921.6 kHz
Technical Data
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Pulse-Width Modulator (PWM)
9.9 Pulse-Width Modulator (PWM)
Freescale Semiconductor, Inc...
Four 8-bit pulse-width modulation channels are available in the
M68HC11K Family devices. They are output on port H pins 3–0. Pairs of
channels can be concatenated to produce 16-bit outputs. Three
programmable clocks and a flexible clock selection scheme provide a
wide range of frequencies.
The 8-bit mode with E = 4 MHz can produce waveforms from 40 kHz at
1 percent duty cycle resolution to less than 10 Hz at 0.4 percent duty
cycle resolution. In 16-bit mode, a duty cycle resolution down to 15 parts
per million can be achieved (at a frequency of 60 Hz). At 1 kHz, the duty
cycle resolution is 250 ppm.
9.9.1 PWM System Description
Figure 9-30 shows a block diagram of the PWM system. Each of four
channels is enabled by bit PWENx in the PWEN register. Each channel
has an 8-bit counter (PWCNTx), a period register (PWPERx), and a duty
cycle register (PWDTYx). The counter is driven by one of three
user-scaled clock sources — clock A, B, or S — selected by the
pulse-width channel select (PCLKx) bit in the pulse-width modulation
timer polarity (PWPOL) register.
A pulse-width modulation period begins when the counter matches the
value stored in the period register. When this happens, a logic value
determined by the polarity bit (PPOLx) in the PWPOL register is driven
on the associated port H output pin, and the counter is reset to 0. When
the counter matches the number stored in the duty cycle register, the
output reverses polarity. The period and duty cycle registers are double
buffered so they can be changed without disturbing the current
waveform. A new period or duty cycle can be forced by writing to the
period (PWPERx) or duty cycle register (PWDTYx) and then to the
counter (PWCNTx). Writing to the counter always resets it to 0.
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E CLOCK
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128
CLOCK S
8
RESET
PCKA1
PCKA2
PCKB1
PCKB2
PCKB3
8-BIT COUNTER
SELECT
CLOCK A
CLOCK B
SELECT
PCLK3
PCLK4
PWEN3
PWEN4
CON12
CLOCK
SELECT
CNT4
Freescale Semiconductor, Inc...
÷2
8-BIT COMPARE =
PWSCAL
PCLK1
PCLK2
CNT3
PWEN1
PWEN2
CON12
CLOCK
SELECT
CNT2
CNT1
PPOL1
8-BIT COMPARE =
PWDTY1
S
8-BIT COMPARE =
16-BIT
PWM
CONTROL
PWPER1
Q
R
Q
S
Q
8-BIT COMPARE =
PWDTY2
8
8
RESET
8-BIT COMPARE =
PWPER2
Q
BIT 0
PW1
M
U
X
BIT 1
PW2
PPOL2
PWCNT2
PORT H
PIN
CONTROL
CON12
RESET
PWCNT1
R
M
U
X
CARRY
PPOL3
8-BIT COMPARE =
S
PWDTY3
8-BIT COMPARE =
PWPER3
8
8
RESET
PWCNT3
BIT 2
PW3
BIT 3
PW4
R
16-BIT
PWM
CONTROL
8-BIT COMPARE =
PWDTY4
S
8-BIT COMPARE =
PWPER4
R
Q
Q
M
U
X
PPOL4
CON34
RESET
PWCNT4
CARRY
PWDTY
PWPER
Figure 9-30. Pulse-Width Modulation Timer Block Diagram
Technical Data
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The three clocks are derived from the E clock by writing to registers
which determine their scaling factors. The clock A frequency is equal to
E divided by 1, 2, 4, or 8, depending on which bits (PCKA[2:1]) in the
PWCLK register are set. The clock B frequency is equal to the E clock
divided by a power of two determined by bits PCKB[3:1] in the PWCLK
register. Clock S is derived by dividing clock A by the integer (1 to 256)
stored in the PWSCAL register, then by two.
Two channels can be concatenated by setting the appropriate bit
(CON34 or CON12) in the PWCLK register. In this mode, the clock
source is determined by the low-order channel, which is channel two in
CON12 and channel four in CON34. The output is also placed on the pin
associated with the low-order channels, so when two channels are
concatenated the pin associated with the high-order channel (PH0
and/or PH2) can be used for GPIO. A read of the high-order byte causes
the low-order byte to be latched for one cycle to guarantee that
double-byte reads are accurate. A write to the low-order byte of the
counter causes reset of the entire counter. A write to the high-order byte
of the counter has no effect.
9.9.2 Pulse-Width Modulation Control Registers
The PWM control registers are described here.
9.9.2.1 Pulse-Width Modulation Timer Clock Select Register
Address: $0060
Bit 7
6
5
4
3
2
1
Bit 0
CON34
CON12
PCKA2
PCKA1
0
PCKB3
PCKB2
PCKB1
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-31. Pulse-Width Modulation Timer Clock Select (PWCLK)
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CON34 — Concatenate Channels 3 and 4 Bit
Channel 3 is the high-order byte, and channel 4 (port H, bit 3) is
output.
0 = Channels 3 and 4 are separate 8-bit PWMs.
1 = Channels 3 and 4 are concatenated to create one 16-bit PWM.
CON12 — Concatenate Channels 1 and 2 Bit
Freescale Semiconductor, Inc...
Channel 1 is the high-order byte, and channel 2 (port H, bit 1) is
output.
0 = Channels 1 and 2 are separate 8-bit PWMs.
1 = Channels 1 and 2 are concatenated to create one 16-bit PWM.
PCKA[2:1] — Prescaler for Clock A Bits
These bits select the frequency for clock A as shown in Table 9-8.
Table 9-8. Clock A Prescaler
PCKA[2:1]
Clock A Frequency
0
0
E
0
1
E/2
1
0
E/4
1 1
E/8
PCKB[3:1] — Prescaler for Clock B Bits
These bits select the frequency for clock B as shown in Table 9-9.
Table 9-9. Clock B Prescaler
PCKB[3:1]
Clock B Frequency
0
0
0
E
0
0
1
E/2
0
1
0
E/4
0
1 1
E/8
1
0
0
E/16
1
0
1
E/32
1 1
0
E/64
1 1 1
E/128
Technical Data
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Pulse-Width Modulator (PWM)
9.9.2.2 Pulse-Width Modulation Timer Polarity Register
Address: $0061
Bit 7
6
5
4
3
2
1
Bit 0
PCLK4
PCLK3
PCLK2
PCLK1
PPOL4
PPOL3
PPOL2
PPOL1
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-32. Pulse-Width Modulation Timer
Polarity Register (PWPOL)
PCLK[4:3] — Pulse-Width Channel 4, 3 Clock Select Bits
0 = Clock B is source.
1 = Clock S is source.
PCLK[2:1] — Pulse-Width Channel 2, 1 Clock Select Bits
0 = Clock A is source.
1 = Clock S is source.
PPOL[4:1] — Pulse-Width Channel x Polarity Bits
0 = PWM channel x output is low at the beginning of the clock cycle
and goes high when duty count is reached.
1 = PWM channel x output is high at the beginning of the clock
cycle and goes low when duty count is reached.
9.9.2.3 Pulse-Width Modulation Timer Prescaler Register
Address: $0062
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-33. Pulse-Width Modulation Timer
Prescaler Register (PWSCAL)
Scaled clock S is generated by dividing clock A by the value in PWSCAL,
then dividing the result by two. If PWSCAL = $00, the divisor is 256, then
two.
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9.9.2.4 Pulse-Width Modulation Timer Enable Register
Address: $0063
Bit 7
6
5
4
3
2
1
Bit 0
TPWSL
DISCP
0
0
PWEN4
PWEN3
PWEN2
PWEN1
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 9-34. Pulse-Width Modulation Timer
Enable Register (PWEN)
TPWSL — PWM Scaled Clock Test Bit — factory use only; only
accessible in special test mode
0 = Normal operation
1 = Clock S is output to PWSCAL register (test only)
DISCP — Disable Compare Scaled E-Clock Bit — factory use only; only
accessible in special test mode
0 = Normal operation
1 = Match of period does not reset associated count register (test
only)
PWEN[4:1] — Pulse-Width Enable for Channels [4:1] Bits
0 = Channel disabled
1 = Channel enabled at port H bits [3:0]
Technical Data
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Pulse-Width Modulator (PWM)
9.9.2.5 Pulse-Width Modulation Timer Counters 1 to 4 Registers
Bit 7
6
5
4
3
2
1
Bit 0
Address: $0064 — PWCNT1
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Address: $0065 — PWCNT2
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $0066 — PWCNT3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $0067 — PWCNT4
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 9-35. Pulse-Width Modulation Timer
Counters 1 to 4 (PWCNT1 to PWCNT4)
Each counter resets to 0 when it is written and can be read at any time.
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9.9.2.6 Pulse-Width Modulation Timer Periods 1 to 4 Registers
Bit 7
6
5
4
3
2
1
Bit 0
Address: $0068 — PWPER1
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Address: $0069 — PWPER2
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $006A — PWPER3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $006B — PWPER4
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 9-36. Pulse-Width Modulation Timer
Periods 1 to 4 (PWPER1 to PWPER4)
Each period register can be read or written at any time. If it is written, the
new period will not take effect until the associated counter is reset by a
match or a write.
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Timing System
Pulse-Width Modulator (PWM)
9.9.2.7 Pulse-Width Modulation Timer Duty Cycle 1 to 4 Registers
Bit 7
6
5
4
3
2
1
Bit 0
Address: $006C — PWDTY1
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Address: $006D — PWDTY2
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $006E — PWDTY3
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Address: $006F — PWDTY4
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 9-37. Pulse-Width Modulation Timer
Duty Cycle 1 to 4 (PWDTY1 to PWDTY4)
Each duty cycle register can be read or written at any time. If it is written,
the new duty cycle will not take effect until the associated counter is reset
by a match or a write.
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Timing System
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Section 10. Analog-to-Digital (A/D) Converter
10.1 Contents
Freescale Semiconductor, Inc...
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
10.3.1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.3.2 Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
10.3.3 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
10.3.4 Digital Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
10.4 A/D Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 226
10.4.1 System Configuration Options Register . . . . . . . . . . . . . . . 226
10.4.2 A/D Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . 227
10.4.3 Analog-to-Digital Converter Result Registers. . . . . . . . . . . 229
10.5 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.5.1 A/D Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
10.5.2 Operation in Stop and Wait Modes . . . . . . . . . . . . . . . . . .230
10.2 Introduction
The analog-to-digital (A/D) system in M68HC11 microcontrollers is an
8-channel, 8-bit, multiplexed input converter. It employs a successive
approximation technique with an all-capacitive charge redistribution
system that does not require external sample-and-hold circuits. A/D
converter timing can be synchronized either to the E clock or an internal
resistor-capacitor (RC) oscillator. Separate power supply inputs, AVDD
and AVSS, allow independent bypassing for noise immunity.
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10.3 Functional Description
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The A/D converter system consists of four functional blocks as shown in
Figure 10-1:
PE0
AN0
•
Multiplexer
•
Analog converter
•
Result storage
•
Digital control
VRH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1
AN1
PE2
AN2
VRL
ANALOG
MUX
PE3
AN3
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
RESULT
PE4
AN4
INTERNAL
DATA BUS
CA
CB
CC
CD
MULT
CCF
PE6
AN6
SCAN
PE5
AN5
ADCTL
PE7
AN7
RESULT REGISTER INTERFACE
ADR1
ADR2
ADR3
ADR4
Figure 10-1. A/D Converter Block Diagram
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Analog-to-Digital (A/D) Converter
Functional Description
10.3.1 Multiplexer
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The multiplexer selects which of the eight analog inputs at port E will be
converted. There are also three internal reference levels which can be
multiplexed to the converter for system testing. Input selection is
controlled by the value of bits CD:CA in the A/D control register
(ADCTL).
The VRH and VRL pins provide inputs for the A/D system reference
voltage. An input voltage equal to VRL converts to $00 and an input
voltage equal to VRH converts to $FF (full scale), with no overflow
indication. For ratiometric conversions of this type, the source of
each analog input should use VRH as the supply voltage and be
referenced to VRL.
10.3.2 Analog Converter
The conversion block contains a digital-to-analog capacitor (DAC) array,
a comparator, and a successive approximation register (SAR). When an
analog input is sampled for conversion, an analog switch connects the
input to the DAC array. This series of scaled capacitors retains the
sample for the duration of the conversion.
A conversion consists of a sequence of eight comparison operations.
Each comparison determines one bit of the result, starting with the most
significant bit (MSB). During each comparison, analog switches connect
different elements of the DAC array to the comparator. The output of the
comparator is stored in the next bit in the successive approximation
register. When a conversion sequence is complete, the contents of the
SAR are transferred to the appropriate result register.
10.3.3 Result Registers
The A/D conversion sequence begins one E-clock cycle after a write to
the analog-to-digital control/status register (ADCTL). Converter
operations are performed in sequences of four conversions each. Each
conversion result in a sequence is stored in one of the four result
registers, ADR[4:1]. The conversion complete flag (CCF) in the ADCTL
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register is set after the fourth conversion in a sequence to signal the
availability of data in the result registers.The result registers are written
during a portion of the system clock cycle when reads do not occur, so
there is no conflict. A conversion sequence can repeat continuously or
stop after one iteration. Figure 10-2 shows the timing of a typical
sequence. In this example, synchronization is referenced to the system
E clock.
0
CONVERT FIRST
CHANNEL, UPDATE
ADR1
32
CONVERT SECOND
CHANNEL, UPDATE
ADR2
64
CONVERT THIRD
CHANNEL, UPDATE
ADR3
96
2
CYC
END
CONVERT FOURTH
CHANNEL, UPDATE
ADR4
REPEAT SEQUENCE, SCAN = 1
SAMPLE ANALOG INPUT
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
4
2
2
2
2
2
2
2
CYCLES
CYC CYC CYC CYC CYC CYC CYC
SUCCESSIVE APPROXIMATION SEQUENCE
SET CC FLAG
12 E CYCLES
WRITE TO ADCTL
Freescale Semiconductor, Inc...
E CLOCK
128 — E CYCLES
Figure 10-2. A/D Conversion Sequence
10.3.4 Digital Control
In addition to the conversion complete status flag, ADCTL bits select
single or continuous conversions, whether conversions are performed
on single or multiple channels, and the analog input(s) to be converted.
Single or continuous conversions are selected by the SCAN bit. Clearing
the SCAN bit selects the single conversion option, in which results are
written to each of the four result registers one time. The first result is
stored in A/D result register 1 (ADR1), and the fourth result is stored in
ADR4. All conversion activity is then halted until the ADCTL register is
written again. In the continuous mode (SCAN =1), conversion activity
does not stop. The fifth conversion is stored in register ADR1
(overwriting the first conversion result), the sixth conversion overwrites
ADR2, and so on.
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Analog-to-Digital (A/D) Converter
Functional Description
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The MULT bit in ADCTL determines whether one or four channels are
converted. When MULT = 0, one channel is converted. The selected
channel is sampled and the conversion results are written to ADR1; the
same channel is sampled again, and the conversion results are stored
in ADR2, and so on. In continuous mode, the same channel continues to
be sampled and converted. Setting the MULT bit converts four different
channels; each result register contains the conversion result of a
different channel. In continuous mode, the same four channels are
converted in each sequence.
ADCTL bits [3:0] select the particular channel(s) to be converted. See
Table 10-1.
Table 10-1. A/D Converter Channel Selection
Channel Select Control Bits
Channel Signal
Result Location
When MULT = 1
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4
ADR1
0101
AN5
ADR2
0110
AN6
ADR3
0111
AN7
ADR4
10XX
Reserved
—
1100
VRH(1)
ADR1
1101
VRL(1)
ADR2
1110
(VRH)/2(1)
ADR3
1111
Reserved(1)
ADR4
CD:CC:CB:CA
1. Used for factory testing
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10.4 A/D Control/Status Registers
The registers involved in A/D operation include OPTION, ADCTL, and
the four result registers ADR[1:4].
Freescale Semiconductor, Inc...
NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
10.4.1 System Configuration Options Register
Bit 7 in the system configuration options register (OPTION), ADPU,
enables the A/D converter system. Setting ADPU applies power to the
A/D circuitry, including the charge pump that drives the analog switches.
Clearing ADPU removes power from the A/D system.
The gates of analog switches in the multiplexer are driven by a charge
pump that develops between seven and eight volts. The high gate
voltage assures low source-to-drain impedance for the analog signals.
Both the charge pump and the comparator circuits require up to 100 µs
to stabilize after setting the ADPU bit.
The CSEL bit (bit 6) determines whether the A/D converter uses the
system E clock or an internal RC oscillator for synchronization. It is
cleared out of reset, selecting the E clock. This is the preferred setting at
normal operating frequencies because all switching and comparator
operations are synchronized to the main MCU clocks. This allows the
comparator output to be sampled at relatively quiet portions of the MCU
clock cycles.
When the E clock frequency is less than 750 kHz, charge leakage in the
capacitor array can cause errors. In this case, set the CSEL bit to select
the internal oscillator, which usually runs at about 2 MHz. The additional
error introduced by the asynchronous oscillator is about ± 1/2 LSB (least
significant bit), which is usually less than that incurred by a slow clock.
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Analog-to-Digital (A/D) Converter
A/D Control/Status Registers
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
ADPU
CSEL
IRQE
DLY(1)
CME
FCME
CR1
CR0
0
0
0
1
0
0
0
0
Read:
Write:
Reset:
1. DLY can be written only once in the first 64 cycles out of reset in normal modes or at any
time in special modes.
Freescale Semiconductor, Inc...
Figure 10-3. System Configuration Options Register (OPTION)
ADPU — A/D Power-up
0 = A/D powered down
1 = A/D powered up
CSEL — Clock Select
0 = A/D and EEPROM use system E clock.
1 = A/D and EEPROM use internal RC clock.
10.4.2 A/D Control/Status Register
All bits in this register can be read or written except bit 7, which is a
read-only status indicator, and bit 6, which always reads as 0. Writing to
ADCTL initiates a conversion, aborting any conversion in progress.
Address: $0030
Bit 7
Read:
6
5
4
3
2
1
Bit 0
SCAN
MULT
CD
CC
CB
CA
U
U
U
U
U
U
CCF
Write:
Reset:
0
0
= Unimplemented
U = Unaffected by reset
Figure 10-4. Analog-to-Digital Control/Status Register (ADCTL)
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CCF — Conversions Complete Flag
Set when all four A/D result registers contain valid conversion results.
Cleared when the ADCTL register is overwritten, starting a new
conversion sequence. In continuous mode, CCF is set at the end of
the first conversion sequence.
Freescale Semiconductor, Inc...
SCAN — Continuous Scan Control Bit
0 = Conversion process stops after each of the four result registers
is written.
1 = Conversions are performed continuously.
MULT — Multiple Channel/Single Channel Control Bit
0 = A single channel specified by the four channel select bits
CD:CA is sampled and converted four times.
1 = Each of four channels is converted and the results written to a
different result register.
NOTE:
When the multiple-channel continuous scan mode is used, extra care is
needed in the design of circuitry driving the A/D inputs. The charge on
the capacitive DAC array before the sample time is related to the voltage
on the previously converted channel. A charge share situation exists
between the internal DAC capacitance and the external circuit
capacitance. Although the amount of charge involved is small, the rate
at which it is repeated is every 64 µs for an E clock of 2 MHz. The RC
charging rate of the external circuit must be balanced against this charge
sharing effect to avoid errors in accuracy. Refer to the M68HC11
Reference Manual, Motorola document order number M68HC11RM/AD,
for further information.
CD:CA — Channel Selects D:A Bits
Refer to Table 10-1. In multiple channel mode (MULT = 1), the two
least significant channel select bits (CB and CA) have no meaning
and the CD and CC bits specify which group of four channels is to be
converted.
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Analog-to-Digital (A/D) Converter
A/D Control/Status Registers
10.4.3 Analog-to-Digital Converter Result Registers
These read-only registers hold an 8-bit conversion result. Writes to these
registers have no effect. Data in the A/D converter result registers is valid
when the CCF flag in the ADCTL register is set, indicating a conversion
sequence is complete. If conversion results are needed sooner, refer to
Figure 10-2, which shows the A/D conversion sequence diagram.
Freescale Semiconductor, Inc...
Bit 7
Address: $0031
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Analog-to-Digital Result Register 1
Bit 6
Bit 5
Bit 4
Write:
Reset:
Undefined after reset
Address: $0032
Read:
Bit 7
Analog-to-Digital Result Register 2
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Undefined after reset
Address: $0033
Read:
Bit 7
Analog-to-Digital Result Register 3
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Undefined after reset
Address: $0034
Read:
Bit 7
Analog-to-Digital Result Register 4
Bit 6
Bit 5
Bit 4
Bit 3
Write:
Reset:
Undefined after reset
= Unimplemented
Figure 10-5. Analog-to-Digital Result Registers (ADR1–ADR4))
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10.5 Design Considerations
This section discusses design considerations.
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10.5.1 A/D Input Pins
Port E pins can also be used as general-purpose digital inputs. Digital
reads of port E pins are not recommended during the sample portion of
an A/D conversion cycle, when the gate signal to the N-channel input is
on. No P-channel devices are directly connected to either input pins or
reference voltage pins, so voltages above VDD do not cause a latchup
problem, although current should be limited according to maximum
ratings. Refer to Figure 10-6.
DIFFUSION/POLY
COUPLER
ANALOG
INPUT
PIN
+ ~20 V
– ~0.7 V
< 2 pF
INPUT
PROTECTION
DEVICE
≤ 4 kΩ
+ ~12 V
– ~0.7 V
DUMMY N-CHANNEL
OUTPUT DEVICE
SEE NOTE 1
*
~ 20 pF
400 nA
JUNCTION
LEAKAGE
DAC
CAPACITANCE
VRL
Note 1. This analog switch is closed only during the 12-cycle sample time.
Figure 10-6. Electrical Model of an A/D Input Pin (Sample Mode)
10.5.2 Operation in Stop and Wait Modes
If a conversion sequence is in progress when either the stop or wait
mode is entered, the conversion of the current channel is suspended.
When the MCU resumes normal operation, that channel is resampled
and the conversion sequence is resumed. As the MCU exits the wait
mode, the A/D circuits are stable and valid results can be obtained on
the first conversion. However, in stop mode, all analog bias currents are
disabled and it is necessary to allow a stabilization period when leaving
stop mode. If stop mode is exited with a delay (DLY = 1), there is enough
time for these circuits to stabilize before the first conversion. If stop mode
is exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for
the A/D circuitry to stabilize to avoid invalid results.
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Section 11. Memory Expansion and Chip Selects
11.1 Contents
Freescale Semiconductor, Inc...
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
11.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
11.3.1 Memory Size and Address Line Allocation. . . . . . . . . . . . . 232
11.3.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
11.3.2.1
Port G Assignment Register . . . . . . . . . . . . . . . . . . . . . 234
11.3.2.2
Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .235
11.3.2.3
Memory Mapping Window Base Register . . . . . . . . . . . 236
11.3.2.4
Memory Mapping Window Control Registers. . . . . . . . .237
11.4 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
11.4.1 Program Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
11.4.2 Input/Output Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . 241
11.4.3 General-Purpose Chip Selects. . . . . . . . . . . . . . . . . . . . . . 242
11.4.3.1
Memory Mapping Size Register . . . . . . . . . . . . . . . . . . .243
11.4.3.2
General-Purpose Chip Select 1 Address Register. . . . .243
11.4.3.3
General-Purpose Chip Select 1 Control Register . . . . . 244
11.4.3.4
General-Purpose Chip Select 2 Address Register. . . . .245
11.4.3.5
General-Purpose Chip Select 2 Control Register . . . . . 245
11.4.4 One Chip Select Driving Another . . . . . . . . . . . . . . . . . . . . 246
11.4.4.1
General-Purpose Chip Select 1 Control Register . . . . . 247
11.4.4.2
General-Purpose Chip Select 2 Control Register . . . . . 247
11.4.5 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
11.5
Memory Expansion Examples . . . . . . . . . . . . . . . . . . . . . . . . 249
11.2 Introduction
This section provides descriptions of the expanded memory and the chip
selects.
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11.3 Memory Expansion
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The M68HC11K Family devices employ a register-based paging
scheme to extend their address range beyond the physical 64-Kbyte
limit of the 16 CPU address lines. Pages are selected using the
expansion address lines XA[18:13] available on port G. This selection
can be facilitated by the chip-select lines on port H, discussed in
11.4 Chip Selects. The M68HC11KS devices do not provide these
features since they lack the required port G and port H lines. Refer to
Figure 1-2. M68HC11KS Family Block Diagram.
11.3.1 Memory Size and Address Line Allocation
To access expanded memory, the user first allocates portion(s) of the 64
Kbyte address space, or window(s), through which the CPU will view
external memory. One or two windows can be designated, and the size
of each window can be 0 (disabled), 8, 16, or 32 Kbytes.
Expanded memory is addressed with a combination of the CPU’s normal
address lines ADDR[15:0] and the expansion address lines XA[18:13].
The expansion address lines select a memory bank, and the CPU’s
normal address lines select a particular location within the bank. The
size of the window(s) and the number of memory banks determine
exactly which expansion address lines are used. The port G assignment
register (PGAR) controls which port G pins function as expanded
address lines. Any port G pins not allocated for memory expansion can
serve as general-purpose input/output (GPIO). When a configuration
uses any of the lower three expansion address lines XA[15:13] they
replace the CPU's equivalent address lines (ADDR[15:13]). Table 11-1
shows how address and expansion lines are allocated for various
combinations of memory banks and window size.
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Table 11-1. CPU Address and Address Expansion Signals
Window Size
Freescale Semiconductor, Inc...
Number
of Banks
8 Kbytes
16 Kbytes
32 Kbytes
32 Kbytes
(Window Based
at $4000)
2
ADDR[12:0]
XA13
ADDR[13:0]
XA14
ADDR[14:0]
XA15
ADDR[13:0]
XA[15:14]
4
ADDR[12:0]
XA[14:13]
ADDR[13:0]
XA[15:14]
ADDR[14:0]
XA[16:15]
ADDR[13:0]
XA[16:14]
8
ADDR[12:0]
XA[15:13]
ADDR[13:0]
XA[16:14]
ADDR[14:0]
XA[17:15]
ADDR[13:0]
XA[17:14]
16
ADDR[12:0]
XA[16:13]
ADDR[13:0]
XA[17:14]
ADDR[14:0]
XA[18:15]
ADDR[13:0]
XA[18:14]
32
ADDR[12:0]
XA[17:13]
ADDR[13:0]
XA[18:14]
—
—
—
—
64
ADDR[12:0]
XA[18:13]
—
—
—
—
—
—
The base address for each window must be an integer multiple of the
window size, with one exception. When the window size is 32 Kbytes,
the base address can be at $4000 as well as the 32-Kbyte multiples
$0000 and $8000.
This special case requires a modification in address line deployment.
Normally, when the bank size is 32 Kbytes and the bank address is
$0000 or $8000, CPU address lines ADDR[14:0] select individual bytes
within the 32-Kbyte space and the ADDR[14:0] pins are connected to
address lines A[14:0] of the memory device. When the base address is
$4000, the CPU address signal ADDR14 must be inverted to allow
32 Kbytes of contiguous memory. To do this, the CPU drives the
inverted ADDR14 signal onto the XA14 pin when the window is active,
and the non-inverted CPU ADDR14 signal onto the XA14 pin when the
window is not active. Therefore, address 14 of the memory device must
be connected to expansion line XA14 rather than normal address line
ADDR14.
If the two memory windows overlap, window 1 has priority, and only the
portion of window 2 that does not overlap window 1 remains active. If a
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window overlaps any portion of internal registers, RAM, or EEPROM,
that portion is repeated in all banks associated with that window. If a
window overlaps (EP)ROM, the (EP)ROM is present in all banks with
XA[18:16] = 0:0:0.
The reset vector most commonly resides in on-chip (EP)ROM at address
$FFFE–$FFFF. However, if the (EP)ROM is disabled or mapped at
address $2000–$7FFF, the reset vector is fetched from external memory
at $FFFE–$FFFF. When expanded memory is enabled, the reset vector
is fetched from external memory at $7FFE–$7FFF, regardless of the
presence of on-chip (EP)ROM.
11.3.2 Control Registers
Expansion address lines are enabled by the port G assignment register
(PGAR). The size and position of memory windows are controlled by the
memory mapping size (MMSIZ) and memory mapping window base
(MMWBR) registers, respectively. The memory mapping window control
registers, MM1CR and MM2CR, select the particular bank or page of
expanded memory present in the window(s) at a given time.
NOTE:
Throughout this manual, the registers are discussed by function. In the
event that not all bits in a register are referenced, the bits that are not
discussed are shaded.
11.3.2.1 Port G Assignment Register
The port G assignment register (PGAR) sets each of port G pins 5:0 as
either an input/output (I/O) pin or memory expansion address line.
Clearing a bit configures the corresponding port G pin as GPIO; setting
the bit configures the pin as an expansion address line. If neither bank
uses a particular expansion address bit, the corresponding pin is
available for GPIO.
NOTE:
A special case exists for the address lines that overlap the CPU address
lines XA[15:13]. If these lines are selected as expansion address lines in
PGAR, but are not used in either window, the corresponding CPU
address line is still output on the appropriate pin.
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Address: $002D
Bit 7
6
5
4
3
2
1
Bit 0
—
—
PGAR5
PGAR4
PGAR3
PGAR2
PGAR1
PGAR0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 11-1. Port G Assignment Register (PGAR)
PGAR[5:0] — Port G Pin Assignment Bits
0 = Corresponding port G pin is GPIO.
1 = Corresponding port G pin is expansion address line XA[18:13].
11.3.2.2 Memory Mapping Size Register
The memory mapping size register (MMSIZ) sets the size of the
windows in use.
Address: $0056
Bit 7
6
5
4
3
2
1
Bit 0
MXGS2
MXGS1
W2SZ1
W2SZ0
0
0
W1SZ1
W1SZ0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-2. Memory Mapping Size Register (MMSIZ)
W2SZ[1:0] — Window 2 Size Bit
W1SZ[1:0] — Window 1 Size Bit
These bits enable the memory windows and determine their size, as
shown in Table 11-2.
Table 11-2. Window Size Select
WxSZ[1:0]
Window Size
00
Window disabled
01
8 K — Window can have up to 64 8-Kbyte banks
10
16 K — Window can have up to 32 16-Kbyte banks
11
32 K — Window can have up to 16 32-Kbyte banks
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11.3.2.3 Memory Mapping Window Base Register
The memory mapping window base register (MMWBR) defines the
starting address of each of the two windows within the CPU 64-Kbyte
address range. The windows normally begin at a boundary related to
their size (an 8-Kbyte window can begin on any 8-Kbyte boundary,
beginning at $0000).
Freescale Semiconductor, Inc...
Address: $0057
Bit 7
6
5
4
3
2
1
Bit 0
W2A15
W2A14
W2A13
0
W1A15
W1A14
W1A13
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-3. Memory Mapping Window Base Register (MMWBR)
W2A[15:13] — Window 2 Base Address Bits
Selects the three most significant bits (MSB) of the base address for
memory mapping window 2. Refer to Table 11-3.
W1A[15:13] — Window Base 1 Address Bits
Selects the three MSB of the base address for memory mapping
window 1. Refer to Table 11-3.
Table 11-3. Memory Expansion Window Base Address
MSB Bits
Window Base Address
WxA[15:13]
8 Kbytes
16 Kbytes
32 Kbytes
000
$0000
$0000
$0000
001
$2000
$0000
$0000
010
$4000
$4000
$4000
011
$6000
$4000
$4000
100
$8000
$8000
$8000
101
$A000
$8000
$8000
110
$C000
$C000
$8000
111
$E000
$C000
$8000
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11.3.2.4 Memory Mapping Window Control Registers
Each of the memory mapping window control registers (MM1CR and
MM2CR) determine the active memory bank for the corresponding
window, containing the value to be output on the expansion address
lines when the CPU selects addresses within its extended memory
window. To change banks, write the address of the new bank into the
appropriate window register.
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Address: $0058
Memory Mapping Window 1 Control Register (MM1CR)
Bit 7
6
5
4
3
2
1
Bit 0
0
X1A18
X1A17
X1A16
X1A15
X1A14
X1A13
0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Address: $0059
Memory Mapping Window 2 Control Register (MM1CR)
Read:
0
X2A18
X2A17
X2A16
X2A15
X2A14
X2A13
0
0
0
0
0
0
0
0
0
Write:
Reset:
Figure 11-4. Memory Mapping Window Control
Registers (MM1CR and MM2CR)
X1A[18:13] — Memory Mapping Window 1 Expansion Address Line
Select Bits
X2A[18:13] — Memory Mapping Window 2 Expansion Address Line
Select Bits
Each bit value written to the MMxCR registers is driven on the
corresponding port G expansion address line (if enabled by PGAR) to
enable the specified bank in the window.
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11.4 Chip Selects
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The M68HC11K Family microcontrollers contain a set of four
software-configured chip select signals which can reduce the amount of
external glue logic needed to interface the MCU to external devices in
the memory map. Each chip select signal is asserted when the CPU
accesses a memory location in its designated range, which is
determined by writes to control registers. Polarity of most chip-select
signals is programmable, as well as the segment of the address cycle
during which the signal is asserted (high E clock or address valid). Some
chip-select signals can be programmed to drive each other as well as
their own designated sections of memory (see 11.4.4 One Chip Select
Driving Another), and the bus cycle during which any chip-select signal
is asserted can be “stretched” up to three clock cycles (see 11.4.5 Clock
Stretching).
The four chip-select signals operate only in expanded modes. The
program chip select (CSPROG) is used to enable external memory in
the 64-Kbyte memory map that contains the reset vectors and program.
The chip select for I/O (CSIO) operates only within the first eight Kbytes
of the memory map. The two general-purpose chip selects, CSGP1 and
CSGP2, can enable devices anywhere in the 1-Mbyte expanded
memory space. Any port H pins 4-7 that are not used for chip-select
functions can serve as GPIO pins.
The six chip select control registers are:
•
CSCTL enables and controls most of the features in CSPROG
and CSIO.
•
GPCS1A, GPCS1C, GPCS2A, and GPCS2C define most of the
operations of the two general-purpose chip selects.
•
CSCSTR controls clock stretching for all four signals.
Table 11-4 summarizes the controls for each of the chip-select signals.
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Table 11-4. Chip Select Control Parameter Summary
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CSIO
CSPROG
Enable
IOEN in CSCTL
1 = enabled, 0 = disabled(1)
Valid
IOCSA in CSCTL
1 = address valid, 0(1) = E high
Polarity
IOPL in CSCTL
Size
IOSZ in CSCTL
1 = active high, 0 = active low(1)
1 = 4 K ($1000–$1FFF)
0 = 8 K ($0000–$1FFF)(1)
Start address
Stretch
Fixed (see size)
IO1S[A:B] in CSCSTR
Enable
Valid
Polarity
PCSEN in CSCTL
Fixed (address valid)
Fixed (active low)
Size
PCSZ[A:B] in CSCTL
Start address
Stretch
Fixed (see size)
PCS[A:B] in CSCSTR
Priority
GCSPR in CSCTL
CSGP1,
Enable
CSGP2
Valid
Set size to 0K to disable
G1AV in GPCS1C
G2AV in GPCS2C
G1POL in GPS1C
G2POL in GPS2C
Polarity
Size
Start address
Stretch
G1SZ[A:D] in GPCS1C
G1SZ[A:D] in GPCS2C
GPCS1A
GPCS2A
CSCSTR
G1DG2 in GPCS1C
G1DPC in GPCS1C
Other
G2DPC in GPCS2C
MXGS2 in MMSIZ
MXGS1 in MMSIZ
0(1), 1, 2, or 3 E clocks
1 = enabled(1), 0 = disabled
0:0 = 64 K ($0000–$FFFF)(1)
0:1 = 32 K ($8000–$FFFF)
1:0 = 16 K ($C000–$FFFF)
1:1 = 8 K ($E000–$FFFF)
0(1), 1, 2, or 3 E clocks
1 = CSGPx above CSPROG
0(1) = CSPROG above CSGPx
1 = address valid, 0 = E high (1)
1 = active high, 0 = active low(1)
2 K to 512 K in nine steps
0K = disabled(1) can also follow memory
expansion window 1 or window 2
0(1), 1, 2, or 3 E clocks
Allows CSGP1 and CSGP2 to be logically ORed
and driven out the CSGP2 pin
Allows CSGP1 and CSPROG to be logically
ORed and driven out the CSPROG pin
Allows CSGP2 and CSPROG to be logically
ORed and driven out the CSPROG pin.
Allows CSGP2 to follow either 64 K CPU
addresses or 512K expansion addresses
Allows CSGP1 to follow either 64 K CPU
addresses or 512K expansion addresses
1. Configuration at reset
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11.4.1 Program Chip Select
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The program chip select signal accesses external memory in the main
program area within the MCU’s 64-Kbyte memory map. Program chip
select validity is fixed at address valid timing and polarity is fixed at active
low. The chip-select control register (CSCTL) contains bits to enable
CSPROG, determine its priority over the general-purpose chip selects,
and set its effective address range. Clock stretching can be set from zero
to three cycles.
Address: $005B
Bit 7
6
5
4
3
2
1
Bit 0
IOEN
IOPL
IOCSA
IOSZ
GCSPR
PCSEN
PCSZA
PCSZB
0
0
0
0
0
1
0
0
Read:
Write:
Reset:
Figure 11-5. Chip-Select Control Register (CSCTL)
GCSPR — General-Purpose Chip Select Priority Bit
0 = Program chip select has priority over general-purpose chip
selects
1 = General-purpose chip selects have priority over program chip
select
PCSEN — Program Chip Select Enable Bit
0 = CSPROG disabled and port H bit 7 available as GPIO
1 = CSPROG enabled out of reset and uses port H bit 7 pin
PCSZA and PCSZB — Program Chip Select Size A Bit and Program
Chip Select Size B Bit
These bits determine the address range of CSPROG, as shown in
Table 11-5.
Table 11-5. Program Chip Select Size
PCSZA
PCSZB
Size (Bytes)
Address Range
0
0
64 K
$0000–$FFFF
0
1
32 K
$8000–$FFFF
1
0
16 K
$C000–$FFFF
1
1
8K
$E000–$FFFF
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11.4.2 Input/Output Chip Select
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The I/O chip select (CSIO) is programmable for a 4-Kbyte size located
at addresses $1000–$1FFF or 8-Kbyte size located at addresses
$0000–$1FFF. The default active-low polarity can be changed to active
high by setting the IOPL bit in CSCTL. Default validity during high E clock
can be changed to address valid time by setting the IOCSA bit in CSCTL.
Clock stretching can be set from zero to three cycles (See 11.4.5 Clock
Stretching). CSIO is disabled out of reset.
Address: $005B
Bit 7
6
5
4
3
2
1
Bit 0
IOEN
IOPL
IOCSA
IOSZ
GCSPR
PCSEN
PCSZA
PCSZB
0
0
0
0
0
1
0
0
Read:
Write:
Reset:
Figure 11-6. Chip-Select Control Register (CSCTL)
IOEN — I/O Chip-Select Enable Bit
0 = CSIO is disabled and port H bit 4 is GPIO.
1 = CSIO is enabled and uses port H bit 4.
IOPL — I/O Chip-Select Polarity Select Bit
0 = CSIO active low
1 = CSIO active high
IOCSA — I/O Chip-Select Address Valid Bit
0 = CSIO is valid during E-clock high time.
1 = CSIO is valid during address valid time.
IOSZ — I/O Chip-Select Size Select Bit
0 = CSIO size is four Kbytes at $1000–$1FFF.
1 = CSIO size is eight Kbytes at $0000–$1FFF.
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11.4.3 General-Purpose Chip Selects
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The general-purpose chip selects are the most flexible and
programmable of the chip-select signals. They can access any memory
in the expanded 1-Mbyte address space. Polarity of active state, E valid
or address valid, size, and starting address are all programmable. Clock
stretching can be set from zero to three cycles. Both signals can be
programmed to drive CSPROG, and GPCS1 can be configured to drive
GPCS2. In addition, each signal can follow a window; for instance, be
asserted whenever the CPU address falls within a selected memory
expansion window regardless of the state of the expanded address
lines.
There are two registers for each of the general-purpose chip select
signals:
•
The control register, GPS1C or GPS2C, determines the GPCS’s
active signal polarity, its valid time, which of the other chip-select
signals it can drive, and either the size of the memory it enables or
which window it follows.
•
The address register, GPS1A or GPS2A, programs the
chip-select’s starting address; valid bits in this register are
determined by the size of the address range selected by the
control register.
In addition, the MMSIZ register contains a bit for each GPCS which
determines whether it is driven by the CPU’s 64-Kbyte address lines or
the expansion address lines.
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11.4.3.1 Memory Mapping Size Register
Address: $0056
Bit 7
6
5
4
3
2
1
Bit 0
MXGS2
MXGS1
W2SZ1
W2SZ0
0
0
W1SZ1
W1SZ0
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 11-7. Memory Mapping Size Register (MMSIZ)
MXGS2 — Memory Expansion Select for GPCS 2 Bit
0 = GPCS 2 based on 64-Kbyte CPU address
1 = GPCS 2 based on expansion address
MXGS1 — Memory Expansion Select for GPCS 1 Bit
0 = GPCS 1 based on 64-Kbyte CPU address
1 = GPCS 1 based on expansion address
11.4.3.2 General-Purpose Chip Select 1 Address Register
Address: $005C
Bit 7
6
5
4
3
2
1
Bit 0
G1A18
G1A17
G1A16
G1A15
G1A14
G1A13
G1A12
G1A11
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-8. General-Purpose Chip Select 1
Address Register (GPCS1A)
G1A[18:11] — General-Purpose Chip Select 1 Address Bits
They select the starting address of GPCS1. Refer to Table 11-6.
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11.4.3.3 General-Purpose Chip Select 1 Control Register
Address: $005D
Read:
Bit 7
6
5
4
3
2
1
Bit 0
G1DG2
G1DPC
G1POL
G1AV
G1SZA
G1SZB
G1SCC
G1SZD
0
0
0
0
0
0
0
0
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 11-9. General-Purpose Chip Select 1
Control Register (GPCS1C)
G1POL — General-Purpose Chip Select 1 Polarity Select Bit
0 = CSGP1 active low
1 = CSGP1 active high
G1AV — General-Purpose Chip Select 1 Address Valid Select Bit
0 = CSGP1 is valid during E high time.
1 = CSGP1 is valid during address valid time.
G1SZ[A:D] — General-Purpose Chip Select 1 Size Bits
They select the range of GPCS1. Refer to Table 11-6.
Table 11-6. General-Purpose Chip Select 1 Size Control
G1SZ[A:D]
Size (Bytes)
Valid Bits
(MXGS1 = 0)
Valid Bits
(MXGS1 = 1)
0000
Disabled
None
None
0001
2K
G1A[15:11]
G1A[18:11]
0010
4K
G1A[15:11]
G1A[18:12]
0011
8K
G1A[15:13]
G1A[18:13]
0100
16 K
G1A[15:14]
G1A[18:14]
0101
32 K
G1A[15]
G1A[18:15]
0110
64 K
None
G1A[18:16]
0111
128 K
None
G1A[18:17]
1000
256 K
None
G1A18
1001
512 K
None
None
1010
Follow window 1
None
None
1011
Follow window 2
None
None
1100–1111
Default to 512 K
None
None
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11.4.3.4 General-Purpose Chip Select 2 Address Register
Address: $005E
Bit 7
6
5
4
3
2
1
Bit 0
G2A18
G2A17
G2A16
G2A15
G2A14
G2A13
G2A12
G2A11
0
0
0
0
0
0
0
0
Read:
Write:
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Reset:
Figure 11-10. General-Purpose Chip Select 2
Address Register (GPCS2A)
G2A[18:11] — General-Purpose Chip Select 2 Address Bits
They select the starting address of GPCS2. Refer to Table 11-7.
11.4.3.5 General-Purpose Chip Select 2 Control Register
Address: $005F
Bit 7
6
5
4
3
2
1
Bit 0
0
G2DPC
G2POL
G2AV
G2SZA
G2SZB
G2SZC
G2SZD
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-11. General-Purpose Chip Select 2
Control Register (GPCS2C)
G2POL — General-Purpose Chip Select 2 Polarity Select Bit
0 = CSGP2 active low
1 = CSGP2 active high
G2AV — General-Purpose Chip Select 2 Address Valid Select Bit
0 = CSGP2 is valid during E high time.
1 = CSGP2 is valid during address valid time.
G2SZ[A:D] — General-Purpose Chip Select 2 Size Bits
They select the range of GPCS2. Refer to Table 11-7.
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Table 11-7. General-Purpose Chip Select 2 Size Control
G2SZ[A:D]
Size
(Bytes)
Valid Bits
(MXGS2 = 0)
Valid Bits
(MXGS2 = 1)
0000
Disabled
None
None
0001
2K
G2A[15:11]
G2A[18:11]
0010
4K
G2A[15:11]
G2A[18:12]
0011
8K
G2A[15:13]
G2A[18:13]
0100
16 K
G2A[15:14]
G2A[18:14]
0101
32 K
G2A[15]
G2A[18:15]
0110
64 K
None
G2A[18:16]
0111
128 K
None
G2A[18:17]
1000
256 K
None
G2A18
1001
512 K
None
None
1010
Follow window 1
None
None
1011
Follow window 2
None
None
1100–1111
Default to 512 K
None
None
11.4.4 One Chip Select Driving Another
The general-purpose chip selects can be programmed to drive other
chip-select signals as well as their own memory areas. Although all of
the eight possible combinations of the bits G1DG2, G1DPC, and G2DPC
are allowed, some combinations cause operations which do not
perform as one might expect. The results of all combinations are defined
in Table 11-8. The priorities defined in the previous sections still apply.
The table assumes that none of the chip-select ranges overlap.
Technical Data
246
M68HC11K Family
Memory Expansion and Chip Selects
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Memory Expansion and Chip Selects
Chip Selects
11.4.4.1 General-Purpose Chip Select 1 Control Register
Address: $005D
Bit 7
6
5
4
3
2
1
Bit 0
G1DG2
G1DPC
G1POL
G1AV
G1SZA
G1SZB
G1SCC
G1SZD
0
0
0
0
0
0
0
0
Read:
Write:
Freescale Semiconductor, Inc...
Reset:
Figure 11-12. General-Purpose Chip Select 1
Control Register (GPCS1C)
G1DG2 — GPCS 1 Drives GPCS 2 Bit
0 = CSGP1 does not affect CSGP2.
1 = CSGP1 and CSGP2 are ORed and driven out of the CSGP2.
G1DPC — General-Purpose Chip Select 1 Drives Program Chip
Select Bit
0 = CSGP1 does not affect CSPROG.
1 = CSGP1 and CSPROG are ORed and driven out of the
CSPROG.
11.4.4.2 General-Purpose Chip Select 2 Control Register
Address: $005F
Bit 7
6
5
4
3
2
1
Bit 0
0
G2DPC
G2POL
G2AV
G2SZA
G2SZB
G2SZC
G2SZD
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-13. General-Purpose Chip Select 2
Control Register (GPCS2C)
G2DPC — General-Purpose Chip Select 2 Drives Program Chip
Select Bit
0 = Does not affect program chip select
1 = CSGP2 and CSPROG are ORed and driven out of the
CSPROG pin.
M68HC11K Family
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Freescale Semiconductor, Inc.
Memory Expansion and Chip Selects
Freescale Semiconductor, Inc...
Table 11-8. One Chip Select Driving Another
G1DG2
G1DPC
G2DPC
Program CS Pin
is Asserted
When Address is in:
General 2 CS Pin
is Asserted
When Address is in:
General 1 CS Pin
is Asserted
When Address is in:
0
0
0
A valid program area
A valid general 2 area
A valid general 1 area
0
0
1
A valid program
or general 2 area
Never asserted
A valid general 1 area
0
1
0
A valid program
or general 1 area
A valid general 2 area
Never asserted
0
1
1
A valid program
or general 1 or 2 area
Never asserted
Never asserted
1
0
0
A valid program area
A valid general 2
or general 1 area
Never asserted
1
0
1
A valid program
or general 2 area
Never asserted
A valid general 1 area
1
1
0
A valid program
or general 1 area
A valid general 2 area
Never asserted
1
1
1
A valid program
or general 1 or 2 area
Never asserted
Never asserted
11.4.5 Clock Stretching
Chip select and bus control signals are synchronized with the external
E clock. To accommodate devices that are slower than the MCU, the
E clock can be stretched when a chip select is asserted so that it remains
high for one to three extra bus cycles. During this stretch, which can
occur only during accesses to addresses in that chip select’s address
range, the other clocks continue running normally, maintaining the
integrity of the timers and baud generators. Each chip select has two
associated bits in the chip-select clock stretch (CSCSTR) register that
set its clock stretching from zero (disabled) to three cycles.
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Memory Expansion and Chip Selects
Memory Expansion Examples
Address: $005A
Bit 7
6
5
4
3
2
1
Bit 0
IOSA
IOSB
GP1SA
GP1SB
GP2SA
GP2SB
PCSA
PCSB
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 11-14. Chip Select Clock Stretch Register (CSCSTR)
Freescale Semiconductor, Inc...
IOS[A:B] — CSIO Stretch Select Bits
GP1S[A:B] — CSGP1 Stretch Select Bits
GP2S[A:B] — CSGP2 Stretch Select Bits
PCS[A:B] — CSPROG Stretch Select Bits
Each of these pairs of bits contain the binary number of cycles of clock
stretch, as shown in Table 11-9.
Table 11-9. CSCSTR Bits Versus Clock Cycles
Bit [A:B]
Clock Stretch
00
None
01
1 cycle
10
2 cycles
11
3 cycles
11.5 Memory Expansion Examples
The first example, shown in Figure 11-15 contains a system with
64 Kbytes of external memory to be accessed through a single 8-Kbyte
window. To access eight Kbytes, or 213 address locations, the CPU will
need 13 address lines, ADDR[12:0]. The number of memory banks
needed is the total memory, 64 Kbytes divided by the window size, eight
Kbytes. This yields eight memory banks, or 23. Thus, three expansion
lines are required, so expansion address lines XA[15:13] replace CPU
address lines ADDR[15:13]. Figure 1-1 shows a memory map and
schematic drawing of this system.
M68HC11K Family
MOTOROLA
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Memory Expansion and Chip Selects
WINDOW 1
$0000
$1000
EE/REG/RAM
$4000
CHIP SELECT 1
$04000
$14000
$24000
$34000
$44000
$54000
$64000
$74000
BANK 0
BANK 1
BANK2
BANK 3
BANK 4
BANK 5
BANK6
BANK 7
XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] =
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
$6000
$05FFF
$25FFF
PGAR = $07
MMWBR = $04
$A000
Freescale Semiconductor, Inc...
$15FFF
MMSIZ = $41
INTERNAL
(EP)ROM
CSCTL
GPCS1A
GPCS1C
GPCS2A
GPCS2C
$FFFF
=
=
=
=
=
$00
$00
$06
$00
$00
$35FFF
$45FFF
$55FFF
E
GPCS2
GPCS1
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
VDD
27C512
XA18
XA17
XA16
XA15
XA14
XA13
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
$75FFF
XA[15:13]
Window 1 @ $4000
Window 2 disabled
Window 1 = 8 Kbytes
Window 2 disabled
General-purpose chip select 1 based on
expanded address
No I/O or program chip selects
General-purpose chip select 1 starting address = $00000
64 Kbyte range (8 x 8 K)
N/A
General-purpose chip select 2 disabled
MC68HC(7)11K
R/W
$65FFF
VCC
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
CE
VSS
D7
D6
D5
D4
D3
D2
D1
D0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 11-15. Memory Expansion Example 1 — Memory Map for a Single
8-Kbyte Window with Eight Banks of External Memory
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Memory Expansion and Chip Selects
Memory Expansion Examples
The second example system shown in Figure 11-16 contains two
memory windows. The first window is organized as in the previous
example, 8 banks of 8 Kbytes each. The second window accesses
256 Kbytes of memory in 16 banks of 16 Kbyte each. To access
16 Kbytes, or 214 address locations, the CPU will need 14 address lines,
ADDR[13:0]. Since ADDR13 is driven on XA13 in this example, XA13
replaces ADDR13 to drive the A13 line in the 6226 devices, but ADDR13
could be used as well. 16 (24) memory banks require four expansion
address lines, A[17:14]. Refer to Figure 11-16 for a memory map and
schematic drawing of this system.
$0000
$1000
WINDOW 1
EE/REG/RAM
CHIP
SELECT
1
$4000
$6000
$8000
$04000
$14000
$24000
$34000
$44000
$54000
$64000
$74000
BANK 0
BANK 1
BANK2
BANK 3
BANK 4
BANK 5
BANK6
BANK 7
XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] = XA[15:13] =
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
$05FFF
$15FFF
$25FFF
$35FFF
$45FFF
$55FFF
$65FFF
$75FFF
WINDOW 2
$A000
$08000
$18000
$28000
$38000
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 15
XA[17:14] =
0:0:0:0
XA[17:14] =
0:0:0:1
XA[17:14] =
0:0:1:0
XA[17:14] =
0:0:1:1
XA[17:14] =
0:1:0:0
XA[17:14] =
1:1:1:1
$0BFFF
$1BFFF
$48000
$F8000
CHIP
SELECT
2
$C000
INTERNAL
(EP)ROM
$FFFF
PGAR = $1F
MMWBR = $84
MMSIZ = $E1
XA[17:13]
Window 1 @ $4000
Window 2 @ $8000
Window 1 = 8 Kbytes
Window 2 = 16 Kbytes
GPCS1, GPCS2 based
on expansion address
$2BFFF
CSCTL
GPCS1A
GPCS1C
GPCS2A
GPCS2C
=
=
=
=
=
$3BFFF
$00
$00
$06
$00
$08
$4BFFF
$FBFFF
No I/O or program chip selects
General-purpose chip select 1 from $00000
64 KByte range (8 x 8 K)
General-purpose chip select 2 from $00000
256 KByte range (16 x 16 K)
Figure 11-16. Memory Expansion Example 2 (Sheet 1 of 2)
Memory Map for One 8-Kbyte Window with Eight Banks and
One 16-Kbyte Window with 16 Banks of External Memory
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VDD
27C512
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
Freescale Semiconductor, Inc...
MC68HC(7)11K
GPCS1
GPCS2
R/W
E
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
XA18
XA17
XA16
XA15
XA14
XA13
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
XA17
XA16
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
XA17
XA16
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
E2
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
OE
CE
VSS
D7
D6
D5
D4
D3
D2
D1
D0
6226
(HIGH)
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
VDD
VCC
OE
W
E1
VSS
D7
D6
D5
D4
D3
D2
D1
D0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
XA17
XA16
XA15
XA14
XA13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
6226
(LOW)
VDD
E2
VCC
OE
W
E1
VSS
D7
D6
D5
D4
D3
D2
D1
D0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 11-16. Memory Expansion Example 2 (Sheet 2 of 2)
Memory Map for One 8-Kbyte Window with Eight Banks and
One 16-Kbyte Window with 16 Banks of External Memory
Technical Data
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Technical Data — M68HC11K Family
Section 12. Electrical Characteristics
Freescale Semiconductor, Inc...
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
12.3
Maximum Ratings for Standard Devices . . . . . . . . . . . . . . . . 254
12.4
Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
12.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
12.7
Power Dissipation Characteristics . . . . . . . . . . . . . . . . . . . . . 257
12.8
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
12.9
Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
12.10 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . 265
12.11 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
12.12 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . 269
12.13 EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .272
M68HC11K Family
MOTOROLA
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Electrical Characteristics
12.2 Introduction
This section contains electrical parameters for standard and extended
voltage devices. When applicable, extended voltage parameters are
shown separately. Diagrams apply to both standard and extended
voltage devices.
12.3 Maximum Ratings for Standard Devices
Freescale Semiconductor, Inc...
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 12.6 Electrical Characteristics for guaranteed
operating conditions.
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Input voltage
VIn
–0.3 to +7.0
V
Current drain per pin(1) excluding VDD,
VSS, AVDD, VRH, and VRL
ID
25
mA
TSTG
–55 to +150
°C
Storage temperature
1. One pin at a time, observing maximum power dissipation limits
NOTE:
This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIn and VOut be constrained to the
range VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD).
Technical Data
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M68HC11K Family
Electrical Characteristics
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Electrical Characteristics
Functional Operating Range
12.4 Functional Operating Range
Rating
Symbol
Value
Unit
TA
TL to TH
−40 to +85
−40 to +105
−40 to +125
°C
VDD
5.0 ± 10%
V
Symbol
Value
Unit
Average junction temperature
TJ
TA + (PD × ΘJA)
°C
Ambient temperature
TA
User-determined
°C
Operating temperature range
MC68HC(7)11KC
MC68HC(7)11KV
MC68HC(7)11KM
Freescale Semiconductor, Inc...
Operating voltage range
12.5 Thermal Characteristics
Characteristic
Package thermal resistance (junction-to-ambient)
80-pin low-profile quad flat pack
68-pin plastic leaded chip carrier
68-pin windowed ceramic cerquad (EPROM)
84-pin plastic leaded chip carrier
80-pin quad flat pack
84-pin J-cerquad
ΘJA
Total power dissipation(1)
PD
PINT + PI/O
K / TJ + 273 °C
W
Device internal power dissipation
PINT
IDD × VDD
W
I/O pin power dissipation(2)
PI/O
User-determined
W
A constant(3)
K
80
50
60
50
85
50
°C/W
PD × (TA + 273°C) +
ΘJA × PD2
W/°C
1. This is an approximate value, neglecting PI/O.
2. For most applications, PI/O ≤ PINT and can be neglected.
3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium).
Use this value of K to solve for PD and T J iteratively for any value of TA.
M68HC11K Family
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Electrical Characteristics
12.6 Electrical Characteristics
Characteristic(1)
Symbol
Min
Max
Unit
VOL
VOH
—
VDD – 0.1
0.1
—
V
Output high voltage, ILoad = – 0.8 mA, VDD = 4.5 V(2)
All outputs except XTAL, RESET, and MODA
VOH
VDD – 0.8
—
V
Output low voltage, ILoad = 1.6 mA
All outputs except XTAL
VOL
—
0.4
V
Input high voltage
All inputs except RESET
RESET
VIH
0.7 x VDD
0.8 x VDD
VDD + 0.3
VDD + 0.3
V
Input low voltage
All Inputs
VIL
VSS – 0.3
0.2 x VDD
V
IOZ
—
±10
µA
Input leakage current, VIn = VDD or VSS(3)
IRQ, XIRQ on standard devices
MODB/VSTBY, XIRQ on EPROM devices
IIn
—
—
±1
±10
µA
Input current with pullup resistors, VIn = VIL
Ports B, F, G, and H
lIPR
100
500
µA
RAM standby voltage, power down
VSB
2.0
VDD
V
RAM standby current, power down
ISB
—
10
µA
Input capacitance
PE[7:0], IRQ, XIRQ, EXTAL
Ports A, B, C, D, F, G, H, MODA/LIR, RESET
CIn
—
—
8
12
pF
Output load capacitance
All outputs except PD[4:1], XOUT, XTAL, MODA/LIR
PD[4:1]
XOUT
CL
—
—
—
90
200
30
Freescale Semiconductor, Inc...
Output voltage, ILoad = ± 10.0 µA(2))
All outputs except XTAL
All outputs except XTAL, RESET, and MODA
I/O ports, three-state leakage, VIn = VIH or VIL
Ports A, B, C, D, F, G, H, MODA/LIR, RESET
pF
1. V DD = 5.0 Vdc ± 10%, V SS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. V OH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification not
applicable to ports C and D in wired-OR mode.
3. Refer to 12.10 Analog-to-Digital Converter Characteristics for leakage current for port E.
Technical Data
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M68HC11K Family
Electrical Characteristics
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Electrical Characteristics
Power Dissipation Characteristics
12.7 Power Dissipation Characteristics
Characteristic
Freescale Semiconductor, Inc...
Maximum total supply current(1)
RUN:
Single-chip mode
Expanded mode
Slow mode
Symbol
2 MHz
3 MHz
4 MHz
Unit
IDD
27
35
6.5
33
42
7.0
40
50
7.5
mA
10
12
3.5
15
17
4.5
20
22
5.5
WAIT: (All peripheral functions shut down)
Single-chip mode
Expanded mode
Slow mode
WIDD
STOP: (No clocks)
Single-chip mode
SIDD
50
50
50
µA
PD
149
193
149
193
220
275
mW
Maximum power dissipation
Single-chip mode
Expanded mode
mA
1. EXTAL is driven with a square wave; tcyc = 500 ns for 2 MHz rating; tcyc = 250 ns for 4 MHz rating;
VIL ≤ 0.2 V; VIH ≥ VDD –0.2 V; no dc loads
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Electrical Characteristics
CLOCKS,
STROBES
~ VDD
VDD – 0.8 VOLTS
0.4 VOLTS
0.4 VOLTS
~ VSS
NOMINAL
TIMING
NOMINAL
TIMING
70% OF VDD
INPUTS
20% OF VDD
NOMINAL
TIMING
~ VDD
VDD – 0.8 VOLTS
OUTPUTS
0.4 VOLTS
Freescale Semiconductor, Inc...
~ VSS
DC TESTING
CLOCKS,
STROBES
~ VDD
70% OF VDD
20% OF VDD
~ VSS
20% OF VDD
SPEC
TIMING
SPEC
TIMING
70% OF VDD
INPUTS
20% OF VDD
SPEC
TIMING
~ VDD
OUTPUTS
~ VSS
SEE NOTE 2
VDD – 0.8 VOLTS
0.4 VOLTS
70% OF VDD
20% OF VDD
AC TESTING
Notes:
1. Full test loads are applied during all DC electrical tests and AC timing measurements.
2. During AC timing measurements, inputs are driven to 0.4 volts and VDD – 0.8 volts while timing
measurements are taken at the 20% and 70% of VDD points.
Figure 12-1. Test Methods
Technical Data
258
M68HC11K Family
Electrical Characteristics
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Freescale Semiconductor, Inc.
Electrical Characteristics
Control Timing
12.8 Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
1.0 MHz
Min
2.0 MHz
3.0 MHz
4.0 MHz
Max Min Max Min Max Min Max
Unit
Frequency of operation
fo
dc
1.0
dc
2.0
dc
3.0
dc
4.0
MHz
E-clock period
tcyc
1000
—
500
—
333
—
250
—
ns
Crystal frequency
fXTAL
—
4.0
—
8.0
—
12.0
—
16.0 MHz
External oscillator frequency
4 fo
dc
4.0
dc
8.0
dc
12.0
dc
16.0 MHz
Processor control setup time
tPCSU = 1/4 tcyc + 50 ns
tPCSU = 1/4 tcyc + 75 ns
(extended voltage devices)
tPCSU
300
—
175
—
133
—
112
—
325
—
200
—
158
—
—
—
PWRSTL
16
1
—
—
16
1
—
—
16
1
—
—
16
1
—
—
tcyc
Mode programming setup time
tMPS
2
—
2
—
2
—
2
—
tcyc
Mode programming hold time
tMPH
10
—
10
—
10
—
10
—
ns
Interrupt pulse width,
IRQ edge-sensitive mode
PWIRQ = tcyc + 20 ns
PW IRQ
1020
—
520
—
353
—
270
—
ns
Wait recovery startup time
tWRS
—
4
—
4
—
4
—
4
tcyc
PWTIM
1020
—
520
—
353
—
270
—
ns
Reset input pulse width(2)
To guarantee external reset vector
Minimum input time(3)
Timer pulse width
PWTIM = tcyc + 20 ns
Input capture, pulse accumulator
ns
1. V DD = 4.5 to 5.5 Vdc for standard devices, VSS = 0 Vdc, TA = TL to TH
All timing measurements refer to 20% VDD and 70% V DD, unless otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for eight clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt.
3. Can be pre-empted by internal reset
PA[3:0]1
PA[3:0]2
PA71,3
PA72,3
PWTIM
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Figure 12-2. Timer Inputs
M68HC11K Family
MOTOROLA
Technical Data
Electrical Characteristics
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259
260
ADDRESS
MODA, MODB
RESET
E
EXTAL
VDD
FFFE
4064 tCYC
Technical Data
Electrical Characteristics
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FFFE
FFFE
FFFF
NEW
PC
FFFE
PWRSTL
FFFE
tMPS
FFFE
Figure 12-3. POR External Reset Timing Diagram
FFFE
tPCSU
Freescale Semiconductor, Inc...
FFFE
tMPH
FFFE
FFFF
NEW
PC
Freescale Semiconductor, Inc.
Electrical Characteristics
M68HC11K Family
MOTOROLA
MOTOROLA
STOP
ADDR + 1
STOP
ADDR
ADDRESS5
tSTOPDELAY3
PWIRQ
M68HC11K Family
Electrical Characteristics
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OPCODE
SP – 8
SP – 8
FFF2
(FFF4)
FFF3
(FFF5)
NEW
PC
RESUME PROGRAM WITH INSTRUCTION
WHICH FOLLOWS THE STOP INSTRUCTION.
STOP
STOP
ADDR + 1 ADDR + 2 SP…SP–7
STOP
ADDR + 1
Figure 12-4. STOP Recovery Timing Diagram
Notes:
1. Edge-sensitive IRQ pin (IRQE bit = 1)
2. Level-sensitive IRQ pin (IRQE bit = 0)
3. tSTOPDELAY = 4064 tcyc if DLY bit = 1 or 4 tcyc if DLY = 0
4. XIRQ with X bit in CCR = 1
5. IRQ or XIRQ with X bit in CCR = 0
STOP
ADDR + 1
STOP
ADDR
ADDRESS4
E
IRQ2
OR XIRQ
IRQ1
INTERNAL
CLOCKS
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Electrical Characteristics
Control Timing
Technical Data
261
262
WAIT
ADDR
WAIT
ADDR + 1
SP – 1
Technical Data
Electrical Characteristics
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––
OP
CODE
DATA
PCL
SP
Notes:
1. Edge-sensitive IRQ pin (IRQE bit = 1)
2. Level-sensitive IRQ pin (IRQE bit = 0)
R/W
NEXT
OP + 1
NEXT
OPCODE
PWIRQ
tPCSU
SP – 8
SP – 8…SP – 8
SP – 8
tPCSU
SP – 8
tWRS
SP – 8
IYL
SP – 2
IYH
SP – 3
IXL
SP – 4
IXH
SP – 5
B
SP – 6
A
SP – 7
Figure 12-6. Interrupt Timing Diagram
PCH
SP – 1
CCR
SP – 8
––
SP – 8
Figure 12-5. WAIT Recovery from Inerrupt Timing Diagram
ADDRESS
OR INTERNAL
INTERRUPT
IRQ 2, XIRQ,
IRQ 1
E
SP – 2…SP – 8
PCL, PCH, YL, YH, XL,
XH, A, B, CCR
STACK REGISTERS
SP
Note: RESET also causes recovery from WAIT.
R/W
ADDRESS
IRQ, XIRQ,
OR INTERNAL
INTERRUPTS
E
Freescale Semiconductor, Inc...
VECT
MSB
VECTOR
ADDR
VECTOR
ADDR
VECT
LSB
VECTOR
ADDR + 1
VECTOR
ADDR + 1
OP
CODE
NEW
PC
NEW
PC
Freescale Semiconductor, Inc.
Electrical Characteristics
M68HC11K Family
MOTOROLA
Freescale Semiconductor, Inc.
Electrical Characteristics
Peripheral Port Timing
12.9 Peripheral Port Timing
1.0 MHz
Characteristic(1)
3.0 MHz
4.0 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
fo
dc
1.0
dc
2.0
dc
3.0
dc
4.0
MHz
tcyc
1000
—
500
—
333
—
250
—
ns
Peripheral data setup time(2)
MCU read of ports A, B, C, D, E,
F, G, and H
tPDSU
100
Peripheral data hold time
MCU read of ports A, B, C, D, E,
F, G, and H
tPDH
50
—
50
—
50
—
50
—
—
200
—
200
—
200
—
200
—
350
—
225
—
183
—
162
—
250
—
250
—
250
—
—
—
400
—
225
—
233
—
—
Frequency of operation (E clock)
E-clock period
Freescale Semiconductor, Inc...
2.0 MHz
Symbol
Delay time, peripheral data write
Standard devices
MCU write to port A, B, G, and H
MCU write to ports C, D, and F
(tPWD = 1/4 tcyc + 100 ns)
Extended voltage
MCU write to port A, B, G, and H
MCU write to ports C, D, and F
(tPWD = 1/4 tcyc + 150 ns)
tPWD
100
100
100
ns
ns
ns
1. VDD = 4.5 to 5.5 Vdc for standard devices, VSS = 0 Vdc, TA = TL to TH
All timing measurements refer to 20% VDD and 70% V DD, unless otherwise noted.
2. Ports C and D timing is valid only in active drive mode. (CWOM and DWOM bits are cleared in OPT2 and SPCR registers,
respectively.)
M68HC11K Family
MOTOROLA
Technical Data
Electrical Characteristics
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Freescale Semiconductor, Inc.
Electrical Characteristics
MCU READ OF PORT
E
tPDSU
tPDH
PORTS A, C, D, F
tPDSU
tPDH
Freescale Semiconductor, Inc...
PORTS B, E, G
Figure 12-7. Port Read Timing Diagram
MCU WRITE TO PORT
E
tPWD
PORTS C, D, F
PREVIOUS PORT DATA
NEW DATA VALID
tPWD
PORTS A, B, G, H
PREVIOUS PORT DATA
NEW DATA VALID
Figure 12-8. Port Write Timing Diagram
Technical Data
264
M68HC11K Family
Electrical Characteristics
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Freescale Semiconductor, Inc.
Electrical Characteristics
Analog-to-Digital Converter Characteristics
12.10 Analog-to-Digital Converter Characteristics
Max
Freescale Semiconductor, Inc...
Characteristic(1)
Parameter
Min Absolute fo ≤ 2.0
MHz
fo > 2.0
Unit
MHz(2)
Resolution
Number of bits resolved by A/D converter
—
8
—
—
Bits
Non-linearity
Maximum deviation from the ideal A/D
transfer characteristics
—
—
± 1/2
±1
LSB
Zero error
Difference between the output of an ideal and an
actual for zero input voltage
—
—
± 1/2
±1
LSB
Full scale
error
Difference between the output of an ideal and an
actual A/D for full-scale input voltage
—
—
± 1/2
±1
LSB
Total unadjusted Maximum sum of non-linearity, zero error, and
error
full-scale error (3)
—
—
± 1/2
± 1 1/2
LSB
Quantization
error
Uncertainty because of converter resolution
—
—
± 1/2
± 1/2
LSB
Absolute
accuracy
Difference between the actual input voltage and the
full-scale weighted equivalent of the binary output
code, all error sources included
—
—
±1
±2
LSB
Conversion
range
Analog input voltage range
VRL
—
VRH
VRH
V
VRH
Maximum analog reference voltage(3)
VRL
—
VRL
Minimum analog reference voltage(3)
∆VR
Minimum difference between VRH and VRL(3)
Conversion
time
Total time to perform a single analog-to-digital
conversion:
E clock
Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase
in input voltage and has no missing codes
Zero Input
reading
Conversion result when VIn = VRL
00
—
Full Scale
reading
Conversion result when VIn = VRH
—
—
VSS
VDD + 0.1 VDD + 0.1
V
—
VRH
VRH
V
3
—
—
—
V
—
—
32
—
—
tcyc + 32
—
tcyc + 32
tcyc
µs
—
—
Hex
FF
FF
Hex
–0.1
Guaranteed
Continued
M68HC11K Family
MOTOROLA
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Electrical Characteristics
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Freescale Semiconductor, Inc.
Electrical Characteristics
Max
Freescale Semiconductor, Inc...
Characteristic(1)
Parameter
Min Absolute fo ≤ 2.0
MHz
fo > 2.0
Unit
MHz(2)
Sample
acquisition time
Analog input acquisition sampling time:
E Clock
Internal RC Oscillator
—
—
12
—
—
12
—
12
tcyc
µs
Sample/hold
capacitance
Input capacitance during sample PE[7:0]
—
20 (Typ)
—
—
pF
Input leakage
Input leakage on A/D pins
PE[7:0]
VRL, VRH
—
—
—
—
400
1.0
400
1.0
nA
µA
1. VDD = 4.5 to 5.5 Vdc for standard devices; VSS = 0 Vdc, TA = TL to TH Source impedances greater than 10 kΩ affect
accuracy adversely because of input leakage.
All timing measurements refer to 20% VDD and 70% V DD, unless otherwise noted.
2. Up to 4.0 MHz for standard devices.
3. Performance is verified down to 2.5 V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5 V ±10%.
Technical Data
266
M68HC11K Family
Electrical Characteristics
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MOTOROLA
Freescale Semiconductor, Inc.
Electrical Characteristics
Expansion Bus Timing
12.11 Expansion Bus Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Num
Symbol
2.0 MHz
3.0 MHz
4.0 MHz
Min
Max
Min
Max
Min
Max
Unit
Frequency of operation (E clock)(2)
fo
dc
2.0
dc
3.0
dc
4.0
MHz
1
Cycle time, tcyc = 1/fo
tcyc
500
—
333
—
250
—
ns
2
Pulse width, E low, PW EL = 1/2 tcyc – 20 ns
PWEL
230
—
147
—
105
—
ns
3
Pulse width, E high(3)
PW EH = 1/2 tcyc – 25 ns
PW EH
225
—
142
—
100
—
ns
tr
tf
—
—
20
20
—
—
20
18
—
—
20
15
ns
4A
4B
E clock
Rise time
Fall time
9
Address hold time, tAH = 1/8 tcyc – 10 ns
tAH
53
—
32
—
21
—
ns
11
Address delay time, tAD = 1/8 tcyc + 40 ns
tAD
—
103
—
82
—
71
ns
12
Address valid time to E rise
tAV = PW EL – tAD
tAV
128
—
65
—
34
—
ns
17
Read data setup time
tDSR
30
—
30
—
20
—
ns
18
Read data hold time
tDHR
0
—
0
—
0
—
ns
19
Write data delay time
tDDW
—
40
—
40
—
40
ns
21
Write data hold time, tDHW = 1/8 tcyc
tDHW
63
—
42
—
31
—
ns
29
MPU address access time(3)
tACCA = tcyc – tf – tDSR – tAD
tACCA
348
—
203
—
144
—
ns
39
Write data setup time(3)
tDSW = PWEH – tDDW
tDSW
185
—
102
—
60
—
ns
50
E valid chip-select delay time
tECSD
—
40
—
40
—
40
ns
tECSA
155
—
72
—
40
—
ns
tCH
0
20
0
20
0
20
ns
(3)
51
E valid chip-select access time
tECSA = PWEH – tECSD – tDSR
52
Chip select hold time
54
Address valid chip-select delay time
tACSD = 1/4 tcyc + 40 ns
tACSD
—
165
—
123
—
103
ns
55
Address valid chip-select access time
tACSA = tcyc – tf – tDSR – tACSD(3)
tACSA
285
—
162
—
113
—
ns
56
Address valid to chip-select time
tAVCS
10
—
10
—
10
—
ns
57
Address valid to data three-state time
tAVDZ
—
10
—
10
—
10
ns
1. VDD = 5.0 ± 10%, V SS = 0 Vdc, TA = TL to TH, unless otherwise noted
All timing measurements refer to 20% VDD and 70% V DD, unless otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance.
3. This parameter is affected by clock stretching. Add n(tcyc) to parameter value, where n = 1, 2, or 3 depending on values
written to CSCSTR register or n = 1 for STRCH = 1 on KS parts.
M68HC11K Family
MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Characteristics
1
3
2
4B
E
4A
11
12
9
R/W, ADDRESS
17
29
18
Freescale Semiconductor, Inc...
READ DATA
57
19
39
21
WRITE DATA
50
51
52
CS E VALID
56
55
CS AD VALID
54
Figure 12-9. Expansion Bus Timing
Technical Data
268
M68HC11K Family
Electrical Characteristics
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MOTOROLA
Freescale Semiconductor, Inc.
Electrical Characteristics
Serial Peripheral Interface Timing
12.12 Serial Peripheral Interface Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Num
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fop(m)
fop(s)
fo/128
dc
fo/2
fo
MHz
1
Cycle time
Master
Slave
tcyc(m)
tcyc(s)
2
1
128
—
tcyc
2
Enable lead time
Slave
tLead(s)
1
—
tcyc
3
Enable lag time
Slave
1
—
tcyc
4
Clock (SCK) high time
Master
Slave
tw(SCKH)m
tw(SCKH)s
tcyc – 25
1/2 tcyc – 25
64 tcyc
—
ns
5
Clock (SCK) low time
Master
Slave
tw(SCKL)m
tw(SCKL)s
tcyc – 25
1/2 tcyc – 25
64 tcyc
—
ns
6
Data setup time (inputs)
Master
Slave
tsu(m)
tsu(s)
30
30
—
—
ns
7
Data hold time (inputs)
Master
Slave
th(m)
th(s)
30
30
—
—
ns
8
Slave access time (time to data active from high-impedance
state)
ta
0
40
ns
9
Slave disable time (hold time
to high-impedance state)
tdis
—
50
ns
10
Data valid (after enable edge)(2)
tv(s)
—
50
ns
11
Data hold time (outputs) (after enable edge)
tho
0
—
ns
tLag(s)
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, T A = TL to TH. All timing measurements refer to 20% VDD and 70% VDD, unless
otherwise noted.
2. Capacitive load on all SPI pins is 200 pF.
M68HC11K Family
MOTOROLA
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Electrical Characteristics
SS
(INPUT)
SS IS HELD HIGH ON MASTER
1
5
SCK (CPOL = 0)
OUTPUT
SCK (CPOL = 1)
OUTPUT
(SEE NOTE)
4
5
(SEE NOTE)
6
Freescale Semiconductor, Inc...
MISO
INPUT
4
7
MSB IN
BIT 6 . . . . . . . 1
11
MOSI
OUTPUT
MASTER MSB OUT
LSB IN
10
BIT 6 . . . . . . . 1
11 (REF)
MASTER LSB OUT
Note: This first clock edge is generated internally but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS IS HELD HIGH ON MASTER
1
5
SEE NOTE
SCK (CPOL = 0)
OUTPUT
4
SCK (CPOL = 1)
OUTPUT
5
SEE NOTE
4
6
MISO
INPUT
MOSI
OUTPUT
MSB IN
10 (REF)
BIT 6 . . . . . . . 1
11
MASTER MSB OUT
7
LSB IN
10
BIT 6 . . . . . . . 1
MASTER LSB OUT
Note: This last clock edge is generated internally but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 12-10. SPI Timing Diagram (Sheet 1 of 2)
Technical Data
270
M68HC11K Family
Electrical Characteristics
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Freescale Semiconductor, Inc.
Electrical Characteristics
Serial Peripheral Interface Timing
SS
INPUT
3
1
5
SCK (CPOL = 0)
INPUT
4
2
SCK (CPOL = 1)
INTPUT
5
8
MISO
OUTPUT
Freescale Semiconductor, Inc...
9
4
SLAVE
MSB OUT
6
MOSI
INPUT
BIT 6 . . . . . . . 1
7
10
MSB IN
11
BIT 6 . . . . . . . 1
SEE
NOTE
SLAVE LSB OUT
11
LSB IN
Note: Not defined, but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS
INPUT
1
5
SCK (CPOL = 0)
INPUT
4
2
SCK (CPOL = 1)
INTPUT
3
5
8
MISO
OUTPUT
10
SEE
NOTE
4
SLAVE
MSB OUT
6
MOSI
INPUT
7
MSB IN
9
BIT 6 . . . . . . . . . . . 1
10
BIT 6 . . . . . . . . 1
SLAVE LSB OUT
11
LSB IN
Note: Not defined, but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 12-10. SPI Timing Diagram (Sheet 2 of 2)
M68HC11K Family
MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Characteristics
12.13 EEPROM Characteristics
Freescale Semiconductor, Inc...
Characteristic(1)
Temperature Range
Unit
–40 to 85°C
–40 to 105°C
–40 to 125°C
Programming time <1.0 MHz, RCO enabled (2)
1.0 to 2.0 MHz, RCO disabled
≥ 2.0 MHz (or anytime RCO enabled)
10
20
10
15
Must use RCO
15
20
Must use RCO
20
ms
Erase time(2)
Byte, row, and bulk
10
10
10
ms
10,000
10,000
10,000
Cycles
10
10
10
Years
Write/erase endurance(3)
Data retention(3)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM programming and
erasure when the E-clock frequency is below 1.0 MHz.
3. Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
Technical Data
272
M68HC11K Family
Electrical Characteristics
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MOTOROLA
Freescale Semiconductor, Inc.
Technical Data — M68HC11K Family
Section 13. Mechanical Data
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
13.3
84-Pin Plastic-Leaded Chip Carrier (Case 780) . . . . . . . . . . . 275
13.4
84-Pin J-Cerquad (Case 780A) . . . . . . . . . . . . . . . . . . . . . . .276
13.5
80-Pin Quad Flat Pack (Case 841B) . . . . . . . . . . . . . . . . . . . 277
13.6
80-Pin Low-Profile Quad Flat Pack (Case 917A) . . . . . . . . . . 278
13.7
68-Pin Plastic Leaded Chip Carrier (Case 779) . . . . . . . . . . . 279
13.8
68-Pin J-Cerquad (Case 779A) . . . . . . . . . . . . . . . . . . . . . . .280
13.2 Introduction
The M68HC11K series microcontrollers are available in:
•
84-pin plastic-leaded chip carrier (PLCC)
•
84-pin J-cerquad (ceramic windowed version of PLCC)
•
80-pin quad flat pack (QFP)
•
80-pin low-profile quad flat pack (LQFP)
•
68-pin PLCC
•
68-pin J-cerquad
M68HC11K Family
MOTOROLA
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Freescale Semiconductor, Inc.
Mechanical Data
The diagrams included in this section show the latest package
specifications available at the time of this publication. To make sure that
you have the latest information, contact one of the following:
•
Local Motorola Sales Office
•
World Wide Web at http://www.motorola.com/semiconductors
Freescale Semiconductor, Inc...
Follow the World Wide Web on-line instructions to retrieve the current
mechanical specifications.
Technical Data
274
M68HC11K Family
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Mechanical Data
84-Pin Plastic-Leaded Chip Carrier (Case 780)
13.3 84-Pin Plastic-Leaded Chip Carrier (Case 780)
B
0.007 (0.18)M T L-M S N
U
-N-
S
0.007 (0.18)M T L-M S N S
Y BRK
D
84X R
Z
Freescale Semiconductor, Inc...
-L-
R1
-M-
W
D
84
1
2X
X
V
G1
VIEW D-D
A
0.007 (0.18)S T L-M S N S
Z
R
0.007 (0.18)S T L-M S N S
E
G
C
0.004 (0.10) T
-T- SEATING
J
2X
G1
PLANE
VIEW S
H
0.007 (0.18)S T L-M S N
S
F
0.007 (0.18)S T L-M S N
S
K1
K
VIEW S
NOTES:
1. DATUMS L, M, AND N DETERMINED WHERE TOP OF LEAD
SHOULDER EXITS PACKAGE BODY AT MOLD PARTING LINE.
2. DIMENSION G1 TO BE MEASURED AT CLOSEST APPROACH
OF LEAD TO DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP AND
BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION
OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT
CAUSE THE H DIMENSION TO BE GREATER THAN 0.037
(0.94). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
R1
M68HC11K Family
MOTOROLA
INCHES
MIN
MAX
1.185 1.195
1.185 1.195
0.165 0.180
0.090 0.120
0.013 0.021
0.050 BSC
0.026 0.032
0.020
--0.025
--1.150 1.156
1.150 1.156
0.042 0.048
0.042 0.048
0.042 0.056
--- 0.020
2°
10 °
0.545 0.565
0.060
--0.025 0.045
MILLIMETERS
MIN MAX
30.10 30.35
30.10 30.35
4.20
4.57
2.29
3.05
0.33
0.53
1.27 BSC
0.66
0.81
0.51
--0.64
--29.21 29.36
29.21 29.36
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2°
10 °
13.84 14.35
1.52
--0.64
1.14
Technical Data
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
275
Freescale Semiconductor, Inc.
Mechanical Data
13.4 84-Pin J-Cerquad (Case 780A)
B
0.18 (0.007)M T N
S
-P
L
S
S
-M
S
U
0.18 (0.007)M T N
-N-
S
-P
S
L
S
-M
S
Y BRK
D
Freescale Semiconductor, Inc...
Z1
-L-
-M-
W
D
84
1
X
V
-P-
G1
0.25 (0.010)M T N
S
-P
S
L
S
-M
S
DETAIL D-D
A
0.18 (0.007)M T L
Z
S
-M
S
N
S
-P
S
S
-M
S
N
S
-P
S
R
0.18 (0.007)M T L
E
0.100 (0.004)
G
C
J
G1
0.25 (0.010)S T L
S
-M
S
H
K1
K
F
N
S
-P
S
-T-
NOTES:
1. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PACKAGE BODY AT GLASS
PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE GLASS
PROTRUSION. ALLOWABLE GLASS PROTRUSION IS
0.25 (0.010) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
5. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
DETAIL S
0.18 (0.007)M T L
S
-M
S
N
S
-P
S
0.18 (0.007)M T N
S
-P
S
L
S
-M
S
0.18 (0.007)M T L
S
-M
S
N
S
-P
S
0.18 (0.007)M T N
S
-P
S
L
S
-M
S
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
Z1
INCHES
MIN
MAX
1.185 1.195
1.185 1.195
0.165 0.180
0.090 0.110
0.013 0.021
0.050 BSC
0.026 0.032
0.020
--0.025
--1.150 1.156
1.150 1.156
0.042 0.048
0.042 0.048
0.042 0.056
--- 0.020
2°
10 °
1.110 1.130
0.040
--2°
10 °
MILLIMETERS
MIN MAX
30.10 30.35
30.10 30.35
4.20
4.57
2.29
2.79
0.33
0.53
1.27 BSC
0.66
0.81
0.51
--0.64
--29.21 29.36
29.21 29.36
1.07
1.21
1.07
1.21
1.07
1.42
--0.50
2°
10 °
28.20 28.70
1.02
--2°
10 °
DETAIL S
Technical Data
276
M68HC11K Family
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Mechanical Data
80-Pin Quad Flat Pack (Case 841B)
13.5 80-Pin Quad Flat Pack (Case 841B)
L
60
41
61
D
D
S
V
B
P
B
0.20 M C A-B
B
0.05 D
Freescale Semiconductor, Inc...
L
0.20 M H A-B
-B-
-A-
S
S
S
40
-A-,-B-,-DDETAIL A
DETAIL A
21
80
1
A
0.20 M H A-B
S
F
20
-DD
S
0.05 A-B
J
S
0.20 M C A-B
S
D
S
D
M
E
DETAIL C
C
-H-
-CSEATING
PLANE
N
DATUM
PLANE
0.20 M C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90 °
0.10
H
M
G
U
T
DATUM -HPLANE
R
K
W
X
DETAIL C
Q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD
AND IS COINCIDENT WITH THE LEAD WHERE THE
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF
THE PARTING LINE.
4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
DATUM PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT DATUM PLANE
-H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
M68HC11K Family
MOTOROLA
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
U
V
W
X
MILLIMETERS
MIN
MAX
13.90 14.10
13.90 14.10
2.15
2.45
0.22
0.38
2.00
2.40
0.22
0.33
0.65 BSC
--0.25
0.13
0.23
0.65
0.95
12.35 REF
5°
10 °
0.13
0.17
0.325 BSC
0°
7°
0.13
0.30
16.95 17.45
0.13
--0°
--16.95 17.45
0.35
0.45
1.6 REF
Technical Data
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
277
Freescale Semiconductor, Inc.
Mechanical Data
13.6 80-Pin Low-Profile Quad Flat Pack (Case 917A)
4X
-X-
4X 20 TIPS
0.20 (0.008)H L-M N
X= L, M, N
0.20 (0.008)T L-M N
80
61
1
P
C
L
60
AB
AB
G
-MVIEW Y
B
V
Freescale Semiconductor, Inc...
PLATING
-L-
3X
VIEW Y
B1
J
V1
BASE
METAL
41
20
21
D
40
-N-
U
0.13 (0.005)M T L-M S N
A1
S
SECTION AB-AB
S1
ROTATED 90 ° CLOCKWISE
A
S
C
8X
q2
0.10 (0.004) T
-H-TSEATING
PLANE
VIEW AA
(W)
C2
0.05 (0.002)S
q1
0.25 (0.010)
2X R R1
GAGE
PLANE
(K)
C1
VIEW AA
E
(Z)
q
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS
COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE
PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.
4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM
PLANE -H-.
5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE
-T-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -H-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.
DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH
TO EXCEED 0.460 (0.018). MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).
DIM
A
A1
B
B1
C
C1
C2
D
E
F
G
J
K
P
R1
S
S1
U
V
V1
W
Z
0
01
02
Technical Data
278
F
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
14.00 BSC
0.551 BSC
7.00 BSC
0.276 BSC
14.00 BSC
0.551 BSC
7.00 BSC
0.276 BSC
--1.60
--- 0.063
0.04
0.24 0.002 0.009
1.30
1.50 0.051 0.059
0.22
0.38 0.009 0.015
0.40
0.75 0.016 0.030
0.17
0.33 0.007 0.013
0.65 BSC
0.026 BSC
0.09
0.27 0.004 0.011
0.50 REF
0.020 REF
0.325 BSC
0.013 REF
0.10
0.20 0.004 0.008
16.00 BSC
0.630 BSC
8.00 BSC
0.315 BSC
0.09
0.16 0.004 0.006
16.00 BSC
0.630 BSC
8.00 BSC
0.315 BSC
0.20 REF
0.008 REF
1.00 REF
0.039 REF
0°
10 °
0°
10 °
0°
--0°
--9°
14 °
9°
14 °
M68HC11K Family
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Mechanical Data
68-Pin Plastic Leaded Chip Carrier (Case 779)
13.7 68-Pin Plastic Leaded Chip Carrier (Case 779)
0.007 M T L-M
B
Y
-N-
0.007 M T L-M
U
BRK
N
S
S
S
N
G1
0.010
S
S
D
Z
Freescale Semiconductor, Inc...
-L-
-M-
W
68
X
D
1
V
Z
VIEW D-D
A
0.007 M T L-M
R
0.007 M T L-M
S
S
N
N
S
0.004
G
J
VIEW S
G1
0.010
T L-M
S
H
S
N
0.007 M T L-M
S
N
K
VIEW S
SEATING
PLANE
S
K1
F
-T-
0.007 M T L-M
S
N
S
S
N
S
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.985 0.995
0.985 0.995
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
--0.025
--0.950 0.956
0.950 0.956
0.042 0.048
0.042 0.048
0.042 0.056
--- 0.020
2°
10 °
0.910 0.930
0.040
---
NOTES:
1. DATUMS L, M, AND N DETERMINED WHERE TOP
OF LEAD SHOULDER EXITS PLASTIC BODY AT
MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 PER
SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012.
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037. THE
DAMBAR INTRUSION(S) SHALL NOT CAUSE THE
H DIMENSION TO BE SMALLER THAN 0.025.
M68HC11K Family
MOTOROLA
S
S
E
C
T L-M
Technical Data
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
279
Freescale Semiconductor, Inc.
Mechanical Data
13.8 68-Pin J-Cerquad (Case 779A)
B
Y
-N-
0.18 (0.007)M T N
U
BRK
S
-P
0.18 (0.007)M T N
S
S
-P
L
S
S
-M
S
L
S
S
-P
-M
S
D
-L-
-M-
Freescale Semiconductor, Inc...
G1
0.25 (0.010)M T N
S
L
S
-M
S
W
68
D
1
DETAIL D-D
V
-P-
L
A
0.18 (0.007)M T L
R
0.18 (0.007)M T L
S
S
-M
-M
S
S
Z
E
C
0.010 (0.04)
G
-TJ
DETAIL S
G1
0.25 (0.010)M T L
S
H
-M
S
N
S
-P
SEATING
PLANE
N
N
S
S
-P
-P
S
S
NOTES:
1. DATUMS -L-, -M-, -N-, AND -P- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING
PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH
IS 0.25 (0.010) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
S
0.18 (0.007)M T L
S
-M
S
N
S
-P
S
0.18 (0.007)M T N
S
-P
S
L
S
-M
S
K
F
0.18 (0.007)M T L
S
-M
S
N
S
-P
S
(0.007)M
S
-P
S
L
S
-M
S
0.18
T N
DIM
A
B
C
E
F
G
H
J
K
L
R
U
V
W
G1
INCHES
MIN
MAX
0.985 0.995
0.985 0.995
0.155 0.200
0.090 0.120
0.017 0.021
0.050 BSC
0.026 0.032
0.020
--0.050 REF
0.003
--0.930 0.958
0.930 0.958
0.036 0.044
0.036 0.044
0.890 0.930
MILLIMETERS
MIN MAX
25.02 25.27
25.02 25.27
3.94
5.08
2.29
3.05
0.43
0.48
1.27 BSC
0.66
0.81
0.51
--1.27 REF
0.08
--23.62 24.33
23.62 24.33
0.91
1.12
0.91
1.12
22.61 23.62
DETAIL S
Technical Data
280
M68HC11K Family
Mechanical Data
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Technical Data — M68HC11K Family
Section 14. Ordering Information
Freescale Semiconductor, Inc...
Use Table 14-1 to determine part numbers when placing an order.
Table 14-1. M68HC11K Family Devices
ROM
or EPROM
RAM
EEPROM
I/O
Chip
Select
Slow
Mode
MC68HC(L)11K0
MC68HC(L)11K1
MC68HC(L)11K4
0
0
24 K
768
768
768
0
640
640
37
37
62
Yes
Yes
Yes
No
No
No
MC68HC711K4
24 K
768
640
62
Yes
No
84-pin J-cerquad(3)
84-pin PLCC
80-pin QFP
MC68HC11KS2
32 K
1K
640
51
No
Yes
68-pin PLCC
80-pin LQFP(4)
MC68HC711KS2
32 K
1K
640
51
No
Yes
68-pin PLCC
80-pin LQFP
68-pin J-cerquad
Device
Number
Packages
84-pin PLCC(1)
80-pin QFP(2)
1. PLCC = Plastic leaded chip carrier
2. QFP = Quad flat pack
3. J-cerquad = Ceramic windowed version of PLCC
4. LQFP = Low-profile quad flat pack
M68HC11K Family
MOTOROLA
Technical Data
Ordering Information
For More Information On This Product,
Go to: www.freescale.com
281
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Ordering Information
Technical Data
282
M68HC11K Family
Ordering Information
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Technical Data — M68HC11K Family
Section 15. Development Support
Freescale Semiconductor, Inc...
Motorola has developed tools for use in debugging and evaluating
M68HC11 equipment. Specific development tools for use with the
M68HC11K series include:
•
M68HC11KEVS evaluation system
•
M68HC711KPGMR programmer board
•
M68HC711KEVB evaluation board
For more information about Motorola and third party development
system hardware and software, contact one of the following:
•
Local Motorola Sales Office
•
World Wide Web at http://www.motorola.com/semiconductors
M68HC11K Family
MOTOROLA
Technical Data
Development Support
For More Information On This Product,
Go to: www.freescale.com
283
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Development Support
Technical Data
284
M68HC11K Family
Development Support
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Technical Data — M68HC11K Family
Index
B
Freescale Semiconductor, Inc...
BAUD Baud Rate
SCP[1:0] SCI Baud Rate Prescaler Selects . . . . . . . . . . . . . . 159
C
CFORC Timer Compare Force
FOC[1:5] Force Output Comparison . . . . . . . . . . . . . . . . . . . . 201
CONFIG System Configuration
NOCOP ROM/PROM Enable . . . . . . . . . . . . . . . . . . . . . . . . . 108
ROMON ROM/PROM Enable . . . . . . . . . . . . . . . . . . . . . . . 88, 89
H
HPRIO Highest Priority I-Bit Interrupt and Miscellaneous
MDA Mode Select A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
PSEL[3:0] Priority Select Bits . . . . . . . . . . . . . . . . . . . . . . . . . 123
RBOOT Read Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . 80
SMOD Special Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I
INIT RAM and I/O Mapping Register
RAM[3:0] RAM Map Position. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
REG[3:0] Register Block Position . . . . . . . . . . . . . . . . . . . . . . . 84
L
LIRDV LIR Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
O
OC1D Output Compare 1 Data
OC1D[7:3] Output Compare Masks. . . . . . . . . . . . . . . . . . . . . 203
OC1M Output Compare 1 Mask
OC1M[7:3] Output Compare 1 Masks . . . . . . . . . . . . . . . . . . . 202
M68HC11K Family
MOTOROLA
Technical Data
Index
For More Information On This Product,
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285
Freescale Semiconductor, Inc.
Index
OPTION System Configuration Options
CME Clock Monitor Enable . . . . . . . . . . . . . . . . . . . . . . . . . . .
CR[1:0] COP Timer Rate Select Bits. . . . . . . . . . . . . . . . . . . .
DLY Enable Oscillator Startup Delay. . . . . . . . . . . . . . . . . . . .
IRQE Configure IRQ for Edge-Sensitive Operation. . . . . . . . .
111
109
132
121
P
Freescale Semiconductor, Inc...
PACTL Pulse Accumulator Control
I4/O5 Input Capture 4/Output Compare 5 . . . . . . . . . . . . . . . . 191
PAEN Pulse Accumulator System Enable. . . . . . . . . . . . . . . . 205
PAMOD Pulse Accumulator Mode . . . . . . . . . . . . . . . . . . . . . 206
RTR[1:0] Real Time Interrupt Rate Select. . . . . . . . . . . . . . . . 210
PPROG EPROM Programming Control
ELAT PROM Latch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
S
SCCR1 SCI Control Register 1
M Mode (SCI Word Size). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
WAKE Wakeup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SCCR2 SCI Control Register 2
ILIE Idle Line Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . 161
RE Receiver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
RIE Receiver Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . . 161
RWU Receiver Wakeup Control . . . . . . . . . . . . . . . . . . . . . . . 162
TCIE Transmit Complete Interrupt Enable . . . . . . . . . . . . . . . 161
TE Transmitter Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
TIE Transmit Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . 161
SCI Control Register 2
SBK Send Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SCSR SCI Status Register
FE Framing Error Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
IDLE Idle Line Detected Flag. . . . . . . . . . . . . . . . . . . . . . . . . . 163
NF Noise Error Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
OR Overrun Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
RDRF Receive Data Register Full Flag. . . . . . . . . . . . . . . . . . 163
TC Transmit Complete Flag . . . . . . . . . . . . . . . . . . . . . . . . . . 163
TDRE Transmit Data Register Empty Flag . . . . . . . . . . . . . . . 163
Technical Data
286
M68HC11K Family
Index
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MOTOROLA
Freescale Semiconductor, Inc.
Index
Freescale Semiconductor, Inc...
SPCR Serial Peripheral Control Register
CPHA Clock Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPOL Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DWOM Port D Wired-OR Mode. . . . . . . . . . . . . . . . . . . . . . . .
MSTR Master Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPE Serial Peripheral System Enable. . . . . . . . . . . . . . . . . . .
SPR[1:0] SPI Clock Rate Selects . . . . . . . . . . . . . . . . . . . . . .
SPSR Serial Peripheral Status Register
MODF Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPIF SPI Transfer Complete Flag . . . . . . . . . . . . . . . . . . . . . .
WCOL Write Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
175
174
174
174
175
176
176
176
T
TCTL1 Timer Control 1
OM[2:5] Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
TCTL2 Timer Control 2
EDGxB and EDGxA Input Capture Edge Control . . . . . . . . . . 195
TFLG1 Timer Interrupt Flag 1
I4/O5F Input Capture 4/Output Compare 5 Flag . . . . . . . 194, 199
IC1F–IC3F Input Capture x Flag . . . . . . . . . . . . . . . . . . . . . . . 194
OC1F–OC4F Output Compare x Flag . . . . . . . . . . . . . . . . . . . 199
TFLG2 Timer Interrupt Flag 2
PAIF Pulse Accumulator Input Edge Flag . . . . . . . . . . . . . . . . 207
PAOVF Pulse Accumulator Overflow Flag . . . . . . . . . . . . . . . 207
RTIF Real-Time Interrupt Flag. . . . . . . . . . . . . . . . . . . . . . . . . 209
TOF Timer Overflow Interrupt Flag . . . . . . . . . . . . . . . . . . . . . 189
TMSK1 Timer Interrupt Mask 1
I4/O5I Input Capture 4
or Output Compare 5 Interrupt Enable . . . . . . . 195, 200
IC1I–IC3I Input Capture x Interrupt Enable . . . . . . . . . . . . . . . 194
OC1I–OC4 Output Compare x Interrupt Enable . . . . . . . . . . . 200
TMSK2 Timer Interrupt Mask 2
PR[1:0] Timer Prescaler Select . . . . . . . . . . . . . . . . . . . . . . . . 190
RTII Real-time Interrupt Enable. . . . . . . . . . . . . . . . . . . . . . . . 209
TOI Timer Overflow Interrupt Enable. . . . . . . . . . . . . . . . . . . . 189
M68HC11K Family
MOTOROLA
Technical Data
Index
For More Information On This Product,
Go to: www.freescale.com
287
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Freescale Semiconductor, Inc...
Index
Technical Data
288
M68HC11K Family
Index
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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Freescale Semiconductor, Inc...
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M68HC11K/D
M68H11E Series Technical Data
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