TI1 MUX36D04IPWR Low-capacitance, low-leakage-current, precision, analog multiplexer Datasheet

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MUX36S08, MUX36D04
SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
MUX36xxx 36-V, Low-Capacitance, Low-Leakage-Current, Precision, Analog Multiplexers
1 Features
3 Description
•
The MUX36S08 and MUX36D04 (MUX36xxx) are
modern complementary metal-oxide semiconductor
(CMOS)
analog
multiplexers
(muxes).
The
MUX36S08 offers 8:1 single-ended channels;
whereas, the MUX36D04 offers differential 4:1 (8:2)
channels. The MUX36S08 and MUX36D04 work
equally well with either dual supplies (±5 V to ±18 V)
or a single supply (10 V to 36 V). They also perform
well with symmetric supplies (such as VDD = 12 V,
VSS = –12 V), and unsymmetric supplies (such as
VDD = 12 V, VSS = –5 V). All digital inputs have TTLlogic compatible thresholds, ensuring both TTL and
CMOS logic compatibility when operating in the valid
supply voltage range.
1
•
•
•
•
•
•
•
•
•
•
•
•
Low On-Capacitance
– MUX36S08: 9.4pF
– MUX36D04: 6.7pF
Low Input Leakage: 1 pA
Low Charge Injection: 0.3 pC
Rail-to-Rail Operation
Wide Supply Range: ±5 V to ±18 V, 10 V to 36 V
Low On-Resistance: 125 Ω
Transition Time: 92 ns
Break-Before-Make Switching Action
EN Pin Connectable to VDD
Logic Levels: 2 V to VDD
Low Supply Current: 45 µA
ESD Protection HBM: 2000 V
Industry-Standard TSSOP Package
The MUX36S08 and MUX36D04 have very low on
and off leakage currents, allowing these multiplexers
to switch signals from high input impedance sources
with minimal error. A low supply current of 45 µA
enables use in portable applications.
Device Information(1)
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process Control
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
PART NUMBER
MUX36S08IPW
MUX36D04IPW
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
Leakage Current vs Temperature
900
ID(ON)+
Bridge Sensor
±
Thermocouple
MUX36D04
ADC
PGA/INA
+
Current
Sensing
VINP
VINM
Leakage Current (pA)
600
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)-
±300
ID(OFF)-
±600
ID(ON)Photo
LED Detector
Optical Sensor
±900
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C00
Analog Inputs
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MUX36S08, MUX36D04
SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics: Dual Supply ..................... 6
Electrical Characteristics: Single Supply................... 8
Typical Characteristics ............................................ 10
Parameter Measurement Information ................ 14
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Truth Tables ............................................................
On-Resistance ........................................................
Off Leakage.............................................................
On-Leakage Current ...............................................
Transition Time .......................................................
Break-Before-Make Delay.......................................
Turn-On and Turn-Off Time ....................................
Charge Injection ......................................................
Off Isolation .............................................................
14
15
15
16
16
17
18
19
19
8.10 Channel-to-Channel Crosstalk .............................. 20
8.11 Bandwidth ............................................................. 20
8.12 THD + Noise ......................................................... 21
9
Detailed Description ............................................ 22
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
22
22
23
25
10 Applications and Implementation...................... 26
10.1 Application Information.......................................... 26
10.2 Typical Application ............................................... 26
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 29
13 Device and Documentation Support ................. 30
13.1
13.2
13.3
13.4
13.5
13.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
14 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2015) to Revision A
•
2
Page
Changed from product preview to production data ................................................................................................................ 1
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SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
5 Device Comparison Table
PRODUCT
DESCRIPTION
MUX36S08
8-channel, single-ended analog multiplexer (8:1 mux)
MUX36D04
4-channel, differential analog multiplexer (8:2 mux)
6 Pin Configuration and Functions
MUX36S08: PW Package
16-Pin TSSOP
Top View
A0
1
16
A1
EN
2
15
A2
VSS
3
14
GND
S1
4
13
VDD
S2
5
12
S5
S3
6
11
S6
S4
7
10
S7
D
8
9
S8
Pin Functions: MUX36S08
PIN
NAME
NO.
FUNCTION
DESCRIPTION
A0
1
Digital input
Address line 0
A1
16
Digital input
Address line 1
A2
15
Digital input
Address line 2
D
8
EN
2
GND
14
S1
4
Analog input or output Source pin 1. Can be an input or output.
S2
5
Analog input or output Source pin 2. Can be an input or output.
S3
6
Analog input or output Source pin 3. Can be an input or output.
S4
7
Analog input or output Source pin 4. Can be an input or output.
S5
12
Analog input or output Source pin 5. Can be an input or output.
S6
11
Analog input or output Source pin 6. Can be an input or output.
S7
10
Analog input or output Source pin 7. Can be an input or output.
S8
9
Analog input or output Source pin 8. Can be an input or output.
VDD
13
Power supply
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
VSS
3
Power supply
Negative power supply. This pin is the most negative power-supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[2:0] logic inputs determine which switch is turned on.
Digital input
Power supply
Ground (0 V) reference
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MUX36D04: PW Package
16-Pin TSSOP
Top View
A0
1
16
A1
EN
2
15
GND
VSS
3
14
VDD
S1A
4
13
S1B
S2A
5
12
S2B
S3A
6
11
S3B
S4A
7
10
S4B
DA
8
9
DB
Pin Functions: MUX36D04
PIN
NAME
NO.
FUNCTION
DESCRIPTION
A0
1
Digital input
Address line 0
A1
16
Digital input
Address line 1
DA
8
Analog input or output Drain pin A. Can be an input or output.
DB
9
Analog input or output Drain pin B. Can be an input or output.
EN
2
GND
15
S1A
4
Analog input or output Source pin 1A. Can be an input or output.
S2A
5
Analog input or output Source pin 2A. Can be an input or output.
S3A
6
Analog input or output Source pin 3A. Can be an input or output.
S4A
7
Analog input or output Source pin 4A. Can be an input or output.
S1B
13
Analog input or output Source pin 1B. Can be an input or output.
S2B
12
Analog input or output Source pin 2B. Can be an input or output.
S3B
11
Analog input or output Source pin 3B. Can be an input or output.
S4B
10
Analog input or output Source pin 4B. Can be an input or output.
VDD
14
Power supply
Positive power supply. This pin is the most positive power supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
VSS
3
Power supply
Negative power supply. This pin is the most negative power supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
4
Digital input
Power supply
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Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[1:0] logic inputs determine which pair of switches is turned on.
Ground (0 V) reference
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Product Folder Links: MUX36S08 MUX36D04
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SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
MIN
MAX
VDD
–0.3
40
VSS
–40
0.3
VDD – VSS
Digital input pins (2)
Voltage
EN, A0, A1, A2 pins
Sx, SxA, SxB pins
Analog output pins (2)
D, DA, DB pins
VSS – 0.3
V
mA
–30
30
Voltage
VSS – 2
VDD + 2
V
Current
–30
30
mA
Voltage
VSS – 2
VDD + 2
V
Current
–30
30
mA
–55
150
Junction, TJ
150
Storage, Tstg
(2)
VDD + 0.3
Current
Operating, TA
(1)
V
40
Analog input pins (2)
Temperature
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Only one pin at a time
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Dual supply
NOM
MAX
5
18
10
36
UNIT
VDD (1)
Positive power-supply voltage
VSS (2)
Negative power-supply voltage (dual supply)
–5
–18
V
VDD – VSS
Supply voltage
10
36
V
VS
Source pins voltage (3)
VSS
VDD
V
VD
Drain pins voltage
VSS
VDD
V
VEN
Enable pin voltage
VSS
VDD
V
VA
Address pins voltage
VSS
VDD
ICH
Channel current (TA = 25°C)
–25
25
mA
TA
Operating temperature
–40
125
°C
(1)
(2)
(3)
Single supply
V
V
When VSS = 0 V, VDD can range from 10 V to 36 V.
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
VS is the voltage on all the S pins.
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7.4 Thermal Information
MUX36xxx
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
103.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
°C/W
RθJB
Junction-to-board thermal resistance
49.8
°C/W
ψJT
Junction-to-top characterization parameter
2.7
°C/W
ψJB
Junction-to-board characterization parameter
49.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics: Dual Supply
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, ICH = 1 mA
RON
On-resistance
VS = ±10 V, ICH = 1 mA
125
170
145
200
TA = –40°C to +85°C
230
TA = –40°C to +125°C
250
2.4
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, ICH = 1 mA
On-resistance flatness
On-resistance drift
VS = 10 V, 0 V, –10 V
9
TA = –40°C to +125°C
11
53
TA = –40°C to +125°C
58
VS = 0 V
0.52
Input leakage current
Switch state is off,
VS = ±10 V, VD = ±10 V (1)
ID
–0.15
0.15
–1.9
1.9
TA = -40°C to +125°C
Output leakage current
0.005
0.5
–2
2
0.008
nA
0.1
–0.5
–0.1
Switch state is on,
D = ±10 V, S = floating
%/°C
TA = –40°C to +125°C
TA = -40°C to +85°C
Ω
0.04
TA = –40°C to +85°C
–0.1
Switch state is off,
S = ±10 V, D = ±10 V (1)
0.001
Ω
45
TA = –40°C to +85°C
–0.04
IS(OFF)
6
TA = –40°C to +85°C
22
RFLAT
Ω
nA
0.1
TA = –40°C to +85°C
–0.5
0.5
TA = –40°C to +125°C
–3.3
3.3
nA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
ID
Input current
(1)
6
2.0
V
0.8
V
0.15
µA
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics: Dual Supply (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
88
136
UNIT
SWITCH DYNAMICS (2)
tON
Enable turn-on time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
144
TA = –40°C to +125°C
151
63
tOFF
Enable turn-off time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
tt
Transition time
83
TA = –40°C to +125°C
90
151
TA = –40°C to +125°C
157
Break-before-make time
delay
VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
QJ
Charge injection
CL = 1 nF, RS = 0 Ω
Off-isolation
VS = 0 V
30
54
±0.6
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channel to D, DA, DB
–96
Adjacent channel to D, DA, DB
–85
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channels
–96
Adjacent channels
–88
Input off-capacitance
f = 1 MHz, VS = 0 V
CD(OFF)
Output off-capacitance
f = 1 MHz, VS = 0 V
CS(ON),
CD(ON)
Output on-capacitance
f = 1 MHz, VS = 0 V
ns
ns
0.3
VS = –15 V to +15 V
ns
143
TA = –40°C to +85°C
tBBM
CS(OFF)
75
TA = –40°C to +85°C
92
VS = 10 V, RL = 300 Ω,
CL= 35 pF,
ns
pC
dB
dB
2.4
2.9
MUX36S08
7.5
8.4
MUX36D04
4.3
5
MUX36S08
9.4
10.6
MUX36D04
6.7
7.7
45
59
pF
pF
pF
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
TA = –40°C to +85°C
62
TA = –40°C to +125°C
83
25
VSS supply current
(2)
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
µA
34
TA = –40°C to +85°C
37
TA = –40°C to +125°C
57
µA
Specified by design, not subject to production testing.
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7.6 Electrical Characteristics: Single Supply
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
235
RON
On-resistance
VS = 10 V, ICH = 1 mA
TA = –40°C to +85°C
390
TA = –40°C to +125°C
430
3.1
ΔRON
On-resistance match
On-resistance drift
IS(OFF)
ID
Input leakage current
VS = 10 V, ICH = 1 mA
340
12
TA = –40°C to +85°C
19
TA = –40°C to +125°C
23
VS = 0 V
0.47
–-0.04
0.001
%/°C
TA = –40°C to +85°C
–0.15
0.15
TA = –40°C to +125°C
–1.9
1.9
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V (1)
TA = –40°C to +85°C
Switch state is on,
D = 1 V and 10 V, S =
floating
TA = –40°C to +85°C
–0.5
0.5
TA = –40°C to +125°C
–3.3
3.3
Output leakage current
TA = –40°C to +125°C
0.005
0.5
–2
2
0.008
nA
0.1
–0.5
–0.1
Ω
0.04
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1 V (1)
–0.1
Ω
nA
0.1
nA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
ID
Input current
2.0
V
0.8
V
0.15
µA
SWITCH DYNAMIC CHARACTERISTICS (2)
85
tON
Enable turn-on time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
145
TA = –40°C to +125°C
149
48
tOFF
Enable turn-off time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
94
TA = –40°C to +125°C
102
Transition time
87
TA = –40°C to +85°C
153
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
TA = –40°C to +125°C
155
Break-before-make time
delay
VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
QJ
Charge injection
CL = 1 nF, RS = 0 Ω
Off-isolation
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channel to D, DA, DB
-96
Adjacent channel to D, DA, DB
-85
Channel-to-channel
crosstalk
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Nonadjacent channels
–96
Adjacent channels
-88
Input off-capacitance
f = 1 MHz, VS = 6 V
CS(OFF)
CD(OFF)
Output off-capacitance
f = 1 MHz, VS = 6 V
CS(ON),
CD(ON)
Output on-capacitance
f = 1 MHz, VS = 6 V
(1)
(2)
8
30
54
VS = 6 V
0.15
VS = 0 V to 12 V,
±0.4
ns
147
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
tBBM
ns
83
TA = –40°C to +85°C
VS = 8 V, CL= 35 pF
tt
140
TA = –40°C to +85°C
ns
ns
pC
dB
dB
2.7
3.2
MUX36S08
9.1
10
MUX36D04
5
5.7
MUX36S08
10.8
12
MUX36D04
6.9
8
pF
pF
pF
When VS is 1 V, VD is 10 V, and vice versa.
Specified by design, not subject to production test.
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Electrical Characteristics: Single Supply (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
42
53
UNIT
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS= 0 V, VEN = 3.3 V
TA = –40°C to +85°C
56
TA = –40°C to +125°C
77
23
VSS supply current
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
38
TA = –40°C to +85°C
31
TA = –40°C to +125°C
51
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7.7 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
250
250
TA = 125ƒC
VDD = +13.5V VDD = +15V
VSS = -13.5V VSS = -15V
150
100
50
VDD = +18V
VSS = -18V
TA = 85ƒC
200
On Resistance (Ÿ)
On Resistance (Ÿ)
200
150
TA = 25ƒC
100
50
VDD = +16.5V
VSS = -16.5V
TA = -40ƒC
TA = 0ƒC
0
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
±18
±12
0
±6
6
12
Source or Drain Voltage (V)
C00
18
C00
VDD = 15 V, VSS = –15 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
700
700
VDD = +5V
VSS = -5V
VDD = +6V
VSS = -6V
500
600
On Resistance (Ÿ)
On Resistance (Ÿ)
600
400
300
200
VDD = +7V
VSS = -7V
100
500
TA = 85ƒC
TA = 125ƒC
400
300
TA = 25ƒC
200
100
TA = 0ƒC
TA = -40ƒC
0
0
±8
±6
±4
±2
0
2
4
6
Source or Drain Voltage (V)
0
8
2
4
6
8
10
Source or Drain Voltage (V)
C00
12
C00
VDD = 12 V, VSS = 0 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
700
250
VDD = 30V
VSS = 0V
On Resistance (Ÿ)
On Resistance (Ÿ)
200
150
100
50
VDD = 36V
VSS = 0V
VDD = 33V
VSS = 0V
VDD = 12V
VSS = 0V
500
400
VDD = 14V
VSS = 0V
300
200
100
0
0
0
6
12
18
24
Source or Drain Voltage (V)
30
36
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2
4
6
8
10
Source or Drain Voltage (V)
C02
Figure 5. On-Resistance vs Source or Drain Voltage
10
VDD = 10V
VSS = 0V
600
12
14
C00
Figure 6. On-Resistance vs Source or Drain Voltage
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Typical Characteristics (continued)
250
250
200
200
On Resistance (Ÿ)
On Resistance (Ÿ)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
100
150
100
50
50
0
0
0
6
12
18
24
Source or Drain Voltage (V)
±12
0
±6
6
VDD = 24 V, VSS = 0 V
C02
VDD = 12 V, VSS = –12 V
Figure 7. On-Resistance vs Source or Drain Voltage
Figure 8. On-Resistance vs Source or Drain Voltage
900
900
ID(ON)+
600
ID(ON)+
600
Leakage Current (pA)
Leakage Current (pA)
12
Source or Drain Voltage (V)
C02
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)-
±300
ID(OFF)-
±600
IS(OFF)+
300
ID(OFF)+
0
±300
IS(OFF)ID(OFF)-
±600
ID(ON)-
ID(ON)-
±900
±900
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
VDD = 15 V, VSS = –15 V
25
50
75
100
125
150
C00
VDD = 12 V, VSS = 0 V
Figure 9. Leakage Current vs Temperature
Figure 10. Leakage Current vs Temperature
2
2
VDD = +10V
VSS = -10V
VDD = +15V
VSS = -15V
1
Charge Injection (pC)
Charge Injection (pC)
0
Temperature (ƒC)
C00
0
VDD = 12V
VSS = 0V
-1
1
VDD = +15V
VSS = -15V
0
VDD = +10V
VSS = -10V
±1
VDD = 12V
VSS = 0V
-2
±2
±15
±10
±5
0
5
10
Source Voltage (V)
MUX36S08, source-to-drain
Figure 11. Charge Injection vs Source Voltage
15
±15
±10
±5
0
5
10
Source Voltage (V)
C00
15
C02
MUX36D04, source-to-drain
Figure 12. Charge Injection vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
VDD = +15V
VSS = -15V
6
Charge Injection (pC)
Turn On and Turn Off Times (ns)
9
VDD = +10V
VSS = -10V
3
0
VDD = 12V
VSS = 0V
±3
±6
tON (VDD = +15V, VSS = -15V)
120
tON (VDD = +12V, VSS = 0V)
90
60
30
tOFF (VDD = +15V, VSS = -15V)
tOFF (VDD = +12V, VSS = 0V)
0
±9
±15
±10
0
±5
5
10
Drain voltage (V)
15
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C01
150
C01
Drain-to-source
Figure 14. Turn-On and Turn-Off Times vs Temperature
0
0
±20
±20
Adjacent channel to D (output)
±40
Adjacent channels
±40
Crosstalk (dB)
Off Isolation (dB)
Figure 13. Charge Injection vs Source or Drain Voltage
±60
±80
±100
±60
±80
±100
±120
Non-Adjacent channels
±120
Non-Adjacent channel to D (output)
±140
±140
10k
100k
1M
10M
100M
Frequency (Hz)
1G
10k
Figure 15. Off Isolation vs Frequency
10M
100M
1G
C013
Figure 16. Crosstalk vs Frequency
3
VDD = +15V
VSS = -15V
On Response (dB)
10
THD+N (%)
1M
Frequency (Hz)
100
VDD = +5V
VSS = -5V
1
0.1
0
±3
±6
0.01
10
100
1k
10k
Frequency (Hz)
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±9
100k
1M
10M
100M
Frequency (Hz)
C014
Figure 17. THD+N vs Frequency
12
100k
C012
1G
C018
Figure 18. On Response vs Frequency
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Typical Characteristics (continued)
18
18
15
15
Capacitance (pF)
Capacitance (pF)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
12
CD(ON)
9
6
CD(OFF)
9
CD(ON)
6
CD(OFF)
CS(OFF)
3
12
3
CS(OFF)
0
0
-15
-10
-5
0
5
10
Source Voltage (V)
15
±15
±5
0
5
10
Source or Drain Voltage (V)
MUX36S08, VDD = 15 V, VSS = –15 V
15
C02
MUX36D04, VDD = 15 V, VSS = –15 V
Figure 19. Capacitance vs Source Voltage
Figure 20. Capacitance vs Source Voltage
18
18
15
15
Capacitance (pF)
Capacitance (pF)
±10
C01
12
CD(ON)
9
6
12
CD(OFF)
9
CD(ON)
6
CD(OFF)
CS(OFF)
3
3
CS(OFF)
0
0
0
5
10
15
20
25
Source Voltage (V)
0
30
20
25
30
C02
Figure 22. Capacitance vs Source Voltage
18
15
15
CD(ON)
Capacitance (pF)
Capacitance (pF)
Figure 21. Capacitance vs Source Voltage
9
CD(OFF)
CS(OFF)
3
15
MUX36D04, VDD = 30 V, VSS = 0 V
18
6
10
Source or Drain Voltage (V)
MUX36S08, VDD = 30 V, VSS = 0 V
12
5
C01
12
CD(OFF)
9
CD(ON)
6
3
CS(OFF)
0
0
0
3
6
9
Source or Drain Voltage (V)
MUX36S08, VDD = 12 V, VSS = 0 V
Figure 23. Capacitance vs Source Voltage
12
0
3
6
9
Source or Drain Voltage (V)
C02
12
C02
MUX36D04, VDD = 12 V, VSS = 0 V
Figure 24. Capacitance vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
Drain Current (mA)
15
10
5
0
±5
±10
±15
±20
±25
±25 ±20 ±15 ±10
±5
0
5
10
15
20
Source Current (mA)
25
C02
Figure 25. Source Current vs Drain Current
8 Parameter Measurement Information
8.1 Truth Tables
Table 1. MUX36S08
(1)
EN
A2
A1
A0
On-channel
0
X (1)
X (1)
X (1)
All channels are off
1
0
0
0
Channel 1
1
0
0
1
Channel 2
1
0
1
0
Channel 3
1
0
1
1
Channel 4
1
1
0
0
Channel 5
1
1
0
1
Channel 6
1
1
1
0
Channel 7
1
1
1
1
Channel 8
X denotes don't care..
Table 2. MUX36D04
(1)
14
EN
A1
A0
On-channel
0
X (1)
X (1)
All channels are off
1
0
0
Channels 1A and 1B
1
0
1
Channels 2A and 2B
1
1
0
Channels 3A and 3B
1
1
1
Channels 4A and 4B
X denotes don't care.
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8.2 On-Resistance
The on-resistance of the MUX36xxx is the ohmic resistance across the S and D pins of the device. The onresistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance. The
measurement setup used to measure RON is as shown in Figure 26. Voltage (V) and current (ICH) are measured
using this setup, and RON is computed as shown in Equation 1:
RON = V / ICH
(1)
V
S
D
ICH
VS
Figure 26. On-Resistance Measurement Setup
8.3 Off Leakage
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. It is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
It is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 27
ID (OFF)
Is (OFF)
S
A
D
VS
A
VD
Figure 27. Off-Leakage Measurement Setup
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8.4 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 28 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
ID (ON)
D
S
NC
A
NC = NO CONNECT
VD
Figure 28. On-Leakage Measurement Setup
8.5 Transition Time
Transition time is defined as the time taken by the output of the MUX36xxx to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of its transition. Figure 29 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
50%
50%
S1
VS1
A0
3V
A1
VIN
S2-S7
A2
tt
tt
90%
Output
MUX36S08
Output
VS8
S8
VS1
2V
EN
D
GND
300 Ÿ
35 pF
90%
VS8
Figure 29. Transition-Time Measurement Setup
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8.6 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from getting connected to each other when
the MUX36xxx is switching. The MUX36xxx output first breaks from the on-state switch before making the
connection with the next on-state switch. The time delay between the break and the make is known as a breakbefore-make delay. Figure 30 shows the setup used to measure break-before-make delay, denoted by the
symbol tBBM.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
S1
VS
A0
0V
A1
VIN
S2-S7
A2
S8
Output
80%
Output
MUX36S08
80%
2V
D
EN
GND
300 Ÿ
35 pF
tBBM
Figure 30. Break-Before-Make Delay Measurement Setup
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8.7 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the MUX36xxx to rise to 90% of the final value after
the enable signal has risen to 50% of its final value. Figure 31 shows the setup used to measure turn-on time.
Turn-on time is denoted by the symbol tON.
Turn off time is defined as the time taken by the output of the MUX36xxx to fall to 10% of the initial value after
the enable signal has fallen to 50% of its initial value. Figure 31 shows the setup used to measure turn-off time.
Turn-off time is denoted by the symbol tOFF.
VDD
VSS
VDD
VSS
3V
Enable
Drive (VIN)
50%
50%
S1
A0
VS
A1
S2-S8
0V
A2
tOFF (EN)
tON (EN)
MUX36S08
0.9 VS
Output
Output
D
EN
GND
0.1 VS
VIN
300 Ÿ
35 pF
Figure 31. Turn-On and Turn-Off Time Measurement Setup
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8.8 Charge Injection
The MUX36xxx have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. Figure 32 shows the setup used to measure charge injection.
VDD
VSS
VDD
VSS
A0
3V
A1
VEN
A2
MUX36S08
RS
D
S
VOUT
EN
VOUT
VOUT
CL
VS
1nF
GND
QINJ = CL X
VOUT
VEN
Figure 32. Charge-Injection Measurement Setup
8.9 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX36xxx when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 33 shows the setup used to measure, and
the equation used to compute, off isolation.
0.1µF
VDD
VSS
0.1µF
NETWORK
VSS
VDD
ANALYZER
50Ÿ
S
50Ÿ
VS
D
VOUT
RL
50Ÿ
GND
Figure 33. Off Isolation Measurement Setup
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8.10 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. Figure 34 shows the setup used to measure,
and the equation used to compute, channel-to-channel crosstalk.
0.1µF
VDD
VSS
0.1µF
NETWORK
VSS
VDD
ANALYZER
VOUT
S1
RL
50Ÿ
R
50Ÿ
S2
VS
GND
Figure 34. Channel-to-Channel Crosstalk Measurement Setup
8.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin of an on-channel and the output measured at the drain pin of the MUX36xxx. Figure 35 shows the
setup used to measure bandwidth of the MUX.
VSS
VDD
0.1µF
0.1µF
NETWORK
VSS
VDD
V1
ANALYZER
50Ÿ
S
VS
V2
D
VOUT
RL
50Ÿ
GND
V2
Attenuation = 20 Û log( )
V1
Figure 35. Bandwidth Measurement Setup
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8.12 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the MUX36xxx varies with the amplitude of the input signal and this results in THD
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. Figure 36 shows the setup used to measure THD+N of the MUX36xxx.
VSS
VDD
0.1µF
0.1µF
AUDIO PRECISION
VSS
VDD
RS
S
IN
VS
VIN
D
V p-p
VOUT
RL
10NŸ
GND
Figure 36. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The MUX36xxx are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX36S08 and MUX36D04. The MUX36S08 is an 8-channel, single-ended, analog
mux. The MUX36D04 is a 4-channel, differential, analog mux. Each channel is turned on or turned off based on
the state of the address lines and enable pin.
9.2 Functional Block Diagram
MUX36D04
MUX36S08
S1
S1A
S2
S2A
S3
S3A
S4
S4A
DA
S1B
DB
S5
D
S6
S2B
S7
S3B
S8
S4B
1-OF-4
DECODER
1-OF-8
DECODER
A0
22
A1
A2
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EN
A0
A1
EN
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9.3 Feature Description
9.3.1 Ultralow Leakage Current
The MUX36xxx provide extremely low on- and off-leakage currents. The MUX36xxx are capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error due to
the ultralow leakage currents. Figure 37 shows typical leakage currents of the MUX36xxx versus temperature.
900
ID(ON)+
Leakage Current (pA)
600
ID(OFF)+
300
IS(OFF)+
0
IS(OFF)-
±300
ID(OFF)-
±600
ID(ON)±900
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C00
Figure 37. Leakage Current vs Temperature
9.3.2 Ultralow Charge Injection
The MUX36xxx have a simple transmission gate topology, as shown in Figure 38. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 38. Transmission Gate Topology
The MUX36xxx have special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 0.3 pC at VS = 0 V, and ±0.6 pC in the full signal range, as shown in Figure 39.
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Feature Description (continued)
Charge Injection (pC)
2
1
VDD = +15V
VSS = -15V
0
VDD = +10V
VSS = -10V
±1
VDD = 12V
VSS = 0V
±2
±15
±10
±5
0
5
10
Source Voltage (V)
15
C02
Figure 39. Source-to-Drain Charge injection vs Source or Drain voltage
The drain-to-source charge injection becomes important when the MUX36xxx are used in Demux mode, where D
becomes the input and Sx becomes the output. Figure 40 shows the drain-to-source charge injection across the
full signal range.
9
VDD = +15V
VSS = -15V
Charge Injection (pC)
6
VDD = +10V
VSS = -10V
3
0
VDD = 12V
VSS = 0V
±3
±6
±9
±15
±10
±5
0
5
10
Drain voltage (V)
15
C01
Figure 40. Drain-to-Source Charge injection vs Source or Drain voltage
9.3.3 Bidirectional Operation
The MUX36xxx are operable in both mux and demux modes. The source (Sx, SxA, SxB) and drain (D, DA, DB)
pins of the MUX36xxx are used either as input or output. Each switch of the MUX36xxx has very similar
characteristics in both directions.
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Feature Description (continued)
9.3.4 Rail-to-Rail Operation
The valid analog signal for the MUX36xxx ranges from VSS to VDD. The input signal to the MUX36xxx can swing
from VSS to VDD without any significant degradation in performance. The on-resistance of the MUX36xxx varies
with input signal, as shown in Figure 41
250
VDD = +13.5V VDD = +15V
VSS = -13.5V VSS = -15V
On Resistance (Ÿ)
200
150
100
50
VDD = +18V
VSS = -18V
VDD = +16.5V
VSS = -16.5V
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
C00
Figure 41. On-resistance vs Source or Drain Voltage
9.4 Device Functional Modes
When the EN pin of the MUX36xxx is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in open state irrespective of the state of the
address lines. The EN pin can be connected to VDD (as high as 36 V).
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10 Applications and Implementation
10.1 Application Information
The MUX36xxx family offers outstanding input/output leakage currents and ultralow charge injection. These
devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX36xxx is
very low. These features makes the MUX36xxx a precision, robust, high-performance analog multiplexer for highvoltage, industrial applications.
10.2 Typical Application
Figure 42 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision
Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX36D04,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs
REF3140
Bridge Sensor
OPA192
+
Photo
Detector
VINP
+
Gain Network
Current Sensing
LED
REF
OPA192
Antialiasing
Filter
Gain Network
OPA192
Optical Sensor
High-Voltage Multiplexed Input
RC Filter
+
MUX36D04
Thermocouple
OPA350
Reference Driver
Gain Network
Gain Network
RC Filter
High-Voltage Level Translation
ADS8864
VINM
VCM
Figure 42. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
10.2.1 Design Requirements
The primary objective is to design a ±20 V, differential, 4-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
10.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 42. The
circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output
buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple
channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog
circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal
input signal at each input channel. Detailed design considerations and component selection procedure can be
found in the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for
High-Voltage Inputs with Lowest Distortion.
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Typical Application (continued)
10.2.3 Application Curve
1
Integral Non-Linearity (LSB)
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
±20
±15
±10
±5
0
5
10
15
ADC Differential Peak-to-Peak Input (V)
20
C03
Figure 43. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
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11 Power Supply Recommendations
The MUX36xxx operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The
MUX36S08 and MUX36D04 operate equally well with either dual supplies (±5 V to ±18 V), or a single supply (10
V to 36 V). They also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable
operation, use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to
ground.
Note that the on-resistance of the MUX36xxx varies with supply voltage, as illustrated in Figure 44
250
VDD = +13.5V VDD = +15V
VSS = -13.5V VSS = -15V
On Resistance (Ÿ)
200
150
100
50
VDD = +18V
VSS = -18V
VDD = +16.5V
VSS = -16.5V
0
±20
±15
±10
±5
0
5
10
15
Source or Drain Voltage (V)
20
C00
Figure 44. On-Resistance Variation With Supply and Input Voltage
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SBOS705A – JANUARY 2016 – REVISED JANUARY 2015
12 Layout
12.1 Layout Guidelines
Figure 45 illustrates an example of a PCB layout with the MUX36S08IPW, and Figure 46 illustrates an example
of a PCB layout with MUX36D04IPW.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as small as possible. In case of the differential signal, ensure the A inputs and B inputs
are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible and only make perpendicular crossings when necessary.
AO
C
A1
EN
AO
Via to
ground plane
A2
12.2 Layout Example
A1
EN
A2
VSS
GND
S1
Via to
ground plane
MUX36S 08IPW
C
VDD
S2
S5
S3
S6
S4
S7
D
S8
C
AO
A1
EN
GND
VSS
VDD
S 1A
MUX36D04IPW
Via to
ground plane
A1
AO
Via to
ground plane
EN
Figure 45. MUX36S08IPW Layout Example
C
S 1B
S 2A
S 2B
S 3A
S 3B
S 4A
S 4B
DA
DB
Figure 46. MUX36D04IPW Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
• ADS8864 data sheet, SBAS492
• OPA140 data sheet, SBOS498
• OPA192 data sheet, SBOS620
13.2 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MUX36S08
Click here
Click here
Click here
Click here
Click here
MUX36D04
Click here
Click here
Click here
Click here
Click here
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MUX36D04IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXD04C
MUX36D04IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXD04C
MUX36S08IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXS08B
MUX36S08IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
MUXS08B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Feb-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MUX36D04IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
MUX36S08IPWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MUX36D04IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
MUX36S08IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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