TI1 CDCR83DBQRG4 Direct rambus clock generator Datasheet

 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
D 400-MHz Differential Clock Source for
D
D
D
D
D
D
D
D
D
Direct Rambus Memory Systems for an
800-MHz Data Transfer Rate
Synchronizes the Clock Domains of the
Rambus Channel With an External System
or Processor Clock
Three Power Operating Modes to Minimize
Power for Mobile and Other
Power-Sensitive Applications
Operates From a Single 3.3-V Supply and
120 mW at 300 MHz (Typ)
Packaged in a Shrink Small-Outline
Package (DBQ)
Supports Frequency Multipliers: 4, 6, 8,
16/3
No External Components Required for PLL
Supports Independent Channel Clocking
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
Designed for Use With TI’s 133-MHz Clock
Synthesizers CDC924 and CDC921
D Cycle-Cycle Jitter Is Less Than 50 ps at
400 MHz
D Certified by Gigatest Labs to Exceed the
D
Rambus DRCG Validation Requirement
Supports Industrial Temperature Range of
−40°C to 85°C
DBQ PACKAGE
(TOP VIEW)
VDDIR
REFCLK
VDDP
GNDP
GNDI
PCLKM
SYNCLKN
GNDC
VDDC
VDDIPD
STOPB
PWRDNB
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
S0
S1
VDDO
GNDO
CLK
NC
CLKB
GNDO
VDDO
MULT0
MULT1
S2
NC − No internal connection
description
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system
or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and
mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus
memory applications.
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK
frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects
the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew
between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK
boundary without incurring additional latency.
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz
with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a
bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for
systems where synchronization between the Rambus clock and a system clock is not required. Test modes are
provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a
high-impedance state for board testing.
The CDCR83 is characterized for operation over free-air temperatures of −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Copyright  2001 − 2005, Texas Instruments Incorporated
!"# $%
$ ! ! & ' $$ ()% $ !* $ #) #$
* ## !%
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1
 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
functional block diagram
PWRDWNB
S0
S1
S2
STOPB
Test MUX
Bypass MUX
ByPCLK
PLLCLK
CLK
PLL
B
REFCLK
CLKB
Phase
Aligner
A
PACLK
φD
2
PCLKM
MULT0
MULT1
SYNCLKN
FUNCTION TABLE†
S0
S1
S2
CLK
CLKB
Normal
0
0
0
Phase aligned clock
Phase aligned clock B
Bypass
1
0
0
PLLCLK
PLLCLKB
Test
1
1
0
REFCLK
REFCLKB
Output test (OE)
0
1
X
Hi-Z
Hi-Z
Reserved
0
0
1
—
—
Reserved
1
0
1
—
—
Hi-Z
Hi-Z
MODE
Reserved
1
1
1
† X = don’t care, Hi-Z = high impedance
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CLK
20
O
Output clock
CLKB
18
O
Output clock (complement)
GNDC
8
GND for phase aligner
GNDI
5
GND for control inputs
GNDO
17, 21
GND for clock outputs
GNDP
4
MULT0
15
I
PLL multiplier select
MULT1
14
I
PLL multiplier select
NC
19
PCLKM
6
I
Phase detector input
PWRDNB
12
I
Active low power down
REFCLK
2
I
Reference clock
S0
24
I
Mode control
S1
23
I
Mode control
S2
13
I
Mode control
STOPB
11
I
Active low output disable
SYNCLKN
7
I
Phase detector input
VDDC
VDDIPD
9
GND for PLL
Not used
10
VDD for phase aligner
Reference voltage for phase detector inputs and STOPB
1
Reference voltage for REFCLK
VDDIR
VDDO
16, 22
VDDP
3
VDD for clock outputs
VDD for PLL
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
PLL divider selection
Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted,
provided that (267 MHz < BUSCLK < 400 MHz) and (33 MHz < REFCLK < 100 MHz).
Table 1. REFCLK and BUSCLK Frequencies
MULT0
MULT1
REFCLK
(MHz)
MULTIPLY
RATIO
BUSCLK
(MHz)
0
0
67
4
267
0
1
50
6
300
0
1
67
6
400
1
1
33
8
267
1
1
50
8
400
1
0
67
16/3
356
Table 2. Clock Output Driver States
STATE
PWRDNB
STOPB
CLK
CLKB
Powerdown
0
X
GND
GND
CLK stop
1
0
Normal
1
1
VX, STOP
PACLK/PLLCLK/
REFCLK†
VX, STOP
PACLKB/PLLCLKB/
REFCLKB
† Depending on the state of S0, S1, and S2
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Output voltage range, VO, at any output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
Input voltage range,VI, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBQ
1400 mW
11 mW/°C
905 mW
740 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
4
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
recommended operating conditions
Supply voltage, VDD
MIN
NOM
MAX
UNIT
3.135
3.3
3.465
V
0.7 × VDD
High-level input voltage, VIH (CMOS)
V
0.3 × VDD
Low-level input voltage, VIL (CMOS)
−0.5 × tc(PD)
Initial phase error at phase detector inputs
(required range for phase aligner)
V
0.5 × tc(PD)
0.3 × VDDIR
REFCLK low-level input voltage, VIL
V
0.7 × VDDIR
REFCLK high-level input voltage, VIH
V
0.3 × VDDIPD
Input signal low voltage, VIL (STOPB)
V
0.7 × VDDIPD
Input signal high voltage, VIH (STOPB)
V
Input reference voltage for (REFCLK) (VDDIR)
1.235
3.465
Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD)
1.235
3.465
High-level output current, IOH
V
−16
mA
16
mA
85
°C
MIN
MAX
UNIT
10
40
ns
250
ps
40%
60%
30
33
Low-level output current, IOL
Operating free-air temperature, TA
V
−40
timing requirements
Input cycle time, tc(in)
Input cycle-to-cycle jitter
Input duty cycle over 10,000 cycles
Input frequency modulation, fmod
Modulation index, nonlinear maximum 0.5%
kHz
0.6%
Phase detector input cycle time (PCLKM and SYNCLKN)
30
Input slew rate, SR
Input duty cycle (PCLKM and SYNCLKN)
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100
1
4
25%
75%
ns
V/ns
5
 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
MIN
TYP‡
MAX
UNIT
VO(STOP)
Output voltage during CLK Stop
(STOPB = 0)
See Figure 1
1.1
2
VO(X)
VO
Output crossing-point voltage
See Figure 1 and Figure 6
1.3
1.8
V
Output voltage swing
See Figure 1
0.4
0.6
V
VIK
Input clamp voltage
VDD = 3.135 V,
See Figure 1
II = −18 mA
−1.2
V
IOH = −1 mA
IOH = −16 mA
2
VOH
High-level output voltage
VDD = min to max,
VDD = 3.135 V,
VOL
Low-level output voltage
VDD = min to max,
VDD = 3.135 V,
IOL = 1 mA
IOL = 16 mA
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
VO = 1 V
VO = 1.65 V
See Figure 1
IOH
IOL
High-level output current
VO = 3.135 V
VO = 1.95 V
High-impedance-state output
current
S0 = 0,
IOZ(STOP)
High-impedance-state output
current during CLK stop
Stop = 0, VO = GND or VDD
IOZ(PD)
High-impedance-state output
current in power-down state
PWRDNB = 0,
VO = GND or VDD
IIH
High-level
input current
IIL
ZO
−52
−51
−14.5
43
mA
−21
61.5
65
25.5
S1 = 1
−10
mA
36
± 10
µA
± 100
µA
100
µA
VI = VDD
10
PWRDNB, S0, S1,
S2, MULT0, MULT1
VDD = 3.465 V,
VI = VDD
10
REFCLK, PCLKM,
SYNCLKN, STOPB
VDD = 3.465 V,
VI = 0
−10
PWRDNB, S0, S1,
S2, MULT0, MULT1
VDD = 3.465 V,
VI = 0
−10
µA
A
A
µA
Output
impedance
High state
RI at IO −14.5 mA to −16.5 mA
15
35
50
Low state
RI at IO 14.5 mA to 16.5 mA
11
17
35
Reference
current
VDDIR, VDDIPD
VDD = 3.465 V
CO
Output capacitance
50
µA
PWRDNB = 1
0.5
mA
VI = VDD or GND
VO = VDD or GND
Supply current in power-down state
REFCLK = 0 MHz to 100 MHz,
PWDNB = 0,
STOPB = 1
POST OFFICE BOX 655303
Ω
PWRDNB = 0
IDD(CLKSTOP) Supply current in CLK stop state
BUSCLK configured for 400 MHz
IDD(NORMAL) Supply current in normal state
BUSCLK = 400 MHz
† VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP
‡ All typical values are at VDD = 3.3 V, TA = 25°C.
6
−32
VDD = 3.465 V,
Input capacitance
V
0.5
REFCLK, PCLKM,
SYNCLKN, STOPB
CI
IDD(PD)
0.1
VO = 1.65 V
VO = 0.4 V
IOZ
Low-level
input current
V
1
VDD = 3.135 V,
VDD = 3.3 V,
VDD = 3.465 V,
Low-level output current
VDD − 0.1 V
2.4
• DALLAS, TEXAS 75265
2
pF
3
pF
100
µA
30
mA
70
mA
 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
tc(out)
Clock output cycle time
t(jitter)
Total cycle jitter over 1, 2,
3, 4, 5, or 6 clock cycles
TEST CONDITIONS
MIN
TYP†
2.5
267 MHz
Infinite and
stopped phase
alignment
60
400 MHz
Static phase error}
−100
PLL output phase error when tracking SSC
Dynamic phase error}
t(DC)
Output duty cycle over 10,000 cycles
See Figure 4
100
ps
−100
100
ps
45%
55%
267 MHz
Output cycle-to-cycle
duty cycle error
80
300 MHz
356 MHz
ps
50
Phase detector phase error for distributed loop
t(DC, err)
ns
70
See Figure 3
t(phase)
t(phase, SSC)
Infinite and
stopped phase
alignment
UNIT
3.75
80
300 MHz
356 MHz
MAX
70
See Figure 5
60
400 MHz
ps
50
tr, tf
Output rise and fall times (measured at 20%−80% of
output voltage)
See Figure 7
∆t
Difference between rise and fall times on a single device
(20%−80%) |tf − tr|
See Figure 7
160
400
ps
100
ps
MAX
UNIT
† All typical values are at VDD = 3.3 V, TA = 25°C.
‡ Assured by design
state transition latency specifications
PARAMETER
t(powerup)
FROM
Delay time, PWRDNB↑ to CLK/CLKB output
settled (excluding t(DISTLOCK))
Delay time, PWRDNB↑ to internal PLL and
clock are on and settled
TO
See Figure 8
Powerdown
Delay time, power up to internal PLL and
clock are on and settled
t(MULT)
MULT0 and MULT1 change to CLK/CLKB
output resettled (excluding t(DISTLOCK))
t(CLKON)
MIN
TYP†
3
Normal
ms
3
Delay time, power up to CLK/CLKB output
settled
t(VDDpowerup)
TEST
CONDITIONS
See Figure 8
VDD
3
Normal
ms
3
Normal
Normal
See Figure 9
1
ms
STOPB↑ to CLK/CLKB glitch-free clock
edges
CLK Stop
Normal
See Figure 10
10
ns
t(CLKSETL)
STOPB↑ to CLK/CLKB output settled to
within 50 ps of the phase before STOPB was
disabled
CLK Stop
Normal
See Figure 10
20
cycles
t(CLKOFF)
STOPB↓ to CLK/CLKB output disabled
CLK
Stop
See Figure 10
5
ns
Normal
† All typical values are at VDD = 3.3 V, TA = 25°C.
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
state transition latency specifications (continued)
PARAMETER
FROM
TO
TEST
CONDITIONS
t(powerdown)
Delay time, PWRDNB↓ to the device in the
power-down mode
Normal
Powerdown
See Figure 8
t(STOP)
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode
(STOPB = 1)
STOPB
Normal
See Figure 10
t(ON)
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
Normal
CLK stop
See Figure 10
Time from when CLK/CLKB output is
settled to when the phase error between
SYNCLKN and PCLKM falls within t(phase)
† All typical values are at VDD = 3.3 V, TA = 25°C.
t(DISTLOCK)
8
Unlocked
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MIN
TYP†
MAX
UNIT
1
ms
100
µs
100
ms
5
ms
 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
68 Ω, ±5%
39 Ω, ±5%
10 pF
39 Ω, ±5%
68 Ω, ±5%
RT = 28 Ω
RT = 28 Ω
100 pF
10 pF
Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL)
CLK
CLKB
tc(1)
tc(2)
Cycle-to-cycle jitter = | tc(1) − tc(2)| over 10000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
CLK
CLKB
tc(3)
tc(4)
Cycle-to-cycle jitter = | tc(3) − tc(4)| over 10000 consecutive cycles
Figure 3. Short Term Cycle-to-Cycle Jitter Over Four Cycles
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
CLK
CLKB
tpd(1)
tc(5)
Duty cycle = (tpd(1)/tc(5))
Figure 4. Output Duty Cycle
CLK
CLKB
tpd(2)
tpd(3)
tc(6)
tc(7)
Duty cycle error = tpd(2) − tpd(3)
Figure 5. Duty Cycle Error (Cycle-to-Cycle)
CLK
VO(X)+
VO(X), nom
VO(X)−
CLKB
Figure 6. Crossing-Point Voltage
VOH
80%
20%
VOL
tr
tf
Figure 7. Voltage Waveforms
PWRDNB
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
t(power down)
t(power up)
CLK/CLKB
Figure 8. PWRDNB Transition Timings
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ÎÎ
ÎÎ
 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
MULT0 and/or
MULT1
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
CLK/CLKB
t(MULT)
Figure 9. MULT Transition Timings
t(ON)
t(STOP)
STOPB
t(CLKSETL)
t(CLKON)
(see Note A)
CLK/CLKB
ÎÎÎÎ
ÎÎÎÎ
Output clock
not specified
glitches ok
Clock enabled
and glitch free
ÎÎÎ
ÎÎÎ
t(CLKOFF)
(see Note A)
Clock output settled
within 50 ps of the
phase before disabled
NOTE A: Vref = VO ± 200 mV
Figure 10. STOPB Transition Timings
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 SCAS632B − APRIL 2001 − REVISED OCTOBER 2005
MECHANICAL DATA
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
24-PIN SHOWN
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13) M
13
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (3,99)
0.150 (3,81)
1
Gage Plane
12
A
0.010 (0,25)
0°−ā 8°
0.035 (0,89)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
A MAX
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
A MIN
0.188
(4,78)
0.337
(8,56)
0.337
(8,56)
DIM
4073301/C 02/97
NOTES: A.
B.
C.
D.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-137
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCR83DBQ
NRND
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCR83DBQG4
NRND
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCR83DBQR
NRND
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCR83DBQRG4
NRND
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCR83DBQR
Package Package Pins
Type Drawing
SSOP/
QSOP
DBQ
24
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.5
9.0
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCR83DBQR
SSOP/QSOP
DBQ
24
2500
346.0
346.0
33.0
Pack Materials-Page 2
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