LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 LM20323 36V, 3A 500 kHz Synchronous Buck Regulator Check for Samples: LM20323 FEATURES 1 • • • • 2 • • • • • • • 4.5V to 36V input voltage range 3A output current, 5.2A peak current 130 mΩ/110 mΩ integrated power MOSFETs 93% peak efficiency with synchronous rectification 1.5% feedback voltage accuracy Current mode control, selectable compensation Fixed 500 kHz switching frequency Adjustable output voltage down to 0.8V Compatible with pre-biased loads Programmable soft-start with external capacitor Precision enable pin with hysteresis • • • • • Integrated OVP, UVLO, PGOOD Internally protected with peak current limit, thermal shutdown and restart Accurate current limit minimizes inductor size Non-linear current mode slope compensation eTSSOP-20 exposed pad package APPLICATIONS • • • Simple to design, high efficiency point of load regulation from a 4.5V to 36V bus High Performance DSPs, FPGAs, ASICs and Microprocessors Communications Infrastructure, Automotive DESCRIPTION The LM20323 is a full featured 500kHz synchronous buck regulator capable of delivering up to 3A of load current. The current mode control loop is externally compensated with only two components, offering both high performance and ease of use. The device is optimized to work over the input voltage range of 4.5V to 36V making it well suited for high voltage systems. The device features internal Over Voltage Protection (OVP) and Over Current Protection (OCP) circuits for increased system reliability. A precision Enable pin and integrated UVLO allows the turn-on of the device to be tightly controlled and sequenced. Startup inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault detection and supply sequencing are possible with the integrated power good (PGOOD) circuit. The LM20323 is designed to work well in multi-rail power supply architectures. The output voltage of the device can be configured to track a higher voltage rail using the SS/TRK pin. If the output of the LM20323 is pre-biased at startup it will not sink current to pull the output low until the internal soft-start ramp exceeds the voltage at the feedback pin. The LM20323 is offered in an exposed pad 20-pin eTSSOP package that can be soldered to the PCB, eliminating the need for bulky heatsinks. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Simplified Application Circuit LM20323 BOOT VIN VIN CBOOT L VOUT SW D1 (Optional) CIN EN COMP SS/TRK AGND RC1 CC1 RFB1 COUT FB RFB2 PGOOD VCC GND CVCC Connection Diagram SS/TRK 1 20 NC FB 2 19 EN PGOOD 3 18 COMP 4 17 BOOT VCC VIN 5 VIN 6 SW 7 14 SW SW 8 13 SW GND 9 12 AGND GND 10 11 GND EP 16 VIN 15 VIN Figure 1. Top View eTSSOP-20 Package Pin Functions Pin Descriptions 2 Pin(s) Name Description 1 SS/TRK Application Information Soft-Start or Tracking control input An internal 4.5 µA current source charges an external capacitor to set the soft-start rate. The PWM can track to an external voltage ramp with a low impedance source. If left open, an internal 1 ms SS ramp is activated. 2 FB Feedback input to the error amplifier from the regulated output This pin is connected to the inverting input of the internal transconductance error amplifier. An 800 mV reference is internally connected to the non-inverting input of the error amplifier. 3 PGOOD Power good output signal Open drain output indicating the output voltage is regulating within tolerance. A pull-up resistor of 10 kΩ to 100 kΩ is recommended if this function is used. 4 COMP Output of the internal error amplifier and input to the Pulse Width Modulator The loop compensation network should be connected between the COMP pin and the AGND pin. 5,6,15,16 7,8,13,14 VIN Input supply voltage Nominal operating range: 4.5V to 36V. SW Switch pin The drain terminal of the internal Synchronous Rectifier power NMOSFET and the source terminal of the internal Control power NMOSFET. 9,10,11 GND Ground Internal reference for the power MOSFETs. 12 AGND Analog ground Internal reference for the regulator control functions. 17 BOOT Boost input for bootstrap capacitor An internal diode from VCC to BOOT charges an external capacitor required from SW to BOOT to power the Control MOSFET gate driver. 18 VCC Output of the high voltage linear regulator. The VCC voltage is regulated to approximately 5.5V. VCC tracks VIN up to about 7.2V. Above VIN = 7.2V, VCC is regulated to approximately 5.5 Volts. A 0.1 µF to 1 µF ceramic decoupling capacitor is required. The VCC pin is an output only. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 Pin Descriptions (continued) Pin(s) Name Description Application Information 19 EN Enable or UVLO input An external voltage divider can be used to set the line undervoltage lockout threshold. If the EN pin is left unconnected, a 2 µA pull-up current source pulls the EN pin high to enable the regulator. 20 NC No Connection Recommend connecting this pin to GND. EP Exposed Pad Exposed pad Exposed metal pad on the underside of the package with a weak electrical connection to GND. Connect this pad to the PC board ground plane in order to improve heat dissipation. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) VIN to GND -0.3V to +38V BOOT to GND -0.3V to +43V BOOT to SW -0.3V to +7V SW to GND -0.5V to +38V SW to GND (Transient) -1.5V (< 20 ns) FB, EN, SS/TRK, COMP, PGOOD to GND -0.3V to +6V VCC to GND -0.3V to +8V Storage Temperature -65°C to 150°C ESD Rating Human Body Model (1) (2) (2) 2kV Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin. Operating Ratings VIN to GND +4.5V to +36V −40°C to + 125°C Junction Temperature Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 3 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Electrical Characteristics Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol VFB Parameter Conditions Min Max Units Feedback Pin Voltage VVIN = 4.5V to 36V 0.8 0.812 V RHSW-DS(ON) High-Side MOSFET On-Resistance ISW = 3A 130 225 mΩ RLSW-DS(ON) Low-Side MOSFET On-Resistance ISW = 3A 110 190 mΩ IQ Operating Quiescent Current VVIN = 4.5V to 36V 2.3 3 mA ISD Shutdown Quiescent Current VEN = 0V 150 180 µA VIN Under Voltage Lockout Rising VVIN 4.25 4.5 V 350 450 mV VUVLO VUVLO(HYS) VVCC 0.788 Typ 4 VIN Under Voltage Lockout Hysteresis VCC Voltage IVCC = -5 mA, VEN = 5V ISS Soft-Start Pin Source Current VSS = 0V VTRKACC Soft-Start/Track Pin Accuracy VSS = 0.4V BOOT Diode Leakage VBOOT = 4V 10 BOOT Diode Forward Voltage IBOOT = -100 mA 0.9 1.1 V Over Voltage Protection Rising Threshold VFB(OVP) / VFB 110 112 % Over Voltage Protection Hysteresis ΔVFB(OVP) / VFB 2 3 % PGOOD Threshold, VOUT Rising VFB(PG) / VFB 95 97 % PGOOD Hysteresis ΔVFB(PG) / VFB 2 3 IBOOT VF-BOOT 5.5 V 2 4.5 7 µA -10 5 15 mV nA Powergood VFB(OVP) VFB(OVP-HYS) VFB(PG) VFB(PG-HYS) TPGOOD 107 93 PGOOD Delay 20 IPGOOD(SNK) PGOOD Low Sink Current VPGOOD = 0.5V IPGOOD(SRC) PGOOD High Leakage Current VPGOOD = 5V 0.6 % µs 1 mA 5 200 nA 520 570 kHz Oscillator FSW1 Switching Frequency DMAX Maximum Duty Cycle IOUT = 3A 470 70 % Error Amplifier Feedback Pin Bias Current VFB = 1V 50 nA ICOMP(SRC) IFB COMP Output Source Current VFB = 0V VCOMP = 0V 200 400 µA ICOMP(SNK) COMP Output Sink Current VFB = 1.6V VCOMP = 1.6V 200 350 µA Error Amplifier DC Transconductance ICOMP = -50 µA to +50 µA 450 515 AVOL Error Amplifier Voltage Gain COMP pin open 2000 V/V GBW Error Amplifier Gain-Bandwidth Product COMP pin open 7 MHz gm 600 µmho Current Limit ILIM Cycle By Cycle Positive Current Limit ILIMNEG Cycle By Cycle Negative Current Limit 2.8 A Cycle By Cycle Current Limit Delay 150 ns TILIM 4.3 5.2 6.0 A Enable VIH_EN EN Pin Rising Threshold VEN(HYS) EN Pin Hysteresis IEN EN Source Current 1.2 1.25 1.3 V 50 mV 2 µA Thermal Shutdown 170 °C Thermal Shutdown Hysteresis 20 °C VEN = 0V, VVIN = 12V Thermal Shutdown TSD TSD(HYS) Thermal Resistance 4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol (1) Parameter θJC Junction to Case θJA Junction to Ambient Conditions (1) Min 0 LFM airflow Typ Max Units 5.6 °C/W 27 °C/W Measured on a 4 layer 2" x 2" PCB with 1 oz. copper weight inner layers and 2 oz. outer layers. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 5 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Typical Performance Characteristics Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Efficiency vs. Load Current Error Amplifier Gain Error Amplifier Phase Line Regulation Load Regulation VCC vs. VIN Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Non-Switching IQ vs. VIN Shutdown IQ vs. VIN PGOOD Output Low Level Voltage vs. IPGOOD Enable Threshold and Hysteresis vs. Temperature UVLO Threshold and Hysteresis vs. Temperature Enable Current vs. Temperature Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 7 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 8 Oscillator Frequency vs. VIN High-Side FET Resistance vs. Temperature Load Transient Response Low-Side FET Resistance vs. Temperature Peak Current Limit vs. Temperature Startup with Prebiased Output Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 5.6 µH, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Startup with CSS = 0 Startup with CSS = 100 nF Startup with Applied Track Signal Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 9 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Block Diagram VCC_INT BOOT INTERNAL +5.5V REGULATOR BOOT VCC ENABLE_INT VIN VCC UVLO + - 4.25V +5.5V REGULATOR 2.7V +2.7V REGULATOR SLOPE COMP COMP 2.7V CURRENT SENSE + 4.5 PA DISCHARGE ERROR AMP gm = 515 Pmho SS/TRK + FB DISCHARGE CURRENT LIMIT 5.2A VREF + 800 mV - BOOT + - + + PWM COMPARATOR 880 mV 740 mV + - OVERVOLTAGE PG-L + - VCC_INT NEGATIVE CURRENT LIMIT UNDERVOLTAGE + - CONTROL LOGIC -2.8A SW VCC THERMAL PROTECTION 2 PA EN 1.25V + - ENABLE_INT 500 kHz OSCILLATOR GND PG-L PGOOD AGND Operation Description GENERAL The LM20323 switching regulator features all of the functions necessary to implement an efficient buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current. The regulator utilizes peak current mode control with nonlinear slope compensation to optimize stability and transient response over the entire output voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle current limiting and easy loop compensation. The 500kHz switching frequency minimizes the inductor size while keeping 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 switching losses low allowing use of a small inductor while still achieving efficiencies as high as 93%. The precision internal voltage reference allows the output to be set as low as 0.8V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the eTSSOP-20 package featuring an exposed pad to aid thermal dissipation. The typical application circuit for the LM20323 is shown in Figure 2 in the design guide. PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.25V (typical). The EN pin has 50 mV of hysteresis and will disable the output when the enable voltage falls below 1.2V (typical). If the EN pin is not used, it should be disconnected so the internal 2 µA pull-up will default this function to the enabled condition. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor divider network from VIN to configure the device to turn-on at a precise input voltage. The precision enable circuitry will remain active even when the device is disabled. PEAK CURRENT MODE CONTROL In most cases, the peak current mode control architecture used in the LM20323 only requires two external components to achieve a stable design. The compensation can be selected to accommodate any capacitor type or value. The external compensation also allows the user to set the crossover frequency and optimize the transient performance of the device. For duty cycles above 50% all peak current mode control buck converters require the addition of an artificial ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation. What makes the LM20323 unique is the amount of slope compensation will change depending on the output voltage. When operating at high output voltages the device will have more slope compensation than when operating at lower output voltages. This is accomplished in the LM20323 by using a non-linear parabolic ramp for the slope compensation. The parabolic slope compensation of the LM20323 is an improvement over the traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage range. CURRENT LIMIT The precise current limit enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events, while at the same time providing frequency and voltage foldback protection during hard short circuit conditions. SOFT-START AND VOLTAGE TRACKING The SS/TRK pin is a dual function pin that can be used to set the startup time or track an external voltage source. The startup or soft-start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground. The soft-start feature allows the regulator output to gradually reach the steady state operating point, thus reducing stresses on the input supply and controlling startup current. If no soft-start capacitor is used the device defaults to the internal soft-start circuitry resulting in a startup time of approximately 1 ms. For applications that require a monotonic startup or utilize the PGOOD pin, an external soft-start capacitor is recommended. The SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two external resistors connected to the SS/TRK pin as shown in Figure 7 in the design guide. PRE-BIAS STARTUP CAPABILITY The LM20323 is in a pre-biased state when it starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the LM20323 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. During start up the LM20323 will not sink current until the soft-start voltage exceeds the voltage on the FB pin. Since the device cannot sink current, it protects the load from damage that might otherwise occur if current is conducted through the parasitic paths of the load. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 11 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20323 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turnon the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage falls back into regulation or the negative current limit is triggered which in turn tri-states the FETs. If the output reaches the UVP threshold the part will continue switching and the PGOOD pin will be deasserted and go low. Typical values for the PGOOD resistor are on the order of 100 kΩ or less. To avoid false tripping during transient glitches the PGOOD pin has 20 µs of built in deglitch time to both rising and falling edges. UVLO The LM20323 has an internal under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 4.25V (typical). The UVLO threshold has 350 mV of hysteresis that keeps the device from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 6 in the design guide. THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the LM20323 tri-states the power FETs and resets soft-start. After the junction cools to approximately 150°C, the part starts up using the normal start up routine. This feature is provided to prevent catastrophic failures from accidental device overheating. Design Guide This section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion. To facilitate component selection discussions the circuit shown in Figure 2 below may be used as a reference. Unless otherwise indicated, all formulas assume units of amps (A) for current, farads (F) for capacitance, henries (H) for inductance and volts (V) for voltages. LM20323 BOOT VIN VIN CIN1 CBOOT L VOUT SW D1 (Optional) CIN2 EN FB VPULLUP COMP RFB1 COUT RFB2 RPG RC1 CC1 CSS PGOOD SS/TRK VCC AGND GND CVCC Figure 2. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: D= VOUT VIN (1) INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle. 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 The inductor selected should have a saturation current rating greater than the peak current limit of the device. Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the current limit in the application may be higher than the specified value. To optimize the performance and prevent the device from entering current limit at maximum load, the inductance is typically selected such that the ripple current, ΔiL, is not greater than 30% of the rated output current. Figure 3 illustrates the switch and inductor ripple current waveforms. Once the input voltage, output voltage, operating frequency and desired ripple current are known, the minimum value for the inductor can be calculated by the formula shown below: LMIN = (VIN - VOUT) x D 'iL x fSW (2) VSW VIN Time IL IL AVG = IOUT 'iL Time Figure 3. Switch and Inductor Current Waveforms If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be more than 10% of the rated output current to provide adequate current sense information for the current mode control loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense information and can be prone to instability. OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20323 that provide excellent performance. The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes, while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading conditions. When selecting the value for the output capacitor, the two performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple can be approximated by using the following formula: 'VOUT = 'iL x RESR + 1 8 x fSW x COUT (3) where, ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output, RESR (Ω) is the series resistance of the output capacitor, fSW(Hz) is the switching frequency, and COUT (F) is the output capacitance used in the design. The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also affect the output voltage droop during a load transient. The peak droop on the output voltage during a load transient is dependent on many factors; however, an approximation of the transient droop ignoring loop bandwidth can be obtained using the following equation: Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 13 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 VDROOP = 'IOUTSTEP x RESR + www.ti.com L x 'IOUTSTEP2 COUT x (VIN - VOUT) (4) where, COUT (F) is the minimum required output capacitance, L (H) is the value of the inductor, VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is the output capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific output ripple or transient droop target. INPUT CAPACITOR SELECTION Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC voltage derating that occurs on Y5V capacitors. The input capacitors CIN1 and CIN2 should be placed as close as possible to the VIN and GND pins on both sides of the device. Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the relationship: IIN-RMS = IOUT D(1 - D) (5) As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device. SETTING THE OUTPUT VOLTAGE (RFB1, RFB2) The resistors RFB1 and RFB2 are selected to set the output voltage for the device. provides suggestions for RFB1 and RFB2 for common output voltages. Table 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) RFB2(kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 52.3 10 5.0 If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using the equation below. RFB1 = VOUT 0.8 - 1 x RFB2 (6) LOOP COMPENSATION (RC1, CC1) The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load and the device itself. Table 2 below gives values for the compensation network that will result in a stable system when using a 150 µF, 6.3V POSCAP (6TPB150MAZB) output capacitor. Table 2. Recommended Compensation for COUT = 150 µF, IOUT = 3A 14 VIN VOUT L (µH) RC (kΩ) CC1 (nF) 12 5 6.8 45.3 4.7 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 Table 2. Recommended Compensation for COUT = 150 µF, IOUT = 3A (continued) VIN VOUT L (µH) RC (kΩ) CC1 (nF) 12 3.3 5.6 32.4 4.7 12 2.5 4.7 30.9 3.3 12 1.5 3.3 19.1 3.3 12 1.2 2.2 21.5 2.2 12 0.8 1.5 15 2.2 5 3.3 2.2 29.4 2.2 5 2.5 3.3 37.4 2.2 5 1.5 2.2 26.7 2.2 5 1.2 2 22.1 2.2 5 0.8 1.5 15 2.2 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20dB/decade from a very low frequency to beyond the crossover frequency. Figure 4 shows the transfer functions for power stage, feedback/compensation network, and the resulting compensated loop for the LM20323. Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Open Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 4. LM20323 Loop Compensation The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback transfer function is set by the feedback resistor ratio, error amp gain and external compensation network. To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should be positioned to cancel the output filter pole (fP(FIL)). Compensation of the LM20323 is achieved by adding an RC network as shown in Figure 5 below. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 15 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com LM20323 COMP RC1 CC2 (optional) CC1 Figure 5. Compensation Network for LM20323 A good starting value for CC1 for most applications is 2.2 nF. Once the value of CC1 is chosen the value of RC1 should be approximated using the equation below to cancel the output filter pole (fP(FIL)) as shown in Figure 4. CC1 IOUT 2xD x + RC1 = COUT VOUT fSW x L -1 (7) A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional phase margin at a lower crossover frequency. As with any attempt to compensate the LM20323 the stability of the system should be verified for desired transient droop and settling time. For low duty cycle operation, when the on-time of the switch node is less than 200ns, an additional capacitor (CC2) should be added from the COMP pin to AGND. The recommended value of this capacitor is 20pF. If low duty cycle jitter on the switch node is observed, the value of this capacitor can be increased to improve noise immunity; however, values much larger than 100pF will cause the pole fP2(EA) to move to a lower frequency degrading the loop stability. BOOT CAPACITOR (CBOOT) The LM20323 integrates an N-channel buck switch and associated floating high voltage level shift / gate driver. This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1 µF ceramic capacitor, connected with short traces between the BOOT pin and SW pin, is recommended. During the off-time of the buck switch, the SW pin voltage is approximately 0V and the bootstrap capacitor is charged from VCC through the internal bootstrap diode. SUB-REGULATOR BYPASS CAPACITOR (CVCC) The capacitor at the VCC pin provides noise filtering for the internal sub-regulator. The recommended value of CVCC should be no smaller than 0.1 µF and no greater than 1 µF. The capacitor should be a good quality ceramic X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. The VCC regulator should not be used for other functions since it isn't protected against short circuit. SETTING THE START UP TIME (CSS) The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below provides a list of soft start capacitors and the corresponding typical start up times. Table 3. Start Up Times for Different Soft-Start Capacitors 16 Start Up Time (ms) CSS (nF) 1 none 5 33 10 68 15 100 20 120 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 If different start up times are needed the equation shown below can be used to calculate the start up time. tSS = 0.8V x CSS ISS (8) As shown above, the start up time is influenced by the value of the soft-start capacitor CSS and the 4.5 µA softstart pin current ISS. While the soft-start capacitor can be sized to meet many start up requirements, there are limitations to its size. The soft-start time can never be faster than 1 ms due to the internal default 1 ms start up time. When the device is enabled there is an approximate time interval of 50 µs when the soft-start capacitor will be discharged just prior to the soft-start ramp. If the enable pin is rapidly pulsed or the soft-start capacitor is large there may not be enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging of soft-start capacitor during long disable periods an external 1MΩ resistor from SS/TRK to ground can be used without greatly affecting the start up time. USING PRECISION ENABLE AND POWER GOOD The precision enable (EN) and power good (PGOOD) pins of the LM20323 can be used to address many sequencing requirements. The turn-on of the LM20323 can be controlled with the precision enable pin by using two external resistors as shown in Figure 6 . External Power Supply VOUT1 LM20323 RA VOUT2 EN RB Figure 6. Sequencing LM20323 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 1 kΩ and 49.9 kΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage. RA = VTO VIH_EN - 1 x RB (9) When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold (VIH_EN), and external resistors need to be considered to ensure proper turn-on of the device. The LM20323 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high when the output is within the PGOOD tolerance window. Typical values for this resistor range from 10 kΩ to 100 kΩ. TRACKING AN EXTERNAL SUPPLY By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 7, the output of the LM20323 can be configured to track an external voltage source to obtain a simultaneous or ratiometric start up. External Power Supply EN VOUT1 R1 LM20323 VOUT2 SS/TRK R2 Figure 7. Tracking an External Supply Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 17 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Since the soft-start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 8, to give the desired start up. Figure 7 shows two common start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates a ratiometric start up. SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 8. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A simultaneous start up provides a more robust power up for these applications since it avoids turning on any parasitic conduction paths that may exist between the core and the I/O pins of the processor. The second most common power on behavior is known as a ratiometric start up. This start up is preferred in applications where both supplies need to be at the final value at the same time. Similar to the soft-start function, the fastest start up possible is 1ms regardless of the rise time of the tracking voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide sufficient overdrive and transient immunity. BENEFIT OF AN EXTERNAL SCHOTTKY The LM20323 employs a 40ns dead time between conduction of the control and synchronous FETs in order to avoid the situation where both FETs simultaneously conduct, causing shoot-through current. During the dead time, the body diode of the synchronous FET acts as a free-wheeling diode and conducts the inductor current. The structure of the high voltage DMOS is optimized for high breakdown voltage, but this typically leads to inefficient body diode conduction due to the reverse recovery charge. The loss associated with the reverse recovery of the body diode of the synchronous FET manifests itself as a loss proportional to load current and switching frequency. The additional efficiency loss becomes apparent at higher input voltages and switching frequencies. One simple solution is to use a small 1A external Schottky diode between SW and GND as shown in Figure 13. The external Schottky diode effectively conducts all inductor current during the dead time, minimizing the current passing through the synchronous MOSFET body diode and eliminating reverse recovery losses. 18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications. A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the increased reverse capacitance. The forward voltage of the synchronous MOSFET body diode is approximately 700 mV, therefore an external Schottky with a forward voltage less than or equal to 700 mV should be selected to ensure the majority of the dead time current is carried by the Schottky. THERMAL CONSIDERATIONS The thermal characteristics of the LM20323 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD x θJA + TA (10) PD = PIN x (1 - Efficiency) - 1.1 x (IOUT)2 x DCR (11) and Where: TJ is the junction temperature in °C. PIN is the input power in Watts (PIN = VIN x IIN). θJA is the junction to ambient thermal resistance for the LM20323. TA is the ambient temperature in °C. IOUT is the output load current. DCR is the inductor series resistance. It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction temperature exceeds 170°C the device will cycle in and out of thermal shutdown. If thermal shutdown occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device. Figure 9 and Figure 10 can be used as a guide to avoid exceeding the maximum junction temperature of 125°C provided an external 1A Schottky diode, such as Central Semiconductor's CMMSH1-40-NST, is used to improve reverse recovery losses. Figure 9. Safe Thermal Operating Areas (IOUT = 3A) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 19 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com Figure 10. Safe Thermal Operating Areas (IOUT = 2.5A) The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature. This data for the figure was derived assuming the device is operating at 3A continuous output current on a 4 layer PCB with an copper area greater than 4 square inches exhibiting a thermal characteristic less than 27 °C/W. Since the internal losses are dominated by the FETs a slight reduction in current by 500mA allows for much larger regions of operation, as shown in Figure 9. Figure 11, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias located under the thermal pad was used to connect the 4 layers. Figure 11. Thermal Resistance vs PCB Area (4 Layer Board) PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched at high slew rates. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin, to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 12). To minimize both loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input and output capacitor should consist of a small localized top side plane that connects to GND and the exposed pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor. 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 LM20323 www.ti.com SNVS557B – MAY 2008 – REVISED JANUARY 2009 2. Minimize the copper area of the switch node. Since the LM20323 has the SW pins on opposite sides of the package it is recommended that the SW pins should be connected with a trace that runs around the package. The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize capacitive and conductive losses. 3. Have a single point ground for all device grounds located under the EP. The ground connections for the compensation, feedback, and soft-start components should be connected together then routed to the EP pin of the device. The AGND pin should connect to GND under the EP. If not properly handled poor grounding can result in degraded load regulation or erratic switching behavior. 4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output resistor divider to FB pin should be as short as possible. This is most important when high value resistors are used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid contaminating the feedback signal with switch noise. 5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the best output accuracy. 6. Provide adequate device heatsinking. For most 3A designs a four layer board is recommended. Use as many vias as is possible to connect the EP to the power plane heatsink. For best results use a 5x4 via array with a minimum via diameter of 12 mils. "Via tenting" with the solder mask may be necessary to prevent wicking of the solder paste applied to the EP. See the Thermal Considerations section to ensure enough copper heatsinking area is used to keep the junction temperature below 125°C. LM20323 PVIN L SW VOUT CIN COUT PGND LOOP1 LOOP2 Figure 12. Schematic of LM20323 Highlighting Layout Sensitive Nodes Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 21 LM20323 SNVS557B – MAY 2008 – REVISED JANUARY 2009 www.ti.com VIN C1 C3 C2 GND C2, C3 should be placed at VIN pins 5,6 and 15,16 respectively. U1 VOUT C4 18 VCC R1 3 ENABLE 19 PGOOD BOOT EN 1 SS 4 COMP 2 FB 12 20 C8 C6 AGND NC LM20323 PGOOD 5 VIN 6 VIN 15 VIN 16 VIN 17 C5 7 SW 8 SW 13 SW 14 SW L1 9 GND 10 GND 11 GND VOUT D1 (OPTIONAL for improved Efficiency) C9 GND EP R3 C7 R2 R4 Figure 13. Typical Application Schematic Table 4. Bill of Materials (VIN = 12V, VOUT = 3.3V, IOUT = 3A) 22 ID Qty Part Number Size Description Vendor U1 1 LM20323MH eTSSOP-20 IC, Switching Regulator NSC C1 1 C3225X5R1E226M 1210 22µF, X5R, 25V, 20% TDK C2, C3 2 GRM21BR61E475KA12L 0805 4.7µF, X5R, 25V, 10% MuRata C5, C6 1 C1608X7R1H104K 0603 100nF, X7R, 50V, 10% TDK C4 1 C1608X5R1A105K 0603 1µF, X7R, 10V, 10% TDK C7 1 C1608C0G1H100J 0603 10pF, C0G, 50V, 5% TDK C8 1 C1608C0G1H102J 0603 1nF, C0G, 50V, 5% TDK C9 1 6TPB150MAZB B 150µF,POSCAP, 6.3V, 20% Sanyo D1 1 CMMSH1-40-NST SOD123 Vr = 40V, Io = 1A, Vf = 0.55V Central Semiconductor L1 1 IHLP4040DZER5R6M01 IHLP4040 5.6µH, 0.018 Ohms, 16A Vishay R1, R4 2 CRCW06031002F 0603 10kΩ, 1% Vishay R2 1 CRCW06034992F 0603 49.9kΩ, 1% Vishay R3 1 CRCW06033092F 0603 30.9kΩ, 1% Vishay Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Links: LM20323 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM20323MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20323MH LM20323MHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20323MH LM20323MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20323MH (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20323MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM20323MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20323MHE/NOPB HTSSOP PWP LM20323MHX/NOPB HTSSOP PWP 20 250 203.0 190.0 41.0 20 2500 349.0 337.0 45.0 Pack Materials-Page 2 MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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